usb: xhci: tegra: add uses_externl_pmic in board_data
[linux-3.10.git] / drivers / usb / host / xhci-tegra.c
1 /*
2  * xhci-tegra.c - Nvidia xHCI host controller driver
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/clk.h>
24 #include <linux/ioport.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irq.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/uaccess.h>
30
31 #include <mach/powergate.h>
32 #include <mach/clk.h>
33 #include <mach/tegra_usb_pad_ctrl.h>
34 #include <mach/tegra_usb_pmc.h>
35 #include <mach/pm_domains.h>
36 #include <mach/mc.h>
37 #include <mach/xusb.h>
38
39 #include "../../../arch/arm/mach-tegra/iomap.h" /* HACK -- remove */
40 #include "xhci-tegra.h"
41 #include "xhci.h"
42
43 /* macros */
44 #define PAGE_SELECT_MASK                        0xFFFFFE00
45 #define PAGE_SELECT_SHIFT                       9
46 #define PAGE_OFFSET_MASK                        0x000001FF
47 #define CSB_PAGE_SELECT(_addr)                                          \
48         ({                                                              \
49                 typecheck(u32, _addr);                                  \
50                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
51         })
52 #define CSB_PAGE_OFFSET(_addr)                                          \
53         ({                                                              \
54                 typecheck(u32, _addr);                                  \
55                 (_addr & PAGE_OFFSET_MASK);                             \
56         })
57
58 /* PMC register definition */
59 #define PMC_PORT_UTMIP_P0               0
60 #define PMC_PORT_UTMIP_P1               1
61 #define PMC_PORT_UTMIP_P2               2
62 #define PMC_PORT_UHSIC_P0               3
63 #define PMC_PORT_NUM                    4
64
65 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
66 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
67 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
68
69 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
70
71 /* private data types */
72 /* command requests from the firmware */
73 enum MBOX_CMD_TYPE {
74         MBOX_CMD_MSG_ENABLED = 1,
75         MBOX_CMD_INC_FALC_CLOCK,
76         MBOX_CMD_DEC_FALC_CLOCK,
77         MBOX_CMD_INC_SSPI_CLOCK,
78         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
79         MBOX_CMD_SET_BW,
80         MBOX_CMD_SET_SS_PWR_GATING,
81         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
82         MBOX_CMD_SAVE_DFE_CTLE_CTX,
83
84         /* needs to be the last cmd */
85         MBOX_CMD_MAX,
86
87         /* resp msg to ack above commands */
88         MBOX_CMD_ACK = 128,
89         MBOX_CMD_NACK
90 };
91
92 /* Usb3 Firmware Cfg Table */
93 struct cfgtbl {
94         u32 boot_loadaddr_in_imem;
95         u32 boot_codedfi_offset;
96         u32 boot_codetag;
97         u32 boot_codesize;
98
99         /* Physical memory reserved by Bootloader/BIOS */
100         u32 phys_memaddr;
101         u16 reqphys_memsize;
102         u16 alloc_phys_memsize;
103
104         /* .rodata section */
105         u32 rodata_img_offset;
106         u32 rodata_section_start;
107         u32 rodata_section_end;
108         u32 main_fnaddr;
109
110         u32 fwimg_cksum;
111         u32 fwimg_created_time;
112
113         /* Fields that get filled by linker during linking phase
114          * or initialized in the FW code.
115          */
116         u32 imem_resident_start;
117         u32 imem_resident_end;
118         u32 idirect_start;
119         u32 idirect_end;
120         u32 l2_imem_start;
121         u32 l2_imem_end;
122         u32 version_id;
123         u8 init_ddirect;
124         u8 reserved[3];
125         u32 phys_addr_log_buffer;
126         u32 total_log_entries;
127         u32 dequeue_ptr;
128
129         /*      Below two dummy variables are used to replace
130          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
131          *      retain the size of struct _CFG_TBL used by other AP/Module.
132          */
133         u32 dummy_var1;
134         u32 dummy_var2;
135
136         /* fwimg_len */
137         u32 fwimg_len;
138         u8 magic[8];
139         u32 SS_low_power_entry_timeout;
140         u8 padding[140]; /* padding bytes to makeup 256-bytes cfgtbl */
141 };
142
143 struct xusb_save_regs {
144         u32 msi_bar_sz;
145         u32 msi_axi_barst;
146         u32 msi_fpci_barst;
147         u32 msi_vec0;
148         u32 msi_en_vec0;
149         u32 fpci_error_masks;
150         u32 intr_mask;
151         u32 ipfs_intr_enable;
152         u32 ufpci_config;
153         u32 clkgate_hysteresis;
154         u32 xusb_host_mccif_fifo_cntrl;
155
156         /* PG does not mention below */
157         u32 hs_pls;
158         u32 fs_pls;
159         u32 hs_fs_speed;
160         u32 hs_fs_pp;
161         u32 cfg_aru;
162         u32 cfg_order;
163         u32 cfg_fladj;
164         u32 cfg_sid;
165         /* DFE and CTLE */
166         u32 tap1_val[2];
167         u32 amp_val[2];
168         u32 ctle_z_val[2];
169         u32 ctle_g_val[2];
170 };
171
172 struct tegra_xhci_firmware {
173         void *data; /* kernel virtual address */
174         size_t size; /* firmware size */
175         dma_addr_t dma; /* dma address for controller */
176 };
177
178 /* structure to hold the offsets of padctl registers */
179 struct tegra_xusb_padctl_regs {
180         u16 boot_media_0;
181         u16 usb2_pad_mux_0;
182         u16 usb2_port_cap_0;
183         u16 snps_oc_map_0;
184         u16 usb2_oc_map_0;
185         u16 ss_port_map_0;
186         u16 oc_det_0;
187         u16 elpg_program_0;
188         u16 usb2_bchrg_otgpad0_ctl0_0;
189         u16 usb2_bchrg_otgpad0_ctl1_0;
190         u16 usb2_bchrg_otgpad1_ctl0_0;
191         u16 usb2_bchrg_otgpad1_ctl1_0;
192         u16 usb2_bchrg_otgpad2_ctl0_0;
193         u16 usb2_bchrg_otgpad2_ctl1_0;
194         u16 usb2_bchrg_bias_pad_0;
195         u16 usb2_bchrg_tdcd_dbnc_timer_0;
196         u16 iophy_pll_p0_ctl1_0;
197         u16 iophy_pll_p0_ctl2_0;
198         u16 iophy_pll_p0_ctl3_0;
199         u16 iophy_pll_p0_ctl4_0;
200         u16 iophy_usb3_pad0_ctl1_0;
201         u16 iophy_usb3_pad1_ctl1_0;
202         u16 iophy_usb3_pad0_ctl2_0;
203         u16 iophy_usb3_pad1_ctl2_0;
204         u16 iophy_usb3_pad0_ctl3_0;
205         u16 iophy_usb3_pad1_ctl3_0;
206         u16 iophy_usb3_pad0_ctl4_0;
207         u16 iophy_usb3_pad1_ctl4_0;
208         u16 iophy_misc_pad_p0_ctl1_0;
209         u16 iophy_misc_pad_p1_ctl1_0;
210         u16 iophy_misc_pad_p0_ctl2_0;
211         u16 iophy_misc_pad_p1_ctl2_0;
212         u16 iophy_misc_pad_p0_ctl3_0;
213         u16 iophy_misc_pad_p1_ctl3_0;
214         u16 iophy_misc_pad_p0_ctl4_0;
215         u16 iophy_misc_pad_p1_ctl4_0;
216         u16 iophy_misc_pad_p0_ctl5_0;
217         u16 iophy_misc_pad_p1_ctl5_0;
218         u16 iophy_misc_pad_p0_ctl6_0;
219         u16 iophy_misc_pad_p1_ctl6_0;
220         u16 usb2_otg_pad0_ctl0_0;
221         u16 usb2_otg_pad1_ctl0_0;
222         u16 usb2_otg_pad2_ctl0_0;
223         u16 usb2_otg_pad0_ctl1_0;
224         u16 usb2_otg_pad1_ctl1_0;
225         u16 usb2_otg_pad2_ctl1_0;
226         u16 usb2_bias_pad_ctl0_0;
227         u16 usb2_bias_pad_ctl1_0;
228         u16 usb2_hsic_pad0_ctl0_0;
229         u16 usb2_hsic_pad1_ctl0_0;
230         u16 usb2_hsic_pad0_ctl1_0;
231         u16 usb2_hsic_pad1_ctl1_0;
232         u16 usb2_hsic_pad0_ctl2_0;
233         u16 usb2_hsic_pad1_ctl2_0;
234         u16 ulpi_link_trim_ctl0;
235         u16 ulpi_null_clk_trim_ctl0;
236         u16 hsic_strb_trim_ctl0;
237         u16 wake_ctl0;
238         u16 pm_spare0;
239         u16 iophy_misc_pad_p2_ctl1_0;
240         u16 iophy_misc_pad_p3_ctl1_0;
241         u16 iophy_misc_pad_p4_ctl1_0;
242         u16 iophy_misc_pad_p2_ctl2_0;
243         u16 iophy_misc_pad_p3_ctl2_0;
244         u16 iophy_misc_pad_p4_ctl2_0;
245         u16 iophy_misc_pad_p2_ctl3_0;
246         u16 iophy_misc_pad_p3_ctl3_0;
247         u16 iophy_misc_pad_p4_ctl3_0;
248         u16 iophy_misc_pad_p2_ctl4_0;
249         u16 iophy_misc_pad_p3_ctl4_0;
250         u16 iophy_misc_pad_p4_ctl4_0;
251         u16 iophy_misc_pad_p2_ctl5_0;
252         u16 iophy_misc_pad_p3_ctl5_0;
253         u16 iophy_misc_pad_p4_ctl5_0;
254         u16 iophy_misc_pad_p2_ctl6_0;
255         u16 iophy_misc_pad_p3_ctl6_0;
256         u16 iophy_misc_pad_p4_ctl6_0;
257         u16 usb3_pad_mux_0;
258         u16 iophy_pll_s0_ctl1_0;
259         u16 iophy_pll_s0_ctl2_0;
260         u16 iophy_pll_s0_ctl3_0;
261         u16 iophy_pll_s0_ctl4_0;
262         u16 iophy_misc_pad_s0_ctl1_0;
263         u16 iophy_misc_pad_s0_ctl2_0;
264         u16 iophy_misc_pad_s0_ctl3_0;
265         u16 iophy_misc_pad_s0_ctl4_0;
266         u16 iophy_misc_pad_s0_ctl5_0;
267         u16 iophy_misc_pad_s0_ctl6_0;
268 };
269
270 struct tegra_xhci_hcd {
271         struct platform_device *pdev;
272         struct xhci_hcd *xhci;
273         u16 device_id;
274
275         spinlock_t lock;
276         struct mutex sync_lock;
277
278         int smi_irq;
279         int padctl_irq;
280         int usb3_irq;
281
282         bool ss_wake_event;
283         bool ss_pwr_gated;
284         bool host_pwr_gated;
285         bool hs_wake_event;
286         bool host_resume_req;
287         bool lp0_exit;
288         bool dfe_ctle_ctx_saved;
289         unsigned long last_jiffies;
290         unsigned long host_phy_base;
291         void __iomem *host_phy_virt_base;
292
293         void __iomem *padctl_base;
294         void __iomem *fpci_base;
295         void __iomem *ipfs_base;
296
297         struct tegra_xusb_platform_data *pdata;
298         struct tegra_xusb_board_data *bdata;
299         struct tegra_xusb_padctl_regs *padregs;
300
301         /* mailbox variables */
302         struct mutex mbox_lock;
303         u32 mbox_owner;
304         u32 cmd_type;
305         u32 cmd_data;
306
307         struct regulator *xusb_vbus_reg;
308         struct regulator *xusb_avddio_usb3_reg;
309         struct regulator *xusb_hvdd_usb3_reg;
310         struct regulator *xusb_avdd_usb3_pll_reg;
311
312         struct work_struct mbox_work;
313         struct work_struct ss_elpg_exit_work;
314         struct work_struct host_elpg_exit_work;
315
316         struct clk *host_clk;
317         struct clk *ss_clk;
318
319         /* XUSB Falcon SuperSpeed Clock */
320         struct clk *falc_clk;
321
322         /* EMC Clock */
323         struct clk *emc_clk;
324         /* XUSB SS PI Clock */
325         struct clk *ss_src_clk;
326         /* PLLE Clock */
327         struct clk *plle_clk;
328         struct clk *pll_u_480M;
329         struct clk *clk_m;
330         /* refPLLE clk */
331         struct clk *pll_re_vco_clk;
332         /*
333          * XUSB/IPFS specific registers these need to be saved/restored in
334          * addition to spec defined registers
335          */
336         struct xusb_save_regs sregs;
337         bool usb2_rh_suspend;
338         bool usb3_rh_suspend;
339         bool hc_in_elpg;
340
341         unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
342         /* firmware loading related */
343         struct tegra_xhci_firmware firmware;
344 };
345
346 static struct tegra_usb_pmc_data pmc_data;
347
348 /* functions */
349 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
350 {
351         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
352 }
353
354 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
355 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
356 {
357         WARN_ON(tegra->sync_lock.owner != current);
358 }
359 #else
360 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
361 #endif
362
363 static bool is_any_hs_connected(struct xhci_hcd *xhci)
364 {
365         __le32 __iomem *addr;
366         int i;
367         int ports;
368         u32 portsc;
369
370         ports = HCS_MAX_PORTS(xhci->hcs_params1);
371         addr = &xhci->op_regs->port_status_base;
372         for (i = 0; i < ports; i++) {
373                 portsc = xhci_readl(xhci, addr);
374                 if ((portsc & PORT_CONNECT) && DEV_HIGHSPEED(portsc))
375                         return true;
376                 addr += NUM_PORT_REGS;
377         }
378         return false;
379 }
380
381 static void debug_print_portsc(struct xhci_hcd *xhci)
382 {
383         __le32 __iomem *addr;
384         int i;
385         int ports;
386
387         ports = HCS_MAX_PORTS(xhci->hcs_params1);
388         addr = &xhci->op_regs->port_status_base;
389         for (i = 0; i < ports; i++) {
390                 xhci_dbg(xhci, "%p port %d status reg = 0x%x\n",
391                                 addr, i, (unsigned int) xhci_readl(xhci, addr));
392                 addr += NUM_PORT_REGS;
393         }
394 }
395
396 static void update_speed(struct tegra_xhci_hcd *tegra, u8 port)
397 {
398         struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
399         u32 portsc;
400
401         portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port +
402                                                 BAR0_XHCI_OP_PORTSC_UTMIP_0));
403         if (DEV_FULLSPEED(portsc))
404                 pmc_data.port_speed = USB_PMC_PORT_SPEED_FULL;
405         else if (DEV_HIGHSPEED(portsc))
406                 pmc_data.port_speed = USB_PMC_PORT_SPEED_HIGH;
407         else if (DEV_LOWSPEED(portsc))
408                 pmc_data.port_speed = USB_PMC_PORT_SPEED_LOW;
409         else if (DEV_SUPERSPEED(portsc))
410                 pmc_data.port_speed = USB_PMC_PORT_SPEED_SUPER;
411         else
412                 pmc_data.port_speed = USB_PMC_PORT_SPEED_UNKNOWN;
413 }
414
415 static void setup_wake_detect(bool setup_wake)
416 {
417         if (setup_wake)
418                 pmc_data.pmc_ops->setup_pmc_wake_detect(&pmc_data);
419         else
420                 pmc_data.pmc_ops->disable_pmc_bus_ctrl(&pmc_data, 0);
421 }
422
423 static void pmc_init(struct tegra_xhci_hcd *tegra, bool setup_wake)
424 {
425         u32 portmap = tegra->bdata->portmap;
426
427         pmc_data.controller_type = TEGRA_USB_3_0;
428         if (portmap & TEGRA_XUSB_USB2_P0) {
429                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 0) & 0xf;
430                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
431                 update_speed(tegra, pmc_data.instance);
432                 tegra_usb_pmc_init(&pmc_data);
433                 setup_wake_detect(setup_wake);
434         }
435         if (portmap & TEGRA_XUSB_USB2_P1) {
436                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 4) & 0xf;
437                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
438                 update_speed(tegra, pmc_data.instance);
439                 tegra_usb_pmc_init(&pmc_data);
440                 setup_wake_detect(setup_wake);
441         }
442         if (portmap & TEGRA_XUSB_USB2_P2) {
443                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 8) & 0xf;
444                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
445                 update_speed(tegra, pmc_data.instance);
446                 tegra_usb_pmc_init(&pmc_data);
447                 setup_wake_detect(setup_wake);
448         }
449         if (portmap & TEGRA_XUSB_HSIC_P0) {
450                 pmc_data.instance = PMC_PORT_UHSIC_P0;
451                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_HSIC;
452                 update_speed(tegra, pmc_data.instance);
453                 tegra_usb_pmc_init(&pmc_data);
454                 setup_wake_detect(setup_wake);
455         }
456 }
457
458 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
459 {
460         void __iomem *fpci_base = tegra->fpci_base;
461         struct platform_device *pdev = tegra->pdev;
462         u32 input_addr;
463         u32 data;
464         u32 csb_page_select;
465
466         /* to select the appropriate CSB page to write to */
467         csb_page_select = CSB_PAGE_SELECT(addr);
468
469         dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
470                         csb_page_select);
471
472         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
473
474         /* selects the appropriate offset in the page to read from */
475         input_addr = CSB_PAGE_OFFSET(addr);
476         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
477
478         dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
479                         input_addr, data);
480         return data;
481 }
482
483 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
484 {
485         void __iomem *fpci_base = tegra->fpci_base;
486         struct platform_device *pdev = tegra->pdev;
487         u32 input_addr;
488         u32 csb_page_select;
489
490         /* to select the appropriate CSB page to write to */
491         csb_page_select = CSB_PAGE_SELECT(addr);
492
493         dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
494                         csb_page_select);
495
496         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
497
498         /* selects the appropriate offset in the page to write to */
499         input_addr = CSB_PAGE_OFFSET(addr);
500         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
501
502         dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
503                         input_addr, data);
504 }
505
506 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
507 {
508         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
509         struct xhci_hcd *xhci = tegra->xhci;
510         u32 reg;
511
512         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
513         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
514         xhci_info(xhci, " PAD MUX = %x\n", reg);
515         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
516         xhci_info(xhci, " PORT CAP = %x\n", reg);
517         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
518         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
519         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
520         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
521         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
522         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
523         reg = readl(tegra->padctl_base + padregs->oc_det_0);
524         xhci_info(xhci, " OC DET 0= %x\n", reg);
525         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad0_ctl2_0);
526         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
527         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad1_ctl2_0);
528         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
529         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl0_0);
530         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
531         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl0_0);
532         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
533         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl1_0);
534         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
535         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl1_0);
536         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
537         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
538         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
539         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad0_ctl0_0);
540         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
541         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad1_ctl0_0);
542         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
543         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
544 }
545
546 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
547 {
548         u32 reg;
549
550         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
551         reg |= IPFS_EN_FPCI;
552         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
553         udelay(10);
554
555         /* Program Bar0 Space */
556         reg = readl(tegra->fpci_base + XUSB_CFG_4);
557         reg |= tegra->host_phy_base;
558         writel(reg, tegra->fpci_base + XUSB_CFG_4);
559         usleep_range(100, 200);
560
561         /* Enable Bus Master */
562         reg = readl(tegra->fpci_base + XUSB_CFG_1);
563         reg |= 0x7;
564         writel(reg, tegra->fpci_base + XUSB_CFG_1);
565
566         /* Set intr mask to enable intr assertion */
567         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
568         reg |= IPFS_IP_INT_MASK;
569         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
570
571         /* Set hysteris to 0x80 */
572         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
573 }
574
575 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
576                 struct platform_device *pdev)
577 {
578         int err = 0;
579
580         tegra->xusb_hvdd_usb3_reg =
581                         devm_regulator_get(&pdev->dev, "hvdd_usb");
582         if (IS_ERR(tegra->xusb_hvdd_usb3_reg)) {
583                 dev_err(&pdev->dev, "hvdd_usb: regulator not found: %ld."
584                         , PTR_ERR(tegra->xusb_hvdd_usb3_reg));
585                 err = PTR_ERR(tegra->xusb_hvdd_usb3_reg);
586                 goto err_null_regulator;
587         } else {
588                 err = regulator_enable(tegra->xusb_hvdd_usb3_reg);
589                 if (err < 0) {
590                         dev_err(&pdev->dev,
591                                 "hvdd_usb3: regulator enable failed:%d\n", err);
592                         goto err_null_regulator;
593                 }
594         }
595
596         tegra->xusb_vbus_reg = devm_regulator_get(&pdev->dev, "usb_vbus");
597         if (IS_ERR(tegra->xusb_vbus_reg)) {
598                 dev_err(&pdev->dev, "vbus regulator not found: %ld."
599                         , PTR_ERR(tegra->xusb_vbus_reg));
600                 err = PTR_ERR(tegra->xusb_vbus_reg);
601                 goto err_put_hvdd_usb3;
602         } else {
603                 err = regulator_enable(tegra->xusb_vbus_reg);
604                 if (err < 0) {
605                         dev_err(&pdev->dev,
606                                 "vbus: regulator enable failed:%d\n", err);
607                         goto err_put_hvdd_usb3;
608                 }
609         }
610
611         tegra->xusb_avdd_usb3_pll_reg =
612                 devm_regulator_get(&pdev->dev, "avdd_usb_pll");
613         if (IS_ERR(tegra->xusb_avdd_usb3_pll_reg)) {
614                 dev_err(&pdev->dev, "avdd_usb3_pll regulator not found: %ld."
615                         , PTR_ERR(tegra->xusb_avdd_usb3_pll_reg));
616                 err = PTR_ERR(tegra->xusb_avdd_usb3_pll_reg);
617                 goto err_put_vbus;
618         } else {
619                 err = regulator_enable(tegra->xusb_avdd_usb3_pll_reg);
620                 if (err < 0) {
621                         dev_err(&pdev->dev,
622                         "avdd_usb3_pll: regulator enable failed:%d\n", err);
623                         goto err_put_vbus;
624                 }
625         }
626
627         tegra->xusb_avddio_usb3_reg =
628                         devm_regulator_get(&pdev->dev, "avddio_usb");
629         if (IS_ERR(tegra->xusb_avddio_usb3_reg)) {
630                 dev_err(&pdev->dev, "avddio_usb3: regulator not found: %ld."
631                         , PTR_ERR(tegra->xusb_avddio_usb3_reg));
632                 err = PTR_ERR(tegra->xusb_avddio_usb3_reg);
633                 goto err_put_usb3_pll;
634         } else {
635                 err = regulator_enable(tegra->xusb_avddio_usb3_reg);
636                 if (err < 0) {
637                         dev_err(&pdev->dev,
638                         "avddio_usb3: regulator enable failed:%d\n", err);
639                         goto err_put_usb3_pll;
640                 }
641         }
642
643         return err;
644
645 err_put_usb3_pll:
646         regulator_disable(tegra->xusb_avdd_usb3_pll_reg);
647 err_put_vbus:
648         regulator_disable(tegra->xusb_vbus_reg);
649 err_put_hvdd_usb3:
650         regulator_disable(tegra->xusb_hvdd_usb3_reg);
651 err_null_regulator:
652         tegra->xusb_vbus_reg = NULL;
653         tegra->xusb_avddio_usb3_reg = NULL;
654         tegra->xusb_hvdd_usb3_reg = NULL;
655         tegra->xusb_avdd_usb3_pll_reg = NULL;
656         return err;
657 }
658
659 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
660 {
661         regulator_disable(tegra->xusb_avddio_usb3_reg);
662         regulator_disable(tegra->xusb_avdd_usb3_pll_reg);
663         regulator_disable(tegra->xusb_vbus_reg);
664         regulator_disable(tegra->xusb_hvdd_usb3_reg);
665
666         tegra->xusb_avddio_usb3_reg = NULL;
667         tegra->xusb_avdd_usb3_pll_reg = NULL;
668         tegra->xusb_vbus_reg = NULL;
669         tegra->xusb_hvdd_usb3_reg = NULL;
670 }
671
672 /*
673  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
674  * are under hardware control
675  */
676 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
677 {
678         struct platform_device *pdev = tegra->pdev;
679         int err = 0;
680
681         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
682         if (IS_ERR(tegra->plle_clk)) {
683                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
684                 err = PTR_ERR(tegra->plle_clk);
685                 return err;
686         }
687         err = clk_enable(tegra->plle_clk);
688         if (err) {
689                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
690                         __func__);
691                 return err;
692         }
693
694         return err;
695 }
696
697 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
698 {
699         clk_disable(tegra->plle_clk);
700         tegra->plle_clk = NULL;
701 }
702
703 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
704 {
705         struct platform_device *pdev = tegra->pdev;
706         int err = 0;
707
708         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
709         if (IS_ERR(tegra->emc_clk)) {
710                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
711                 return PTR_ERR(tegra->emc_clk);
712         }
713
714         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
715                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
716                 if (IS_ERR(tegra->pll_re_vco_clk)) {
717                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
718                         err = PTR_ERR(tegra->pll_re_vco_clk);
719                         goto get_pll_re_vco_clk_failed;
720                 }
721         }
722
723         /* get the clock handle of 120MHz clock source */
724         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
725         if (IS_ERR(tegra->pll_u_480M)) {
726                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
727                 err = PTR_ERR(tegra->pll_u_480M);
728                 goto get_pll_u_480M_failed;
729         }
730
731         /* get the clock handle of 12MHz clock source */
732         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
733         if (IS_ERR(tegra->clk_m)) {
734                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
735                 err = PTR_ERR(tegra->clk_m);
736                 goto clk_get_clk_m_failed;
737         }
738
739         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
740         if (IS_ERR(tegra->ss_src_clk)) {
741                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
742                 err = PTR_ERR(tegra->ss_src_clk);
743                 tegra->ss_src_clk = NULL;
744                 goto get_ss_src_clk_failed;
745         }
746
747         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
748         if (IS_ERR(tegra->host_clk)) {
749                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
750                 err = PTR_ERR(tegra->host_clk);
751                 tegra->host_clk = NULL;
752                 goto get_host_clk_failed;
753         }
754
755         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
756         if (IS_ERR(tegra->ss_clk)) {
757                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
758                 err = PTR_ERR(tegra->ss_clk);
759                 tegra->ss_clk = NULL;
760                 goto get_ss_clk_failed;
761         }
762
763         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
764                 err = clk_enable(tegra->pll_re_vco_clk);
765                 if (err) {
766                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
767                         goto enable_pll_re_vco_clk_failed;
768                 }
769         }
770         /* enable ss clock */
771         err = clk_enable(tegra->host_clk);
772         if (err) {
773                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
774                 goto enable_host_clk_failed;
775         }
776
777         err = clk_enable(tegra->ss_clk);
778         if (err) {
779                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
780                 goto eanble_ss_clk_failed;
781         }
782
783         err = clk_enable(tegra->emc_clk);
784         if (err) {
785                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
786                 goto eanble_emc_clk_failed;
787         }
788
789         return 0;
790
791 eanble_emc_clk_failed:
792         clk_disable(tegra->ss_clk);
793
794 eanble_ss_clk_failed:
795         clk_disable(tegra->host_clk);
796
797 enable_host_clk_failed:
798         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
799                 clk_disable(tegra->pll_re_vco_clk);
800
801 enable_pll_re_vco_clk_failed:
802         tegra->ss_clk = NULL;
803
804 get_ss_clk_failed:
805         tegra->host_clk = NULL;
806
807 get_host_clk_failed:
808         tegra->ss_src_clk = NULL;
809
810 get_ss_src_clk_failed:
811         tegra->clk_m = NULL;
812
813 clk_get_clk_m_failed:
814         tegra->pll_u_480M = NULL;
815
816 get_pll_u_480M_failed:
817         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
818                 tegra->pll_re_vco_clk = NULL;
819
820 get_pll_re_vco_clk_failed:
821         tegra->emc_clk = NULL;
822
823         return err;
824 }
825
826 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
827 {
828         clk_disable(tegra->ss_clk);
829         clk_disable(tegra->host_clk);
830         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
831                 clk_disable(tegra->pll_re_vco_clk);
832         tegra->ss_clk = NULL;
833         tegra->host_clk = NULL;
834         tegra->ss_src_clk = NULL;
835         tegra->clk_m = NULL;
836         tegra->pll_u_480M = NULL;
837         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
838                 tegra->pll_re_vco_clk = NULL;
839 }
840
841 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
842         bool enable)
843 {
844         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
845         u32 reg;
846
847         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
848                 reg = readl(tegra->padctl_base +
849                         padregs->iophy_misc_pad_p0_ctl3_0);
850                 if (enable) {
851                         reg &= ~RX_IDLE_MODE;
852                         reg |= RX_IDLE_MODE_OVRD;
853                 } else {
854                         reg |= RX_IDLE_MODE;
855                         reg &= ~RX_IDLE_MODE_OVRD;
856                 }
857                 writel(reg, tegra->padctl_base +
858                         padregs->iophy_misc_pad_p0_ctl3_0);
859         }
860
861         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
862                 reg = readl(tegra->padctl_base +
863                         padregs->iophy_misc_pad_p1_ctl3_0);
864                 if (enable) {
865                         reg &= ~RX_IDLE_MODE;
866                         reg |= RX_IDLE_MODE_OVRD;
867                 } else {
868                         reg |= RX_IDLE_MODE;
869                         reg &= ~RX_IDLE_MODE_OVRD;
870                 }
871                 writel(reg, tegra->padctl_base +
872                         padregs->iophy_misc_pad_p1_ctl3_0);
873
874                 /* SATA lane also if USB3_SS port1 mapped to it */
875                 if (XUSB_DEVICE_ID_T124 == tegra->device_id &&
876                                 tegra->bdata->lane_owner & BIT(0)) {
877                         reg = readl(tegra->padctl_base +
878                                 padregs->iophy_misc_pad_s0_ctl3_0);
879                         if (enable) {
880                                 reg &= ~RX_IDLE_MODE;
881                                 reg |= RX_IDLE_MODE_OVRD;
882                         } else {
883                                 reg |= RX_IDLE_MODE;
884                                 reg &= ~RX_IDLE_MODE_OVRD;
885                         }
886                         writel(reg, tegra->padctl_base +
887                                 padregs->iophy_misc_pad_s0_ctl3_0);
888                 }
889         }
890 }
891
892 /* Enable ss clk, host clk, falcon clk,
893  * fs clk, dev clk, plle and refplle
894  */
895
896 static int
897 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
898                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
899 {
900         int ret = 0;
901         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
902         int fw_req_rate = rate, cur_rate;
903
904         /* Do not handle clock change as needed for HS disconnect issue */
905         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
906                 *sw_resp = fw_req_rate | (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
907                 return ret;
908         }
909
910         /* frequency request from firmware is in KHz.
911          * Convert it to MHz
912          */
913
914         /* get current rate of clock */
915         cur_rate = clk_get_rate(clk_handle);
916         cur_rate /= 1000;
917
918         if (fw_req_rate == cur_rate) {
919                 cmd_ack = MBOX_CMD_ACK;
920                 *sw_resp = fw_req_rate;
921         } else {
922
923                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
924                         /* Change SS clock source to CLK_M at 12MHz */
925                         clk_set_parent(clk_handle, tegra->clk_m);
926                         clk_set_rate(clk_handle, fw_req_rate * 1000);
927
928                         /* save leakage power when SS freq is being decreased */
929                         tegra_xhci_rx_idle_mode_override(tegra, true);
930                 } else if (clk_handle == tegra->ss_src_clk &&
931                                 fw_req_rate == 120000) {
932                         /* Change SS clock source to HSIC_480 at 120MHz */
933                         clk_set_rate(clk_handle,  3000 * 1000);
934                         clk_set_parent(clk_handle, tegra->pll_u_480M);
935
936                         /* clear ovrd bits when SS freq is being increased */
937                         tegra_xhci_rx_idle_mode_override(tegra, false);
938                 }
939
940                 *sw_resp = clk_get_rate(clk_handle);
941                 *sw_resp /= 1000;
942
943                 if (*sw_resp != fw_req_rate) {
944                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
945                                 cur_rate, fw_req_rate);
946                         cmd_ack = MBOX_CMD_NACK;
947                 }
948         }
949         *sw_resp |= (cmd_ack << MBOX_CMD_SHIFT);
950         return ret;
951 }
952
953 static void tegra_xhci_save_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
954         u8 port)
955 {
956         struct xhci_hcd *xhci = tegra->xhci;
957         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
958         u32 offset;
959         u32 reg;
960
961         xhci_info(xhci, "saving dfe_cntl and ctle context for port %d\n", port);
962
963         if (port == 3 /* SATA pad */)
964                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
965         else
966                 offset = port ? padregs->iophy_misc_pad_p1_ctl6_0 :
967                                 padregs->iophy_misc_pad_p0_ctl6_0;
968
969         /* save tap1_val[] for the port for dfe_cntl */
970         reg = readl(tegra->padctl_base + offset);
971         reg &= ~(0xff << 16);
972         reg |= (0x32 << 16);
973         writel(reg, tegra->padctl_base + offset);
974
975         reg = readl(tegra->padctl_base + offset);
976         tegra->sregs.tap1_val[port] = ((reg & (0x1f << 24)) >> 24);
977
978         /* save amp_val[] for the port for dfe_cntl */
979         reg = readl(tegra->padctl_base + offset);
980         reg &= ~(0xff << 16);
981         reg |= (0x33 << 16);
982         writel(reg, tegra->padctl_base + offset);
983
984         reg = readl(tegra->padctl_base + offset);
985         tegra->sregs.amp_val[port] = ((reg & (0x7f << 24)) >> 24);
986
987         /* save ctle_z_val[] for the port for ctle */
988         reg = readl(tegra->padctl_base + offset);
989         reg &= ~(0xff << 16);
990         reg |= (0x20 << 16);
991         writel(reg, tegra->padctl_base + offset);
992
993         reg = readl(tegra->padctl_base + offset);
994         tegra->sregs.ctle_z_val[port] = ((reg & (0x3f << 24)) >> 24);
995
996         /* save ctle_g_val[] for the port for ctle */
997         reg = readl(tegra->padctl_base + offset);
998         reg &= ~(0xff << 16);
999         reg |= (0x21 << 16);
1000         writel(reg, tegra->padctl_base + offset);
1001
1002         reg = readl(tegra->padctl_base + offset);
1003         tegra->sregs.ctle_g_val[port] = ((reg & (0x3f << 24)) >> 24);
1004         tegra->dfe_ctle_ctx_saved = true;
1005 }
1006
1007 static void tegra_xhci_restore_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
1008         u8 port)
1009 {
1010         struct xhci_hcd *xhci = tegra->xhci;
1011         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1012         u32 ctl4_offset, ctl2_offset;
1013         u32 reg;
1014
1015         /* don't restore if not saved */
1016         if (tegra->dfe_ctle_ctx_saved == false)
1017                 return;
1018
1019         if (port == 3 /* SATA pad */) {
1020                 ctl4_offset = padregs->iophy_misc_pad_s0_ctl4_0;
1021                 ctl2_offset = padregs->iophy_misc_pad_s0_ctl2_0;
1022         } else {
1023                 ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1024                                 padregs->iophy_usb3_pad0_ctl4_0;
1025                 ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1026                                 padregs->iophy_usb3_pad0_ctl2_0;
1027         }
1028
1029         xhci_info(xhci, "restoring dfe_cntl/ctle context of port %d\n", port);
1030
1031         /* restore dfe_cntl for the port */
1032         reg = readl(tegra->padctl_base + ctl4_offset);
1033         reg &= ~((0x7f << 16) | (0x1f << 24));
1034         reg |= ((tegra->sregs.amp_val[port] << 16) |
1035                 (tegra->sregs.tap1_val[port] << 24));
1036         writel(reg, tegra->padctl_base + ctl4_offset);
1037
1038         /* restore ctle for the port */
1039         reg = readl(tegra->padctl_base + ctl2_offset);
1040         reg &= ~((0x3f << 8) | (0x3f << 16));
1041         reg |= ((tegra->sregs.ctle_g_val[port] << 8) |
1042                 (tegra->sregs.ctle_z_val[port] << 16));
1043         writel(reg, tegra->padctl_base + ctl2_offset);
1044 }
1045
1046 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
1047         u8 port)
1048 {
1049         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1050         u32 reg;
1051
1052         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1053         reg &= ~USB2_ULPI_PAD;
1054         reg |= USB2_ULPI_PAD_OWNER_XUSB;
1055         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1056
1057         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1058         reg &= ~USB2_ULPI_PORT_CAP;
1059         reg |= (tegra->bdata->ulpicap << 24);
1060         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1061         /* FIXME: Program below when more details available
1062          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
1063          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
1064          */
1065 }
1066
1067 static void tegra_xhci_program_hsic_pad(struct tegra_xhci_hcd *tegra,
1068         u8 port)
1069 {
1070         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1071         u32 ctl0_offset;
1072         u32 reg;
1073
1074         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1075         reg &= ~(port ? USB2_HSIC_PAD_PORT1 : USB2_HSIC_PAD_PORT0);
1076         reg |= port ? USB2_HSIC_PAD_P1_OWNER_XUSB :
1077                         USB2_HSIC_PAD_P0_OWNER_XUSB;
1078         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1079
1080         ctl0_offset = port ? padregs->usb2_hsic_pad1_ctl0_0 :
1081                         padregs->usb2_hsic_pad0_ctl0_0;
1082
1083         reg = readl(tegra->padctl_base + ctl0_offset);
1084         reg &= ~(HSIC_TX_SLEWP | HSIC_TX_SLEWN);
1085         writel(reg, tegra->padctl_base + ctl0_offset);
1086
1087         /* FIXME Program below when more details available
1088          * XUSB_PADCTL_HSIC_PAD0_CTL_0_0
1089          * XUSB_PADCTL_HSIC_PAD0_CTL_1_0
1090          * XUSB_PADCTL_HSIC_PAD0_CTL_2_0
1091          * XUSB_PADCTL_HSIC_PAD1_CTL_0_0
1092          * XUSB_PADCTL_HSIC_PAD1_CTL_1_0
1093          * XUSB_PADCTL_HSIC_PAD1_CTL_2_0
1094          * XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0
1095          */
1096 }
1097
1098 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
1099         u8 port)
1100 {
1101         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1102         u32 reg;
1103         u32 ctl0_offset, ctl1_offset;
1104
1105         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1106         reg &= ~USB2_OTG_PAD_PORT_MASK(port);
1107         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
1108         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1109
1110         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1111         reg &= ~USB2_PORT_CAP_MASK(port);
1112         reg |= USB2_PORT_CAP_HOST(port);
1113         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1114
1115         /*
1116          * Modify only the bits which belongs to the port
1117          * and enable respective VBUS_PAD for the port
1118          */
1119         if (tegra->bdata->uses_external_pmic == false) {
1120                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1121                 reg &= ~(port == 2 ? OC_DET_VBUS_ENABLE2_OC_MAP :
1122                         port ? OC_DET_VBUS_ENABLE1_OC_MAP :
1123                                 OC_DET_VBUS_ENABLE0_OC_MAP);
1124
1125                 reg |= (port == 2) ? OC_DET_VBUS_EN2_OC_DETECTED_VBUS_PAD2 :
1126                         port ? OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1 :
1127                                 OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0;
1128                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1129         }
1130         /*
1131          * enable respective VBUS_PAD if port is mapped to any SS port
1132          */
1133         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1134         reg &= ~((port == 2) ? USB2_OC_MAP_PORT2 :
1135                 port ? USB2_OC_MAP_PORT1 : USB2_OC_MAP_PORT0);
1136         reg |= (0x4 | port) << (port * 3);
1137         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1138
1139         ctl0_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl0_0 :
1140                         port ? padregs->usb2_otg_pad1_ctl0_0 :
1141                                 padregs->usb2_otg_pad0_ctl0_0;
1142         ctl1_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl1_0 :
1143                         port ? padregs->usb2_otg_pad1_ctl1_0 :
1144                                 padregs->usb2_otg_pad0_ctl1_0;
1145
1146         reg = readl(tegra->padctl_base + ctl0_offset);
1147         reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
1148                 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
1149                 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
1150
1151         reg |= tegra->pdata->hs_slew;
1152         reg |= (port == 2) ? tegra->pdata->ls_rslew_pad2 :
1153                         port ? tegra->pdata->ls_rslew_pad1 :
1154                         tegra->pdata->ls_rslew_pad0;
1155         reg |= (port == 2) ? tegra->pdata->hs_curr_level_pad2 :
1156                         port ? tegra->pdata->hs_curr_level_pad1 :
1157                         tegra->pdata->hs_curr_level_pad0;
1158         writel(reg, tegra->padctl_base + ctl0_offset);
1159
1160         reg = readl(tegra->padctl_base + ctl1_offset);
1161         reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
1162                 | USB2_OTG_PD_CHRP_FORCE_POWERUP
1163                 | USB2_OTG_PD_DISC_FORCE_POWERUP
1164                 | USB2_OTG_PD_DR);
1165         reg |= (tegra->pdata->hs_iref_cap << 9) |
1166                 (tegra->pdata->hs_term_range_adj << 3);
1167         writel(reg, tegra->padctl_base + ctl1_offset);
1168 }
1169
1170 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
1171         u8 port)
1172 {
1173         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1174         u32 ctl2_offset, ctl4_offset;
1175         u32 reg;
1176
1177         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1178                         padregs->iophy_usb3_pad0_ctl2_0;
1179         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1180                         padregs->iophy_usb3_pad0_ctl4_0;
1181
1182         reg = readl(tegra->padctl_base + ctl2_offset);
1183         reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
1184                 IOPHY_USB3_CDRCNTL);
1185         reg |= tegra->pdata->rx_wander | tegra->pdata->rx_eq |
1186                 tegra->pdata->cdr_cntl;
1187         writel(reg, tegra->padctl_base + ctl2_offset);
1188
1189         reg = readl(tegra->padctl_base + ctl4_offset);
1190         reg = tegra->pdata->dfe_cntl;
1191         writel(reg, tegra->padctl_base + ctl4_offset);
1192
1193         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1194         reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
1195         reg |= (tegra->bdata->ss_portmap &
1196                 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
1197         writel(reg, tegra->padctl_base + padregs->ss_port_map_0);
1198
1199         tegra_xhci_restore_dfe_ctle_context(tegra, port);
1200         /* SATA also if USB3_SS port1 mapped to it */
1201         if ((port == 1) && (XUSB_DEVICE_ID_T124 == tegra->device_id) &&
1202                         (tegra->bdata->lane_owner & BIT(0)))
1203                 tegra_xhci_restore_dfe_ctle_context(tegra, 3);
1204 }
1205
1206 /* This function assigns the USB ports to the controllers,
1207  * then programs the port capabilities and pad parameters
1208  * of ports assigned to XUSB after booted to OS.
1209  */
1210 void
1211 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
1212 {
1213         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1214         u32 reg, oc_bits = 0;
1215
1216         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1217         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
1218         reg |= tegra->pdata->hs_squelch_level | tegra->pdata->hs_disc_lvl;
1219         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1220
1221         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1222         reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3;
1223         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
1224         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1225
1226         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1227         reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
1228         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1229                 reg |= OC_DET_VBUS_ENABLE2_OC_MAP;
1230         writel(reg, tegra->padctl_base + padregs->oc_det_0);
1231
1232         /* check if over current seen. Clear if present */
1233         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1234                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
1235         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1236                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
1237         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1238                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
1239
1240         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1241         if (reg & oc_bits) {
1242                 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
1243                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1244
1245                 usleep_range(100, 200);
1246
1247                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1248                 if (reg & oc_bits)
1249                         xhci_info(tegra->xhci, "Over current still present\n");
1250         }
1251
1252         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1253         reg = USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1;
1254         if (XUSB_DEVICE_ID_T124 == tegra->device_id)
1255                 reg |= USB2_OC_MAP_PORT2;
1256         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1257
1258         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1259                 tegra_xhci_program_utmip_pad(tegra, 0);
1260         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1261                 tegra_xhci_program_utmip_pad(tegra, 1);
1262         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1263                 tegra_xhci_program_utmip_pad(tegra, 2);
1264
1265         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
1266                 tegra_xhci_program_ulpi_pad(tegra, 0);
1267
1268         if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P0)
1269                 tegra_xhci_program_hsic_pad(tegra, 0);
1270         if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P1)
1271                 tegra_xhci_program_hsic_pad(tegra, 1);
1272
1273         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1274                 tegra_xhci_program_ss_pad(tegra, 0);
1275         } else {
1276                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1277                 reg = readl(tegra->padctl_base +
1278                         padregs->iophy_misc_pad_p0_ctl3_0);
1279                 reg &= ~RX_IDLE_MODE;
1280                 reg |= RX_IDLE_MODE_OVRD;
1281                 writel(reg, tegra->padctl_base +
1282                         padregs->iophy_misc_pad_p0_ctl3_0);
1283         }
1284
1285         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1286                 tegra_xhci_program_ss_pad(tegra, 1);
1287         } else {
1288                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1289                 reg = readl(tegra->padctl_base +
1290                         padregs->iophy_misc_pad_p1_ctl3_0);
1291                 reg &= ~RX_IDLE_MODE;
1292                 reg |= RX_IDLE_MODE_OVRD;
1293                 writel(reg, tegra->padctl_base +
1294                         padregs->iophy_misc_pad_p1_ctl3_0);
1295
1296                 /* SATA lane also if USB3_SS port1 mapped to it but unused */
1297                 if (XUSB_DEVICE_ID_T124 == tegra->device_id &&
1298                                 tegra->bdata->lane_owner & BIT(0)) {
1299                         reg = readl(tegra->padctl_base +
1300                                 padregs->iophy_misc_pad_s0_ctl3_0);
1301                         reg &= ~RX_IDLE_MODE;
1302                         reg |= RX_IDLE_MODE_OVRD;
1303                         writel(reg, tegra->padctl_base +
1304                                 padregs->iophy_misc_pad_s0_ctl3_0);
1305                 }
1306         }
1307         if (XUSB_DEVICE_ID_T124 == tegra->device_id)
1308                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
1309
1310 }
1311
1312 /* This function read XUSB registers and stores in device context */
1313 static void
1314 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
1315 {
1316
1317         /* a. Save the IPFS registers */
1318         tegra->sregs.msi_bar_sz =
1319                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
1320
1321         tegra->sregs.msi_axi_barst =
1322                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
1323
1324         tegra->sregs.msi_fpci_barst =
1325                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
1326
1327         tegra->sregs.msi_vec0 =
1328                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
1329
1330         tegra->sregs.msi_en_vec0 =
1331                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
1332
1333         tegra->sregs.fpci_error_masks =
1334                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
1335
1336         tegra->sregs.intr_mask =
1337                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1338
1339         tegra->sregs.ipfs_intr_enable =
1340                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
1341
1342         tegra->sregs.ufpci_config =
1343                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
1344
1345         tegra->sregs.clkgate_hysteresis =
1346                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1347
1348         tegra->sregs.xusb_host_mccif_fifo_cntrl =
1349                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
1350
1351         /* b. Save the CFG registers */
1352
1353         tegra->sregs.hs_pls =
1354                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
1355
1356         tegra->sregs.fs_pls =
1357                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
1358
1359         tegra->sregs.hs_fs_speed =
1360                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
1361
1362         tegra->sregs.hs_fs_pp =
1363                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
1364
1365         tegra->sregs.cfg_aru =
1366                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
1367
1368         tegra->sregs.cfg_order =
1369                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
1370
1371         tegra->sregs.cfg_fladj =
1372                 readl(tegra->fpci_base + XUSB_CFG_24);
1373
1374         tegra->sregs.cfg_sid =
1375                 readl(tegra->fpci_base + XUSB_CFG_16);
1376 }
1377
1378 /* This function restores XUSB registers from device context */
1379 static void
1380 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
1381 {
1382         /* Restore Cfg registers */
1383         writel(tegra->sregs.hs_pls,
1384                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
1385
1386         writel(tegra->sregs.fs_pls,
1387                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
1388
1389         writel(tegra->sregs.hs_fs_speed,
1390                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
1391
1392         writel(tegra->sregs.hs_fs_pp,
1393                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
1394
1395         writel(tegra->sregs.cfg_aru,
1396                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
1397
1398         writel(tegra->sregs.cfg_order,
1399                 tegra->fpci_base + XUSB_CFG_FPCICFG);
1400
1401         writel(tegra->sregs.cfg_fladj,
1402                 tegra->fpci_base + XUSB_CFG_24);
1403
1404         writel(tegra->sregs.cfg_sid,
1405                 tegra->fpci_base + XUSB_CFG_16);
1406
1407         /* Restore IPFS registers */
1408
1409         writel(tegra->sregs.msi_bar_sz,
1410                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
1411
1412         writel(tegra->sregs.msi_axi_barst,
1413                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
1414
1415         writel(tegra->sregs.msi_fpci_barst,
1416                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
1417
1418         writel(tegra->sregs.msi_vec0,
1419                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
1420
1421         writel(tegra->sregs.msi_en_vec0,
1422                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
1423
1424         writel(tegra->sregs.fpci_error_masks,
1425                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
1426
1427         writel(tegra->sregs.intr_mask,
1428                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1429
1430         writel(tegra->sregs.ipfs_intr_enable,
1431                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
1432
1433         writel(tegra->sregs.ufpci_config,
1434                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
1435
1436         writel(tegra->sregs.clkgate_hysteresis,
1437                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1438
1439         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
1440                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
1441 }
1442
1443 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
1444 {
1445         struct platform_device *pdev = tegra->pdev;
1446         u32 reg, timeout = 0xff, cmd;
1447
1448         mutex_lock(&tegra->mbox_lock);
1449
1450         do {
1451                 writel(MBOX_OWNER_SW,
1452                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
1453                 reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
1454                 usleep_range(10, 20);
1455         } while (reg != MBOX_OWNER_SW && timeout--);
1456
1457         if ((timeout == 0) && (reg != MBOX_OWNER_SW)) {
1458                 dev_err(&pdev->dev, "Failed to set mbox message owner ID\n");
1459                 mutex_unlock(&tegra->mbox_lock);
1460                 return;
1461         }
1462
1463         writel((MBOX_CMD_MSG_ENABLED << MBOX_CMD_SHIFT),
1464                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
1465
1466         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1467         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
1468         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1469
1470         mutex_unlock(&tegra->mbox_lock);
1471 }
1472
1473 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
1474 {
1475         struct platform_device *pdev = tegra->pdev;
1476         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
1477         u32 phys_addr_lo;
1478         u32 HwReg;
1479         u16 nblocks;
1480         time_t fw_time;
1481         struct tm fw_tm;
1482         u8 hc_caplength;
1483         u32 usbsts, count = 0xff;
1484         struct xhci_cap_regs __iomem *cap_regs;
1485         struct xhci_op_regs __iomem *op_regs;
1486
1487         /* enable mbox interrupt */
1488         writel(readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD) | MBOX_INT_EN,
1489                 tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1490
1491         /* First thing, reset the ARU. By the time we get to
1492          * loading boot code below, reset would be complete.
1493          * alternatively we can busy wait on rst pending bit.
1494          */
1495         /* Don't reset during ELPG/LP0 exit path */
1496         if (resetARU) {
1497                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
1498                 usleep_range(1000, 2000);
1499         }
1500
1501         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
1502                 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
1503                                 csb_read(tegra, XUSB_FALC_CPUCTL));
1504                 return 0;
1505         }
1506
1507         phys_addr_lo = tegra->firmware.dma;
1508         phys_addr_lo += sizeof(struct cfgtbl);
1509
1510         /* Program the size of DFI into ILOAD_ATTR */
1511         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
1512
1513         /* Boot code of the firmware reads the ILOAD_BASE_LO register
1514          * to get to the start of the dfi in system memory.
1515          */
1516         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
1517
1518         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
1519         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
1520
1521         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
1522         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
1523
1524         /* Invalidate L2IMEM. */
1525         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
1526
1527         /* Initiate fetch of Bootcode from system memory into L2IMEM.
1528          * Program BootCode location and size in system memory.
1529          */
1530         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
1531                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
1532                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
1533         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
1534                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
1535                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
1536         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
1537
1538         /* Trigger L2IMEM Load operation. */
1539         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
1540
1541         /* Setup Falcon Auto-fill */
1542         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
1543         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
1544                 nblocks += 1;
1545         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
1546
1547         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
1548         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
1549                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
1550         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
1551
1552         csb_write(tegra, XUSB_FALC_DMACTL, 0);
1553         msleep(50);
1554
1555         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
1556
1557         /* Start Falcon CPU */
1558         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
1559         usleep_range(1000, 2000);
1560
1561         fw_time = cfg_tbl->fwimg_created_time;
1562         time_to_tm(fw_time, 0, &fw_tm);
1563         dev_info(&pdev->dev,
1564                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
1565                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
1566                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
1567                 fw_tm.tm_min, fw_tm.tm_sec,
1568                 csb_read(tegra, XUSB_FALC_CPUCTL));
1569
1570         /* return fail if firmware status is not good */
1571         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
1572                 return -EFAULT;
1573
1574         cap_regs = IO_ADDRESS(tegra->host_phy_base);
1575         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
1576         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
1577
1578         /* wait for USBSTS_CNR to get set */
1579         do {
1580                 usbsts = ioread32(&op_regs->status);
1581         } while ((usbsts & STS_CNR) && count--);
1582
1583         if (!count && (usbsts & STS_CNR)) {
1584                 dev_err(&pdev->dev, "Controller not ready\n");
1585                 return -EFAULT;
1586         }
1587         return 0;
1588 }
1589
1590 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
1591         bool release)
1592 {
1593         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1594         u32 reg;
1595
1596         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1597         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
1598                         USB2_OTG_PAD_PORT_MASK(2));
1599
1600         if (!release) {
1601                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1602                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
1603                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1604                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
1605                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1606                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
1607         }
1608
1609         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1610 }
1611 /* SS ELPG Entry initiated by fw */
1612 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
1613 {
1614         struct xhci_hcd *xhci = tegra->xhci;
1615         u32 ret = 0;
1616
1617         must_have_sync_lock(tegra);
1618
1619         /* This is SS partition ELPG entry
1620          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
1621          */
1622
1623         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
1624          * only if it is sw initiated one
1625          */
1626
1627         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
1628          * SuperSpeed partition ELPG entry via mailbox protocol
1629          */
1630
1631         /* STEP 2: xHCI PEP driver and XUSB device mode driver
1632          * enable the XUSB wakeup interrupts for the SuperSpeed
1633          * and USB2.0 ports assigned to host.Section 4.1 Step 3
1634          */
1635         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
1636
1637         /* STEP 3: xHCI PEP driver initiates the signal sequence
1638          * to enable the XUSB SSwake detection logic for the
1639          * SuperSpeed ports assigned to host.Section 4.1 Step 4
1640          */
1641         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, true);
1642
1643         /* STEP 4: System Power Management driver asserts reset
1644          * to XUSB SuperSpeed partition then disables its clocks
1645          */
1646         tegra_periph_reset_assert(tegra->ss_clk);
1647         clk_disable(tegra->ss_clk);
1648
1649         usleep_range(100, 200);
1650
1651         /* STEP 5: System Power Management driver disables the
1652          * XUSB SuperSpeed partition power rails.
1653          */
1654         debug_print_portsc(xhci);
1655
1656         /* tegra_powergate_partition also does partition reset assert */
1657         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
1658         if (ret) {
1659                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
1660                                 __func__);
1661                 /* TODO: error recovery? */
1662         }
1663         tegra->ss_pwr_gated = true;
1664
1665         /* STEP 6: xHCI PEP driver initiates the signal sequence
1666          * to enable the XUSB SSwake detection logic for the
1667          * SuperSpeed ports assigned to host.Section 4.1 Step 7
1668          */
1669         tegra_xhci_ss_vcore(tegra->bdata->portmap, true);
1670
1671         return ret;
1672 }
1673
1674 /* Host ELPG Entry */
1675 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
1676 {
1677         struct xhci_hcd *xhci = tegra->xhci;
1678         u32 ret;
1679
1680         must_have_sync_lock(tegra);
1681
1682         /* If ss is already powergated skip ss ctx save stuff */
1683         if (tegra->ss_pwr_gated) {
1684                 xhci_info(xhci, "%s: SS partition is already powergated\n",
1685                         __func__);
1686         } else {
1687                 ret = tegra_xhci_ss_elpg_entry(tegra);
1688                 if (ret) {
1689                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
1690                                 __func__, ret);
1691                         return ret;
1692                 }
1693         }
1694
1695         /* 1. IS INTR PENDING INT_PENDING=1 ? */
1696
1697         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
1698         tegra_xhci_save_xusb_ctx(tegra);
1699
1700         pmc_init(tegra, 1);
1701
1702         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
1703         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
1704                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
1705
1706         /* STEP 4: Assert reset to host clk and disable host clk */
1707         tegra_periph_reset_assert(tegra->host_clk);
1708
1709         clk_disable(tegra->host_clk);
1710
1711         /* wait 150us */
1712         usleep_range(150, 200);
1713
1714         /* flush MC client of XUSB_HOST */
1715         tegra_powergate_mc_flush(TEGRA_POWERGATE_XUSBC);
1716
1717         /* STEP 4: Powergate host partition */
1718         /* tegra_powergate_partition also does partition reset assert */
1719         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
1720         if (ret) {
1721                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
1722                         __func__, ret);
1723                 /* TODO: error handling? */
1724                 return ret;
1725         }
1726         tegra->host_pwr_gated = true;
1727
1728         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1729                 clk_disable(tegra->pll_re_vco_clk);
1730         clk_disable(tegra->emc_clk);
1731         /* set port ownership to SNPS */
1732         tegra_xhci_release_port_ownership(tegra, true);
1733
1734         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
1735                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
1736
1737         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
1738         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
1739                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
1740         return ret;
1741 }
1742
1743 /* SS ELPG Exit triggered by PADCTL irq */
1744 /**
1745  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
1746  *
1747  * This function must be called with tegra->sync_lock acquired.
1748  *
1749  * @tegra: xhci controller context
1750  * @return 0 for success, or error numbers
1751  */
1752 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
1753 {
1754         struct xhci_hcd *xhci = tegra->xhci;
1755         int ret = 0;
1756
1757         must_have_sync_lock(tegra);
1758
1759         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
1760                         tegra->hs_wake_event || tegra->host_resume_req)) {
1761
1762                 /*
1763                  * PWR_UNGATE SS partition. XUSBA
1764                  * tegra_unpowergate_partition also does partition reset
1765                  * deassert
1766                  */
1767                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
1768                 if (ret) {
1769                         xhci_err(xhci,
1770                         "%s: could not unpowergate xusba partition %d\n",
1771                         __func__, ret);
1772                         goto out;
1773                 }
1774                 if (tegra->ss_wake_event)
1775                         tegra->ss_wake_event = false;
1776
1777         } else {
1778                 xhci_info(xhci, "%s: ss already power gated\n",
1779                         __func__);
1780                 return ret;
1781         }
1782
1783         /* Step 3: Enable clock to ss partition */
1784         clk_enable(tegra->ss_clk);
1785
1786         /* Step 4: Disable ss wake detection logic */
1787         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
1788
1789         /* Step 4.1: Disable ss wake detection logic */
1790         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
1791
1792         /* wait 150us */
1793         usleep_range(150, 200);
1794
1795         /* Step 4.2: Disable ss wake detection logic */
1796         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
1797
1798         /* Step 6 Deassert reset for ss clks */
1799         tegra_periph_reset_deassert(tegra->ss_clk);
1800
1801         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
1802         tegra->ss_pwr_gated = false;
1803 out:
1804         return ret;
1805 }
1806
1807 static void ss_partition_elpg_exit_work(struct work_struct *work)
1808 {
1809         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
1810                 ss_elpg_exit_work);
1811
1812         mutex_lock(&tegra->sync_lock);
1813         tegra_xhci_ss_partition_elpg_exit(tegra);
1814         mutex_unlock(&tegra->sync_lock);
1815 }
1816
1817 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
1818 static void update_remote_wakeup_ports_pmc(struct tegra_xhci_hcd *tegra)
1819 {
1820         struct xhci_hcd *xhci = tegra->xhci;
1821         u32 wake2_status;
1822
1823 #define PMC_WAKE2_STATUS        0x168
1824 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
1825
1826         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
1827
1828         if (wake2_status & PADCTL_WAKE) {
1829                 /* FIXME: This is customized for Dalmore, find a generic way */
1830                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
1831                 /* clear wake status */
1832                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
1833         }
1834
1835         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
1836                         __func__, tegra->usb3_rh_remote_wakeup_ports);
1837 }
1838
1839 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
1840 {
1841         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1842         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
1843         int port, num_ports;
1844         unsigned long *remote_wakeup_ports;
1845         u32 portsc;
1846         __le32 __iomem  **port_array;
1847         unsigned char *rh;
1848         unsigned int retry = 64;
1849
1850
1851         if (hcd == xhci->shared_hcd) {
1852                 port_array = xhci->usb3_ports;
1853                 num_ports = xhci->num_usb3_ports;
1854                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
1855                 rh = "usb3 roothub";
1856         } else
1857                 return;
1858
1859         while (*remote_wakeup_ports && retry--) {
1860                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
1861                         portsc = xhci_readl(xhci, port_array[port]);
1862
1863                         if (!(portsc & PORT_CONNECT)) {
1864                                 /* nothing to do if already disconnected */
1865                                 clear_bit(port, remote_wakeup_ports);
1866                                 continue;
1867                         }
1868
1869                         if ((portsc & PORT_PLS_MASK) == XDEV_U0)
1870                                 clear_bit(port, remote_wakeup_ports);
1871                         else
1872                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
1873                                                 __func__, rh, port, portsc);
1874                 }
1875
1876                 if (*remote_wakeup_ports)
1877                         msleep(20); /* give some time, irq will direct U0 */
1878         }
1879
1880         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
1881                         *remote_wakeup_ports);
1882 }
1883
1884 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
1885 {
1886         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1887         u32 reg, utmip_rctrl_val, utmip_tctrl_val;
1888
1889         /* Program XUSB as port owner for all usb2 ports */
1890         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1891         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
1892                         USB2_OTG_PAD_PORT_MASK(2));
1893         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
1894                 USB2_OTG_PAD_PORT_OWNER_XUSB(1) | USB2_OTG_PAD_PORT_MASK(2);
1895         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1896
1897         /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
1898          * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
1899          */
1900         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1901         reg &= ~((1 << 12) | (1 << 13));
1902         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1903
1904         /* wait 20us */
1905         usleep_range(20, 30);
1906
1907         /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
1908          * :: TCTRL and RCTRL
1909          */
1910         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl1_0);
1911         utmip_rctrl_val = RCTRL(reg);
1912         utmip_tctrl_val = TCTRL(reg);
1913
1914         /*
1915          * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
1916          * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
1917          */
1918         pmc_data.utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
1919         pmc_data.utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
1920
1921         xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
1922                 pmc_data.utmip_rctrl_val, pmc_data.utmip_tctrl_val);
1923
1924         /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
1925          * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
1926          */
1927         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1928         reg |= (1 << 13);
1929         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1930
1931         /* Program these values into PMC regiseter and program the
1932          * PMC override
1933          */
1934         reg = PMC_TCTRL_VAL(pmc_data.utmip_tctrl_val) |
1935                 PMC_RCTRL_VAL(pmc_data.utmip_rctrl_val);
1936         tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG, 0xffffffff, reg);
1937
1938         reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
1939         tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
1940
1941         /* Restore correct port ownership in padctl */
1942         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1943         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
1944                         USB2_OTG_PAD_PORT_MASK(2));
1945         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1946                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
1947         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1948                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
1949         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1950                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
1951         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1952 }
1953
1954 /* Host ELPG Exit triggered by PADCTL irq */
1955 /**
1956  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
1957  *
1958  * This function must be called with tegra->sync_lock acquired.
1959  *
1960  * @tegra: xhci controller context
1961  * @return 0 for success, or error numbers
1962  */
1963 static int
1964 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
1965 {
1966         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1967         struct xhci_hcd *xhci = tegra->xhci;
1968         int ret = 0;
1969
1970         must_have_sync_lock(tegra);
1971
1972         if (!tegra->hc_in_elpg)
1973                 return 0;
1974
1975         clk_enable(tegra->emc_clk);
1976         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1977                 clk_enable(tegra->pll_re_vco_clk);
1978         /* Step 2: Enable clock to host partition */
1979         clk_enable(tegra->host_clk);
1980
1981         if (tegra->lp0_exit) {
1982                 u32 reg, oc_bits = 0;
1983
1984                 tegra_xhci_war_for_tctrl_rctrl(tegra);
1985                 /* check if over current seen. Clear if present */
1986                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1987                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
1988                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1989                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
1990                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1991                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
1992
1993                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1994                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
1995                 if (reg & oc_bits) {
1996                         xhci_info(xhci, "Over current detected. Clearing...\n");
1997                         writel(reg, tegra->padctl_base + padregs->oc_det_0);
1998
1999                         usleep_range(100, 200);
2000
2001                         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2002                         if (reg & oc_bits)
2003                                 xhci_info(xhci, "Over current still present\n");
2004                 }
2005                 tegra_xhci_padctl_portmap_and_caps(tegra);
2006                 /* release clamps post deassert */
2007                 tegra->lp0_exit = false;
2008         }
2009
2010         /* Clear FLUSH_ENABLE of MC client */
2011         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
2012
2013         /* set port ownership back to xusb */
2014         tegra_xhci_release_port_ownership(tegra, false);
2015
2016         /*
2017          * PWR_UNGATE Host partition. XUSBC
2018          * tegra_unpowergate_partition also does partition reset deassert
2019          */
2020         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
2021         if (ret) {
2022                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2023                         __func__, ret);
2024                 goto out;
2025         }
2026
2027         /* Step 4: Deassert reset to host partition clk */
2028         tegra_periph_reset_deassert(tegra->host_clk);
2029
2030         /* Step 6.1: IPFS and XUSB BAR initialization */
2031         tegra_xhci_cfg(tegra);
2032
2033         /* Step 6.2: IPFS and XUSB related restore */
2034         tegra_xhci_restore_ctx(tegra);
2035
2036         /* Step 8: xhci spec related ctx restore
2037          * will be done in xhci_resume().Do it here.
2038          */
2039
2040         tegra_xhci_ss_partition_elpg_exit(tegra);
2041
2042         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
2043         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
2044                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
2045                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
2046         }
2047
2048         /* clear ovrd bits */
2049         tegra_xhci_rx_idle_mode_override(tegra, false);
2050
2051         /* Load firmware */
2052         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
2053                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
2054                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
2055                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
2056                         __func__,
2057                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
2058                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
2059                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
2060                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
2061                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
2062                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
2063                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
2064                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
2065                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
2066         debug_print_portsc(xhci);
2067
2068         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
2069         if (ret < 0) {
2070                 xhci_err(xhci, "%s: failed to load firmware %d\n",
2071                         __func__, ret);
2072                 goto out;
2073         }
2074
2075         pmc_init(tegra, 0);
2076
2077         tegra->hc_in_elpg = false;
2078         ret = xhci_resume(tegra->xhci, 0);
2079         if (ret) {
2080                 xhci_err(xhci, "%s: could not resume right %d\n",
2081                                 __func__, ret);
2082                 goto out;
2083         }
2084
2085         update_remote_wakeup_ports_pmc(tegra);
2086
2087         if (tegra->hs_wake_event)
2088                 tegra->hs_wake_event = false;
2089
2090         if (tegra->host_resume_req)
2091                 tegra->host_resume_req = false;
2092
2093         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
2094                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
2095
2096         tegra->host_pwr_gated = false;
2097 out:
2098         return ret;
2099 }
2100
2101 static void host_partition_elpg_exit_work(struct work_struct *work)
2102 {
2103         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2104                 host_elpg_exit_work);
2105
2106         mutex_lock(&tegra->sync_lock);
2107         tegra_xhci_host_partition_elpg_exit(tegra);
2108         mutex_unlock(&tegra->sync_lock);
2109 }
2110
2111 /* Mailbox handling function. This function handles requests
2112  * from firmware and communicates with clock and powergating
2113  * module to alter clock rates and to power gate/ungate xusb
2114  * partitions.
2115  *
2116  * Following is the structure of mailbox messages.
2117  * bit 31:28 - msg type
2118  * bits 27:0 - mbox data
2119  * FIXME:  Check if we can just call clock functions like below
2120  * or should we schedule it for calling later ?
2121  */
2122
2123 static void
2124 tegra_xhci_process_mbox_message(struct work_struct *work)
2125 {
2126         u32 sw_resp = 0, cmd, data_in, fw_msg;
2127         int ret = 0;
2128         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2129                                         mbox_work);
2130         struct xhci_hcd *xhci = tegra->xhci;
2131         unsigned int freq_khz;
2132
2133         mutex_lock(&tegra->mbox_lock);
2134
2135         /* get the owner id */
2136         tegra->mbox_owner = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2137         tegra->mbox_owner &= MBOX_OWNER_ID_MASK;
2138
2139         /* get the mbox message from firmware */
2140         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
2141
2142         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2143         if (data_in) {
2144                 mutex_unlock(&tegra->mbox_lock);
2145                 return;
2146         }
2147
2148         /* get cmd type and cmd data */
2149         tegra->cmd_type = (fw_msg & MBOX_CMD_TYPE_MASK) >> MBOX_CMD_SHIFT;
2150         tegra->cmd_data = (fw_msg & MBOX_CMD_DATA_MASK);
2151
2152         /* decode the message and make appropriate requests to
2153          * clock or powergating module.
2154          */
2155
2156         switch (tegra->cmd_type) {
2157         case MBOX_CMD_INC_FALC_CLOCK:
2158         case MBOX_CMD_DEC_FALC_CLOCK:
2159                 ret = tegra_xusb_request_clk_rate(
2160                                 tegra,
2161                                 tegra->falc_clk,
2162                                 tegra->cmd_data,
2163                                 &sw_resp);
2164                 if (ret)
2165                         xhci_err(xhci, "%s: could not set required falc rate\n",
2166                                 __func__);
2167                 goto send_sw_response;
2168         case MBOX_CMD_INC_SSPI_CLOCK:
2169         case MBOX_CMD_DEC_SSPI_CLOCK:
2170                 ret = tegra_xusb_request_clk_rate(
2171                                 tegra,
2172                                 tegra->ss_src_clk,
2173                                 tegra->cmd_data,
2174                                 &sw_resp);
2175                 if (ret)
2176                         xhci_err(xhci, "%s: could not set required ss rate.\n",
2177                                 __func__);
2178                 goto send_sw_response;
2179         case MBOX_CMD_SET_BW:
2180                 /* fw sends BW request in MByte/sec */
2181                 freq_khz = tegra_emc_bw_to_freq_req(tegra->cmd_data << 10);
2182                 clk_set_rate(tegra->emc_clk, freq_khz * 1000);
2183
2184                 /* clear MBOX_SMI_INT_EN bit */
2185                 cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2186                 cmd &= ~MBOX_SMI_INT_EN;
2187                 writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2188
2189                 /* clear mbox owner as ACK will not be sent for this request */
2190                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2191                 break;
2192         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
2193                 tegra_xhci_save_dfe_ctle_context(tegra, tegra->cmd_data);
2194                 tegra_xhci_restore_dfe_ctle_context(tegra, tegra->cmd_data);
2195                 /* SATA lane also if USB3_SS port1 mapped to it */
2196                 if (tegra->cmd_data == 0x1 &&
2197                         XUSB_DEVICE_ID_T124 == tegra->device_id &&
2198                                 tegra->bdata->lane_owner & BIT(0)) {
2199                         tegra_xhci_save_dfe_ctle_context(tegra, 3);
2200                         tegra_xhci_restore_dfe_ctle_context(tegra, 3);
2201                 }
2202
2203                 sw_resp |= (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
2204                 goto send_sw_response;
2205         case MBOX_CMD_ACK:
2206                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2207                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2208                 break;
2209         case MBOX_CMD_NACK:
2210                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2211                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2212                 break;
2213         default:
2214                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
2215                                 __func__, tegra->cmd_type);
2216         }
2217         mutex_unlock(&tegra->mbox_lock);
2218         return;
2219
2220 send_sw_response:
2221         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2222         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2223         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
2224         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2225
2226         mutex_unlock(&tegra->mbox_lock);
2227 }
2228
2229 static irqreturn_t tegra_xhci_xusb_host_irq(int irq, void *ptrdev)
2230 {
2231         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2232         struct xhci_hcd *xhci = tegra->xhci;
2233
2234         xhci_dbg(xhci, "%s", __func__);
2235         return IRQ_HANDLED;
2236 }
2237
2238 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
2239 {
2240         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2241         struct xhci_hcd *xhci = tegra->xhci;
2242         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2243         u32 elpg_program0 = 0;
2244
2245         spin_lock(&tegra->lock);
2246
2247         tegra->last_jiffies = jiffies;
2248
2249         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
2250         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
2251
2252         /* Clear the interrupt cause. We already read the intr status. */
2253         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2254         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
2255
2256         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
2257         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
2258                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2259         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
2260                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
2261         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
2262                 __func__,
2263                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad0_ctl0_0));
2264         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
2265                 __func__,
2266                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad1_ctl0_0));
2267         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
2268                 __func__,
2269                 readl(tegra->padctl_base + padregs->usb2_bchrg_bias_pad_0));
2270
2271         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
2272                 tegra->ss_wake_event = true;
2273         else if (elpg_program0 &
2274                         (USB2_PORT0_WAKEUP_EVENT | USB2_PORT1_WAKEUP_EVENT))
2275                 tegra->hs_wake_event = true;
2276
2277         if (tegra->ss_wake_event || tegra->hs_wake_event) {
2278                 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
2279                         xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
2280                         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
2281                 } else if (tegra->ss_pwr_gated
2282                                 && tegra->host_pwr_gated) {
2283                         xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
2284                                 __func__);
2285                         schedule_work(&tegra->host_elpg_exit_work);
2286                 }
2287         } else {
2288                 xhci_err(xhci, "error: wake due to no hs/ss event\n");
2289                 tegra_usb_pad_reg_write(padregs->elpg_program_0, 0xffffffff);
2290         }
2291         spin_unlock(&tegra->lock);
2292         return IRQ_HANDLED;
2293 }
2294
2295 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
2296 {
2297         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2298         u32 temp;
2299
2300         spin_lock(&tegra->lock);
2301
2302         /* clear the mbox intr status 1st thing. Other
2303          * bits are W1C bits, so just write to SMI bit.
2304          */
2305
2306         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
2307
2308         /* write 1 to clear SMI INTR en bit ( bit 3 ) */
2309         temp = MBOX_SMI_INTR_EN;
2310         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
2311
2312         schedule_work(&tegra->mbox_work);
2313
2314         spin_unlock(&tegra->lock);
2315         return IRQ_HANDLED;
2316 }
2317
2318 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
2319 {
2320         /*
2321          * As of now platform drivers don't provide MSI support so we ensure
2322          * here that the generic code does not try to make a pci_dev from our
2323          * dev struct in order to setup MSI
2324          */
2325         xhci->quirks |= XHCI_BROKEN_MSI;
2326         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
2327 }
2328
2329 /* called during probe() after chip reset completes */
2330 static int xhci_plat_setup(struct usb_hcd *hcd)
2331 {
2332         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
2333 }
2334
2335 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
2336         const char *name, void __iomem **region)
2337 {
2338         struct resource *res;
2339         void __iomem *mem;
2340
2341         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
2342         if (!res) {
2343                 dev_err(&pdev->dev, "memory resource %s doesn't exist\n", name);
2344                 return -ENODEV;
2345         }
2346
2347         mem = devm_request_and_ioremap(&pdev->dev, res);
2348         if (!mem) {
2349                 dev_err(&pdev->dev, "failed to ioremap for %s\n", name);
2350                 return -EFAULT;
2351         }
2352         *region = mem;
2353
2354         return 0;
2355 }
2356
2357 static int tegra_xhci_request_irq(struct platform_device *pdev,
2358         const char *rscname, irq_handler_t handler, unsigned long irqflags,
2359         const char *devname, int *irq_no)
2360 {
2361         int ret;
2362         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2363         struct resource *res;
2364
2365         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, rscname);
2366         if (!res) {
2367                 dev_err(&pdev->dev, "irq resource %s doesn't exist\n", rscname);
2368                 return -ENODEV;
2369         }
2370
2371         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
2372                         devname, tegra);
2373         if (ret != 0) {
2374                 dev_err(&pdev->dev,
2375                         "failed to request_irq for %s (irq %d), error = %d\n",
2376                         devname, res->start, ret);
2377                 return ret;
2378         }
2379         *irq_no = res->start;
2380
2381         return 0;
2382 }
2383
2384 #ifdef CONFIG_PM
2385
2386 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
2387 {
2388         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2389         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2390         int err = 0;
2391         unsigned long flags;
2392
2393         mutex_lock(&tegra->sync_lock);
2394
2395         if (xhci->shared_hcd == hcd) {
2396                 tegra->usb3_rh_suspend = true;
2397                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
2398         } else if (xhci->main_hcd == hcd) {
2399                 tegra->usb2_rh_suspend = true;
2400                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
2401         }
2402
2403         WARN_ON(tegra->hc_in_elpg);
2404
2405         /* suspend xhci bus. This will also set remote mask */
2406         err = xhci_bus_suspend(hcd);
2407         if (err) {
2408                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
2409                                 __func__, err);
2410                 goto xhci_bus_suspend_failed;
2411         }
2412
2413         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
2414                 goto done; /* one of the root hubs is still working */
2415
2416         spin_lock_irqsave(&tegra->lock, flags);
2417         tegra->hc_in_elpg = true;
2418         spin_unlock_irqrestore(&tegra->lock, flags);
2419
2420         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
2421
2422         /* save xhci spec ctx. Already done by xhci_suspend */
2423         err = xhci_suspend(tegra->xhci);
2424         if (err) {
2425                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
2426                 goto xhci_suspend_failed;
2427         }
2428
2429         /* Powergate host. Include ss power gate if not already done */
2430         err = tegra_xhci_host_elpg_entry(tegra);
2431         if (err) {
2432                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
2433                                 __func__, err);
2434                 goto tegra_xhci_host_elpg_entry_failed;
2435         }
2436
2437         /* At this point,ensure ss/hs intr enables are always on */
2438         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2439         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2440
2441 done:
2442         /* pads are disabled only if usb2 root hub in xusb is idle */
2443         /* pads will actually be disabled only when all usb2 ports are idle */
2444         if (xhci->main_hcd == hcd) {
2445                 utmi_phy_pad_disable();
2446                 utmi_phy_iddq_override(true);
2447                 /* port ownership to SNPS when no HS connected to save power */
2448                 if (!is_any_hs_connected(xhci))
2449                         tegra_xhci_release_port_ownership(tegra, true);
2450         } else if (xhci->shared_hcd == hcd) {
2451                 /* save leakage power when SS not in use.
2452                  * This is also done when fw mbox message is received for freq
2453                  * decrease but on T114 we don't change freq due to sw WAR
2454                  * used for hs disconnect issue.
2455                  */
2456                 tegra_xhci_rx_idle_mode_override(tegra, true);
2457         }
2458         mutex_unlock(&tegra->sync_lock);
2459         return 0;
2460
2461 tegra_xhci_host_elpg_entry_failed:
2462
2463 xhci_suspend_failed:
2464         tegra->hc_in_elpg = false;
2465 xhci_bus_suspend_failed:
2466         if (xhci->shared_hcd == hcd)
2467                 tegra->usb3_rh_suspend = false;
2468         else if (xhci->main_hcd == hcd)
2469                 tegra->usb2_rh_suspend = false;
2470
2471         mutex_unlock(&tegra->sync_lock);
2472         return err;
2473 }
2474
2475 /* First, USB2HCD and then USB3HCD resume will be called */
2476 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
2477 {
2478         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2479         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2480         int err = 0;
2481
2482         mutex_lock(&tegra->sync_lock);
2483
2484         tegra->host_resume_req = true;
2485
2486         if (xhci->shared_hcd == hcd)
2487                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
2488         else if (xhci->main_hcd == hcd)
2489                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
2490
2491         /* pads are disabled only if usb2 root hub in xusb is idle */
2492         /* pads will actually be disabled only when all usb2 ports are idle */
2493         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
2494                 utmi_phy_pad_enable();
2495                 utmi_phy_iddq_override(false);
2496                 tegra_xhci_release_port_ownership(tegra, false);
2497         } else if (xhci->shared_hcd == hcd && tegra->usb3_rh_suspend) {
2498                 /* clear ovrd bits */
2499                 tegra_xhci_rx_idle_mode_override(tegra, false);
2500         }
2501         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
2502                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
2503                         tegra_xhci_host_partition_elpg_exit(tegra);
2504         }
2505
2506          /* handle remote wakeup before resuming bus */
2507         wait_remote_wakeup_ports(hcd);
2508
2509         err = xhci_bus_resume(hcd);
2510         if (err) {
2511                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
2512                                 __func__, err);
2513                 goto xhci_bus_resume_failed;
2514         }
2515
2516         if (xhci->shared_hcd == hcd)
2517                 tegra->usb3_rh_suspend = false;
2518         else if (xhci->main_hcd == hcd)
2519                 tegra->usb2_rh_suspend = false;
2520
2521         mutex_unlock(&tegra->sync_lock);
2522         return 0;
2523
2524 xhci_bus_resume_failed:
2525         /* TODO: reverse elpg? */
2526         mutex_unlock(&tegra->sync_lock);
2527         return err;
2528 }
2529 #endif
2530
2531 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
2532 {
2533         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2534         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2535         irqreturn_t iret = IRQ_HANDLED;
2536         u32 status;
2537
2538         spin_lock(&tegra->lock);
2539         if (tegra->hc_in_elpg) {
2540                 spin_lock(&xhci->lock);
2541                 if (HCD_HW_ACCESSIBLE(hcd)) {
2542                         status = xhci_readl(xhci, &xhci->op_regs->status);
2543                         status |= STS_EINT;
2544                         xhci_writel(xhci, status, &xhci->op_regs->status);
2545                 }
2546                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
2547                                 __func__);
2548                 schedule_work(&tegra->host_elpg_exit_work);
2549                 spin_unlock(&xhci->lock);
2550         } else
2551                 iret = xhci_irq(hcd);
2552         spin_unlock(&tegra->lock);
2553
2554         return iret;
2555 }
2556
2557
2558 static const struct hc_driver tegra_plat_xhci_driver = {
2559         .description =          "tegra-xhci",
2560         .product_desc =         "Nvidia xHCI Host Controller",
2561         .hcd_priv_size =        sizeof(struct xhci_hcd *),
2562
2563         /*
2564          * generic hardware linkage
2565          */
2566         .irq =                  tegra_xhci_irq,
2567         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
2568
2569         /*
2570          * basic lifecycle operations
2571          */
2572         .reset =                xhci_plat_setup,
2573         .start =                xhci_run,
2574         .stop =                 xhci_stop,
2575         .shutdown =             xhci_shutdown,
2576
2577         /*
2578          * managing i/o requests and associated device resources
2579          */
2580         .urb_enqueue =          xhci_urb_enqueue,
2581         .urb_dequeue =          xhci_urb_dequeue,
2582         .alloc_dev =            xhci_alloc_dev,
2583         .free_dev =             xhci_free_dev,
2584         .alloc_streams =        xhci_alloc_streams,
2585         .free_streams =         xhci_free_streams,
2586         .add_endpoint =         xhci_add_endpoint,
2587         .drop_endpoint =        xhci_drop_endpoint,
2588         .endpoint_reset =       xhci_endpoint_reset,
2589         .check_bandwidth =      xhci_check_bandwidth,
2590         .reset_bandwidth =      xhci_reset_bandwidth,
2591         .address_device =       xhci_address_device,
2592         .update_hub_device =    xhci_update_hub_device,
2593         .reset_device =         xhci_discover_or_reset_device,
2594
2595         /*
2596          * scheduling support
2597          */
2598         .get_frame_number =     xhci_get_frame,
2599
2600         /* Root hub support */
2601         .hub_control =          xhci_hub_control,
2602         .hub_status_data =      xhci_hub_status_data,
2603
2604 #ifdef CONFIG_PM
2605         .bus_suspend =          tegra_xhci_bus_suspend,
2606         .bus_resume =           tegra_xhci_bus_resume,
2607 #endif
2608 };
2609
2610 #ifdef CONFIG_PM
2611 static int
2612 tegra_xhci_suspend(struct platform_device *pdev,
2613                                                 pm_message_t state)
2614 {
2615         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2616         struct xhci_hcd *xhci = tegra->xhci;
2617
2618         int ret = 0;
2619
2620         mutex_lock(&tegra->sync_lock);
2621         if (!tegra->hc_in_elpg) {
2622                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
2623                                 __func__);
2624                 mutex_unlock(&tegra->sync_lock);
2625                 return -EBUSY;
2626         }
2627         mutex_unlock(&tegra->sync_lock);
2628
2629         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2630         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
2631
2632         /* enable_irq_wake for ss ports */
2633         ret = enable_irq_wake(tegra->padctl_irq);
2634         if (ret < 0) {
2635                 xhci_err(xhci,
2636                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
2637                 __func__, tegra->padctl_irq, ret);
2638         }
2639
2640         /* enable_irq_wake for hs/fs/ls ports */
2641         ret = enable_irq_wake(tegra->usb3_irq);
2642         if (ret < 0) {
2643                 xhci_err(xhci,
2644                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
2645                 __func__, tegra->usb3_irq, ret);
2646         }
2647         regulator_disable(tegra->xusb_avdd_usb3_pll_reg);
2648         regulator_disable(tegra->xusb_avddio_usb3_reg);
2649         tegra_usb2_clocks_deinit(tegra);
2650
2651         return ret;
2652 }
2653
2654 static int
2655 tegra_xhci_resume(struct platform_device *pdev)
2656 {
2657         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2658
2659         dev_dbg(&pdev->dev, "%s\n", __func__);
2660
2661         tegra->last_jiffies = jiffies;
2662
2663         disable_irq_wake(tegra->padctl_irq);
2664         disable_irq_wake(tegra->usb3_irq);
2665         tegra->lp0_exit = true;
2666
2667         regulator_enable(tegra->xusb_avddio_usb3_reg);
2668         regulator_enable(tegra->xusb_avdd_usb3_pll_reg);
2669         tegra_usb2_clocks_init(tegra);
2670
2671         return 0;
2672 }
2673 #endif
2674
2675
2676 static int init_bootloader_firmware(struct tegra_xhci_hcd *tegra)
2677 {
2678         struct platform_device *pdev = tegra->pdev;
2679         void __iomem *fw_mmio_base;
2680         phys_addr_t fw_mem_phy_addr;
2681         size_t fw_size;
2682         dma_addr_t fw_dma;
2683 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2684         int ret;
2685 #endif
2686
2687         /* bootloader saved firmware memory address in PMC SCRATCH34 register */
2688         fw_mem_phy_addr = tegra_usb_pmc_reg_read(PMC_SCRATCH34);
2689
2690         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
2691                         fw_mem_phy_addr, sizeof(struct cfgtbl));
2692
2693         if (!fw_mmio_base) {
2694                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
2695                                         fw_mem_phy_addr);
2696                         return -ENOMEM;
2697         }
2698
2699         fw_size = ioread32(fw_mmio_base + FW_SIZE_OFFSET);
2700         devm_iounmap(&pdev->dev, fw_mmio_base);
2701
2702         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
2703                         fw_mem_phy_addr, fw_size);
2704         if (!fw_mmio_base) {
2705                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
2706                                         fw_mem_phy_addr);
2707                         return -ENOMEM;
2708         }
2709
2710         dev_info(&pdev->dev, "Firmware Memory: phy 0x%x mapped 0x%p (%d Bytes)\n",
2711                         fw_mem_phy_addr, fw_mmio_base, fw_size);
2712
2713 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2714         fw_dma = dma_map_linear(&pdev->dev, fw_mem_phy_addr, fw_size,
2715                         DMA_TO_DEVICE);
2716         if (fw_dma == DMA_ERROR_CODE) {
2717                 dev_err(&pdev->dev, "%s: dma_map_linear failed\n",
2718                                 __func__);
2719                 ret = -ENOMEM;
2720                 goto error_iounmap;
2721         }
2722 #else
2723         fw_dma = fw_mem_phy_addr;
2724 #endif
2725         dev_info(&pdev->dev, "Firmware DMA Memory: dma 0x%p (%d Bytes)\n",
2726                         (void *) fw_dma, fw_size);
2727
2728         /* all set and ready to go */
2729         tegra->firmware.data = fw_mmio_base;
2730         tegra->firmware.dma = fw_dma;
2731         tegra->firmware.size = fw_size;
2732
2733         return 0;
2734
2735 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2736 error_iounmap:
2737         devm_iounmap(&pdev->dev, fw_mmio_base);
2738         return ret;
2739 #endif
2740 }
2741
2742 static void deinit_bootloader_firmware(struct tegra_xhci_hcd *tegra)
2743 {
2744         struct platform_device *pdev = tegra->pdev;
2745         void __iomem *fw_mmio_base = tegra->firmware.data;
2746
2747 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2748         dma_unmap_single(&pdev->dev, tegra->firmware.dma,
2749                         tegra->firmware.size, DMA_TO_DEVICE);
2750 #endif
2751         devm_iounmap(&pdev->dev, fw_mmio_base);
2752
2753         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
2754 }
2755
2756 static int init_firmware(struct tegra_xhci_hcd *tegra)
2757 {
2758         return init_bootloader_firmware(tegra);
2759 }
2760
2761 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
2762 {
2763         deinit_bootloader_firmware(tegra);
2764 }
2765
2766 static struct tegra_xusb_padctl_regs t114_padregs_offset = {
2767         .boot_media_0                   = 0x0,
2768         .usb2_pad_mux_0                 = 0x4,
2769         .usb2_port_cap_0                = 0x8,
2770         .snps_oc_map_0                  = 0xc,
2771         .usb2_oc_map_0                  = 0x10,
2772         .ss_port_map_0                  = 0x14,
2773         .oc_det_0                       = 0x18,
2774         .elpg_program_0                 = 0x1c,
2775         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
2776         .usb2_bchrg_otgpad0_ctl1_0      = 0xffff,
2777         .usb2_bchrg_otgpad1_ctl0_0      = 0x24,
2778         .usb2_bchrg_otgpad1_ctl1_0      = 0xffff,
2779         .usb2_bchrg_otgpad2_ctl0_0      = 0xffff,
2780         .usb2_bchrg_otgpad2_ctl1_0      = 0xffff,
2781         .usb2_bchrg_bias_pad_0          = 0x28,
2782         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
2783         .iophy_pll_p0_ctl1_0            = 0x30,
2784         .iophy_pll_p0_ctl2_0            = 0x34,
2785         .iophy_pll_p0_ctl3_0            = 0x38,
2786         .iophy_pll_p0_ctl4_0            = 0x3c,
2787         .iophy_usb3_pad0_ctl1_0         = 0x40,
2788         .iophy_usb3_pad1_ctl1_0         = 0x44,
2789         .iophy_usb3_pad0_ctl2_0         = 0x48,
2790         .iophy_usb3_pad1_ctl2_0         = 0x4c,
2791         .iophy_usb3_pad0_ctl3_0         = 0x50,
2792         .iophy_usb3_pad1_ctl3_0         = 0x54,
2793         .iophy_usb3_pad0_ctl4_0         = 0x58,
2794         .iophy_usb3_pad1_ctl4_0         = 0x5c,
2795         .iophy_misc_pad_p0_ctl1_0       = 0x60,
2796         .iophy_misc_pad_p1_ctl1_0       = 0x64,
2797         .iophy_misc_pad_p0_ctl2_0       = 0x68,
2798         .iophy_misc_pad_p1_ctl2_0       = 0x6c,
2799         .iophy_misc_pad_p0_ctl3_0       = 0x70,
2800         .iophy_misc_pad_p1_ctl3_0       = 0x74,
2801         .iophy_misc_pad_p0_ctl4_0       = 0x78,
2802         .iophy_misc_pad_p1_ctl4_0       = 0x7c,
2803         .iophy_misc_pad_p0_ctl5_0       = 0x80,
2804         .iophy_misc_pad_p1_ctl5_0       = 0x84,
2805         .iophy_misc_pad_p0_ctl6_0       = 0x88,
2806         .iophy_misc_pad_p1_ctl6_0       = 0x8c,
2807         .usb2_otg_pad0_ctl0_0           = 0x90,
2808         .usb2_otg_pad1_ctl0_0           = 0x94,
2809         .usb2_otg_pad2_ctl0_0           = 0xffff,
2810         .usb2_otg_pad0_ctl1_0           = 0x98,
2811         .usb2_otg_pad1_ctl1_0           = 0x9c,
2812         .usb2_otg_pad2_ctl1_0           = 0xffff,
2813         .usb2_bias_pad_ctl0_0           = 0xa0,
2814         .usb2_bias_pad_ctl1_0           = 0xa4,
2815         .usb2_hsic_pad0_ctl0_0          = 0xa8,
2816         .usb2_hsic_pad1_ctl0_0          = 0xac,
2817         .usb2_hsic_pad0_ctl1_0          = 0xb0,
2818         .usb2_hsic_pad1_ctl1_0          = 0xb4,
2819         .usb2_hsic_pad0_ctl2_0          = 0xb8,
2820         .usb2_hsic_pad1_ctl2_0          = 0xbc,
2821         .ulpi_link_trim_ctl0            = 0xc0,
2822         .ulpi_null_clk_trim_ctl0        = 0xc4,
2823         .hsic_strb_trim_ctl0            = 0xc8,
2824         .wake_ctl0                      = 0xcc,
2825         .pm_spare0                      = 0xd0,
2826         .iophy_misc_pad_p2_ctl1_0       = 0xffff,
2827         .iophy_misc_pad_p3_ctl1_0       = 0xffff,
2828         .iophy_misc_pad_p4_ctl1_0       = 0xffff,
2829         .iophy_misc_pad_p2_ctl2_0       = 0xffff,
2830         .iophy_misc_pad_p3_ctl2_0       = 0xffff,
2831         .iophy_misc_pad_p4_ctl2_0       = 0xffff,
2832         .iophy_misc_pad_p2_ctl3_0       = 0xffff,
2833         .iophy_misc_pad_p3_ctl3_0       = 0xffff,
2834         .iophy_misc_pad_p4_ctl3_0       = 0xffff,
2835         .iophy_misc_pad_p2_ctl4_0       = 0xffff,
2836         .iophy_misc_pad_p3_ctl4_0       = 0xffff,
2837         .iophy_misc_pad_p4_ctl4_0       = 0xffff,
2838         .iophy_misc_pad_p2_ctl5_0       = 0xffff,
2839         .iophy_misc_pad_p3_ctl5_0       = 0xffff,
2840         .iophy_misc_pad_p4_ctl5_0       = 0xffff,
2841         .iophy_misc_pad_p2_ctl6_0       = 0xffff,
2842         .iophy_misc_pad_p3_ctl6_0       = 0xffff,
2843         .iophy_misc_pad_p4_ctl6_0       = 0xffff,
2844         .usb3_pad_mux_0                 = 0xffff,
2845         .iophy_pll_s0_ctl1_0            = 0xffff,
2846         .iophy_pll_s0_ctl2_0            = 0xffff,
2847         .iophy_pll_s0_ctl3_0            = 0xffff,
2848         .iophy_pll_s0_ctl4_0            = 0xffff,
2849         .iophy_misc_pad_s0_ctl1_0       = 0xffff,
2850         .iophy_misc_pad_s0_ctl2_0       = 0xffff,
2851         .iophy_misc_pad_s0_ctl3_0       = 0xffff,
2852         .iophy_misc_pad_s0_ctl4_0       = 0xffff,
2853         .iophy_misc_pad_s0_ctl5_0       = 0xffff,
2854         .iophy_misc_pad_s0_ctl6_0       = 0xffff,
2855 };
2856
2857 static struct tegra_xusb_padctl_regs t124_padregs_offset = {
2858         .boot_media_0                   = 0x0,
2859         .usb2_pad_mux_0                 = 0x4,
2860         .usb2_port_cap_0                = 0x8,
2861         .snps_oc_map_0                  = 0xc,
2862         .usb2_oc_map_0                  = 0x10,
2863         .ss_port_map_0                  = 0x14,
2864         .oc_det_0                       = 0x18,
2865         .elpg_program_0                 = 0x1c,
2866         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
2867         .usb2_bchrg_otgpad0_ctl1_0      = 0x24,
2868         .usb2_bchrg_otgpad1_ctl0_0      = 0x28,
2869         .usb2_bchrg_otgpad1_ctl1_0      = 0x2c,
2870         .usb2_bchrg_otgpad2_ctl0_0      = 0x30,
2871         .usb2_bchrg_otgpad2_ctl1_0      = 0x34,
2872         .usb2_bchrg_bias_pad_0          = 0x38,
2873         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
2874         .iophy_pll_p0_ctl1_0            = 0x40,
2875         .iophy_pll_p0_ctl2_0            = 0x44,
2876         .iophy_pll_p0_ctl3_0            = 0x48,
2877         .iophy_pll_p0_ctl4_0            = 0x4c,
2878         .iophy_usb3_pad0_ctl1_0         = 0x50,
2879         .iophy_usb3_pad1_ctl1_0         = 0x54,
2880         .iophy_usb3_pad0_ctl2_0         = 0x58,
2881         .iophy_usb3_pad1_ctl2_0         = 0x5c,
2882         .iophy_usb3_pad0_ctl3_0         = 0x60,
2883         .iophy_usb3_pad1_ctl3_0         = 0x64,
2884         .iophy_usb3_pad0_ctl4_0         = 0x68,
2885         .iophy_usb3_pad1_ctl4_0         = 0x6c,
2886         .iophy_misc_pad_p0_ctl1_0       = 0x70,
2887         .iophy_misc_pad_p1_ctl1_0       = 0x74,
2888         .iophy_misc_pad_p0_ctl2_0       = 0x78,
2889         .iophy_misc_pad_p1_ctl2_0       = 0x7c,
2890         .iophy_misc_pad_p0_ctl3_0       = 0x80,
2891         .iophy_misc_pad_p1_ctl3_0       = 0x84,
2892         .iophy_misc_pad_p0_ctl4_0       = 0x88,
2893         .iophy_misc_pad_p1_ctl4_0       = 0x8c,
2894         .iophy_misc_pad_p0_ctl5_0       = 0x90,
2895         .iophy_misc_pad_p1_ctl5_0       = 0x94,
2896         .iophy_misc_pad_p0_ctl6_0       = 0x98,
2897         .iophy_misc_pad_p1_ctl6_0       = 0x9c,
2898         .usb2_otg_pad0_ctl0_0           = 0xa0,
2899         .usb2_otg_pad1_ctl0_0           = 0xa4,
2900         .usb2_otg_pad2_ctl0_0           = 0xa8,
2901         .usb2_otg_pad0_ctl1_0           = 0xac,
2902         .usb2_otg_pad1_ctl1_0           = 0xb0,
2903         .usb2_otg_pad2_ctl1_0           = 0xb4,
2904         .usb2_bias_pad_ctl0_0           = 0xb8,
2905         .usb2_bias_pad_ctl1_0           = 0xbc,
2906         .usb2_hsic_pad0_ctl0_0          = 0xc0,
2907         .usb2_hsic_pad1_ctl0_0          = 0xc4,
2908         .usb2_hsic_pad0_ctl1_0          = 0xc8,
2909         .usb2_hsic_pad1_ctl1_0          = 0xcc,
2910         .usb2_hsic_pad0_ctl2_0          = 0xd0,
2911         .usb2_hsic_pad1_ctl2_0          = 0xd4,
2912         .ulpi_link_trim_ctl0            = 0xd8,
2913         .ulpi_null_clk_trim_ctl0        = 0xdc,
2914         .hsic_strb_trim_ctl0            = 0xe0,
2915         .wake_ctl0                      = 0xe4,
2916         .pm_spare0                      = 0xe8,
2917         .iophy_misc_pad_p2_ctl1_0       = 0xec,
2918         .iophy_misc_pad_p3_ctl1_0       = 0xf0,
2919         .iophy_misc_pad_p4_ctl1_0       = 0xf4,
2920         .iophy_misc_pad_p2_ctl2_0       = 0xf8,
2921         .iophy_misc_pad_p3_ctl2_0       = 0xfc,
2922         .iophy_misc_pad_p4_ctl2_0       = 0x100,
2923         .iophy_misc_pad_p2_ctl3_0       = 0x104,
2924         .iophy_misc_pad_p3_ctl3_0       = 0x108,
2925         .iophy_misc_pad_p4_ctl3_0       = 0x10c,
2926         .iophy_misc_pad_p2_ctl4_0       = 0x110,
2927         .iophy_misc_pad_p3_ctl4_0       = 0x114,
2928         .iophy_misc_pad_p4_ctl4_0       = 0x118,
2929         .iophy_misc_pad_p2_ctl5_0       = 0x11c,
2930         .iophy_misc_pad_p3_ctl5_0       = 0x120,
2931         .iophy_misc_pad_p4_ctl5_0       = 0x124,
2932         .iophy_misc_pad_p2_ctl6_0       = 0x128,
2933         .iophy_misc_pad_p3_ctl6_0       = 0x12c,
2934         .iophy_misc_pad_p4_ctl6_0       = 0x130,
2935         .usb3_pad_mux_0                 = 0x134,
2936         .iophy_pll_s0_ctl1_0            = 0x138,
2937         .iophy_pll_s0_ctl2_0            = 0x13c,
2938         .iophy_pll_s0_ctl3_0            = 0x140,
2939         .iophy_pll_s0_ctl4_0            = 0x144,
2940         .iophy_misc_pad_s0_ctl1_0       = 0x148,
2941         .iophy_misc_pad_s0_ctl2_0       = 0x14c,
2942         .iophy_misc_pad_s0_ctl3_0       = 0x150,
2943         .iophy_misc_pad_s0_ctl4_0       = 0x154,
2944         .iophy_misc_pad_s0_ctl5_0       = 0x158,
2945         .iophy_misc_pad_s0_ctl6_0       = 0x15c,
2946 };
2947
2948 /* TODO: we have to refine error handling in tegra_xhci_probe() */
2949 static int tegra_xhci_probe(struct platform_device *pdev)
2950 {
2951         const struct hc_driver *driver;
2952         struct xhci_hcd *xhci;
2953         struct tegra_xhci_hcd *tegra;
2954         struct resource *res;
2955         struct usb_hcd  *hcd;
2956         u32 pmc_reg, val;
2957         int ret;
2958         int irq;
2959
2960         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
2961
2962         if (usb_disabled())
2963                 return -ENODEV;
2964
2965         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
2966         if (!tegra) {
2967                 dev_err(&pdev->dev, "memory alloc failed\n");
2968                 return -ENOMEM;
2969         }
2970         tegra->pdev = pdev;
2971         tegra->pdata = dev_get_platdata(&pdev->dev);
2972         tegra->bdata = tegra->pdata->bdata;
2973
2974         ret = tegra_xhci_request_mem_region(pdev, "padctl",
2975                         &tegra->padctl_base);
2976         if (ret) {
2977                 dev_err(&pdev->dev, "failed to map padctl\n");
2978                 return ret;
2979         }
2980
2981         ret = tegra_xhci_request_mem_region(pdev, "fpci", &tegra->fpci_base);
2982         if (ret) {
2983                 dev_err(&pdev->dev, "failed to map fpci\n");
2984                 return ret;
2985         }
2986
2987         ret = tegra_xhci_request_mem_region(pdev, "ipfs", &tegra->ipfs_base);
2988         if (ret) {
2989                 dev_err(&pdev->dev, "failed to map ipfs\n");
2990                 return ret;
2991         }
2992
2993         ret = tegra_xusb_partitions_clk_init(tegra);
2994         if (ret) {
2995                 dev_err(&pdev->dev,
2996                         "failed to initialize xusb partitions clocks\n");
2997                 return ret;
2998         }
2999
3000         /* Enable power rails to the PAD,VBUS
3001          * and pull-up voltage.Initialize the regulators
3002          */
3003         ret = tegra_xusb_regulator_init(tegra, pdev);
3004         if (ret) {
3005                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
3006                 goto err_deinit_xusb_partition_clk;
3007         }
3008
3009         /* Enable UTMIP, PLLU and PLLE */
3010         ret = tegra_usb2_clocks_init(tegra);
3011         if (ret) {
3012                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
3013                 goto err_deinit_tegra_xusb_regulator;
3014         }
3015
3016         /* tegra_unpowergate_partition also does partition reset deassert */
3017         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
3018         if (ret)
3019                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
3020
3021         /* tegra_unpowergate_partition also does partition reset deassert */
3022         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3023         if (ret)
3024                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
3025
3026         /* reset the pointer back to NULL. driver uses it */
3027         /* platform_set_drvdata(pdev, NULL); */
3028
3029         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "host");
3030         if (!res) {
3031                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
3032                 ret = -ENODEV;
3033                 goto err_deinit_usb2_clocks;
3034         }
3035         tegra->host_phy_base = res->start;
3036
3037         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
3038                                 res->start, resource_size(res));
3039         if (!tegra->host_phy_virt_base) {
3040                 dev_err(&pdev->dev, "error mapping host phy memory\n");
3041                 ret = -ENOMEM;
3042                 goto err_deinit_usb2_clocks;
3043         }
3044
3045         /* Setup IPFS access and BAR0 space */
3046         tegra_xhci_cfg(tegra);
3047
3048         val = readl(tegra->fpci_base + XUSB_CFG_0);
3049         tegra->device_id = (val >> 16) & 0xffff;
3050
3051         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
3052                 (XUSB_DEVICE_ID_T114 == tegra->device_id) ? "T114" : "T124+");
3053
3054         if (XUSB_DEVICE_ID_T114 == tegra->device_id) {
3055                 tegra->padregs = &t114_padregs_offset;
3056         } else if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
3057                 tegra->padregs = &t124_padregs_offset;
3058         } else {
3059                 dev_info(&pdev->dev, "XUSB device_id neither T114 nor T124!\n");
3060                 dev_info(&pdev->dev, "XUSB using T124 pad register offsets!\n");
3061                 tegra->padregs = &t124_padregs_offset;
3062         }
3063
3064         /* calculate rctrl_val and tctrl_val once at boot time */
3065         tegra_xhci_war_for_tctrl_rctrl(tegra);
3066
3067         /* Program the XUSB pads to take ownership of ports */
3068         tegra_xhci_padctl_portmap_and_caps(tegra);
3069
3070         /* Release XUSB wake logic state latching */
3071         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
3072         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
3073
3074         /* Deassert reset to XUSB host, ss, dev clocks */
3075         tegra_periph_reset_deassert(tegra->host_clk);
3076         tegra_periph_reset_deassert(tegra->ss_clk);
3077
3078         ret = init_firmware(tegra);
3079         if (ret < 0) {
3080                 dev_err(&pdev->dev, "failed to init firmware\n");
3081                 ret = -ENODEV;
3082                 goto err_deinit_usb2_clocks;
3083         }
3084
3085         ret = load_firmware(tegra, true /* do reset ARU */);
3086         if (ret < 0) {
3087                 dev_err(&pdev->dev, "failed to load firmware\n");
3088                 ret = -ENODEV;
3089                 goto err_deinit_firmware;
3090         }
3091
3092         device_init_wakeup(&pdev->dev, 1);
3093         driver = &tegra_plat_xhci_driver;
3094
3095         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
3096         if (!hcd) {
3097                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
3098                 ret = -ENOMEM;
3099                 goto err_deinit_firmware;
3100         }
3101
3102         ret = tegra_xhci_request_mem_region(pdev, "host", &hcd->regs);
3103         if (ret) {
3104                 dev_err(&pdev->dev, "failed to map host\n");
3105                 goto err_put_usb2_hcd;
3106         }
3107         hcd->rsrc_start = res->start;
3108         hcd->rsrc_len = resource_size(res);
3109
3110         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "host");
3111         if (!res) {
3112                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
3113                 ret = -ENODEV;
3114                 goto err_put_usb2_hcd;
3115         }
3116         irq = res->start;
3117         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
3118         if (ret) {
3119                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
3120                 goto err_put_usb2_hcd;
3121         }
3122
3123         /* USB 2.0 roothub is stored in the platform_device now. */
3124         hcd = dev_get_drvdata(&pdev->dev);
3125         xhci = hcd_to_xhci(hcd);
3126         tegra->xhci = xhci;
3127         platform_set_drvdata(pdev, tegra);
3128
3129         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
3130                                                 dev_name(&pdev->dev), hcd);
3131         if (!xhci->shared_hcd) {
3132                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
3133                 ret = -ENOMEM;
3134                 goto err_remove_usb2_hcd;
3135         }
3136
3137         /*
3138          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
3139          * is called by usb_add_hcd().
3140          */
3141         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
3142
3143         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
3144         if (ret) {
3145                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
3146                 goto err_put_usb3_hcd;
3147         }
3148
3149         device_init_wakeup(&hcd->self.root_hub->dev, 1);
3150         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
3151         spin_lock_init(&tegra->lock);
3152         mutex_init(&tegra->sync_lock);
3153         mutex_init(&tegra->mbox_lock);
3154
3155         /* do mailbox related initializations */
3156         tegra->mbox_owner = 0xffff;
3157         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
3158
3159         tegra_xhci_enable_fw_message(tegra);
3160
3161         /* do ss partition elpg exit related initialization */
3162         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
3163
3164         /* do host partition elpg exit related initialization */
3165         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
3166
3167         /* Register interrupt handler for SMI line to handle mailbox
3168          * interrupt from firmware
3169          */
3170         ret = tegra_xhci_request_irq(pdev, "host-smi", tegra_xhci_smi_irq,
3171                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
3172         if (ret != 0)
3173                 goto err_remove_usb3_hcd;
3174
3175         /* Register interrupt handler for PADCTRL line to
3176          * handle wake on connect irqs interrupt from
3177          * firmware
3178          */
3179         ret = tegra_xhci_request_irq(pdev, "padctl", tegra_xhci_padctl_irq,
3180                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
3181                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
3182         if (ret != 0)
3183                 goto err_remove_usb3_hcd;
3184
3185         ret = tegra_xhci_request_irq(pdev, "usb3", tegra_xhci_xusb_host_irq,
3186                         IRQF_SHARED | IRQF_TRIGGER_HIGH, "xusb_host_irq",
3187                         &tegra->usb3_irq);
3188         if (ret != 0)
3189                 goto err_remove_usb3_hcd;
3190
3191         tegra->ss_pwr_gated = false;
3192         tegra->host_pwr_gated = false;
3193         tegra->hc_in_elpg = false;
3194         tegra->hs_wake_event = false;
3195         tegra->host_resume_req = false;
3196         tegra->lp0_exit = false;
3197         tegra->dfe_ctle_ctx_saved = false;
3198
3199         /* reset wake event to NONE */
3200         pmc_reg = tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0);
3201         pmc_reg |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE);
3202         pmc_reg |= UTMIP_WAKE_VAL(1, WAKE_VAL_NONE);
3203         pmc_reg |= UTMIP_WAKE_VAL(2, WAKE_VAL_NONE);
3204         pmc_reg |= UTMIP_WAKE_VAL(3, WAKE_VAL_NONE);
3205         tegra_usb_pmc_reg_write(PMC_UTMIP_UHSIC_SLEEP_CFG_0, pmc_reg);
3206
3207         tegra_xhci_debug_read_pads(tegra);
3208         utmi_phy_pad_enable();
3209         utmi_phy_iddq_override(false);
3210
3211         tegra_pd_add_device(&pdev->dev);
3212
3213         return 0;
3214
3215 err_remove_usb3_hcd:
3216         usb_remove_hcd(xhci->shared_hcd);
3217 err_put_usb3_hcd:
3218         usb_put_hcd(xhci->shared_hcd);
3219 err_remove_usb2_hcd:
3220         kfree(tegra->xhci);
3221         usb_remove_hcd(hcd);
3222 err_put_usb2_hcd:
3223         usb_put_hcd(hcd);
3224 err_deinit_firmware:
3225         deinit_firmware(tegra);
3226 err_deinit_usb2_clocks:
3227         tegra_usb2_clocks_deinit(tegra);
3228 err_deinit_tegra_xusb_regulator:
3229         tegra_xusb_regulator_deinit(tegra);
3230 err_deinit_xusb_partition_clk:
3231         tegra_xusb_partitions_clk_deinit(tegra);
3232
3233         return ret;
3234 }
3235
3236 static int tegra_xhci_remove(struct platform_device *pdev)
3237 {
3238         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3239         struct xhci_hcd *xhci = NULL;
3240         struct usb_hcd *hcd = NULL;
3241
3242         if (tegra == NULL)
3243                 return -EINVAL;
3244
3245         xhci = tegra->xhci;
3246         hcd = xhci_to_hcd(xhci);
3247
3248         devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
3249         devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
3250         devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
3251         usb_remove_hcd(xhci->shared_hcd);
3252         usb_put_hcd(xhci->shared_hcd);
3253         usb_remove_hcd(hcd);
3254         usb_put_hcd(hcd);
3255         kfree(xhci);
3256
3257         deinit_firmware(tegra);
3258         tegra_xusb_regulator_deinit(tegra);
3259         tegra_usb2_clocks_deinit(tegra);
3260         if (!tegra->hc_in_elpg)
3261                 tegra_xusb_partitions_clk_deinit(tegra);
3262         utmi_phy_pad_disable();
3263         utmi_phy_iddq_override(true);
3264
3265         return 0;
3266 }
3267
3268 static void tegra_xhci_shutdown(struct platform_device *pdev)
3269 {
3270         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3271         struct xhci_hcd *xhci = NULL;
3272         struct usb_hcd *hcd = NULL;
3273
3274         if (tegra == NULL)
3275                 return;
3276
3277         if (tegra->hc_in_elpg) {
3278                 mutex_lock(&tegra->sync_lock);
3279                 tegra_xhci_host_partition_elpg_exit(tegra);
3280                 mutex_unlock(&tegra->sync_lock);
3281         }
3282         xhci = tegra->xhci;
3283         hcd = xhci_to_hcd(xhci);
3284         xhci_shutdown(hcd);
3285 }
3286
3287 static struct platform_driver tegra_xhci_driver = {
3288         .probe  = tegra_xhci_probe,
3289         .remove = tegra_xhci_remove,
3290         .shutdown = tegra_xhci_shutdown,
3291 #ifdef CONFIG_PM
3292         .suspend = tegra_xhci_suspend,
3293         .resume  = tegra_xhci_resume,
3294 #endif
3295         .driver = {
3296                 .name = "tegra-xhci",
3297         },
3298 };
3299 MODULE_ALIAS("platform:tegra-xhci");
3300
3301 int tegra_xhci_register_plat(void)
3302 {
3303         return platform_driver_register(&tegra_xhci_driver);
3304 }
3305
3306 void tegra_xhci_unregister_plat(void)
3307 {
3308         platform_driver_unregister(&tegra_xhci_driver);
3309 }