usb: xhci: tegra: remove power saving change
[linux-3.10.git] / drivers / usb / host / xhci-tegra.c
1 /*
2  * xhci-tegra.c - Nvidia xHCI host controller driver
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/clk.h>
24 #include <linux/ioport.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irq.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/uaccess.h>
30 #include <linux/gpio.h>
31
32 #include <mach/powergate.h>
33 #include <mach/clk.h>
34 #include <mach/tegra_usb_pad_ctrl.h>
35 #include <mach/tegra_usb_pmc.h>
36 #include <mach/pm_domains.h>
37 #include <mach/mc.h>
38 #include <mach/xusb.h>
39
40 #include "../../../arch/arm/mach-tegra/iomap.h" /* HACK -- remove */
41 #include "xhci-tegra.h"
42 #include "xhci.h"
43
44 /* macros */
45 #define PAGE_SELECT_MASK                        0xFFFFFE00
46 #define PAGE_SELECT_SHIFT                       9
47 #define PAGE_OFFSET_MASK                        0x000001FF
48 #define CSB_PAGE_SELECT(_addr)                                          \
49         ({                                                              \
50                 typecheck(u32, _addr);                                  \
51                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
52         })
53 #define CSB_PAGE_OFFSET(_addr)                                          \
54         ({                                                              \
55                 typecheck(u32, _addr);                                  \
56                 (_addr & PAGE_OFFSET_MASK);                             \
57         })
58
59 /* PMC register definition */
60 #define PMC_PORT_UTMIP_P0               0
61 #define PMC_PORT_UTMIP_P1               1
62 #define PMC_PORT_UTMIP_P2               2
63 #define PMC_PORT_UHSIC_P0               3
64 #define PMC_PORT_NUM                    4
65
66 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
67 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
68 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
69
70 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
71
72 /* private data types */
73 /* command requests from the firmware */
74 enum MBOX_CMD_TYPE {
75         MBOX_CMD_MSG_ENABLED = 1,
76         MBOX_CMD_INC_FALC_CLOCK,
77         MBOX_CMD_DEC_FALC_CLOCK,
78         MBOX_CMD_INC_SSPI_CLOCK,
79         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
80         MBOX_CMD_SET_BW,
81         MBOX_CMD_SET_SS_PWR_GATING,
82         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
83         MBOX_CMD_SAVE_DFE_CTLE_CTX,
84
85         /* needs to be the last cmd */
86         MBOX_CMD_MAX,
87
88         /* resp msg to ack above commands */
89         MBOX_CMD_ACK = 128,
90         MBOX_CMD_NACK
91 };
92
93 /* Usb3 Firmware Cfg Table */
94 struct cfgtbl {
95         u32 boot_loadaddr_in_imem;
96         u32 boot_codedfi_offset;
97         u32 boot_codetag;
98         u32 boot_codesize;
99
100         /* Physical memory reserved by Bootloader/BIOS */
101         u32 phys_memaddr;
102         u16 reqphys_memsize;
103         u16 alloc_phys_memsize;
104
105         /* .rodata section */
106         u32 rodata_img_offset;
107         u32 rodata_section_start;
108         u32 rodata_section_end;
109         u32 main_fnaddr;
110
111         u32 fwimg_cksum;
112         u32 fwimg_created_time;
113
114         /* Fields that get filled by linker during linking phase
115          * or initialized in the FW code.
116          */
117         u32 imem_resident_start;
118         u32 imem_resident_end;
119         u32 idirect_start;
120         u32 idirect_end;
121         u32 l2_imem_start;
122         u32 l2_imem_end;
123         u32 version_id;
124         u8 init_ddirect;
125         u8 reserved[3];
126         u32 phys_addr_log_buffer;
127         u32 total_log_entries;
128         u32 dequeue_ptr;
129
130         /*      Below two dummy variables are used to replace
131          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
132          *      retain the size of struct _CFG_TBL used by other AP/Module.
133          */
134         u32 dummy_var1;
135         u32 dummy_var2;
136
137         /* fwimg_len */
138         u32 fwimg_len;
139         u8 magic[8];
140         u32 SS_low_power_entry_timeout;
141         u8 padding[140]; /* padding bytes to makeup 256-bytes cfgtbl */
142 };
143
144 struct xusb_save_regs {
145         u32 msi_bar_sz;
146         u32 msi_axi_barst;
147         u32 msi_fpci_barst;
148         u32 msi_vec0;
149         u32 msi_en_vec0;
150         u32 fpci_error_masks;
151         u32 intr_mask;
152         u32 ipfs_intr_enable;
153         u32 ufpci_config;
154         u32 clkgate_hysteresis;
155         u32 xusb_host_mccif_fifo_cntrl;
156
157         /* PG does not mention below */
158         u32 hs_pls;
159         u32 fs_pls;
160         u32 hs_fs_speed;
161         u32 hs_fs_pp;
162         u32 cfg_aru;
163         u32 cfg_order;
164         u32 cfg_fladj;
165         u32 cfg_sid;
166         /* DFE and CTLE */
167         u32 tap1_val[2];
168         u32 amp_val[2];
169         u32 ctle_z_val[2];
170         u32 ctle_g_val[2];
171 };
172
173 struct tegra_xhci_firmware {
174         void *data; /* kernel virtual address */
175         size_t size; /* firmware size */
176         dma_addr_t dma; /* dma address for controller */
177 };
178
179 /* structure to hold the offsets of padctl registers */
180 struct tegra_xusb_padctl_regs {
181         u16 boot_media_0;
182         u16 usb2_pad_mux_0;
183         u16 usb2_port_cap_0;
184         u16 snps_oc_map_0;
185         u16 usb2_oc_map_0;
186         u16 ss_port_map_0;
187         u16 oc_det_0;
188         u16 elpg_program_0;
189         u16 usb2_bchrg_otgpad0_ctl0_0;
190         u16 usb2_bchrg_otgpad0_ctl1_0;
191         u16 usb2_bchrg_otgpad1_ctl0_0;
192         u16 usb2_bchrg_otgpad1_ctl1_0;
193         u16 usb2_bchrg_otgpad2_ctl0_0;
194         u16 usb2_bchrg_otgpad2_ctl1_0;
195         u16 usb2_bchrg_bias_pad_0;
196         u16 usb2_bchrg_tdcd_dbnc_timer_0;
197         u16 iophy_pll_p0_ctl1_0;
198         u16 iophy_pll_p0_ctl2_0;
199         u16 iophy_pll_p0_ctl3_0;
200         u16 iophy_pll_p0_ctl4_0;
201         u16 iophy_usb3_pad0_ctl1_0;
202         u16 iophy_usb3_pad1_ctl1_0;
203         u16 iophy_usb3_pad0_ctl2_0;
204         u16 iophy_usb3_pad1_ctl2_0;
205         u16 iophy_usb3_pad0_ctl3_0;
206         u16 iophy_usb3_pad1_ctl3_0;
207         u16 iophy_usb3_pad0_ctl4_0;
208         u16 iophy_usb3_pad1_ctl4_0;
209         u16 iophy_misc_pad_p0_ctl1_0;
210         u16 iophy_misc_pad_p1_ctl1_0;
211         u16 iophy_misc_pad_p0_ctl2_0;
212         u16 iophy_misc_pad_p1_ctl2_0;
213         u16 iophy_misc_pad_p0_ctl3_0;
214         u16 iophy_misc_pad_p1_ctl3_0;
215         u16 iophy_misc_pad_p0_ctl4_0;
216         u16 iophy_misc_pad_p1_ctl4_0;
217         u16 iophy_misc_pad_p0_ctl5_0;
218         u16 iophy_misc_pad_p1_ctl5_0;
219         u16 iophy_misc_pad_p0_ctl6_0;
220         u16 iophy_misc_pad_p1_ctl6_0;
221         u16 usb2_otg_pad0_ctl0_0;
222         u16 usb2_otg_pad1_ctl0_0;
223         u16 usb2_otg_pad2_ctl0_0;
224         u16 usb2_otg_pad0_ctl1_0;
225         u16 usb2_otg_pad1_ctl1_0;
226         u16 usb2_otg_pad2_ctl1_0;
227         u16 usb2_bias_pad_ctl0_0;
228         u16 usb2_bias_pad_ctl1_0;
229         u16 usb2_hsic_pad0_ctl0_0;
230         u16 usb2_hsic_pad1_ctl0_0;
231         u16 usb2_hsic_pad0_ctl1_0;
232         u16 usb2_hsic_pad1_ctl1_0;
233         u16 usb2_hsic_pad0_ctl2_0;
234         u16 usb2_hsic_pad1_ctl2_0;
235         u16 ulpi_link_trim_ctl0;
236         u16 ulpi_null_clk_trim_ctl0;
237         u16 hsic_strb_trim_ctl0;
238         u16 wake_ctl0;
239         u16 pm_spare0;
240         u16 iophy_misc_pad_p2_ctl1_0;
241         u16 iophy_misc_pad_p3_ctl1_0;
242         u16 iophy_misc_pad_p4_ctl1_0;
243         u16 iophy_misc_pad_p2_ctl2_0;
244         u16 iophy_misc_pad_p3_ctl2_0;
245         u16 iophy_misc_pad_p4_ctl2_0;
246         u16 iophy_misc_pad_p2_ctl3_0;
247         u16 iophy_misc_pad_p3_ctl3_0;
248         u16 iophy_misc_pad_p4_ctl3_0;
249         u16 iophy_misc_pad_p2_ctl4_0;
250         u16 iophy_misc_pad_p3_ctl4_0;
251         u16 iophy_misc_pad_p4_ctl4_0;
252         u16 iophy_misc_pad_p2_ctl5_0;
253         u16 iophy_misc_pad_p3_ctl5_0;
254         u16 iophy_misc_pad_p4_ctl5_0;
255         u16 iophy_misc_pad_p2_ctl6_0;
256         u16 iophy_misc_pad_p3_ctl6_0;
257         u16 iophy_misc_pad_p4_ctl6_0;
258         u16 usb3_pad_mux_0;
259         u16 iophy_pll_s0_ctl1_0;
260         u16 iophy_pll_s0_ctl2_0;
261         u16 iophy_pll_s0_ctl3_0;
262         u16 iophy_pll_s0_ctl4_0;
263         u16 iophy_misc_pad_s0_ctl1_0;
264         u16 iophy_misc_pad_s0_ctl2_0;
265         u16 iophy_misc_pad_s0_ctl3_0;
266         u16 iophy_misc_pad_s0_ctl4_0;
267         u16 iophy_misc_pad_s0_ctl5_0;
268         u16 iophy_misc_pad_s0_ctl6_0;
269 };
270
271 struct tegra_xhci_hcd {
272         struct platform_device *pdev;
273         struct xhci_hcd *xhci;
274         u16 device_id;
275
276         spinlock_t lock;
277         struct mutex sync_lock;
278
279         int smi_irq;
280         int padctl_irq;
281         int usb3_irq;
282
283         bool ss_wake_event;
284         bool ss_pwr_gated;
285         bool host_pwr_gated;
286         bool hs_wake_event;
287         bool host_resume_req;
288         bool lp0_exit;
289         bool dfe_ctle_ctx_saved;
290         unsigned long last_jiffies;
291         unsigned long host_phy_base;
292         void __iomem *host_phy_virt_base;
293
294         void __iomem *padctl_base;
295         void __iomem *fpci_base;
296         void __iomem *ipfs_base;
297
298         struct tegra_xusb_platform_data *pdata;
299         struct tegra_xusb_board_data *bdata;
300         struct tegra_xusb_padctl_regs *padregs;
301
302         /* mailbox variables */
303         struct mutex mbox_lock;
304         u32 mbox_owner;
305         u32 cmd_type;
306         u32 cmd_data;
307
308         struct regulator *xusb_vbus_reg;
309         struct regulator *xusb_avddio_usb3_reg;
310         struct regulator *xusb_hvdd_usb3_reg;
311         struct regulator *xusb_avdd_usb3_pll_reg;
312
313         struct work_struct mbox_work;
314         struct work_struct ss_elpg_exit_work;
315         struct work_struct host_elpg_exit_work;
316
317         struct clk *host_clk;
318         struct clk *ss_clk;
319
320         /* XUSB Falcon SuperSpeed Clock */
321         struct clk *falc_clk;
322
323         /* EMC Clock */
324         struct clk *emc_clk;
325         /* XUSB SS PI Clock */
326         struct clk *ss_src_clk;
327         /* PLLE Clock */
328         struct clk *plle_clk;
329         struct clk *pll_u_480M;
330         struct clk *clk_m;
331         /* refPLLE clk */
332         struct clk *pll_re_vco_clk;
333         /*
334          * XUSB/IPFS specific registers these need to be saved/restored in
335          * addition to spec defined registers
336          */
337         struct xusb_save_regs sregs;
338         bool usb2_rh_suspend;
339         bool usb3_rh_suspend;
340         bool hc_in_elpg;
341
342         unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
343         /* firmware loading related */
344         struct tegra_xhci_firmware firmware;
345 };
346
347 static struct tegra_usb_pmc_data pmc_data;
348
349 /* functions */
350 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
351 {
352         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
353 }
354
355 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
356 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
357 {
358         WARN_ON(tegra->sync_lock.owner != current);
359 }
360 #else
361 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
362 #endif
363
364 static void tegra_xhci_setup_gpio_for_ss_lane(struct tegra_xhci_hcd *tegra)
365 {
366         int err = 0;
367
368         if (!tegra->bdata->gpio_controls_muxed_ss_lanes)
369                 return;
370
371         if (tegra->bdata->lane_owner & BIT(0)) {
372                 /* USB3_SS port1 is using SATA lane so set (MUX_SATA)
373                  * GPIO P11 to '0'
374                  */
375                 err = gpio_request((tegra->bdata->gpio_ss1_sata & 0xffff),
376                         "gpio_ss1_sata");
377                 if (err < 0)
378                         pr_err("%s: gpio_ss1_sata gpio_request failed %d\n",
379                                 __func__, err);
380                 err = gpio_direction_output((tegra->bdata->gpio_ss1_sata
381                         & 0xffff), 1);
382                 if (err < 0)
383                         pr_err("%s: gpio_ss1_sata gpio_direction failed %d\n",
384                                 __func__, err);
385                 __gpio_set_value((tegra->bdata->gpio_ss1_sata & 0xffff),
386                                 ((tegra->bdata->gpio_ss1_sata >> 16)));
387         }
388 }
389
390 static void debug_print_portsc(struct xhci_hcd *xhci)
391 {
392         __le32 __iomem *addr;
393         int i;
394         int ports;
395
396         ports = HCS_MAX_PORTS(xhci->hcs_params1);
397         addr = &xhci->op_regs->port_status_base;
398         for (i = 0; i < ports; i++) {
399                 xhci_dbg(xhci, "%p port %d status reg = 0x%x\n",
400                                 addr, i, (unsigned int) xhci_readl(xhci, addr));
401                 addr += NUM_PORT_REGS;
402         }
403 }
404
405 static void update_speed(struct tegra_xhci_hcd *tegra, u8 port)
406 {
407         struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
408         u32 portsc;
409
410         portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port +
411                                                 BAR0_XHCI_OP_PORTSC_UTMIP_0));
412         if (DEV_FULLSPEED(portsc))
413                 pmc_data.port_speed = USB_PMC_PORT_SPEED_FULL;
414         else if (DEV_HIGHSPEED(portsc))
415                 pmc_data.port_speed = USB_PMC_PORT_SPEED_HIGH;
416         else if (DEV_LOWSPEED(portsc))
417                 pmc_data.port_speed = USB_PMC_PORT_SPEED_LOW;
418         else if (DEV_SUPERSPEED(portsc))
419                 pmc_data.port_speed = USB_PMC_PORT_SPEED_SUPER;
420         else
421                 pmc_data.port_speed = USB_PMC_PORT_SPEED_UNKNOWN;
422 }
423
424 static void setup_wake_detect(bool setup_wake)
425 {
426         if (setup_wake)
427                 pmc_data.pmc_ops->setup_pmc_wake_detect(&pmc_data);
428         else
429                 pmc_data.pmc_ops->disable_pmc_bus_ctrl(&pmc_data, 0);
430 }
431
432 static void pmc_init(struct tegra_xhci_hcd *tegra, bool setup_wake)
433 {
434         u32 portmap = tegra->bdata->portmap;
435
436         pmc_data.controller_type = TEGRA_USB_3_0;
437         if (portmap & TEGRA_XUSB_USB2_P0) {
438                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 0) & 0xf;
439                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
440                 update_speed(tegra, pmc_data.instance);
441                 tegra_usb_pmc_init(&pmc_data);
442                 setup_wake_detect(setup_wake);
443         }
444         if (portmap & TEGRA_XUSB_USB2_P1) {
445                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 4) & 0xf;
446                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
447                 update_speed(tegra, pmc_data.instance);
448                 tegra_usb_pmc_init(&pmc_data);
449                 setup_wake_detect(setup_wake);
450         }
451         if (portmap & TEGRA_XUSB_USB2_P2) {
452                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 8) & 0xf;
453                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
454                 update_speed(tegra, pmc_data.instance);
455                 tegra_usb_pmc_init(&pmc_data);
456                 setup_wake_detect(setup_wake);
457         }
458         if (portmap & TEGRA_XUSB_HSIC_P0) {
459                 pmc_data.instance = PMC_PORT_UHSIC_P0;
460                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_HSIC;
461                 update_speed(tegra, pmc_data.instance);
462                 tegra_usb_pmc_init(&pmc_data);
463                 setup_wake_detect(setup_wake);
464         }
465 }
466
467 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
468 {
469         void __iomem *fpci_base = tegra->fpci_base;
470         struct platform_device *pdev = tegra->pdev;
471         u32 input_addr;
472         u32 data;
473         u32 csb_page_select;
474
475         /* to select the appropriate CSB page to write to */
476         csb_page_select = CSB_PAGE_SELECT(addr);
477
478         dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
479                         csb_page_select);
480
481         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
482
483         /* selects the appropriate offset in the page to read from */
484         input_addr = CSB_PAGE_OFFSET(addr);
485         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
486
487         dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
488                         input_addr, data);
489         return data;
490 }
491
492 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
493 {
494         void __iomem *fpci_base = tegra->fpci_base;
495         struct platform_device *pdev = tegra->pdev;
496         u32 input_addr;
497         u32 csb_page_select;
498
499         /* to select the appropriate CSB page to write to */
500         csb_page_select = CSB_PAGE_SELECT(addr);
501
502         dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
503                         csb_page_select);
504
505         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
506
507         /* selects the appropriate offset in the page to write to */
508         input_addr = CSB_PAGE_OFFSET(addr);
509         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
510
511         dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
512                         input_addr, data);
513 }
514
515 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
516 {
517         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
518         struct xhci_hcd *xhci = tegra->xhci;
519         u32 reg;
520
521         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
522         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
523         xhci_info(xhci, " PAD MUX = %x\n", reg);
524         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
525         xhci_info(xhci, " PORT CAP = %x\n", reg);
526         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
527         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
528         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
529         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
530         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
531         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
532         reg = readl(tegra->padctl_base + padregs->oc_det_0);
533         xhci_info(xhci, " OC DET 0= %x\n", reg);
534         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad0_ctl2_0);
535         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
536         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad1_ctl2_0);
537         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
538         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl0_0);
539         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
540         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl0_0);
541         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
542         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl1_0);
543         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
544         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl1_0);
545         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
546         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
547         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
548         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad0_ctl0_0);
549         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
550         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad1_ctl0_0);
551         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
552         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
553 }
554
555 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
556 {
557         u32 reg;
558
559         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
560         reg |= IPFS_EN_FPCI;
561         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
562         udelay(10);
563
564         /* Program Bar0 Space */
565         reg = readl(tegra->fpci_base + XUSB_CFG_4);
566         reg |= tegra->host_phy_base;
567         writel(reg, tegra->fpci_base + XUSB_CFG_4);
568         usleep_range(100, 200);
569
570         /* Enable Bus Master */
571         reg = readl(tegra->fpci_base + XUSB_CFG_1);
572         reg |= 0x7;
573         writel(reg, tegra->fpci_base + XUSB_CFG_1);
574
575         /* Set intr mask to enable intr assertion */
576         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
577         reg |= IPFS_IP_INT_MASK;
578         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
579
580         /* Set hysteris to 0x80 */
581         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
582 }
583
584 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
585                 struct platform_device *pdev)
586 {
587         int err = 0;
588
589         tegra->xusb_hvdd_usb3_reg =
590                         devm_regulator_get(&pdev->dev, "hvdd_usb");
591         if (IS_ERR(tegra->xusb_hvdd_usb3_reg)) {
592                 dev_err(&pdev->dev, "hvdd_usb: regulator not found: %ld."
593                         , PTR_ERR(tegra->xusb_hvdd_usb3_reg));
594                 err = PTR_ERR(tegra->xusb_hvdd_usb3_reg);
595                 goto err_null_regulator;
596         } else {
597                 err = regulator_enable(tegra->xusb_hvdd_usb3_reg);
598                 if (err < 0) {
599                         dev_err(&pdev->dev,
600                                 "hvdd_usb3: regulator enable failed:%d\n", err);
601                         goto err_null_regulator;
602                 }
603         }
604
605         tegra->xusb_vbus_reg = devm_regulator_get(&pdev->dev, "usb_vbus");
606         if (IS_ERR(tegra->xusb_vbus_reg)) {
607                 dev_err(&pdev->dev, "vbus regulator not found: %ld."
608                         , PTR_ERR(tegra->xusb_vbus_reg));
609                 err = PTR_ERR(tegra->xusb_vbus_reg);
610                 goto err_put_hvdd_usb3;
611         } else {
612                 err = regulator_enable(tegra->xusb_vbus_reg);
613                 if (err < 0) {
614                         dev_err(&pdev->dev,
615                                 "vbus: regulator enable failed:%d\n", err);
616                         goto err_put_hvdd_usb3;
617                 }
618         }
619
620         tegra->xusb_avdd_usb3_pll_reg =
621                 devm_regulator_get(&pdev->dev, "avdd_usb_pll");
622         if (IS_ERR(tegra->xusb_avdd_usb3_pll_reg)) {
623                 dev_err(&pdev->dev, "avdd_usb3_pll regulator not found: %ld."
624                         , PTR_ERR(tegra->xusb_avdd_usb3_pll_reg));
625                 err = PTR_ERR(tegra->xusb_avdd_usb3_pll_reg);
626                 goto err_put_vbus;
627         } else {
628                 err = regulator_enable(tegra->xusb_avdd_usb3_pll_reg);
629                 if (err < 0) {
630                         dev_err(&pdev->dev,
631                         "avdd_usb3_pll: regulator enable failed:%d\n", err);
632                         goto err_put_vbus;
633                 }
634         }
635
636         tegra->xusb_avddio_usb3_reg =
637                         devm_regulator_get(&pdev->dev, "avddio_usb");
638         if (IS_ERR(tegra->xusb_avddio_usb3_reg)) {
639                 dev_err(&pdev->dev, "avddio_usb3: regulator not found: %ld."
640                         , PTR_ERR(tegra->xusb_avddio_usb3_reg));
641                 err = PTR_ERR(tegra->xusb_avddio_usb3_reg);
642                 goto err_put_usb3_pll;
643         } else {
644                 err = regulator_enable(tegra->xusb_avddio_usb3_reg);
645                 if (err < 0) {
646                         dev_err(&pdev->dev,
647                         "avddio_usb3: regulator enable failed:%d\n", err);
648                         goto err_put_usb3_pll;
649                 }
650         }
651
652         return err;
653
654 err_put_usb3_pll:
655         regulator_disable(tegra->xusb_avdd_usb3_pll_reg);
656 err_put_vbus:
657         regulator_disable(tegra->xusb_vbus_reg);
658 err_put_hvdd_usb3:
659         regulator_disable(tegra->xusb_hvdd_usb3_reg);
660 err_null_regulator:
661         tegra->xusb_vbus_reg = NULL;
662         tegra->xusb_avddio_usb3_reg = NULL;
663         tegra->xusb_hvdd_usb3_reg = NULL;
664         tegra->xusb_avdd_usb3_pll_reg = NULL;
665         return err;
666 }
667
668 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
669 {
670         regulator_disable(tegra->xusb_avddio_usb3_reg);
671         regulator_disable(tegra->xusb_avdd_usb3_pll_reg);
672         regulator_disable(tegra->xusb_vbus_reg);
673         regulator_disable(tegra->xusb_hvdd_usb3_reg);
674
675         tegra->xusb_avddio_usb3_reg = NULL;
676         tegra->xusb_avdd_usb3_pll_reg = NULL;
677         tegra->xusb_vbus_reg = NULL;
678         tegra->xusb_hvdd_usb3_reg = NULL;
679 }
680
681 /*
682  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
683  * are under hardware control
684  */
685 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
686 {
687         struct platform_device *pdev = tegra->pdev;
688         int err = 0;
689
690         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
691         if (IS_ERR(tegra->plle_clk)) {
692                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
693                 err = PTR_ERR(tegra->plle_clk);
694                 return err;
695         }
696         err = clk_enable(tegra->plle_clk);
697         if (err) {
698                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
699                         __func__);
700                 return err;
701         }
702
703         return err;
704 }
705
706 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
707 {
708         clk_disable(tegra->plle_clk);
709         tegra->plle_clk = NULL;
710 }
711
712 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
713 {
714         struct platform_device *pdev = tegra->pdev;
715         int err = 0;
716
717         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
718         if (IS_ERR(tegra->emc_clk)) {
719                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
720                 return PTR_ERR(tegra->emc_clk);
721         }
722
723         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
724                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
725                 if (IS_ERR(tegra->pll_re_vco_clk)) {
726                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
727                         err = PTR_ERR(tegra->pll_re_vco_clk);
728                         goto get_pll_re_vco_clk_failed;
729                 }
730         }
731
732         /* get the clock handle of 120MHz clock source */
733         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
734         if (IS_ERR(tegra->pll_u_480M)) {
735                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
736                 err = PTR_ERR(tegra->pll_u_480M);
737                 goto get_pll_u_480M_failed;
738         }
739
740         /* get the clock handle of 12MHz clock source */
741         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
742         if (IS_ERR(tegra->clk_m)) {
743                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
744                 err = PTR_ERR(tegra->clk_m);
745                 goto clk_get_clk_m_failed;
746         }
747
748         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
749         if (IS_ERR(tegra->ss_src_clk)) {
750                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
751                 err = PTR_ERR(tegra->ss_src_clk);
752                 tegra->ss_src_clk = NULL;
753                 goto get_ss_src_clk_failed;
754         }
755
756         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
757         if (IS_ERR(tegra->host_clk)) {
758                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
759                 err = PTR_ERR(tegra->host_clk);
760                 tegra->host_clk = NULL;
761                 goto get_host_clk_failed;
762         }
763
764         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
765         if (IS_ERR(tegra->ss_clk)) {
766                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
767                 err = PTR_ERR(tegra->ss_clk);
768                 tegra->ss_clk = NULL;
769                 goto get_ss_clk_failed;
770         }
771
772         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
773                 err = clk_enable(tegra->pll_re_vco_clk);
774                 if (err) {
775                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
776                         goto enable_pll_re_vco_clk_failed;
777                 }
778         }
779         /* enable ss clock */
780         err = clk_enable(tegra->host_clk);
781         if (err) {
782                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
783                 goto enable_host_clk_failed;
784         }
785
786         err = clk_enable(tegra->ss_clk);
787         if (err) {
788                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
789                 goto eanble_ss_clk_failed;
790         }
791
792         err = clk_enable(tegra->emc_clk);
793         if (err) {
794                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
795                 goto eanble_emc_clk_failed;
796         }
797
798         return 0;
799
800 eanble_emc_clk_failed:
801         clk_disable(tegra->ss_clk);
802
803 eanble_ss_clk_failed:
804         clk_disable(tegra->host_clk);
805
806 enable_host_clk_failed:
807         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
808                 clk_disable(tegra->pll_re_vco_clk);
809
810 enable_pll_re_vco_clk_failed:
811         tegra->ss_clk = NULL;
812
813 get_ss_clk_failed:
814         tegra->host_clk = NULL;
815
816 get_host_clk_failed:
817         tegra->ss_src_clk = NULL;
818
819 get_ss_src_clk_failed:
820         tegra->clk_m = NULL;
821
822 clk_get_clk_m_failed:
823         tegra->pll_u_480M = NULL;
824
825 get_pll_u_480M_failed:
826         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
827                 tegra->pll_re_vco_clk = NULL;
828
829 get_pll_re_vco_clk_failed:
830         tegra->emc_clk = NULL;
831
832         return err;
833 }
834
835 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
836 {
837         clk_disable(tegra->ss_clk);
838         clk_disable(tegra->host_clk);
839         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
840                 clk_disable(tegra->pll_re_vco_clk);
841         tegra->ss_clk = NULL;
842         tegra->host_clk = NULL;
843         tegra->ss_src_clk = NULL;
844         tegra->clk_m = NULL;
845         tegra->pll_u_480M = NULL;
846         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
847                 tegra->pll_re_vco_clk = NULL;
848 }
849
850 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
851         bool enable)
852 {
853         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
854         u32 reg;
855
856         /* Issue is only applicable for T114 */
857         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
858                 return;
859
860         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
861                 reg = readl(tegra->padctl_base +
862                         padregs->iophy_misc_pad_p0_ctl3_0);
863                 if (enable) {
864                         reg &= ~RX_IDLE_MODE;
865                         reg |= RX_IDLE_MODE_OVRD;
866                 } else {
867                         reg |= RX_IDLE_MODE;
868                         reg &= ~RX_IDLE_MODE_OVRD;
869                 }
870                 writel(reg, tegra->padctl_base +
871                         padregs->iophy_misc_pad_p0_ctl3_0);
872         }
873
874         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
875                 reg = readl(tegra->padctl_base +
876                         padregs->iophy_misc_pad_p1_ctl3_0);
877                 if (enable) {
878                         reg &= ~RX_IDLE_MODE;
879                         reg |= RX_IDLE_MODE_OVRD;
880                 } else {
881                         reg |= RX_IDLE_MODE;
882                         reg &= ~RX_IDLE_MODE_OVRD;
883                 }
884                 writel(reg, tegra->padctl_base +
885                         padregs->iophy_misc_pad_p1_ctl3_0);
886
887                 /* SATA lane also if USB3_SS port1 mapped to it */
888                 if (XUSB_DEVICE_ID_T124 == tegra->device_id &&
889                                 tegra->bdata->lane_owner & BIT(0)) {
890                         reg = readl(tegra->padctl_base +
891                                 padregs->iophy_misc_pad_s0_ctl3_0);
892                         if (enable) {
893                                 reg &= ~RX_IDLE_MODE;
894                                 reg |= RX_IDLE_MODE_OVRD;
895                         } else {
896                                 reg |= RX_IDLE_MODE;
897                                 reg &= ~RX_IDLE_MODE_OVRD;
898                         }
899                         writel(reg, tegra->padctl_base +
900                                 padregs->iophy_misc_pad_s0_ctl3_0);
901                 }
902         }
903 }
904
905 /* Enable ss clk, host clk, falcon clk,
906  * fs clk, dev clk, plle and refplle
907  */
908
909 static int
910 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
911                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
912 {
913         int ret = 0;
914         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
915         int fw_req_rate = rate, cur_rate;
916
917         /* Do not handle clock change as needed for HS disconnect issue */
918         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
919                 *sw_resp = fw_req_rate | (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
920                 return ret;
921         }
922
923         /* frequency request from firmware is in KHz.
924          * Convert it to MHz
925          */
926
927         /* get current rate of clock */
928         cur_rate = clk_get_rate(clk_handle);
929         cur_rate /= 1000;
930
931         if (fw_req_rate == cur_rate) {
932                 cmd_ack = MBOX_CMD_ACK;
933                 *sw_resp = fw_req_rate;
934         } else {
935
936                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
937                         /* Change SS clock source to CLK_M at 12MHz */
938                         clk_set_parent(clk_handle, tegra->clk_m);
939                         clk_set_rate(clk_handle, fw_req_rate * 1000);
940
941                         /* save leakage power when SS freq is being decreased */
942                         tegra_xhci_rx_idle_mode_override(tegra, true);
943                 } else if (clk_handle == tegra->ss_src_clk &&
944                                 fw_req_rate == 120000) {
945                         /* Change SS clock source to HSIC_480 at 120MHz */
946                         clk_set_rate(clk_handle,  3000 * 1000);
947                         clk_set_parent(clk_handle, tegra->pll_u_480M);
948
949                         /* clear ovrd bits when SS freq is being increased */
950                         tegra_xhci_rx_idle_mode_override(tegra, false);
951                 }
952
953                 *sw_resp = clk_get_rate(clk_handle);
954                 *sw_resp /= 1000;
955
956                 if (*sw_resp != fw_req_rate) {
957                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
958                                 cur_rate, fw_req_rate);
959                         cmd_ack = MBOX_CMD_NACK;
960                 }
961         }
962         *sw_resp |= (cmd_ack << MBOX_CMD_SHIFT);
963         return ret;
964 }
965
966 static void tegra_xhci_save_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
967         u8 port)
968 {
969         struct xhci_hcd *xhci = tegra->xhci;
970         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
971         u32 offset;
972         u32 reg;
973
974         xhci_info(xhci, "saving dfe_cntl and ctle context for port %d\n", port);
975
976         if (port == 3 /* SATA pad */)
977                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
978         else
979                 offset = port ? padregs->iophy_misc_pad_p1_ctl6_0 :
980                                 padregs->iophy_misc_pad_p0_ctl6_0;
981
982         /* save tap1_val[] for the port for dfe_cntl */
983         reg = readl(tegra->padctl_base + offset);
984         reg &= ~(0xff << 16);
985         reg |= (0x32 << 16);
986         writel(reg, tegra->padctl_base + offset);
987
988         reg = readl(tegra->padctl_base + offset);
989         tegra->sregs.tap1_val[port] = ((reg & (0x1f << 24)) >> 24);
990
991         /* save amp_val[] for the port for dfe_cntl */
992         reg = readl(tegra->padctl_base + offset);
993         reg &= ~(0xff << 16);
994         reg |= (0x33 << 16);
995         writel(reg, tegra->padctl_base + offset);
996
997         reg = readl(tegra->padctl_base + offset);
998         tegra->sregs.amp_val[port] = ((reg & (0x7f << 24)) >> 24);
999
1000         /* save ctle_z_val[] for the port for ctle */
1001         reg = readl(tegra->padctl_base + offset);
1002         reg &= ~(0xff << 16);
1003         reg |= (0x20 << 16);
1004         writel(reg, tegra->padctl_base + offset);
1005
1006         reg = readl(tegra->padctl_base + offset);
1007         tegra->sregs.ctle_z_val[port] = ((reg & (0x3f << 24)) >> 24);
1008
1009         /* save ctle_g_val[] for the port for ctle */
1010         reg = readl(tegra->padctl_base + offset);
1011         reg &= ~(0xff << 16);
1012         reg |= (0x21 << 16);
1013         writel(reg, tegra->padctl_base + offset);
1014
1015         reg = readl(tegra->padctl_base + offset);
1016         tegra->sregs.ctle_g_val[port] = ((reg & (0x3f << 24)) >> 24);
1017         tegra->dfe_ctle_ctx_saved = true;
1018 }
1019
1020 static void tegra_xhci_restore_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
1021         u8 port)
1022 {
1023         struct xhci_hcd *xhci = tegra->xhci;
1024         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1025         u32 ctl4_offset, ctl2_offset;
1026         u32 reg;
1027
1028         /* don't restore if not saved */
1029         if (tegra->dfe_ctle_ctx_saved == false)
1030                 return;
1031
1032         if (port == 3 /* SATA pad */) {
1033                 ctl4_offset = padregs->iophy_misc_pad_s0_ctl4_0;
1034                 ctl2_offset = padregs->iophy_misc_pad_s0_ctl2_0;
1035         } else {
1036                 ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1037                                 padregs->iophy_usb3_pad0_ctl4_0;
1038                 ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1039                                 padregs->iophy_usb3_pad0_ctl2_0;
1040         }
1041
1042         xhci_info(xhci, "restoring dfe_cntl/ctle context of port %d\n", port);
1043
1044         /* restore dfe_cntl for the port */
1045         reg = readl(tegra->padctl_base + ctl4_offset);
1046         reg &= ~((0x7f << 16) | (0x1f << 24));
1047         reg |= ((tegra->sregs.amp_val[port] << 16) |
1048                 (tegra->sregs.tap1_val[port] << 24));
1049         writel(reg, tegra->padctl_base + ctl4_offset);
1050
1051         /* restore ctle for the port */
1052         reg = readl(tegra->padctl_base + ctl2_offset);
1053         reg &= ~((0x3f << 8) | (0x3f << 16));
1054         reg |= ((tegra->sregs.ctle_g_val[port] << 8) |
1055                 (tegra->sregs.ctle_z_val[port] << 16));
1056         writel(reg, tegra->padctl_base + ctl2_offset);
1057 }
1058
1059 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
1060         u8 port)
1061 {
1062         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1063         u32 reg;
1064
1065         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1066         reg &= ~USB2_ULPI_PAD;
1067         reg |= USB2_ULPI_PAD_OWNER_XUSB;
1068         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1069
1070         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1071         reg &= ~USB2_ULPI_PORT_CAP;
1072         reg |= (tegra->bdata->ulpicap << 24);
1073         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1074         /* FIXME: Program below when more details available
1075          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
1076          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
1077          */
1078 }
1079
1080 static void tegra_xhci_program_hsic_pad(struct tegra_xhci_hcd *tegra,
1081         u8 port)
1082 {
1083         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1084         u32 ctl0_offset;
1085         u32 reg;
1086
1087         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1088         reg &= ~(port ? USB2_HSIC_PAD_PORT1 : USB2_HSIC_PAD_PORT0);
1089         reg |= port ? USB2_HSIC_PAD_P1_OWNER_XUSB :
1090                         USB2_HSIC_PAD_P0_OWNER_XUSB;
1091         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1092
1093         ctl0_offset = port ? padregs->usb2_hsic_pad1_ctl0_0 :
1094                         padregs->usb2_hsic_pad0_ctl0_0;
1095
1096         reg = readl(tegra->padctl_base + ctl0_offset);
1097         reg &= ~(HSIC_TX_SLEWP | HSIC_TX_SLEWN);
1098         writel(reg, tegra->padctl_base + ctl0_offset);
1099
1100         /* FIXME Program below when more details available
1101          * XUSB_PADCTL_HSIC_PAD0_CTL_0_0
1102          * XUSB_PADCTL_HSIC_PAD0_CTL_1_0
1103          * XUSB_PADCTL_HSIC_PAD0_CTL_2_0
1104          * XUSB_PADCTL_HSIC_PAD1_CTL_0_0
1105          * XUSB_PADCTL_HSIC_PAD1_CTL_1_0
1106          * XUSB_PADCTL_HSIC_PAD1_CTL_2_0
1107          * XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0
1108          */
1109 }
1110
1111 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
1112         u8 port)
1113 {
1114         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1115         u32 reg;
1116         u32 ctl0_offset, ctl1_offset;
1117
1118         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1119         reg &= ~USB2_OTG_PAD_PORT_MASK(port);
1120         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
1121         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1122
1123         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1124         reg &= ~USB2_PORT_CAP_MASK(port);
1125         reg |= USB2_PORT_CAP_HOST(port);
1126         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1127
1128         /*
1129          * Modify only the bits which belongs to the port
1130          * and enable respective VBUS_PAD for the port
1131          */
1132         if (tegra->bdata->uses_external_pmic == false) {
1133                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1134                 reg &= ~(port == 2 ? OC_DET_VBUS_ENABLE2_OC_MAP :
1135                         port ? OC_DET_VBUS_ENABLE1_OC_MAP :
1136                                 OC_DET_VBUS_ENABLE0_OC_MAP);
1137
1138                 reg |= (port == 2) ? OC_DET_VBUS_EN2_OC_DETECTED_VBUS_PAD2 :
1139                         port ? OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1 :
1140                                 OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0;
1141                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1142         }
1143         /*
1144          * enable respective VBUS_PAD if port is mapped to any SS port
1145          */
1146         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1147         reg &= ~((port == 2) ? USB2_OC_MAP_PORT2 :
1148                 port ? USB2_OC_MAP_PORT1 : USB2_OC_MAP_PORT0);
1149         reg |= (0x4 | port) << (port * 3);
1150         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1151
1152         ctl0_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl0_0 :
1153                         port ? padregs->usb2_otg_pad1_ctl0_0 :
1154                                 padregs->usb2_otg_pad0_ctl0_0;
1155         ctl1_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl1_0 :
1156                         port ? padregs->usb2_otg_pad1_ctl1_0 :
1157                                 padregs->usb2_otg_pad0_ctl1_0;
1158
1159         reg = readl(tegra->padctl_base + ctl0_offset);
1160         reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
1161                 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
1162                 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
1163
1164         reg |= tegra->pdata->hs_slew;
1165         reg |= (port == 2) ? tegra->pdata->ls_rslew_pad2 :
1166                         port ? tegra->pdata->ls_rslew_pad1 :
1167                         tegra->pdata->ls_rslew_pad0;
1168         reg |= (port == 2) ? tegra->pdata->hs_curr_level_pad2 :
1169                         port ? tegra->pdata->hs_curr_level_pad1 :
1170                         tegra->pdata->hs_curr_level_pad0;
1171         writel(reg, tegra->padctl_base + ctl0_offset);
1172
1173         reg = readl(tegra->padctl_base + ctl1_offset);
1174         reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
1175                 | USB2_OTG_PD_CHRP_FORCE_POWERUP
1176                 | USB2_OTG_PD_DISC_FORCE_POWERUP
1177                 | USB2_OTG_PD_DR);
1178         reg |= (tegra->pdata->hs_iref_cap << 9) |
1179                 (tegra->pdata->hs_term_range_adj << 3);
1180         writel(reg, tegra->padctl_base + ctl1_offset);
1181 }
1182
1183 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
1184         u8 port)
1185 {
1186         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1187         u32 ctl2_offset, ctl4_offset;
1188         u32 reg;
1189
1190         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1191                         padregs->iophy_usb3_pad0_ctl2_0;
1192         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1193                         padregs->iophy_usb3_pad0_ctl4_0;
1194
1195         reg = readl(tegra->padctl_base + ctl2_offset);
1196         reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
1197                 IOPHY_USB3_CDRCNTL);
1198         reg |= tegra->pdata->rx_wander | tegra->pdata->rx_eq |
1199                 tegra->pdata->cdr_cntl;
1200         writel(reg, tegra->padctl_base + ctl2_offset);
1201
1202         reg = readl(tegra->padctl_base + ctl4_offset);
1203         reg = tegra->pdata->dfe_cntl;
1204         writel(reg, tegra->padctl_base + ctl4_offset);
1205
1206         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1207         reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
1208         reg |= (tegra->bdata->ss_portmap &
1209                 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
1210         writel(reg, tegra->padctl_base + padregs->ss_port_map_0);
1211
1212         tegra_xhci_restore_dfe_ctle_context(tegra, port);
1213         /* SATA also if USB3_SS port1 mapped to it */
1214         if ((port == 1) && (XUSB_DEVICE_ID_T124 == tegra->device_id) &&
1215                         (tegra->bdata->lane_owner & BIT(0)))
1216                 tegra_xhci_restore_dfe_ctle_context(tegra, 3);
1217 }
1218
1219 /* This function assigns the USB ports to the controllers,
1220  * then programs the port capabilities and pad parameters
1221  * of ports assigned to XUSB after booted to OS.
1222  */
1223 void
1224 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
1225 {
1226         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1227         u32 reg, oc_bits = 0;
1228
1229         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1230         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
1231         reg |= tegra->pdata->hs_squelch_level | tegra->pdata->hs_disc_lvl;
1232         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1233
1234         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1235         reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3;
1236         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
1237         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1238
1239         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1240         reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
1241         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1242                 reg |= OC_DET_VBUS_ENABLE2_OC_MAP;
1243         writel(reg, tegra->padctl_base + padregs->oc_det_0);
1244
1245         /* check if over current seen. Clear if present */
1246         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1247                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
1248         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1249                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
1250         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1251                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
1252
1253         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1254         if (reg & oc_bits) {
1255                 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
1256                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1257
1258                 usleep_range(100, 200);
1259
1260                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1261                 if (reg & oc_bits)
1262                         xhci_info(tegra->xhci, "Over current still present\n");
1263         }
1264
1265         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1266         reg = USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1;
1267         if (XUSB_DEVICE_ID_T124 == tegra->device_id)
1268                 reg |= USB2_OC_MAP_PORT2;
1269         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1270
1271         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1272                 tegra_xhci_program_utmip_pad(tegra, 0);
1273         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1274                 tegra_xhci_program_utmip_pad(tegra, 1);
1275         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1276                 tegra_xhci_program_utmip_pad(tegra, 2);
1277
1278         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
1279                 tegra_xhci_program_ulpi_pad(tegra, 0);
1280
1281         if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P0)
1282                 tegra_xhci_program_hsic_pad(tegra, 0);
1283         if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P1)
1284                 tegra_xhci_program_hsic_pad(tegra, 1);
1285
1286         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1287                 tegra_xhci_program_ss_pad(tegra, 0);
1288         } else {
1289                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1290                 reg = readl(tegra->padctl_base +
1291                         padregs->iophy_misc_pad_p0_ctl3_0);
1292                 reg &= ~RX_IDLE_MODE;
1293                 reg |= RX_IDLE_MODE_OVRD;
1294                 writel(reg, tegra->padctl_base +
1295                         padregs->iophy_misc_pad_p0_ctl3_0);
1296         }
1297
1298         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1299                 tegra_xhci_program_ss_pad(tegra, 1);
1300         } else {
1301                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1302                 reg = readl(tegra->padctl_base +
1303                         padregs->iophy_misc_pad_p1_ctl3_0);
1304                 reg &= ~RX_IDLE_MODE;
1305                 reg |= RX_IDLE_MODE_OVRD;
1306                 writel(reg, tegra->padctl_base +
1307                         padregs->iophy_misc_pad_p1_ctl3_0);
1308
1309                 /* SATA lane also if USB3_SS port1 mapped to it but unused */
1310                 if (XUSB_DEVICE_ID_T124 == tegra->device_id &&
1311                                 tegra->bdata->lane_owner & BIT(0)) {
1312                         reg = readl(tegra->padctl_base +
1313                                 padregs->iophy_misc_pad_s0_ctl3_0);
1314                         reg &= ~RX_IDLE_MODE;
1315                         reg |= RX_IDLE_MODE_OVRD;
1316                         writel(reg, tegra->padctl_base +
1317                                 padregs->iophy_misc_pad_s0_ctl3_0);
1318                 }
1319         }
1320         if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
1321                 tegra_xhci_setup_gpio_for_ss_lane(tegra);
1322                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
1323         }
1324 }
1325
1326 /* This function read XUSB registers and stores in device context */
1327 static void
1328 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
1329 {
1330
1331         /* a. Save the IPFS registers */
1332         tegra->sregs.msi_bar_sz =
1333                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
1334
1335         tegra->sregs.msi_axi_barst =
1336                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
1337
1338         tegra->sregs.msi_fpci_barst =
1339                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
1340
1341         tegra->sregs.msi_vec0 =
1342                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
1343
1344         tegra->sregs.msi_en_vec0 =
1345                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
1346
1347         tegra->sregs.fpci_error_masks =
1348                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
1349
1350         tegra->sregs.intr_mask =
1351                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1352
1353         tegra->sregs.ipfs_intr_enable =
1354                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
1355
1356         tegra->sregs.ufpci_config =
1357                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
1358
1359         tegra->sregs.clkgate_hysteresis =
1360                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1361
1362         tegra->sregs.xusb_host_mccif_fifo_cntrl =
1363                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
1364
1365         /* b. Save the CFG registers */
1366
1367         tegra->sregs.hs_pls =
1368                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
1369
1370         tegra->sregs.fs_pls =
1371                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
1372
1373         tegra->sregs.hs_fs_speed =
1374                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
1375
1376         tegra->sregs.hs_fs_pp =
1377                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
1378
1379         tegra->sregs.cfg_aru =
1380                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
1381
1382         tegra->sregs.cfg_order =
1383                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
1384
1385         tegra->sregs.cfg_fladj =
1386                 readl(tegra->fpci_base + XUSB_CFG_24);
1387
1388         tegra->sregs.cfg_sid =
1389                 readl(tegra->fpci_base + XUSB_CFG_16);
1390 }
1391
1392 /* This function restores XUSB registers from device context */
1393 static void
1394 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
1395 {
1396         /* Restore Cfg registers */
1397         writel(tegra->sregs.hs_pls,
1398                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
1399
1400         writel(tegra->sregs.fs_pls,
1401                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
1402
1403         writel(tegra->sregs.hs_fs_speed,
1404                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
1405
1406         writel(tegra->sregs.hs_fs_pp,
1407                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
1408
1409         writel(tegra->sregs.cfg_aru,
1410                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
1411
1412         writel(tegra->sregs.cfg_order,
1413                 tegra->fpci_base + XUSB_CFG_FPCICFG);
1414
1415         writel(tegra->sregs.cfg_fladj,
1416                 tegra->fpci_base + XUSB_CFG_24);
1417
1418         writel(tegra->sregs.cfg_sid,
1419                 tegra->fpci_base + XUSB_CFG_16);
1420
1421         /* Restore IPFS registers */
1422
1423         writel(tegra->sregs.msi_bar_sz,
1424                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
1425
1426         writel(tegra->sregs.msi_axi_barst,
1427                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
1428
1429         writel(tegra->sregs.msi_fpci_barst,
1430                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
1431
1432         writel(tegra->sregs.msi_vec0,
1433                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
1434
1435         writel(tegra->sregs.msi_en_vec0,
1436                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
1437
1438         writel(tegra->sregs.fpci_error_masks,
1439                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
1440
1441         writel(tegra->sregs.intr_mask,
1442                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1443
1444         writel(tegra->sregs.ipfs_intr_enable,
1445                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
1446
1447         writel(tegra->sregs.ufpci_config,
1448                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
1449
1450         writel(tegra->sregs.clkgate_hysteresis,
1451                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1452
1453         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
1454                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
1455 }
1456
1457 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
1458 {
1459         struct platform_device *pdev = tegra->pdev;
1460         u32 reg, timeout = 0xff, cmd;
1461
1462         mutex_lock(&tegra->mbox_lock);
1463
1464         do {
1465                 writel(MBOX_OWNER_SW,
1466                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
1467                 reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
1468                 usleep_range(10, 20);
1469         } while (reg != MBOX_OWNER_SW && timeout--);
1470
1471         if ((timeout == 0) && (reg != MBOX_OWNER_SW)) {
1472                 dev_err(&pdev->dev, "Failed to set mbox message owner ID\n");
1473                 mutex_unlock(&tegra->mbox_lock);
1474                 return;
1475         }
1476
1477         writel((MBOX_CMD_MSG_ENABLED << MBOX_CMD_SHIFT),
1478                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
1479
1480         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1481         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
1482         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1483
1484         mutex_unlock(&tegra->mbox_lock);
1485 }
1486
1487 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
1488 {
1489         struct platform_device *pdev = tegra->pdev;
1490         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
1491         u32 phys_addr_lo;
1492         u32 HwReg;
1493         u16 nblocks;
1494         time_t fw_time;
1495         struct tm fw_tm;
1496         u8 hc_caplength;
1497         u32 usbsts, count = 0xff;
1498         struct xhci_cap_regs __iomem *cap_regs;
1499         struct xhci_op_regs __iomem *op_regs;
1500
1501         /* enable mbox interrupt */
1502         writel(readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD) | MBOX_INT_EN,
1503                 tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1504
1505         /* First thing, reset the ARU. By the time we get to
1506          * loading boot code below, reset would be complete.
1507          * alternatively we can busy wait on rst pending bit.
1508          */
1509         /* Don't reset during ELPG/LP0 exit path */
1510         if (resetARU) {
1511                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
1512                 usleep_range(1000, 2000);
1513         }
1514
1515         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
1516                 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
1517                                 csb_read(tegra, XUSB_FALC_CPUCTL));
1518                 return 0;
1519         }
1520
1521         phys_addr_lo = tegra->firmware.dma;
1522         phys_addr_lo += sizeof(struct cfgtbl);
1523
1524         /* Program the size of DFI into ILOAD_ATTR */
1525         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
1526
1527         /* Boot code of the firmware reads the ILOAD_BASE_LO register
1528          * to get to the start of the dfi in system memory.
1529          */
1530         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
1531
1532         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
1533         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
1534
1535         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
1536         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
1537
1538         /* Invalidate L2IMEM. */
1539         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
1540
1541         /* Initiate fetch of Bootcode from system memory into L2IMEM.
1542          * Program BootCode location and size in system memory.
1543          */
1544         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
1545                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
1546                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
1547         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
1548                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
1549                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
1550         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
1551
1552         /* Trigger L2IMEM Load operation. */
1553         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
1554
1555         /* Setup Falcon Auto-fill */
1556         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
1557         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
1558                 nblocks += 1;
1559         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
1560
1561         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
1562         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
1563                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
1564         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
1565
1566         csb_write(tegra, XUSB_FALC_DMACTL, 0);
1567         msleep(50);
1568
1569         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
1570
1571         /* Start Falcon CPU */
1572         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
1573         usleep_range(1000, 2000);
1574
1575         fw_time = cfg_tbl->fwimg_created_time;
1576         time_to_tm(fw_time, 0, &fw_tm);
1577         dev_info(&pdev->dev,
1578                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
1579                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
1580                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
1581                 fw_tm.tm_min, fw_tm.tm_sec,
1582                 csb_read(tegra, XUSB_FALC_CPUCTL));
1583
1584         /* return fail if firmware status is not good */
1585         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
1586                 return -EFAULT;
1587
1588         cap_regs = IO_ADDRESS(tegra->host_phy_base);
1589         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
1590         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
1591
1592         /* wait for USBSTS_CNR to get set */
1593         do {
1594                 usbsts = ioread32(&op_regs->status);
1595         } while ((usbsts & STS_CNR) && count--);
1596
1597         if (!count && (usbsts & STS_CNR)) {
1598                 dev_err(&pdev->dev, "Controller not ready\n");
1599                 return -EFAULT;
1600         }
1601         return 0;
1602 }
1603
1604 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
1605         bool release)
1606 {
1607         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1608         u32 reg;
1609
1610         /* Issue is only applicable for T114 */
1611         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
1612                 return;
1613
1614         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1615         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
1616                         USB2_OTG_PAD_PORT_MASK(2));
1617
1618         if (!release) {
1619                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1620                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
1621                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1622                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
1623                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1624                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
1625         }
1626
1627         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1628 }
1629 /* SS ELPG Entry initiated by fw */
1630 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
1631 {
1632         struct xhci_hcd *xhci = tegra->xhci;
1633         u32 ret = 0;
1634
1635         must_have_sync_lock(tegra);
1636
1637         /* This is SS partition ELPG entry
1638          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
1639          */
1640
1641         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
1642          * only if it is sw initiated one
1643          */
1644
1645         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
1646          * SuperSpeed partition ELPG entry via mailbox protocol
1647          */
1648
1649         /* STEP 2: xHCI PEP driver and XUSB device mode driver
1650          * enable the XUSB wakeup interrupts for the SuperSpeed
1651          * and USB2.0 ports assigned to host.Section 4.1 Step 3
1652          */
1653         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
1654
1655         /* STEP 3: xHCI PEP driver initiates the signal sequence
1656          * to enable the XUSB SSwake detection logic for the
1657          * SuperSpeed ports assigned to host.Section 4.1 Step 4
1658          */
1659         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, true);
1660
1661         /* STEP 4: System Power Management driver asserts reset
1662          * to XUSB SuperSpeed partition then disables its clocks
1663          */
1664         tegra_periph_reset_assert(tegra->ss_clk);
1665         clk_disable(tegra->ss_clk);
1666
1667         usleep_range(100, 200);
1668
1669         /* STEP 5: System Power Management driver disables the
1670          * XUSB SuperSpeed partition power rails.
1671          */
1672         debug_print_portsc(xhci);
1673
1674         /* tegra_powergate_partition also does partition reset assert */
1675         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
1676         if (ret) {
1677                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
1678                                 __func__);
1679                 /* TODO: error recovery? */
1680         }
1681         tegra->ss_pwr_gated = true;
1682
1683         /* STEP 6: xHCI PEP driver initiates the signal sequence
1684          * to enable the XUSB SSwake detection logic for the
1685          * SuperSpeed ports assigned to host.Section 4.1 Step 7
1686          */
1687         tegra_xhci_ss_vcore(tegra->bdata->portmap, true);
1688
1689         return ret;
1690 }
1691
1692 /* Host ELPG Entry */
1693 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
1694 {
1695         struct xhci_hcd *xhci = tegra->xhci;
1696         u32 ret;
1697
1698         must_have_sync_lock(tegra);
1699
1700         /* If ss is already powergated skip ss ctx save stuff */
1701         if (tegra->ss_pwr_gated) {
1702                 xhci_info(xhci, "%s: SS partition is already powergated\n",
1703                         __func__);
1704         } else {
1705                 ret = tegra_xhci_ss_elpg_entry(tegra);
1706                 if (ret) {
1707                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
1708                                 __func__, ret);
1709                         return ret;
1710                 }
1711         }
1712
1713         /* 1. IS INTR PENDING INT_PENDING=1 ? */
1714
1715         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
1716         tegra_xhci_save_xusb_ctx(tegra);
1717
1718         pmc_init(tegra, 1);
1719
1720         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
1721         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
1722                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
1723
1724         /* STEP 4: Assert reset to host clk and disable host clk */
1725         tegra_periph_reset_assert(tegra->host_clk);
1726
1727         clk_disable(tegra->host_clk);
1728
1729         /* wait 150us */
1730         usleep_range(150, 200);
1731
1732         /* flush MC client of XUSB_HOST */
1733         tegra_powergate_mc_flush(TEGRA_POWERGATE_XUSBC);
1734
1735         /* STEP 4: Powergate host partition */
1736         /* tegra_powergate_partition also does partition reset assert */
1737         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
1738         if (ret) {
1739                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
1740                         __func__, ret);
1741                 /* TODO: error handling? */
1742                 return ret;
1743         }
1744         tegra->host_pwr_gated = true;
1745
1746         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1747                 clk_disable(tegra->pll_re_vco_clk);
1748         clk_disable(tegra->emc_clk);
1749         /* set port ownership to SNPS */
1750         tegra_xhci_release_port_ownership(tegra, true);
1751
1752         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
1753                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
1754
1755         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
1756         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
1757                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
1758         return ret;
1759 }
1760
1761 /* SS ELPG Exit triggered by PADCTL irq */
1762 /**
1763  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
1764  *
1765  * This function must be called with tegra->sync_lock acquired.
1766  *
1767  * @tegra: xhci controller context
1768  * @return 0 for success, or error numbers
1769  */
1770 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
1771 {
1772         struct xhci_hcd *xhci = tegra->xhci;
1773         int ret = 0;
1774
1775         must_have_sync_lock(tegra);
1776
1777         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
1778                         tegra->hs_wake_event || tegra->host_resume_req)) {
1779
1780                 /*
1781                  * PWR_UNGATE SS partition. XUSBA
1782                  * tegra_unpowergate_partition also does partition reset
1783                  * deassert
1784                  */
1785                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
1786                 if (ret) {
1787                         xhci_err(xhci,
1788                         "%s: could not unpowergate xusba partition %d\n",
1789                         __func__, ret);
1790                         goto out;
1791                 }
1792                 if (tegra->ss_wake_event)
1793                         tegra->ss_wake_event = false;
1794
1795         } else {
1796                 xhci_info(xhci, "%s: ss already power gated\n",
1797                         __func__);
1798                 return ret;
1799         }
1800
1801         /* Step 3: Enable clock to ss partition */
1802         clk_enable(tegra->ss_clk);
1803
1804         /* Step 4: Disable ss wake detection logic */
1805         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
1806
1807         /* Step 4.1: Disable ss wake detection logic */
1808         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
1809
1810         /* wait 150us */
1811         usleep_range(150, 200);
1812
1813         /* Step 4.2: Disable ss wake detection logic */
1814         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
1815
1816         /* Step 6 Deassert reset for ss clks */
1817         tegra_periph_reset_deassert(tegra->ss_clk);
1818
1819         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
1820         tegra->ss_pwr_gated = false;
1821 out:
1822         return ret;
1823 }
1824
1825 static void ss_partition_elpg_exit_work(struct work_struct *work)
1826 {
1827         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
1828                 ss_elpg_exit_work);
1829
1830         mutex_lock(&tegra->sync_lock);
1831         tegra_xhci_ss_partition_elpg_exit(tegra);
1832         mutex_unlock(&tegra->sync_lock);
1833 }
1834
1835 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
1836 static void update_remote_wakeup_ports_pmc(struct tegra_xhci_hcd *tegra)
1837 {
1838         struct xhci_hcd *xhci = tegra->xhci;
1839         u32 wake2_status;
1840
1841 #define PMC_WAKE2_STATUS        0x168
1842 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
1843
1844         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
1845
1846         if (wake2_status & PADCTL_WAKE) {
1847                 /* FIXME: This is customized for Dalmore, find a generic way */
1848                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
1849                 /* clear wake status */
1850                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
1851         }
1852
1853         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
1854                         __func__, tegra->usb3_rh_remote_wakeup_ports);
1855 }
1856
1857 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
1858 {
1859         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1860         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
1861         int port, num_ports;
1862         unsigned long *remote_wakeup_ports;
1863         u32 portsc;
1864         __le32 __iomem  **port_array;
1865         unsigned char *rh;
1866         unsigned int retry = 64;
1867
1868
1869         if (hcd == xhci->shared_hcd) {
1870                 port_array = xhci->usb3_ports;
1871                 num_ports = xhci->num_usb3_ports;
1872                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
1873                 rh = "usb3 roothub";
1874         } else
1875                 return;
1876
1877         while (*remote_wakeup_ports && retry--) {
1878                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
1879                         portsc = xhci_readl(xhci, port_array[port]);
1880
1881                         if (!(portsc & PORT_CONNECT)) {
1882                                 /* nothing to do if already disconnected */
1883                                 clear_bit(port, remote_wakeup_ports);
1884                                 continue;
1885                         }
1886
1887                         if ((portsc & PORT_PLS_MASK) == XDEV_U0)
1888                                 clear_bit(port, remote_wakeup_ports);
1889                         else
1890                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
1891                                                 __func__, rh, port, portsc);
1892                 }
1893
1894                 if (*remote_wakeup_ports)
1895                         msleep(20); /* give some time, irq will direct U0 */
1896         }
1897
1898         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
1899                         *remote_wakeup_ports);
1900 }
1901
1902 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
1903 {
1904         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1905         u32 reg, utmip_rctrl_val, utmip_tctrl_val;
1906
1907         /* Program XUSB as port owner for all usb2 ports */
1908         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1909         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
1910                         USB2_OTG_PAD_PORT_MASK(2));
1911         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
1912                 USB2_OTG_PAD_PORT_OWNER_XUSB(1) | USB2_OTG_PAD_PORT_MASK(2);
1913         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1914
1915         /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
1916          * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
1917          */
1918         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1919         reg &= ~((1 << 12) | (1 << 13));
1920         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1921
1922         /* wait 20us */
1923         usleep_range(20, 30);
1924
1925         /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
1926          * :: TCTRL and RCTRL
1927          */
1928         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl1_0);
1929         utmip_rctrl_val = RCTRL(reg);
1930         utmip_tctrl_val = TCTRL(reg);
1931
1932         /*
1933          * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
1934          * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
1935          */
1936         pmc_data.utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
1937         pmc_data.utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
1938
1939         xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
1940                 pmc_data.utmip_rctrl_val, pmc_data.utmip_tctrl_val);
1941
1942         /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
1943          * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
1944          */
1945         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1946         reg |= (1 << 13);
1947         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1948
1949         /* Program these values into PMC regiseter and program the
1950          * PMC override
1951          */
1952         reg = PMC_TCTRL_VAL(pmc_data.utmip_tctrl_val) |
1953                 PMC_RCTRL_VAL(pmc_data.utmip_rctrl_val);
1954         tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG, 0xffffffff, reg);
1955
1956         reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
1957         tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
1958
1959         /* Restore correct port ownership in padctl */
1960         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1961         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
1962                         USB2_OTG_PAD_PORT_MASK(2));
1963         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1964                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
1965         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1966                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
1967         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1968                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
1969         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1970 }
1971
1972 /* Host ELPG Exit triggered by PADCTL irq */
1973 /**
1974  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
1975  *
1976  * This function must be called with tegra->sync_lock acquired.
1977  *
1978  * @tegra: xhci controller context
1979  * @return 0 for success, or error numbers
1980  */
1981 static int
1982 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
1983 {
1984         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1985         struct xhci_hcd *xhci = tegra->xhci;
1986         int ret = 0;
1987
1988         must_have_sync_lock(tegra);
1989
1990         if (!tegra->hc_in_elpg)
1991                 return 0;
1992
1993         clk_enable(tegra->emc_clk);
1994         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1995                 clk_enable(tegra->pll_re_vco_clk);
1996         /* Step 2: Enable clock to host partition */
1997         clk_enable(tegra->host_clk);
1998
1999         if (tegra->lp0_exit) {
2000                 u32 reg, oc_bits = 0;
2001
2002                 /* Issue is only applicable for T114 */
2003                 if (XUSB_DEVICE_ID_T114 == tegra->device_id)
2004                         tegra_xhci_war_for_tctrl_rctrl(tegra);
2005                 /* check if over current seen. Clear if present */
2006                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2007                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2008                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2009                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2010                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2011                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2012
2013                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2014                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
2015                 if (reg & oc_bits) {
2016                         xhci_info(xhci, "Over current detected. Clearing...\n");
2017                         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2018
2019                         usleep_range(100, 200);
2020
2021                         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2022                         if (reg & oc_bits)
2023                                 xhci_info(xhci, "Over current still present\n");
2024                 }
2025                 tegra_xhci_padctl_portmap_and_caps(tegra);
2026                 /* release clamps post deassert */
2027                 tegra->lp0_exit = false;
2028         }
2029
2030         /* Clear FLUSH_ENABLE of MC client */
2031         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
2032
2033         /* set port ownership back to xusb */
2034         tegra_xhci_release_port_ownership(tegra, false);
2035
2036         /*
2037          * PWR_UNGATE Host partition. XUSBC
2038          * tegra_unpowergate_partition also does partition reset deassert
2039          */
2040         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
2041         if (ret) {
2042                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2043                         __func__, ret);
2044                 goto out;
2045         }
2046
2047         /* Step 4: Deassert reset to host partition clk */
2048         tegra_periph_reset_deassert(tegra->host_clk);
2049
2050         /* Step 6.1: IPFS and XUSB BAR initialization */
2051         tegra_xhci_cfg(tegra);
2052
2053         /* Step 6.2: IPFS and XUSB related restore */
2054         tegra_xhci_restore_ctx(tegra);
2055
2056         /* Step 8: xhci spec related ctx restore
2057          * will be done in xhci_resume().Do it here.
2058          */
2059
2060         tegra_xhci_ss_partition_elpg_exit(tegra);
2061
2062         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
2063         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
2064                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
2065                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
2066         }
2067
2068         /* clear ovrd bits */
2069         tegra_xhci_rx_idle_mode_override(tegra, false);
2070
2071         /* Load firmware */
2072         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
2073                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
2074                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
2075                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
2076                         __func__,
2077                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
2078                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
2079                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
2080                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
2081                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
2082                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
2083                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
2084                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
2085                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
2086         debug_print_portsc(xhci);
2087
2088         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
2089         if (ret < 0) {
2090                 xhci_err(xhci, "%s: failed to load firmware %d\n",
2091                         __func__, ret);
2092                 goto out;
2093         }
2094
2095         pmc_init(tegra, 0);
2096
2097         tegra->hc_in_elpg = false;
2098         ret = xhci_resume(tegra->xhci, 0);
2099         if (ret) {
2100                 xhci_err(xhci, "%s: could not resume right %d\n",
2101                                 __func__, ret);
2102                 goto out;
2103         }
2104
2105         update_remote_wakeup_ports_pmc(tegra);
2106
2107         if (tegra->hs_wake_event)
2108                 tegra->hs_wake_event = false;
2109
2110         if (tegra->host_resume_req)
2111                 tegra->host_resume_req = false;
2112
2113         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
2114                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
2115
2116         tegra->host_pwr_gated = false;
2117 out:
2118         return ret;
2119 }
2120
2121 static void host_partition_elpg_exit_work(struct work_struct *work)
2122 {
2123         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2124                 host_elpg_exit_work);
2125
2126         mutex_lock(&tegra->sync_lock);
2127         tegra_xhci_host_partition_elpg_exit(tegra);
2128         mutex_unlock(&tegra->sync_lock);
2129 }
2130
2131 /* Mailbox handling function. This function handles requests
2132  * from firmware and communicates with clock and powergating
2133  * module to alter clock rates and to power gate/ungate xusb
2134  * partitions.
2135  *
2136  * Following is the structure of mailbox messages.
2137  * bit 31:28 - msg type
2138  * bits 27:0 - mbox data
2139  * FIXME:  Check if we can just call clock functions like below
2140  * or should we schedule it for calling later ?
2141  */
2142
2143 static void
2144 tegra_xhci_process_mbox_message(struct work_struct *work)
2145 {
2146         u32 sw_resp = 0, cmd, data_in, fw_msg;
2147         int ret = 0;
2148         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2149                                         mbox_work);
2150         struct xhci_hcd *xhci = tegra->xhci;
2151         unsigned int freq_khz;
2152
2153         mutex_lock(&tegra->mbox_lock);
2154
2155         /* get the owner id */
2156         tegra->mbox_owner = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2157         tegra->mbox_owner &= MBOX_OWNER_ID_MASK;
2158
2159         /* get the mbox message from firmware */
2160         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
2161
2162         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2163         if (data_in) {
2164                 mutex_unlock(&tegra->mbox_lock);
2165                 return;
2166         }
2167
2168         /* get cmd type and cmd data */
2169         tegra->cmd_type = (fw_msg & MBOX_CMD_TYPE_MASK) >> MBOX_CMD_SHIFT;
2170         tegra->cmd_data = (fw_msg & MBOX_CMD_DATA_MASK);
2171
2172         /* decode the message and make appropriate requests to
2173          * clock or powergating module.
2174          */
2175
2176         switch (tegra->cmd_type) {
2177         case MBOX_CMD_INC_FALC_CLOCK:
2178         case MBOX_CMD_DEC_FALC_CLOCK:
2179                 ret = tegra_xusb_request_clk_rate(
2180                                 tegra,
2181                                 tegra->falc_clk,
2182                                 tegra->cmd_data,
2183                                 &sw_resp);
2184                 if (ret)
2185                         xhci_err(xhci, "%s: could not set required falc rate\n",
2186                                 __func__);
2187                 goto send_sw_response;
2188         case MBOX_CMD_INC_SSPI_CLOCK:
2189         case MBOX_CMD_DEC_SSPI_CLOCK:
2190                 ret = tegra_xusb_request_clk_rate(
2191                                 tegra,
2192                                 tegra->ss_src_clk,
2193                                 tegra->cmd_data,
2194                                 &sw_resp);
2195                 if (ret)
2196                         xhci_err(xhci, "%s: could not set required ss rate.\n",
2197                                 __func__);
2198                 goto send_sw_response;
2199         case MBOX_CMD_SET_BW:
2200                 /* fw sends BW request in MByte/sec */
2201                 freq_khz = tegra_emc_bw_to_freq_req(tegra->cmd_data << 10);
2202                 clk_set_rate(tegra->emc_clk, freq_khz * 1000);
2203
2204                 /* clear MBOX_SMI_INT_EN bit */
2205                 cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2206                 cmd &= ~MBOX_SMI_INT_EN;
2207                 writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2208
2209                 /* clear mbox owner as ACK will not be sent for this request */
2210                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2211                 break;
2212         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
2213                 tegra_xhci_save_dfe_ctle_context(tegra, tegra->cmd_data);
2214                 tegra_xhci_restore_dfe_ctle_context(tegra, tegra->cmd_data);
2215                 /* SATA lane also if USB3_SS port1 mapped to it */
2216                 if (tegra->cmd_data == 0x1 &&
2217                         XUSB_DEVICE_ID_T124 == tegra->device_id &&
2218                                 tegra->bdata->lane_owner & BIT(0)) {
2219                         tegra_xhci_save_dfe_ctle_context(tegra, 3);
2220                         tegra_xhci_restore_dfe_ctle_context(tegra, 3);
2221                 }
2222
2223                 sw_resp |= (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
2224                 goto send_sw_response;
2225         case MBOX_CMD_ACK:
2226                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2227                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2228                 break;
2229         case MBOX_CMD_NACK:
2230                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2231                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2232                 break;
2233         default:
2234                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
2235                                 __func__, tegra->cmd_type);
2236         }
2237         mutex_unlock(&tegra->mbox_lock);
2238         return;
2239
2240 send_sw_response:
2241         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2242         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2243         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
2244         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2245
2246         mutex_unlock(&tegra->mbox_lock);
2247 }
2248
2249 static irqreturn_t tegra_xhci_xusb_host_irq(int irq, void *ptrdev)
2250 {
2251         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2252         struct xhci_hcd *xhci = tegra->xhci;
2253
2254         xhci_dbg(xhci, "%s", __func__);
2255         return IRQ_HANDLED;
2256 }
2257
2258 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
2259 {
2260         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2261         struct xhci_hcd *xhci = tegra->xhci;
2262         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2263         u32 elpg_program0 = 0;
2264
2265         spin_lock(&tegra->lock);
2266
2267         tegra->last_jiffies = jiffies;
2268
2269         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
2270         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
2271
2272         /* Clear the interrupt cause. We already read the intr status. */
2273         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2274         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
2275
2276         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
2277         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
2278                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2279         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
2280                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
2281         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
2282                 __func__,
2283                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad0_ctl0_0));
2284         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
2285                 __func__,
2286                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad1_ctl0_0));
2287         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
2288                 __func__,
2289                 readl(tegra->padctl_base + padregs->usb2_bchrg_bias_pad_0));
2290
2291         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
2292                 tegra->ss_wake_event = true;
2293         else if (elpg_program0 &
2294                         (USB2_PORT0_WAKEUP_EVENT | USB2_PORT1_WAKEUP_EVENT))
2295                 tegra->hs_wake_event = true;
2296
2297         if (tegra->ss_wake_event || tegra->hs_wake_event) {
2298                 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
2299                         xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
2300                         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
2301                 } else if (tegra->ss_pwr_gated
2302                                 && tegra->host_pwr_gated) {
2303                         xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
2304                                 __func__);
2305                         schedule_work(&tegra->host_elpg_exit_work);
2306                 }
2307         } else {
2308                 xhci_err(xhci, "error: wake due to no hs/ss event\n");
2309                 tegra_usb_pad_reg_write(padregs->elpg_program_0, 0xffffffff);
2310         }
2311         spin_unlock(&tegra->lock);
2312         return IRQ_HANDLED;
2313 }
2314
2315 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
2316 {
2317         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2318         u32 temp;
2319
2320         spin_lock(&tegra->lock);
2321
2322         /* clear the mbox intr status 1st thing. Other
2323          * bits are W1C bits, so just write to SMI bit.
2324          */
2325
2326         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
2327
2328         /* write 1 to clear SMI INTR en bit ( bit 3 ) */
2329         temp = MBOX_SMI_INTR_EN;
2330         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
2331
2332         schedule_work(&tegra->mbox_work);
2333
2334         spin_unlock(&tegra->lock);
2335         return IRQ_HANDLED;
2336 }
2337
2338 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
2339 {
2340         /*
2341          * As of now platform drivers don't provide MSI support so we ensure
2342          * here that the generic code does not try to make a pci_dev from our
2343          * dev struct in order to setup MSI
2344          */
2345         xhci->quirks |= XHCI_BROKEN_MSI;
2346         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
2347 }
2348
2349 /* called during probe() after chip reset completes */
2350 static int xhci_plat_setup(struct usb_hcd *hcd)
2351 {
2352         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
2353 }
2354
2355 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
2356         const char *name, void __iomem **region)
2357 {
2358         struct resource *res;
2359         void __iomem *mem;
2360
2361         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
2362         if (!res) {
2363                 dev_err(&pdev->dev, "memory resource %s doesn't exist\n", name);
2364                 return -ENODEV;
2365         }
2366
2367         mem = devm_request_and_ioremap(&pdev->dev, res);
2368         if (!mem) {
2369                 dev_err(&pdev->dev, "failed to ioremap for %s\n", name);
2370                 return -EFAULT;
2371         }
2372         *region = mem;
2373
2374         return 0;
2375 }
2376
2377 static int tegra_xhci_request_irq(struct platform_device *pdev,
2378         const char *rscname, irq_handler_t handler, unsigned long irqflags,
2379         const char *devname, int *irq_no)
2380 {
2381         int ret;
2382         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2383         struct resource *res;
2384
2385         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, rscname);
2386         if (!res) {
2387                 dev_err(&pdev->dev, "irq resource %s doesn't exist\n", rscname);
2388                 return -ENODEV;
2389         }
2390
2391         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
2392                         devname, tegra);
2393         if (ret != 0) {
2394                 dev_err(&pdev->dev,
2395                         "failed to request_irq for %s (irq %d), error = %d\n",
2396                         devname, res->start, ret);
2397                 return ret;
2398         }
2399         *irq_no = res->start;
2400
2401         return 0;
2402 }
2403
2404 #ifdef CONFIG_PM
2405
2406 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
2407 {
2408         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2409         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2410         int err = 0;
2411         unsigned long flags;
2412
2413         mutex_lock(&tegra->sync_lock);
2414
2415         if (xhci->shared_hcd == hcd) {
2416                 tegra->usb3_rh_suspend = true;
2417                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
2418         } else if (xhci->main_hcd == hcd) {
2419                 tegra->usb2_rh_suspend = true;
2420                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
2421         }
2422
2423         WARN_ON(tegra->hc_in_elpg);
2424
2425         /* suspend xhci bus. This will also set remote mask */
2426         err = xhci_bus_suspend(hcd);
2427         if (err) {
2428                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
2429                                 __func__, err);
2430                 goto xhci_bus_suspend_failed;
2431         }
2432
2433         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
2434                 goto done; /* one of the root hubs is still working */
2435
2436         spin_lock_irqsave(&tegra->lock, flags);
2437         tegra->hc_in_elpg = true;
2438         spin_unlock_irqrestore(&tegra->lock, flags);
2439
2440         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
2441
2442         /* save xhci spec ctx. Already done by xhci_suspend */
2443         err = xhci_suspend(tegra->xhci);
2444         if (err) {
2445                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
2446                 goto xhci_suspend_failed;
2447         }
2448
2449         /* Powergate host. Include ss power gate if not already done */
2450         err = tegra_xhci_host_elpg_entry(tegra);
2451         if (err) {
2452                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
2453                                 __func__, err);
2454                 goto tegra_xhci_host_elpg_entry_failed;
2455         }
2456
2457         /* At this point,ensure ss/hs intr enables are always on */
2458         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2459         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2460
2461 done:
2462         /* pads are disabled only if usb2 root hub in xusb is idle */
2463         /* pads will actually be disabled only when all usb2 ports are idle */
2464         if (xhci->main_hcd == hcd) {
2465                 utmi_phy_pad_disable();
2466                 utmi_phy_iddq_override(true);
2467         }
2468         mutex_unlock(&tegra->sync_lock);
2469         return 0;
2470
2471 tegra_xhci_host_elpg_entry_failed:
2472
2473 xhci_suspend_failed:
2474         tegra->hc_in_elpg = false;
2475 xhci_bus_suspend_failed:
2476         if (xhci->shared_hcd == hcd)
2477                 tegra->usb3_rh_suspend = false;
2478         else if (xhci->main_hcd == hcd)
2479                 tegra->usb2_rh_suspend = false;
2480
2481         mutex_unlock(&tegra->sync_lock);
2482         return err;
2483 }
2484
2485 /* First, USB2HCD and then USB3HCD resume will be called */
2486 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
2487 {
2488         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2489         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2490         int err = 0;
2491
2492         mutex_lock(&tegra->sync_lock);
2493
2494         tegra->host_resume_req = true;
2495
2496         if (xhci->shared_hcd == hcd)
2497                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
2498         else if (xhci->main_hcd == hcd)
2499                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
2500
2501         /* pads are disabled only if usb2 root hub in xusb is idle */
2502         /* pads will actually be disabled only when all usb2 ports are idle */
2503         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
2504                 utmi_phy_pad_enable();
2505                 utmi_phy_iddq_override(false);
2506         }
2507         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
2508                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
2509                         tegra_xhci_host_partition_elpg_exit(tegra);
2510         }
2511
2512          /* handle remote wakeup before resuming bus */
2513         wait_remote_wakeup_ports(hcd);
2514
2515         err = xhci_bus_resume(hcd);
2516         if (err) {
2517                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
2518                                 __func__, err);
2519                 goto xhci_bus_resume_failed;
2520         }
2521
2522         if (xhci->shared_hcd == hcd)
2523                 tegra->usb3_rh_suspend = false;
2524         else if (xhci->main_hcd == hcd)
2525                 tegra->usb2_rh_suspend = false;
2526
2527         mutex_unlock(&tegra->sync_lock);
2528         return 0;
2529
2530 xhci_bus_resume_failed:
2531         /* TODO: reverse elpg? */
2532         mutex_unlock(&tegra->sync_lock);
2533         return err;
2534 }
2535 #endif
2536
2537 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
2538 {
2539         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2540         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2541         irqreturn_t iret = IRQ_HANDLED;
2542         u32 status;
2543
2544         spin_lock(&tegra->lock);
2545         if (tegra->hc_in_elpg) {
2546                 spin_lock(&xhci->lock);
2547                 if (HCD_HW_ACCESSIBLE(hcd)) {
2548                         status = xhci_readl(xhci, &xhci->op_regs->status);
2549                         status |= STS_EINT;
2550                         xhci_writel(xhci, status, &xhci->op_regs->status);
2551                 }
2552                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
2553                                 __func__);
2554                 schedule_work(&tegra->host_elpg_exit_work);
2555                 spin_unlock(&xhci->lock);
2556         } else
2557                 iret = xhci_irq(hcd);
2558         spin_unlock(&tegra->lock);
2559
2560         return iret;
2561 }
2562
2563
2564 static const struct hc_driver tegra_plat_xhci_driver = {
2565         .description =          "tegra-xhci",
2566         .product_desc =         "Nvidia xHCI Host Controller",
2567         .hcd_priv_size =        sizeof(struct xhci_hcd *),
2568
2569         /*
2570          * generic hardware linkage
2571          */
2572         .irq =                  tegra_xhci_irq,
2573         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
2574
2575         /*
2576          * basic lifecycle operations
2577          */
2578         .reset =                xhci_plat_setup,
2579         .start =                xhci_run,
2580         .stop =                 xhci_stop,
2581         .shutdown =             xhci_shutdown,
2582
2583         /*
2584          * managing i/o requests and associated device resources
2585          */
2586         .urb_enqueue =          xhci_urb_enqueue,
2587         .urb_dequeue =          xhci_urb_dequeue,
2588         .alloc_dev =            xhci_alloc_dev,
2589         .free_dev =             xhci_free_dev,
2590         .alloc_streams =        xhci_alloc_streams,
2591         .free_streams =         xhci_free_streams,
2592         .add_endpoint =         xhci_add_endpoint,
2593         .drop_endpoint =        xhci_drop_endpoint,
2594         .endpoint_reset =       xhci_endpoint_reset,
2595         .check_bandwidth =      xhci_check_bandwidth,
2596         .reset_bandwidth =      xhci_reset_bandwidth,
2597         .address_device =       xhci_address_device,
2598         .update_hub_device =    xhci_update_hub_device,
2599         .reset_device =         xhci_discover_or_reset_device,
2600
2601         /*
2602          * scheduling support
2603          */
2604         .get_frame_number =     xhci_get_frame,
2605
2606         /* Root hub support */
2607         .hub_control =          xhci_hub_control,
2608         .hub_status_data =      xhci_hub_status_data,
2609
2610 #ifdef CONFIG_PM
2611         .bus_suspend =          tegra_xhci_bus_suspend,
2612         .bus_resume =           tegra_xhci_bus_resume,
2613 #endif
2614 };
2615
2616 #ifdef CONFIG_PM
2617 static int
2618 tegra_xhci_suspend(struct platform_device *pdev,
2619                                                 pm_message_t state)
2620 {
2621         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2622         struct xhci_hcd *xhci = tegra->xhci;
2623
2624         int ret = 0;
2625
2626         mutex_lock(&tegra->sync_lock);
2627         if (!tegra->hc_in_elpg) {
2628                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
2629                                 __func__);
2630                 mutex_unlock(&tegra->sync_lock);
2631                 return -EBUSY;
2632         }
2633         mutex_unlock(&tegra->sync_lock);
2634
2635         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2636         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
2637
2638         /* enable_irq_wake for ss ports */
2639         ret = enable_irq_wake(tegra->padctl_irq);
2640         if (ret < 0) {
2641                 xhci_err(xhci,
2642                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
2643                 __func__, tegra->padctl_irq, ret);
2644         }
2645
2646         /* enable_irq_wake for hs/fs/ls ports */
2647         ret = enable_irq_wake(tegra->usb3_irq);
2648         if (ret < 0) {
2649                 xhci_err(xhci,
2650                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
2651                 __func__, tegra->usb3_irq, ret);
2652         }
2653         regulator_disable(tegra->xusb_avdd_usb3_pll_reg);
2654         regulator_disable(tegra->xusb_avddio_usb3_reg);
2655         tegra_usb2_clocks_deinit(tegra);
2656
2657         return ret;
2658 }
2659
2660 static int
2661 tegra_xhci_resume(struct platform_device *pdev)
2662 {
2663         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2664
2665         dev_dbg(&pdev->dev, "%s\n", __func__);
2666
2667         tegra->last_jiffies = jiffies;
2668
2669         disable_irq_wake(tegra->padctl_irq);
2670         disable_irq_wake(tegra->usb3_irq);
2671         tegra->lp0_exit = true;
2672
2673         regulator_enable(tegra->xusb_avddio_usb3_reg);
2674         regulator_enable(tegra->xusb_avdd_usb3_pll_reg);
2675         tegra_usb2_clocks_init(tegra);
2676
2677         return 0;
2678 }
2679 #endif
2680
2681
2682 static int init_bootloader_firmware(struct tegra_xhci_hcd *tegra)
2683 {
2684         struct platform_device *pdev = tegra->pdev;
2685         void __iomem *fw_mmio_base;
2686         phys_addr_t fw_mem_phy_addr;
2687         size_t fw_size;
2688         dma_addr_t fw_dma;
2689 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2690         int ret;
2691 #endif
2692
2693         /* bootloader saved firmware memory address in PMC SCRATCH34 register */
2694         fw_mem_phy_addr = tegra_usb_pmc_reg_read(PMC_SCRATCH34);
2695
2696         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
2697                         fw_mem_phy_addr, sizeof(struct cfgtbl));
2698
2699         if (!fw_mmio_base) {
2700                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
2701                                         fw_mem_phy_addr);
2702                         return -ENOMEM;
2703         }
2704
2705         fw_size = ioread32(fw_mmio_base + FW_SIZE_OFFSET);
2706         devm_iounmap(&pdev->dev, fw_mmio_base);
2707
2708         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
2709                         fw_mem_phy_addr, fw_size);
2710         if (!fw_mmio_base) {
2711                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
2712                                         fw_mem_phy_addr);
2713                         return -ENOMEM;
2714         }
2715
2716         dev_info(&pdev->dev, "Firmware Memory: phy 0x%x mapped 0x%p (%d Bytes)\n",
2717                         fw_mem_phy_addr, fw_mmio_base, fw_size);
2718
2719 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2720         fw_dma = dma_map_linear(&pdev->dev, fw_mem_phy_addr, fw_size,
2721                         DMA_TO_DEVICE);
2722         if (fw_dma == DMA_ERROR_CODE) {
2723                 dev_err(&pdev->dev, "%s: dma_map_linear failed\n",
2724                                 __func__);
2725                 ret = -ENOMEM;
2726                 goto error_iounmap;
2727         }
2728 #else
2729         fw_dma = fw_mem_phy_addr;
2730 #endif
2731         dev_info(&pdev->dev, "Firmware DMA Memory: dma 0x%p (%d Bytes)\n",
2732                         (void *) fw_dma, fw_size);
2733
2734         /* all set and ready to go */
2735         tegra->firmware.data = fw_mmio_base;
2736         tegra->firmware.dma = fw_dma;
2737         tegra->firmware.size = fw_size;
2738
2739         return 0;
2740
2741 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2742 error_iounmap:
2743         devm_iounmap(&pdev->dev, fw_mmio_base);
2744         return ret;
2745 #endif
2746 }
2747
2748 static void deinit_bootloader_firmware(struct tegra_xhci_hcd *tegra)
2749 {
2750         struct platform_device *pdev = tegra->pdev;
2751         void __iomem *fw_mmio_base = tegra->firmware.data;
2752
2753 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2754         dma_unmap_single(&pdev->dev, tegra->firmware.dma,
2755                         tegra->firmware.size, DMA_TO_DEVICE);
2756 #endif
2757         devm_iounmap(&pdev->dev, fw_mmio_base);
2758
2759         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
2760 }
2761
2762 static int init_firmware(struct tegra_xhci_hcd *tegra)
2763 {
2764         return init_bootloader_firmware(tegra);
2765 }
2766
2767 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
2768 {
2769         deinit_bootloader_firmware(tegra);
2770 }
2771
2772 static struct tegra_xusb_padctl_regs t114_padregs_offset = {
2773         .boot_media_0                   = 0x0,
2774         .usb2_pad_mux_0                 = 0x4,
2775         .usb2_port_cap_0                = 0x8,
2776         .snps_oc_map_0                  = 0xc,
2777         .usb2_oc_map_0                  = 0x10,
2778         .ss_port_map_0                  = 0x14,
2779         .oc_det_0                       = 0x18,
2780         .elpg_program_0                 = 0x1c,
2781         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
2782         .usb2_bchrg_otgpad0_ctl1_0      = 0xffff,
2783         .usb2_bchrg_otgpad1_ctl0_0      = 0x24,
2784         .usb2_bchrg_otgpad1_ctl1_0      = 0xffff,
2785         .usb2_bchrg_otgpad2_ctl0_0      = 0xffff,
2786         .usb2_bchrg_otgpad2_ctl1_0      = 0xffff,
2787         .usb2_bchrg_bias_pad_0          = 0x28,
2788         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
2789         .iophy_pll_p0_ctl1_0            = 0x30,
2790         .iophy_pll_p0_ctl2_0            = 0x34,
2791         .iophy_pll_p0_ctl3_0            = 0x38,
2792         .iophy_pll_p0_ctl4_0            = 0x3c,
2793         .iophy_usb3_pad0_ctl1_0         = 0x40,
2794         .iophy_usb3_pad1_ctl1_0         = 0x44,
2795         .iophy_usb3_pad0_ctl2_0         = 0x48,
2796         .iophy_usb3_pad1_ctl2_0         = 0x4c,
2797         .iophy_usb3_pad0_ctl3_0         = 0x50,
2798         .iophy_usb3_pad1_ctl3_0         = 0x54,
2799         .iophy_usb3_pad0_ctl4_0         = 0x58,
2800         .iophy_usb3_pad1_ctl4_0         = 0x5c,
2801         .iophy_misc_pad_p0_ctl1_0       = 0x60,
2802         .iophy_misc_pad_p1_ctl1_0       = 0x64,
2803         .iophy_misc_pad_p0_ctl2_0       = 0x68,
2804         .iophy_misc_pad_p1_ctl2_0       = 0x6c,
2805         .iophy_misc_pad_p0_ctl3_0       = 0x70,
2806         .iophy_misc_pad_p1_ctl3_0       = 0x74,
2807         .iophy_misc_pad_p0_ctl4_0       = 0x78,
2808         .iophy_misc_pad_p1_ctl4_0       = 0x7c,
2809         .iophy_misc_pad_p0_ctl5_0       = 0x80,
2810         .iophy_misc_pad_p1_ctl5_0       = 0x84,
2811         .iophy_misc_pad_p0_ctl6_0       = 0x88,
2812         .iophy_misc_pad_p1_ctl6_0       = 0x8c,
2813         .usb2_otg_pad0_ctl0_0           = 0x90,
2814         .usb2_otg_pad1_ctl0_0           = 0x94,
2815         .usb2_otg_pad2_ctl0_0           = 0xffff,
2816         .usb2_otg_pad0_ctl1_0           = 0x98,
2817         .usb2_otg_pad1_ctl1_0           = 0x9c,
2818         .usb2_otg_pad2_ctl1_0           = 0xffff,
2819         .usb2_bias_pad_ctl0_0           = 0xa0,
2820         .usb2_bias_pad_ctl1_0           = 0xa4,
2821         .usb2_hsic_pad0_ctl0_0          = 0xa8,
2822         .usb2_hsic_pad1_ctl0_0          = 0xac,
2823         .usb2_hsic_pad0_ctl1_0          = 0xb0,
2824         .usb2_hsic_pad1_ctl1_0          = 0xb4,
2825         .usb2_hsic_pad0_ctl2_0          = 0xb8,
2826         .usb2_hsic_pad1_ctl2_0          = 0xbc,
2827         .ulpi_link_trim_ctl0            = 0xc0,
2828         .ulpi_null_clk_trim_ctl0        = 0xc4,
2829         .hsic_strb_trim_ctl0            = 0xc8,
2830         .wake_ctl0                      = 0xcc,
2831         .pm_spare0                      = 0xd0,
2832         .iophy_misc_pad_p2_ctl1_0       = 0xffff,
2833         .iophy_misc_pad_p3_ctl1_0       = 0xffff,
2834         .iophy_misc_pad_p4_ctl1_0       = 0xffff,
2835         .iophy_misc_pad_p2_ctl2_0       = 0xffff,
2836         .iophy_misc_pad_p3_ctl2_0       = 0xffff,
2837         .iophy_misc_pad_p4_ctl2_0       = 0xffff,
2838         .iophy_misc_pad_p2_ctl3_0       = 0xffff,
2839         .iophy_misc_pad_p3_ctl3_0       = 0xffff,
2840         .iophy_misc_pad_p4_ctl3_0       = 0xffff,
2841         .iophy_misc_pad_p2_ctl4_0       = 0xffff,
2842         .iophy_misc_pad_p3_ctl4_0       = 0xffff,
2843         .iophy_misc_pad_p4_ctl4_0       = 0xffff,
2844         .iophy_misc_pad_p2_ctl5_0       = 0xffff,
2845         .iophy_misc_pad_p3_ctl5_0       = 0xffff,
2846         .iophy_misc_pad_p4_ctl5_0       = 0xffff,
2847         .iophy_misc_pad_p2_ctl6_0       = 0xffff,
2848         .iophy_misc_pad_p3_ctl6_0       = 0xffff,
2849         .iophy_misc_pad_p4_ctl6_0       = 0xffff,
2850         .usb3_pad_mux_0                 = 0xffff,
2851         .iophy_pll_s0_ctl1_0            = 0xffff,
2852         .iophy_pll_s0_ctl2_0            = 0xffff,
2853         .iophy_pll_s0_ctl3_0            = 0xffff,
2854         .iophy_pll_s0_ctl4_0            = 0xffff,
2855         .iophy_misc_pad_s0_ctl1_0       = 0xffff,
2856         .iophy_misc_pad_s0_ctl2_0       = 0xffff,
2857         .iophy_misc_pad_s0_ctl3_0       = 0xffff,
2858         .iophy_misc_pad_s0_ctl4_0       = 0xffff,
2859         .iophy_misc_pad_s0_ctl5_0       = 0xffff,
2860         .iophy_misc_pad_s0_ctl6_0       = 0xffff,
2861 };
2862
2863 static struct tegra_xusb_padctl_regs t124_padregs_offset = {
2864         .boot_media_0                   = 0x0,
2865         .usb2_pad_mux_0                 = 0x4,
2866         .usb2_port_cap_0                = 0x8,
2867         .snps_oc_map_0                  = 0xc,
2868         .usb2_oc_map_0                  = 0x10,
2869         .ss_port_map_0                  = 0x14,
2870         .oc_det_0                       = 0x18,
2871         .elpg_program_0                 = 0x1c,
2872         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
2873         .usb2_bchrg_otgpad0_ctl1_0      = 0x24,
2874         .usb2_bchrg_otgpad1_ctl0_0      = 0x28,
2875         .usb2_bchrg_otgpad1_ctl1_0      = 0x2c,
2876         .usb2_bchrg_otgpad2_ctl0_0      = 0x30,
2877         .usb2_bchrg_otgpad2_ctl1_0      = 0x34,
2878         .usb2_bchrg_bias_pad_0          = 0x38,
2879         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
2880         .iophy_pll_p0_ctl1_0            = 0x40,
2881         .iophy_pll_p0_ctl2_0            = 0x44,
2882         .iophy_pll_p0_ctl3_0            = 0x48,
2883         .iophy_pll_p0_ctl4_0            = 0x4c,
2884         .iophy_usb3_pad0_ctl1_0         = 0x50,
2885         .iophy_usb3_pad1_ctl1_0         = 0x54,
2886         .iophy_usb3_pad0_ctl2_0         = 0x58,
2887         .iophy_usb3_pad1_ctl2_0         = 0x5c,
2888         .iophy_usb3_pad0_ctl3_0         = 0x60,
2889         .iophy_usb3_pad1_ctl3_0         = 0x64,
2890         .iophy_usb3_pad0_ctl4_0         = 0x68,
2891         .iophy_usb3_pad1_ctl4_0         = 0x6c,
2892         .iophy_misc_pad_p0_ctl1_0       = 0x70,
2893         .iophy_misc_pad_p1_ctl1_0       = 0x74,
2894         .iophy_misc_pad_p0_ctl2_0       = 0x78,
2895         .iophy_misc_pad_p1_ctl2_0       = 0x7c,
2896         .iophy_misc_pad_p0_ctl3_0       = 0x80,
2897         .iophy_misc_pad_p1_ctl3_0       = 0x84,
2898         .iophy_misc_pad_p0_ctl4_0       = 0x88,
2899         .iophy_misc_pad_p1_ctl4_0       = 0x8c,
2900         .iophy_misc_pad_p0_ctl5_0       = 0x90,
2901         .iophy_misc_pad_p1_ctl5_0       = 0x94,
2902         .iophy_misc_pad_p0_ctl6_0       = 0x98,
2903         .iophy_misc_pad_p1_ctl6_0       = 0x9c,
2904         .usb2_otg_pad0_ctl0_0           = 0xa0,
2905         .usb2_otg_pad1_ctl0_0           = 0xa4,
2906         .usb2_otg_pad2_ctl0_0           = 0xa8,
2907         .usb2_otg_pad0_ctl1_0           = 0xac,
2908         .usb2_otg_pad1_ctl1_0           = 0xb0,
2909         .usb2_otg_pad2_ctl1_0           = 0xb4,
2910         .usb2_bias_pad_ctl0_0           = 0xb8,
2911         .usb2_bias_pad_ctl1_0           = 0xbc,
2912         .usb2_hsic_pad0_ctl0_0          = 0xc0,
2913         .usb2_hsic_pad1_ctl0_0          = 0xc4,
2914         .usb2_hsic_pad0_ctl1_0          = 0xc8,
2915         .usb2_hsic_pad1_ctl1_0          = 0xcc,
2916         .usb2_hsic_pad0_ctl2_0          = 0xd0,
2917         .usb2_hsic_pad1_ctl2_0          = 0xd4,
2918         .ulpi_link_trim_ctl0            = 0xd8,
2919         .ulpi_null_clk_trim_ctl0        = 0xdc,
2920         .hsic_strb_trim_ctl0            = 0xe0,
2921         .wake_ctl0                      = 0xe4,
2922         .pm_spare0                      = 0xe8,
2923         .iophy_misc_pad_p2_ctl1_0       = 0xec,
2924         .iophy_misc_pad_p3_ctl1_0       = 0xf0,
2925         .iophy_misc_pad_p4_ctl1_0       = 0xf4,
2926         .iophy_misc_pad_p2_ctl2_0       = 0xf8,
2927         .iophy_misc_pad_p3_ctl2_0       = 0xfc,
2928         .iophy_misc_pad_p4_ctl2_0       = 0x100,
2929         .iophy_misc_pad_p2_ctl3_0       = 0x104,
2930         .iophy_misc_pad_p3_ctl3_0       = 0x108,
2931         .iophy_misc_pad_p4_ctl3_0       = 0x10c,
2932         .iophy_misc_pad_p2_ctl4_0       = 0x110,
2933         .iophy_misc_pad_p3_ctl4_0       = 0x114,
2934         .iophy_misc_pad_p4_ctl4_0       = 0x118,
2935         .iophy_misc_pad_p2_ctl5_0       = 0x11c,
2936         .iophy_misc_pad_p3_ctl5_0       = 0x120,
2937         .iophy_misc_pad_p4_ctl5_0       = 0x124,
2938         .iophy_misc_pad_p2_ctl6_0       = 0x128,
2939         .iophy_misc_pad_p3_ctl6_0       = 0x12c,
2940         .iophy_misc_pad_p4_ctl6_0       = 0x130,
2941         .usb3_pad_mux_0                 = 0x134,
2942         .iophy_pll_s0_ctl1_0            = 0x138,
2943         .iophy_pll_s0_ctl2_0            = 0x13c,
2944         .iophy_pll_s0_ctl3_0            = 0x140,
2945         .iophy_pll_s0_ctl4_0            = 0x144,
2946         .iophy_misc_pad_s0_ctl1_0       = 0x148,
2947         .iophy_misc_pad_s0_ctl2_0       = 0x14c,
2948         .iophy_misc_pad_s0_ctl3_0       = 0x150,
2949         .iophy_misc_pad_s0_ctl4_0       = 0x154,
2950         .iophy_misc_pad_s0_ctl5_0       = 0x158,
2951         .iophy_misc_pad_s0_ctl6_0       = 0x15c,
2952 };
2953
2954 /* TODO: we have to refine error handling in tegra_xhci_probe() */
2955 static int tegra_xhci_probe(struct platform_device *pdev)
2956 {
2957         const struct hc_driver *driver;
2958         struct xhci_hcd *xhci;
2959         struct tegra_xhci_hcd *tegra;
2960         struct resource *res;
2961         struct usb_hcd  *hcd;
2962         u32 pmc_reg, val;
2963         int ret;
2964         int irq;
2965
2966         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
2967
2968         if (usb_disabled())
2969                 return -ENODEV;
2970
2971         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
2972         if (!tegra) {
2973                 dev_err(&pdev->dev, "memory alloc failed\n");
2974                 return -ENOMEM;
2975         }
2976         tegra->pdev = pdev;
2977         tegra->pdata = dev_get_platdata(&pdev->dev);
2978         tegra->bdata = tegra->pdata->bdata;
2979
2980         ret = tegra_xhci_request_mem_region(pdev, "padctl",
2981                         &tegra->padctl_base);
2982         if (ret) {
2983                 dev_err(&pdev->dev, "failed to map padctl\n");
2984                 return ret;
2985         }
2986
2987         ret = tegra_xhci_request_mem_region(pdev, "fpci", &tegra->fpci_base);
2988         if (ret) {
2989                 dev_err(&pdev->dev, "failed to map fpci\n");
2990                 return ret;
2991         }
2992
2993         ret = tegra_xhci_request_mem_region(pdev, "ipfs", &tegra->ipfs_base);
2994         if (ret) {
2995                 dev_err(&pdev->dev, "failed to map ipfs\n");
2996                 return ret;
2997         }
2998
2999         ret = tegra_xusb_partitions_clk_init(tegra);
3000         if (ret) {
3001                 dev_err(&pdev->dev,
3002                         "failed to initialize xusb partitions clocks\n");
3003                 return ret;
3004         }
3005
3006         /* Enable power rails to the PAD,VBUS
3007          * and pull-up voltage.Initialize the regulators
3008          */
3009         ret = tegra_xusb_regulator_init(tegra, pdev);
3010         if (ret) {
3011                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
3012                 goto err_deinit_xusb_partition_clk;
3013         }
3014
3015         /* Enable UTMIP, PLLU and PLLE */
3016         ret = tegra_usb2_clocks_init(tegra);
3017         if (ret) {
3018                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
3019                 goto err_deinit_tegra_xusb_regulator;
3020         }
3021
3022         /* tegra_unpowergate_partition also does partition reset deassert */
3023         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
3024         if (ret)
3025                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
3026
3027         /* tegra_unpowergate_partition also does partition reset deassert */
3028         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3029         if (ret)
3030                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
3031
3032         /* reset the pointer back to NULL. driver uses it */
3033         /* platform_set_drvdata(pdev, NULL); */
3034
3035         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "host");
3036         if (!res) {
3037                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
3038                 ret = -ENODEV;
3039                 goto err_deinit_usb2_clocks;
3040         }
3041         tegra->host_phy_base = res->start;
3042
3043         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
3044                                 res->start, resource_size(res));
3045         if (!tegra->host_phy_virt_base) {
3046                 dev_err(&pdev->dev, "error mapping host phy memory\n");
3047                 ret = -ENOMEM;
3048                 goto err_deinit_usb2_clocks;
3049         }
3050
3051         /* Setup IPFS access and BAR0 space */
3052         tegra_xhci_cfg(tegra);
3053
3054         val = readl(tegra->fpci_base + XUSB_CFG_0);
3055         tegra->device_id = (val >> 16) & 0xffff;
3056
3057         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
3058                 (XUSB_DEVICE_ID_T114 == tegra->device_id) ? "T114" : "T124+");
3059
3060         if (XUSB_DEVICE_ID_T114 == tegra->device_id) {
3061                 tegra->padregs = &t114_padregs_offset;
3062         } else if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
3063                 tegra->padregs = &t124_padregs_offset;
3064         } else {
3065                 dev_info(&pdev->dev, "XUSB device_id neither T114 nor T124!\n");
3066                 dev_info(&pdev->dev, "XUSB using T124 pad register offsets!\n");
3067                 tegra->padregs = &t124_padregs_offset;
3068         }
3069
3070         /* calculate rctrl_val and tctrl_val once at boot time */
3071         tegra_xhci_war_for_tctrl_rctrl(tegra);
3072
3073         /* Program the XUSB pads to take ownership of ports */
3074         tegra_xhci_padctl_portmap_and_caps(tegra);
3075
3076         /* Release XUSB wake logic state latching */
3077         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
3078         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
3079
3080         /* Deassert reset to XUSB host, ss, dev clocks */
3081         tegra_periph_reset_deassert(tegra->host_clk);
3082         tegra_periph_reset_deassert(tegra->ss_clk);
3083
3084         ret = init_firmware(tegra);
3085         if (ret < 0) {
3086                 dev_err(&pdev->dev, "failed to init firmware\n");
3087                 ret = -ENODEV;
3088                 goto err_deinit_usb2_clocks;
3089         }
3090
3091         ret = load_firmware(tegra, true /* do reset ARU */);
3092         if (ret < 0) {
3093                 dev_err(&pdev->dev, "failed to load firmware\n");
3094                 ret = -ENODEV;
3095                 goto err_deinit_firmware;
3096         }
3097
3098         device_init_wakeup(&pdev->dev, 1);
3099         driver = &tegra_plat_xhci_driver;
3100
3101         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
3102         if (!hcd) {
3103                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
3104                 ret = -ENOMEM;
3105                 goto err_deinit_firmware;
3106         }
3107
3108         ret = tegra_xhci_request_mem_region(pdev, "host", &hcd->regs);
3109         if (ret) {
3110                 dev_err(&pdev->dev, "failed to map host\n");
3111                 goto err_put_usb2_hcd;
3112         }
3113         hcd->rsrc_start = res->start;
3114         hcd->rsrc_len = resource_size(res);
3115
3116         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "host");
3117         if (!res) {
3118                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
3119                 ret = -ENODEV;
3120                 goto err_put_usb2_hcd;
3121         }
3122         irq = res->start;
3123         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
3124         if (ret) {
3125                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
3126                 goto err_put_usb2_hcd;
3127         }
3128
3129         /* USB 2.0 roothub is stored in the platform_device now. */
3130         hcd = dev_get_drvdata(&pdev->dev);
3131         xhci = hcd_to_xhci(hcd);
3132         tegra->xhci = xhci;
3133         platform_set_drvdata(pdev, tegra);
3134
3135         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
3136                                                 dev_name(&pdev->dev), hcd);
3137         if (!xhci->shared_hcd) {
3138                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
3139                 ret = -ENOMEM;
3140                 goto err_remove_usb2_hcd;
3141         }
3142
3143         /*
3144          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
3145          * is called by usb_add_hcd().
3146          */
3147         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
3148
3149         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
3150         if (ret) {
3151                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
3152                 goto err_put_usb3_hcd;
3153         }
3154
3155         device_init_wakeup(&hcd->self.root_hub->dev, 1);
3156         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
3157         spin_lock_init(&tegra->lock);
3158         mutex_init(&tegra->sync_lock);
3159         mutex_init(&tegra->mbox_lock);
3160
3161         /* do mailbox related initializations */
3162         tegra->mbox_owner = 0xffff;
3163         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
3164
3165         tegra_xhci_enable_fw_message(tegra);
3166
3167         /* do ss partition elpg exit related initialization */
3168         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
3169
3170         /* do host partition elpg exit related initialization */
3171         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
3172
3173         /* Register interrupt handler for SMI line to handle mailbox
3174          * interrupt from firmware
3175          */
3176         ret = tegra_xhci_request_irq(pdev, "host-smi", tegra_xhci_smi_irq,
3177                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
3178         if (ret != 0)
3179                 goto err_remove_usb3_hcd;
3180
3181         /* Register interrupt handler for PADCTRL line to
3182          * handle wake on connect irqs interrupt from
3183          * firmware
3184          */
3185         ret = tegra_xhci_request_irq(pdev, "padctl", tegra_xhci_padctl_irq,
3186                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
3187                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
3188         if (ret != 0)
3189                 goto err_remove_usb3_hcd;
3190
3191         ret = tegra_xhci_request_irq(pdev, "usb3", tegra_xhci_xusb_host_irq,
3192                         IRQF_SHARED | IRQF_TRIGGER_HIGH, "xusb_host_irq",
3193                         &tegra->usb3_irq);
3194         if (ret != 0)
3195                 goto err_remove_usb3_hcd;
3196
3197         tegra->ss_pwr_gated = false;
3198         tegra->host_pwr_gated = false;
3199         tegra->hc_in_elpg = false;
3200         tegra->hs_wake_event = false;
3201         tegra->host_resume_req = false;
3202         tegra->lp0_exit = false;
3203         tegra->dfe_ctle_ctx_saved = false;
3204
3205         /* reset wake event to NONE */
3206         pmc_reg = tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0);
3207         pmc_reg |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE);
3208         pmc_reg |= UTMIP_WAKE_VAL(1, WAKE_VAL_NONE);
3209         pmc_reg |= UTMIP_WAKE_VAL(2, WAKE_VAL_NONE);
3210         pmc_reg |= UTMIP_WAKE_VAL(3, WAKE_VAL_NONE);
3211         tegra_usb_pmc_reg_write(PMC_UTMIP_UHSIC_SLEEP_CFG_0, pmc_reg);
3212
3213         tegra_xhci_debug_read_pads(tegra);
3214         utmi_phy_pad_enable();
3215         utmi_phy_iddq_override(false);
3216
3217         tegra_pd_add_device(&pdev->dev);
3218
3219         return 0;
3220
3221 err_remove_usb3_hcd:
3222         usb_remove_hcd(xhci->shared_hcd);
3223 err_put_usb3_hcd:
3224         usb_put_hcd(xhci->shared_hcd);
3225 err_remove_usb2_hcd:
3226         kfree(tegra->xhci);
3227         usb_remove_hcd(hcd);
3228 err_put_usb2_hcd:
3229         usb_put_hcd(hcd);
3230 err_deinit_firmware:
3231         deinit_firmware(tegra);
3232 err_deinit_usb2_clocks:
3233         tegra_usb2_clocks_deinit(tegra);
3234 err_deinit_tegra_xusb_regulator:
3235         tegra_xusb_regulator_deinit(tegra);
3236 err_deinit_xusb_partition_clk:
3237         tegra_xusb_partitions_clk_deinit(tegra);
3238
3239         return ret;
3240 }
3241
3242 static int tegra_xhci_remove(struct platform_device *pdev)
3243 {
3244         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3245         struct xhci_hcd *xhci = NULL;
3246         struct usb_hcd *hcd = NULL;
3247
3248         if (tegra == NULL)
3249                 return -EINVAL;
3250
3251         xhci = tegra->xhci;
3252         hcd = xhci_to_hcd(xhci);
3253
3254         devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
3255         devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
3256         devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
3257         usb_remove_hcd(xhci->shared_hcd);
3258         usb_put_hcd(xhci->shared_hcd);
3259         usb_remove_hcd(hcd);
3260         usb_put_hcd(hcd);
3261         kfree(xhci);
3262
3263         deinit_firmware(tegra);
3264         tegra_xusb_regulator_deinit(tegra);
3265         tegra_usb2_clocks_deinit(tegra);
3266         if (!tegra->hc_in_elpg)
3267                 tegra_xusb_partitions_clk_deinit(tegra);
3268         utmi_phy_pad_disable();
3269         utmi_phy_iddq_override(true);
3270
3271         return 0;
3272 }
3273
3274 static void tegra_xhci_shutdown(struct platform_device *pdev)
3275 {
3276         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3277         struct xhci_hcd *xhci = NULL;
3278         struct usb_hcd *hcd = NULL;
3279
3280         if (tegra == NULL)
3281                 return;
3282
3283         if (tegra->hc_in_elpg) {
3284                 mutex_lock(&tegra->sync_lock);
3285                 tegra_xhci_host_partition_elpg_exit(tegra);
3286                 mutex_unlock(&tegra->sync_lock);
3287         }
3288         xhci = tegra->xhci;
3289         hcd = xhci_to_hcd(xhci);
3290         xhci_shutdown(hcd);
3291 }
3292
3293 static struct platform_driver tegra_xhci_driver = {
3294         .probe  = tegra_xhci_probe,
3295         .remove = tegra_xhci_remove,
3296         .shutdown = tegra_xhci_shutdown,
3297 #ifdef CONFIG_PM
3298         .suspend = tegra_xhci_suspend,
3299         .resume  = tegra_xhci_resume,
3300 #endif
3301         .driver = {
3302                 .name = "tegra-xhci",
3303         },
3304 };
3305 MODULE_ALIAS("platform:tegra-xhci");
3306
3307 int tegra_xhci_register_plat(void)
3308 {
3309         return platform_driver_register(&tegra_xhci_driver);
3310 }
3311
3312 void tegra_xhci_unregister_plat(void)
3313 {
3314         platform_driver_unregister(&tegra_xhci_driver);
3315 }