usb: xhci: tegra: refine shutdown path
[linux-3.10.git] / drivers / usb / host / xhci-tegra.c
1 /*
2  * xhci-tegra.c - Nvidia xHCI host controller driver
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/clk.h>
24 #include <linux/ioport.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irq.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/uaccess.h>
30 #include <linux/circ_buf.h>
31 #include <linux/vmalloc.h>
32 #include <linux/debugfs.h>
33 #include <linux/kthread.h>
34 #include <linux/gpio.h>
35
36 #include <mach/powergate.h>
37 #include <mach/clk.h>
38 #include <mach/tegra_usb_pad_ctrl.h>
39 #include <mach/tegra_usb_pmc.h>
40 #include <mach/pm_domains.h>
41 #include <mach/mc.h>
42 #include <mach/xusb.h>
43
44 #include "../../../arch/arm/mach-tegra/iomap.h" /* HACK -- remove */
45 #include "xhci-tegra.h"
46 #include "xhci.h"
47
48 /* macros */
49 #define FW_IOCTL_LOG_DEQUEUE_LOW        (4)
50 #define FW_IOCTL_LOG_DEQUEUE_HIGH       (5)
51 #define FW_IOCTL_DATA_SHIFT             (0)
52 #define FW_IOCTL_DATA_MASK              (0x00ffffff)
53 #define FW_IOCTL_TYPE_SHIFT             (24)
54 #define FW_IOCTL_TYPE_MASK              (0xff000000)
55 #define FW_LOG_SIZE                     (sizeof(struct log_entry))
56 #define FW_LOG_COUNT                    (4096)
57 #define FW_LOG_RING_SIZE                (FW_LOG_SIZE * FW_LOG_COUNT)
58 #define FW_LOG_PAYLOAD_SIZE             (27)
59 #define DRIVER                          (0x01)
60 #define CIRC_BUF_SIZE                   (4 * (1 << 20)) /* 4MB */
61 #define FW_LOG_THREAD_RELAX             (msecs_to_jiffies(100))
62
63 /* tegra_xhci_firmware_log.flags bits */
64 #define FW_LOG_CONTEXT_VALID            (0)
65 #define FW_LOG_FILE_OPENED              (1)
66
67 #define PAGE_SELECT_MASK                        0xFFFFFE00
68 #define PAGE_SELECT_SHIFT                       9
69 #define PAGE_OFFSET_MASK                        0x000001FF
70 #define CSB_PAGE_SELECT(_addr)                                          \
71         ({                                                              \
72                 typecheck(u32, _addr);                                  \
73                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
74         })
75 #define CSB_PAGE_OFFSET(_addr)                                          \
76         ({                                                              \
77                 typecheck(u32, _addr);                                  \
78                 (_addr & PAGE_OFFSET_MASK);                             \
79         })
80
81 /* PMC register definition */
82 #define PMC_PORT_UTMIP_P0               0
83 #define PMC_PORT_UTMIP_P1               1
84 #define PMC_PORT_UTMIP_P2               2
85 #define PMC_PORT_UHSIC_P0               3
86 #define PMC_PORT_NUM                    4
87
88 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
89 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
90 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
91
92 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
93
94 /* private data types */
95 /* command requests from the firmware */
96 enum MBOX_CMD_TYPE {
97         MBOX_CMD_MSG_ENABLED = 1,
98         MBOX_CMD_INC_FALC_CLOCK,
99         MBOX_CMD_DEC_FALC_CLOCK,
100         MBOX_CMD_INC_SSPI_CLOCK,
101         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
102         MBOX_CMD_SET_BW,
103         MBOX_CMD_SET_SS_PWR_GATING,
104         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
105         MBOX_CMD_SAVE_DFE_CTLE_CTX,
106
107         /* needs to be the last cmd */
108         MBOX_CMD_MAX,
109
110         /* resp msg to ack above commands */
111         MBOX_CMD_ACK = 128,
112         MBOX_CMD_NACK
113 };
114
115 struct log_entry {
116         u32 sequence_no;
117         u8 data[FW_LOG_PAYLOAD_SIZE];
118         u8 owner;
119 };
120
121 /* Usb3 Firmware Cfg Table */
122 struct cfgtbl {
123         u32 boot_loadaddr_in_imem;
124         u32 boot_codedfi_offset;
125         u32 boot_codetag;
126         u32 boot_codesize;
127
128         /* Physical memory reserved by Bootloader/BIOS */
129         u32 phys_memaddr;
130         u16 reqphys_memsize;
131         u16 alloc_phys_memsize;
132
133         /* .rodata section */
134         u32 rodata_img_offset;
135         u32 rodata_section_start;
136         u32 rodata_section_end;
137         u32 main_fnaddr;
138
139         u32 fwimg_cksum;
140         u32 fwimg_created_time;
141
142         /* Fields that get filled by linker during linking phase
143          * or initialized in the FW code.
144          */
145         u32 imem_resident_start;
146         u32 imem_resident_end;
147         u32 idirect_start;
148         u32 idirect_end;
149         u32 l2_imem_start;
150         u32 l2_imem_end;
151         u32 version_id;
152         u8 init_ddirect;
153         u8 reserved[3];
154         u32 phys_addr_log_buffer;
155         u32 total_log_entries;
156         u32 dequeue_ptr;
157
158         /*      Below two dummy variables are used to replace
159          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
160          *      retain the size of struct _CFG_TBL used by other AP/Module.
161          */
162         u32 dummy_var1;
163         u32 dummy_var2;
164
165         /* fwimg_len */
166         u32 fwimg_len;
167         u8 magic[8];
168         u32 SS_low_power_entry_timeout;
169         u8 padding[140]; /* padding bytes to makeup 256-bytes cfgtbl */
170 };
171
172 struct xusb_save_regs {
173         u32 msi_bar_sz;
174         u32 msi_axi_barst;
175         u32 msi_fpci_barst;
176         u32 msi_vec0;
177         u32 msi_en_vec0;
178         u32 fpci_error_masks;
179         u32 intr_mask;
180         u32 ipfs_intr_enable;
181         u32 ufpci_config;
182         u32 clkgate_hysteresis;
183         u32 xusb_host_mccif_fifo_cntrl;
184
185         /* PG does not mention below */
186         u32 hs_pls;
187         u32 fs_pls;
188         u32 hs_fs_speed;
189         u32 hs_fs_pp;
190         u32 cfg_aru;
191         u32 cfg_order;
192         u32 cfg_fladj;
193         u32 cfg_sid;
194         /* DFE and CTLE */
195         u32 tap1_val[2];
196         u32 amp_val[2];
197         u32 ctle_z_val[2];
198         u32 ctle_g_val[2];
199 };
200
201 struct tegra_xhci_firmware {
202         void *data; /* kernel virtual address */
203         size_t size; /* firmware size */
204         dma_addr_t dma; /* dma address for controller */
205 };
206
207 struct tegra_xhci_firmware_log {
208         dma_addr_t phys_addr;           /* dma-able address */
209         void *virt_addr;                /* kernel va of the shared log buffer */
210         struct log_entry *dequeue;      /* current dequeue pointer (va) */
211         struct circ_buf circ;           /* big circular buffer */
212
213         struct task_struct *thread;     /* a thread to consume log */
214         struct mutex mutex;
215         wait_queue_head_t read_wait;
216         wait_queue_head_t write_wait;
217         struct dentry *path;
218         struct dentry *log_file;
219         unsigned long flags;
220 };
221
222 /* structure to hold the offsets of padctl registers */
223 struct tegra_xusb_padctl_regs {
224         u16 boot_media_0;
225         u16 usb2_pad_mux_0;
226         u16 usb2_port_cap_0;
227         u16 snps_oc_map_0;
228         u16 usb2_oc_map_0;
229         u16 ss_port_map_0;
230         u16 oc_det_0;
231         u16 elpg_program_0;
232         u16 usb2_bchrg_otgpad0_ctl0_0;
233         u16 usb2_bchrg_otgpad0_ctl1_0;
234         u16 usb2_bchrg_otgpad1_ctl0_0;
235         u16 usb2_bchrg_otgpad1_ctl1_0;
236         u16 usb2_bchrg_otgpad2_ctl0_0;
237         u16 usb2_bchrg_otgpad2_ctl1_0;
238         u16 usb2_bchrg_bias_pad_0;
239         u16 usb2_bchrg_tdcd_dbnc_timer_0;
240         u16 iophy_pll_p0_ctl1_0;
241         u16 iophy_pll_p0_ctl2_0;
242         u16 iophy_pll_p0_ctl3_0;
243         u16 iophy_pll_p0_ctl4_0;
244         u16 iophy_usb3_pad0_ctl1_0;
245         u16 iophy_usb3_pad1_ctl1_0;
246         u16 iophy_usb3_pad0_ctl2_0;
247         u16 iophy_usb3_pad1_ctl2_0;
248         u16 iophy_usb3_pad0_ctl3_0;
249         u16 iophy_usb3_pad1_ctl3_0;
250         u16 iophy_usb3_pad0_ctl4_0;
251         u16 iophy_usb3_pad1_ctl4_0;
252         u16 iophy_misc_pad_p0_ctl1_0;
253         u16 iophy_misc_pad_p1_ctl1_0;
254         u16 iophy_misc_pad_p0_ctl2_0;
255         u16 iophy_misc_pad_p1_ctl2_0;
256         u16 iophy_misc_pad_p0_ctl3_0;
257         u16 iophy_misc_pad_p1_ctl3_0;
258         u16 iophy_misc_pad_p0_ctl4_0;
259         u16 iophy_misc_pad_p1_ctl4_0;
260         u16 iophy_misc_pad_p0_ctl5_0;
261         u16 iophy_misc_pad_p1_ctl5_0;
262         u16 iophy_misc_pad_p0_ctl6_0;
263         u16 iophy_misc_pad_p1_ctl6_0;
264         u16 usb2_otg_pad0_ctl0_0;
265         u16 usb2_otg_pad1_ctl0_0;
266         u16 usb2_otg_pad2_ctl0_0;
267         u16 usb2_otg_pad0_ctl1_0;
268         u16 usb2_otg_pad1_ctl1_0;
269         u16 usb2_otg_pad2_ctl1_0;
270         u16 usb2_bias_pad_ctl0_0;
271         u16 usb2_bias_pad_ctl1_0;
272         u16 usb2_hsic_pad0_ctl0_0;
273         u16 usb2_hsic_pad1_ctl0_0;
274         u16 usb2_hsic_pad0_ctl1_0;
275         u16 usb2_hsic_pad1_ctl1_0;
276         u16 usb2_hsic_pad0_ctl2_0;
277         u16 usb2_hsic_pad1_ctl2_0;
278         u16 ulpi_link_trim_ctl0;
279         u16 ulpi_null_clk_trim_ctl0;
280         u16 hsic_strb_trim_ctl0;
281         u16 wake_ctl0;
282         u16 pm_spare0;
283         u16 iophy_misc_pad_p2_ctl1_0;
284         u16 iophy_misc_pad_p3_ctl1_0;
285         u16 iophy_misc_pad_p4_ctl1_0;
286         u16 iophy_misc_pad_p2_ctl2_0;
287         u16 iophy_misc_pad_p3_ctl2_0;
288         u16 iophy_misc_pad_p4_ctl2_0;
289         u16 iophy_misc_pad_p2_ctl3_0;
290         u16 iophy_misc_pad_p3_ctl3_0;
291         u16 iophy_misc_pad_p4_ctl3_0;
292         u16 iophy_misc_pad_p2_ctl4_0;
293         u16 iophy_misc_pad_p3_ctl4_0;
294         u16 iophy_misc_pad_p4_ctl4_0;
295         u16 iophy_misc_pad_p2_ctl5_0;
296         u16 iophy_misc_pad_p3_ctl5_0;
297         u16 iophy_misc_pad_p4_ctl5_0;
298         u16 iophy_misc_pad_p2_ctl6_0;
299         u16 iophy_misc_pad_p3_ctl6_0;
300         u16 iophy_misc_pad_p4_ctl6_0;
301         u16 usb3_pad_mux_0;
302         u16 iophy_pll_s0_ctl1_0;
303         u16 iophy_pll_s0_ctl2_0;
304         u16 iophy_pll_s0_ctl3_0;
305         u16 iophy_pll_s0_ctl4_0;
306         u16 iophy_misc_pad_s0_ctl1_0;
307         u16 iophy_misc_pad_s0_ctl2_0;
308         u16 iophy_misc_pad_s0_ctl3_0;
309         u16 iophy_misc_pad_s0_ctl4_0;
310         u16 iophy_misc_pad_s0_ctl5_0;
311         u16 iophy_misc_pad_s0_ctl6_0;
312 };
313
314 struct tegra_xhci_hcd {
315         struct platform_device *pdev;
316         struct xhci_hcd *xhci;
317         u16 device_id;
318
319         spinlock_t lock;
320         struct mutex sync_lock;
321
322         int smi_irq;
323         int padctl_irq;
324         int usb3_irq;
325
326         bool ss_wake_event;
327         bool ss_pwr_gated;
328         bool host_pwr_gated;
329         bool hs_wake_event;
330         bool host_resume_req;
331         bool lp0_exit;
332         bool dfe_ctle_ctx_saved;
333         unsigned long last_jiffies;
334         unsigned long host_phy_base;
335         void __iomem *host_phy_virt_base;
336
337         void __iomem *padctl_base;
338         void __iomem *fpci_base;
339         void __iomem *ipfs_base;
340
341         struct tegra_xusb_platform_data *pdata;
342         struct tegra_xusb_board_data *bdata;
343         struct tegra_xusb_padctl_regs *padregs;
344
345         /* mailbox variables */
346         struct mutex mbox_lock;
347         u32 mbox_owner;
348         u32 cmd_type;
349         u32 cmd_data;
350
351         struct regulator *xusb_s5p0v_reg;
352         struct regulator *xusb_s5p0v1_reg;
353         struct regulator *xusb_s5p0v2_reg;
354         struct regulator *xusb_s1p05v_reg;
355         struct regulator *xusb_s3p3v_reg;
356         struct regulator *xusb_s1p8v_reg;
357
358         struct work_struct mbox_work;
359         struct work_struct ss_elpg_exit_work;
360         struct work_struct host_elpg_exit_work;
361
362         struct clk *host_clk;
363         struct clk *ss_clk;
364
365         /* XUSB Falcon SuperSpeed Clock */
366         struct clk *falc_clk;
367
368         /* EMC Clock */
369         struct clk *emc_clk;
370         /* XUSB SS PI Clock */
371         struct clk *ss_src_clk;
372         /* PLLE Clock */
373         struct clk *plle_clk;
374         struct clk *pll_u_480M;
375         struct clk *clk_m;
376         /* refPLLE clk */
377         struct clk *pll_re_vco_clk;
378         /*
379          * XUSB/IPFS specific registers these need to be saved/restored in
380          * addition to spec defined registers
381          */
382         struct xusb_save_regs sregs;
383         bool usb2_rh_suspend;
384         bool usb3_rh_suspend;
385         bool hc_in_elpg;
386
387         unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
388         /* firmware loading related */
389         struct tegra_xhci_firmware firmware;
390
391         struct tegra_xhci_firmware_log log;
392 };
393
394 static struct tegra_usb_pmc_data pmc_data;
395
396 /* functions */
397 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
398 {
399         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
400 }
401
402 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
403 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
404 {
405         WARN_ON(tegra->sync_lock.owner != current);
406 }
407 #else
408 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
409 #endif
410
411 static void tegra_xhci_setup_gpio_for_ss_lane(struct tegra_xhci_hcd *tegra)
412 {
413         int err = 0;
414
415         if (!tegra->bdata->gpio_controls_muxed_ss_lanes)
416                 return;
417
418         if (tegra->bdata->lane_owner & BIT(0)) {
419                 /* USB3_SS port1 is using SATA lane so set (MUX_SATA)
420                  * GPIO P11 to '0'
421                  */
422                 err = gpio_request((tegra->bdata->gpio_ss1_sata & 0xffff),
423                         "gpio_ss1_sata");
424                 if (err < 0)
425                         pr_err("%s: gpio_ss1_sata gpio_request failed %d\n",
426                                 __func__, err);
427                 err = gpio_direction_output((tegra->bdata->gpio_ss1_sata
428                         & 0xffff), 1);
429                 if (err < 0)
430                         pr_err("%s: gpio_ss1_sata gpio_direction failed %d\n",
431                                 __func__, err);
432                 __gpio_set_value((tegra->bdata->gpio_ss1_sata & 0xffff),
433                                 ((tegra->bdata->gpio_ss1_sata >> 16)));
434         }
435 }
436
437 static void debug_print_portsc(struct xhci_hcd *xhci)
438 {
439         __le32 __iomem *addr;
440         int i;
441         int ports;
442
443         ports = HCS_MAX_PORTS(xhci->hcs_params1);
444         addr = &xhci->op_regs->port_status_base;
445         for (i = 0; i < ports; i++) {
446                 xhci_dbg(xhci, "%p port %d status reg = 0x%x\n",
447                                 addr, i, (unsigned int) xhci_readl(xhci, addr));
448                 addr += NUM_PORT_REGS;
449         }
450 }
451
452 static void update_speed(struct tegra_xhci_hcd *tegra, u8 port)
453 {
454         struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
455         u32 portsc;
456
457         if (tegra->hc_in_elpg)
458                 return;
459
460         portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port +
461                                                 BAR0_XHCI_OP_PORTSC_UTMIP_0));
462         if (DEV_FULLSPEED(portsc))
463                 pmc_data.port_speed = USB_PMC_PORT_SPEED_FULL;
464         else if (DEV_HIGHSPEED(portsc))
465                 pmc_data.port_speed = USB_PMC_PORT_SPEED_HIGH;
466         else if (DEV_LOWSPEED(portsc))
467                 pmc_data.port_speed = USB_PMC_PORT_SPEED_LOW;
468         else if (DEV_SUPERSPEED(portsc))
469                 pmc_data.port_speed = USB_PMC_PORT_SPEED_SUPER;
470         else
471                 pmc_data.port_speed = USB_PMC_PORT_SPEED_UNKNOWN;
472 }
473
474 static void setup_wake_detect(bool setup_wake)
475 {
476         if (setup_wake)
477                 pmc_data.pmc_ops->setup_pmc_wake_detect(&pmc_data);
478         else
479                 pmc_data.pmc_ops->disable_pmc_bus_ctrl(&pmc_data, 0);
480 }
481
482 static void pmc_init(struct tegra_xhci_hcd *tegra, bool setup_wake)
483 {
484         u32 portmap = tegra->bdata->portmap;
485
486         pmc_data.controller_type = TEGRA_USB_3_0;
487         if (portmap & TEGRA_XUSB_USB2_P0) {
488                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 0) & 0xf;
489                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
490                 update_speed(tegra, pmc_data.instance);
491                 tegra_usb_pmc_init(&pmc_data);
492                 setup_wake_detect(setup_wake);
493         }
494         if (portmap & TEGRA_XUSB_USB2_P1) {
495                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 4) & 0xf;
496                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
497                 update_speed(tegra, pmc_data.instance);
498                 tegra_usb_pmc_init(&pmc_data);
499                 setup_wake_detect(setup_wake);
500         }
501         if (portmap & TEGRA_XUSB_USB2_P2) {
502                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 8) & 0xf;
503                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
504                 update_speed(tegra, pmc_data.instance);
505                 tegra_usb_pmc_init(&pmc_data);
506                 setup_wake_detect(setup_wake);
507         }
508         if (portmap & TEGRA_XUSB_HSIC_P0) {
509                 pmc_data.instance = PMC_PORT_UHSIC_P0;
510                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_HSIC;
511                 update_speed(tegra, pmc_data.instance);
512                 tegra_usb_pmc_init(&pmc_data);
513                 setup_wake_detect(setup_wake);
514         }
515 }
516
517 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
518 {
519         void __iomem *fpci_base = tegra->fpci_base;
520         struct platform_device *pdev = tegra->pdev;
521         u32 input_addr;
522         u32 data;
523         u32 csb_page_select;
524
525         /* to select the appropriate CSB page to write to */
526         csb_page_select = CSB_PAGE_SELECT(addr);
527
528         dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
529                         csb_page_select);
530
531         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
532
533         /* selects the appropriate offset in the page to read from */
534         input_addr = CSB_PAGE_OFFSET(addr);
535         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
536
537         dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
538                         input_addr, data);
539         return data;
540 }
541
542 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
543 {
544         void __iomem *fpci_base = tegra->fpci_base;
545         struct platform_device *pdev = tegra->pdev;
546         u32 input_addr;
547         u32 csb_page_select;
548
549         /* to select the appropriate CSB page to write to */
550         csb_page_select = CSB_PAGE_SELECT(addr);
551
552         dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
553                         csb_page_select);
554
555         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
556
557         /* selects the appropriate offset in the page to write to */
558         input_addr = CSB_PAGE_OFFSET(addr);
559         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
560
561         dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
562                         input_addr, data);
563 }
564
565 /**
566  * fw_log_next - find next log entry in a tegra_xhci_firmware_log context.
567  *      This function takes care of wrapping. That means when current log entry
568  *      is the last one, it returns with the first one.
569  *
570  * @param log   The tegra_xhci_firmware_log context.
571  * @param this  The current log entry.
572  * @return      The log entry which is next to the current one.
573  */
574 static inline struct log_entry *fw_log_next(
575                 struct tegra_xhci_firmware_log *log, struct log_entry *this)
576 {
577         struct log_entry *first = (struct log_entry *) log->virt_addr;
578         struct log_entry *last = first + FW_LOG_COUNT - 1;
579
580         WARN((this < first) || (this > last), "%s: invalid input\n", __func__);
581
582         return (this == last) ? first : (this + 1);
583 }
584
585 /**
586  * fw_log_update_dequeue_pointer - update dequeue pointer to both firmware and
587  *      tegra_xhci_firmware_log.dequeue.
588  *
589  * @param log   The tegra_xhci_firmware_log context.
590  * @param n     Counts of log entries to fast-forward.
591  */
592 static inline void fw_log_update_deq_pointer(
593                 struct tegra_xhci_firmware_log *log, int n)
594 {
595         struct tegra_xhci_hcd *tegra =
596                         container_of(log, struct tegra_xhci_hcd, log);
597         struct device *dev = &tegra->pdev->dev;
598         struct log_entry *deq = tegra->log.dequeue;
599         dma_addr_t physical_addr;
600         u32 reg;
601
602         dev_dbg(dev, "curr 0x%p fast-forward %d entries\n", deq, n);
603         while (n-- > 0)
604                 deq = fw_log_next(log, deq);
605
606         tegra->log.dequeue = deq;
607         physical_addr = tegra->log.phys_addr +
608                         ((u8 *)deq - (u8 *)tegra->log.virt_addr);
609
610         /* update dequeue pointer to firmware */
611         reg = (FW_IOCTL_LOG_DEQUEUE_LOW << FW_IOCTL_TYPE_SHIFT);
612         reg |= (physical_addr & 0xffff); /* lower 16-bits */
613         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
614
615         reg = (FW_IOCTL_LOG_DEQUEUE_HIGH << FW_IOCTL_TYPE_SHIFT);
616         reg |= ((physical_addr >> 16) & 0xffff); /* higher 16-bits */
617         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
618
619         dev_dbg(dev, "new 0x%p physical addr 0x%x\n", deq, physical_addr);
620 }
621
622 static inline bool circ_buffer_full(struct circ_buf *circ)
623 {
624         int space = CIRC_SPACE(circ->head, circ->tail, CIRC_BUF_SIZE);
625
626         return (space <= FW_LOG_SIZE);
627 }
628
629 /**
630  * fw_log_copy - copy firmware log from device's buffer to driver's circular
631  *      buffer.
632  * @param tegra tegra_xhci_hcd context
633  * @return true,        We still have firmware log in device's buffer to copy.
634  *                      This function returned due the driver's circular buffer
635  *                      is full. Caller should invoke this function again as
636  *                      soon as there is space in driver's circular buffer.
637  *         false,       Device's buffer is empty.
638  */
639 static inline bool fw_log_copy(struct tegra_xhci_hcd *tegra)
640 {
641         struct device *dev = &tegra->pdev->dev;
642         struct circ_buf *circ = &tegra->log.circ;
643         int head, tail;
644         int buffer_len, copy_len;
645         struct log_entry *entry;
646         struct log_entry *first = tegra->log.virt_addr;
647         static u32 last_seq = -1;
648
649         while (tegra->log.dequeue->owner == DRIVER) {
650
651                 /* calculate maximum contiguous driver buffer length */
652                 head = circ->head;
653                 tail = ACCESS_ONCE(circ->tail);
654                 buffer_len = CIRC_SPACE_TO_END(head, tail, CIRC_BUF_SIZE);
655                 /* round down to FW_LOG_SIZE */
656                 buffer_len -= (buffer_len % FW_LOG_SIZE);
657                 if (!buffer_len)
658                         return true; /* log available but no space left */
659
660                 /* calculate maximum contiguous log copy length */
661                 entry = tegra->log.dequeue;
662                 copy_len = 0;
663                 do {
664                         if ((last_seq + 1) != entry->sequence_no) {
665                                 dev_warn(dev,
666                                 "%s: discontinuous seq no, expect %u get %u\n",
667                                 __func__, last_seq + 1, entry->sequence_no);
668                         }
669                         last_seq = entry->sequence_no;
670                         copy_len += FW_LOG_SIZE;
671                         buffer_len -= FW_LOG_SIZE;
672                         if (!buffer_len)
673                                 break; /* no space left */
674                         entry = fw_log_next(&tegra->log, entry);
675                 } while ((entry->owner == DRIVER) && (entry != first));
676
677                 memcpy(&circ->buf[head], tegra->log.dequeue, copy_len);
678                 memset(tegra->log.dequeue, 0, copy_len);
679                 circ->head = (circ->head + copy_len) & (CIRC_BUF_SIZE - 1);
680
681                 mb();
682
683                 fw_log_update_deq_pointer(&tegra->log, copy_len/FW_LOG_SIZE);
684
685                 dev_dbg(dev, "copied %d entries, new dequeue 0x%p\n",
686                                 copy_len/FW_LOG_SIZE, tegra->log.dequeue);
687                 wake_up_interruptible(&tegra->log.read_wait);
688         }
689
690         return false;
691 }
692
693 static int fw_log_thread(void *data)
694 {
695         struct tegra_xhci_hcd *tegra = data;
696         struct device *dev = &tegra->pdev->dev;
697         struct circ_buf *circ = &tegra->log.circ;
698         bool logs_left;
699
700         dev_dbg(dev, "start firmware log thread\n");
701
702         do {
703                 mutex_lock(&tegra->log.mutex);
704                 if (circ_buffer_full(circ)) {
705                         mutex_unlock(&tegra->log.mutex);
706                         dev_info(dev, "%s: circ buffer full\n", __func__);
707                         wait_event_interruptible(tegra->log.write_wait,
708                                         !circ_buffer_full(circ));
709                         mutex_lock(&tegra->log.mutex);
710                 }
711
712                 logs_left = fw_log_copy(tegra);
713                 mutex_unlock(&tegra->log.mutex);
714
715                 /* relax if no logs left  */
716                 if (!logs_left)
717                         schedule_timeout_interruptible(FW_LOG_THREAD_RELAX);
718         } while (!kthread_should_stop());
719
720         dev_dbg(dev, "stop firmware log thread\n");
721         return 0;
722 }
723
724 static inline bool circ_buffer_empty(struct circ_buf *circ)
725 {
726         return (CIRC_CNT(circ->head, circ->tail, CIRC_BUF_SIZE) == 0);
727 }
728
729 static ssize_t fw_log_file_read(struct file *file, char __user *buf,
730                 size_t count, loff_t *offp)
731 {
732         struct tegra_xhci_hcd *tegra = file->private_data;
733         struct platform_device *pdev = tegra->pdev;
734         struct circ_buf *circ = &tegra->log.circ;
735         int head, tail;
736         size_t n = 0;
737         int s;
738
739         mutex_lock(&tegra->log.mutex);
740
741         while (circ_buffer_empty(circ)) {
742                 mutex_unlock(&tegra->log.mutex);
743                 if (file->f_flags & O_NONBLOCK)
744                         return -EAGAIN; /* non-blocking read */
745
746                 dev_dbg(&pdev->dev, "%s: nothing to read\n", __func__);
747
748                 if (wait_event_interruptible(tegra->log.read_wait,
749                                 !circ_buffer_empty(circ)))
750                         return -ERESTARTSYS;
751
752                 if (mutex_lock_interruptible(&tegra->log.mutex))
753                         return -ERESTARTSYS;
754         }
755
756         while (count > 0) {
757                 head = ACCESS_ONCE(circ->head);
758                 tail = circ->tail;
759                 s = min_t(int, count,
760                                 CIRC_CNT_TO_END(head, tail, CIRC_BUF_SIZE));
761
762                 if (s > 0) {
763                         if (copy_to_user(&buf[n], &circ->buf[tail], s)) {
764                                 dev_warn(&pdev->dev, "copy_to_user failed\n");
765                                 mutex_unlock(&tegra->log.mutex);
766                                 return -EFAULT;
767                         }
768                         circ->tail = (circ->tail + s) & (CIRC_BUF_SIZE - 1);
769
770                         count -= s;
771                         n += s;
772                 } else
773                         break;
774         }
775
776         mutex_unlock(&tegra->log.mutex);
777
778         wake_up_interruptible(&tegra->log.write_wait);
779
780         dev_dbg(&pdev->dev, "%s: %d bytes\n", __func__, n);
781
782         return n;
783 }
784
785 static int fw_log_file_open(struct inode *inode, struct file *file)
786 {
787         struct tegra_xhci_hcd *tegra;
788         file->private_data = inode->i_private;
789         tegra = file->private_data;
790
791         if (test_and_set_bit(FW_LOG_FILE_OPENED, &tegra->log.flags)) {
792                 dev_info(&tegra->pdev->dev, "%s: already opened\n", __func__);
793                 return -EBUSY;
794         }
795
796         return 0;
797 }
798
799 static int fw_log_file_close(struct inode *inode, struct file *file)
800 {
801         struct tegra_xhci_hcd *tegra = file->private_data;
802
803         clear_bit(FW_LOG_FILE_OPENED, &tegra->log.flags);
804
805         return 0;
806 }
807
808 static const struct file_operations firmware_log_fops = {
809                 .open           = fw_log_file_open,
810                 .release        = fw_log_file_close,
811                 .read           = fw_log_file_read,
812 };
813
814 static int fw_log_init(struct tegra_xhci_hcd *tegra)
815 {
816         struct platform_device *pdev = tegra->pdev;
817         int rc = 0;
818
819         /* allocate buffer to be shared between driver and firmware */
820         tegra->log.virt_addr = dma_alloc_writecombine(&pdev->dev,
821                         FW_LOG_RING_SIZE, &tegra->log.phys_addr, GFP_KERNEL);
822
823         if (!tegra->log.virt_addr) {
824                 dev_err(&pdev->dev, "dma_alloc_writecombine() size %d failed\n",
825                                 FW_LOG_RING_SIZE);
826                 return -ENOMEM;
827         }
828
829         dev_info(&pdev->dev, "%d bytes log buffer physical 0x%u virtual 0x%p\n",
830                 FW_LOG_RING_SIZE, tegra->log.phys_addr, tegra->log.virt_addr);
831
832         memset(tegra->log.virt_addr, 0, FW_LOG_RING_SIZE);
833         tegra->log.dequeue = tegra->log.virt_addr;
834
835         tegra->log.circ.buf = vmalloc(CIRC_BUF_SIZE);
836         if (!tegra->log.circ.buf) {
837                 dev_err(&pdev->dev, "vmalloc size %d failed\n", CIRC_BUF_SIZE);
838                 rc = -ENOMEM;
839                 goto error_free_dma;
840         }
841
842         tegra->log.circ.head = 0;
843         tegra->log.circ.tail = 0;
844
845         init_waitqueue_head(&tegra->log.read_wait);
846         init_waitqueue_head(&tegra->log.write_wait);
847
848         mutex_init(&tegra->log.mutex);
849
850         tegra->log.path = debugfs_create_dir("tegra_xhci", NULL);
851         if (IS_ERR_OR_NULL(tegra->log.path)) {
852                 dev_warn(&pdev->dev, "debugfs_create_dir() failed\n");
853                 rc = -ENOMEM;
854                 goto error_free_mem;
855         }
856
857         tegra->log.log_file = debugfs_create_file("firmware_log",
858                         S_IRUGO, tegra->log.path, tegra, &firmware_log_fops);
859         if ((!tegra->log.log_file) ||
860                         (tegra->log.log_file == ERR_PTR(-ENODEV))) {
861                 dev_warn(&pdev->dev, "debugfs_create_file() failed\n");
862                 rc = -ENOMEM;
863                 goto error_remove_debugfs_path;
864         }
865
866         tegra->log.thread = kthread_run(fw_log_thread, tegra, "xusb-fw-log");
867         if (IS_ERR(tegra->log.thread)) {
868                 dev_warn(&pdev->dev, "kthread_run() failed\n");
869                 rc = -ENOMEM;
870                 goto error_remove_debugfs_file;
871         }
872
873         set_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags);
874         return rc;
875
876 error_remove_debugfs_file:
877         debugfs_remove(tegra->log.log_file);
878 error_remove_debugfs_path:
879         debugfs_remove(tegra->log.path);
880 error_free_mem:
881         vfree(tegra->log.circ.buf);
882 error_free_dma:
883         dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
884                         tegra->log.virt_addr, tegra->log.phys_addr);
885         memset(&tegra->log, sizeof(tegra->log), 0);
886         return rc;
887 }
888
889 static void fw_log_deinit(struct tegra_xhci_hcd *tegra)
890 {
891         struct platform_device *pdev = tegra->pdev;
892
893         if (test_and_clear_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
894                 debugfs_remove(tegra->log.log_file);
895                 debugfs_remove(tegra->log.path);
896
897                 wake_up_interruptible(&tegra->log.read_wait);
898                 wake_up_interruptible(&tegra->log.write_wait);
899                 kthread_stop(tegra->log.thread);
900
901                 dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
902                         tegra->log.virt_addr, tegra->log.phys_addr);
903                 vfree(tegra->log.circ.buf);
904
905                 mutex_destroy(&tegra->log.mutex);
906         }
907 }
908
909 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
910 {
911         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
912         struct xhci_hcd *xhci = tegra->xhci;
913         u32 reg;
914
915         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
916         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
917         xhci_info(xhci, " PAD MUX = %x\n", reg);
918         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
919         xhci_info(xhci, " PORT CAP = %x\n", reg);
920         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
921         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
922         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
923         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
924         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
925         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
926         reg = readl(tegra->padctl_base + padregs->oc_det_0);
927         xhci_info(xhci, " OC DET 0= %x\n", reg);
928         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad0_ctl2_0);
929         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
930         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad1_ctl2_0);
931         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
932         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl0_0);
933         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
934         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl0_0);
935         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
936         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl1_0);
937         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
938         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl1_0);
939         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
940         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
941         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
942         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad0_ctl0_0);
943         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
944         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad1_ctl0_0);
945         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
946         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
947 }
948
949 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
950 {
951         u32 reg;
952
953         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
954         reg |= IPFS_EN_FPCI;
955         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
956         udelay(10);
957
958         /* Program Bar0 Space */
959         reg = readl(tegra->fpci_base + XUSB_CFG_4);
960         reg |= tegra->host_phy_base;
961         writel(reg, tegra->fpci_base + XUSB_CFG_4);
962         usleep_range(100, 200);
963
964         /* Enable Bus Master */
965         reg = readl(tegra->fpci_base + XUSB_CFG_1);
966         reg |= 0x7;
967         writel(reg, tegra->fpci_base + XUSB_CFG_1);
968
969         /* Set intr mask to enable intr assertion */
970         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
971         reg |= IPFS_IP_INT_MASK;
972         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
973
974         /* Set hysteris to 0x80 */
975         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
976 }
977
978 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
979                 struct platform_device *pdev)
980 {
981         struct tegra_xusb_regulator_name *supply = &tegra->bdata->supply;
982         int err = 0;
983
984         tegra->xusb_s3p3v_reg =
985                         devm_regulator_get(&pdev->dev, supply->s3p3v);
986         if (IS_ERR(tegra->xusb_s3p3v_reg)) {
987                 dev_err(&pdev->dev, "3p3v: regulator not found: %ld."
988                         , PTR_ERR(tegra->xusb_s3p3v_reg));
989                 err = PTR_ERR(tegra->xusb_s3p3v_reg);
990                 goto err_null_regulator;
991         } else {
992                 err = regulator_enable(tegra->xusb_s3p3v_reg);
993                 if (err < 0) {
994                         dev_err(&pdev->dev,
995                                 "3p3v: regulator enable failed:%d\n", err);
996                         goto err_null_regulator;
997                 }
998         }
999
1000         tegra->xusb_s5p0v_reg = devm_regulator_get(&pdev->dev, supply->s5p0v);
1001         if (IS_ERR(tegra->xusb_s5p0v_reg)) {
1002                 dev_err(&pdev->dev, "5p0v regulator not found: %ld."
1003                         , PTR_ERR(tegra->xusb_s5p0v_reg));
1004                 err = PTR_ERR(tegra->xusb_s5p0v_reg);
1005                 goto err_put_s3p3v_reg;
1006         } else {
1007                 err = regulator_enable(tegra->xusb_s5p0v_reg);
1008                 if (err < 0) {
1009                         dev_err(&pdev->dev,
1010                                 "5p0v: regulator enable failed:%d\n", err);
1011                         goto err_put_s3p3v_reg;
1012                 }
1013         }
1014
1015         tegra->xusb_s1p8v_reg =
1016                 devm_regulator_get(&pdev->dev, supply->s1p8v);
1017         if (IS_ERR(tegra->xusb_s1p8v_reg)) {
1018                 dev_err(&pdev->dev, "1p8v regulator not found: %ld."
1019                         , PTR_ERR(tegra->xusb_s1p8v_reg));
1020                 err = PTR_ERR(tegra->xusb_s1p8v_reg);
1021                 goto err_put_s5p0v_reg;
1022         } else {
1023                 err = regulator_enable(tegra->xusb_s1p8v_reg);
1024                 if (err < 0) {
1025                         dev_err(&pdev->dev,
1026                         "1p8v: regulator enable failed:%d\n", err);
1027                         goto err_put_s5p0v_reg;
1028                 }
1029         }
1030
1031         tegra->xusb_s1p05v_reg =
1032                         devm_regulator_get(&pdev->dev, supply->s1p05v);
1033         if (IS_ERR(tegra->xusb_s1p05v_reg)) {
1034                 dev_err(&pdev->dev, "1p05v: regulator not found: %ld."
1035                         , PTR_ERR(tegra->xusb_s1p05v_reg));
1036                 err = PTR_ERR(tegra->xusb_s1p05v_reg);
1037                 goto err_put_s1p8v_reg;
1038         } else {
1039                 err = regulator_enable(tegra->xusb_s1p05v_reg);
1040                 if (err < 0) {
1041                         dev_err(&pdev->dev,
1042                         "1p05v: regulator enable failed:%d\n", err);
1043                         goto err_put_s1p8v_reg;
1044                 }
1045         }
1046
1047         if (tegra->bdata->uses_different_vbus_per_port) {
1048                 tegra->xusb_s5p0v1_reg = devm_regulator_get(&pdev->dev,
1049                                                 supply->s5p0v1);
1050                 if (IS_ERR(tegra->xusb_s5p0v1_reg)) {
1051                         dev_err(&pdev->dev, "5p0v1 regulator not found: %ld."
1052                                 , PTR_ERR(tegra->xusb_s5p0v1_reg));
1053                         err = PTR_ERR(tegra->xusb_s5p0v1_reg);
1054                         goto err_put_s1p05v_reg;
1055                 } else {
1056                         err = regulator_enable(tegra->xusb_s5p0v1_reg);
1057                         if (err < 0) {
1058                                 dev_err(&pdev->dev,
1059                                 "5p0v1: regulator enable failed:%d\n", err);
1060                                 goto err_put_s1p05v_reg;
1061                         }
1062                 }
1063
1064                 tegra->xusb_s5p0v2_reg = devm_regulator_get(&pdev->dev,
1065                                                 supply->s5p0v2);
1066                 if (IS_ERR(tegra->xusb_s5p0v2_reg)) {
1067                         dev_err(&pdev->dev, "5p0v2 regulator not found: %ld."
1068                                 , PTR_ERR(tegra->xusb_s5p0v2_reg));
1069                         err = PTR_ERR(tegra->xusb_s5p0v2_reg);
1070                         goto err_put_s1p5v1_reg;
1071                 } else {
1072                         err = regulator_enable(tegra->xusb_s5p0v2_reg);
1073                         if (err < 0) {
1074                                 dev_err(&pdev->dev,
1075                                 "5p0v2: regulator enable failed:%d\n", err);
1076                                 goto err_put_s1p5v1_reg;
1077                         }
1078                 }
1079         }
1080         return err;
1081
1082 err_put_s1p5v1_reg:
1083         if (tegra->bdata->uses_different_vbus_per_port)
1084                 regulator_disable(tegra->xusb_s5p0v1_reg);
1085 err_put_s1p05v_reg:
1086         regulator_disable(tegra->xusb_s1p05v_reg);
1087 err_put_s1p8v_reg:
1088         regulator_disable(tegra->xusb_s1p8v_reg);
1089 err_put_s5p0v_reg:
1090         regulator_disable(tegra->xusb_s5p0v_reg);
1091 err_put_s3p3v_reg:
1092         regulator_disable(tegra->xusb_s3p3v_reg);
1093 err_null_regulator:
1094         tegra->xusb_s5p0v_reg = NULL;
1095         tegra->xusb_s5p0v1_reg = NULL;
1096         tegra->xusb_s5p0v2_reg = NULL;
1097         tegra->xusb_s1p05v_reg = NULL;
1098         tegra->xusb_s3p3v_reg = NULL;
1099         tegra->xusb_s1p8v_reg = NULL;
1100         return err;
1101 }
1102
1103 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
1104 {
1105         regulator_disable(tegra->xusb_s1p05v_reg);
1106         regulator_disable(tegra->xusb_s1p8v_reg);
1107         regulator_disable(tegra->xusb_s5p0v_reg);
1108         regulator_disable(tegra->xusb_s3p3v_reg);
1109         if (tegra->bdata->uses_different_vbus_per_port) {
1110                 regulator_disable(tegra->xusb_s5p0v1_reg);
1111                 regulator_disable(tegra->xusb_s5p0v2_reg);
1112         }
1113
1114         tegra->xusb_s1p05v_reg = NULL;
1115         tegra->xusb_s1p8v_reg = NULL;
1116         tegra->xusb_s5p0v_reg = NULL;
1117         tegra->xusb_s5p0v1_reg = NULL;
1118         tegra->xusb_s5p0v2_reg = NULL;
1119         tegra->xusb_s3p3v_reg = NULL;
1120 }
1121
1122 /*
1123  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
1124  * are under hardware control
1125  */
1126 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
1127 {
1128         struct platform_device *pdev = tegra->pdev;
1129         int err = 0;
1130
1131         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
1132         if (IS_ERR(tegra->plle_clk)) {
1133                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
1134                 err = PTR_ERR(tegra->plle_clk);
1135                 return err;
1136         }
1137         err = clk_enable(tegra->plle_clk);
1138         if (err) {
1139                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
1140                         __func__);
1141                 return err;
1142         }
1143
1144         return err;
1145 }
1146
1147 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
1148 {
1149         clk_disable(tegra->plle_clk);
1150         tegra->plle_clk = NULL;
1151 }
1152
1153 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
1154 {
1155         struct platform_device *pdev = tegra->pdev;
1156         int err = 0;
1157
1158         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
1159         if (IS_ERR(tegra->emc_clk)) {
1160                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
1161                 return PTR_ERR(tegra->emc_clk);
1162         }
1163
1164         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1165                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
1166                 if (IS_ERR(tegra->pll_re_vco_clk)) {
1167                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
1168                         err = PTR_ERR(tegra->pll_re_vco_clk);
1169                         goto get_pll_re_vco_clk_failed;
1170                 }
1171         }
1172
1173         /* get the clock handle of 120MHz clock source */
1174         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
1175         if (IS_ERR(tegra->pll_u_480M)) {
1176                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
1177                 err = PTR_ERR(tegra->pll_u_480M);
1178                 goto get_pll_u_480M_failed;
1179         }
1180
1181         /* get the clock handle of 12MHz clock source */
1182         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1183         if (IS_ERR(tegra->clk_m)) {
1184                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
1185                 err = PTR_ERR(tegra->clk_m);
1186                 goto clk_get_clk_m_failed;
1187         }
1188
1189         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
1190         if (IS_ERR(tegra->ss_src_clk)) {
1191                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
1192                 err = PTR_ERR(tegra->ss_src_clk);
1193                 tegra->ss_src_clk = NULL;
1194                 goto get_ss_src_clk_failed;
1195         }
1196
1197         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
1198         if (IS_ERR(tegra->host_clk)) {
1199                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
1200                 err = PTR_ERR(tegra->host_clk);
1201                 tegra->host_clk = NULL;
1202                 goto get_host_clk_failed;
1203         }
1204
1205         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
1206         if (IS_ERR(tegra->ss_clk)) {
1207                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
1208                 err = PTR_ERR(tegra->ss_clk);
1209                 tegra->ss_clk = NULL;
1210                 goto get_ss_clk_failed;
1211         }
1212
1213         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1214                 err = clk_enable(tegra->pll_re_vco_clk);
1215                 if (err) {
1216                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
1217                         goto enable_pll_re_vco_clk_failed;
1218                 }
1219         }
1220         /* enable ss clock */
1221         err = clk_enable(tegra->host_clk);
1222         if (err) {
1223                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
1224                 goto enable_host_clk_failed;
1225         }
1226
1227         err = clk_enable(tegra->ss_clk);
1228         if (err) {
1229                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
1230                 goto eanble_ss_clk_failed;
1231         }
1232
1233         err = clk_enable(tegra->emc_clk);
1234         if (err) {
1235                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
1236                 goto eanble_emc_clk_failed;
1237         }
1238
1239         return 0;
1240
1241 eanble_emc_clk_failed:
1242         clk_disable(tegra->ss_clk);
1243
1244 eanble_ss_clk_failed:
1245         clk_disable(tegra->host_clk);
1246
1247 enable_host_clk_failed:
1248         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1249                 clk_disable(tegra->pll_re_vco_clk);
1250
1251 enable_pll_re_vco_clk_failed:
1252         tegra->ss_clk = NULL;
1253
1254 get_ss_clk_failed:
1255         tegra->host_clk = NULL;
1256
1257 get_host_clk_failed:
1258         tegra->ss_src_clk = NULL;
1259
1260 get_ss_src_clk_failed:
1261         tegra->clk_m = NULL;
1262
1263 clk_get_clk_m_failed:
1264         tegra->pll_u_480M = NULL;
1265
1266 get_pll_u_480M_failed:
1267         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1268                 tegra->pll_re_vco_clk = NULL;
1269
1270 get_pll_re_vco_clk_failed:
1271         tegra->emc_clk = NULL;
1272
1273         return err;
1274 }
1275
1276 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
1277 {
1278         clk_disable(tegra->ss_clk);
1279         clk_disable(tegra->host_clk);
1280         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1281                 clk_disable(tegra->pll_re_vco_clk);
1282         tegra->ss_clk = NULL;
1283         tegra->host_clk = NULL;
1284         tegra->ss_src_clk = NULL;
1285         tegra->clk_m = NULL;
1286         tegra->pll_u_480M = NULL;
1287         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1288                 tegra->pll_re_vco_clk = NULL;
1289 }
1290
1291 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
1292         bool enable)
1293 {
1294         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1295         u32 reg;
1296
1297         /* Issue is only applicable for T114 */
1298         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
1299                 return;
1300
1301         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1302                 reg = readl(tegra->padctl_base +
1303                         padregs->iophy_misc_pad_p0_ctl3_0);
1304                 if (enable) {
1305                         reg &= ~RX_IDLE_MODE;
1306                         reg |= RX_IDLE_MODE_OVRD;
1307                 } else {
1308                         reg |= RX_IDLE_MODE;
1309                         reg &= ~RX_IDLE_MODE_OVRD;
1310                 }
1311                 writel(reg, tegra->padctl_base +
1312                         padregs->iophy_misc_pad_p0_ctl3_0);
1313         }
1314
1315         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1316                 reg = readl(tegra->padctl_base +
1317                         padregs->iophy_misc_pad_p1_ctl3_0);
1318                 if (enable) {
1319                         reg &= ~RX_IDLE_MODE;
1320                         reg |= RX_IDLE_MODE_OVRD;
1321                 } else {
1322                         reg |= RX_IDLE_MODE;
1323                         reg &= ~RX_IDLE_MODE_OVRD;
1324                 }
1325                 writel(reg, tegra->padctl_base +
1326                         padregs->iophy_misc_pad_p1_ctl3_0);
1327
1328                 /* SATA lane also if USB3_SS port1 mapped to it */
1329                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
1330                                 tegra->bdata->lane_owner & BIT(0)) {
1331                         reg = readl(tegra->padctl_base +
1332                                 padregs->iophy_misc_pad_s0_ctl3_0);
1333                         if (enable) {
1334                                 reg &= ~RX_IDLE_MODE;
1335                                 reg |= RX_IDLE_MODE_OVRD;
1336                         } else {
1337                                 reg |= RX_IDLE_MODE;
1338                                 reg &= ~RX_IDLE_MODE_OVRD;
1339                         }
1340                         writel(reg, tegra->padctl_base +
1341                                 padregs->iophy_misc_pad_s0_ctl3_0);
1342                 }
1343         }
1344 }
1345
1346 /* Enable ss clk, host clk, falcon clk,
1347  * fs clk, dev clk, plle and refplle
1348  */
1349
1350 static int
1351 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
1352                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
1353 {
1354         int ret = 0;
1355         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
1356         int fw_req_rate = rate, cur_rate;
1357
1358         /* Do not handle clock change as needed for HS disconnect issue */
1359         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1360                 *sw_resp = fw_req_rate | (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
1361                 return ret;
1362         }
1363
1364         /* frequency request from firmware is in KHz.
1365          * Convert it to MHz
1366          */
1367
1368         /* get current rate of clock */
1369         cur_rate = clk_get_rate(clk_handle);
1370         cur_rate /= 1000;
1371
1372         if (fw_req_rate == cur_rate) {
1373                 cmd_ack = MBOX_CMD_ACK;
1374                 *sw_resp = fw_req_rate;
1375         } else {
1376
1377                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
1378                         /* Change SS clock source to CLK_M at 12MHz */
1379                         clk_set_parent(clk_handle, tegra->clk_m);
1380                         clk_set_rate(clk_handle, fw_req_rate * 1000);
1381
1382                         /* save leakage power when SS freq is being decreased */
1383                         tegra_xhci_rx_idle_mode_override(tegra, true);
1384                 } else if (clk_handle == tegra->ss_src_clk &&
1385                                 fw_req_rate == 120000) {
1386                         /* Change SS clock source to HSIC_480 at 120MHz */
1387                         clk_set_rate(clk_handle,  3000 * 1000);
1388                         clk_set_parent(clk_handle, tegra->pll_u_480M);
1389
1390                         /* clear ovrd bits when SS freq is being increased */
1391                         tegra_xhci_rx_idle_mode_override(tegra, false);
1392                 }
1393
1394                 *sw_resp = clk_get_rate(clk_handle);
1395                 *sw_resp /= 1000;
1396
1397                 if (*sw_resp != fw_req_rate) {
1398                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
1399                                 cur_rate, fw_req_rate);
1400                         cmd_ack = MBOX_CMD_NACK;
1401                 }
1402         }
1403         *sw_resp |= (cmd_ack << MBOX_CMD_SHIFT);
1404         return ret;
1405 }
1406
1407 static void tegra_xhci_save_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
1408         u8 port)
1409 {
1410         struct xhci_hcd *xhci = tegra->xhci;
1411         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1412         u32 offset;
1413         u32 reg;
1414
1415         xhci_info(xhci, "saving dfe_cntl and ctle context for port %d\n", port);
1416
1417         if (port == 3 /* SATA pad */)
1418                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1419         else
1420                 offset = port ? padregs->iophy_misc_pad_p1_ctl6_0 :
1421                                 padregs->iophy_misc_pad_p0_ctl6_0;
1422
1423         /* save tap1_val[] for the port for dfe_cntl */
1424         reg = readl(tegra->padctl_base + offset);
1425         reg &= ~(0xff << 16);
1426         reg |= (0x32 << 16);
1427         writel(reg, tegra->padctl_base + offset);
1428
1429         reg = readl(tegra->padctl_base + offset);
1430         tegra->sregs.tap1_val[port] = ((reg & (0x1f << 24)) >> 24);
1431
1432         /* save amp_val[] for the port for dfe_cntl */
1433         reg = readl(tegra->padctl_base + offset);
1434         reg &= ~(0xff << 16);
1435         reg |= (0x33 << 16);
1436         writel(reg, tegra->padctl_base + offset);
1437
1438         reg = readl(tegra->padctl_base + offset);
1439         tegra->sregs.amp_val[port] = ((reg & (0x7f << 24)) >> 24);
1440
1441         /* save ctle_z_val[] for the port for ctle */
1442         reg = readl(tegra->padctl_base + offset);
1443         reg &= ~(0xff << 16);
1444         reg |= (0x20 << 16);
1445         writel(reg, tegra->padctl_base + offset);
1446
1447         reg = readl(tegra->padctl_base + offset);
1448         tegra->sregs.ctle_z_val[port] = ((reg & (0x3f << 24)) >> 24);
1449
1450         /* save ctle_g_val[] for the port for ctle */
1451         reg = readl(tegra->padctl_base + offset);
1452         reg &= ~(0xff << 16);
1453         reg |= (0x21 << 16);
1454         writel(reg, tegra->padctl_base + offset);
1455
1456         reg = readl(tegra->padctl_base + offset);
1457         tegra->sregs.ctle_g_val[port] = ((reg & (0x3f << 24)) >> 24);
1458         tegra->dfe_ctle_ctx_saved = true;
1459 }
1460
1461 static void tegra_xhci_restore_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
1462         u8 port)
1463 {
1464         struct xhci_hcd *xhci = tegra->xhci;
1465         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1466         u32 ctl4_offset, ctl2_offset;
1467         u32 reg;
1468
1469         /* don't restore if not saved */
1470         if (tegra->dfe_ctle_ctx_saved == false)
1471                 return;
1472
1473         if (port == 3 /* SATA pad */) {
1474                 ctl4_offset = padregs->iophy_misc_pad_s0_ctl4_0;
1475                 ctl2_offset = padregs->iophy_misc_pad_s0_ctl2_0;
1476         } else {
1477                 ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1478                                 padregs->iophy_usb3_pad0_ctl4_0;
1479                 ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1480                                 padregs->iophy_usb3_pad0_ctl2_0;
1481         }
1482
1483         xhci_info(xhci, "restoring dfe_cntl/ctle context of port %d\n", port);
1484
1485         /* restore dfe_cntl for the port */
1486         reg = readl(tegra->padctl_base + ctl4_offset);
1487         reg &= ~((0x7f << 16) | (0x1f << 24));
1488         reg |= ((tegra->sregs.amp_val[port] << 16) |
1489                 (tegra->sregs.tap1_val[port] << 24));
1490         writel(reg, tegra->padctl_base + ctl4_offset);
1491
1492         /* restore ctle for the port */
1493         reg = readl(tegra->padctl_base + ctl2_offset);
1494         reg &= ~((0x3f << 8) | (0x3f << 16));
1495         reg |= ((tegra->sregs.ctle_g_val[port] << 8) |
1496                 (tegra->sregs.ctle_z_val[port] << 16));
1497         writel(reg, tegra->padctl_base + ctl2_offset);
1498 }
1499
1500 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
1501         u8 port)
1502 {
1503         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1504         u32 reg;
1505
1506         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1507         reg &= ~USB2_ULPI_PAD;
1508         reg |= USB2_ULPI_PAD_OWNER_XUSB;
1509         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1510
1511         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1512         reg &= ~USB2_ULPI_PORT_CAP;
1513         reg |= (tegra->bdata->ulpicap << 24);
1514         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1515         /* FIXME: Program below when more details available
1516          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
1517          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
1518          */
1519 }
1520
1521 static void tegra_xhci_program_hsic_pad(struct tegra_xhci_hcd *tegra,
1522         u8 port)
1523 {
1524         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1525         u32 ctl0_offset;
1526         u32 reg;
1527
1528         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1529         reg &= ~(port ? USB2_HSIC_PAD_PORT1 : USB2_HSIC_PAD_PORT0);
1530         reg |= port ? USB2_HSIC_PAD_P1_OWNER_XUSB :
1531                         USB2_HSIC_PAD_P0_OWNER_XUSB;
1532         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1533
1534         ctl0_offset = port ? padregs->usb2_hsic_pad1_ctl0_0 :
1535                         padregs->usb2_hsic_pad0_ctl0_0;
1536
1537         reg = readl(tegra->padctl_base + ctl0_offset);
1538         reg &= ~(HSIC_TX_SLEWP | HSIC_TX_SLEWN);
1539         writel(reg, tegra->padctl_base + ctl0_offset);
1540
1541         /* FIXME Program below when more details available
1542          * XUSB_PADCTL_HSIC_PAD0_CTL_0_0
1543          * XUSB_PADCTL_HSIC_PAD0_CTL_1_0
1544          * XUSB_PADCTL_HSIC_PAD0_CTL_2_0
1545          * XUSB_PADCTL_HSIC_PAD1_CTL_0_0
1546          * XUSB_PADCTL_HSIC_PAD1_CTL_1_0
1547          * XUSB_PADCTL_HSIC_PAD1_CTL_2_0
1548          * XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0
1549          */
1550 }
1551
1552 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
1553         u8 port)
1554 {
1555         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1556         u32 reg;
1557         u32 ctl0_offset, ctl1_offset;
1558
1559         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1560         reg &= ~USB2_OTG_PAD_PORT_MASK(port);
1561         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
1562         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1563
1564         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1565         reg &= ~USB2_PORT_CAP_MASK(port);
1566         reg |= USB2_PORT_CAP_HOST(port);
1567         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1568
1569         /*
1570          * Modify only the bits which belongs to the port
1571          * and enable respective VBUS_PAD for the port
1572          */
1573         if (tegra->bdata->uses_external_pmic == false) {
1574                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1575                 reg &= ~(port == 2 ? OC_DET_VBUS_ENABLE2_OC_MAP :
1576                         port ? OC_DET_VBUS_ENABLE1_OC_MAP :
1577                                 OC_DET_VBUS_ENABLE0_OC_MAP);
1578
1579                 reg |= (port == 2) ? OC_DET_VBUS_EN2_OC_DETECTED_VBUS_PAD2 :
1580                         port ? OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1 :
1581                                 OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0;
1582                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1583         }
1584         /*
1585          * enable respective VBUS_PAD if port is mapped to any SS port
1586          */
1587         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1588         reg &= ~((port == 2) ? USB2_OC_MAP_PORT2 :
1589                 port ? USB2_OC_MAP_PORT1 : USB2_OC_MAP_PORT0);
1590         reg |= (0x4 | port) << (port * 3);
1591         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1592
1593         ctl0_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl0_0 :
1594                         port ? padregs->usb2_otg_pad1_ctl0_0 :
1595                                 padregs->usb2_otg_pad0_ctl0_0;
1596         ctl1_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl1_0 :
1597                         port ? padregs->usb2_otg_pad1_ctl1_0 :
1598                                 padregs->usb2_otg_pad0_ctl1_0;
1599
1600         reg = readl(tegra->padctl_base + ctl0_offset);
1601         reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
1602                 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
1603                 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
1604
1605         reg |= tegra->pdata->hs_slew;
1606         reg |= (port == 2) ? tegra->pdata->ls_rslew_pad2 :
1607                         port ? tegra->pdata->ls_rslew_pad1 :
1608                         tegra->pdata->ls_rslew_pad0;
1609         reg |= (port == 2) ? tegra->pdata->hs_curr_level_pad2 :
1610                         port ? tegra->pdata->hs_curr_level_pad1 :
1611                         tegra->pdata->hs_curr_level_pad0;
1612         writel(reg, tegra->padctl_base + ctl0_offset);
1613
1614         reg = readl(tegra->padctl_base + ctl1_offset);
1615         reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
1616                 | USB2_OTG_PD_CHRP_FORCE_POWERUP
1617                 | USB2_OTG_PD_DISC_FORCE_POWERUP
1618                 | USB2_OTG_PD_DR);
1619         reg |= (tegra->pdata->hs_iref_cap << 9) |
1620                 (tegra->pdata->hs_term_range_adj << 3);
1621         writel(reg, tegra->padctl_base + ctl1_offset);
1622 }
1623
1624 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
1625         u8 port)
1626 {
1627         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1628         u32 ctl2_offset, ctl4_offset, ctl5_offset;
1629         u32 reg;
1630
1631         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1632                         padregs->iophy_usb3_pad0_ctl2_0;
1633         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1634                         padregs->iophy_usb3_pad0_ctl4_0;
1635         ctl5_offset = port ? padregs->iophy_misc_pad_p1_ctl5_0 :
1636                         padregs->iophy_misc_pad_p0_ctl5_0;
1637
1638         reg = readl(tegra->padctl_base + ctl2_offset);
1639         reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
1640                 IOPHY_USB3_CDRCNTL);
1641         reg |= tegra->pdata->rx_wander | tegra->pdata->rx_eq |
1642                 tegra->pdata->cdr_cntl;
1643         writel(reg, tegra->padctl_base + ctl2_offset);
1644
1645         reg = readl(tegra->padctl_base + ctl4_offset);
1646         reg = tegra->pdata->dfe_cntl;
1647         writel(reg, tegra->padctl_base + ctl4_offset);
1648
1649         reg = readl(tegra->padctl_base + ctl5_offset);
1650         reg |= RX_QEYE_EN;
1651         writel(reg, tegra->padctl_base + ctl5_offset);
1652
1653         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1654         reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
1655         reg |= (tegra->bdata->ss_portmap &
1656                 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
1657         writel(reg, tegra->padctl_base + padregs->ss_port_map_0);
1658
1659         tegra_xhci_restore_dfe_ctle_context(tegra, port);
1660         /* SATA also if USB3_SS port1 mapped to it */
1661         if ((port == 1) && (XUSB_DEVICE_ID_T114 != tegra->device_id) &&
1662                         (tegra->bdata->lane_owner & BIT(0)))
1663                 tegra_xhci_restore_dfe_ctle_context(tegra, 3);
1664 }
1665
1666 /* This function assigns the USB ports to the controllers,
1667  * then programs the port capabilities and pad parameters
1668  * of ports assigned to XUSB after booted to OS.
1669  */
1670 void
1671 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
1672 {
1673         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1674         u32 reg, oc_bits = 0;
1675
1676         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1677         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
1678         reg |= tegra->pdata->hs_squelch_level | tegra->pdata->hs_disc_lvl;
1679         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1680
1681         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1682         reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3;
1683         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
1684         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1685
1686         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1687         reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
1688         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1689                 reg |= OC_DET_VBUS_ENABLE2_OC_MAP;
1690         writel(reg, tegra->padctl_base + padregs->oc_det_0);
1691
1692         /* check if over current seen. Clear if present */
1693         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1694                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
1695         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1696                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
1697         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1698                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
1699
1700         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1701         if (reg & oc_bits) {
1702                 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
1703                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1704
1705                 usleep_range(100, 200);
1706
1707                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1708                 if (reg & oc_bits)
1709                         xhci_info(tegra->xhci, "Over current still present\n");
1710         }
1711
1712         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1713         reg = USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1;
1714         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1715                 reg |= USB2_OC_MAP_PORT2;
1716         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1717
1718         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1719                 tegra_xhci_program_utmip_pad(tegra, 0);
1720         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1721                 tegra_xhci_program_utmip_pad(tegra, 1);
1722         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1723                 tegra_xhci_program_utmip_pad(tegra, 2);
1724
1725         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
1726                 tegra_xhci_program_ulpi_pad(tegra, 0);
1727
1728         if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P0)
1729                 tegra_xhci_program_hsic_pad(tegra, 0);
1730         if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P1)
1731                 tegra_xhci_program_hsic_pad(tegra, 1);
1732
1733         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1734                 tegra_xhci_program_ss_pad(tegra, 0);
1735         } else {
1736                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1737                 reg = readl(tegra->padctl_base +
1738                         padregs->iophy_misc_pad_p0_ctl3_0);
1739                 reg &= ~RX_IDLE_MODE;
1740                 reg |= RX_IDLE_MODE_OVRD;
1741                 writel(reg, tegra->padctl_base +
1742                         padregs->iophy_misc_pad_p0_ctl3_0);
1743         }
1744
1745         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1746                 tegra_xhci_program_ss_pad(tegra, 1);
1747         } else {
1748                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1749                 reg = readl(tegra->padctl_base +
1750                         padregs->iophy_misc_pad_p1_ctl3_0);
1751                 reg &= ~RX_IDLE_MODE;
1752                 reg |= RX_IDLE_MODE_OVRD;
1753                 writel(reg, tegra->padctl_base +
1754                         padregs->iophy_misc_pad_p1_ctl3_0);
1755
1756                 /* SATA lane also if USB3_SS port1 mapped to it but unused */
1757                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
1758                                 tegra->bdata->lane_owner & BIT(0)) {
1759                         reg = readl(tegra->padctl_base +
1760                                 padregs->iophy_misc_pad_s0_ctl3_0);
1761                         reg &= ~RX_IDLE_MODE;
1762                         reg |= RX_IDLE_MODE_OVRD;
1763                         writel(reg, tegra->padctl_base +
1764                                 padregs->iophy_misc_pad_s0_ctl3_0);
1765                 }
1766         }
1767         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
1768                 tegra_xhci_setup_gpio_for_ss_lane(tegra);
1769                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
1770         }
1771 }
1772
1773 /* This function read XUSB registers and stores in device context */
1774 static void
1775 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
1776 {
1777
1778         /* a. Save the IPFS registers */
1779         tegra->sregs.msi_bar_sz =
1780                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
1781
1782         tegra->sregs.msi_axi_barst =
1783                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
1784
1785         tegra->sregs.msi_fpci_barst =
1786                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
1787
1788         tegra->sregs.msi_vec0 =
1789                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
1790
1791         tegra->sregs.msi_en_vec0 =
1792                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
1793
1794         tegra->sregs.fpci_error_masks =
1795                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
1796
1797         tegra->sregs.intr_mask =
1798                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1799
1800         tegra->sregs.ipfs_intr_enable =
1801                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
1802
1803         tegra->sregs.ufpci_config =
1804                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
1805
1806         tegra->sregs.clkgate_hysteresis =
1807                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1808
1809         tegra->sregs.xusb_host_mccif_fifo_cntrl =
1810                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
1811
1812         /* b. Save the CFG registers */
1813
1814         tegra->sregs.hs_pls =
1815                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
1816
1817         tegra->sregs.fs_pls =
1818                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
1819
1820         tegra->sregs.hs_fs_speed =
1821                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
1822
1823         tegra->sregs.hs_fs_pp =
1824                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
1825
1826         tegra->sregs.cfg_aru =
1827                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
1828
1829         tegra->sregs.cfg_order =
1830                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
1831
1832         tegra->sregs.cfg_fladj =
1833                 readl(tegra->fpci_base + XUSB_CFG_24);
1834
1835         tegra->sregs.cfg_sid =
1836                 readl(tegra->fpci_base + XUSB_CFG_16);
1837 }
1838
1839 /* This function restores XUSB registers from device context */
1840 static void
1841 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
1842 {
1843         /* Restore Cfg registers */
1844         writel(tegra->sregs.hs_pls,
1845                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
1846
1847         writel(tegra->sregs.fs_pls,
1848                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
1849
1850         writel(tegra->sregs.hs_fs_speed,
1851                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
1852
1853         writel(tegra->sregs.hs_fs_pp,
1854                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
1855
1856         writel(tegra->sregs.cfg_aru,
1857                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
1858
1859         writel(tegra->sregs.cfg_order,
1860                 tegra->fpci_base + XUSB_CFG_FPCICFG);
1861
1862         writel(tegra->sregs.cfg_fladj,
1863                 tegra->fpci_base + XUSB_CFG_24);
1864
1865         writel(tegra->sregs.cfg_sid,
1866                 tegra->fpci_base + XUSB_CFG_16);
1867
1868         /* Restore IPFS registers */
1869
1870         writel(tegra->sregs.msi_bar_sz,
1871                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
1872
1873         writel(tegra->sregs.msi_axi_barst,
1874                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
1875
1876         writel(tegra->sregs.msi_fpci_barst,
1877                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
1878
1879         writel(tegra->sregs.msi_vec0,
1880                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
1881
1882         writel(tegra->sregs.msi_en_vec0,
1883                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
1884
1885         writel(tegra->sregs.fpci_error_masks,
1886                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
1887
1888         writel(tegra->sregs.intr_mask,
1889                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1890
1891         writel(tegra->sregs.ipfs_intr_enable,
1892                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
1893
1894         writel(tegra->sregs.ufpci_config,
1895                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
1896
1897         writel(tegra->sregs.clkgate_hysteresis,
1898                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1899
1900         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
1901                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
1902 }
1903
1904 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
1905 {
1906         struct platform_device *pdev = tegra->pdev;
1907         u32 reg, timeout = 0xff, cmd;
1908
1909         mutex_lock(&tegra->mbox_lock);
1910
1911         do {
1912                 writel(MBOX_OWNER_SW,
1913                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
1914                 reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
1915                 usleep_range(10, 20);
1916         } while (reg != MBOX_OWNER_SW && timeout--);
1917
1918         if ((timeout == 0) && (reg != MBOX_OWNER_SW)) {
1919                 dev_err(&pdev->dev, "Failed to set mbox message owner ID\n");
1920                 mutex_unlock(&tegra->mbox_lock);
1921                 return;
1922         }
1923
1924         writel((MBOX_CMD_MSG_ENABLED << MBOX_CMD_SHIFT),
1925                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
1926
1927         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1928         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
1929         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1930
1931         mutex_unlock(&tegra->mbox_lock);
1932 }
1933
1934 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
1935 {
1936         struct platform_device *pdev = tegra->pdev;
1937         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
1938         u32 phys_addr_lo;
1939         u32 HwReg;
1940         u16 nblocks;
1941         time_t fw_time;
1942         struct tm fw_tm;
1943         u8 hc_caplength;
1944         u32 usbsts, count = 0xff;
1945         struct xhci_cap_regs __iomem *cap_regs;
1946         struct xhci_op_regs __iomem *op_regs;
1947
1948         /* enable mbox interrupt */
1949         writel(readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD) | MBOX_INT_EN,
1950                 tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1951
1952         /* First thing, reset the ARU. By the time we get to
1953          * loading boot code below, reset would be complete.
1954          * alternatively we can busy wait on rst pending bit.
1955          */
1956         /* Don't reset during ELPG/LP0 exit path */
1957         if (resetARU) {
1958                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
1959                 usleep_range(1000, 2000);
1960         }
1961
1962         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
1963                 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
1964                                 csb_read(tegra, XUSB_FALC_CPUCTL));
1965                 return 0;
1966         }
1967
1968         /* update the phys_log_buffer and total_entries here */
1969         cfg_tbl->phys_addr_log_buffer = tegra->log.phys_addr;
1970         cfg_tbl->total_log_entries = FW_LOG_COUNT;
1971
1972         phys_addr_lo = tegra->firmware.dma;
1973         phys_addr_lo += sizeof(struct cfgtbl);
1974
1975         /* Program the size of DFI into ILOAD_ATTR */
1976         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
1977
1978         /* Boot code of the firmware reads the ILOAD_BASE_LO register
1979          * to get to the start of the dfi in system memory.
1980          */
1981         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
1982
1983         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
1984         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
1985
1986         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
1987         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
1988
1989         /* Invalidate L2IMEM. */
1990         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
1991
1992         /* Initiate fetch of Bootcode from system memory into L2IMEM.
1993          * Program BootCode location and size in system memory.
1994          */
1995         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
1996                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
1997                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
1998         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
1999                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
2000                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
2001         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
2002
2003         /* Trigger L2IMEM Load operation. */
2004         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
2005
2006         /* Setup Falcon Auto-fill */
2007         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
2008         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
2009                 nblocks += 1;
2010         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
2011
2012         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
2013         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
2014                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
2015         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
2016
2017         csb_write(tegra, XUSB_FALC_DMACTL, 0);
2018         msleep(50);
2019
2020         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
2021
2022         /* Start Falcon CPU */
2023         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
2024         usleep_range(1000, 2000);
2025
2026         fw_time = cfg_tbl->fwimg_created_time;
2027         time_to_tm(fw_time, 0, &fw_tm);
2028         dev_info(&pdev->dev,
2029                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
2030                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
2031                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
2032                 fw_tm.tm_min, fw_tm.tm_sec,
2033                 csb_read(tegra, XUSB_FALC_CPUCTL));
2034
2035         /* return fail if firmware status is not good */
2036         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
2037                 return -EFAULT;
2038
2039         cap_regs = IO_ADDRESS(tegra->host_phy_base);
2040         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
2041         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
2042
2043         /* wait for USBSTS_CNR to get set */
2044         do {
2045                 usbsts = ioread32(&op_regs->status);
2046         } while ((usbsts & STS_CNR) && count--);
2047
2048         if (!count && (usbsts & STS_CNR)) {
2049                 dev_err(&pdev->dev, "Controller not ready\n");
2050                 return -EFAULT;
2051         }
2052         return 0;
2053 }
2054
2055 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
2056         bool release)
2057 {
2058         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2059         u32 reg;
2060
2061         /* Issue is only applicable for T114 */
2062         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
2063                 return;
2064
2065         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2066         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2067                         USB2_OTG_PAD_PORT_MASK(2));
2068
2069         if (!release) {
2070                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2071                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2072                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2073                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2074                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2075                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2076         }
2077
2078         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2079 }
2080 /* SS ELPG Entry initiated by fw */
2081 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
2082 {
2083         struct xhci_hcd *xhci = tegra->xhci;
2084         u32 ret = 0;
2085
2086         must_have_sync_lock(tegra);
2087
2088         /* This is SS partition ELPG entry
2089          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
2090          */
2091
2092         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
2093          * only if it is sw initiated one
2094          */
2095
2096         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
2097          * SuperSpeed partition ELPG entry via mailbox protocol
2098          */
2099
2100         /* STEP 2: xHCI PEP driver and XUSB device mode driver
2101          * enable the XUSB wakeup interrupts for the SuperSpeed
2102          * and USB2.0 ports assigned to host.Section 4.1 Step 3
2103          */
2104         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2105
2106         /* STEP 3: xHCI PEP driver initiates the signal sequence
2107          * to enable the XUSB SSwake detection logic for the
2108          * SuperSpeed ports assigned to host.Section 4.1 Step 4
2109          */
2110         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, true);
2111
2112         /* STEP 4: System Power Management driver asserts reset
2113          * to XUSB SuperSpeed partition then disables its clocks
2114          */
2115         tegra_periph_reset_assert(tegra->ss_clk);
2116         clk_disable(tegra->ss_clk);
2117
2118         usleep_range(100, 200);
2119
2120         /* STEP 5: System Power Management driver disables the
2121          * XUSB SuperSpeed partition power rails.
2122          */
2123         debug_print_portsc(xhci);
2124
2125         /* tegra_powergate_partition also does partition reset assert */
2126         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
2127         if (ret) {
2128                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
2129                                 __func__);
2130                 /* TODO: error recovery? */
2131         }
2132         tegra->ss_pwr_gated = true;
2133
2134         /* STEP 6: xHCI PEP driver initiates the signal sequence
2135          * to enable the XUSB SSwake detection logic for the
2136          * SuperSpeed ports assigned to host.Section 4.1 Step 7
2137          */
2138         tegra_xhci_ss_vcore(tegra->bdata->portmap, true);
2139
2140         return ret;
2141 }
2142
2143 /* Host ELPG Entry */
2144 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
2145 {
2146         struct xhci_hcd *xhci = tegra->xhci;
2147         u32 ret;
2148
2149         must_have_sync_lock(tegra);
2150
2151         /* If ss is already powergated skip ss ctx save stuff */
2152         if (tegra->ss_pwr_gated) {
2153                 xhci_info(xhci, "%s: SS partition is already powergated\n",
2154                         __func__);
2155         } else {
2156                 ret = tegra_xhci_ss_elpg_entry(tegra);
2157                 if (ret) {
2158                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
2159                                 __func__, ret);
2160                         return ret;
2161                 }
2162         }
2163
2164         /* 1. IS INTR PENDING INT_PENDING=1 ? */
2165
2166         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
2167         tegra_xhci_save_xusb_ctx(tegra);
2168
2169         pmc_init(tegra, 1);
2170
2171         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2172         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2173                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2174
2175         /* STEP 4: Assert reset to host clk and disable host clk */
2176         tegra_periph_reset_assert(tegra->host_clk);
2177
2178         clk_disable(tegra->host_clk);
2179
2180         /* wait 150us */
2181         usleep_range(150, 200);
2182
2183         /* flush MC client of XUSB_HOST */
2184         tegra_powergate_mc_flush(TEGRA_POWERGATE_XUSBC);
2185
2186         /* STEP 4: Powergate host partition */
2187         /* tegra_powergate_partition also does partition reset assert */
2188         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
2189         if (ret) {
2190                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2191                         __func__, ret);
2192                 /* TODO: error handling? */
2193                 return ret;
2194         }
2195         tegra->host_pwr_gated = true;
2196
2197         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2198                 clk_disable(tegra->pll_re_vco_clk);
2199         clk_disable(tegra->emc_clk);
2200         /* set port ownership to SNPS */
2201         tegra_xhci_release_port_ownership(tegra, true);
2202
2203         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2204                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2205
2206         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
2207         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
2208                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
2209         return ret;
2210 }
2211
2212 /* SS ELPG Exit triggered by PADCTL irq */
2213 /**
2214  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
2215  *
2216  * This function must be called with tegra->sync_lock acquired.
2217  *
2218  * @tegra: xhci controller context
2219  * @return 0 for success, or error numbers
2220  */
2221 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2222 {
2223         struct xhci_hcd *xhci = tegra->xhci;
2224         int ret = 0;
2225
2226         must_have_sync_lock(tegra);
2227
2228         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
2229                         tegra->hs_wake_event || tegra->host_resume_req)) {
2230
2231                 /*
2232                  * PWR_UNGATE SS partition. XUSBA
2233                  * tegra_unpowergate_partition also does partition reset
2234                  * deassert
2235                  */
2236                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
2237                 if (ret) {
2238                         xhci_err(xhci,
2239                         "%s: could not unpowergate xusba partition %d\n",
2240                         __func__, ret);
2241                         goto out;
2242                 }
2243                 if (tegra->ss_wake_event)
2244                         tegra->ss_wake_event = false;
2245
2246         } else {
2247                 xhci_info(xhci, "%s: ss already power gated\n",
2248                         __func__);
2249                 return ret;
2250         }
2251
2252         /* Step 3: Enable clock to ss partition */
2253         clk_enable(tegra->ss_clk);
2254
2255         /* Step 4: Disable ss wake detection logic */
2256         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2257
2258         /* Step 4.1: Disable ss wake detection logic */
2259         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
2260
2261         /* wait 150us */
2262         usleep_range(150, 200);
2263
2264         /* Step 4.2: Disable ss wake detection logic */
2265         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
2266
2267         /* Step 6 Deassert reset for ss clks */
2268         tegra_periph_reset_deassert(tegra->ss_clk);
2269
2270         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
2271         tegra->ss_pwr_gated = false;
2272 out:
2273         return ret;
2274 }
2275
2276 static void ss_partition_elpg_exit_work(struct work_struct *work)
2277 {
2278         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2279                 ss_elpg_exit_work);
2280
2281         mutex_lock(&tegra->sync_lock);
2282         tegra_xhci_ss_partition_elpg_exit(tegra);
2283         mutex_unlock(&tegra->sync_lock);
2284 }
2285
2286 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
2287 static void update_remote_wakeup_ports_pmc(struct tegra_xhci_hcd *tegra)
2288 {
2289         struct xhci_hcd *xhci = tegra->xhci;
2290         u32 wake2_status;
2291
2292 #define PMC_WAKE2_STATUS        0x168
2293 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
2294
2295         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
2296
2297         if (wake2_status & PADCTL_WAKE) {
2298                 /* FIXME: This is customized for Dalmore, find a generic way */
2299                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
2300                 /* clear wake status */
2301                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
2302         }
2303
2304         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
2305                         __func__, tegra->usb3_rh_remote_wakeup_ports);
2306 }
2307
2308 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
2309 {
2310         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2311         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2312         int port, num_ports;
2313         unsigned long *remote_wakeup_ports;
2314         u32 portsc;
2315         __le32 __iomem  **port_array;
2316         unsigned char *rh;
2317         unsigned int retry = 64;
2318
2319
2320         if (hcd == xhci->shared_hcd) {
2321                 port_array = xhci->usb3_ports;
2322                 num_ports = xhci->num_usb3_ports;
2323                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
2324                 rh = "usb3 roothub";
2325         } else
2326                 return;
2327
2328         while (*remote_wakeup_ports && retry--) {
2329                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
2330                         portsc = xhci_readl(xhci, port_array[port]);
2331
2332                         if (!(portsc & PORT_CONNECT)) {
2333                                 /* nothing to do if already disconnected */
2334                                 clear_bit(port, remote_wakeup_ports);
2335                                 continue;
2336                         }
2337
2338                         if ((portsc & PORT_PLS_MASK) == XDEV_U0)
2339                                 clear_bit(port, remote_wakeup_ports);
2340                         else
2341                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
2342                                                 __func__, rh, port, portsc);
2343                 }
2344
2345                 if (*remote_wakeup_ports)
2346                         msleep(20); /* give some time, irq will direct U0 */
2347         }
2348
2349         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
2350                         *remote_wakeup_ports);
2351 }
2352
2353 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
2354 {
2355         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2356         u32 reg, utmip_rctrl_val, utmip_tctrl_val;
2357
2358         /* Program XUSB as port owner for all usb2 ports */
2359         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2360         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2361                         USB2_OTG_PAD_PORT_MASK(2));
2362         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
2363                 USB2_OTG_PAD_PORT_OWNER_XUSB(1) | USB2_OTG_PAD_PORT_MASK(2);
2364         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2365
2366         /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
2367          * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
2368          */
2369         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2370         reg &= ~((1 << 12) | (1 << 13));
2371         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2372
2373         /* wait 20us */
2374         usleep_range(20, 30);
2375
2376         /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
2377          * :: TCTRL and RCTRL
2378          */
2379         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl1_0);
2380         utmip_rctrl_val = RCTRL(reg);
2381         utmip_tctrl_val = TCTRL(reg);
2382
2383         /*
2384          * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
2385          * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
2386          */
2387         pmc_data.utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
2388         pmc_data.utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
2389
2390         xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
2391                 pmc_data.utmip_rctrl_val, pmc_data.utmip_tctrl_val);
2392
2393         /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
2394          * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
2395          */
2396         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2397         reg |= (1 << 13);
2398         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2399
2400         /* Program these values into PMC regiseter and program the
2401          * PMC override
2402          */
2403         reg = PMC_TCTRL_VAL(pmc_data.utmip_tctrl_val) |
2404                 PMC_RCTRL_VAL(pmc_data.utmip_rctrl_val);
2405         tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG, 0xffffffff, reg);
2406
2407         reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
2408         tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
2409
2410         /* Restore correct port ownership in padctl */
2411         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2412         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2413                         USB2_OTG_PAD_PORT_MASK(2));
2414         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2415                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2416         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2417                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2418         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2419                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2420         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2421 }
2422
2423 /* Host ELPG Exit triggered by PADCTL irq */
2424 /**
2425  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
2426  *
2427  * This function must be called with tegra->sync_lock acquired.
2428  *
2429  * @tegra: xhci controller context
2430  * @return 0 for success, or error numbers
2431  */
2432 static int
2433 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2434 {
2435         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2436         struct xhci_hcd *xhci = tegra->xhci;
2437         int ret = 0;
2438
2439         must_have_sync_lock(tegra);
2440
2441         if (!tegra->hc_in_elpg)
2442                 return 0;
2443
2444         clk_enable(tegra->emc_clk);
2445         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2446                 clk_enable(tegra->pll_re_vco_clk);
2447         /* Step 2: Enable clock to host partition */
2448         clk_enable(tegra->host_clk);
2449
2450         if (tegra->lp0_exit) {
2451                 u32 reg, oc_bits = 0;
2452
2453                 /* Issue is only applicable for T114 */
2454                 if (XUSB_DEVICE_ID_T114 == tegra->device_id)
2455                         tegra_xhci_war_for_tctrl_rctrl(tegra);
2456                 /* check if over current seen. Clear if present */
2457                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2458                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2459                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2460                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2461                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2462                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2463
2464                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2465                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
2466                 if (reg & oc_bits) {
2467                         xhci_info(xhci, "Over current detected. Clearing...\n");
2468                         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2469
2470                         usleep_range(100, 200);
2471
2472                         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2473                         if (reg & oc_bits)
2474                                 xhci_info(xhci, "Over current still present\n");
2475                 }
2476                 tegra_xhci_padctl_portmap_and_caps(tegra);
2477                 /* release clamps post deassert */
2478                 tegra->lp0_exit = false;
2479         }
2480
2481         /* Clear FLUSH_ENABLE of MC client */
2482         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
2483
2484         /* set port ownership back to xusb */
2485         tegra_xhci_release_port_ownership(tegra, false);
2486
2487         /*
2488          * PWR_UNGATE Host partition. XUSBC
2489          * tegra_unpowergate_partition also does partition reset deassert
2490          */
2491         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
2492         if (ret) {
2493                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2494                         __func__, ret);
2495                 goto out;
2496         }
2497
2498         /* Step 4: Deassert reset to host partition clk */
2499         tegra_periph_reset_deassert(tegra->host_clk);
2500
2501         /* Step 6.1: IPFS and XUSB BAR initialization */
2502         tegra_xhci_cfg(tegra);
2503
2504         /* Step 6.2: IPFS and XUSB related restore */
2505         tegra_xhci_restore_ctx(tegra);
2506
2507         /* Step 8: xhci spec related ctx restore
2508          * will be done in xhci_resume().Do it here.
2509          */
2510
2511         tegra_xhci_ss_partition_elpg_exit(tegra);
2512
2513         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
2514         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
2515                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
2516                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
2517         }
2518
2519         /* clear ovrd bits */
2520         tegra_xhci_rx_idle_mode_override(tegra, false);
2521
2522         /* Load firmware */
2523         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
2524                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
2525                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
2526                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
2527                         __func__,
2528                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
2529                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
2530                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
2531                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
2532                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
2533                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
2534                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
2535                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
2536                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
2537         debug_print_portsc(xhci);
2538
2539         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
2540         if (ret < 0) {
2541                 xhci_err(xhci, "%s: failed to load firmware %d\n",
2542                         __func__, ret);
2543                 goto out;
2544         }
2545
2546         pmc_init(tegra, 0);
2547
2548         tegra->hc_in_elpg = false;
2549         ret = xhci_resume(tegra->xhci, 0);
2550         if (ret) {
2551                 xhci_err(xhci, "%s: could not resume right %d\n",
2552                                 __func__, ret);
2553                 goto out;
2554         }
2555
2556         update_remote_wakeup_ports_pmc(tegra);
2557
2558         if (tegra->hs_wake_event)
2559                 tegra->hs_wake_event = false;
2560
2561         if (tegra->host_resume_req)
2562                 tegra->host_resume_req = false;
2563
2564         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
2565                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
2566
2567         tegra->host_pwr_gated = false;
2568 out:
2569         return ret;
2570 }
2571
2572 static void host_partition_elpg_exit_work(struct work_struct *work)
2573 {
2574         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2575                 host_elpg_exit_work);
2576
2577         mutex_lock(&tegra->sync_lock);
2578         tegra_xhci_host_partition_elpg_exit(tegra);
2579         mutex_unlock(&tegra->sync_lock);
2580 }
2581
2582 /* Mailbox handling function. This function handles requests
2583  * from firmware and communicates with clock and powergating
2584  * module to alter clock rates and to power gate/ungate xusb
2585  * partitions.
2586  *
2587  * Following is the structure of mailbox messages.
2588  * bit 31:28 - msg type
2589  * bits 27:0 - mbox data
2590  * FIXME:  Check if we can just call clock functions like below
2591  * or should we schedule it for calling later ?
2592  */
2593
2594 static void
2595 tegra_xhci_process_mbox_message(struct work_struct *work)
2596 {
2597         u32 sw_resp = 0, cmd, data_in, fw_msg;
2598         int ret = 0;
2599         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2600                                         mbox_work);
2601         struct xhci_hcd *xhci = tegra->xhci;
2602         unsigned int freq_khz;
2603
2604         mutex_lock(&tegra->mbox_lock);
2605
2606         /* get the owner id */
2607         tegra->mbox_owner = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2608         tegra->mbox_owner &= MBOX_OWNER_ID_MASK;
2609
2610         /* get the mbox message from firmware */
2611         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
2612
2613         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2614         if (data_in) {
2615                 mutex_unlock(&tegra->mbox_lock);
2616                 return;
2617         }
2618
2619         /* get cmd type and cmd data */
2620         tegra->cmd_type = (fw_msg & MBOX_CMD_TYPE_MASK) >> MBOX_CMD_SHIFT;
2621         tegra->cmd_data = (fw_msg & MBOX_CMD_DATA_MASK);
2622
2623         /* decode the message and make appropriate requests to
2624          * clock or powergating module.
2625          */
2626
2627         switch (tegra->cmd_type) {
2628         case MBOX_CMD_INC_FALC_CLOCK:
2629         case MBOX_CMD_DEC_FALC_CLOCK:
2630                 ret = tegra_xusb_request_clk_rate(
2631                                 tegra,
2632                                 tegra->falc_clk,
2633                                 tegra->cmd_data,
2634                                 &sw_resp);
2635                 if (ret)
2636                         xhci_err(xhci, "%s: could not set required falc rate\n",
2637                                 __func__);
2638                 goto send_sw_response;
2639         case MBOX_CMD_INC_SSPI_CLOCK:
2640         case MBOX_CMD_DEC_SSPI_CLOCK:
2641                 ret = tegra_xusb_request_clk_rate(
2642                                 tegra,
2643                                 tegra->ss_src_clk,
2644                                 tegra->cmd_data,
2645                                 &sw_resp);
2646                 if (ret)
2647                         xhci_err(xhci, "%s: could not set required ss rate.\n",
2648                                 __func__);
2649                 goto send_sw_response;
2650         case MBOX_CMD_SET_BW:
2651                 /* fw sends BW request in MByte/sec */
2652                 freq_khz = tegra_emc_bw_to_freq_req(tegra->cmd_data << 10);
2653                 clk_set_rate(tegra->emc_clk, freq_khz * 1000);
2654
2655                 /* clear MBOX_SMI_INT_EN bit */
2656                 cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2657                 cmd &= ~MBOX_SMI_INT_EN;
2658                 writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2659
2660                 /* clear mbox owner as ACK will not be sent for this request */
2661                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2662                 break;
2663         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
2664                 tegra_xhci_save_dfe_ctle_context(tegra, tegra->cmd_data);
2665                 tegra_xhci_restore_dfe_ctle_context(tegra, tegra->cmd_data);
2666                 /* SATA lane also if USB3_SS port1 mapped to it */
2667                 if (tegra->cmd_data == 0x1 &&
2668                         XUSB_DEVICE_ID_T114 != tegra->device_id &&
2669                                 tegra->bdata->lane_owner & BIT(0)) {
2670                         tegra_xhci_save_dfe_ctle_context(tegra, 3);
2671                         tegra_xhci_restore_dfe_ctle_context(tegra, 3);
2672                 }
2673
2674                 sw_resp |= (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
2675                 goto send_sw_response;
2676         case MBOX_CMD_ACK:
2677                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2678                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2679                 break;
2680         case MBOX_CMD_NACK:
2681                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2682                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2683                 break;
2684         default:
2685                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
2686                                 __func__, tegra->cmd_type);
2687         }
2688         mutex_unlock(&tegra->mbox_lock);
2689         return;
2690
2691 send_sw_response:
2692         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2693         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2694         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
2695         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2696
2697         mutex_unlock(&tegra->mbox_lock);
2698 }
2699
2700 static irqreturn_t tegra_xhci_xusb_host_irq(int irq, void *ptrdev)
2701 {
2702         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2703         struct xhci_hcd *xhci = tegra->xhci;
2704
2705         xhci_dbg(xhci, "%s", __func__);
2706         return IRQ_HANDLED;
2707 }
2708
2709 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
2710 {
2711         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2712         struct xhci_hcd *xhci = tegra->xhci;
2713         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2714         u32 elpg_program0 = 0;
2715
2716         spin_lock(&tegra->lock);
2717
2718         tegra->last_jiffies = jiffies;
2719
2720         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
2721         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
2722
2723         /* Clear the interrupt cause. We already read the intr status. */
2724         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2725         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
2726
2727         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
2728         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
2729                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2730         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
2731                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
2732         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
2733                 __func__,
2734                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad0_ctl0_0));
2735         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
2736                 __func__,
2737                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad1_ctl0_0));
2738         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
2739                 __func__,
2740                 readl(tegra->padctl_base + padregs->usb2_bchrg_bias_pad_0));
2741
2742         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
2743                 tegra->ss_wake_event = true;
2744         else if (elpg_program0 &
2745                         (USB2_PORT0_WAKEUP_EVENT | USB2_PORT1_WAKEUP_EVENT))
2746                 tegra->hs_wake_event = true;
2747
2748         if (tegra->ss_wake_event || tegra->hs_wake_event) {
2749                 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
2750                         xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
2751                         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
2752                 } else if (tegra->ss_pwr_gated
2753                                 && tegra->host_pwr_gated) {
2754                         xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
2755                                 __func__);
2756                         schedule_work(&tegra->host_elpg_exit_work);
2757                 }
2758         } else {
2759                 xhci_err(xhci, "error: wake due to no hs/ss event\n");
2760                 tegra_usb_pad_reg_write(padregs->elpg_program_0, 0xffffffff);
2761         }
2762         spin_unlock(&tegra->lock);
2763         return IRQ_HANDLED;
2764 }
2765
2766 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
2767 {
2768         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2769         u32 temp;
2770
2771         spin_lock(&tegra->lock);
2772
2773         /* clear the mbox intr status 1st thing. Other
2774          * bits are W1C bits, so just write to SMI bit.
2775          */
2776
2777         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
2778
2779         /* write 1 to clear SMI INTR en bit ( bit 3 ) */
2780         temp = MBOX_SMI_INTR_EN;
2781         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
2782
2783         schedule_work(&tegra->mbox_work);
2784
2785         spin_unlock(&tegra->lock);
2786         return IRQ_HANDLED;
2787 }
2788
2789 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
2790 {
2791         /*
2792          * As of now platform drivers don't provide MSI support so we ensure
2793          * here that the generic code does not try to make a pci_dev from our
2794          * dev struct in order to setup MSI
2795          */
2796         xhci->quirks |= XHCI_BROKEN_MSI;
2797         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
2798 }
2799
2800 /* called during probe() after chip reset completes */
2801 static int xhci_plat_setup(struct usb_hcd *hcd)
2802 {
2803         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
2804 }
2805
2806 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
2807         const char *name, void __iomem **region)
2808 {
2809         struct resource *res;
2810         void __iomem *mem;
2811
2812         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
2813         if (!res) {
2814                 dev_err(&pdev->dev, "memory resource %s doesn't exist\n", name);
2815                 return -ENODEV;
2816         }
2817
2818         mem = devm_request_and_ioremap(&pdev->dev, res);
2819         if (!mem) {
2820                 dev_err(&pdev->dev, "failed to ioremap for %s\n", name);
2821                 return -EFAULT;
2822         }
2823         *region = mem;
2824
2825         return 0;
2826 }
2827
2828 static int tegra_xhci_request_irq(struct platform_device *pdev,
2829         const char *rscname, irq_handler_t handler, unsigned long irqflags,
2830         const char *devname, int *irq_no)
2831 {
2832         int ret;
2833         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2834         struct resource *res;
2835
2836         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, rscname);
2837         if (!res) {
2838                 dev_err(&pdev->dev, "irq resource %s doesn't exist\n", rscname);
2839                 return -ENODEV;
2840         }
2841
2842         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
2843                         devname, tegra);
2844         if (ret != 0) {
2845                 dev_err(&pdev->dev,
2846                         "failed to request_irq for %s (irq %d), error = %d\n",
2847                         devname, res->start, ret);
2848                 return ret;
2849         }
2850         *irq_no = res->start;
2851
2852         return 0;
2853 }
2854
2855 #ifdef CONFIG_PM
2856
2857 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
2858 {
2859         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2860         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2861         int err = 0;
2862         unsigned long flags;
2863
2864         mutex_lock(&tegra->sync_lock);
2865
2866         if (xhci->shared_hcd == hcd) {
2867                 tegra->usb3_rh_suspend = true;
2868                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
2869         } else if (xhci->main_hcd == hcd) {
2870                 tegra->usb2_rh_suspend = true;
2871                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
2872         }
2873
2874         WARN_ON(tegra->hc_in_elpg);
2875
2876         /* suspend xhci bus. This will also set remote mask */
2877         err = xhci_bus_suspend(hcd);
2878         if (err) {
2879                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
2880                                 __func__, err);
2881                 goto xhci_bus_suspend_failed;
2882         }
2883
2884         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
2885                 goto done; /* one of the root hubs is still working */
2886
2887         spin_lock_irqsave(&tegra->lock, flags);
2888         tegra->hc_in_elpg = true;
2889         spin_unlock_irqrestore(&tegra->lock, flags);
2890
2891         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
2892
2893         /* save xhci spec ctx. Already done by xhci_suspend */
2894         err = xhci_suspend(tegra->xhci);
2895         if (err) {
2896                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
2897                 goto xhci_suspend_failed;
2898         }
2899
2900         /* Powergate host. Include ss power gate if not already done */
2901         err = tegra_xhci_host_elpg_entry(tegra);
2902         if (err) {
2903                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
2904                                 __func__, err);
2905                 goto tegra_xhci_host_elpg_entry_failed;
2906         }
2907
2908         /* At this point,ensure ss/hs intr enables are always on */
2909         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2910         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2911
2912 done:
2913         /* pads are disabled only if usb2 root hub in xusb is idle */
2914         /* pads will actually be disabled only when all usb2 ports are idle */
2915         if (xhci->main_hcd == hcd) {
2916                 utmi_phy_pad_disable();
2917                 utmi_phy_iddq_override(true);
2918         }
2919         mutex_unlock(&tegra->sync_lock);
2920         return 0;
2921
2922 tegra_xhci_host_elpg_entry_failed:
2923
2924 xhci_suspend_failed:
2925         tegra->hc_in_elpg = false;
2926 xhci_bus_suspend_failed:
2927         if (xhci->shared_hcd == hcd)
2928                 tegra->usb3_rh_suspend = false;
2929         else if (xhci->main_hcd == hcd)
2930                 tegra->usb2_rh_suspend = false;
2931
2932         mutex_unlock(&tegra->sync_lock);
2933         return err;
2934 }
2935
2936 /* First, USB2HCD and then USB3HCD resume will be called */
2937 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
2938 {
2939         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2940         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2941         int err = 0;
2942
2943         mutex_lock(&tegra->sync_lock);
2944
2945         tegra->host_resume_req = true;
2946
2947         if (xhci->shared_hcd == hcd)
2948                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
2949         else if (xhci->main_hcd == hcd)
2950                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
2951
2952         /* pads are disabled only if usb2 root hub in xusb is idle */
2953         /* pads will actually be disabled only when all usb2 ports are idle */
2954         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
2955                 utmi_phy_pad_enable();
2956                 utmi_phy_iddq_override(false);
2957         }
2958         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
2959                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
2960                         tegra_xhci_host_partition_elpg_exit(tegra);
2961         }
2962
2963          /* handle remote wakeup before resuming bus */
2964         wait_remote_wakeup_ports(hcd);
2965
2966         err = xhci_bus_resume(hcd);
2967         if (err) {
2968                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
2969                                 __func__, err);
2970                 goto xhci_bus_resume_failed;
2971         }
2972
2973         if (xhci->shared_hcd == hcd)
2974                 tegra->usb3_rh_suspend = false;
2975         else if (xhci->main_hcd == hcd)
2976                 tegra->usb2_rh_suspend = false;
2977
2978         mutex_unlock(&tegra->sync_lock);
2979         return 0;
2980
2981 xhci_bus_resume_failed:
2982         /* TODO: reverse elpg? */
2983         mutex_unlock(&tegra->sync_lock);
2984         return err;
2985 }
2986 #endif
2987
2988 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
2989 {
2990         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2991         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2992         irqreturn_t iret = IRQ_HANDLED;
2993         u32 status;
2994
2995         spin_lock(&tegra->lock);
2996         if (tegra->hc_in_elpg) {
2997                 spin_lock(&xhci->lock);
2998                 if (HCD_HW_ACCESSIBLE(hcd)) {
2999                         status = xhci_readl(xhci, &xhci->op_regs->status);
3000                         status |= STS_EINT;
3001                         xhci_writel(xhci, status, &xhci->op_regs->status);
3002                 }
3003                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
3004                                 __func__);
3005                 schedule_work(&tegra->host_elpg_exit_work);
3006                 spin_unlock(&xhci->lock);
3007         } else
3008                 iret = xhci_irq(hcd);
3009         spin_unlock(&tegra->lock);
3010
3011         return iret;
3012 }
3013
3014
3015 static const struct hc_driver tegra_plat_xhci_driver = {
3016         .description =          "tegra-xhci",
3017         .product_desc =         "Nvidia xHCI Host Controller",
3018         .hcd_priv_size =        sizeof(struct xhci_hcd *),
3019
3020         /*
3021          * generic hardware linkage
3022          */
3023         .irq =                  tegra_xhci_irq,
3024         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
3025
3026         /*
3027          * basic lifecycle operations
3028          */
3029         .reset =                xhci_plat_setup,
3030         .start =                xhci_run,
3031         .stop =                 xhci_stop,
3032         .shutdown =             xhci_shutdown,
3033
3034         /*
3035          * managing i/o requests and associated device resources
3036          */
3037         .urb_enqueue =          xhci_urb_enqueue,
3038         .urb_dequeue =          xhci_urb_dequeue,
3039         .alloc_dev =            xhci_alloc_dev,
3040         .free_dev =             xhci_free_dev,
3041         .alloc_streams =        xhci_alloc_streams,
3042         .free_streams =         xhci_free_streams,
3043         .add_endpoint =         xhci_add_endpoint,
3044         .drop_endpoint =        xhci_drop_endpoint,
3045         .endpoint_reset =       xhci_endpoint_reset,
3046         .check_bandwidth =      xhci_check_bandwidth,
3047         .reset_bandwidth =      xhci_reset_bandwidth,
3048         .address_device =       xhci_address_device,
3049         .update_hub_device =    xhci_update_hub_device,
3050         .reset_device =         xhci_discover_or_reset_device,
3051
3052         /*
3053          * scheduling support
3054          */
3055         .get_frame_number =     xhci_get_frame,
3056
3057         /* Root hub support */
3058         .hub_control =          xhci_hub_control,
3059         .hub_status_data =      xhci_hub_status_data,
3060
3061 #ifdef CONFIG_PM
3062         .bus_suspend =          tegra_xhci_bus_suspend,
3063         .bus_resume =           tegra_xhci_bus_resume,
3064 #endif
3065 };
3066
3067 #ifdef CONFIG_PM
3068 static int
3069 tegra_xhci_suspend(struct platform_device *pdev,
3070                                                 pm_message_t state)
3071 {
3072         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3073         struct xhci_hcd *xhci = tegra->xhci;
3074
3075         int ret = 0;
3076
3077         mutex_lock(&tegra->sync_lock);
3078         if (!tegra->hc_in_elpg) {
3079                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
3080                                 __func__);
3081                 mutex_unlock(&tegra->sync_lock);
3082                 return -EBUSY;
3083         }
3084         mutex_unlock(&tegra->sync_lock);
3085
3086         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3087         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3088
3089         /* enable_irq_wake for ss ports */
3090         ret = enable_irq_wake(tegra->padctl_irq);
3091         if (ret < 0) {
3092                 xhci_err(xhci,
3093                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
3094                 __func__, tegra->padctl_irq, ret);
3095         }
3096
3097         /* enable_irq_wake for hs/fs/ls ports */
3098         ret = enable_irq_wake(tegra->usb3_irq);
3099         if (ret < 0) {
3100                 xhci_err(xhci,
3101                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
3102                 __func__, tegra->usb3_irq, ret);
3103         }
3104         regulator_disable(tegra->xusb_s1p8v_reg);
3105         regulator_disable(tegra->xusb_s1p05v_reg);
3106         tegra_usb2_clocks_deinit(tegra);
3107
3108         return ret;
3109 }
3110
3111 static int
3112 tegra_xhci_resume(struct platform_device *pdev)
3113 {
3114         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3115
3116         dev_dbg(&pdev->dev, "%s\n", __func__);
3117
3118         tegra->last_jiffies = jiffies;
3119
3120         disable_irq_wake(tegra->padctl_irq);
3121         disable_irq_wake(tegra->usb3_irq);
3122         tegra->lp0_exit = true;
3123
3124         regulator_enable(tegra->xusb_s1p05v_reg);
3125         regulator_enable(tegra->xusb_s1p8v_reg);
3126         tegra_usb2_clocks_init(tegra);
3127
3128         return 0;
3129 }
3130 #endif
3131
3132
3133 static int init_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3134 {
3135         struct platform_device *pdev = tegra->pdev;
3136         void __iomem *fw_mmio_base;
3137         phys_addr_t fw_mem_phy_addr;
3138         size_t fw_size;
3139         dma_addr_t fw_dma;
3140 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3141         int ret;
3142 #endif
3143
3144         /* bootloader saved firmware memory address in PMC SCRATCH34 register */
3145         fw_mem_phy_addr = tegra_usb_pmc_reg_read(PMC_SCRATCH34);
3146
3147         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3148                         fw_mem_phy_addr, sizeof(struct cfgtbl));
3149
3150         if (!fw_mmio_base) {
3151                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3152                                         fw_mem_phy_addr);
3153                         return -ENOMEM;
3154         }
3155
3156         fw_size = ioread32(fw_mmio_base + FW_SIZE_OFFSET);
3157         devm_iounmap(&pdev->dev, fw_mmio_base);
3158
3159         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3160                         fw_mem_phy_addr, fw_size);
3161         if (!fw_mmio_base) {
3162                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3163                                         fw_mem_phy_addr);
3164                         return -ENOMEM;
3165         }
3166
3167         dev_info(&pdev->dev, "Firmware Memory: phy 0x%x mapped 0x%p (%d Bytes)\n",
3168                         fw_mem_phy_addr, fw_mmio_base, fw_size);
3169
3170 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3171         fw_dma = dma_map_linear(&pdev->dev, fw_mem_phy_addr, fw_size,
3172                         DMA_TO_DEVICE);
3173         if (fw_dma == DMA_ERROR_CODE) {
3174                 dev_err(&pdev->dev, "%s: dma_map_linear failed\n",
3175                                 __func__);
3176                 ret = -ENOMEM;
3177                 goto error_iounmap;
3178         }
3179 #else
3180         fw_dma = fw_mem_phy_addr;
3181 #endif
3182         dev_info(&pdev->dev, "Firmware DMA Memory: dma 0x%p (%d Bytes)\n",
3183                         (void *) fw_dma, fw_size);
3184
3185         /* all set and ready to go */
3186         tegra->firmware.data = fw_mmio_base;
3187         tegra->firmware.dma = fw_dma;
3188         tegra->firmware.size = fw_size;
3189
3190         return 0;
3191
3192 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3193 error_iounmap:
3194         devm_iounmap(&pdev->dev, fw_mmio_base);
3195         return ret;
3196 #endif
3197 }
3198
3199 static void deinit_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3200 {
3201         struct platform_device *pdev = tegra->pdev;
3202         void __iomem *fw_mmio_base = tegra->firmware.data;
3203
3204 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3205         dma_unmap_single(&pdev->dev, tegra->firmware.dma,
3206                         tegra->firmware.size, DMA_TO_DEVICE);
3207 #endif
3208         devm_iounmap(&pdev->dev, fw_mmio_base);
3209
3210         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
3211 }
3212
3213 static int init_firmware(struct tegra_xhci_hcd *tegra)
3214 {
3215         return init_bootloader_firmware(tegra);
3216 }
3217
3218 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
3219 {
3220         deinit_bootloader_firmware(tegra);
3221 }
3222
3223 static struct tegra_xusb_padctl_regs t114_padregs_offset = {
3224         .boot_media_0                   = 0x0,
3225         .usb2_pad_mux_0                 = 0x4,
3226         .usb2_port_cap_0                = 0x8,
3227         .snps_oc_map_0                  = 0xc,
3228         .usb2_oc_map_0                  = 0x10,
3229         .ss_port_map_0                  = 0x14,
3230         .oc_det_0                       = 0x18,
3231         .elpg_program_0                 = 0x1c,
3232         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3233         .usb2_bchrg_otgpad0_ctl1_0      = 0xffff,
3234         .usb2_bchrg_otgpad1_ctl0_0      = 0x24,
3235         .usb2_bchrg_otgpad1_ctl1_0      = 0xffff,
3236         .usb2_bchrg_otgpad2_ctl0_0      = 0xffff,
3237         .usb2_bchrg_otgpad2_ctl1_0      = 0xffff,
3238         .usb2_bchrg_bias_pad_0          = 0x28,
3239         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
3240         .iophy_pll_p0_ctl1_0            = 0x30,
3241         .iophy_pll_p0_ctl2_0            = 0x34,
3242         .iophy_pll_p0_ctl3_0            = 0x38,
3243         .iophy_pll_p0_ctl4_0            = 0x3c,
3244         .iophy_usb3_pad0_ctl1_0         = 0x40,
3245         .iophy_usb3_pad1_ctl1_0         = 0x44,
3246         .iophy_usb3_pad0_ctl2_0         = 0x48,
3247         .iophy_usb3_pad1_ctl2_0         = 0x4c,
3248         .iophy_usb3_pad0_ctl3_0         = 0x50,
3249         .iophy_usb3_pad1_ctl3_0         = 0x54,
3250         .iophy_usb3_pad0_ctl4_0         = 0x58,
3251         .iophy_usb3_pad1_ctl4_0         = 0x5c,
3252         .iophy_misc_pad_p0_ctl1_0       = 0x60,
3253         .iophy_misc_pad_p1_ctl1_0       = 0x64,
3254         .iophy_misc_pad_p0_ctl2_0       = 0x68,
3255         .iophy_misc_pad_p1_ctl2_0       = 0x6c,
3256         .iophy_misc_pad_p0_ctl3_0       = 0x70,
3257         .iophy_misc_pad_p1_ctl3_0       = 0x74,
3258         .iophy_misc_pad_p0_ctl4_0       = 0x78,
3259         .iophy_misc_pad_p1_ctl4_0       = 0x7c,
3260         .iophy_misc_pad_p0_ctl5_0       = 0x80,
3261         .iophy_misc_pad_p1_ctl5_0       = 0x84,
3262         .iophy_misc_pad_p0_ctl6_0       = 0x88,
3263         .iophy_misc_pad_p1_ctl6_0       = 0x8c,
3264         .usb2_otg_pad0_ctl0_0           = 0x90,
3265         .usb2_otg_pad1_ctl0_0           = 0x94,
3266         .usb2_otg_pad2_ctl0_0           = 0xffff,
3267         .usb2_otg_pad0_ctl1_0           = 0x98,
3268         .usb2_otg_pad1_ctl1_0           = 0x9c,
3269         .usb2_otg_pad2_ctl1_0           = 0xffff,
3270         .usb2_bias_pad_ctl0_0           = 0xa0,
3271         .usb2_bias_pad_ctl1_0           = 0xa4,
3272         .usb2_hsic_pad0_ctl0_0          = 0xa8,
3273         .usb2_hsic_pad1_ctl0_0          = 0xac,
3274         .usb2_hsic_pad0_ctl1_0          = 0xb0,
3275         .usb2_hsic_pad1_ctl1_0          = 0xb4,
3276         .usb2_hsic_pad0_ctl2_0          = 0xb8,
3277         .usb2_hsic_pad1_ctl2_0          = 0xbc,
3278         .ulpi_link_trim_ctl0            = 0xc0,
3279         .ulpi_null_clk_trim_ctl0        = 0xc4,
3280         .hsic_strb_trim_ctl0            = 0xc8,
3281         .wake_ctl0                      = 0xcc,
3282         .pm_spare0                      = 0xd0,
3283         .iophy_misc_pad_p2_ctl1_0       = 0xffff,
3284         .iophy_misc_pad_p3_ctl1_0       = 0xffff,
3285         .iophy_misc_pad_p4_ctl1_0       = 0xffff,
3286         .iophy_misc_pad_p2_ctl2_0       = 0xffff,
3287         .iophy_misc_pad_p3_ctl2_0       = 0xffff,
3288         .iophy_misc_pad_p4_ctl2_0       = 0xffff,
3289         .iophy_misc_pad_p2_ctl3_0       = 0xffff,
3290         .iophy_misc_pad_p3_ctl3_0       = 0xffff,
3291         .iophy_misc_pad_p4_ctl3_0       = 0xffff,
3292         .iophy_misc_pad_p2_ctl4_0       = 0xffff,
3293         .iophy_misc_pad_p3_ctl4_0       = 0xffff,
3294         .iophy_misc_pad_p4_ctl4_0       = 0xffff,
3295         .iophy_misc_pad_p2_ctl5_0       = 0xffff,
3296         .iophy_misc_pad_p3_ctl5_0       = 0xffff,
3297         .iophy_misc_pad_p4_ctl5_0       = 0xffff,
3298         .iophy_misc_pad_p2_ctl6_0       = 0xffff,
3299         .iophy_misc_pad_p3_ctl6_0       = 0xffff,
3300         .iophy_misc_pad_p4_ctl6_0       = 0xffff,
3301         .usb3_pad_mux_0                 = 0xffff,
3302         .iophy_pll_s0_ctl1_0            = 0xffff,
3303         .iophy_pll_s0_ctl2_0            = 0xffff,
3304         .iophy_pll_s0_ctl3_0            = 0xffff,
3305         .iophy_pll_s0_ctl4_0            = 0xffff,
3306         .iophy_misc_pad_s0_ctl1_0       = 0xffff,
3307         .iophy_misc_pad_s0_ctl2_0       = 0xffff,
3308         .iophy_misc_pad_s0_ctl3_0       = 0xffff,
3309         .iophy_misc_pad_s0_ctl4_0       = 0xffff,
3310         .iophy_misc_pad_s0_ctl5_0       = 0xffff,
3311         .iophy_misc_pad_s0_ctl6_0       = 0xffff,
3312 };
3313
3314 static struct tegra_xusb_padctl_regs t124_padregs_offset = {
3315         .boot_media_0                   = 0x0,
3316         .usb2_pad_mux_0                 = 0x4,
3317         .usb2_port_cap_0                = 0x8,
3318         .snps_oc_map_0                  = 0xc,
3319         .usb2_oc_map_0                  = 0x10,
3320         .ss_port_map_0                  = 0x14,
3321         .oc_det_0                       = 0x18,
3322         .elpg_program_0                 = 0x1c,
3323         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3324         .usb2_bchrg_otgpad0_ctl1_0      = 0x24,
3325         .usb2_bchrg_otgpad1_ctl0_0      = 0x28,
3326         .usb2_bchrg_otgpad1_ctl1_0      = 0x2c,
3327         .usb2_bchrg_otgpad2_ctl0_0      = 0x30,
3328         .usb2_bchrg_otgpad2_ctl1_0      = 0x34,
3329         .usb2_bchrg_bias_pad_0          = 0x38,
3330         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
3331         .iophy_pll_p0_ctl1_0            = 0x40,
3332         .iophy_pll_p0_ctl2_0            = 0x44,
3333         .iophy_pll_p0_ctl3_0            = 0x48,
3334         .iophy_pll_p0_ctl4_0            = 0x4c,
3335         .iophy_usb3_pad0_ctl1_0         = 0x50,
3336         .iophy_usb3_pad1_ctl1_0         = 0x54,
3337         .iophy_usb3_pad0_ctl2_0         = 0x58,
3338         .iophy_usb3_pad1_ctl2_0         = 0x5c,
3339         .iophy_usb3_pad0_ctl3_0         = 0x60,
3340         .iophy_usb3_pad1_ctl3_0         = 0x64,
3341         .iophy_usb3_pad0_ctl4_0         = 0x68,
3342         .iophy_usb3_pad1_ctl4_0         = 0x6c,
3343         .iophy_misc_pad_p0_ctl1_0       = 0x70,
3344         .iophy_misc_pad_p1_ctl1_0       = 0x74,
3345         .iophy_misc_pad_p0_ctl2_0       = 0x78,
3346         .iophy_misc_pad_p1_ctl2_0       = 0x7c,
3347         .iophy_misc_pad_p0_ctl3_0       = 0x80,
3348         .iophy_misc_pad_p1_ctl3_0       = 0x84,
3349         .iophy_misc_pad_p0_ctl4_0       = 0x88,
3350         .iophy_misc_pad_p1_ctl4_0       = 0x8c,
3351         .iophy_misc_pad_p0_ctl5_0       = 0x90,
3352         .iophy_misc_pad_p1_ctl5_0       = 0x94,
3353         .iophy_misc_pad_p0_ctl6_0       = 0x98,
3354         .iophy_misc_pad_p1_ctl6_0       = 0x9c,
3355         .usb2_otg_pad0_ctl0_0           = 0xa0,
3356         .usb2_otg_pad1_ctl0_0           = 0xa4,
3357         .usb2_otg_pad2_ctl0_0           = 0xa8,
3358         .usb2_otg_pad0_ctl1_0           = 0xac,
3359         .usb2_otg_pad1_ctl1_0           = 0xb0,
3360         .usb2_otg_pad2_ctl1_0           = 0xb4,
3361         .usb2_bias_pad_ctl0_0           = 0xb8,
3362         .usb2_bias_pad_ctl1_0           = 0xbc,
3363         .usb2_hsic_pad0_ctl0_0          = 0xc0,
3364         .usb2_hsic_pad1_ctl0_0          = 0xc4,
3365         .usb2_hsic_pad0_ctl1_0          = 0xc8,
3366         .usb2_hsic_pad1_ctl1_0          = 0xcc,
3367         .usb2_hsic_pad0_ctl2_0          = 0xd0,
3368         .usb2_hsic_pad1_ctl2_0          = 0xd4,
3369         .ulpi_link_trim_ctl0            = 0xd8,
3370         .ulpi_null_clk_trim_ctl0        = 0xdc,
3371         .hsic_strb_trim_ctl0            = 0xe0,
3372         .wake_ctl0                      = 0xe4,
3373         .pm_spare0                      = 0xe8,
3374         .iophy_misc_pad_p2_ctl1_0       = 0xec,
3375         .iophy_misc_pad_p3_ctl1_0       = 0xf0,
3376         .iophy_misc_pad_p4_ctl1_0       = 0xf4,
3377         .iophy_misc_pad_p2_ctl2_0       = 0xf8,
3378         .iophy_misc_pad_p3_ctl2_0       = 0xfc,
3379         .iophy_misc_pad_p4_ctl2_0       = 0x100,
3380         .iophy_misc_pad_p2_ctl3_0       = 0x104,
3381         .iophy_misc_pad_p3_ctl3_0       = 0x108,
3382         .iophy_misc_pad_p4_ctl3_0       = 0x10c,
3383         .iophy_misc_pad_p2_ctl4_0       = 0x110,
3384         .iophy_misc_pad_p3_ctl4_0       = 0x114,
3385         .iophy_misc_pad_p4_ctl4_0       = 0x118,
3386         .iophy_misc_pad_p2_ctl5_0       = 0x11c,
3387         .iophy_misc_pad_p3_ctl5_0       = 0x120,
3388         .iophy_misc_pad_p4_ctl5_0       = 0x124,
3389         .iophy_misc_pad_p2_ctl6_0       = 0x128,
3390         .iophy_misc_pad_p3_ctl6_0       = 0x12c,
3391         .iophy_misc_pad_p4_ctl6_0       = 0x130,
3392         .usb3_pad_mux_0                 = 0x134,
3393         .iophy_pll_s0_ctl1_0            = 0x138,
3394         .iophy_pll_s0_ctl2_0            = 0x13c,
3395         .iophy_pll_s0_ctl3_0            = 0x140,
3396         .iophy_pll_s0_ctl4_0            = 0x144,
3397         .iophy_misc_pad_s0_ctl1_0       = 0x148,
3398         .iophy_misc_pad_s0_ctl2_0       = 0x14c,
3399         .iophy_misc_pad_s0_ctl3_0       = 0x150,
3400         .iophy_misc_pad_s0_ctl4_0       = 0x154,
3401         .iophy_misc_pad_s0_ctl5_0       = 0x158,
3402         .iophy_misc_pad_s0_ctl6_0       = 0x15c,
3403 };
3404
3405 /* TODO: we have to refine error handling in tegra_xhci_probe() */
3406 static int tegra_xhci_probe(struct platform_device *pdev)
3407 {
3408         const struct hc_driver *driver;
3409         struct xhci_hcd *xhci;
3410         struct tegra_xhci_hcd *tegra;
3411         struct resource *res;
3412         struct usb_hcd  *hcd;
3413         u32 pmc_reg, val;
3414         int ret;
3415         int irq;
3416
3417         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
3418
3419         if (usb_disabled())
3420                 return -ENODEV;
3421
3422         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
3423         if (!tegra) {
3424                 dev_err(&pdev->dev, "memory alloc failed\n");
3425                 return -ENOMEM;
3426         }
3427         tegra->pdev = pdev;
3428         tegra->pdata = dev_get_platdata(&pdev->dev);
3429         tegra->bdata = tegra->pdata->bdata;
3430
3431         ret = tegra_xhci_request_mem_region(pdev, "padctl",
3432                         &tegra->padctl_base);
3433         if (ret) {
3434                 dev_err(&pdev->dev, "failed to map padctl\n");
3435                 return ret;
3436         }
3437
3438         ret = tegra_xhci_request_mem_region(pdev, "fpci", &tegra->fpci_base);
3439         if (ret) {
3440                 dev_err(&pdev->dev, "failed to map fpci\n");
3441                 return ret;
3442         }
3443
3444         ret = tegra_xhci_request_mem_region(pdev, "ipfs", &tegra->ipfs_base);
3445         if (ret) {
3446                 dev_err(&pdev->dev, "failed to map ipfs\n");
3447                 return ret;
3448         }
3449
3450         ret = tegra_xusb_partitions_clk_init(tegra);
3451         if (ret) {
3452                 dev_err(&pdev->dev,
3453                         "failed to initialize xusb partitions clocks\n");
3454                 return ret;
3455         }
3456
3457         /* Enable power rails to the PAD,VBUS
3458          * and pull-up voltage.Initialize the regulators
3459          */
3460         ret = tegra_xusb_regulator_init(tegra, pdev);
3461         if (ret) {
3462                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
3463                 goto err_deinit_xusb_partition_clk;
3464         }
3465
3466         /* Enable UTMIP, PLLU and PLLE */
3467         ret = tegra_usb2_clocks_init(tegra);
3468         if (ret) {
3469                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
3470                 goto err_deinit_tegra_xusb_regulator;
3471         }
3472
3473         /* tegra_unpowergate_partition also does partition reset deassert */
3474         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
3475         if (ret)
3476                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
3477
3478         /* tegra_unpowergate_partition also does partition reset deassert */
3479         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3480         if (ret)
3481                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
3482
3483         /* reset the pointer back to NULL. driver uses it */
3484         /* platform_set_drvdata(pdev, NULL); */
3485
3486         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "host");
3487         if (!res) {
3488                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
3489                 ret = -ENODEV;
3490                 goto err_deinit_usb2_clocks;
3491         }
3492         tegra->host_phy_base = res->start;
3493
3494         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
3495                                 res->start, resource_size(res));
3496         if (!tegra->host_phy_virt_base) {
3497                 dev_err(&pdev->dev, "error mapping host phy memory\n");
3498                 ret = -ENOMEM;
3499                 goto err_deinit_usb2_clocks;
3500         }
3501
3502         /* Setup IPFS access and BAR0 space */
3503         tegra_xhci_cfg(tegra);
3504
3505         val = readl(tegra->fpci_base + XUSB_CFG_0);
3506         tegra->device_id = (val >> 16) & 0xffff;
3507
3508         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
3509                 (XUSB_DEVICE_ID_T114 == tegra->device_id) ? "T114" : "T124+");
3510
3511         if (XUSB_DEVICE_ID_T114 == tegra->device_id) {
3512                 tegra->padregs = &t114_padregs_offset;
3513         } else if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
3514                 tegra->padregs = &t124_padregs_offset;
3515         } else {
3516                 dev_info(&pdev->dev, "XUSB device_id neither T114 nor T124!\n");
3517                 dev_info(&pdev->dev, "XUSB using T124 pad register offsets!\n");
3518                 tegra->padregs = &t124_padregs_offset;
3519         }
3520
3521         /* calculate rctrl_val and tctrl_val once at boot time */
3522         tegra_xhci_war_for_tctrl_rctrl(tegra);
3523
3524         /* Program the XUSB pads to take ownership of ports */
3525         tegra_xhci_padctl_portmap_and_caps(tegra);
3526
3527         /* Release XUSB wake logic state latching */
3528         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
3529         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
3530
3531         /* Deassert reset to XUSB host, ss, dev clocks */
3532         tegra_periph_reset_deassert(tegra->host_clk);
3533         tegra_periph_reset_deassert(tegra->ss_clk);
3534
3535         fw_log_init(tegra);
3536         ret = init_firmware(tegra);
3537         if (ret < 0) {
3538                 dev_err(&pdev->dev, "failed to init firmware\n");
3539                 ret = -ENODEV;
3540                 goto err_deinit_usb2_clocks;
3541         }
3542
3543         ret = load_firmware(tegra, true /* do reset ARU */);
3544         if (ret < 0) {
3545                 dev_err(&pdev->dev, "failed to load firmware\n");
3546                 ret = -ENODEV;
3547                 goto err_deinit_firmware;
3548         }
3549
3550         device_init_wakeup(&pdev->dev, 1);
3551         driver = &tegra_plat_xhci_driver;
3552
3553         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
3554         if (!hcd) {
3555                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
3556                 ret = -ENOMEM;
3557                 goto err_deinit_firmware;
3558         }
3559
3560         ret = tegra_xhci_request_mem_region(pdev, "host", &hcd->regs);
3561         if (ret) {
3562                 dev_err(&pdev->dev, "failed to map host\n");
3563                 goto err_put_usb2_hcd;
3564         }
3565         hcd->rsrc_start = res->start;
3566         hcd->rsrc_len = resource_size(res);
3567
3568         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "host");
3569         if (!res) {
3570                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
3571                 ret = -ENODEV;
3572                 goto err_put_usb2_hcd;
3573         }
3574         irq = res->start;
3575         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
3576         if (ret) {
3577                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
3578                 goto err_put_usb2_hcd;
3579         }
3580
3581         /* USB 2.0 roothub is stored in the platform_device now. */
3582         hcd = dev_get_drvdata(&pdev->dev);
3583         xhci = hcd_to_xhci(hcd);
3584         tegra->xhci = xhci;
3585         platform_set_drvdata(pdev, tegra);
3586
3587         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
3588                                                 dev_name(&pdev->dev), hcd);
3589         if (!xhci->shared_hcd) {
3590                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
3591                 ret = -ENOMEM;
3592                 goto err_remove_usb2_hcd;
3593         }
3594
3595         /*
3596          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
3597          * is called by usb_add_hcd().
3598          */
3599         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
3600
3601         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
3602         if (ret) {
3603                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
3604                 goto err_put_usb3_hcd;
3605         }
3606
3607         device_init_wakeup(&hcd->self.root_hub->dev, 1);
3608         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
3609         spin_lock_init(&tegra->lock);
3610         mutex_init(&tegra->sync_lock);
3611         mutex_init(&tegra->mbox_lock);
3612
3613         /* do mailbox related initializations */
3614         tegra->mbox_owner = 0xffff;
3615         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
3616
3617         tegra_xhci_enable_fw_message(tegra);
3618
3619         /* do ss partition elpg exit related initialization */
3620         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
3621
3622         /* do host partition elpg exit related initialization */
3623         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
3624
3625         /* Register interrupt handler for SMI line to handle mailbox
3626          * interrupt from firmware
3627          */
3628         ret = tegra_xhci_request_irq(pdev, "host-smi", tegra_xhci_smi_irq,
3629                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
3630         if (ret != 0)
3631                 goto err_remove_usb3_hcd;
3632
3633         /* Register interrupt handler for PADCTRL line to
3634          * handle wake on connect irqs interrupt from
3635          * firmware
3636          */
3637         ret = tegra_xhci_request_irq(pdev, "padctl", tegra_xhci_padctl_irq,
3638                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
3639                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
3640         if (ret != 0)
3641                 goto err_remove_usb3_hcd;
3642
3643         ret = tegra_xhci_request_irq(pdev, "usb3", tegra_xhci_xusb_host_irq,
3644                         IRQF_SHARED | IRQF_TRIGGER_HIGH, "xusb_host_irq",
3645                         &tegra->usb3_irq);
3646         if (ret != 0)
3647                 goto err_remove_usb3_hcd;
3648
3649         tegra->ss_pwr_gated = false;
3650         tegra->host_pwr_gated = false;
3651         tegra->hc_in_elpg = false;
3652         tegra->hs_wake_event = false;
3653         tegra->host_resume_req = false;
3654         tegra->lp0_exit = false;
3655         tegra->dfe_ctle_ctx_saved = false;
3656
3657         /* reset wake event to NONE */
3658         pmc_reg = tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0);
3659         pmc_reg |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE);
3660         pmc_reg |= UTMIP_WAKE_VAL(1, WAKE_VAL_NONE);
3661         pmc_reg |= UTMIP_WAKE_VAL(2, WAKE_VAL_NONE);
3662         pmc_reg |= UTMIP_WAKE_VAL(3, WAKE_VAL_NONE);
3663         tegra_usb_pmc_reg_write(PMC_UTMIP_UHSIC_SLEEP_CFG_0, pmc_reg);
3664
3665         tegra_xhci_debug_read_pads(tegra);
3666         utmi_phy_pad_enable();
3667         utmi_phy_iddq_override(false);
3668
3669         tegra_pd_add_device(&pdev->dev);
3670
3671         return 0;
3672
3673 err_remove_usb3_hcd:
3674         usb_remove_hcd(xhci->shared_hcd);
3675 err_put_usb3_hcd:
3676         usb_put_hcd(xhci->shared_hcd);
3677 err_remove_usb2_hcd:
3678         kfree(tegra->xhci);
3679         usb_remove_hcd(hcd);
3680 err_put_usb2_hcd:
3681         usb_put_hcd(hcd);
3682 err_deinit_firmware:
3683         deinit_firmware(tegra);
3684 err_deinit_usb2_clocks:
3685         tegra_usb2_clocks_deinit(tegra);
3686 err_deinit_tegra_xusb_regulator:
3687         tegra_xusb_regulator_deinit(tegra);
3688 err_deinit_xusb_partition_clk:
3689         tegra_xusb_partitions_clk_deinit(tegra);
3690
3691         return ret;
3692 }
3693
3694 static int tegra_xhci_remove(struct platform_device *pdev)
3695 {
3696         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3697         struct xhci_hcd *xhci = NULL;
3698         struct usb_hcd *hcd = NULL;
3699
3700         if (tegra == NULL)
3701                 return -EINVAL;
3702
3703         xhci = tegra->xhci;
3704         hcd = xhci_to_hcd(xhci);
3705
3706         devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
3707         devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
3708         devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
3709         usb_remove_hcd(xhci->shared_hcd);
3710         usb_put_hcd(xhci->shared_hcd);
3711         usb_remove_hcd(hcd);
3712         usb_put_hcd(hcd);
3713         kfree(xhci);
3714
3715         deinit_firmware(tegra);
3716         fw_log_deinit(tegra);
3717         tegra_xusb_regulator_deinit(tegra);
3718         tegra_usb2_clocks_deinit(tegra);
3719         if (!tegra->hc_in_elpg)
3720                 tegra_xusb_partitions_clk_deinit(tegra);
3721         utmi_phy_pad_disable();
3722         utmi_phy_iddq_override(true);
3723
3724         return 0;
3725 }
3726
3727 static void tegra_xhci_shutdown(struct platform_device *pdev)
3728 {
3729         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3730         struct xhci_hcd *xhci = NULL;
3731         struct usb_hcd *hcd = NULL;
3732
3733         if (tegra == NULL)
3734                 return;
3735
3736         if (tegra->hc_in_elpg) {
3737                 mutex_lock(&tegra->sync_lock);
3738                 pmc_init(tegra, 0);
3739                 mutex_unlock(&tegra->sync_lock);
3740         } else {
3741                 xhci = tegra->xhci;
3742                 hcd = xhci_to_hcd(xhci);
3743                 xhci_shutdown(hcd);
3744         }
3745 }
3746
3747 static struct platform_driver tegra_xhci_driver = {
3748         .probe  = tegra_xhci_probe,
3749         .remove = tegra_xhci_remove,
3750         .shutdown = tegra_xhci_shutdown,
3751 #ifdef CONFIG_PM
3752         .suspend = tegra_xhci_suspend,
3753         .resume  = tegra_xhci_resume,
3754 #endif
3755         .driver = {
3756                 .name = "tegra-xhci",
3757         },
3758 };
3759 MODULE_ALIAS("platform:tegra-xhci");
3760
3761 int tegra_xhci_register_plat(void)
3762 {
3763         return platform_driver_register(&tegra_xhci_driver);
3764 }
3765
3766 void tegra_xhci_unregister_plat(void)
3767 {
3768         platform_driver_unregister(&tegra_xhci_driver);
3769 }