usb: xhci: tegra: setup gpios for ss lanes
[linux-3.10.git] / drivers / usb / host / xhci-tegra.c
1 /*
2  * xhci-tegra.c - Nvidia xHCI host controller driver
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/clk.h>
24 #include <linux/ioport.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irq.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/uaccess.h>
30 #include <linux/gpio.h>
31
32 #include <mach/powergate.h>
33 #include <mach/clk.h>
34 #include <mach/tegra_usb_pad_ctrl.h>
35 #include <mach/tegra_usb_pmc.h>
36 #include <mach/pm_domains.h>
37 #include <mach/mc.h>
38 #include <mach/xusb.h>
39
40 #include "../../../arch/arm/mach-tegra/iomap.h" /* HACK -- remove */
41 #include "xhci-tegra.h"
42 #include "xhci.h"
43
44 /* macros */
45 #define PAGE_SELECT_MASK                        0xFFFFFE00
46 #define PAGE_SELECT_SHIFT                       9
47 #define PAGE_OFFSET_MASK                        0x000001FF
48 #define CSB_PAGE_SELECT(_addr)                                          \
49         ({                                                              \
50                 typecheck(u32, _addr);                                  \
51                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
52         })
53 #define CSB_PAGE_OFFSET(_addr)                                          \
54         ({                                                              \
55                 typecheck(u32, _addr);                                  \
56                 (_addr & PAGE_OFFSET_MASK);                             \
57         })
58
59 /* PMC register definition */
60 #define PMC_PORT_UTMIP_P0               0
61 #define PMC_PORT_UTMIP_P1               1
62 #define PMC_PORT_UTMIP_P2               2
63 #define PMC_PORT_UHSIC_P0               3
64 #define PMC_PORT_NUM                    4
65
66 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
67 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
68 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
69
70 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
71
72 /* private data types */
73 /* command requests from the firmware */
74 enum MBOX_CMD_TYPE {
75         MBOX_CMD_MSG_ENABLED = 1,
76         MBOX_CMD_INC_FALC_CLOCK,
77         MBOX_CMD_DEC_FALC_CLOCK,
78         MBOX_CMD_INC_SSPI_CLOCK,
79         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
80         MBOX_CMD_SET_BW,
81         MBOX_CMD_SET_SS_PWR_GATING,
82         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
83         MBOX_CMD_SAVE_DFE_CTLE_CTX,
84
85         /* needs to be the last cmd */
86         MBOX_CMD_MAX,
87
88         /* resp msg to ack above commands */
89         MBOX_CMD_ACK = 128,
90         MBOX_CMD_NACK
91 };
92
93 /* Usb3 Firmware Cfg Table */
94 struct cfgtbl {
95         u32 boot_loadaddr_in_imem;
96         u32 boot_codedfi_offset;
97         u32 boot_codetag;
98         u32 boot_codesize;
99
100         /* Physical memory reserved by Bootloader/BIOS */
101         u32 phys_memaddr;
102         u16 reqphys_memsize;
103         u16 alloc_phys_memsize;
104
105         /* .rodata section */
106         u32 rodata_img_offset;
107         u32 rodata_section_start;
108         u32 rodata_section_end;
109         u32 main_fnaddr;
110
111         u32 fwimg_cksum;
112         u32 fwimg_created_time;
113
114         /* Fields that get filled by linker during linking phase
115          * or initialized in the FW code.
116          */
117         u32 imem_resident_start;
118         u32 imem_resident_end;
119         u32 idirect_start;
120         u32 idirect_end;
121         u32 l2_imem_start;
122         u32 l2_imem_end;
123         u32 version_id;
124         u8 init_ddirect;
125         u8 reserved[3];
126         u32 phys_addr_log_buffer;
127         u32 total_log_entries;
128         u32 dequeue_ptr;
129
130         /*      Below two dummy variables are used to replace
131          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
132          *      retain the size of struct _CFG_TBL used by other AP/Module.
133          */
134         u32 dummy_var1;
135         u32 dummy_var2;
136
137         /* fwimg_len */
138         u32 fwimg_len;
139         u8 magic[8];
140         u32 SS_low_power_entry_timeout;
141         u8 padding[140]; /* padding bytes to makeup 256-bytes cfgtbl */
142 };
143
144 struct xusb_save_regs {
145         u32 msi_bar_sz;
146         u32 msi_axi_barst;
147         u32 msi_fpci_barst;
148         u32 msi_vec0;
149         u32 msi_en_vec0;
150         u32 fpci_error_masks;
151         u32 intr_mask;
152         u32 ipfs_intr_enable;
153         u32 ufpci_config;
154         u32 clkgate_hysteresis;
155         u32 xusb_host_mccif_fifo_cntrl;
156
157         /* PG does not mention below */
158         u32 hs_pls;
159         u32 fs_pls;
160         u32 hs_fs_speed;
161         u32 hs_fs_pp;
162         u32 cfg_aru;
163         u32 cfg_order;
164         u32 cfg_fladj;
165         u32 cfg_sid;
166         /* DFE and CTLE */
167         u32 tap1_val[2];
168         u32 amp_val[2];
169         u32 ctle_z_val[2];
170         u32 ctle_g_val[2];
171 };
172
173 struct tegra_xhci_firmware {
174         void *data; /* kernel virtual address */
175         size_t size; /* firmware size */
176         dma_addr_t dma; /* dma address for controller */
177 };
178
179 /* structure to hold the offsets of padctl registers */
180 struct tegra_xusb_padctl_regs {
181         u16 boot_media_0;
182         u16 usb2_pad_mux_0;
183         u16 usb2_port_cap_0;
184         u16 snps_oc_map_0;
185         u16 usb2_oc_map_0;
186         u16 ss_port_map_0;
187         u16 oc_det_0;
188         u16 elpg_program_0;
189         u16 usb2_bchrg_otgpad0_ctl0_0;
190         u16 usb2_bchrg_otgpad0_ctl1_0;
191         u16 usb2_bchrg_otgpad1_ctl0_0;
192         u16 usb2_bchrg_otgpad1_ctl1_0;
193         u16 usb2_bchrg_otgpad2_ctl0_0;
194         u16 usb2_bchrg_otgpad2_ctl1_0;
195         u16 usb2_bchrg_bias_pad_0;
196         u16 usb2_bchrg_tdcd_dbnc_timer_0;
197         u16 iophy_pll_p0_ctl1_0;
198         u16 iophy_pll_p0_ctl2_0;
199         u16 iophy_pll_p0_ctl3_0;
200         u16 iophy_pll_p0_ctl4_0;
201         u16 iophy_usb3_pad0_ctl1_0;
202         u16 iophy_usb3_pad1_ctl1_0;
203         u16 iophy_usb3_pad0_ctl2_0;
204         u16 iophy_usb3_pad1_ctl2_0;
205         u16 iophy_usb3_pad0_ctl3_0;
206         u16 iophy_usb3_pad1_ctl3_0;
207         u16 iophy_usb3_pad0_ctl4_0;
208         u16 iophy_usb3_pad1_ctl4_0;
209         u16 iophy_misc_pad_p0_ctl1_0;
210         u16 iophy_misc_pad_p1_ctl1_0;
211         u16 iophy_misc_pad_p0_ctl2_0;
212         u16 iophy_misc_pad_p1_ctl2_0;
213         u16 iophy_misc_pad_p0_ctl3_0;
214         u16 iophy_misc_pad_p1_ctl3_0;
215         u16 iophy_misc_pad_p0_ctl4_0;
216         u16 iophy_misc_pad_p1_ctl4_0;
217         u16 iophy_misc_pad_p0_ctl5_0;
218         u16 iophy_misc_pad_p1_ctl5_0;
219         u16 iophy_misc_pad_p0_ctl6_0;
220         u16 iophy_misc_pad_p1_ctl6_0;
221         u16 usb2_otg_pad0_ctl0_0;
222         u16 usb2_otg_pad1_ctl0_0;
223         u16 usb2_otg_pad2_ctl0_0;
224         u16 usb2_otg_pad0_ctl1_0;
225         u16 usb2_otg_pad1_ctl1_0;
226         u16 usb2_otg_pad2_ctl1_0;
227         u16 usb2_bias_pad_ctl0_0;
228         u16 usb2_bias_pad_ctl1_0;
229         u16 usb2_hsic_pad0_ctl0_0;
230         u16 usb2_hsic_pad1_ctl0_0;
231         u16 usb2_hsic_pad0_ctl1_0;
232         u16 usb2_hsic_pad1_ctl1_0;
233         u16 usb2_hsic_pad0_ctl2_0;
234         u16 usb2_hsic_pad1_ctl2_0;
235         u16 ulpi_link_trim_ctl0;
236         u16 ulpi_null_clk_trim_ctl0;
237         u16 hsic_strb_trim_ctl0;
238         u16 wake_ctl0;
239         u16 pm_spare0;
240         u16 iophy_misc_pad_p2_ctl1_0;
241         u16 iophy_misc_pad_p3_ctl1_0;
242         u16 iophy_misc_pad_p4_ctl1_0;
243         u16 iophy_misc_pad_p2_ctl2_0;
244         u16 iophy_misc_pad_p3_ctl2_0;
245         u16 iophy_misc_pad_p4_ctl2_0;
246         u16 iophy_misc_pad_p2_ctl3_0;
247         u16 iophy_misc_pad_p3_ctl3_0;
248         u16 iophy_misc_pad_p4_ctl3_0;
249         u16 iophy_misc_pad_p2_ctl4_0;
250         u16 iophy_misc_pad_p3_ctl4_0;
251         u16 iophy_misc_pad_p4_ctl4_0;
252         u16 iophy_misc_pad_p2_ctl5_0;
253         u16 iophy_misc_pad_p3_ctl5_0;
254         u16 iophy_misc_pad_p4_ctl5_0;
255         u16 iophy_misc_pad_p2_ctl6_0;
256         u16 iophy_misc_pad_p3_ctl6_0;
257         u16 iophy_misc_pad_p4_ctl6_0;
258         u16 usb3_pad_mux_0;
259         u16 iophy_pll_s0_ctl1_0;
260         u16 iophy_pll_s0_ctl2_0;
261         u16 iophy_pll_s0_ctl3_0;
262         u16 iophy_pll_s0_ctl4_0;
263         u16 iophy_misc_pad_s0_ctl1_0;
264         u16 iophy_misc_pad_s0_ctl2_0;
265         u16 iophy_misc_pad_s0_ctl3_0;
266         u16 iophy_misc_pad_s0_ctl4_0;
267         u16 iophy_misc_pad_s0_ctl5_0;
268         u16 iophy_misc_pad_s0_ctl6_0;
269 };
270
271 struct tegra_xhci_hcd {
272         struct platform_device *pdev;
273         struct xhci_hcd *xhci;
274         u16 device_id;
275
276         spinlock_t lock;
277         struct mutex sync_lock;
278
279         int smi_irq;
280         int padctl_irq;
281         int usb3_irq;
282
283         bool ss_wake_event;
284         bool ss_pwr_gated;
285         bool host_pwr_gated;
286         bool hs_wake_event;
287         bool host_resume_req;
288         bool lp0_exit;
289         bool dfe_ctle_ctx_saved;
290         unsigned long last_jiffies;
291         unsigned long host_phy_base;
292         void __iomem *host_phy_virt_base;
293
294         void __iomem *padctl_base;
295         void __iomem *fpci_base;
296         void __iomem *ipfs_base;
297
298         struct tegra_xusb_platform_data *pdata;
299         struct tegra_xusb_board_data *bdata;
300         struct tegra_xusb_padctl_regs *padregs;
301
302         /* mailbox variables */
303         struct mutex mbox_lock;
304         u32 mbox_owner;
305         u32 cmd_type;
306         u32 cmd_data;
307
308         struct regulator *xusb_vbus_reg;
309         struct regulator *xusb_avddio_usb3_reg;
310         struct regulator *xusb_hvdd_usb3_reg;
311         struct regulator *xusb_avdd_usb3_pll_reg;
312
313         struct work_struct mbox_work;
314         struct work_struct ss_elpg_exit_work;
315         struct work_struct host_elpg_exit_work;
316
317         struct clk *host_clk;
318         struct clk *ss_clk;
319
320         /* XUSB Falcon SuperSpeed Clock */
321         struct clk *falc_clk;
322
323         /* EMC Clock */
324         struct clk *emc_clk;
325         /* XUSB SS PI Clock */
326         struct clk *ss_src_clk;
327         /* PLLE Clock */
328         struct clk *plle_clk;
329         struct clk *pll_u_480M;
330         struct clk *clk_m;
331         /* refPLLE clk */
332         struct clk *pll_re_vco_clk;
333         /*
334          * XUSB/IPFS specific registers these need to be saved/restored in
335          * addition to spec defined registers
336          */
337         struct xusb_save_regs sregs;
338         bool usb2_rh_suspend;
339         bool usb3_rh_suspend;
340         bool hc_in_elpg;
341
342         unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
343         /* firmware loading related */
344         struct tegra_xhci_firmware firmware;
345 };
346
347 static struct tegra_usb_pmc_data pmc_data;
348
349 /* functions */
350 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
351 {
352         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
353 }
354
355 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
356 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
357 {
358         WARN_ON(tegra->sync_lock.owner != current);
359 }
360 #else
361 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
362 #endif
363
364 static void tegra_xhci_setup_gpio_for_ss_lane(struct tegra_xhci_hcd *tegra)
365 {
366         int err = 0;
367
368         if (!tegra->bdata->gpio_controls_muxed_ss_lanes)
369                 return;
370
371         if (tegra->bdata->lane_owner & BIT(0)) {
372                 /* USB3_SS port1 is using SATA lane so set (MUX_SATA)
373                  * GPIO P11 to '0'
374                  */
375                 err = gpio_request((tegra->bdata->gpio_ss1_sata & 0xffff),
376                         "gpio_ss1_sata");
377                 if (err < 0)
378                         pr_err("%s: gpio_ss1_sata gpio_request failed %d\n",
379                                 __func__, err);
380                 err = gpio_direction_output((tegra->bdata->gpio_ss1_sata
381                         & 0xffff), 1);
382                 if (err < 0)
383                         pr_err("%s: gpio_ss1_sata gpio_direction failed %d\n",
384                                 __func__, err);
385                 __gpio_set_value((tegra->bdata->gpio_ss1_sata & 0xffff),
386                                 ((tegra->bdata->gpio_ss1_sata >> 16)));
387         }
388 }
389
390 static bool is_any_hs_connected(struct xhci_hcd *xhci)
391 {
392         __le32 __iomem *addr;
393         int i;
394         int ports;
395         u32 portsc;
396
397         ports = HCS_MAX_PORTS(xhci->hcs_params1);
398         addr = &xhci->op_regs->port_status_base;
399         for (i = 0; i < ports; i++) {
400                 portsc = xhci_readl(xhci, addr);
401                 if ((portsc & PORT_CONNECT) && DEV_HIGHSPEED(portsc))
402                         return true;
403                 addr += NUM_PORT_REGS;
404         }
405         return false;
406 }
407
408 static void debug_print_portsc(struct xhci_hcd *xhci)
409 {
410         __le32 __iomem *addr;
411         int i;
412         int ports;
413
414         ports = HCS_MAX_PORTS(xhci->hcs_params1);
415         addr = &xhci->op_regs->port_status_base;
416         for (i = 0; i < ports; i++) {
417                 xhci_dbg(xhci, "%p port %d status reg = 0x%x\n",
418                                 addr, i, (unsigned int) xhci_readl(xhci, addr));
419                 addr += NUM_PORT_REGS;
420         }
421 }
422
423 static void update_speed(struct tegra_xhci_hcd *tegra, u8 port)
424 {
425         struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
426         u32 portsc;
427
428         portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port +
429                                                 BAR0_XHCI_OP_PORTSC_UTMIP_0));
430         if (DEV_FULLSPEED(portsc))
431                 pmc_data.port_speed = USB_PMC_PORT_SPEED_FULL;
432         else if (DEV_HIGHSPEED(portsc))
433                 pmc_data.port_speed = USB_PMC_PORT_SPEED_HIGH;
434         else if (DEV_LOWSPEED(portsc))
435                 pmc_data.port_speed = USB_PMC_PORT_SPEED_LOW;
436         else if (DEV_SUPERSPEED(portsc))
437                 pmc_data.port_speed = USB_PMC_PORT_SPEED_SUPER;
438         else
439                 pmc_data.port_speed = USB_PMC_PORT_SPEED_UNKNOWN;
440 }
441
442 static void setup_wake_detect(bool setup_wake)
443 {
444         if (setup_wake)
445                 pmc_data.pmc_ops->setup_pmc_wake_detect(&pmc_data);
446         else
447                 pmc_data.pmc_ops->disable_pmc_bus_ctrl(&pmc_data, 0);
448 }
449
450 static void pmc_init(struct tegra_xhci_hcd *tegra, bool setup_wake)
451 {
452         u32 portmap = tegra->bdata->portmap;
453
454         pmc_data.controller_type = TEGRA_USB_3_0;
455         if (portmap & TEGRA_XUSB_USB2_P0) {
456                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 0) & 0xf;
457                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
458                 update_speed(tegra, pmc_data.instance);
459                 tegra_usb_pmc_init(&pmc_data);
460                 setup_wake_detect(setup_wake);
461         }
462         if (portmap & TEGRA_XUSB_USB2_P1) {
463                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 4) & 0xf;
464                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
465                 update_speed(tegra, pmc_data.instance);
466                 tegra_usb_pmc_init(&pmc_data);
467                 setup_wake_detect(setup_wake);
468         }
469         if (portmap & TEGRA_XUSB_USB2_P2) {
470                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 8) & 0xf;
471                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
472                 update_speed(tegra, pmc_data.instance);
473                 tegra_usb_pmc_init(&pmc_data);
474                 setup_wake_detect(setup_wake);
475         }
476         if (portmap & TEGRA_XUSB_HSIC_P0) {
477                 pmc_data.instance = PMC_PORT_UHSIC_P0;
478                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_HSIC;
479                 update_speed(tegra, pmc_data.instance);
480                 tegra_usb_pmc_init(&pmc_data);
481                 setup_wake_detect(setup_wake);
482         }
483 }
484
485 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
486 {
487         void __iomem *fpci_base = tegra->fpci_base;
488         struct platform_device *pdev = tegra->pdev;
489         u32 input_addr;
490         u32 data;
491         u32 csb_page_select;
492
493         /* to select the appropriate CSB page to write to */
494         csb_page_select = CSB_PAGE_SELECT(addr);
495
496         dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
497                         csb_page_select);
498
499         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
500
501         /* selects the appropriate offset in the page to read from */
502         input_addr = CSB_PAGE_OFFSET(addr);
503         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
504
505         dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
506                         input_addr, data);
507         return data;
508 }
509
510 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
511 {
512         void __iomem *fpci_base = tegra->fpci_base;
513         struct platform_device *pdev = tegra->pdev;
514         u32 input_addr;
515         u32 csb_page_select;
516
517         /* to select the appropriate CSB page to write to */
518         csb_page_select = CSB_PAGE_SELECT(addr);
519
520         dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
521                         csb_page_select);
522
523         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
524
525         /* selects the appropriate offset in the page to write to */
526         input_addr = CSB_PAGE_OFFSET(addr);
527         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
528
529         dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
530                         input_addr, data);
531 }
532
533 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
534 {
535         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
536         struct xhci_hcd *xhci = tegra->xhci;
537         u32 reg;
538
539         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
540         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
541         xhci_info(xhci, " PAD MUX = %x\n", reg);
542         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
543         xhci_info(xhci, " PORT CAP = %x\n", reg);
544         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
545         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
546         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
547         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
548         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
549         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
550         reg = readl(tegra->padctl_base + padregs->oc_det_0);
551         xhci_info(xhci, " OC DET 0= %x\n", reg);
552         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad0_ctl2_0);
553         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
554         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad1_ctl2_0);
555         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
556         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl0_0);
557         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
558         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl0_0);
559         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
560         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl1_0);
561         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
562         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl1_0);
563         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
564         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
565         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
566         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad0_ctl0_0);
567         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
568         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad1_ctl0_0);
569         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
570         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
571 }
572
573 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
574 {
575         u32 reg;
576
577         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
578         reg |= IPFS_EN_FPCI;
579         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
580         udelay(10);
581
582         /* Program Bar0 Space */
583         reg = readl(tegra->fpci_base + XUSB_CFG_4);
584         reg |= tegra->host_phy_base;
585         writel(reg, tegra->fpci_base + XUSB_CFG_4);
586         usleep_range(100, 200);
587
588         /* Enable Bus Master */
589         reg = readl(tegra->fpci_base + XUSB_CFG_1);
590         reg |= 0x7;
591         writel(reg, tegra->fpci_base + XUSB_CFG_1);
592
593         /* Set intr mask to enable intr assertion */
594         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
595         reg |= IPFS_IP_INT_MASK;
596         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
597
598         /* Set hysteris to 0x80 */
599         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
600 }
601
602 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
603                 struct platform_device *pdev)
604 {
605         int err = 0;
606
607         tegra->xusb_hvdd_usb3_reg =
608                         devm_regulator_get(&pdev->dev, "hvdd_usb");
609         if (IS_ERR(tegra->xusb_hvdd_usb3_reg)) {
610                 dev_err(&pdev->dev, "hvdd_usb: regulator not found: %ld."
611                         , PTR_ERR(tegra->xusb_hvdd_usb3_reg));
612                 err = PTR_ERR(tegra->xusb_hvdd_usb3_reg);
613                 goto err_null_regulator;
614         } else {
615                 err = regulator_enable(tegra->xusb_hvdd_usb3_reg);
616                 if (err < 0) {
617                         dev_err(&pdev->dev,
618                                 "hvdd_usb3: regulator enable failed:%d\n", err);
619                         goto err_null_regulator;
620                 }
621         }
622
623         tegra->xusb_vbus_reg = devm_regulator_get(&pdev->dev, "usb_vbus");
624         if (IS_ERR(tegra->xusb_vbus_reg)) {
625                 dev_err(&pdev->dev, "vbus regulator not found: %ld."
626                         , PTR_ERR(tegra->xusb_vbus_reg));
627                 err = PTR_ERR(tegra->xusb_vbus_reg);
628                 goto err_put_hvdd_usb3;
629         } else {
630                 err = regulator_enable(tegra->xusb_vbus_reg);
631                 if (err < 0) {
632                         dev_err(&pdev->dev,
633                                 "vbus: regulator enable failed:%d\n", err);
634                         goto err_put_hvdd_usb3;
635                 }
636         }
637
638         tegra->xusb_avdd_usb3_pll_reg =
639                 devm_regulator_get(&pdev->dev, "avdd_usb_pll");
640         if (IS_ERR(tegra->xusb_avdd_usb3_pll_reg)) {
641                 dev_err(&pdev->dev, "avdd_usb3_pll regulator not found: %ld."
642                         , PTR_ERR(tegra->xusb_avdd_usb3_pll_reg));
643                 err = PTR_ERR(tegra->xusb_avdd_usb3_pll_reg);
644                 goto err_put_vbus;
645         } else {
646                 err = regulator_enable(tegra->xusb_avdd_usb3_pll_reg);
647                 if (err < 0) {
648                         dev_err(&pdev->dev,
649                         "avdd_usb3_pll: regulator enable failed:%d\n", err);
650                         goto err_put_vbus;
651                 }
652         }
653
654         tegra->xusb_avddio_usb3_reg =
655                         devm_regulator_get(&pdev->dev, "avddio_usb");
656         if (IS_ERR(tegra->xusb_avddio_usb3_reg)) {
657                 dev_err(&pdev->dev, "avddio_usb3: regulator not found: %ld."
658                         , PTR_ERR(tegra->xusb_avddio_usb3_reg));
659                 err = PTR_ERR(tegra->xusb_avddio_usb3_reg);
660                 goto err_put_usb3_pll;
661         } else {
662                 err = regulator_enable(tegra->xusb_avddio_usb3_reg);
663                 if (err < 0) {
664                         dev_err(&pdev->dev,
665                         "avddio_usb3: regulator enable failed:%d\n", err);
666                         goto err_put_usb3_pll;
667                 }
668         }
669
670         return err;
671
672 err_put_usb3_pll:
673         regulator_disable(tegra->xusb_avdd_usb3_pll_reg);
674 err_put_vbus:
675         regulator_disable(tegra->xusb_vbus_reg);
676 err_put_hvdd_usb3:
677         regulator_disable(tegra->xusb_hvdd_usb3_reg);
678 err_null_regulator:
679         tegra->xusb_vbus_reg = NULL;
680         tegra->xusb_avddio_usb3_reg = NULL;
681         tegra->xusb_hvdd_usb3_reg = NULL;
682         tegra->xusb_avdd_usb3_pll_reg = NULL;
683         return err;
684 }
685
686 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
687 {
688         regulator_disable(tegra->xusb_avddio_usb3_reg);
689         regulator_disable(tegra->xusb_avdd_usb3_pll_reg);
690         regulator_disable(tegra->xusb_vbus_reg);
691         regulator_disable(tegra->xusb_hvdd_usb3_reg);
692
693         tegra->xusb_avddio_usb3_reg = NULL;
694         tegra->xusb_avdd_usb3_pll_reg = NULL;
695         tegra->xusb_vbus_reg = NULL;
696         tegra->xusb_hvdd_usb3_reg = NULL;
697 }
698
699 /*
700  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
701  * are under hardware control
702  */
703 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
704 {
705         struct platform_device *pdev = tegra->pdev;
706         int err = 0;
707
708         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
709         if (IS_ERR(tegra->plle_clk)) {
710                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
711                 err = PTR_ERR(tegra->plle_clk);
712                 return err;
713         }
714         err = clk_enable(tegra->plle_clk);
715         if (err) {
716                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
717                         __func__);
718                 return err;
719         }
720
721         return err;
722 }
723
724 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
725 {
726         clk_disable(tegra->plle_clk);
727         tegra->plle_clk = NULL;
728 }
729
730 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
731 {
732         struct platform_device *pdev = tegra->pdev;
733         int err = 0;
734
735         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
736         if (IS_ERR(tegra->emc_clk)) {
737                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
738                 return PTR_ERR(tegra->emc_clk);
739         }
740
741         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
742                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
743                 if (IS_ERR(tegra->pll_re_vco_clk)) {
744                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
745                         err = PTR_ERR(tegra->pll_re_vco_clk);
746                         goto get_pll_re_vco_clk_failed;
747                 }
748         }
749
750         /* get the clock handle of 120MHz clock source */
751         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
752         if (IS_ERR(tegra->pll_u_480M)) {
753                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
754                 err = PTR_ERR(tegra->pll_u_480M);
755                 goto get_pll_u_480M_failed;
756         }
757
758         /* get the clock handle of 12MHz clock source */
759         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
760         if (IS_ERR(tegra->clk_m)) {
761                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
762                 err = PTR_ERR(tegra->clk_m);
763                 goto clk_get_clk_m_failed;
764         }
765
766         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
767         if (IS_ERR(tegra->ss_src_clk)) {
768                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
769                 err = PTR_ERR(tegra->ss_src_clk);
770                 tegra->ss_src_clk = NULL;
771                 goto get_ss_src_clk_failed;
772         }
773
774         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
775         if (IS_ERR(tegra->host_clk)) {
776                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
777                 err = PTR_ERR(tegra->host_clk);
778                 tegra->host_clk = NULL;
779                 goto get_host_clk_failed;
780         }
781
782         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
783         if (IS_ERR(tegra->ss_clk)) {
784                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
785                 err = PTR_ERR(tegra->ss_clk);
786                 tegra->ss_clk = NULL;
787                 goto get_ss_clk_failed;
788         }
789
790         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
791                 err = clk_enable(tegra->pll_re_vco_clk);
792                 if (err) {
793                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
794                         goto enable_pll_re_vco_clk_failed;
795                 }
796         }
797         /* enable ss clock */
798         err = clk_enable(tegra->host_clk);
799         if (err) {
800                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
801                 goto enable_host_clk_failed;
802         }
803
804         err = clk_enable(tegra->ss_clk);
805         if (err) {
806                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
807                 goto eanble_ss_clk_failed;
808         }
809
810         err = clk_enable(tegra->emc_clk);
811         if (err) {
812                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
813                 goto eanble_emc_clk_failed;
814         }
815
816         return 0;
817
818 eanble_emc_clk_failed:
819         clk_disable(tegra->ss_clk);
820
821 eanble_ss_clk_failed:
822         clk_disable(tegra->host_clk);
823
824 enable_host_clk_failed:
825         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
826                 clk_disable(tegra->pll_re_vco_clk);
827
828 enable_pll_re_vco_clk_failed:
829         tegra->ss_clk = NULL;
830
831 get_ss_clk_failed:
832         tegra->host_clk = NULL;
833
834 get_host_clk_failed:
835         tegra->ss_src_clk = NULL;
836
837 get_ss_src_clk_failed:
838         tegra->clk_m = NULL;
839
840 clk_get_clk_m_failed:
841         tegra->pll_u_480M = NULL;
842
843 get_pll_u_480M_failed:
844         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
845                 tegra->pll_re_vco_clk = NULL;
846
847 get_pll_re_vco_clk_failed:
848         tegra->emc_clk = NULL;
849
850         return err;
851 }
852
853 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
854 {
855         clk_disable(tegra->ss_clk);
856         clk_disable(tegra->host_clk);
857         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
858                 clk_disable(tegra->pll_re_vco_clk);
859         tegra->ss_clk = NULL;
860         tegra->host_clk = NULL;
861         tegra->ss_src_clk = NULL;
862         tegra->clk_m = NULL;
863         tegra->pll_u_480M = NULL;
864         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
865                 tegra->pll_re_vco_clk = NULL;
866 }
867
868 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
869         bool enable)
870 {
871         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
872         u32 reg;
873
874         /* Issue is only applicable for T114 */
875         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
876                 return;
877
878         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
879                 reg = readl(tegra->padctl_base +
880                         padregs->iophy_misc_pad_p0_ctl3_0);
881                 if (enable) {
882                         reg &= ~RX_IDLE_MODE;
883                         reg |= RX_IDLE_MODE_OVRD;
884                 } else {
885                         reg |= RX_IDLE_MODE;
886                         reg &= ~RX_IDLE_MODE_OVRD;
887                 }
888                 writel(reg, tegra->padctl_base +
889                         padregs->iophy_misc_pad_p0_ctl3_0);
890         }
891
892         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
893                 reg = readl(tegra->padctl_base +
894                         padregs->iophy_misc_pad_p1_ctl3_0);
895                 if (enable) {
896                         reg &= ~RX_IDLE_MODE;
897                         reg |= RX_IDLE_MODE_OVRD;
898                 } else {
899                         reg |= RX_IDLE_MODE;
900                         reg &= ~RX_IDLE_MODE_OVRD;
901                 }
902                 writel(reg, tegra->padctl_base +
903                         padregs->iophy_misc_pad_p1_ctl3_0);
904
905                 /* SATA lane also if USB3_SS port1 mapped to it */
906                 if (XUSB_DEVICE_ID_T124 == tegra->device_id &&
907                                 tegra->bdata->lane_owner & BIT(0)) {
908                         reg = readl(tegra->padctl_base +
909                                 padregs->iophy_misc_pad_s0_ctl3_0);
910                         if (enable) {
911                                 reg &= ~RX_IDLE_MODE;
912                                 reg |= RX_IDLE_MODE_OVRD;
913                         } else {
914                                 reg |= RX_IDLE_MODE;
915                                 reg &= ~RX_IDLE_MODE_OVRD;
916                         }
917                         writel(reg, tegra->padctl_base +
918                                 padregs->iophy_misc_pad_s0_ctl3_0);
919                 }
920         }
921 }
922
923 /* Enable ss clk, host clk, falcon clk,
924  * fs clk, dev clk, plle and refplle
925  */
926
927 static int
928 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
929                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
930 {
931         int ret = 0;
932         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
933         int fw_req_rate = rate, cur_rate;
934
935         /* Do not handle clock change as needed for HS disconnect issue */
936         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
937                 *sw_resp = fw_req_rate | (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
938                 return ret;
939         }
940
941         /* frequency request from firmware is in KHz.
942          * Convert it to MHz
943          */
944
945         /* get current rate of clock */
946         cur_rate = clk_get_rate(clk_handle);
947         cur_rate /= 1000;
948
949         if (fw_req_rate == cur_rate) {
950                 cmd_ack = MBOX_CMD_ACK;
951                 *sw_resp = fw_req_rate;
952         } else {
953
954                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
955                         /* Change SS clock source to CLK_M at 12MHz */
956                         clk_set_parent(clk_handle, tegra->clk_m);
957                         clk_set_rate(clk_handle, fw_req_rate * 1000);
958
959                         /* save leakage power when SS freq is being decreased */
960                         tegra_xhci_rx_idle_mode_override(tegra, true);
961                 } else if (clk_handle == tegra->ss_src_clk &&
962                                 fw_req_rate == 120000) {
963                         /* Change SS clock source to HSIC_480 at 120MHz */
964                         clk_set_rate(clk_handle,  3000 * 1000);
965                         clk_set_parent(clk_handle, tegra->pll_u_480M);
966
967                         /* clear ovrd bits when SS freq is being increased */
968                         tegra_xhci_rx_idle_mode_override(tegra, false);
969                 }
970
971                 *sw_resp = clk_get_rate(clk_handle);
972                 *sw_resp /= 1000;
973
974                 if (*sw_resp != fw_req_rate) {
975                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
976                                 cur_rate, fw_req_rate);
977                         cmd_ack = MBOX_CMD_NACK;
978                 }
979         }
980         *sw_resp |= (cmd_ack << MBOX_CMD_SHIFT);
981         return ret;
982 }
983
984 static void tegra_xhci_save_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
985         u8 port)
986 {
987         struct xhci_hcd *xhci = tegra->xhci;
988         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
989         u32 offset;
990         u32 reg;
991
992         xhci_info(xhci, "saving dfe_cntl and ctle context for port %d\n", port);
993
994         if (port == 3 /* SATA pad */)
995                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
996         else
997                 offset = port ? padregs->iophy_misc_pad_p1_ctl6_0 :
998                                 padregs->iophy_misc_pad_p0_ctl6_0;
999
1000         /* save tap1_val[] for the port for dfe_cntl */
1001         reg = readl(tegra->padctl_base + offset);
1002         reg &= ~(0xff << 16);
1003         reg |= (0x32 << 16);
1004         writel(reg, tegra->padctl_base + offset);
1005
1006         reg = readl(tegra->padctl_base + offset);
1007         tegra->sregs.tap1_val[port] = ((reg & (0x1f << 24)) >> 24);
1008
1009         /* save amp_val[] for the port for dfe_cntl */
1010         reg = readl(tegra->padctl_base + offset);
1011         reg &= ~(0xff << 16);
1012         reg |= (0x33 << 16);
1013         writel(reg, tegra->padctl_base + offset);
1014
1015         reg = readl(tegra->padctl_base + offset);
1016         tegra->sregs.amp_val[port] = ((reg & (0x7f << 24)) >> 24);
1017
1018         /* save ctle_z_val[] for the port for ctle */
1019         reg = readl(tegra->padctl_base + offset);
1020         reg &= ~(0xff << 16);
1021         reg |= (0x20 << 16);
1022         writel(reg, tegra->padctl_base + offset);
1023
1024         reg = readl(tegra->padctl_base + offset);
1025         tegra->sregs.ctle_z_val[port] = ((reg & (0x3f << 24)) >> 24);
1026
1027         /* save ctle_g_val[] for the port for ctle */
1028         reg = readl(tegra->padctl_base + offset);
1029         reg &= ~(0xff << 16);
1030         reg |= (0x21 << 16);
1031         writel(reg, tegra->padctl_base + offset);
1032
1033         reg = readl(tegra->padctl_base + offset);
1034         tegra->sregs.ctle_g_val[port] = ((reg & (0x3f << 24)) >> 24);
1035         tegra->dfe_ctle_ctx_saved = true;
1036 }
1037
1038 static void tegra_xhci_restore_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
1039         u8 port)
1040 {
1041         struct xhci_hcd *xhci = tegra->xhci;
1042         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1043         u32 ctl4_offset, ctl2_offset;
1044         u32 reg;
1045
1046         /* don't restore if not saved */
1047         if (tegra->dfe_ctle_ctx_saved == false)
1048                 return;
1049
1050         if (port == 3 /* SATA pad */) {
1051                 ctl4_offset = padregs->iophy_misc_pad_s0_ctl4_0;
1052                 ctl2_offset = padregs->iophy_misc_pad_s0_ctl2_0;
1053         } else {
1054                 ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1055                                 padregs->iophy_usb3_pad0_ctl4_0;
1056                 ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1057                                 padregs->iophy_usb3_pad0_ctl2_0;
1058         }
1059
1060         xhci_info(xhci, "restoring dfe_cntl/ctle context of port %d\n", port);
1061
1062         /* restore dfe_cntl for the port */
1063         reg = readl(tegra->padctl_base + ctl4_offset);
1064         reg &= ~((0x7f << 16) | (0x1f << 24));
1065         reg |= ((tegra->sregs.amp_val[port] << 16) |
1066                 (tegra->sregs.tap1_val[port] << 24));
1067         writel(reg, tegra->padctl_base + ctl4_offset);
1068
1069         /* restore ctle for the port */
1070         reg = readl(tegra->padctl_base + ctl2_offset);
1071         reg &= ~((0x3f << 8) | (0x3f << 16));
1072         reg |= ((tegra->sregs.ctle_g_val[port] << 8) |
1073                 (tegra->sregs.ctle_z_val[port] << 16));
1074         writel(reg, tegra->padctl_base + ctl2_offset);
1075 }
1076
1077 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
1078         u8 port)
1079 {
1080         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1081         u32 reg;
1082
1083         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1084         reg &= ~USB2_ULPI_PAD;
1085         reg |= USB2_ULPI_PAD_OWNER_XUSB;
1086         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1087
1088         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1089         reg &= ~USB2_ULPI_PORT_CAP;
1090         reg |= (tegra->bdata->ulpicap << 24);
1091         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1092         /* FIXME: Program below when more details available
1093          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
1094          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
1095          */
1096 }
1097
1098 static void tegra_xhci_program_hsic_pad(struct tegra_xhci_hcd *tegra,
1099         u8 port)
1100 {
1101         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1102         u32 ctl0_offset;
1103         u32 reg;
1104
1105         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1106         reg &= ~(port ? USB2_HSIC_PAD_PORT1 : USB2_HSIC_PAD_PORT0);
1107         reg |= port ? USB2_HSIC_PAD_P1_OWNER_XUSB :
1108                         USB2_HSIC_PAD_P0_OWNER_XUSB;
1109         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1110
1111         ctl0_offset = port ? padregs->usb2_hsic_pad1_ctl0_0 :
1112                         padregs->usb2_hsic_pad0_ctl0_0;
1113
1114         reg = readl(tegra->padctl_base + ctl0_offset);
1115         reg &= ~(HSIC_TX_SLEWP | HSIC_TX_SLEWN);
1116         writel(reg, tegra->padctl_base + ctl0_offset);
1117
1118         /* FIXME Program below when more details available
1119          * XUSB_PADCTL_HSIC_PAD0_CTL_0_0
1120          * XUSB_PADCTL_HSIC_PAD0_CTL_1_0
1121          * XUSB_PADCTL_HSIC_PAD0_CTL_2_0
1122          * XUSB_PADCTL_HSIC_PAD1_CTL_0_0
1123          * XUSB_PADCTL_HSIC_PAD1_CTL_1_0
1124          * XUSB_PADCTL_HSIC_PAD1_CTL_2_0
1125          * XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0
1126          */
1127 }
1128
1129 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
1130         u8 port)
1131 {
1132         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1133         u32 reg;
1134         u32 ctl0_offset, ctl1_offset;
1135
1136         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1137         reg &= ~USB2_OTG_PAD_PORT_MASK(port);
1138         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
1139         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1140
1141         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1142         reg &= ~USB2_PORT_CAP_MASK(port);
1143         reg |= USB2_PORT_CAP_HOST(port);
1144         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1145
1146         /*
1147          * Modify only the bits which belongs to the port
1148          * and enable respective VBUS_PAD for the port
1149          */
1150         if (tegra->bdata->uses_external_pmic == false) {
1151                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1152                 reg &= ~(port == 2 ? OC_DET_VBUS_ENABLE2_OC_MAP :
1153                         port ? OC_DET_VBUS_ENABLE1_OC_MAP :
1154                                 OC_DET_VBUS_ENABLE0_OC_MAP);
1155
1156                 reg |= (port == 2) ? OC_DET_VBUS_EN2_OC_DETECTED_VBUS_PAD2 :
1157                         port ? OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1 :
1158                                 OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0;
1159                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1160         }
1161         /*
1162          * enable respective VBUS_PAD if port is mapped to any SS port
1163          */
1164         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1165         reg &= ~((port == 2) ? USB2_OC_MAP_PORT2 :
1166                 port ? USB2_OC_MAP_PORT1 : USB2_OC_MAP_PORT0);
1167         reg |= (0x4 | port) << (port * 3);
1168         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1169
1170         ctl0_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl0_0 :
1171                         port ? padregs->usb2_otg_pad1_ctl0_0 :
1172                                 padregs->usb2_otg_pad0_ctl0_0;
1173         ctl1_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl1_0 :
1174                         port ? padregs->usb2_otg_pad1_ctl1_0 :
1175                                 padregs->usb2_otg_pad0_ctl1_0;
1176
1177         reg = readl(tegra->padctl_base + ctl0_offset);
1178         reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
1179                 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
1180                 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
1181
1182         reg |= tegra->pdata->hs_slew;
1183         reg |= (port == 2) ? tegra->pdata->ls_rslew_pad2 :
1184                         port ? tegra->pdata->ls_rslew_pad1 :
1185                         tegra->pdata->ls_rslew_pad0;
1186         reg |= (port == 2) ? tegra->pdata->hs_curr_level_pad2 :
1187                         port ? tegra->pdata->hs_curr_level_pad1 :
1188                         tegra->pdata->hs_curr_level_pad0;
1189         writel(reg, tegra->padctl_base + ctl0_offset);
1190
1191         reg = readl(tegra->padctl_base + ctl1_offset);
1192         reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
1193                 | USB2_OTG_PD_CHRP_FORCE_POWERUP
1194                 | USB2_OTG_PD_DISC_FORCE_POWERUP
1195                 | USB2_OTG_PD_DR);
1196         reg |= (tegra->pdata->hs_iref_cap << 9) |
1197                 (tegra->pdata->hs_term_range_adj << 3);
1198         writel(reg, tegra->padctl_base + ctl1_offset);
1199 }
1200
1201 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
1202         u8 port)
1203 {
1204         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1205         u32 ctl2_offset, ctl4_offset;
1206         u32 reg;
1207
1208         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1209                         padregs->iophy_usb3_pad0_ctl2_0;
1210         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1211                         padregs->iophy_usb3_pad0_ctl4_0;
1212
1213         reg = readl(tegra->padctl_base + ctl2_offset);
1214         reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
1215                 IOPHY_USB3_CDRCNTL);
1216         reg |= tegra->pdata->rx_wander | tegra->pdata->rx_eq |
1217                 tegra->pdata->cdr_cntl;
1218         writel(reg, tegra->padctl_base + ctl2_offset);
1219
1220         reg = readl(tegra->padctl_base + ctl4_offset);
1221         reg = tegra->pdata->dfe_cntl;
1222         writel(reg, tegra->padctl_base + ctl4_offset);
1223
1224         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1225         reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
1226         reg |= (tegra->bdata->ss_portmap &
1227                 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
1228         writel(reg, tegra->padctl_base + padregs->ss_port_map_0);
1229
1230         tegra_xhci_restore_dfe_ctle_context(tegra, port);
1231         /* SATA also if USB3_SS port1 mapped to it */
1232         if ((port == 1) && (XUSB_DEVICE_ID_T124 == tegra->device_id) &&
1233                         (tegra->bdata->lane_owner & BIT(0)))
1234                 tegra_xhci_restore_dfe_ctle_context(tegra, 3);
1235 }
1236
1237 /* This function assigns the USB ports to the controllers,
1238  * then programs the port capabilities and pad parameters
1239  * of ports assigned to XUSB after booted to OS.
1240  */
1241 void
1242 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
1243 {
1244         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1245         u32 reg, oc_bits = 0;
1246
1247         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1248         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
1249         reg |= tegra->pdata->hs_squelch_level | tegra->pdata->hs_disc_lvl;
1250         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1251
1252         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1253         reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3;
1254         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
1255         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1256
1257         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1258         reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
1259         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1260                 reg |= OC_DET_VBUS_ENABLE2_OC_MAP;
1261         writel(reg, tegra->padctl_base + padregs->oc_det_0);
1262
1263         /* check if over current seen. Clear if present */
1264         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1265                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
1266         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1267                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
1268         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1269                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
1270
1271         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1272         if (reg & oc_bits) {
1273                 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
1274                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1275
1276                 usleep_range(100, 200);
1277
1278                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1279                 if (reg & oc_bits)
1280                         xhci_info(tegra->xhci, "Over current still present\n");
1281         }
1282
1283         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1284         reg = USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1;
1285         if (XUSB_DEVICE_ID_T124 == tegra->device_id)
1286                 reg |= USB2_OC_MAP_PORT2;
1287         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1288
1289         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1290                 tegra_xhci_program_utmip_pad(tegra, 0);
1291         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1292                 tegra_xhci_program_utmip_pad(tegra, 1);
1293         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1294                 tegra_xhci_program_utmip_pad(tegra, 2);
1295
1296         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
1297                 tegra_xhci_program_ulpi_pad(tegra, 0);
1298
1299         if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P0)
1300                 tegra_xhci_program_hsic_pad(tegra, 0);
1301         if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P1)
1302                 tegra_xhci_program_hsic_pad(tegra, 1);
1303
1304         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1305                 tegra_xhci_program_ss_pad(tegra, 0);
1306         } else {
1307                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1308                 reg = readl(tegra->padctl_base +
1309                         padregs->iophy_misc_pad_p0_ctl3_0);
1310                 reg &= ~RX_IDLE_MODE;
1311                 reg |= RX_IDLE_MODE_OVRD;
1312                 writel(reg, tegra->padctl_base +
1313                         padregs->iophy_misc_pad_p0_ctl3_0);
1314         }
1315
1316         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1317                 tegra_xhci_program_ss_pad(tegra, 1);
1318         } else {
1319                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1320                 reg = readl(tegra->padctl_base +
1321                         padregs->iophy_misc_pad_p1_ctl3_0);
1322                 reg &= ~RX_IDLE_MODE;
1323                 reg |= RX_IDLE_MODE_OVRD;
1324                 writel(reg, tegra->padctl_base +
1325                         padregs->iophy_misc_pad_p1_ctl3_0);
1326
1327                 /* SATA lane also if USB3_SS port1 mapped to it but unused */
1328                 if (XUSB_DEVICE_ID_T124 == tegra->device_id &&
1329                                 tegra->bdata->lane_owner & BIT(0)) {
1330                         reg = readl(tegra->padctl_base +
1331                                 padregs->iophy_misc_pad_s0_ctl3_0);
1332                         reg &= ~RX_IDLE_MODE;
1333                         reg |= RX_IDLE_MODE_OVRD;
1334                         writel(reg, tegra->padctl_base +
1335                                 padregs->iophy_misc_pad_s0_ctl3_0);
1336                 }
1337         }
1338         if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
1339                 tegra_xhci_setup_gpio_for_ss_lane(tegra);
1340                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
1341         }
1342 }
1343
1344 /* This function read XUSB registers and stores in device context */
1345 static void
1346 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
1347 {
1348
1349         /* a. Save the IPFS registers */
1350         tegra->sregs.msi_bar_sz =
1351                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
1352
1353         tegra->sregs.msi_axi_barst =
1354                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
1355
1356         tegra->sregs.msi_fpci_barst =
1357                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
1358
1359         tegra->sregs.msi_vec0 =
1360                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
1361
1362         tegra->sregs.msi_en_vec0 =
1363                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
1364
1365         tegra->sregs.fpci_error_masks =
1366                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
1367
1368         tegra->sregs.intr_mask =
1369                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1370
1371         tegra->sregs.ipfs_intr_enable =
1372                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
1373
1374         tegra->sregs.ufpci_config =
1375                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
1376
1377         tegra->sregs.clkgate_hysteresis =
1378                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1379
1380         tegra->sregs.xusb_host_mccif_fifo_cntrl =
1381                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
1382
1383         /* b. Save the CFG registers */
1384
1385         tegra->sregs.hs_pls =
1386                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
1387
1388         tegra->sregs.fs_pls =
1389                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
1390
1391         tegra->sregs.hs_fs_speed =
1392                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
1393
1394         tegra->sregs.hs_fs_pp =
1395                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
1396
1397         tegra->sregs.cfg_aru =
1398                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
1399
1400         tegra->sregs.cfg_order =
1401                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
1402
1403         tegra->sregs.cfg_fladj =
1404                 readl(tegra->fpci_base + XUSB_CFG_24);
1405
1406         tegra->sregs.cfg_sid =
1407                 readl(tegra->fpci_base + XUSB_CFG_16);
1408 }
1409
1410 /* This function restores XUSB registers from device context */
1411 static void
1412 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
1413 {
1414         /* Restore Cfg registers */
1415         writel(tegra->sregs.hs_pls,
1416                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
1417
1418         writel(tegra->sregs.fs_pls,
1419                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
1420
1421         writel(tegra->sregs.hs_fs_speed,
1422                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
1423
1424         writel(tegra->sregs.hs_fs_pp,
1425                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
1426
1427         writel(tegra->sregs.cfg_aru,
1428                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
1429
1430         writel(tegra->sregs.cfg_order,
1431                 tegra->fpci_base + XUSB_CFG_FPCICFG);
1432
1433         writel(tegra->sregs.cfg_fladj,
1434                 tegra->fpci_base + XUSB_CFG_24);
1435
1436         writel(tegra->sregs.cfg_sid,
1437                 tegra->fpci_base + XUSB_CFG_16);
1438
1439         /* Restore IPFS registers */
1440
1441         writel(tegra->sregs.msi_bar_sz,
1442                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
1443
1444         writel(tegra->sregs.msi_axi_barst,
1445                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
1446
1447         writel(tegra->sregs.msi_fpci_barst,
1448                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
1449
1450         writel(tegra->sregs.msi_vec0,
1451                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
1452
1453         writel(tegra->sregs.msi_en_vec0,
1454                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
1455
1456         writel(tegra->sregs.fpci_error_masks,
1457                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
1458
1459         writel(tegra->sregs.intr_mask,
1460                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1461
1462         writel(tegra->sregs.ipfs_intr_enable,
1463                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
1464
1465         writel(tegra->sregs.ufpci_config,
1466                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
1467
1468         writel(tegra->sregs.clkgate_hysteresis,
1469                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1470
1471         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
1472                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
1473 }
1474
1475 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
1476 {
1477         struct platform_device *pdev = tegra->pdev;
1478         u32 reg, timeout = 0xff, cmd;
1479
1480         mutex_lock(&tegra->mbox_lock);
1481
1482         do {
1483                 writel(MBOX_OWNER_SW,
1484                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
1485                 reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
1486                 usleep_range(10, 20);
1487         } while (reg != MBOX_OWNER_SW && timeout--);
1488
1489         if ((timeout == 0) && (reg != MBOX_OWNER_SW)) {
1490                 dev_err(&pdev->dev, "Failed to set mbox message owner ID\n");
1491                 mutex_unlock(&tegra->mbox_lock);
1492                 return;
1493         }
1494
1495         writel((MBOX_CMD_MSG_ENABLED << MBOX_CMD_SHIFT),
1496                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
1497
1498         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1499         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
1500         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1501
1502         mutex_unlock(&tegra->mbox_lock);
1503 }
1504
1505 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
1506 {
1507         struct platform_device *pdev = tegra->pdev;
1508         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
1509         u32 phys_addr_lo;
1510         u32 HwReg;
1511         u16 nblocks;
1512         time_t fw_time;
1513         struct tm fw_tm;
1514         u8 hc_caplength;
1515         u32 usbsts, count = 0xff;
1516         struct xhci_cap_regs __iomem *cap_regs;
1517         struct xhci_op_regs __iomem *op_regs;
1518
1519         /* enable mbox interrupt */
1520         writel(readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD) | MBOX_INT_EN,
1521                 tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1522
1523         /* First thing, reset the ARU. By the time we get to
1524          * loading boot code below, reset would be complete.
1525          * alternatively we can busy wait on rst pending bit.
1526          */
1527         /* Don't reset during ELPG/LP0 exit path */
1528         if (resetARU) {
1529                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
1530                 usleep_range(1000, 2000);
1531         }
1532
1533         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
1534                 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
1535                                 csb_read(tegra, XUSB_FALC_CPUCTL));
1536                 return 0;
1537         }
1538
1539         phys_addr_lo = tegra->firmware.dma;
1540         phys_addr_lo += sizeof(struct cfgtbl);
1541
1542         /* Program the size of DFI into ILOAD_ATTR */
1543         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
1544
1545         /* Boot code of the firmware reads the ILOAD_BASE_LO register
1546          * to get to the start of the dfi in system memory.
1547          */
1548         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
1549
1550         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
1551         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
1552
1553         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
1554         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
1555
1556         /* Invalidate L2IMEM. */
1557         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
1558
1559         /* Initiate fetch of Bootcode from system memory into L2IMEM.
1560          * Program BootCode location and size in system memory.
1561          */
1562         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
1563                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
1564                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
1565         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
1566                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
1567                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
1568         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
1569
1570         /* Trigger L2IMEM Load operation. */
1571         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
1572
1573         /* Setup Falcon Auto-fill */
1574         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
1575         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
1576                 nblocks += 1;
1577         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
1578
1579         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
1580         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
1581                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
1582         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
1583
1584         csb_write(tegra, XUSB_FALC_DMACTL, 0);
1585         msleep(50);
1586
1587         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
1588
1589         /* Start Falcon CPU */
1590         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
1591         usleep_range(1000, 2000);
1592
1593         fw_time = cfg_tbl->fwimg_created_time;
1594         time_to_tm(fw_time, 0, &fw_tm);
1595         dev_info(&pdev->dev,
1596                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
1597                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
1598                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
1599                 fw_tm.tm_min, fw_tm.tm_sec,
1600                 csb_read(tegra, XUSB_FALC_CPUCTL));
1601
1602         /* return fail if firmware status is not good */
1603         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
1604                 return -EFAULT;
1605
1606         cap_regs = IO_ADDRESS(tegra->host_phy_base);
1607         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
1608         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
1609
1610         /* wait for USBSTS_CNR to get set */
1611         do {
1612                 usbsts = ioread32(&op_regs->status);
1613         } while ((usbsts & STS_CNR) && count--);
1614
1615         if (!count && (usbsts & STS_CNR)) {
1616                 dev_err(&pdev->dev, "Controller not ready\n");
1617                 return -EFAULT;
1618         }
1619         return 0;
1620 }
1621
1622 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
1623         bool release)
1624 {
1625         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1626         u32 reg;
1627
1628         /* Issue is only applicable for T114 */
1629         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
1630                 return;
1631
1632         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1633         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
1634                         USB2_OTG_PAD_PORT_MASK(2));
1635
1636         if (!release) {
1637                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1638                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
1639                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1640                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
1641                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1642                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
1643         }
1644
1645         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1646 }
1647 /* SS ELPG Entry initiated by fw */
1648 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
1649 {
1650         struct xhci_hcd *xhci = tegra->xhci;
1651         u32 ret = 0;
1652
1653         must_have_sync_lock(tegra);
1654
1655         /* This is SS partition ELPG entry
1656          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
1657          */
1658
1659         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
1660          * only if it is sw initiated one
1661          */
1662
1663         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
1664          * SuperSpeed partition ELPG entry via mailbox protocol
1665          */
1666
1667         /* STEP 2: xHCI PEP driver and XUSB device mode driver
1668          * enable the XUSB wakeup interrupts for the SuperSpeed
1669          * and USB2.0 ports assigned to host.Section 4.1 Step 3
1670          */
1671         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
1672
1673         /* STEP 3: xHCI PEP driver initiates the signal sequence
1674          * to enable the XUSB SSwake detection logic for the
1675          * SuperSpeed ports assigned to host.Section 4.1 Step 4
1676          */
1677         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, true);
1678
1679         /* STEP 4: System Power Management driver asserts reset
1680          * to XUSB SuperSpeed partition then disables its clocks
1681          */
1682         tegra_periph_reset_assert(tegra->ss_clk);
1683         clk_disable(tegra->ss_clk);
1684
1685         usleep_range(100, 200);
1686
1687         /* STEP 5: System Power Management driver disables the
1688          * XUSB SuperSpeed partition power rails.
1689          */
1690         debug_print_portsc(xhci);
1691
1692         /* tegra_powergate_partition also does partition reset assert */
1693         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
1694         if (ret) {
1695                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
1696                                 __func__);
1697                 /* TODO: error recovery? */
1698         }
1699         tegra->ss_pwr_gated = true;
1700
1701         /* STEP 6: xHCI PEP driver initiates the signal sequence
1702          * to enable the XUSB SSwake detection logic for the
1703          * SuperSpeed ports assigned to host.Section 4.1 Step 7
1704          */
1705         tegra_xhci_ss_vcore(tegra->bdata->portmap, true);
1706
1707         return ret;
1708 }
1709
1710 /* Host ELPG Entry */
1711 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
1712 {
1713         struct xhci_hcd *xhci = tegra->xhci;
1714         u32 ret;
1715
1716         must_have_sync_lock(tegra);
1717
1718         /* If ss is already powergated skip ss ctx save stuff */
1719         if (tegra->ss_pwr_gated) {
1720                 xhci_info(xhci, "%s: SS partition is already powergated\n",
1721                         __func__);
1722         } else {
1723                 ret = tegra_xhci_ss_elpg_entry(tegra);
1724                 if (ret) {
1725                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
1726                                 __func__, ret);
1727                         return ret;
1728                 }
1729         }
1730
1731         /* 1. IS INTR PENDING INT_PENDING=1 ? */
1732
1733         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
1734         tegra_xhci_save_xusb_ctx(tegra);
1735
1736         pmc_init(tegra, 1);
1737
1738         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
1739         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
1740                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
1741
1742         /* STEP 4: Assert reset to host clk and disable host clk */
1743         tegra_periph_reset_assert(tegra->host_clk);
1744
1745         clk_disable(tegra->host_clk);
1746
1747         /* wait 150us */
1748         usleep_range(150, 200);
1749
1750         /* flush MC client of XUSB_HOST */
1751         tegra_powergate_mc_flush(TEGRA_POWERGATE_XUSBC);
1752
1753         /* STEP 4: Powergate host partition */
1754         /* tegra_powergate_partition also does partition reset assert */
1755         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
1756         if (ret) {
1757                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
1758                         __func__, ret);
1759                 /* TODO: error handling? */
1760                 return ret;
1761         }
1762         tegra->host_pwr_gated = true;
1763
1764         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1765                 clk_disable(tegra->pll_re_vco_clk);
1766         clk_disable(tegra->emc_clk);
1767         /* set port ownership to SNPS */
1768         tegra_xhci_release_port_ownership(tegra, true);
1769
1770         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
1771                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
1772
1773         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
1774         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
1775                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
1776         return ret;
1777 }
1778
1779 /* SS ELPG Exit triggered by PADCTL irq */
1780 /**
1781  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
1782  *
1783  * This function must be called with tegra->sync_lock acquired.
1784  *
1785  * @tegra: xhci controller context
1786  * @return 0 for success, or error numbers
1787  */
1788 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
1789 {
1790         struct xhci_hcd *xhci = tegra->xhci;
1791         int ret = 0;
1792
1793         must_have_sync_lock(tegra);
1794
1795         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
1796                         tegra->hs_wake_event || tegra->host_resume_req)) {
1797
1798                 /*
1799                  * PWR_UNGATE SS partition. XUSBA
1800                  * tegra_unpowergate_partition also does partition reset
1801                  * deassert
1802                  */
1803                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
1804                 if (ret) {
1805                         xhci_err(xhci,
1806                         "%s: could not unpowergate xusba partition %d\n",
1807                         __func__, ret);
1808                         goto out;
1809                 }
1810                 if (tegra->ss_wake_event)
1811                         tegra->ss_wake_event = false;
1812
1813         } else {
1814                 xhci_info(xhci, "%s: ss already power gated\n",
1815                         __func__);
1816                 return ret;
1817         }
1818
1819         /* Step 3: Enable clock to ss partition */
1820         clk_enable(tegra->ss_clk);
1821
1822         /* Step 4: Disable ss wake detection logic */
1823         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
1824
1825         /* Step 4.1: Disable ss wake detection logic */
1826         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
1827
1828         /* wait 150us */
1829         usleep_range(150, 200);
1830
1831         /* Step 4.2: Disable ss wake detection logic */
1832         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
1833
1834         /* Step 6 Deassert reset for ss clks */
1835         tegra_periph_reset_deassert(tegra->ss_clk);
1836
1837         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
1838         tegra->ss_pwr_gated = false;
1839 out:
1840         return ret;
1841 }
1842
1843 static void ss_partition_elpg_exit_work(struct work_struct *work)
1844 {
1845         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
1846                 ss_elpg_exit_work);
1847
1848         mutex_lock(&tegra->sync_lock);
1849         tegra_xhci_ss_partition_elpg_exit(tegra);
1850         mutex_unlock(&tegra->sync_lock);
1851 }
1852
1853 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
1854 static void update_remote_wakeup_ports_pmc(struct tegra_xhci_hcd *tegra)
1855 {
1856         struct xhci_hcd *xhci = tegra->xhci;
1857         u32 wake2_status;
1858
1859 #define PMC_WAKE2_STATUS        0x168
1860 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
1861
1862         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
1863
1864         if (wake2_status & PADCTL_WAKE) {
1865                 /* FIXME: This is customized for Dalmore, find a generic way */
1866                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
1867                 /* clear wake status */
1868                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
1869         }
1870
1871         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
1872                         __func__, tegra->usb3_rh_remote_wakeup_ports);
1873 }
1874
1875 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
1876 {
1877         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1878         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
1879         int port, num_ports;
1880         unsigned long *remote_wakeup_ports;
1881         u32 portsc;
1882         __le32 __iomem  **port_array;
1883         unsigned char *rh;
1884         unsigned int retry = 64;
1885
1886
1887         if (hcd == xhci->shared_hcd) {
1888                 port_array = xhci->usb3_ports;
1889                 num_ports = xhci->num_usb3_ports;
1890                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
1891                 rh = "usb3 roothub";
1892         } else
1893                 return;
1894
1895         while (*remote_wakeup_ports && retry--) {
1896                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
1897                         portsc = xhci_readl(xhci, port_array[port]);
1898
1899                         if (!(portsc & PORT_CONNECT)) {
1900                                 /* nothing to do if already disconnected */
1901                                 clear_bit(port, remote_wakeup_ports);
1902                                 continue;
1903                         }
1904
1905                         if ((portsc & PORT_PLS_MASK) == XDEV_U0)
1906                                 clear_bit(port, remote_wakeup_ports);
1907                         else
1908                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
1909                                                 __func__, rh, port, portsc);
1910                 }
1911
1912                 if (*remote_wakeup_ports)
1913                         msleep(20); /* give some time, irq will direct U0 */
1914         }
1915
1916         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
1917                         *remote_wakeup_ports);
1918 }
1919
1920 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
1921 {
1922         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1923         u32 reg, utmip_rctrl_val, utmip_tctrl_val;
1924
1925         /* Program XUSB as port owner for all usb2 ports */
1926         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1927         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
1928                         USB2_OTG_PAD_PORT_MASK(2));
1929         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
1930                 USB2_OTG_PAD_PORT_OWNER_XUSB(1) | USB2_OTG_PAD_PORT_MASK(2);
1931         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1932
1933         /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
1934          * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
1935          */
1936         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1937         reg &= ~((1 << 12) | (1 << 13));
1938         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1939
1940         /* wait 20us */
1941         usleep_range(20, 30);
1942
1943         /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
1944          * :: TCTRL and RCTRL
1945          */
1946         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl1_0);
1947         utmip_rctrl_val = RCTRL(reg);
1948         utmip_tctrl_val = TCTRL(reg);
1949
1950         /*
1951          * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
1952          * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
1953          */
1954         pmc_data.utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
1955         pmc_data.utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
1956
1957         xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
1958                 pmc_data.utmip_rctrl_val, pmc_data.utmip_tctrl_val);
1959
1960         /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
1961          * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
1962          */
1963         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1964         reg |= (1 << 13);
1965         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1966
1967         /* Program these values into PMC regiseter and program the
1968          * PMC override
1969          */
1970         reg = PMC_TCTRL_VAL(pmc_data.utmip_tctrl_val) |
1971                 PMC_RCTRL_VAL(pmc_data.utmip_rctrl_val);
1972         tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG, 0xffffffff, reg);
1973
1974         reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
1975         tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
1976
1977         /* Restore correct port ownership in padctl */
1978         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1979         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
1980                         USB2_OTG_PAD_PORT_MASK(2));
1981         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1982                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
1983         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1984                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
1985         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1986                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
1987         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1988 }
1989
1990 /* Host ELPG Exit triggered by PADCTL irq */
1991 /**
1992  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
1993  *
1994  * This function must be called with tegra->sync_lock acquired.
1995  *
1996  * @tegra: xhci controller context
1997  * @return 0 for success, or error numbers
1998  */
1999 static int
2000 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2001 {
2002         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2003         struct xhci_hcd *xhci = tegra->xhci;
2004         int ret = 0;
2005
2006         must_have_sync_lock(tegra);
2007
2008         if (!tegra->hc_in_elpg)
2009                 return 0;
2010
2011         clk_enable(tegra->emc_clk);
2012         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2013                 clk_enable(tegra->pll_re_vco_clk);
2014         /* Step 2: Enable clock to host partition */
2015         clk_enable(tegra->host_clk);
2016
2017         if (tegra->lp0_exit) {
2018                 u32 reg, oc_bits = 0;
2019
2020                 /* Issue is only applicable for T114 */
2021                 if (XUSB_DEVICE_ID_T114 == tegra->device_id)
2022                         tegra_xhci_war_for_tctrl_rctrl(tegra);
2023                 /* check if over current seen. Clear if present */
2024                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2025                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2026                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2027                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2028                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2029                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2030
2031                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2032                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
2033                 if (reg & oc_bits) {
2034                         xhci_info(xhci, "Over current detected. Clearing...\n");
2035                         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2036
2037                         usleep_range(100, 200);
2038
2039                         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2040                         if (reg & oc_bits)
2041                                 xhci_info(xhci, "Over current still present\n");
2042                 }
2043                 tegra_xhci_padctl_portmap_and_caps(tegra);
2044                 /* release clamps post deassert */
2045                 tegra->lp0_exit = false;
2046         }
2047
2048         /* Clear FLUSH_ENABLE of MC client */
2049         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
2050
2051         /* set port ownership back to xusb */
2052         tegra_xhci_release_port_ownership(tegra, false);
2053
2054         /*
2055          * PWR_UNGATE Host partition. XUSBC
2056          * tegra_unpowergate_partition also does partition reset deassert
2057          */
2058         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
2059         if (ret) {
2060                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2061                         __func__, ret);
2062                 goto out;
2063         }
2064
2065         /* Step 4: Deassert reset to host partition clk */
2066         tegra_periph_reset_deassert(tegra->host_clk);
2067
2068         /* Step 6.1: IPFS and XUSB BAR initialization */
2069         tegra_xhci_cfg(tegra);
2070
2071         /* Step 6.2: IPFS and XUSB related restore */
2072         tegra_xhci_restore_ctx(tegra);
2073
2074         /* Step 8: xhci spec related ctx restore
2075          * will be done in xhci_resume().Do it here.
2076          */
2077
2078         tegra_xhci_ss_partition_elpg_exit(tegra);
2079
2080         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
2081         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
2082                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
2083                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
2084         }
2085
2086         /* clear ovrd bits */
2087         tegra_xhci_rx_idle_mode_override(tegra, false);
2088
2089         /* Load firmware */
2090         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
2091                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
2092                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
2093                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
2094                         __func__,
2095                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
2096                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
2097                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
2098                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
2099                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
2100                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
2101                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
2102                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
2103                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
2104         debug_print_portsc(xhci);
2105
2106         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
2107         if (ret < 0) {
2108                 xhci_err(xhci, "%s: failed to load firmware %d\n",
2109                         __func__, ret);
2110                 goto out;
2111         }
2112
2113         pmc_init(tegra, 0);
2114
2115         tegra->hc_in_elpg = false;
2116         ret = xhci_resume(tegra->xhci, 0);
2117         if (ret) {
2118                 xhci_err(xhci, "%s: could not resume right %d\n",
2119                                 __func__, ret);
2120                 goto out;
2121         }
2122
2123         update_remote_wakeup_ports_pmc(tegra);
2124
2125         if (tegra->hs_wake_event)
2126                 tegra->hs_wake_event = false;
2127
2128         if (tegra->host_resume_req)
2129                 tegra->host_resume_req = false;
2130
2131         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
2132                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
2133
2134         tegra->host_pwr_gated = false;
2135 out:
2136         return ret;
2137 }
2138
2139 static void host_partition_elpg_exit_work(struct work_struct *work)
2140 {
2141         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2142                 host_elpg_exit_work);
2143
2144         mutex_lock(&tegra->sync_lock);
2145         tegra_xhci_host_partition_elpg_exit(tegra);
2146         mutex_unlock(&tegra->sync_lock);
2147 }
2148
2149 /* Mailbox handling function. This function handles requests
2150  * from firmware and communicates with clock and powergating
2151  * module to alter clock rates and to power gate/ungate xusb
2152  * partitions.
2153  *
2154  * Following is the structure of mailbox messages.
2155  * bit 31:28 - msg type
2156  * bits 27:0 - mbox data
2157  * FIXME:  Check if we can just call clock functions like below
2158  * or should we schedule it for calling later ?
2159  */
2160
2161 static void
2162 tegra_xhci_process_mbox_message(struct work_struct *work)
2163 {
2164         u32 sw_resp = 0, cmd, data_in, fw_msg;
2165         int ret = 0;
2166         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2167                                         mbox_work);
2168         struct xhci_hcd *xhci = tegra->xhci;
2169         unsigned int freq_khz;
2170
2171         mutex_lock(&tegra->mbox_lock);
2172
2173         /* get the owner id */
2174         tegra->mbox_owner = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2175         tegra->mbox_owner &= MBOX_OWNER_ID_MASK;
2176
2177         /* get the mbox message from firmware */
2178         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
2179
2180         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2181         if (data_in) {
2182                 mutex_unlock(&tegra->mbox_lock);
2183                 return;
2184         }
2185
2186         /* get cmd type and cmd data */
2187         tegra->cmd_type = (fw_msg & MBOX_CMD_TYPE_MASK) >> MBOX_CMD_SHIFT;
2188         tegra->cmd_data = (fw_msg & MBOX_CMD_DATA_MASK);
2189
2190         /* decode the message and make appropriate requests to
2191          * clock or powergating module.
2192          */
2193
2194         switch (tegra->cmd_type) {
2195         case MBOX_CMD_INC_FALC_CLOCK:
2196         case MBOX_CMD_DEC_FALC_CLOCK:
2197                 ret = tegra_xusb_request_clk_rate(
2198                                 tegra,
2199                                 tegra->falc_clk,
2200                                 tegra->cmd_data,
2201                                 &sw_resp);
2202                 if (ret)
2203                         xhci_err(xhci, "%s: could not set required falc rate\n",
2204                                 __func__);
2205                 goto send_sw_response;
2206         case MBOX_CMD_INC_SSPI_CLOCK:
2207         case MBOX_CMD_DEC_SSPI_CLOCK:
2208                 ret = tegra_xusb_request_clk_rate(
2209                                 tegra,
2210                                 tegra->ss_src_clk,
2211                                 tegra->cmd_data,
2212                                 &sw_resp);
2213                 if (ret)
2214                         xhci_err(xhci, "%s: could not set required ss rate.\n",
2215                                 __func__);
2216                 goto send_sw_response;
2217         case MBOX_CMD_SET_BW:
2218                 /* fw sends BW request in MByte/sec */
2219                 freq_khz = tegra_emc_bw_to_freq_req(tegra->cmd_data << 10);
2220                 clk_set_rate(tegra->emc_clk, freq_khz * 1000);
2221
2222                 /* clear MBOX_SMI_INT_EN bit */
2223                 cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2224                 cmd &= ~MBOX_SMI_INT_EN;
2225                 writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2226
2227                 /* clear mbox owner as ACK will not be sent for this request */
2228                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2229                 break;
2230         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
2231                 tegra_xhci_save_dfe_ctle_context(tegra, tegra->cmd_data);
2232                 tegra_xhci_restore_dfe_ctle_context(tegra, tegra->cmd_data);
2233                 /* SATA lane also if USB3_SS port1 mapped to it */
2234                 if (tegra->cmd_data == 0x1 &&
2235                         XUSB_DEVICE_ID_T124 == tegra->device_id &&
2236                                 tegra->bdata->lane_owner & BIT(0)) {
2237                         tegra_xhci_save_dfe_ctle_context(tegra, 3);
2238                         tegra_xhci_restore_dfe_ctle_context(tegra, 3);
2239                 }
2240
2241                 sw_resp |= (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
2242                 goto send_sw_response;
2243         case MBOX_CMD_ACK:
2244                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2245                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2246                 break;
2247         case MBOX_CMD_NACK:
2248                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2249                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2250                 break;
2251         default:
2252                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
2253                                 __func__, tegra->cmd_type);
2254         }
2255         mutex_unlock(&tegra->mbox_lock);
2256         return;
2257
2258 send_sw_response:
2259         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2260         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2261         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
2262         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2263
2264         mutex_unlock(&tegra->mbox_lock);
2265 }
2266
2267 static irqreturn_t tegra_xhci_xusb_host_irq(int irq, void *ptrdev)
2268 {
2269         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2270         struct xhci_hcd *xhci = tegra->xhci;
2271
2272         xhci_dbg(xhci, "%s", __func__);
2273         return IRQ_HANDLED;
2274 }
2275
2276 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
2277 {
2278         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2279         struct xhci_hcd *xhci = tegra->xhci;
2280         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2281         u32 elpg_program0 = 0;
2282
2283         spin_lock(&tegra->lock);
2284
2285         tegra->last_jiffies = jiffies;
2286
2287         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
2288         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
2289
2290         /* Clear the interrupt cause. We already read the intr status. */
2291         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2292         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
2293
2294         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
2295         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
2296                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2297         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
2298                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
2299         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
2300                 __func__,
2301                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad0_ctl0_0));
2302         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
2303                 __func__,
2304                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad1_ctl0_0));
2305         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
2306                 __func__,
2307                 readl(tegra->padctl_base + padregs->usb2_bchrg_bias_pad_0));
2308
2309         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
2310                 tegra->ss_wake_event = true;
2311         else if (elpg_program0 &
2312                         (USB2_PORT0_WAKEUP_EVENT | USB2_PORT1_WAKEUP_EVENT))
2313                 tegra->hs_wake_event = true;
2314
2315         if (tegra->ss_wake_event || tegra->hs_wake_event) {
2316                 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
2317                         xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
2318                         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
2319                 } else if (tegra->ss_pwr_gated
2320                                 && tegra->host_pwr_gated) {
2321                         xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
2322                                 __func__);
2323                         schedule_work(&tegra->host_elpg_exit_work);
2324                 }
2325         } else {
2326                 xhci_err(xhci, "error: wake due to no hs/ss event\n");
2327                 tegra_usb_pad_reg_write(padregs->elpg_program_0, 0xffffffff);
2328         }
2329         spin_unlock(&tegra->lock);
2330         return IRQ_HANDLED;
2331 }
2332
2333 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
2334 {
2335         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2336         u32 temp;
2337
2338         spin_lock(&tegra->lock);
2339
2340         /* clear the mbox intr status 1st thing. Other
2341          * bits are W1C bits, so just write to SMI bit.
2342          */
2343
2344         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
2345
2346         /* write 1 to clear SMI INTR en bit ( bit 3 ) */
2347         temp = MBOX_SMI_INTR_EN;
2348         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
2349
2350         schedule_work(&tegra->mbox_work);
2351
2352         spin_unlock(&tegra->lock);
2353         return IRQ_HANDLED;
2354 }
2355
2356 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
2357 {
2358         /*
2359          * As of now platform drivers don't provide MSI support so we ensure
2360          * here that the generic code does not try to make a pci_dev from our
2361          * dev struct in order to setup MSI
2362          */
2363         xhci->quirks |= XHCI_BROKEN_MSI;
2364         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
2365 }
2366
2367 /* called during probe() after chip reset completes */
2368 static int xhci_plat_setup(struct usb_hcd *hcd)
2369 {
2370         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
2371 }
2372
2373 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
2374         const char *name, void __iomem **region)
2375 {
2376         struct resource *res;
2377         void __iomem *mem;
2378
2379         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
2380         if (!res) {
2381                 dev_err(&pdev->dev, "memory resource %s doesn't exist\n", name);
2382                 return -ENODEV;
2383         }
2384
2385         mem = devm_request_and_ioremap(&pdev->dev, res);
2386         if (!mem) {
2387                 dev_err(&pdev->dev, "failed to ioremap for %s\n", name);
2388                 return -EFAULT;
2389         }
2390         *region = mem;
2391
2392         return 0;
2393 }
2394
2395 static int tegra_xhci_request_irq(struct platform_device *pdev,
2396         const char *rscname, irq_handler_t handler, unsigned long irqflags,
2397         const char *devname, int *irq_no)
2398 {
2399         int ret;
2400         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2401         struct resource *res;
2402
2403         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, rscname);
2404         if (!res) {
2405                 dev_err(&pdev->dev, "irq resource %s doesn't exist\n", rscname);
2406                 return -ENODEV;
2407         }
2408
2409         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
2410                         devname, tegra);
2411         if (ret != 0) {
2412                 dev_err(&pdev->dev,
2413                         "failed to request_irq for %s (irq %d), error = %d\n",
2414                         devname, res->start, ret);
2415                 return ret;
2416         }
2417         *irq_no = res->start;
2418
2419         return 0;
2420 }
2421
2422 #ifdef CONFIG_PM
2423
2424 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
2425 {
2426         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2427         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2428         int err = 0;
2429         unsigned long flags;
2430
2431         mutex_lock(&tegra->sync_lock);
2432
2433         if (xhci->shared_hcd == hcd) {
2434                 tegra->usb3_rh_suspend = true;
2435                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
2436         } else if (xhci->main_hcd == hcd) {
2437                 tegra->usb2_rh_suspend = true;
2438                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
2439         }
2440
2441         WARN_ON(tegra->hc_in_elpg);
2442
2443         /* suspend xhci bus. This will also set remote mask */
2444         err = xhci_bus_suspend(hcd);
2445         if (err) {
2446                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
2447                                 __func__, err);
2448                 goto xhci_bus_suspend_failed;
2449         }
2450
2451         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
2452                 goto done; /* one of the root hubs is still working */
2453
2454         spin_lock_irqsave(&tegra->lock, flags);
2455         tegra->hc_in_elpg = true;
2456         spin_unlock_irqrestore(&tegra->lock, flags);
2457
2458         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
2459
2460         /* save xhci spec ctx. Already done by xhci_suspend */
2461         err = xhci_suspend(tegra->xhci);
2462         if (err) {
2463                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
2464                 goto xhci_suspend_failed;
2465         }
2466
2467         /* Powergate host. Include ss power gate if not already done */
2468         err = tegra_xhci_host_elpg_entry(tegra);
2469         if (err) {
2470                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
2471                                 __func__, err);
2472                 goto tegra_xhci_host_elpg_entry_failed;
2473         }
2474
2475         /* At this point,ensure ss/hs intr enables are always on */
2476         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2477         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2478
2479 done:
2480         /* pads are disabled only if usb2 root hub in xusb is idle */
2481         /* pads will actually be disabled only when all usb2 ports are idle */
2482         if (xhci->main_hcd == hcd) {
2483                 utmi_phy_pad_disable();
2484                 utmi_phy_iddq_override(true);
2485                 /* port ownership to SNPS when no HS connected to save power */
2486                 if (!is_any_hs_connected(xhci))
2487                         tegra_xhci_release_port_ownership(tegra, true);
2488         } else if (xhci->shared_hcd == hcd) {
2489                 /* save leakage power when SS not in use.
2490                  * This is also done when fw mbox message is received for freq
2491                  * decrease but on T114 we don't change freq due to sw WAR
2492                  * used for hs disconnect issue.
2493                  */
2494                 tegra_xhci_rx_idle_mode_override(tegra, true);
2495         }
2496         mutex_unlock(&tegra->sync_lock);
2497         return 0;
2498
2499 tegra_xhci_host_elpg_entry_failed:
2500
2501 xhci_suspend_failed:
2502         tegra->hc_in_elpg = false;
2503 xhci_bus_suspend_failed:
2504         if (xhci->shared_hcd == hcd)
2505                 tegra->usb3_rh_suspend = false;
2506         else if (xhci->main_hcd == hcd)
2507                 tegra->usb2_rh_suspend = false;
2508
2509         mutex_unlock(&tegra->sync_lock);
2510         return err;
2511 }
2512
2513 /* First, USB2HCD and then USB3HCD resume will be called */
2514 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
2515 {
2516         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2517         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2518         int err = 0;
2519
2520         mutex_lock(&tegra->sync_lock);
2521
2522         tegra->host_resume_req = true;
2523
2524         if (xhci->shared_hcd == hcd)
2525                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
2526         else if (xhci->main_hcd == hcd)
2527                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
2528
2529         /* pads are disabled only if usb2 root hub in xusb is idle */
2530         /* pads will actually be disabled only when all usb2 ports are idle */
2531         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
2532                 utmi_phy_pad_enable();
2533                 utmi_phy_iddq_override(false);
2534                 tegra_xhci_release_port_ownership(tegra, false);
2535         } else if (xhci->shared_hcd == hcd && tegra->usb3_rh_suspend) {
2536                 /* clear ovrd bits */
2537                 tegra_xhci_rx_idle_mode_override(tegra, false);
2538         }
2539         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
2540                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
2541                         tegra_xhci_host_partition_elpg_exit(tegra);
2542         }
2543
2544          /* handle remote wakeup before resuming bus */
2545         wait_remote_wakeup_ports(hcd);
2546
2547         err = xhci_bus_resume(hcd);
2548         if (err) {
2549                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
2550                                 __func__, err);
2551                 goto xhci_bus_resume_failed;
2552         }
2553
2554         if (xhci->shared_hcd == hcd)
2555                 tegra->usb3_rh_suspend = false;
2556         else if (xhci->main_hcd == hcd)
2557                 tegra->usb2_rh_suspend = false;
2558
2559         mutex_unlock(&tegra->sync_lock);
2560         return 0;
2561
2562 xhci_bus_resume_failed:
2563         /* TODO: reverse elpg? */
2564         mutex_unlock(&tegra->sync_lock);
2565         return err;
2566 }
2567 #endif
2568
2569 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
2570 {
2571         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2572         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2573         irqreturn_t iret = IRQ_HANDLED;
2574         u32 status;
2575
2576         spin_lock(&tegra->lock);
2577         if (tegra->hc_in_elpg) {
2578                 spin_lock(&xhci->lock);
2579                 if (HCD_HW_ACCESSIBLE(hcd)) {
2580                         status = xhci_readl(xhci, &xhci->op_regs->status);
2581                         status |= STS_EINT;
2582                         xhci_writel(xhci, status, &xhci->op_regs->status);
2583                 }
2584                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
2585                                 __func__);
2586                 schedule_work(&tegra->host_elpg_exit_work);
2587                 spin_unlock(&xhci->lock);
2588         } else
2589                 iret = xhci_irq(hcd);
2590         spin_unlock(&tegra->lock);
2591
2592         return iret;
2593 }
2594
2595
2596 static const struct hc_driver tegra_plat_xhci_driver = {
2597         .description =          "tegra-xhci",
2598         .product_desc =         "Nvidia xHCI Host Controller",
2599         .hcd_priv_size =        sizeof(struct xhci_hcd *),
2600
2601         /*
2602          * generic hardware linkage
2603          */
2604         .irq =                  tegra_xhci_irq,
2605         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
2606
2607         /*
2608          * basic lifecycle operations
2609          */
2610         .reset =                xhci_plat_setup,
2611         .start =                xhci_run,
2612         .stop =                 xhci_stop,
2613         .shutdown =             xhci_shutdown,
2614
2615         /*
2616          * managing i/o requests and associated device resources
2617          */
2618         .urb_enqueue =          xhci_urb_enqueue,
2619         .urb_dequeue =          xhci_urb_dequeue,
2620         .alloc_dev =            xhci_alloc_dev,
2621         .free_dev =             xhci_free_dev,
2622         .alloc_streams =        xhci_alloc_streams,
2623         .free_streams =         xhci_free_streams,
2624         .add_endpoint =         xhci_add_endpoint,
2625         .drop_endpoint =        xhci_drop_endpoint,
2626         .endpoint_reset =       xhci_endpoint_reset,
2627         .check_bandwidth =      xhci_check_bandwidth,
2628         .reset_bandwidth =      xhci_reset_bandwidth,
2629         .address_device =       xhci_address_device,
2630         .update_hub_device =    xhci_update_hub_device,
2631         .reset_device =         xhci_discover_or_reset_device,
2632
2633         /*
2634          * scheduling support
2635          */
2636         .get_frame_number =     xhci_get_frame,
2637
2638         /* Root hub support */
2639         .hub_control =          xhci_hub_control,
2640         .hub_status_data =      xhci_hub_status_data,
2641
2642 #ifdef CONFIG_PM
2643         .bus_suspend =          tegra_xhci_bus_suspend,
2644         .bus_resume =           tegra_xhci_bus_resume,
2645 #endif
2646 };
2647
2648 #ifdef CONFIG_PM
2649 static int
2650 tegra_xhci_suspend(struct platform_device *pdev,
2651                                                 pm_message_t state)
2652 {
2653         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2654         struct xhci_hcd *xhci = tegra->xhci;
2655
2656         int ret = 0;
2657
2658         mutex_lock(&tegra->sync_lock);
2659         if (!tegra->hc_in_elpg) {
2660                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
2661                                 __func__);
2662                 mutex_unlock(&tegra->sync_lock);
2663                 return -EBUSY;
2664         }
2665         mutex_unlock(&tegra->sync_lock);
2666
2667         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2668         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
2669
2670         /* enable_irq_wake for ss ports */
2671         ret = enable_irq_wake(tegra->padctl_irq);
2672         if (ret < 0) {
2673                 xhci_err(xhci,
2674                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
2675                 __func__, tegra->padctl_irq, ret);
2676         }
2677
2678         /* enable_irq_wake for hs/fs/ls ports */
2679         ret = enable_irq_wake(tegra->usb3_irq);
2680         if (ret < 0) {
2681                 xhci_err(xhci,
2682                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
2683                 __func__, tegra->usb3_irq, ret);
2684         }
2685         regulator_disable(tegra->xusb_avdd_usb3_pll_reg);
2686         regulator_disable(tegra->xusb_avddio_usb3_reg);
2687         tegra_usb2_clocks_deinit(tegra);
2688
2689         return ret;
2690 }
2691
2692 static int
2693 tegra_xhci_resume(struct platform_device *pdev)
2694 {
2695         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2696
2697         dev_dbg(&pdev->dev, "%s\n", __func__);
2698
2699         tegra->last_jiffies = jiffies;
2700
2701         disable_irq_wake(tegra->padctl_irq);
2702         disable_irq_wake(tegra->usb3_irq);
2703         tegra->lp0_exit = true;
2704
2705         regulator_enable(tegra->xusb_avddio_usb3_reg);
2706         regulator_enable(tegra->xusb_avdd_usb3_pll_reg);
2707         tegra_usb2_clocks_init(tegra);
2708
2709         return 0;
2710 }
2711 #endif
2712
2713
2714 static int init_bootloader_firmware(struct tegra_xhci_hcd *tegra)
2715 {
2716         struct platform_device *pdev = tegra->pdev;
2717         void __iomem *fw_mmio_base;
2718         phys_addr_t fw_mem_phy_addr;
2719         size_t fw_size;
2720         dma_addr_t fw_dma;
2721 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2722         int ret;
2723 #endif
2724
2725         /* bootloader saved firmware memory address in PMC SCRATCH34 register */
2726         fw_mem_phy_addr = tegra_usb_pmc_reg_read(PMC_SCRATCH34);
2727
2728         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
2729                         fw_mem_phy_addr, sizeof(struct cfgtbl));
2730
2731         if (!fw_mmio_base) {
2732                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
2733                                         fw_mem_phy_addr);
2734                         return -ENOMEM;
2735         }
2736
2737         fw_size = ioread32(fw_mmio_base + FW_SIZE_OFFSET);
2738         devm_iounmap(&pdev->dev, fw_mmio_base);
2739
2740         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
2741                         fw_mem_phy_addr, fw_size);
2742         if (!fw_mmio_base) {
2743                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
2744                                         fw_mem_phy_addr);
2745                         return -ENOMEM;
2746         }
2747
2748         dev_info(&pdev->dev, "Firmware Memory: phy 0x%x mapped 0x%p (%d Bytes)\n",
2749                         fw_mem_phy_addr, fw_mmio_base, fw_size);
2750
2751 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2752         fw_dma = dma_map_linear(&pdev->dev, fw_mem_phy_addr, fw_size,
2753                         DMA_TO_DEVICE);
2754         if (fw_dma == DMA_ERROR_CODE) {
2755                 dev_err(&pdev->dev, "%s: dma_map_linear failed\n",
2756                                 __func__);
2757                 ret = -ENOMEM;
2758                 goto error_iounmap;
2759         }
2760 #else
2761         fw_dma = fw_mem_phy_addr;
2762 #endif
2763         dev_info(&pdev->dev, "Firmware DMA Memory: dma 0x%p (%d Bytes)\n",
2764                         (void *) fw_dma, fw_size);
2765
2766         /* all set and ready to go */
2767         tegra->firmware.data = fw_mmio_base;
2768         tegra->firmware.dma = fw_dma;
2769         tegra->firmware.size = fw_size;
2770
2771         return 0;
2772
2773 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2774 error_iounmap:
2775         devm_iounmap(&pdev->dev, fw_mmio_base);
2776         return ret;
2777 #endif
2778 }
2779
2780 static void deinit_bootloader_firmware(struct tegra_xhci_hcd *tegra)
2781 {
2782         struct platform_device *pdev = tegra->pdev;
2783         void __iomem *fw_mmio_base = tegra->firmware.data;
2784
2785 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2786         dma_unmap_single(&pdev->dev, tegra->firmware.dma,
2787                         tegra->firmware.size, DMA_TO_DEVICE);
2788 #endif
2789         devm_iounmap(&pdev->dev, fw_mmio_base);
2790
2791         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
2792 }
2793
2794 static int init_firmware(struct tegra_xhci_hcd *tegra)
2795 {
2796         return init_bootloader_firmware(tegra);
2797 }
2798
2799 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
2800 {
2801         deinit_bootloader_firmware(tegra);
2802 }
2803
2804 static struct tegra_xusb_padctl_regs t114_padregs_offset = {
2805         .boot_media_0                   = 0x0,
2806         .usb2_pad_mux_0                 = 0x4,
2807         .usb2_port_cap_0                = 0x8,
2808         .snps_oc_map_0                  = 0xc,
2809         .usb2_oc_map_0                  = 0x10,
2810         .ss_port_map_0                  = 0x14,
2811         .oc_det_0                       = 0x18,
2812         .elpg_program_0                 = 0x1c,
2813         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
2814         .usb2_bchrg_otgpad0_ctl1_0      = 0xffff,
2815         .usb2_bchrg_otgpad1_ctl0_0      = 0x24,
2816         .usb2_bchrg_otgpad1_ctl1_0      = 0xffff,
2817         .usb2_bchrg_otgpad2_ctl0_0      = 0xffff,
2818         .usb2_bchrg_otgpad2_ctl1_0      = 0xffff,
2819         .usb2_bchrg_bias_pad_0          = 0x28,
2820         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
2821         .iophy_pll_p0_ctl1_0            = 0x30,
2822         .iophy_pll_p0_ctl2_0            = 0x34,
2823         .iophy_pll_p0_ctl3_0            = 0x38,
2824         .iophy_pll_p0_ctl4_0            = 0x3c,
2825         .iophy_usb3_pad0_ctl1_0         = 0x40,
2826         .iophy_usb3_pad1_ctl1_0         = 0x44,
2827         .iophy_usb3_pad0_ctl2_0         = 0x48,
2828         .iophy_usb3_pad1_ctl2_0         = 0x4c,
2829         .iophy_usb3_pad0_ctl3_0         = 0x50,
2830         .iophy_usb3_pad1_ctl3_0         = 0x54,
2831         .iophy_usb3_pad0_ctl4_0         = 0x58,
2832         .iophy_usb3_pad1_ctl4_0         = 0x5c,
2833         .iophy_misc_pad_p0_ctl1_0       = 0x60,
2834         .iophy_misc_pad_p1_ctl1_0       = 0x64,
2835         .iophy_misc_pad_p0_ctl2_0       = 0x68,
2836         .iophy_misc_pad_p1_ctl2_0       = 0x6c,
2837         .iophy_misc_pad_p0_ctl3_0       = 0x70,
2838         .iophy_misc_pad_p1_ctl3_0       = 0x74,
2839         .iophy_misc_pad_p0_ctl4_0       = 0x78,
2840         .iophy_misc_pad_p1_ctl4_0       = 0x7c,
2841         .iophy_misc_pad_p0_ctl5_0       = 0x80,
2842         .iophy_misc_pad_p1_ctl5_0       = 0x84,
2843         .iophy_misc_pad_p0_ctl6_0       = 0x88,
2844         .iophy_misc_pad_p1_ctl6_0       = 0x8c,
2845         .usb2_otg_pad0_ctl0_0           = 0x90,
2846         .usb2_otg_pad1_ctl0_0           = 0x94,
2847         .usb2_otg_pad2_ctl0_0           = 0xffff,
2848         .usb2_otg_pad0_ctl1_0           = 0x98,
2849         .usb2_otg_pad1_ctl1_0           = 0x9c,
2850         .usb2_otg_pad2_ctl1_0           = 0xffff,
2851         .usb2_bias_pad_ctl0_0           = 0xa0,
2852         .usb2_bias_pad_ctl1_0           = 0xa4,
2853         .usb2_hsic_pad0_ctl0_0          = 0xa8,
2854         .usb2_hsic_pad1_ctl0_0          = 0xac,
2855         .usb2_hsic_pad0_ctl1_0          = 0xb0,
2856         .usb2_hsic_pad1_ctl1_0          = 0xb4,
2857         .usb2_hsic_pad0_ctl2_0          = 0xb8,
2858         .usb2_hsic_pad1_ctl2_0          = 0xbc,
2859         .ulpi_link_trim_ctl0            = 0xc0,
2860         .ulpi_null_clk_trim_ctl0        = 0xc4,
2861         .hsic_strb_trim_ctl0            = 0xc8,
2862         .wake_ctl0                      = 0xcc,
2863         .pm_spare0                      = 0xd0,
2864         .iophy_misc_pad_p2_ctl1_0       = 0xffff,
2865         .iophy_misc_pad_p3_ctl1_0       = 0xffff,
2866         .iophy_misc_pad_p4_ctl1_0       = 0xffff,
2867         .iophy_misc_pad_p2_ctl2_0       = 0xffff,
2868         .iophy_misc_pad_p3_ctl2_0       = 0xffff,
2869         .iophy_misc_pad_p4_ctl2_0       = 0xffff,
2870         .iophy_misc_pad_p2_ctl3_0       = 0xffff,
2871         .iophy_misc_pad_p3_ctl3_0       = 0xffff,
2872         .iophy_misc_pad_p4_ctl3_0       = 0xffff,
2873         .iophy_misc_pad_p2_ctl4_0       = 0xffff,
2874         .iophy_misc_pad_p3_ctl4_0       = 0xffff,
2875         .iophy_misc_pad_p4_ctl4_0       = 0xffff,
2876         .iophy_misc_pad_p2_ctl5_0       = 0xffff,
2877         .iophy_misc_pad_p3_ctl5_0       = 0xffff,
2878         .iophy_misc_pad_p4_ctl5_0       = 0xffff,
2879         .iophy_misc_pad_p2_ctl6_0       = 0xffff,
2880         .iophy_misc_pad_p3_ctl6_0       = 0xffff,
2881         .iophy_misc_pad_p4_ctl6_0       = 0xffff,
2882         .usb3_pad_mux_0                 = 0xffff,
2883         .iophy_pll_s0_ctl1_0            = 0xffff,
2884         .iophy_pll_s0_ctl2_0            = 0xffff,
2885         .iophy_pll_s0_ctl3_0            = 0xffff,
2886         .iophy_pll_s0_ctl4_0            = 0xffff,
2887         .iophy_misc_pad_s0_ctl1_0       = 0xffff,
2888         .iophy_misc_pad_s0_ctl2_0       = 0xffff,
2889         .iophy_misc_pad_s0_ctl3_0       = 0xffff,
2890         .iophy_misc_pad_s0_ctl4_0       = 0xffff,
2891         .iophy_misc_pad_s0_ctl5_0       = 0xffff,
2892         .iophy_misc_pad_s0_ctl6_0       = 0xffff,
2893 };
2894
2895 static struct tegra_xusb_padctl_regs t124_padregs_offset = {
2896         .boot_media_0                   = 0x0,
2897         .usb2_pad_mux_0                 = 0x4,
2898         .usb2_port_cap_0                = 0x8,
2899         .snps_oc_map_0                  = 0xc,
2900         .usb2_oc_map_0                  = 0x10,
2901         .ss_port_map_0                  = 0x14,
2902         .oc_det_0                       = 0x18,
2903         .elpg_program_0                 = 0x1c,
2904         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
2905         .usb2_bchrg_otgpad0_ctl1_0      = 0x24,
2906         .usb2_bchrg_otgpad1_ctl0_0      = 0x28,
2907         .usb2_bchrg_otgpad1_ctl1_0      = 0x2c,
2908         .usb2_bchrg_otgpad2_ctl0_0      = 0x30,
2909         .usb2_bchrg_otgpad2_ctl1_0      = 0x34,
2910         .usb2_bchrg_bias_pad_0          = 0x38,
2911         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
2912         .iophy_pll_p0_ctl1_0            = 0x40,
2913         .iophy_pll_p0_ctl2_0            = 0x44,
2914         .iophy_pll_p0_ctl3_0            = 0x48,
2915         .iophy_pll_p0_ctl4_0            = 0x4c,
2916         .iophy_usb3_pad0_ctl1_0         = 0x50,
2917         .iophy_usb3_pad1_ctl1_0         = 0x54,
2918         .iophy_usb3_pad0_ctl2_0         = 0x58,
2919         .iophy_usb3_pad1_ctl2_0         = 0x5c,
2920         .iophy_usb3_pad0_ctl3_0         = 0x60,
2921         .iophy_usb3_pad1_ctl3_0         = 0x64,
2922         .iophy_usb3_pad0_ctl4_0         = 0x68,
2923         .iophy_usb3_pad1_ctl4_0         = 0x6c,
2924         .iophy_misc_pad_p0_ctl1_0       = 0x70,
2925         .iophy_misc_pad_p1_ctl1_0       = 0x74,
2926         .iophy_misc_pad_p0_ctl2_0       = 0x78,
2927         .iophy_misc_pad_p1_ctl2_0       = 0x7c,
2928         .iophy_misc_pad_p0_ctl3_0       = 0x80,
2929         .iophy_misc_pad_p1_ctl3_0       = 0x84,
2930         .iophy_misc_pad_p0_ctl4_0       = 0x88,
2931         .iophy_misc_pad_p1_ctl4_0       = 0x8c,
2932         .iophy_misc_pad_p0_ctl5_0       = 0x90,
2933         .iophy_misc_pad_p1_ctl5_0       = 0x94,
2934         .iophy_misc_pad_p0_ctl6_0       = 0x98,
2935         .iophy_misc_pad_p1_ctl6_0       = 0x9c,
2936         .usb2_otg_pad0_ctl0_0           = 0xa0,
2937         .usb2_otg_pad1_ctl0_0           = 0xa4,
2938         .usb2_otg_pad2_ctl0_0           = 0xa8,
2939         .usb2_otg_pad0_ctl1_0           = 0xac,
2940         .usb2_otg_pad1_ctl1_0           = 0xb0,
2941         .usb2_otg_pad2_ctl1_0           = 0xb4,
2942         .usb2_bias_pad_ctl0_0           = 0xb8,
2943         .usb2_bias_pad_ctl1_0           = 0xbc,
2944         .usb2_hsic_pad0_ctl0_0          = 0xc0,
2945         .usb2_hsic_pad1_ctl0_0          = 0xc4,
2946         .usb2_hsic_pad0_ctl1_0          = 0xc8,
2947         .usb2_hsic_pad1_ctl1_0          = 0xcc,
2948         .usb2_hsic_pad0_ctl2_0          = 0xd0,
2949         .usb2_hsic_pad1_ctl2_0          = 0xd4,
2950         .ulpi_link_trim_ctl0            = 0xd8,
2951         .ulpi_null_clk_trim_ctl0        = 0xdc,
2952         .hsic_strb_trim_ctl0            = 0xe0,
2953         .wake_ctl0                      = 0xe4,
2954         .pm_spare0                      = 0xe8,
2955         .iophy_misc_pad_p2_ctl1_0       = 0xec,
2956         .iophy_misc_pad_p3_ctl1_0       = 0xf0,
2957         .iophy_misc_pad_p4_ctl1_0       = 0xf4,
2958         .iophy_misc_pad_p2_ctl2_0       = 0xf8,
2959         .iophy_misc_pad_p3_ctl2_0       = 0xfc,
2960         .iophy_misc_pad_p4_ctl2_0       = 0x100,
2961         .iophy_misc_pad_p2_ctl3_0       = 0x104,
2962         .iophy_misc_pad_p3_ctl3_0       = 0x108,
2963         .iophy_misc_pad_p4_ctl3_0       = 0x10c,
2964         .iophy_misc_pad_p2_ctl4_0       = 0x110,
2965         .iophy_misc_pad_p3_ctl4_0       = 0x114,
2966         .iophy_misc_pad_p4_ctl4_0       = 0x118,
2967         .iophy_misc_pad_p2_ctl5_0       = 0x11c,
2968         .iophy_misc_pad_p3_ctl5_0       = 0x120,
2969         .iophy_misc_pad_p4_ctl5_0       = 0x124,
2970         .iophy_misc_pad_p2_ctl6_0       = 0x128,
2971         .iophy_misc_pad_p3_ctl6_0       = 0x12c,
2972         .iophy_misc_pad_p4_ctl6_0       = 0x130,
2973         .usb3_pad_mux_0                 = 0x134,
2974         .iophy_pll_s0_ctl1_0            = 0x138,
2975         .iophy_pll_s0_ctl2_0            = 0x13c,
2976         .iophy_pll_s0_ctl3_0            = 0x140,
2977         .iophy_pll_s0_ctl4_0            = 0x144,
2978         .iophy_misc_pad_s0_ctl1_0       = 0x148,
2979         .iophy_misc_pad_s0_ctl2_0       = 0x14c,
2980         .iophy_misc_pad_s0_ctl3_0       = 0x150,
2981         .iophy_misc_pad_s0_ctl4_0       = 0x154,
2982         .iophy_misc_pad_s0_ctl5_0       = 0x158,
2983         .iophy_misc_pad_s0_ctl6_0       = 0x15c,
2984 };
2985
2986 /* TODO: we have to refine error handling in tegra_xhci_probe() */
2987 static int tegra_xhci_probe(struct platform_device *pdev)
2988 {
2989         const struct hc_driver *driver;
2990         struct xhci_hcd *xhci;
2991         struct tegra_xhci_hcd *tegra;
2992         struct resource *res;
2993         struct usb_hcd  *hcd;
2994         u32 pmc_reg, val;
2995         int ret;
2996         int irq;
2997
2998         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
2999
3000         if (usb_disabled())
3001                 return -ENODEV;
3002
3003         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
3004         if (!tegra) {
3005                 dev_err(&pdev->dev, "memory alloc failed\n");
3006                 return -ENOMEM;
3007         }
3008         tegra->pdev = pdev;
3009         tegra->pdata = dev_get_platdata(&pdev->dev);
3010         tegra->bdata = tegra->pdata->bdata;
3011
3012         ret = tegra_xhci_request_mem_region(pdev, "padctl",
3013                         &tegra->padctl_base);
3014         if (ret) {
3015                 dev_err(&pdev->dev, "failed to map padctl\n");
3016                 return ret;
3017         }
3018
3019         ret = tegra_xhci_request_mem_region(pdev, "fpci", &tegra->fpci_base);
3020         if (ret) {
3021                 dev_err(&pdev->dev, "failed to map fpci\n");
3022                 return ret;
3023         }
3024
3025         ret = tegra_xhci_request_mem_region(pdev, "ipfs", &tegra->ipfs_base);
3026         if (ret) {
3027                 dev_err(&pdev->dev, "failed to map ipfs\n");
3028                 return ret;
3029         }
3030
3031         ret = tegra_xusb_partitions_clk_init(tegra);
3032         if (ret) {
3033                 dev_err(&pdev->dev,
3034                         "failed to initialize xusb partitions clocks\n");
3035                 return ret;
3036         }
3037
3038         /* Enable power rails to the PAD,VBUS
3039          * and pull-up voltage.Initialize the regulators
3040          */
3041         ret = tegra_xusb_regulator_init(tegra, pdev);
3042         if (ret) {
3043                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
3044                 goto err_deinit_xusb_partition_clk;
3045         }
3046
3047         /* Enable UTMIP, PLLU and PLLE */
3048         ret = tegra_usb2_clocks_init(tegra);
3049         if (ret) {
3050                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
3051                 goto err_deinit_tegra_xusb_regulator;
3052         }
3053
3054         /* tegra_unpowergate_partition also does partition reset deassert */
3055         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
3056         if (ret)
3057                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
3058
3059         /* tegra_unpowergate_partition also does partition reset deassert */
3060         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3061         if (ret)
3062                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
3063
3064         /* reset the pointer back to NULL. driver uses it */
3065         /* platform_set_drvdata(pdev, NULL); */
3066
3067         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "host");
3068         if (!res) {
3069                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
3070                 ret = -ENODEV;
3071                 goto err_deinit_usb2_clocks;
3072         }
3073         tegra->host_phy_base = res->start;
3074
3075         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
3076                                 res->start, resource_size(res));
3077         if (!tegra->host_phy_virt_base) {
3078                 dev_err(&pdev->dev, "error mapping host phy memory\n");
3079                 ret = -ENOMEM;
3080                 goto err_deinit_usb2_clocks;
3081         }
3082
3083         /* Setup IPFS access and BAR0 space */
3084         tegra_xhci_cfg(tegra);
3085
3086         val = readl(tegra->fpci_base + XUSB_CFG_0);
3087         tegra->device_id = (val >> 16) & 0xffff;
3088
3089         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
3090                 (XUSB_DEVICE_ID_T114 == tegra->device_id) ? "T114" : "T124+");
3091
3092         if (XUSB_DEVICE_ID_T114 == tegra->device_id) {
3093                 tegra->padregs = &t114_padregs_offset;
3094         } else if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
3095                 tegra->padregs = &t124_padregs_offset;
3096         } else {
3097                 dev_info(&pdev->dev, "XUSB device_id neither T114 nor T124!\n");
3098                 dev_info(&pdev->dev, "XUSB using T124 pad register offsets!\n");
3099                 tegra->padregs = &t124_padregs_offset;
3100         }
3101
3102         /* calculate rctrl_val and tctrl_val once at boot time */
3103         tegra_xhci_war_for_tctrl_rctrl(tegra);
3104
3105         /* Program the XUSB pads to take ownership of ports */
3106         tegra_xhci_padctl_portmap_and_caps(tegra);
3107
3108         /* Release XUSB wake logic state latching */
3109         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
3110         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
3111
3112         /* Deassert reset to XUSB host, ss, dev clocks */
3113         tegra_periph_reset_deassert(tegra->host_clk);
3114         tegra_periph_reset_deassert(tegra->ss_clk);
3115
3116         ret = init_firmware(tegra);
3117         if (ret < 0) {
3118                 dev_err(&pdev->dev, "failed to init firmware\n");
3119                 ret = -ENODEV;
3120                 goto err_deinit_usb2_clocks;
3121         }
3122
3123         ret = load_firmware(tegra, true /* do reset ARU */);
3124         if (ret < 0) {
3125                 dev_err(&pdev->dev, "failed to load firmware\n");
3126                 ret = -ENODEV;
3127                 goto err_deinit_firmware;
3128         }
3129
3130         device_init_wakeup(&pdev->dev, 1);
3131         driver = &tegra_plat_xhci_driver;
3132
3133         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
3134         if (!hcd) {
3135                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
3136                 ret = -ENOMEM;
3137                 goto err_deinit_firmware;
3138         }
3139
3140         ret = tegra_xhci_request_mem_region(pdev, "host", &hcd->regs);
3141         if (ret) {
3142                 dev_err(&pdev->dev, "failed to map host\n");
3143                 goto err_put_usb2_hcd;
3144         }
3145         hcd->rsrc_start = res->start;
3146         hcd->rsrc_len = resource_size(res);
3147
3148         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "host");
3149         if (!res) {
3150                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
3151                 ret = -ENODEV;
3152                 goto err_put_usb2_hcd;
3153         }
3154         irq = res->start;
3155         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
3156         if (ret) {
3157                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
3158                 goto err_put_usb2_hcd;
3159         }
3160
3161         /* USB 2.0 roothub is stored in the platform_device now. */
3162         hcd = dev_get_drvdata(&pdev->dev);
3163         xhci = hcd_to_xhci(hcd);
3164         tegra->xhci = xhci;
3165         platform_set_drvdata(pdev, tegra);
3166
3167         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
3168                                                 dev_name(&pdev->dev), hcd);
3169         if (!xhci->shared_hcd) {
3170                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
3171                 ret = -ENOMEM;
3172                 goto err_remove_usb2_hcd;
3173         }
3174
3175         /*
3176          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
3177          * is called by usb_add_hcd().
3178          */
3179         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
3180
3181         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
3182         if (ret) {
3183                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
3184                 goto err_put_usb3_hcd;
3185         }
3186
3187         device_init_wakeup(&hcd->self.root_hub->dev, 1);
3188         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
3189         spin_lock_init(&tegra->lock);
3190         mutex_init(&tegra->sync_lock);
3191         mutex_init(&tegra->mbox_lock);
3192
3193         /* do mailbox related initializations */
3194         tegra->mbox_owner = 0xffff;
3195         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
3196
3197         tegra_xhci_enable_fw_message(tegra);
3198
3199         /* do ss partition elpg exit related initialization */
3200         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
3201
3202         /* do host partition elpg exit related initialization */
3203         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
3204
3205         /* Register interrupt handler for SMI line to handle mailbox
3206          * interrupt from firmware
3207          */
3208         ret = tegra_xhci_request_irq(pdev, "host-smi", tegra_xhci_smi_irq,
3209                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
3210         if (ret != 0)
3211                 goto err_remove_usb3_hcd;
3212
3213         /* Register interrupt handler for PADCTRL line to
3214          * handle wake on connect irqs interrupt from
3215          * firmware
3216          */
3217         ret = tegra_xhci_request_irq(pdev, "padctl", tegra_xhci_padctl_irq,
3218                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
3219                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
3220         if (ret != 0)
3221                 goto err_remove_usb3_hcd;
3222
3223         ret = tegra_xhci_request_irq(pdev, "usb3", tegra_xhci_xusb_host_irq,
3224                         IRQF_SHARED | IRQF_TRIGGER_HIGH, "xusb_host_irq",
3225                         &tegra->usb3_irq);
3226         if (ret != 0)
3227                 goto err_remove_usb3_hcd;
3228
3229         tegra->ss_pwr_gated = false;
3230         tegra->host_pwr_gated = false;
3231         tegra->hc_in_elpg = false;
3232         tegra->hs_wake_event = false;
3233         tegra->host_resume_req = false;
3234         tegra->lp0_exit = false;
3235         tegra->dfe_ctle_ctx_saved = false;
3236
3237         /* reset wake event to NONE */
3238         pmc_reg = tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0);
3239         pmc_reg |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE);
3240         pmc_reg |= UTMIP_WAKE_VAL(1, WAKE_VAL_NONE);
3241         pmc_reg |= UTMIP_WAKE_VAL(2, WAKE_VAL_NONE);
3242         pmc_reg |= UTMIP_WAKE_VAL(3, WAKE_VAL_NONE);
3243         tegra_usb_pmc_reg_write(PMC_UTMIP_UHSIC_SLEEP_CFG_0, pmc_reg);
3244
3245         tegra_xhci_debug_read_pads(tegra);
3246         utmi_phy_pad_enable();
3247         utmi_phy_iddq_override(false);
3248
3249         tegra_pd_add_device(&pdev->dev);
3250
3251         return 0;
3252
3253 err_remove_usb3_hcd:
3254         usb_remove_hcd(xhci->shared_hcd);
3255 err_put_usb3_hcd:
3256         usb_put_hcd(xhci->shared_hcd);
3257 err_remove_usb2_hcd:
3258         kfree(tegra->xhci);
3259         usb_remove_hcd(hcd);
3260 err_put_usb2_hcd:
3261         usb_put_hcd(hcd);
3262 err_deinit_firmware:
3263         deinit_firmware(tegra);
3264 err_deinit_usb2_clocks:
3265         tegra_usb2_clocks_deinit(tegra);
3266 err_deinit_tegra_xusb_regulator:
3267         tegra_xusb_regulator_deinit(tegra);
3268 err_deinit_xusb_partition_clk:
3269         tegra_xusb_partitions_clk_deinit(tegra);
3270
3271         return ret;
3272 }
3273
3274 static int tegra_xhci_remove(struct platform_device *pdev)
3275 {
3276         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3277         struct xhci_hcd *xhci = NULL;
3278         struct usb_hcd *hcd = NULL;
3279
3280         if (tegra == NULL)
3281                 return -EINVAL;
3282
3283         xhci = tegra->xhci;
3284         hcd = xhci_to_hcd(xhci);
3285
3286         devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
3287         devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
3288         devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
3289         usb_remove_hcd(xhci->shared_hcd);
3290         usb_put_hcd(xhci->shared_hcd);
3291         usb_remove_hcd(hcd);
3292         usb_put_hcd(hcd);
3293         kfree(xhci);
3294
3295         deinit_firmware(tegra);
3296         tegra_xusb_regulator_deinit(tegra);
3297         tegra_usb2_clocks_deinit(tegra);
3298         if (!tegra->hc_in_elpg)
3299                 tegra_xusb_partitions_clk_deinit(tegra);
3300         utmi_phy_pad_disable();
3301         utmi_phy_iddq_override(true);
3302
3303         return 0;
3304 }
3305
3306 static void tegra_xhci_shutdown(struct platform_device *pdev)
3307 {
3308         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3309         struct xhci_hcd *xhci = NULL;
3310         struct usb_hcd *hcd = NULL;
3311
3312         if (tegra == NULL)
3313                 return;
3314
3315         if (tegra->hc_in_elpg) {
3316                 mutex_lock(&tegra->sync_lock);
3317                 tegra_xhci_host_partition_elpg_exit(tegra);
3318                 mutex_unlock(&tegra->sync_lock);
3319         }
3320         xhci = tegra->xhci;
3321         hcd = xhci_to_hcd(xhci);
3322         xhci_shutdown(hcd);
3323 }
3324
3325 static struct platform_driver tegra_xhci_driver = {
3326         .probe  = tegra_xhci_probe,
3327         .remove = tegra_xhci_remove,
3328         .shutdown = tegra_xhci_shutdown,
3329 #ifdef CONFIG_PM
3330         .suspend = tegra_xhci_suspend,
3331         .resume  = tegra_xhci_resume,
3332 #endif
3333         .driver = {
3334                 .name = "tegra-xhci",
3335         },
3336 };
3337 MODULE_ALIAS("platform:tegra-xhci");
3338
3339 int tegra_xhci_register_plat(void)
3340 {
3341         return platform_driver_register(&tegra_xhci_driver);
3342 }
3343
3344 void tegra_xhci_unregister_plat(void)
3345 {
3346         platform_driver_unregister(&tegra_xhci_driver);
3347 }