xhci: tegra: Support HSIC device power on/off
[linux-3.10.git] / drivers / usb / host / xhci-tegra.c
1 /*
2  * xhci-tegra.c - Nvidia xHCI host controller driver
3  *
4  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/clk.h>
24 #include <linux/ioport.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irq.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/uaccess.h>
30 #include <linux/circ_buf.h>
31 #include <linux/vmalloc.h>
32 #include <linux/debugfs.h>
33 #include <linux/kthread.h>
34 #include <linux/gpio.h>
35 #include <linux/usb/otg.h>
36 #include <linux/clk/tegra.h>
37 #include <linux/tegra-powergate.h>
38 #include <linux/firmware.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/of.h>
41 #include <linux/of_device.h>
42 #include <linux/of_gpio.h>
43 #include <linux/tegra-fuse.h>
44
45 #include <mach/tegra_usb_pad_ctrl.h>
46 #include <mach/tegra_usb_pmc.h>
47 #include <mach/pm_domains.h>
48 #include <mach/mc.h>
49 #include <mach/xusb.h>
50
51 #include "xhci-tegra.h"
52 #include "xhci.h"
53 #include "../../../arch/arm/mach-tegra/iomap.h"
54
55 /* macros */
56 #define FW_IOCTL_LOG_DEQUEUE_LOW        (4)
57 #define FW_IOCTL_LOG_DEQUEUE_HIGH       (5)
58 #define FW_IOCTL_DATA_SHIFT             (0)
59 #define FW_IOCTL_DATA_MASK              (0x00ffffff)
60 #define FW_IOCTL_TYPE_SHIFT             (24)
61 #define FW_IOCTL_TYPE_MASK              (0xff000000)
62 #define FW_LOG_SIZE                     (sizeof(struct log_entry))
63 #define FW_LOG_COUNT                    (4096)
64 #define FW_LOG_RING_SIZE                (FW_LOG_SIZE * FW_LOG_COUNT)
65 #define FW_LOG_PAYLOAD_SIZE             (27)
66 #define DRIVER                          (0x01)
67 #define CIRC_BUF_SIZE                   (4 * (1 << 20)) /* 4MB */
68 #define FW_LOG_THREAD_RELAX             (msecs_to_jiffies(100))
69
70 /* tegra_xhci_firmware_log.flags bits */
71 #define FW_LOG_CONTEXT_VALID            (0)
72 #define FW_LOG_FILE_OPENED              (1)
73
74 #define PAGE_SELECT_MASK                        0xFFFFFE00
75 #define PAGE_SELECT_SHIFT                       9
76 #define PAGE_OFFSET_MASK                        0x000001FF
77 #define CSB_PAGE_SELECT(_addr)                                          \
78         ({                                                              \
79                 typecheck(u32, _addr);                                  \
80                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
81         })
82 #define CSB_PAGE_OFFSET(_addr)                                          \
83         ({                                                              \
84                 typecheck(u32, _addr);                                  \
85                 (_addr & PAGE_OFFSET_MASK);                             \
86         })
87
88 #define reg_dump(_dev, _base, _reg)                                     \
89         dev_dbg(_dev, "%s: %s @%x = 0x%x\n", __func__, #_reg,           \
90                 _reg, readl(_base + _reg))
91
92 #define PMC_PORTMAP_MASK(map, pad)      (((map) >> 4*(pad)) & 0xF)
93
94 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
95 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
96 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
97
98 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
99
100 /* private data types */
101 /* command requests from the firmware */
102 enum MBOX_CMD_TYPE {
103         MBOX_CMD_MSG_ENABLED = 1,
104         MBOX_CMD_INC_FALC_CLOCK,
105         MBOX_CMD_DEC_FALC_CLOCK,
106         MBOX_CMD_INC_SSPI_CLOCK,
107         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
108         MBOX_CMD_SET_BW,
109         MBOX_CMD_SET_SS_PWR_GATING,
110         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
111         MBOX_CMD_SAVE_DFE_CTLE_CTX,
112         MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
113         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* 11, unused */
114         MBOX_CMD_STAR_HSIC_IDLE,
115         MBOX_CMD_STOP_HSIC_IDLE,
116         MBOX_CMD_DBC_WAKE_STACK, /* unused */
117         MBOX_CMD_HSIC_PRETEND_CONNECT,
118
119         /* needs to be the last cmd */
120         MBOX_CMD_MAX,
121
122         /* resp msg to ack above commands */
123         MBOX_CMD_ACK = 128,
124         MBOX_CMD_NACK
125 };
126
127 struct log_entry {
128         u32 sequence_no;
129         u8 data[FW_LOG_PAYLOAD_SIZE];
130         u8 owner;
131 };
132
133 /* Usb3 Firmware Cfg Table */
134 struct cfgtbl {
135         u32 boot_loadaddr_in_imem;
136         u32 boot_codedfi_offset;
137         u32 boot_codetag;
138         u32 boot_codesize;
139
140         /* Physical memory reserved by Bootloader/BIOS */
141         u32 phys_memaddr;
142         u16 reqphys_memsize;
143         u16 alloc_phys_memsize;
144
145         /* .rodata section */
146         u32 rodata_img_offset;
147         u32 rodata_section_start;
148         u32 rodata_section_end;
149         u32 main_fnaddr;
150
151         u32 fwimg_cksum;
152         u32 fwimg_created_time;
153
154         /* Fields that get filled by linker during linking phase
155          * or initialized in the FW code.
156          */
157         u32 imem_resident_start;
158         u32 imem_resident_end;
159         u32 idirect_start;
160         u32 idirect_end;
161         u32 l2_imem_start;
162         u32 l2_imem_end;
163         u32 version_id;
164         u8 init_ddirect;
165         u8 reserved[3];
166         u32 phys_addr_log_buffer;
167         u32 total_log_entries;
168         u32 dequeue_ptr;
169
170         /*      Below two dummy variables are used to replace
171          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
172          *      retain the size of struct _CFG_TBL used by other AP/Module.
173          */
174         u32 dummy_var1;
175         u32 dummy_var2;
176
177         /* fwimg_len */
178         u32 fwimg_len;
179         u8 magic[8];
180         u32 SS_low_power_entry_timeout;
181         u8 num_hsic_port;
182         u8 padding[139]; /* padding bytes to makeup 256-bytes cfgtbl */
183 };
184
185 struct xusb_save_regs {
186         u32 msi_bar_sz;
187         u32 msi_axi_barst;
188         u32 msi_fpci_barst;
189         u32 msi_vec0;
190         u32 msi_en_vec0;
191         u32 fpci_error_masks;
192         u32 intr_mask;
193         u32 ipfs_intr_enable;
194         u32 ufpci_config;
195         u32 clkgate_hysteresis;
196         u32 xusb_host_mccif_fifo_cntrl;
197
198         /* PG does not mention below */
199         u32 hs_pls;
200         u32 fs_pls;
201         u32 hs_fs_speed;
202         u32 hs_fs_pp;
203         u32 cfg_aru;
204         u32 cfg_order;
205         u32 cfg_fladj;
206         u32 cfg_sid;
207         /* DFE and CTLE */
208         u32 tap1_val[XUSB_SS_PORT_COUNT];
209         u32 amp_val[XUSB_SS_PORT_COUNT];
210         u32 ctle_z_val[XUSB_SS_PORT_COUNT];
211         u32 ctle_g_val[XUSB_SS_PORT_COUNT];
212 };
213
214 struct tegra_xhci_firmware {
215         void *data; /* kernel virtual address */
216         size_t size; /* firmware size */
217         dma_addr_t dma; /* dma address for controller */
218 };
219
220 struct tegra_xhci_firmware_log {
221         dma_addr_t phys_addr;           /* dma-able address */
222         void *virt_addr;                /* kernel va of the shared log buffer */
223         struct log_entry *dequeue;      /* current dequeue pointer (va) */
224         struct circ_buf circ;           /* big circular buffer */
225         u32 seq;                        /* log sequence number */
226
227         struct task_struct *thread;     /* a thread to consume log */
228         struct mutex mutex;
229         wait_queue_head_t read_wait;
230         wait_queue_head_t write_wait;
231         wait_queue_head_t intr_wait;
232         struct dentry *path;
233         struct dentry *log_file;
234         unsigned long flags;
235 };
236
237 /* structure to hold the offsets of padctl registers */
238 struct tegra_xusb_padctl_regs {
239         u16 boot_media_0;
240         u16 usb2_pad_mux_0;
241         u16 usb2_port_cap_0;
242         u16 snps_oc_map_0;
243         u16 usb2_oc_map_0;
244         u16 ss_port_map_0;
245         u16 oc_det_0;
246         u16 elpg_program_0;
247         u16 usb2_bchrg_otgpad0_ctl0_0;
248         u16 usb2_bchrg_otgpad0_ctl1_0;
249         u16 usb2_bchrg_otgpad1_ctl0_0;
250         u16 usb2_bchrg_otgpad1_ctl1_0;
251         u16 usb2_bchrg_otgpad2_ctl0_0;
252         u16 usb2_bchrg_otgpad2_ctl1_0;
253         u16 usb2_bchrg_bias_pad_0;
254         u16 usb2_bchrg_tdcd_dbnc_timer_0;
255         u16 iophy_pll_p0_ctl1_0;
256         u16 iophy_pll_p0_ctl2_0;
257         u16 iophy_pll_p0_ctl3_0;
258         u16 iophy_pll_p0_ctl4_0;
259         u16 iophy_usb3_pad0_ctl1_0;
260         u16 iophy_usb3_pad1_ctl1_0;
261         u16 iophy_usb3_pad0_ctl2_0;
262         u16 iophy_usb3_pad1_ctl2_0;
263         u16 iophy_usb3_pad0_ctl3_0;
264         u16 iophy_usb3_pad1_ctl3_0;
265         u16 iophy_usb3_pad0_ctl4_0;
266         u16 iophy_usb3_pad1_ctl4_0;
267         u16 iophy_misc_pad_p0_ctl1_0;
268         u16 iophy_misc_pad_p1_ctl1_0;
269         u16 iophy_misc_pad_p0_ctl2_0;
270         u16 iophy_misc_pad_p1_ctl2_0;
271         u16 iophy_misc_pad_p0_ctl3_0;
272         u16 iophy_misc_pad_p1_ctl3_0;
273         u16 iophy_misc_pad_p0_ctl4_0;
274         u16 iophy_misc_pad_p1_ctl4_0;
275         u16 iophy_misc_pad_p0_ctl5_0;
276         u16 iophy_misc_pad_p1_ctl5_0;
277         u16 iophy_misc_pad_p0_ctl6_0;
278         u16 iophy_misc_pad_p1_ctl6_0;
279         u16 usb2_otg_pad0_ctl0_0;
280         u16 usb2_otg_pad1_ctl0_0;
281         u16 usb2_otg_pad2_ctl0_0;
282         u16 usb2_otg_pad0_ctl1_0;
283         u16 usb2_otg_pad1_ctl1_0;
284         u16 usb2_otg_pad2_ctl1_0;
285         u16 usb2_bias_pad_ctl0_0;
286         u16 usb2_bias_pad_ctl1_0;
287         u16 usb2_hsic_pad0_ctl0_0;
288         u16 usb2_hsic_pad1_ctl0_0;
289         u16 usb2_hsic_pad0_ctl1_0;
290         u16 usb2_hsic_pad1_ctl1_0;
291         u16 usb2_hsic_pad0_ctl2_0;
292         u16 usb2_hsic_pad1_ctl2_0;
293         u16 ulpi_link_trim_ctl0;
294         u16 ulpi_null_clk_trim_ctl0;
295         u16 hsic_strb_trim_ctl0;
296         u16 wake_ctl0;
297         u16 pm_spare0;
298         u16 iophy_misc_pad_p2_ctl1_0;
299         u16 iophy_misc_pad_p3_ctl1_0;
300         u16 iophy_misc_pad_p4_ctl1_0;
301         u16 iophy_misc_pad_p2_ctl2_0;
302         u16 iophy_misc_pad_p3_ctl2_0;
303         u16 iophy_misc_pad_p4_ctl2_0;
304         u16 iophy_misc_pad_p2_ctl3_0;
305         u16 iophy_misc_pad_p3_ctl3_0;
306         u16 iophy_misc_pad_p4_ctl3_0;
307         u16 iophy_misc_pad_p2_ctl4_0;
308         u16 iophy_misc_pad_p3_ctl4_0;
309         u16 iophy_misc_pad_p4_ctl4_0;
310         u16 iophy_misc_pad_p2_ctl5_0;
311         u16 iophy_misc_pad_p3_ctl5_0;
312         u16 iophy_misc_pad_p4_ctl5_0;
313         u16 iophy_misc_pad_p2_ctl6_0;
314         u16 iophy_misc_pad_p3_ctl6_0;
315         u16 iophy_misc_pad_p4_ctl6_0;
316         u16 usb3_pad_mux_0;
317         u16 iophy_pll_s0_ctl1_0;
318         u16 iophy_pll_s0_ctl2_0;
319         u16 iophy_pll_s0_ctl3_0;
320         u16 iophy_pll_s0_ctl4_0;
321         u16 iophy_misc_pad_s0_ctl1_0;
322         u16 iophy_misc_pad_s0_ctl2_0;
323         u16 iophy_misc_pad_s0_ctl3_0;
324         u16 iophy_misc_pad_s0_ctl4_0;
325         u16 iophy_misc_pad_s0_ctl5_0;
326         u16 iophy_misc_pad_s0_ctl6_0;
327 };
328
329 struct tegra_xhci_hcd {
330         struct platform_device *pdev;
331         struct xhci_hcd *xhci;
332         u16 device_id;
333
334         spinlock_t lock;
335         struct mutex sync_lock;
336
337         int smi_irq;
338         int padctl_irq;
339         int usb3_irq;
340         int usb2_irq;
341
342         bool ss_wake_event;
343         bool ss_pwr_gated;
344         bool host_pwr_gated;
345         bool hs_wake_event;
346         bool host_resume_req;
347         bool lp0_exit;
348         bool dfe_ctx_saved[XUSB_SS_PORT_COUNT];
349         bool ctle_ctx_saved[XUSB_SS_PORT_COUNT];
350         unsigned long last_jiffies;
351         unsigned long host_phy_base;
352         unsigned long host_phy_size;
353         void __iomem *host_phy_virt_base;
354
355         void __iomem *padctl_base;
356         void __iomem *fpci_base;
357         void __iomem *ipfs_base;
358
359         struct tegra_xusb_platform_data *pdata;
360         struct tegra_xusb_board_data *bdata;
361         struct tegra_xusb_chip_calib *cdata;
362         struct tegra_xusb_padctl_regs *padregs;
363         const struct tegra_xusb_soc_config *soc_config;
364         u64 tegra_xusb_dmamask;
365
366         /* mailbox variables */
367         struct mutex mbox_lock;
368         u32 mbox_owner;
369         u32 cmd_type;
370         u32 cmd_data;
371
372         struct regulator *xusb_utmi_vbus_regs[XUSB_UTMI_COUNT];
373
374         struct regulator *xusb_s1p05v_reg;
375         struct regulator *xusb_s3p3v_reg;
376         struct regulator *xusb_s1p8v_reg;
377         struct regulator *vddio_hsic_reg;
378         int vddio_hsic_refcnt;
379
380         struct work_struct mbox_work;
381         struct work_struct ss_elpg_exit_work;
382         struct work_struct host_elpg_exit_work;
383
384         struct clk *host_clk;
385         struct clk *ss_clk;
386
387         /* XUSB Falcon SuperSpeed Clock */
388         struct clk *falc_clk;
389
390         /* EMC Clock */
391         struct clk *emc_clk;
392         /* XUSB SS PI Clock */
393         struct clk *ss_src_clk;
394         /* PLLE Clock */
395         struct clk *plle_clk;
396         struct clk *pll_u_480M;
397         struct clk *clk_m;
398         /* refPLLE clk */
399         struct clk *pll_re_vco_clk;
400         /*
401          * XUSB/IPFS specific registers these need to be saved/restored in
402          * addition to spec defined registers
403          */
404         struct xusb_save_regs sregs;
405         bool usb2_rh_suspend;
406         bool usb3_rh_suspend;
407         bool hc_in_elpg;
408
409         /* otg transceiver */
410         struct usb_phy *transceiver;
411         struct notifier_block otgnb;
412
413         unsigned long usb2_rh_remote_wakeup_ports; /* one bit per port */
414         unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
415         /* firmware loading related */
416         struct tegra_xhci_firmware firmware;
417
418         struct tegra_xhci_firmware_log log;
419         struct device_attribute hsic_power_attr[XUSB_HSIC_COUNT];
420
421         bool init_done;
422 };
423
424 static int tegra_xhci_probe2(struct tegra_xhci_hcd *tegra);
425 static int tegra_xhci_remove(struct platform_device *pdev);
426 static void init_filesystem_firmware_done(const struct firmware *fw,
427                                         void *context);
428
429 static struct tegra_usb_pmc_data pmc_data[XUSB_UTMI_COUNT];
430 static struct tegra_usb_pmc_data pmc_hsic_data[XUSB_HSIC_COUNT];
431 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
432         u8 port)  __attribute__ ((unused));
433
434 #define FIRMWARE_FILE "tegra_xusb_firmware"
435 static char *firmware_file = FIRMWARE_FILE;
436 #define FIRMWARE_FILE_HELP      \
437         "used to specify firmware file of Tegra XHCI host controller. "\
438         "Default value is \"" FIRMWARE_FILE "\"."
439
440 module_param(firmware_file, charp, S_IRUGO);
441 MODULE_PARM_DESC(firmware_file, FIRMWARE_FILE_HELP);
442
443 /* functions */
444 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
445 {
446         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
447 }
448
449 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
450 {
451 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
452         WARN_ON(tegra->sync_lock.owner != current);
453 #endif
454 }
455
456 #define for_each_enabled_hsic_pad(_pad, _tegra_xhci_hcd)                \
457         for (_pad = find_next_enabled_hsic_pad(_tegra_xhci_hcd, 0);     \
458             (_pad < XUSB_HSIC_COUNT) && (_pad >= 0);                    \
459             _pad = find_next_enabled_hsic_pad(_tegra_xhci_hcd, _pad + 1))
460
461 static inline int find_next_enabled_pad(struct tegra_xhci_hcd *tegra,
462                                                 int start, int last)
463 {
464         unsigned long portmap = tegra->bdata->portmap;
465         return find_next_bit(&portmap, last , start);
466 }
467
468 static inline int find_next_enabled_hsic_pad(struct tegra_xhci_hcd *tegra,
469                                                 int curr_pad)
470 {
471         int start = XUSB_HSIC_INDEX + curr_pad;
472         int last = XUSB_HSIC_INDEX + XUSB_HSIC_COUNT;
473
474         if ((curr_pad < 0) || (curr_pad >= XUSB_HSIC_COUNT))
475                 return -1;
476
477         return find_next_enabled_pad(tegra, start, last) - XUSB_HSIC_INDEX;
478 }
479
480 static void tegra_xhci_setup_gpio_for_ss_lane(struct tegra_xhci_hcd *tegra)
481 {
482         int err = 0;
483
484         if (!tegra->bdata->gpio_controls_muxed_ss_lanes)
485                 return;
486
487         if (tegra->bdata->lane_owner & BIT(0)) {
488                 /* USB3_SS port1 is using SATA lane so set (MUX_SATA)
489                  * GPIO P11 to '0'
490                  */
491                 err = gpio_request((tegra->bdata->gpio_ss1_sata & 0xffff),
492                         "gpio_ss1_sata");
493                 if (err < 0)
494                         pr_err("%s: gpio_ss1_sata gpio_request failed %d\n",
495                                 __func__, err);
496                 err = gpio_direction_output((tegra->bdata->gpio_ss1_sata
497                         & 0xffff), 1);
498                 if (err < 0)
499                         pr_err("%s: gpio_ss1_sata gpio_direction failed %d\n",
500                                 __func__, err);
501                 __gpio_set_value((tegra->bdata->gpio_ss1_sata & 0xffff),
502                                 ((tegra->bdata->gpio_ss1_sata >> 16)));
503         }
504 }
505
506 static u32 xhci_read_portsc(struct xhci_hcd *xhci, unsigned int port)
507 {
508         int num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
509         __le32 __iomem *addr;
510
511         if (port >= num_ports) {
512                 xhci_err(xhci, "%s invalid port %u\n", __func__, port);
513                 return -1;
514         }
515
516         addr = &xhci->op_regs->port_status_base + (NUM_PORT_REGS * port);
517         return xhci_readl(xhci, addr);
518 }
519
520 static void debug_print_portsc(struct xhci_hcd *xhci)
521 {
522         __le32 __iomem *addr = &xhci->op_regs->port_status_base;
523         u32 reg;
524         int i;
525         int ports;
526
527         ports = HCS_MAX_PORTS(xhci->hcs_params1);
528         for (i = 0; i < ports; i++) {
529                 reg = xhci_read_portsc(xhci, i);
530                 xhci_dbg(xhci, "@%p port %d status reg = 0x%x\n",
531                                 addr, i, (unsigned int) reg);
532                 addr += NUM_PORT_REGS;
533         }
534 }
535 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra);
536
537 static bool is_otg_host(struct tegra_xhci_hcd *tegra)
538 {
539         if (!tegra->transceiver)
540                 return true;
541         else if (tegra->transceiver->state == OTG_STATE_A_HOST)
542                 return true;
543         else
544                 return false;
545 }
546
547 static int update_speed(struct tegra_xhci_hcd *tegra, u8 port)
548 {
549         struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
550         u32 portsc;
551
552         portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port));
553         if (DEV_FULLSPEED(portsc))
554                 return USB_PMC_PORT_SPEED_FULL;
555         else if (DEV_HIGHSPEED(portsc))
556                 return USB_PMC_PORT_SPEED_HIGH;
557         else if (DEV_LOWSPEED(portsc))
558                 return USB_PMC_PORT_SPEED_LOW;
559         else if (DEV_SUPERSPEED(portsc))
560                 return USB_PMC_PORT_SPEED_SUPER;
561         else
562                 return USB_PMC_PORT_SPEED_UNKNOWN;
563 }
564
565 static void pmc_init(struct tegra_xhci_hcd *tegra)
566 {
567         struct tegra_usb_pmc_data *pmc;
568         struct device *dev = &tegra->pdev->dev;
569         int pad;
570
571         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
572                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
573                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
574                         pmc = &pmc_data[pad];
575                         if (tegra->soc_config->pmc_portmap)
576                                 pmc->instance = PMC_PORTMAP_MASK(
577                                                 tegra->soc_config->pmc_portmap,
578                                                 pad);
579                         else
580                                 pmc->instance = pad;
581                         pmc->phy_type = TEGRA_USB_PHY_INTF_UTMI;
582                         pmc->port_speed = USB_PMC_PORT_SPEED_UNKNOWN;
583                         pmc->controller_type = TEGRA_USB_3_0;
584                         tegra_usb_pmc_init(pmc);
585                 }
586         }
587
588         for_each_enabled_hsic_pad(pad, tegra) {
589                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
590                 pmc = &pmc_hsic_data[pad];
591                 pmc->instance = pad + 1;
592                 pmc->phy_type = TEGRA_USB_PHY_INTF_HSIC;
593                 pmc->port_speed = USB_PMC_PORT_SPEED_HIGH;
594                 pmc->controller_type = TEGRA_USB_3_0;
595                 tegra_usb_pmc_init(pmc);
596         }
597 }
598
599 static void pmc_setup_wake_detect(struct tegra_xhci_hcd *tegra)
600 {
601         struct tegra_usb_pmc_data *pmc;
602         struct device *dev = &tegra->pdev->dev;
603         u32 portsc;
604         int port;
605         int pad;
606
607         for_each_enabled_hsic_pad(pad, tegra) {
608                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
609
610                 pmc = &pmc_hsic_data[pad];
611                 port = hsic_pad_to_port(pad);
612                 portsc = xhci_read_portsc(tegra->xhci, port);
613                 dev_dbg(dev, "%s hsic pad %d portsc 0x%x\n",
614                         __func__, pad, portsc);
615
616                 if (((int) portsc != -1) && (portsc & PORT_CONNECT))
617                         pmc->pmc_ops->setup_pmc_wake_detect(pmc);
618         }
619
620         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
621                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
622                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
623                         pmc = &pmc_data[pad];
624                         pmc->port_speed = update_speed(tegra, pad);
625                         if (pad == 0) {
626                                 if (is_otg_host(tegra))
627                                         pmc->pmc_ops->setup_pmc_wake_detect(
628                                                                         pmc);
629                         } else
630                                 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
631                 }
632         }
633 }
634
635 static void pmc_disable_bus_ctrl(struct tegra_xhci_hcd *tegra)
636 {
637         struct tegra_usb_pmc_data *pmc;
638         struct device *dev = &tegra->pdev->dev;
639         int pad;
640
641         for_each_enabled_hsic_pad(pad, tegra) {
642                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
643
644                 pmc = &pmc_hsic_data[pad];
645                 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
646         }
647
648         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
649                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
650                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
651                         pmc = &pmc_data[pad];
652                         pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
653                 }
654         }
655 }
656
657 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
658 {
659         void __iomem *fpci_base = tegra->fpci_base;
660         struct platform_device *pdev = tegra->pdev;
661         u32 input_addr;
662         u32 data;
663         u32 csb_page_select;
664
665         /* to select the appropriate CSB page to write to */
666         csb_page_select = CSB_PAGE_SELECT(addr);
667
668         dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
669                         csb_page_select);
670
671         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
672
673         /* selects the appropriate offset in the page to read from */
674         input_addr = CSB_PAGE_OFFSET(addr);
675         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
676
677         dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
678                         input_addr, data);
679         return data;
680 }
681
682 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
683 {
684         void __iomem *fpci_base = tegra->fpci_base;
685         struct platform_device *pdev = tegra->pdev;
686         u32 input_addr;
687         u32 csb_page_select;
688
689         /* to select the appropriate CSB page to write to */
690         csb_page_select = CSB_PAGE_SELECT(addr);
691
692         dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
693                         csb_page_select);
694
695         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
696
697         /* selects the appropriate offset in the page to write to */
698         input_addr = CSB_PAGE_OFFSET(addr);
699         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
700
701         dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
702                         input_addr, data);
703 }
704
705 static int fw_message_send(struct tegra_xhci_hcd *tegra,
706         enum MBOX_CMD_TYPE type, u32 data)
707 {
708         struct device *dev = &tegra->pdev->dev;
709         void __iomem *base = tegra->fpci_base;
710         unsigned long target;
711         u32 reg;
712
713         dev_dbg(dev, "%s type %d data 0x%x\n", __func__, type, data);
714
715         mutex_lock(&tegra->mbox_lock);
716
717         target = jiffies + msecs_to_jiffies(20);
718         /* wait mailbox to become idle, timeout in 20ms */
719         while (((reg = readl(base + XUSB_CFG_ARU_MBOX_OWNER)) != 0) &&
720                 time_is_after_jiffies(target)) {
721                 mutex_unlock(&tegra->mbox_lock);
722                 usleep_range(100, 200);
723                 mutex_lock(&tegra->mbox_lock);
724         }
725
726         if (reg != 0) {
727                 dev_err(dev, "%s mailbox is still busy\n", __func__);
728                 goto timeout;
729         }
730
731         target = jiffies + msecs_to_jiffies(10);
732         /* acquire mailbox , timeout in 10ms */
733         writel(MBOX_OWNER_SW, base + XUSB_CFG_ARU_MBOX_OWNER);
734         while (((reg = readl(base + XUSB_CFG_ARU_MBOX_OWNER)) != MBOX_OWNER_SW)
735                 && time_is_after_jiffies(target)) {
736                 mutex_unlock(&tegra->mbox_lock);
737                 usleep_range(100, 200);
738                 mutex_lock(&tegra->mbox_lock);
739                 writel(MBOX_OWNER_SW, base + XUSB_CFG_ARU_MBOX_OWNER);
740         }
741
742         if (reg != MBOX_OWNER_SW) {
743                 dev_err(dev, "%s acquire mailbox timeout\n", __func__);
744                 goto timeout;
745         }
746
747         reg = CMD_TYPE(type) | CMD_DATA(data);
748         writel(reg, base + XUSB_CFG_ARU_MBOX_DATA_IN);
749
750         reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
751         reg |= MBOX_INT_EN | MBOX_FALC_INT_EN;
752         writel(reg, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
753
754         mutex_unlock(&tegra->mbox_lock);
755         return 0;
756
757 timeout:
758         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_CMD);
759         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_DATA_IN);
760         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_DATA_OUT);
761         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_OWNER);
762         mutex_unlock(&tegra->mbox_lock);
763         return -ETIMEDOUT;
764 }
765
766 /**
767  * fw_log_next - find next log entry in a tegra_xhci_firmware_log context.
768  *      This function takes care of wrapping. That means when current log entry
769  *      is the last one, it returns with the first one.
770  *
771  * @param log   The tegra_xhci_firmware_log context.
772  * @param this  The current log entry.
773  * @return      The log entry which is next to the current one.
774  */
775 static inline struct log_entry *fw_log_next(
776                 struct tegra_xhci_firmware_log *log, struct log_entry *this)
777 {
778         struct log_entry *first = (struct log_entry *) log->virt_addr;
779         struct log_entry *last = first + FW_LOG_COUNT - 1;
780
781         WARN((this < first) || (this > last), "%s: invalid input\n", __func__);
782
783         return (this == last) ? first : (this + 1);
784 }
785
786 /**
787  * fw_log_update_dequeue_pointer - update dequeue pointer to both firmware and
788  *      tegra_xhci_firmware_log.dequeue.
789  *
790  * @param log   The tegra_xhci_firmware_log context.
791  * @param n     Counts of log entries to fast-forward.
792  */
793 static inline void fw_log_update_deq_pointer(
794                 struct tegra_xhci_firmware_log *log, int n)
795 {
796         struct tegra_xhci_hcd *tegra =
797                         container_of(log, struct tegra_xhci_hcd, log);
798         struct device *dev = &tegra->pdev->dev;
799         struct log_entry *deq = tegra->log.dequeue;
800         dma_addr_t physical_addr;
801         u32 reg;
802
803         dev_dbg(dev, "curr 0x%p fast-forward %d entries\n", deq, n);
804         while (n-- > 0)
805                 deq = fw_log_next(log, deq);
806
807         tegra->log.dequeue = deq;
808         physical_addr = tegra->log.phys_addr +
809                         ((u8 *)deq - (u8 *)tegra->log.virt_addr);
810
811         /* update dequeue pointer to firmware */
812         reg = (FW_IOCTL_LOG_DEQUEUE_LOW << FW_IOCTL_TYPE_SHIFT);
813         reg |= (physical_addr & 0xffff); /* lower 16-bits */
814         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
815
816         reg = (FW_IOCTL_LOG_DEQUEUE_HIGH << FW_IOCTL_TYPE_SHIFT);
817         reg |= ((physical_addr >> 16) & 0xffff); /* higher 16-bits */
818         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
819
820         dev_dbg(dev, "new 0x%p physical addr 0x%x\n", deq, (u32)physical_addr);
821 }
822
823 static inline bool circ_buffer_full(struct circ_buf *circ)
824 {
825         int space = CIRC_SPACE(circ->head, circ->tail, CIRC_BUF_SIZE);
826
827         return (space <= FW_LOG_SIZE);
828 }
829
830 static inline bool fw_log_available(struct tegra_xhci_hcd *tegra)
831 {
832         return (tegra->log.dequeue->owner == DRIVER);
833 }
834
835 /**
836  * fw_log_wait_empty_timeout - wait firmware log thread to clean up shared
837  *      log buffer.
838  * @param tegra:        tegra_xhci_hcd context
839  * @param msec:         timeout value in millisecond
840  * @return true:        shared log buffer is empty,
841  *         false:       shared log buffer isn't empty.
842  */
843 static inline bool fw_log_wait_empty_timeout(struct tegra_xhci_hcd *tegra,
844                 unsigned timeout)
845 {
846         unsigned long target = jiffies + msecs_to_jiffies(timeout);
847         bool ret;
848
849         mutex_lock(&tegra->log.mutex);
850
851         while (fw_log_available(tegra) && time_is_after_jiffies(target)) {
852                 mutex_unlock(&tegra->log.mutex);
853                 usleep_range(1000, 2000);
854                 mutex_lock(&tegra->log.mutex);
855         }
856
857         ret = fw_log_available(tegra);
858         mutex_unlock(&tegra->log.mutex);
859
860         return ret;
861 }
862
863 /**
864  * fw_log_copy - copy firmware log from device's buffer to driver's circular
865  *      buffer.
866  * @param tegra tegra_xhci_hcd context
867  * @return true,        We still have firmware log in device's buffer to copy.
868  *                      This function returned due the driver's circular buffer
869  *                      is full. Caller should invoke this function again as
870  *                      soon as there is space in driver's circular buffer.
871  *         false,       Device's buffer is empty.
872  */
873 static inline bool fw_log_copy(struct tegra_xhci_hcd *tegra)
874 {
875         struct device *dev = &tegra->pdev->dev;
876         struct circ_buf *circ = &tegra->log.circ;
877         int head, tail;
878         int buffer_len, copy_len;
879         struct log_entry *entry;
880         struct log_entry *first = tegra->log.virt_addr;
881
882         while (fw_log_available(tegra)) {
883
884                 /* calculate maximum contiguous driver buffer length */
885                 head = circ->head;
886                 tail = ACCESS_ONCE(circ->tail);
887                 buffer_len = CIRC_SPACE_TO_END(head, tail, CIRC_BUF_SIZE);
888                 /* round down to FW_LOG_SIZE */
889                 buffer_len -= (buffer_len % FW_LOG_SIZE);
890                 if (!buffer_len)
891                         return true; /* log available but no space left */
892
893                 /* calculate maximum contiguous log copy length */
894                 entry = tegra->log.dequeue;
895                 copy_len = 0;
896                 do {
897                         if (tegra->log.seq != entry->sequence_no) {
898                                 dev_warn(dev,
899                                 "%s: discontinuous seq no, expect %u get %u\n",
900                                 __func__, tegra->log.seq, entry->sequence_no);
901                         }
902                         tegra->log.seq = entry->sequence_no + 1;
903
904                         copy_len += FW_LOG_SIZE;
905                         buffer_len -= FW_LOG_SIZE;
906                         if (!buffer_len)
907                                 break; /* no space left */
908                         entry = fw_log_next(&tegra->log, entry);
909                 } while ((entry->owner == DRIVER) && (entry != first));
910
911                 memcpy(&circ->buf[head], tegra->log.dequeue, copy_len);
912                 memset(tegra->log.dequeue, 0, copy_len);
913                 circ->head = (circ->head + copy_len) & (CIRC_BUF_SIZE - 1);
914
915                 mb();
916
917                 fw_log_update_deq_pointer(&tegra->log, copy_len/FW_LOG_SIZE);
918
919                 dev_dbg(dev, "copied %d entries, new dequeue 0x%p\n",
920                                 copy_len/FW_LOG_SIZE, tegra->log.dequeue);
921                 wake_up_interruptible(&tegra->log.read_wait);
922         }
923
924         return false;
925 }
926
927 static int fw_log_thread(void *data)
928 {
929         struct tegra_xhci_hcd *tegra = data;
930         struct device *dev = &tegra->pdev->dev;
931         struct circ_buf *circ = &tegra->log.circ;
932         bool logs_left;
933
934         dev_dbg(dev, "start firmware log thread\n");
935
936         do {
937                 mutex_lock(&tegra->log.mutex);
938                 if (circ_buffer_full(circ)) {
939                         mutex_unlock(&tegra->log.mutex);
940                         dev_info(dev, "%s: circ buffer full\n", __func__);
941                         wait_event_interruptible(tegra->log.write_wait,
942                             kthread_should_stop() || !circ_buffer_full(circ));
943                         mutex_lock(&tegra->log.mutex);
944                 }
945
946                 logs_left = fw_log_copy(tegra);
947                 mutex_unlock(&tegra->log.mutex);
948
949                 /* relax if no logs left  */
950                 if (!logs_left)
951                         wait_event_interruptible_timeout(tegra->log.intr_wait,
952                                 fw_log_available(tegra), FW_LOG_THREAD_RELAX);
953         } while (!kthread_should_stop());
954
955         dev_dbg(dev, "stop firmware log thread\n");
956         return 0;
957 }
958
959 static inline bool circ_buffer_empty(struct circ_buf *circ)
960 {
961         return (CIRC_CNT(circ->head, circ->tail, CIRC_BUF_SIZE) == 0);
962 }
963
964 static ssize_t fw_log_file_read(struct file *file, char __user *buf,
965                 size_t count, loff_t *offp)
966 {
967         struct tegra_xhci_hcd *tegra = file->private_data;
968         struct platform_device *pdev = tegra->pdev;
969         struct circ_buf *circ = &tegra->log.circ;
970         int head, tail;
971         size_t n = 0;
972         int s;
973
974         mutex_lock(&tegra->log.mutex);
975
976         while (circ_buffer_empty(circ)) {
977                 mutex_unlock(&tegra->log.mutex);
978                 if (file->f_flags & O_NONBLOCK)
979                         return -EAGAIN; /* non-blocking read */
980
981                 dev_dbg(&pdev->dev, "%s: nothing to read\n", __func__);
982
983                 if (wait_event_interruptible(tegra->log.read_wait,
984                                 !circ_buffer_empty(circ)))
985                         return -ERESTARTSYS;
986
987                 if (mutex_lock_interruptible(&tegra->log.mutex))
988                         return -ERESTARTSYS;
989         }
990
991         while (count > 0) {
992                 head = ACCESS_ONCE(circ->head);
993                 tail = circ->tail;
994                 s = min_t(int, count,
995                                 CIRC_CNT_TO_END(head, tail, CIRC_BUF_SIZE));
996
997                 if (s > 0) {
998                         if (copy_to_user(&buf[n], &circ->buf[tail], s)) {
999                                 dev_warn(&pdev->dev, "copy_to_user failed\n");
1000                                 mutex_unlock(&tegra->log.mutex);
1001                                 return -EFAULT;
1002                         }
1003                         circ->tail = (circ->tail + s) & (CIRC_BUF_SIZE - 1);
1004
1005                         count -= s;
1006                         n += s;
1007                 } else
1008                         break;
1009         }
1010
1011         mutex_unlock(&tegra->log.mutex);
1012
1013         wake_up_interruptible(&tegra->log.write_wait);
1014
1015         dev_dbg(&pdev->dev, "%s: %d bytes\n", __func__, n);
1016
1017         return n;
1018 }
1019
1020 static int fw_log_file_open(struct inode *inode, struct file *file)
1021 {
1022         struct tegra_xhci_hcd *tegra;
1023         file->private_data = inode->i_private;
1024         tegra = file->private_data;
1025
1026         if (test_and_set_bit(FW_LOG_FILE_OPENED, &tegra->log.flags)) {
1027                 dev_info(&tegra->pdev->dev, "%s: already opened\n", __func__);
1028                 return -EBUSY;
1029         }
1030
1031         return 0;
1032 }
1033
1034 static int fw_log_file_close(struct inode *inode, struct file *file)
1035 {
1036         struct tegra_xhci_hcd *tegra = file->private_data;
1037
1038         clear_bit(FW_LOG_FILE_OPENED, &tegra->log.flags);
1039
1040         return 0;
1041 }
1042
1043 static const struct file_operations firmware_log_fops = {
1044                 .open           = fw_log_file_open,
1045                 .release        = fw_log_file_close,
1046                 .read           = fw_log_file_read,
1047                 .owner          = THIS_MODULE,
1048 };
1049
1050 static int fw_log_init(struct tegra_xhci_hcd *tegra)
1051 {
1052         struct platform_device *pdev = tegra->pdev;
1053         int rc = 0;
1054
1055         /* allocate buffer to be shared between driver and firmware */
1056         tegra->log.virt_addr = dma_alloc_writecombine(&pdev->dev,
1057                         FW_LOG_RING_SIZE, &tegra->log.phys_addr, GFP_KERNEL);
1058
1059         if (!tegra->log.virt_addr) {
1060                 dev_err(&pdev->dev, "dma_alloc_writecombine() size %d failed\n",
1061                                 FW_LOG_RING_SIZE);
1062                 return -ENOMEM;
1063         }
1064
1065         dev_info(&pdev->dev,
1066                 "%d bytes log buffer physical 0x%u virtual 0x%p\n",
1067                 FW_LOG_RING_SIZE, (u32)tegra->log.phys_addr,
1068                 tegra->log.virt_addr);
1069
1070         memset(tegra->log.virt_addr, 0, FW_LOG_RING_SIZE);
1071         tegra->log.dequeue = tegra->log.virt_addr;
1072
1073         tegra->log.circ.buf = vmalloc(CIRC_BUF_SIZE);
1074         if (!tegra->log.circ.buf) {
1075                 dev_err(&pdev->dev, "vmalloc size %d failed\n", CIRC_BUF_SIZE);
1076                 rc = -ENOMEM;
1077                 goto error_free_dma;
1078         }
1079
1080         tegra->log.circ.head = 0;
1081         tegra->log.circ.tail = 0;
1082
1083         init_waitqueue_head(&tegra->log.read_wait);
1084         init_waitqueue_head(&tegra->log.write_wait);
1085         init_waitqueue_head(&tegra->log.intr_wait);
1086
1087         mutex_init(&tegra->log.mutex);
1088
1089         tegra->log.path = debugfs_create_dir("tegra_xhci", NULL);
1090         if (IS_ERR_OR_NULL(tegra->log.path)) {
1091                 dev_warn(&pdev->dev, "debugfs_create_dir() failed\n");
1092                 rc = -ENOMEM;
1093                 goto error_free_mem;
1094         }
1095
1096         tegra->log.log_file = debugfs_create_file("firmware_log",
1097                         S_IRUGO, tegra->log.path, tegra, &firmware_log_fops);
1098         if ((!tegra->log.log_file) ||
1099                         (tegra->log.log_file == ERR_PTR(-ENODEV))) {
1100                 dev_warn(&pdev->dev, "debugfs_create_file() failed\n");
1101                 rc = -ENOMEM;
1102                 goto error_remove_debugfs_path;
1103         }
1104
1105         tegra->log.thread = kthread_run(fw_log_thread, tegra, "xusb-fw-log");
1106         if (IS_ERR(tegra->log.thread)) {
1107                 dev_warn(&pdev->dev, "kthread_run() failed\n");
1108                 rc = -ENOMEM;
1109                 goto error_remove_debugfs_file;
1110         }
1111
1112         set_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags);
1113         return rc;
1114
1115 error_remove_debugfs_file:
1116         debugfs_remove(tegra->log.log_file);
1117 error_remove_debugfs_path:
1118         debugfs_remove(tegra->log.path);
1119 error_free_mem:
1120         vfree(tegra->log.circ.buf);
1121 error_free_dma:
1122         dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1123                         tegra->log.virt_addr, tegra->log.phys_addr);
1124         memset(&tegra->log, sizeof(tegra->log), 0);
1125         return rc;
1126 }
1127
1128 static void fw_log_deinit(struct tegra_xhci_hcd *tegra)
1129 {
1130         struct platform_device *pdev = tegra->pdev;
1131
1132         if (test_and_clear_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
1133
1134                 debugfs_remove(tegra->log.log_file);
1135                 debugfs_remove(tegra->log.path);
1136
1137                 wake_up_interruptible(&tegra->log.read_wait);
1138                 wake_up_interruptible(&tegra->log.write_wait);
1139                 kthread_stop(tegra->log.thread);
1140
1141                 mutex_lock(&tegra->log.mutex);
1142                 dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1143                         tegra->log.virt_addr, tegra->log.phys_addr);
1144                 vfree(tegra->log.circ.buf);
1145                 tegra->log.circ.head = tegra->log.circ.tail = 0;
1146                 mutex_unlock(&tegra->log.mutex);
1147
1148                 mutex_destroy(&tegra->log.mutex);
1149         }
1150 }
1151
1152 /* hsic pad operations */
1153 /*
1154  * HSIC pads need VDDIO_HSIC power rail turned on to be functional. There is
1155  * only one VDDIO_HSIC power rail shared by all HSIC pads.
1156  */
1157 static int hsic_power_rail_enable(struct tegra_xhci_hcd *tegra)
1158 {
1159         struct device *dev = &tegra->pdev->dev;
1160         struct tegra_xusb_regulator_name *supply = &tegra->bdata->supply;
1161         int ret;
1162
1163         if (tegra->vddio_hsic_reg)
1164                 goto done;
1165
1166         tegra->vddio_hsic_reg = devm_regulator_get(dev, supply->vddio_hsic);
1167         if (IS_ERR_OR_NULL(tegra->vddio_hsic_reg)) {
1168                 dev_err(dev, "%s get vddio_hsic failed\n", __func__);
1169                 ret = PTR_ERR(tegra->vddio_hsic_reg);
1170                 goto get_failed;
1171         }
1172
1173         dev_dbg(dev, "%s regulator_enable vddio_hsic\n", __func__);
1174         ret = regulator_enable(tegra->vddio_hsic_reg);
1175         if (ret < 0) {
1176                 dev_err(dev, "%s enable vddio_hsic failed\n", __func__);
1177                 goto enable_failed;
1178         }
1179
1180 done:
1181         tegra->vddio_hsic_refcnt++;
1182         WARN(tegra->vddio_hsic_refcnt > XUSB_HSIC_COUNT,
1183                         "vddio_hsic_refcnt exceeds\n");
1184         return 0;
1185
1186 enable_failed:
1187         devm_regulator_put(tegra->vddio_hsic_reg);
1188 get_failed:
1189         tegra->vddio_hsic_reg = NULL;
1190         return ret;
1191 }
1192
1193 static int hsic_power_rail_disable(struct tegra_xhci_hcd *tegra)
1194 {
1195         struct device *dev = &tegra->pdev->dev;
1196         int ret;
1197
1198         WARN_ON(!tegra->vddio_hsic_reg || !tegra->vddio_hsic_refcnt);
1199
1200         tegra->vddio_hsic_refcnt--;
1201         if (tegra->vddio_hsic_refcnt)
1202                 return 0;
1203
1204         dev_dbg(dev, "%s regulator_disable vddio_hsic\n", __func__);
1205         ret = regulator_disable(tegra->vddio_hsic_reg);
1206         if (ret < 0) {
1207                 dev_err(dev, "%s disable vddio_hsic failed\n", __func__);
1208                 tegra->vddio_hsic_refcnt++;
1209                 return ret;
1210         }
1211
1212         devm_regulator_put(tegra->vddio_hsic_reg);
1213         tegra->vddio_hsic_reg = NULL;
1214
1215         return 0;
1216 }
1217
1218 static int hsic_pad_enable(struct tegra_xhci_hcd *tegra, unsigned pad)
1219 {
1220         struct device *dev = &tegra->pdev->dev;
1221         void __iomem *base = tegra->padctl_base;
1222         struct tegra_xusb_hsic_config *hsic = &tegra->bdata->hsic[pad];
1223         u32 reg;
1224
1225         if (pad >= XUSB_HSIC_COUNT) {
1226                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1227                 return -EINVAL;
1228         }
1229
1230         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1231
1232         reg = readl(base + HSIC_PAD_CTL_2(pad));
1233         reg &= ~(RX_STROBE_TRIM(~0) | RX_DATA_TRIM(~0));
1234         reg |= RX_STROBE_TRIM(hsic->rx_strobe_trim);
1235         reg |= RX_DATA_TRIM(hsic->rx_data_trim);
1236         writel(reg, base + HSIC_PAD_CTL_2(pad));
1237
1238         reg = readl(base + HSIC_PAD_CTL_0(pad));
1239         reg &= ~(TX_RTUNEP(~0) | TX_RTUNEN(~0) | TX_SLEWP(~0) | TX_SLEWN(~0));
1240         reg |= TX_RTUNEP(hsic->tx_rtune_p);
1241         reg |= TX_RTUNEN(hsic->tx_rtune_n);
1242         reg |= TX_SLEWP(hsic->tx_slew_p);
1243         reg |= TX_SLEWN(hsic->tx_slew_n);
1244         writel(reg, base + HSIC_PAD_CTL_0(pad));
1245
1246         reg = readl(base + HSIC_PAD_CTL_1(pad));
1247         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1248         reg |= (RPD_DATA | RPU_STROBE); /* keep HSIC in IDLE */
1249         if (hsic->auto_term_en)
1250                 reg |= AUTO_TERM_EN;
1251         else
1252                 reg &= ~AUTO_TERM_EN;
1253         reg &= ~(PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1254         writel(reg, base + HSIC_PAD_CTL_1(pad));
1255
1256         /* Wait for 25 us */
1257         usleep_range(25, 50);
1258
1259         /* Power down tracking circuit */
1260         reg = readl(base + HSIC_PAD_CTL_1(pad));
1261         reg |= PD_TRX;
1262         writel(reg, base + HSIC_PAD_CTL_1(pad));
1263
1264         reg = readl(base + HSIC_STRB_TRIM_CONTROL);
1265         reg &= ~(STRB_TRIM_VAL(~0));
1266         reg |= STRB_TRIM_VAL(hsic->strb_trim_val);
1267         writel(reg, base + HSIC_STRB_TRIM_CONTROL);
1268
1269         reg = readl(base + USB2_PAD_MUX);
1270         reg |= USB2_HSIC_PAD_PORT(pad);
1271         writel(reg, base + USB2_PAD_MUX);
1272
1273         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1274         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1275         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1276         reg_dump(dev, base, HSIC_STRB_TRIM_CONTROL);
1277         reg_dump(dev, base, USB2_PAD_MUX);
1278         return 0;
1279 }
1280
1281 static void hsic_pad_pretend_connect(struct tegra_xhci_hcd *tegra)
1282 {
1283         struct device *dev = &tegra->pdev->dev;
1284         struct tegra_xusb_hsic_config *hsic;
1285         struct usb_device *hs_root_hub = tegra->xhci->main_hcd->self.root_hub;
1286         int pad;
1287         u32 portsc;
1288         int port;
1289         int enabled_pads = 0;
1290         unsigned long wait_ports = 0;
1291         unsigned long target;
1292
1293         for_each_enabled_hsic_pad(pad, tegra) {
1294                 hsic = &tegra->bdata->hsic[pad];
1295                 if (hsic->pretend_connect)
1296                         enabled_pads++;
1297         }
1298
1299         if (enabled_pads == 0) {
1300                 dev_dbg(dev, "%s no hsic pretend_connect enabled\n", __func__);
1301                 return;
1302         }
1303
1304         usb_disable_autosuspend(hs_root_hub);
1305
1306         for_each_enabled_hsic_pad(pad, tegra) {
1307                 hsic = &tegra->bdata->hsic[pad];
1308                 if (!hsic->pretend_connect)
1309                         continue;
1310
1311                 port = hsic_pad_to_port(pad);
1312                 portsc = xhci_read_portsc(tegra->xhci, port);
1313                 dev_dbg(dev, "%s pad %u portsc 0x%x\n", __func__, pad, portsc);
1314
1315                 if (!(portsc & PORT_CONNECT)) {
1316                         /* firmware wants 1-based port index */
1317                         fw_message_send(tegra,
1318                                 MBOX_CMD_HSIC_PRETEND_CONNECT, BIT(port + 1));
1319                 }
1320
1321                 set_bit(port, &wait_ports);
1322         }
1323
1324         /* wait till port reaches U0 */
1325         target = jiffies + msecs_to_jiffies(500);
1326         do {
1327                 for_each_set_bit(port, &wait_ports, BITS_PER_LONG) {
1328                         portsc = xhci_read_portsc(tegra->xhci, port);
1329                         pad = port_to_hsic_pad(port);
1330                         dev_dbg(dev, "%s pad %u portsc 0x%x\n", __func__,
1331                                 pad, portsc);
1332                         if ((PORT_PLS_MASK & portsc) == XDEV_U0)
1333                                 clear_bit(port, &wait_ports);
1334                 }
1335
1336                 if (wait_ports)
1337                         usleep_range(1000, 5000);
1338         } while (wait_ports && time_is_after_jiffies(target));
1339
1340         if (wait_ports)
1341                 dev_warn(dev, "%s HSIC pad(s) didn't reach U0.\n", __func__);
1342
1343         usb_enable_autosuspend(hs_root_hub);
1344
1345         return;
1346 }
1347
1348 static int hsic_pad_disable(struct tegra_xhci_hcd *tegra, unsigned pad)
1349 {
1350         struct device *dev = &tegra->pdev->dev;
1351         void __iomem *base = tegra->padctl_base;
1352         u32 reg;
1353
1354         if (pad >= XUSB_HSIC_COUNT) {
1355                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1356                 return -EINVAL;
1357         }
1358
1359         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1360
1361         reg = readl(base + USB2_PAD_MUX);
1362         reg &= ~USB2_HSIC_PAD_PORT(pad);
1363         writel(reg, base + USB2_PAD_MUX);
1364
1365         reg = readl(base + HSIC_PAD_CTL_1(pad));
1366         reg |= (PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1367         writel(reg, base + HSIC_PAD_CTL_1(pad));
1368
1369         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1370         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1371         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1372         reg_dump(dev, base, USB2_PAD_MUX);
1373         return 0;
1374 }
1375
1376 enum hsic_pad_pupd {
1377         PUPD_DISABLE = 0,
1378         PUPD_IDLE,
1379         PUPD_RESET
1380 };
1381
1382 static int hsic_pad_pupd_set(struct tegra_xhci_hcd *tegra, unsigned pad,
1383         enum hsic_pad_pupd pupd)
1384 {
1385         struct device *dev = &tegra->pdev->dev;
1386         void __iomem *base = tegra->padctl_base;
1387         u32 reg;
1388
1389         if (pad >= XUSB_HSIC_COUNT) {
1390                 dev_err(dev, "%s invalid HSIC pad number %u\n", __func__, pad);
1391                 return -EINVAL;
1392         }
1393
1394         dev_dbg(dev, "%s pad %u pupd %d\n", __func__, pad, pupd);
1395
1396         reg = readl(base + HSIC_PAD_CTL_1(pad));
1397         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1398
1399         if (pupd == PUPD_IDLE)
1400                 reg |= (RPD_DATA | RPU_STROBE);
1401         else if (pupd == PUPD_RESET)
1402                 reg |= (RPD_DATA | RPD_STROBE);
1403         else if (pupd != PUPD_DISABLE) {
1404                 dev_err(dev, "%s invalid pupd %d\n", __func__, pupd);
1405                 return -EINVAL;
1406         }
1407
1408         writel(reg, base + HSIC_PAD_CTL_1(pad));
1409
1410         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1411
1412         return 0;
1413 }
1414
1415
1416 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
1417 {
1418         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1419         struct xhci_hcd *xhci = tegra->xhci;
1420         u32 reg;
1421
1422         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
1423         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1424         xhci_info(xhci, " PAD MUX = %x\n", reg);
1425         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1426         xhci_info(xhci, " PORT CAP = %x\n", reg);
1427         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1428         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
1429         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1430         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
1431         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1432         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
1433         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1434         xhci_info(xhci, " OC DET 0= %x\n", reg);
1435         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad0_ctl2_0);
1436         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
1437         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad1_ctl2_0);
1438         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
1439         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl0_0);
1440         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
1441         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl0_0);
1442         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
1443         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl1_0);
1444         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
1445         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl1_0);
1446         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
1447         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1448         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
1449         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad0_ctl0_0);
1450         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
1451         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad1_ctl0_0);
1452         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
1453         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
1454 }
1455
1456 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
1457 {
1458         u32 reg;
1459
1460         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1461         reg |= IPFS_EN_FPCI;
1462         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1463         udelay(10);
1464
1465         /* Program Bar0 Space */
1466         reg = readl(tegra->fpci_base + XUSB_CFG_4);
1467         reg |= tegra->host_phy_base;
1468         writel(reg, tegra->fpci_base + XUSB_CFG_4);
1469         usleep_range(100, 200);
1470
1471         /* Enable Bus Master */
1472         reg = readl(tegra->fpci_base + XUSB_CFG_1);
1473         reg |= 0x7;
1474         writel(reg, tegra->fpci_base + XUSB_CFG_1);
1475
1476         /* Set intr mask to enable intr assertion */
1477         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1478         reg |= IPFS_IP_INT_MASK;
1479         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1480
1481         /* Set hysteris to 0x80 */
1482         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1483 }
1484
1485 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
1486                 struct platform_device *pdev)
1487 {
1488         struct tegra_xusb_regulator_name *supply = &tegra->bdata->supply;
1489         int i;
1490         int err = 0;
1491
1492         tegra->xusb_s3p3v_reg =
1493                         devm_regulator_get(&pdev->dev, supply->s3p3v);
1494         if (IS_ERR(tegra->xusb_s3p3v_reg)) {
1495                 dev_err(&pdev->dev, "3p3v: regulator not found: %ld."
1496                         , PTR_ERR(tegra->xusb_s3p3v_reg));
1497                 err = PTR_ERR(tegra->xusb_s3p3v_reg);
1498                 goto err_null_regulator;
1499         } else {
1500                 err = regulator_enable(tegra->xusb_s3p3v_reg);
1501                 if (err < 0) {
1502                         dev_err(&pdev->dev,
1503                                 "3p3v: regulator enable failed:%d\n", err);
1504                         goto err_null_regulator;
1505                 }
1506         }
1507
1508         /* enable utmi vbuses */
1509         memset(tegra->xusb_utmi_vbus_regs, 0,
1510                         sizeof(tegra->xusb_utmi_vbus_regs));
1511         for (i = 0; i < XUSB_UTMI_COUNT; i++) {
1512                 struct regulator *reg = NULL;
1513                 const char *reg_name = supply->utmi_vbuses[i];
1514                 if (BIT(XUSB_UTMI_INDEX + i) & tegra->bdata->portmap) {
1515                         if (i == 0 && tegra->transceiver)
1516                                 continue;
1517                         reg = devm_regulator_get(&pdev->dev, reg_name);
1518                         if (IS_ERR(reg)) {
1519                                 dev_err(&pdev->dev,
1520                                         "%s regulator not found: %ld.",
1521                                         reg_name, PTR_ERR(reg));
1522                                 err = PTR_ERR(reg);
1523                         } else {
1524                                 err = regulator_enable(reg);
1525                                 if (err < 0) {
1526                                         dev_err(&pdev->dev,
1527                                         "%s: regulator enable failed: %d\n",
1528                                         reg_name, err);
1529                                 }
1530                         }
1531                         if (err)
1532                                 goto err_put_utmi_vbus_reg;
1533                 }
1534                 tegra->xusb_utmi_vbus_regs[i] = reg;
1535         }
1536
1537         tegra->xusb_s1p8v_reg =
1538                 devm_regulator_get(&pdev->dev, supply->s1p8v);
1539         if (IS_ERR(tegra->xusb_s1p8v_reg)) {
1540                 dev_err(&pdev->dev, "1p8v regulator not found: %ld."
1541                         , PTR_ERR(tegra->xusb_s1p8v_reg));
1542                 err = PTR_ERR(tegra->xusb_s1p8v_reg);
1543                 goto err_put_utmi_vbus_reg;
1544         } else {
1545                 err = regulator_enable(tegra->xusb_s1p8v_reg);
1546                 if (err < 0) {
1547                         dev_err(&pdev->dev,
1548                         "1p8v: regulator enable failed:%d\n", err);
1549                         goto err_put_utmi_vbus_reg;
1550                 }
1551         }
1552
1553         tegra->xusb_s1p05v_reg =
1554                         devm_regulator_get(&pdev->dev, supply->s1p05v);
1555         if (IS_ERR(tegra->xusb_s1p05v_reg)) {
1556                 dev_err(&pdev->dev, "1p05v: regulator not found: %ld."
1557                         , PTR_ERR(tegra->xusb_s1p05v_reg));
1558                 err = PTR_ERR(tegra->xusb_s1p05v_reg);
1559                 goto err_put_s1p8v_reg;
1560         } else {
1561                 err = regulator_enable(tegra->xusb_s1p05v_reg);
1562                 if (err < 0) {
1563                         dev_err(&pdev->dev,
1564                         "1p05v: regulator enable failed:%d\n", err);
1565                         goto err_put_s1p8v_reg;
1566                 }
1567         }
1568
1569         return err;
1570
1571 err_put_s1p8v_reg:
1572         regulator_disable(tegra->xusb_s1p8v_reg);
1573 err_put_utmi_vbus_reg:
1574         for (i = 0; i < XUSB_UTMI_COUNT; i++) {
1575                 struct regulator *reg = tegra->xusb_utmi_vbus_regs[i];
1576                 if (!IS_ERR_OR_NULL(reg))
1577                         regulator_disable(reg);
1578         }
1579         regulator_disable(tegra->xusb_s3p3v_reg);
1580 err_null_regulator:
1581         for (i = 0; i < XUSB_UTMI_COUNT; i++)
1582                 tegra->xusb_utmi_vbus_regs[i] = NULL;
1583         tegra->xusb_s1p05v_reg = NULL;
1584         tegra->xusb_s3p3v_reg = NULL;
1585         tegra->xusb_s1p8v_reg = NULL;
1586         return err;
1587 }
1588
1589 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
1590 {
1591         int i;
1592
1593         regulator_disable(tegra->xusb_s1p05v_reg);
1594         regulator_disable(tegra->xusb_s1p8v_reg);
1595
1596         for (i = 0; i < XUSB_UTMI_COUNT; i++) {
1597                 if (BIT(XUSB_UTMI_INDEX + i) & tegra->bdata->portmap) {
1598                         struct regulator *reg = tegra->xusb_utmi_vbus_regs[i];
1599                         if (!IS_ERR_OR_NULL(reg))
1600                                 regulator_disable(reg);
1601                         tegra->xusb_utmi_vbus_regs[i] = NULL;
1602                 }
1603         }
1604
1605         regulator_disable(tegra->xusb_s3p3v_reg);
1606
1607         tegra->xusb_s1p05v_reg = NULL;
1608         tegra->xusb_s1p8v_reg = NULL;
1609         tegra->xusb_s3p3v_reg = NULL;
1610 }
1611
1612 /*
1613  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
1614  * are under hardware control
1615  */
1616 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
1617 {
1618         struct platform_device *pdev = tegra->pdev;
1619         int err = 0;
1620
1621         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
1622         if (IS_ERR(tegra->plle_clk)) {
1623                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
1624                 err = PTR_ERR(tegra->plle_clk);
1625                 return err;
1626         }
1627         err = clk_enable(tegra->plle_clk);
1628         if (err) {
1629                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
1630                         __func__);
1631                 return err;
1632         }
1633
1634         return err;
1635 }
1636
1637 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
1638 {
1639         clk_disable(tegra->plle_clk);
1640         tegra->plle_clk = NULL;
1641 }
1642
1643 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
1644 {
1645         struct platform_device *pdev = tegra->pdev;
1646         int err = 0;
1647
1648         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
1649         if (IS_ERR(tegra->emc_clk)) {
1650                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
1651                 return PTR_ERR(tegra->emc_clk);
1652         }
1653
1654         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1655                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
1656                 if (IS_ERR(tegra->pll_re_vco_clk)) {
1657                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
1658                         err = PTR_ERR(tegra->pll_re_vco_clk);
1659                         goto get_pll_re_vco_clk_failed;
1660                 }
1661         }
1662
1663         /* get the clock handle of 120MHz clock source */
1664         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
1665         if (IS_ERR(tegra->pll_u_480M)) {
1666                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
1667                 err = PTR_ERR(tegra->pll_u_480M);
1668                 goto get_pll_u_480M_failed;
1669         }
1670
1671         /* get the clock handle of 12MHz clock source */
1672         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1673         if (IS_ERR(tegra->clk_m)) {
1674                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
1675                 err = PTR_ERR(tegra->clk_m);
1676                 goto clk_get_clk_m_failed;
1677         }
1678
1679         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
1680         if (IS_ERR(tegra->ss_src_clk)) {
1681                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
1682                 err = PTR_ERR(tegra->ss_src_clk);
1683                 tegra->ss_src_clk = NULL;
1684                 goto get_ss_src_clk_failed;
1685         }
1686
1687         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
1688         if (IS_ERR(tegra->host_clk)) {
1689                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
1690                 err = PTR_ERR(tegra->host_clk);
1691                 tegra->host_clk = NULL;
1692                 goto get_host_clk_failed;
1693         }
1694
1695         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
1696         if (IS_ERR(tegra->ss_clk)) {
1697                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
1698                 err = PTR_ERR(tegra->ss_clk);
1699                 tegra->ss_clk = NULL;
1700                 goto get_ss_clk_failed;
1701         }
1702
1703         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1704                 err = clk_enable(tegra->pll_re_vco_clk);
1705                 if (err) {
1706                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
1707                         goto enable_pll_re_vco_clk_failed;
1708                 }
1709         }
1710         return 0;
1711
1712 enable_pll_re_vco_clk_failed:
1713         tegra->ss_clk = NULL;
1714
1715 get_ss_clk_failed:
1716         tegra->host_clk = NULL;
1717
1718 get_host_clk_failed:
1719         tegra->ss_src_clk = NULL;
1720
1721 get_ss_src_clk_failed:
1722         tegra->clk_m = NULL;
1723
1724 clk_get_clk_m_failed:
1725         tegra->pll_u_480M = NULL;
1726
1727 get_pll_u_480M_failed:
1728         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1729                 tegra->pll_re_vco_clk = NULL;
1730
1731 get_pll_re_vco_clk_failed:
1732         tegra->emc_clk = NULL;
1733
1734         return err;
1735 }
1736
1737 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
1738 {
1739         clk_disable(tegra->ss_clk);
1740         clk_disable(tegra->host_clk);
1741         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1742                 clk_disable(tegra->pll_re_vco_clk);
1743         tegra->ss_clk = NULL;
1744         tegra->host_clk = NULL;
1745         tegra->ss_src_clk = NULL;
1746         tegra->clk_m = NULL;
1747         tegra->pll_u_480M = NULL;
1748         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1749                 tegra->pll_re_vco_clk = NULL;
1750 }
1751
1752 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
1753         bool enable)
1754 {
1755         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1756         u32 reg;
1757
1758         /* Issue is only applicable for T114 */
1759         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
1760                 return;
1761
1762         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1763                 reg = readl(tegra->padctl_base +
1764                         padregs->iophy_misc_pad_p0_ctl3_0);
1765                 if (enable) {
1766                         reg &= ~RX_IDLE_MODE;
1767                         reg |= RX_IDLE_MODE_OVRD;
1768                 } else {
1769                         reg |= RX_IDLE_MODE;
1770                         reg &= ~RX_IDLE_MODE_OVRD;
1771                 }
1772                 writel(reg, tegra->padctl_base +
1773                         padregs->iophy_misc_pad_p0_ctl3_0);
1774         }
1775
1776         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1777                 reg = readl(tegra->padctl_base +
1778                         padregs->iophy_misc_pad_p1_ctl3_0);
1779                 if (enable) {
1780                         reg &= ~RX_IDLE_MODE;
1781                         reg |= RX_IDLE_MODE_OVRD;
1782                 } else {
1783                         reg |= RX_IDLE_MODE;
1784                         reg &= ~RX_IDLE_MODE_OVRD;
1785                 }
1786                 writel(reg, tegra->padctl_base +
1787                         padregs->iophy_misc_pad_p1_ctl3_0);
1788
1789                 /* SATA lane also if USB3_SS port1 mapped to it */
1790                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
1791                                 tegra->bdata->lane_owner & BIT(0)) {
1792                         reg = readl(tegra->padctl_base +
1793                                 padregs->iophy_misc_pad_s0_ctl3_0);
1794                         if (enable) {
1795                                 reg &= ~RX_IDLE_MODE;
1796                                 reg |= RX_IDLE_MODE_OVRD;
1797                         } else {
1798                                 reg |= RX_IDLE_MODE;
1799                                 reg &= ~RX_IDLE_MODE_OVRD;
1800                         }
1801                         writel(reg, tegra->padctl_base +
1802                                 padregs->iophy_misc_pad_s0_ctl3_0);
1803                 }
1804         }
1805 }
1806
1807 /* Enable ss clk, host clk, falcon clk,
1808  * fs clk, dev clk, plle and refplle
1809  */
1810
1811 static int
1812 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
1813                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
1814 {
1815         int ret = 0;
1816         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
1817         int fw_req_rate = rate, cur_rate;
1818
1819         /* Do not handle clock change as needed for HS disconnect issue */
1820         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1821                 *sw_resp = CMD_DATA(fw_req_rate) | CMD_TYPE(MBOX_CMD_ACK);
1822                 return ret;
1823         }
1824
1825         /* frequency request from firmware is in KHz.
1826          * Convert it to MHz
1827          */
1828
1829         /* get current rate of clock */
1830         cur_rate = clk_get_rate(clk_handle);
1831         cur_rate /= 1000;
1832
1833         if (fw_req_rate == cur_rate) {
1834                 cmd_ack = MBOX_CMD_ACK;
1835
1836         } else {
1837
1838                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
1839                         /* Change SS clock source to CLK_M at 12MHz */
1840                         clk_set_parent(clk_handle, tegra->clk_m);
1841                         clk_set_rate(clk_handle, fw_req_rate * 1000);
1842
1843                         /* save leakage power when SS freq is being decreased */
1844                         tegra_xhci_rx_idle_mode_override(tegra, true);
1845                 } else if (clk_handle == tegra->ss_src_clk &&
1846                                 fw_req_rate == 120000) {
1847                         /* Change SS clock source to HSIC_480 at 120MHz */
1848                         clk_set_rate(clk_handle,  3000 * 1000);
1849                         clk_set_parent(clk_handle, tegra->pll_u_480M);
1850
1851                         /* clear ovrd bits when SS freq is being increased */
1852                         tegra_xhci_rx_idle_mode_override(tegra, false);
1853                 }
1854
1855                 cur_rate = (clk_get_rate(clk_handle) / 1000);
1856
1857                 if (cur_rate != fw_req_rate) {
1858                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
1859                                 cur_rate, fw_req_rate);
1860                         cmd_ack = MBOX_CMD_NACK;
1861                 }
1862         }
1863         *sw_resp = CMD_DATA(cur_rate) | CMD_TYPE(cmd_ack);
1864         return ret;
1865 }
1866
1867 static void tegra_xusb_set_bw(struct tegra_xhci_hcd *tegra, unsigned int bw)
1868 {
1869         unsigned int freq_khz;
1870
1871         freq_khz = tegra_emc_bw_to_freq_req(bw);
1872         clk_set_rate(tegra->emc_clk, freq_khz * 1000);
1873 }
1874
1875 static void tegra_xhci_save_dfe_context(struct tegra_xhci_hcd *tegra,
1876         u8 port)
1877 {
1878         struct xhci_hcd *xhci = tegra->xhci;
1879         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1880         u32 offset;
1881         u32 reg;
1882
1883         if (port > (XUSB_SS_PORT_COUNT - 1)) {
1884                 pr_err("%s invalid SS port number %u\n", __func__, port);
1885                 return;
1886         }
1887
1888         xhci_info(xhci, "saving restore DFE context for port %d\n", port);
1889
1890         /* if port1 is mapped to SATA lane then read from SATA register */
1891         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1892                         tegra->bdata->lane_owner & BIT(0))
1893                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1894         else
1895                 offset = MISC_PAD_CTL_6_0(port);
1896
1897         /*
1898          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
1899          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
1900          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
1901          */
1902         reg = readl(tegra->padctl_base + offset);
1903         reg &= ~MISC_OUT_SEL(~0);
1904         reg |= MISC_OUT_SEL(0x32);
1905         writel(reg, tegra->padctl_base + offset);
1906
1907         reg = readl(tegra->padctl_base + offset);
1908         tegra->sregs.tap1_val[port] = MISC_OUT_TAP_VAL(reg);
1909
1910         reg = readl(tegra->padctl_base + offset);
1911         reg &= ~MISC_OUT_SEL(~0);
1912         reg |= MISC_OUT_SEL(0x33);
1913         writel(reg, tegra->padctl_base + offset);
1914
1915         reg = readl(tegra->padctl_base + offset);
1916         tegra->sregs.amp_val[port] = MISC_OUT_AMP_VAL(reg);
1917
1918         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1919         reg &= ~DFE_CNTL_TAP_VAL(~0);
1920         reg |= DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
1921         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1922
1923         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1924         reg &= ~DFE_CNTL_AMP_VAL(~0);
1925         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]);
1926         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1927
1928         tegra->dfe_ctx_saved[port] = true;
1929 }
1930
1931 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
1932         u8 port)
1933 {
1934         struct xhci_hcd *xhci = tegra->xhci;
1935         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1936         u32 offset;
1937         u32 reg;
1938
1939         if (port > (XUSB_SS_PORT_COUNT - 1)) {
1940                 pr_err("%s invalid SS port number %u\n", __func__, port);
1941                 return;
1942         }
1943
1944         xhci_info(xhci, "saving restore CTLE context for port %d\n", port);
1945
1946         /* if port1 is mapped to SATA lane then read from SATA register */
1947         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1948                         tegra->bdata->lane_owner & BIT(0))
1949                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1950         else
1951                 offset = MISC_PAD_CTL_6_0(port);
1952
1953         /*
1954          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
1955          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
1956          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
1957          */
1958         reg = readl(tegra->padctl_base + offset);
1959         reg &= ~MISC_OUT_SEL(~0);
1960         reg |= MISC_OUT_SEL(0xa1);
1961         writel(reg, tegra->padctl_base + offset);
1962
1963         reg = readl(tegra->padctl_base + offset);
1964         reg &= ~MISC_OUT_SEL(~0);
1965         reg |= MISC_OUT_SEL(0x21);
1966         writel(reg, tegra->padctl_base + offset);
1967
1968         reg = readl(tegra->padctl_base + offset);
1969         tegra->sregs.ctle_g_val[port] = MISC_OUT_G_Z_VAL(reg);
1970
1971         reg = readl(tegra->padctl_base + offset);
1972         reg &= ~MISC_OUT_SEL(~0);
1973         reg |= MISC_OUT_SEL(0x48);
1974         writel(reg, tegra->padctl_base + offset);
1975
1976         reg = readl(tegra->padctl_base + offset);
1977         tegra->sregs.ctle_z_val[port] = MISC_OUT_G_Z_VAL(reg);
1978
1979         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1980         reg &= ~RX_EQ_Z_VAL(~0);
1981         reg |= RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]);
1982         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1983
1984         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1985         reg &= ~RX_EQ_G_VAL(~0);
1986         reg |= RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]);
1987         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1988
1989         tegra->ctle_ctx_saved[port] = true;
1990 }
1991
1992 static void tegra_xhci_restore_dfe_context(struct tegra_xhci_hcd *tegra,
1993         u8 port)
1994 {
1995         struct xhci_hcd *xhci = tegra->xhci;
1996         u32 reg;
1997
1998         /* don't restore if not saved */
1999         if (tegra->dfe_ctx_saved[port] == false)
2000                 return;
2001
2002         xhci_info(xhci, "restoring dfe context of port %d\n", port);
2003
2004         /* restore dfe_cntl for the port */
2005         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
2006         reg &= ~(DFE_CNTL_AMP_VAL(~0) |
2007                         DFE_CNTL_TAP_VAL(~0));
2008         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]) |
2009                 DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
2010         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
2011 }
2012
2013 void restore_ctle_context(struct tegra_xhci_hcd *tegra,
2014         u8 port)
2015 {
2016         struct xhci_hcd *xhci = tegra->xhci;
2017         u32 reg;
2018
2019         /* don't restore if not saved */
2020         if (tegra->ctle_ctx_saved[port] == false)
2021                 return;
2022
2023         xhci_info(xhci, "restoring CTLE context of port %d\n", port);
2024
2025         /* restore ctle for the port */
2026         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
2027         reg &= ~(RX_EQ_Z_VAL(~0) |
2028                         RX_EQ_G_VAL(~0));
2029         reg |= (RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]) |
2030                 RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]));
2031         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
2032 }
2033
2034 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
2035         u8 port)
2036 {
2037         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2038         u32 reg;
2039
2040         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2041         reg &= ~USB2_ULPI_PAD;
2042         reg |= USB2_ULPI_PAD_OWNER_XUSB;
2043         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2044
2045         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
2046         reg &= ~USB2_ULPI_PORT_CAP;
2047         reg |= (tegra->bdata->ulpicap << 24);
2048         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
2049         /* FIXME: Program below when more details available
2050          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
2051          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
2052          */
2053 }
2054
2055 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
2056         u8 port)
2057 {
2058         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2059         u32 reg;
2060         u32 ctl0_offset, ctl1_offset;
2061
2062         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2063         reg &= ~USB2_OTG_PAD_PORT_MASK(port);
2064         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
2065         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2066
2067         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
2068         reg &= ~USB2_PORT_CAP_MASK(port);
2069         reg |= USB2_PORT_CAP_HOST(port);
2070         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
2071
2072         /*
2073          * Modify only the bits which belongs to the port
2074          * and enable respective VBUS_PAD for the port
2075          */
2076         if (tegra->bdata->uses_external_pmic == false) {
2077                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2078                 reg &= ~(port == 2 ? OC_DET_VBUS_ENABLE2_OC_MAP :
2079                         port ? OC_DET_VBUS_ENABLE1_OC_MAP :
2080                                 OC_DET_VBUS_ENABLE0_OC_MAP);
2081
2082                 reg |= (port == 2) ? OC_DET_VBUS_EN2_OC_DETECTED_VBUS_PAD2 :
2083                         port ? OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1 :
2084                                 OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0;
2085                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
2086         }
2087         /*
2088          * enable respective VBUS_PAD if port is mapped to any SS port
2089          */
2090         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
2091         reg &= ~((port == 2) ? USB2_OC_MAP_PORT2 :
2092                 port ? USB2_OC_MAP_PORT1 : USB2_OC_MAP_PORT0);
2093         reg |= (0x4 | port) << (port * 3);
2094         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
2095
2096         ctl0_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl0_0 :
2097                         port ? padregs->usb2_otg_pad1_ctl0_0 :
2098                                 padregs->usb2_otg_pad0_ctl0_0;
2099         ctl1_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl1_0 :
2100                         port ? padregs->usb2_otg_pad1_ctl1_0 :
2101                                 padregs->usb2_otg_pad0_ctl1_0;
2102
2103         reg = readl(tegra->padctl_base + ctl0_offset);
2104         reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
2105                 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
2106                 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
2107
2108         reg |= tegra->soc_config->hs_slew;
2109         reg |= (port == 2) ? tegra->soc_config->ls_rslew_pad2 :
2110                         port ? tegra->soc_config->ls_rslew_pad1 :
2111                         tegra->soc_config->ls_rslew_pad0;
2112         reg |= (port == 2) ? tegra->cdata->hs_curr_level_pad2 :
2113                         port ? tegra->cdata->hs_curr_level_pad1 :
2114                         tegra->cdata->hs_curr_level_pad0;
2115         writel(reg, tegra->padctl_base + ctl0_offset);
2116
2117         reg = readl(tegra->padctl_base + ctl1_offset);
2118         reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
2119                 | USB2_OTG_PD_CHRP_FORCE_POWERUP
2120                 | USB2_OTG_PD_DISC_FORCE_POWERUP
2121                 | USB2_OTG_PD_DR);
2122         reg |= (tegra->cdata->hs_iref_cap << 9) |
2123                 (tegra->cdata->hs_term_range_adj << 3);
2124         writel(reg, tegra->padctl_base + ctl1_offset);
2125
2126         /*Release OTG port if not in host mode*/
2127
2128         if ((port == 0) && !is_otg_host(tegra))
2129                 tegra_xhci_release_otg_port(true);
2130 }
2131
2132 static inline bool xusb_use_sata_lane(struct tegra_xhci_hcd *tegra)
2133 {
2134         return ((XUSB_DEVICE_ID_T114 == tegra->device_id) ? false
2135         : ((tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
2136                 && (tegra->bdata->lane_owner & BIT(0))));
2137 }
2138
2139 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
2140         u8 port)
2141 {
2142         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2143         u32 ctl2_offset, ctl4_offset, ctl5_offset;
2144         u32 reg;
2145
2146         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
2147                         padregs->iophy_usb3_pad0_ctl2_0;
2148         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
2149                         padregs->iophy_usb3_pad0_ctl4_0;
2150         ctl5_offset = port ? padregs->iophy_misc_pad_p1_ctl5_0 :
2151                         padregs->iophy_misc_pad_p0_ctl5_0;
2152
2153         reg = readl(tegra->padctl_base + ctl2_offset);
2154         reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
2155                 IOPHY_USB3_CDRCNTL);
2156         reg |= tegra->soc_config->rx_wander | tegra->soc_config->rx_eq |
2157                 tegra->soc_config->cdr_cntl;
2158         writel(reg, tegra->padctl_base + ctl2_offset);
2159
2160         reg = readl(tegra->padctl_base + ctl4_offset);
2161         reg = tegra->soc_config->dfe_cntl;
2162         writel(reg, tegra->padctl_base + ctl4_offset);
2163
2164         reg = readl(tegra->padctl_base + ctl5_offset);
2165         reg |= RX_QEYE_EN;
2166         writel(reg, tegra->padctl_base + ctl5_offset);
2167
2168         reg = readl(tegra->padctl_base + MISC_PAD_CTL_2_0(port));
2169         reg &= ~SPARE_IN(~0);
2170         reg |= SPARE_IN(tegra->soc_config->spare_in);
2171         writel(reg, tegra->padctl_base + MISC_PAD_CTL_2_0(port));
2172
2173         if (xusb_use_sata_lane(tegra)) {
2174                 reg = readl(tegra->padctl_base + MISC_PAD_S0_CTL_5_0);
2175                 reg |= RX_QEYE_EN;
2176                 writel(reg, tegra->padctl_base + MISC_PAD_S0_CTL_5_0);
2177
2178                 reg = readl(tegra->padctl_base + MISC_PAD_S0_CTL_2_0);
2179                 reg &= ~SPARE_IN(~0);
2180                 reg |= SPARE_IN(tegra->soc_config->spare_in);
2181                 writel(reg, tegra->padctl_base + MISC_PAD_S0_CTL_2_0);
2182         }
2183
2184         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
2185         reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
2186         reg |= (tegra->bdata->ss_portmap &
2187                 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
2188         writel(reg, tegra->padctl_base + padregs->ss_port_map_0);
2189
2190         tegra_xhci_restore_dfe_context(tegra, port);
2191         tegra_xhci_restore_ctle_context(tegra, port);
2192 }
2193
2194 /* This function assigns the USB ports to the controllers,
2195  * then programs the port capabilities and pad parameters
2196  * of ports assigned to XUSB after booted to OS.
2197  */
2198 void
2199 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
2200 {
2201         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2202         u32 reg, oc_bits = 0;
2203         unsigned pad;
2204
2205         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2206         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
2207         reg |= tegra->cdata->hs_squelch_level | tegra->soc_config->hs_disc_lvl;
2208         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2209
2210         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
2211         reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3;
2212         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
2213         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
2214
2215         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2216         reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
2217         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2218                 reg |= OC_DET_VBUS_ENABLE2_OC_MAP;
2219         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2220
2221         /* check if over current seen. Clear if present */
2222         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2223                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2224         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2225                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2226         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2227                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2228
2229         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2230         if (reg & oc_bits) {
2231                 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
2232                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
2233
2234                 usleep_range(100, 200);
2235
2236                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2237                 if (reg & oc_bits)
2238                         xhci_info(tegra->xhci, "Over current still present\n");
2239         }
2240
2241         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
2242         reg = USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1;
2243         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2244                 reg |= USB2_OC_MAP_PORT2;
2245         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
2246
2247         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2248                 tegra_xhci_program_utmip_pad(tegra, 0);
2249         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2250                 tegra_xhci_program_utmip_pad(tegra, 1);
2251         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2252                 tegra_xhci_program_utmip_pad(tegra, 2);
2253
2254         for_each_enabled_hsic_pad(pad, tegra)
2255                 hsic_pad_enable(tegra, pad);
2256
2257         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
2258                 tegra_xhci_program_ulpi_pad(tegra, 0);
2259
2260         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
2261                 tegra_xhci_program_ss_pad(tegra, 0);
2262         } else {
2263                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
2264                 reg = readl(tegra->padctl_base +
2265                         padregs->iophy_misc_pad_p0_ctl3_0);
2266                 reg &= ~RX_IDLE_MODE;
2267                 reg |= RX_IDLE_MODE_OVRD;
2268                 writel(reg, tegra->padctl_base +
2269                         padregs->iophy_misc_pad_p0_ctl3_0);
2270         }
2271
2272         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
2273                 tegra_xhci_program_ss_pad(tegra, 1);
2274         } else {
2275                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
2276                 reg = readl(tegra->padctl_base +
2277                         padregs->iophy_misc_pad_p1_ctl3_0);
2278                 reg &= ~RX_IDLE_MODE;
2279                 reg |= RX_IDLE_MODE_OVRD;
2280                 writel(reg, tegra->padctl_base +
2281                         padregs->iophy_misc_pad_p1_ctl3_0);
2282
2283                 /* SATA lane also if USB3_SS port1 mapped to it but unused */
2284                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
2285                                 tegra->bdata->lane_owner & BIT(0)) {
2286                         reg = readl(tegra->padctl_base +
2287                                 padregs->iophy_misc_pad_s0_ctl3_0);
2288                         reg &= ~RX_IDLE_MODE;
2289                         reg |= RX_IDLE_MODE_OVRD;
2290                         writel(reg, tegra->padctl_base +
2291                                 padregs->iophy_misc_pad_s0_ctl3_0);
2292                 }
2293         }
2294         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2295                 tegra_xhci_setup_gpio_for_ss_lane(tegra);
2296                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
2297         }
2298 }
2299
2300 /* This function read XUSB registers and stores in device context */
2301 static void
2302 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
2303 {
2304
2305         /* a. Save the IPFS registers */
2306         tegra->sregs.msi_bar_sz =
2307                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2308
2309         tegra->sregs.msi_axi_barst =
2310                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2311
2312         tegra->sregs.msi_fpci_barst =
2313                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2314
2315         tegra->sregs.msi_vec0 =
2316                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2317
2318         tegra->sregs.msi_en_vec0 =
2319                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2320
2321         tegra->sregs.fpci_error_masks =
2322                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2323
2324         tegra->sregs.intr_mask =
2325                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2326
2327         tegra->sregs.ipfs_intr_enable =
2328                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2329
2330         tegra->sregs.ufpci_config =
2331                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2332
2333         tegra->sregs.clkgate_hysteresis =
2334                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2335
2336         tegra->sregs.xusb_host_mccif_fifo_cntrl =
2337                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2338
2339         /* b. Save the CFG registers */
2340
2341         tegra->sregs.hs_pls =
2342                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2343
2344         tegra->sregs.fs_pls =
2345                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2346
2347         tegra->sregs.hs_fs_speed =
2348                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2349
2350         tegra->sregs.hs_fs_pp =
2351                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2352
2353         tegra->sregs.cfg_aru =
2354                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2355
2356         tegra->sregs.cfg_order =
2357                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
2358
2359         tegra->sregs.cfg_fladj =
2360                 readl(tegra->fpci_base + XUSB_CFG_24);
2361
2362         tegra->sregs.cfg_sid =
2363                 readl(tegra->fpci_base + XUSB_CFG_16);
2364 }
2365
2366 /* This function restores XUSB registers from device context */
2367 static void
2368 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
2369 {
2370         /* Restore Cfg registers */
2371         writel(tegra->sregs.hs_pls,
2372                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2373
2374         writel(tegra->sregs.fs_pls,
2375                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2376
2377         writel(tegra->sregs.hs_fs_speed,
2378                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2379
2380         writel(tegra->sregs.hs_fs_pp,
2381                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2382
2383         writel(tegra->sregs.cfg_aru,
2384                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2385
2386         writel(tegra->sregs.cfg_order,
2387                 tegra->fpci_base + XUSB_CFG_FPCICFG);
2388
2389         writel(tegra->sregs.cfg_fladj,
2390                 tegra->fpci_base + XUSB_CFG_24);
2391
2392         writel(tegra->sregs.cfg_sid,
2393                 tegra->fpci_base + XUSB_CFG_16);
2394
2395         /* Restore IPFS registers */
2396
2397         writel(tegra->sregs.msi_bar_sz,
2398                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2399
2400         writel(tegra->sregs.msi_axi_barst,
2401                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2402
2403         writel(tegra->sregs.msi_fpci_barst,
2404                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2405
2406         writel(tegra->sregs.msi_vec0,
2407                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2408
2409         writel(tegra->sregs.msi_en_vec0,
2410                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2411
2412         writel(tegra->sregs.fpci_error_masks,
2413                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2414
2415         writel(tegra->sregs.intr_mask,
2416                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2417
2418         writel(tegra->sregs.ipfs_intr_enable,
2419                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2420
2421         writel(tegra->sregs.ufpci_config,
2422                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2423
2424         writel(tegra->sregs.clkgate_hysteresis,
2425                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2426
2427         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
2428                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2429 }
2430
2431 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
2432 {
2433         fw_message_send(tegra, MBOX_CMD_MSG_ENABLED, 0 /* no data needed */);
2434 }
2435
2436 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
2437 {
2438         struct platform_device *pdev = tegra->pdev;
2439         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
2440         u32 phys_addr_lo;
2441         u32 HwReg;
2442         u16 nblocks;
2443         time_t fw_time;
2444         struct tm fw_tm;
2445         u8 hc_caplength;
2446         u32 usbsts, count = 0xff;
2447         struct xhci_cap_regs __iomem *cap_regs;
2448         struct xhci_op_regs __iomem *op_regs;
2449         int pad;
2450
2451         /* enable mbox interrupt */
2452         writel(readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD) | MBOX_INT_EN,
2453                 tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2454
2455         /* First thing, reset the ARU. By the time we get to
2456          * loading boot code below, reset would be complete.
2457          * alternatively we can busy wait on rst pending bit.
2458          */
2459         /* Don't reset during ELPG/LP0 exit path */
2460         if (resetARU) {
2461                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
2462                 usleep_range(1000, 2000);
2463         }
2464
2465         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
2466                 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
2467                                 csb_read(tegra, XUSB_FALC_CPUCTL));
2468                 return 0;
2469         }
2470
2471         /* update the phys_log_buffer and total_entries here */
2472         cfg_tbl->phys_addr_log_buffer = tegra->log.phys_addr;
2473         cfg_tbl->total_log_entries = FW_LOG_COUNT;
2474
2475         phys_addr_lo = tegra->firmware.dma;
2476         phys_addr_lo += sizeof(struct cfgtbl);
2477
2478         /* Program the size of DFI into ILOAD_ATTR */
2479         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
2480
2481         /* Boot code of the firmware reads the ILOAD_BASE_LO register
2482          * to get to the start of the dfi in system memory.
2483          */
2484         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
2485
2486         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
2487         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
2488
2489         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
2490         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
2491
2492         /* Invalidate L2IMEM. */
2493         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
2494
2495         /* Initiate fetch of Bootcode from system memory into L2IMEM.
2496          * Program BootCode location and size in system memory.
2497          */
2498         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
2499                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
2500                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
2501         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
2502                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
2503                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
2504         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
2505
2506         /* Trigger L2IMEM Load operation. */
2507         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
2508
2509         /* Setup Falcon Auto-fill */
2510         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
2511         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
2512                 nblocks += 1;
2513         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
2514
2515         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
2516         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
2517                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
2518         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
2519
2520         csb_write(tegra, XUSB_FALC_DMACTL, 0);
2521         msleep(50);
2522
2523         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
2524
2525         /* Start Falcon CPU */
2526         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
2527         usleep_range(1000, 2000);
2528
2529         fw_time = cfg_tbl->fwimg_created_time;
2530         time_to_tm(fw_time, 0, &fw_tm);
2531         dev_info(&pdev->dev,
2532                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
2533                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
2534                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
2535                 fw_tm.tm_min, fw_tm.tm_sec,
2536                 csb_read(tegra, XUSB_FALC_CPUCTL));
2537
2538         cfg_tbl->num_hsic_port = 0;
2539         for_each_enabled_hsic_pad(pad, tegra)
2540                 cfg_tbl->num_hsic_port++;
2541
2542         dev_dbg(&pdev->dev, "num_hsic_port %d\n", cfg_tbl->num_hsic_port);
2543
2544         /* return fail if firmware status is not good */
2545         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
2546                 return -EFAULT;
2547
2548         cap_regs = IO_ADDRESS(tegra->host_phy_base);
2549         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
2550         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
2551
2552         /* wait for USBSTS_CNR to get set */
2553         do {
2554                 usbsts = ioread32(&op_regs->status);
2555         } while ((usbsts & STS_CNR) && count--);
2556
2557         if (!count && (usbsts & STS_CNR)) {
2558                 dev_err(&pdev->dev, "Controller not ready\n");
2559                 return -EFAULT;
2560         }
2561         for_each_enabled_hsic_pad(pad, tegra)
2562                 hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
2563
2564         return 0;
2565 }
2566
2567 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
2568         bool release)
2569 {
2570         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2571         u32 reg;
2572
2573         /* Issue is only applicable for T114 */
2574         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
2575                 return;
2576
2577         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2578         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2579                         USB2_OTG_PAD_PORT_MASK(2));
2580
2581         if (!release) {
2582                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2583                         if (is_otg_host(tegra))
2584                                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2585                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2586                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2587                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2588                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2589         }
2590
2591         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2592 }
2593 /* SS ELPG Entry initiated by fw */
2594 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
2595 {
2596         struct xhci_hcd *xhci = tegra->xhci;
2597         u32 ret = 0;
2598
2599         must_have_sync_lock(tegra);
2600
2601         /* update maximum BW requirement to 0 */
2602         tegra_xusb_set_bw(tegra, 0);
2603
2604         /* This is SS partition ELPG entry
2605          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
2606          */
2607
2608         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
2609          * only if it is sw initiated one
2610          */
2611
2612         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
2613          * SuperSpeed partition ELPG entry via mailbox protocol
2614          */
2615
2616         /* STEP 2: xHCI PEP driver and XUSB device mode driver
2617          * enable the XUSB wakeup interrupts for the SuperSpeed
2618          * and USB2.0 ports assigned to host.Section 4.1 Step 3
2619          */
2620         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2621
2622         /* STEP 3: xHCI PEP driver initiates the signal sequence
2623          * to enable the XUSB SSwake detection logic for the
2624          * SuperSpeed ports assigned to host.Section 4.1 Step 4
2625          */
2626         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, true);
2627
2628         /* STEP 4: System Power Management driver asserts reset
2629          * to XUSB SuperSpeed partition then disables its clocks
2630          */
2631         tegra_periph_reset_assert(tegra->ss_clk);
2632         clk_disable(tegra->ss_clk);
2633
2634         usleep_range(100, 200);
2635
2636         /* STEP 5: System Power Management driver disables the
2637          * XUSB SuperSpeed partition power rails.
2638          */
2639         debug_print_portsc(xhci);
2640
2641         /* tegra_powergate_partition also does partition reset assert */
2642         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
2643         if (ret) {
2644                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
2645                                 __func__);
2646                 /* TODO: error recovery? */
2647         }
2648         tegra->ss_pwr_gated = true;
2649
2650         /* STEP 6: xHCI PEP driver initiates the signal sequence
2651          * to enable the XUSB SSwake detection logic for the
2652          * SuperSpeed ports assigned to host.Section 4.1 Step 7
2653          */
2654         tegra_xhci_ss_vcore(tegra->bdata->portmap, true);
2655
2656         return ret;
2657 }
2658
2659 /* Host ELPG Entry */
2660 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
2661 {
2662         struct xhci_hcd *xhci = tegra->xhci;
2663         u32 ret;
2664
2665         must_have_sync_lock(tegra);
2666
2667         /* If ss is already powergated skip ss ctx save stuff */
2668         if (tegra->ss_pwr_gated) {
2669                 xhci_info(xhci, "%s: SS partition is already powergated\n",
2670                         __func__);
2671         } else {
2672                 ret = tegra_xhci_ss_elpg_entry(tegra);
2673                 if (ret) {
2674                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
2675                                 __func__, ret);
2676                         return ret;
2677                 }
2678         }
2679
2680         /* 1. IS INTR PENDING INT_PENDING=1 ? */
2681
2682         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
2683         tegra_xhci_save_xusb_ctx(tegra);
2684
2685         /* calculate rctrl_val and tctrl_val */
2686         tegra_xhci_war_for_tctrl_rctrl(tegra);
2687
2688         pmc_setup_wake_detect(tegra);
2689
2690         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2691         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2692                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2693
2694         /* tegra_powergate_partition also does partition reset assert */
2695         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
2696         if (ret) {
2697                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2698                         __func__, ret);
2699                 /* TODO: error handling? */
2700                 return ret;
2701         }
2702         tegra->host_pwr_gated = true;
2703         clk_disable(tegra->host_clk);
2704
2705         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2706                 clk_disable(tegra->pll_re_vco_clk);
2707         clk_disable(tegra->emc_clk);
2708         /* set port ownership to SNPS */
2709         tegra_xhci_release_port_ownership(tegra, true);
2710
2711         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2712                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2713
2714         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
2715         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
2716                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
2717         return ret;
2718 }
2719
2720 /* SS ELPG Exit triggered by PADCTL irq */
2721 /**
2722  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
2723  *
2724  * This function must be called with tegra->sync_lock acquired.
2725  *
2726  * @tegra: xhci controller context
2727  * @return 0 for success, or error numbers
2728  */
2729 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2730 {
2731         struct xhci_hcd *xhci = tegra->xhci;
2732         int ret = 0;
2733
2734         must_have_sync_lock(tegra);
2735
2736         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
2737                         tegra->hs_wake_event || tegra->host_resume_req)) {
2738
2739                 /*
2740                  * PWR_UNGATE SS partition. XUSBA
2741                  * tegra_unpowergate_partition also does partition reset
2742                  * deassert
2743                  */
2744                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
2745                 if (ret) {
2746                         xhci_err(xhci,
2747                         "%s: could not unpowergate xusba partition %d\n",
2748                         __func__, ret);
2749                         goto out;
2750                 }
2751                 if (tegra->ss_wake_event)
2752                         tegra->ss_wake_event = false;
2753
2754         } else {
2755                 xhci_info(xhci, "%s: ss already power gated\n",
2756                         __func__);
2757                 return ret;
2758         }
2759
2760         /* Step 3: Enable clock to ss partition */
2761         clk_enable(tegra->ss_clk);
2762
2763         /* Step 4: Disable ss wake detection logic */
2764         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2765
2766         /* Step 4.1: Disable ss wake detection logic */
2767         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
2768
2769         /* wait 150us */
2770         usleep_range(150, 200);
2771
2772         /* Step 4.2: Disable ss wake detection logic */
2773         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
2774
2775         /* Step 6 Deassert reset for ss clks */
2776         tegra_periph_reset_deassert(tegra->ss_clk);
2777
2778         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
2779         tegra->ss_pwr_gated = false;
2780 out:
2781         return ret;
2782 }
2783
2784 static void ss_partition_elpg_exit_work(struct work_struct *work)
2785 {
2786         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2787                 ss_elpg_exit_work);
2788
2789         mutex_lock(&tegra->sync_lock);
2790         tegra_xhci_ss_partition_elpg_exit(tegra);
2791         mutex_unlock(&tegra->sync_lock);
2792 }
2793
2794 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
2795 static void update_remote_wakeup_ports(struct tegra_xhci_hcd *tegra)
2796 {
2797         struct xhci_hcd *xhci = tegra->xhci;
2798         u32 wake2_status;
2799         int port;
2800
2801 #define PMC_WAKE2_STATUS        0x168
2802 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
2803
2804         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
2805
2806         if (wake2_status & PADCTL_WAKE) {
2807                 /* FIXME: This is customized for Dalmore, find a generic way */
2808                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
2809                 /* clear wake status */
2810                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
2811         }
2812
2813         /* set all usb2 ports with RESUME link state as wakup ports  */
2814         for (port = 0; port < xhci->num_usb2_ports; port++) {
2815                 u32 portsc = xhci_readl(xhci, xhci->usb2_ports[port]);
2816                 if ((portsc & PORT_PLS_MASK) == XDEV_RESUME)
2817                         set_bit(port, &tegra->usb2_rh_remote_wakeup_ports);
2818         }
2819
2820         xhci_dbg(xhci, "%s: usb2 roothub remote_wakeup_ports 0x%lx\n",
2821                         __func__, tegra->usb2_rh_remote_wakeup_ports);
2822         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
2823                         __func__, tegra->usb3_rh_remote_wakeup_ports);
2824 }
2825
2826 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
2827 {
2828         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2829         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2830         int port, num_ports;
2831         unsigned long *remote_wakeup_ports;
2832         u32 portsc;
2833         __le32 __iomem  **port_array;
2834         unsigned char *rh;
2835         unsigned int retry = 64;
2836         struct xhci_bus_state *bus_state;
2837
2838         bus_state = &xhci->bus_state[hcd_index(hcd)];
2839
2840         if (hcd == xhci->shared_hcd) {
2841                 port_array = xhci->usb3_ports;
2842                 num_ports = xhci->num_usb3_ports;
2843                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
2844                 rh = "usb3 roothub";
2845         } else {
2846                 port_array = xhci->usb2_ports;
2847                 num_ports = xhci->num_usb2_ports;
2848                 remote_wakeup_ports = &tegra->usb2_rh_remote_wakeup_ports;
2849                 rh = "usb2 roothub";
2850         }
2851
2852         while (*remote_wakeup_ports && retry--) {
2853                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
2854                         bool can_continue;
2855
2856                         portsc = xhci_readl(xhci, port_array[port]);
2857
2858                         if (!(portsc & PORT_CONNECT)) {
2859                                 /* nothing to do if already disconnected */
2860                                 clear_bit(port, remote_wakeup_ports);
2861                                 continue;
2862                         }
2863
2864                         if (hcd == xhci->shared_hcd) {
2865                                 can_continue =
2866                                         (portsc & PORT_PLS_MASK) == XDEV_U0;
2867                         } else {
2868                                 unsigned long flags;
2869
2870                                 spin_lock_irqsave(&xhci->lock, flags);
2871                                 can_continue =
2872                                 test_bit(port, &bus_state->resuming_ports);
2873                                 spin_unlock_irqrestore(&xhci->lock, flags);
2874                         }
2875
2876                         if (can_continue)
2877                                 clear_bit(port, remote_wakeup_ports);
2878                         else
2879                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
2880                                         __func__, rh, port, portsc);
2881                 }
2882
2883                 if (*remote_wakeup_ports)
2884                         msleep(20); /* give some time, irq will direct U0 */
2885         }
2886
2887         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
2888                         *remote_wakeup_ports);
2889 }
2890
2891 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
2892 {
2893         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2894         u32 reg, utmip_rctrl_val, utmip_tctrl_val, pad_mux, portmux, portowner;
2895
2896         portmux = USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1);
2897         portowner = USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
2898                         USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2899
2900         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2901                 portmux |= USB2_OTG_PAD_PORT_MASK(2);
2902                 portowner |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2903         }
2904
2905         /* Use xusb padctl space only when xusb owns all UTMIP port */
2906         pad_mux = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2907         if ((pad_mux & portmux) == portowner) {
2908                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
2909                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
2910                  */
2911                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2912                 reg &= ~((1 << 12) | (1 << 13));
2913                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2914
2915                 /* wait 20us */
2916                 usleep_range(20, 30);
2917
2918                 /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
2919                  * :: TCTRL and RCTRL
2920                  */
2921                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl1_0);
2922                 utmip_rctrl_val = RCTRL(reg);
2923                 utmip_tctrl_val = TCTRL(reg);
2924
2925                 /*
2926                  * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
2927                  * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
2928                  */
2929                 utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
2930                 utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
2931                 utmi_phy_update_trking_data(utmip_tctrl_val, utmip_rctrl_val);
2932                 xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
2933                                         utmip_rctrl_val, utmip_tctrl_val);
2934
2935                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
2936                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
2937                  */
2938                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2939                 reg |= (1 << 13);
2940                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2941
2942                 /* Program these values into PMC regiseter and program the
2943                  * PMC override.
2944                  */
2945                 reg = PMC_TCTRL_VAL(utmip_tctrl_val) |
2946                                 PMC_RCTRL_VAL(utmip_rctrl_val);
2947                 tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG,
2948                                         0xffffffff, reg);
2949                 reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
2950                 tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
2951         } else {
2952                 /* Use common PMC API to use SNPS register space */
2953                 utmi_phy_set_snps_trking_data();
2954         }
2955 }
2956
2957 /* Host ELPG Exit triggered by PADCTL irq */
2958 /**
2959  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
2960  *
2961  * This function must be called with tegra->sync_lock acquired.
2962  *
2963  * @tegra: xhci controller context
2964  * @return 0 for success, or error numbers
2965  */
2966 static int
2967 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2968 {
2969         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2970         struct xhci_hcd *xhci = tegra->xhci;
2971         int ret = 0;
2972
2973         must_have_sync_lock(tegra);
2974
2975         if (!tegra->hc_in_elpg)
2976                 return 0;
2977
2978         clk_enable(tegra->emc_clk);
2979         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2980                 clk_enable(tegra->pll_re_vco_clk);
2981
2982         if (tegra->lp0_exit) {
2983                 u32 reg, oc_bits = 0;
2984
2985                 /* Issue is only applicable for T114 */
2986                 if (XUSB_DEVICE_ID_T114 == tegra->device_id)
2987                         tegra_xhci_war_for_tctrl_rctrl(tegra);
2988                 /* check if over current seen. Clear if present */
2989                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2990                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2991                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2992                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2993                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2994                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2995
2996                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2997                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
2998                 if (reg & oc_bits) {
2999                         xhci_info(xhci, "Over current detected. Clearing...\n");
3000                         writel(reg, tegra->padctl_base + padregs->oc_det_0);
3001
3002                         usleep_range(100, 200);
3003
3004                         reg = readl(tegra->padctl_base + padregs->oc_det_0);
3005                         if (reg & oc_bits)
3006                                 xhci_info(xhci, "Over current still present\n");
3007                 }
3008                 tegra_xhci_padctl_portmap_and_caps(tegra);
3009                 /* release clamps post deassert */
3010                 tegra->lp0_exit = false;
3011         }
3012
3013         /* Clear FLUSH_ENABLE of MC client */
3014         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
3015
3016         /* set port ownership back to xusb */
3017         tegra_xhci_release_port_ownership(tegra, false);
3018
3019         /*
3020          * PWR_UNGATE Host partition. XUSBC
3021          * tegra_unpowergate_partition also does partition reset deassert
3022          */
3023         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3024         if (ret) {
3025                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
3026                         __func__, ret);
3027                 goto out;
3028         }
3029         clk_enable(tegra->host_clk);
3030
3031         /* Step 4: Deassert reset to host partition clk */
3032         tegra_periph_reset_deassert(tegra->host_clk);
3033
3034         /* Step 6.1: IPFS and XUSB BAR initialization */
3035         tegra_xhci_cfg(tegra);
3036
3037         /* Step 6.2: IPFS and XUSB related restore */
3038         tegra_xhci_restore_ctx(tegra);
3039
3040         /* Step 8: xhci spec related ctx restore
3041          * will be done in xhci_resume().Do it here.
3042          */
3043
3044         tegra_xhci_ss_partition_elpg_exit(tegra);
3045
3046         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
3047         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
3048                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
3049                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
3050         }
3051
3052         /* clear ovrd bits */
3053         tegra_xhci_rx_idle_mode_override(tegra, false);
3054
3055         /* Load firmware */
3056         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
3057                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
3058                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
3059                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
3060                         __func__,
3061                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
3062                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
3063                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
3064                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
3065                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
3066                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
3067                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
3068                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
3069                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
3070         debug_print_portsc(xhci);
3071
3072         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
3073         if (ret < 0) {
3074                 xhci_err(xhci, "%s: failed to load firmware %d\n",
3075                         __func__, ret);
3076                 goto out;
3077         }
3078
3079         pmc_disable_bus_ctrl(tegra);
3080
3081         tegra->hc_in_elpg = false;
3082         ret = xhci_resume(tegra->xhci, 0);
3083         if (ret) {
3084                 xhci_err(xhci, "%s: could not resume right %d\n",
3085                                 __func__, ret);
3086                 goto out;
3087         }
3088
3089         update_remote_wakeup_ports(tegra);
3090
3091         if (tegra->hs_wake_event)
3092                 tegra->hs_wake_event = false;
3093
3094         if (tegra->host_resume_req)
3095                 tegra->host_resume_req = false;
3096
3097         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
3098                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
3099
3100         tegra->host_pwr_gated = false;
3101 out:
3102         return ret;
3103 }
3104
3105 static void host_partition_elpg_exit_work(struct work_struct *work)
3106 {
3107         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3108                 host_elpg_exit_work);
3109
3110         mutex_lock(&tegra->sync_lock);
3111         tegra_xhci_host_partition_elpg_exit(tegra);
3112         mutex_unlock(&tegra->sync_lock);
3113 }
3114
3115 /* Mailbox handling function. This function handles requests
3116  * from firmware and communicates with clock and powergating
3117  * module to alter clock rates and to power gate/ungate xusb
3118  * partitions.
3119  *
3120  * Following is the structure of mailbox messages.
3121  * bit 31:28 - msg type
3122  * bits 27:0 - mbox data
3123  * FIXME:  Check if we can just call clock functions like below
3124  * or should we schedule it for calling later ?
3125  */
3126
3127 static void
3128 tegra_xhci_process_mbox_message(struct work_struct *work)
3129 {
3130         u32 sw_resp = 0, cmd, data_in, fw_msg;
3131         int ret = 0;
3132         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3133                                         mbox_work);
3134         struct xhci_hcd *xhci = tegra->xhci;
3135         int pad, port;
3136         unsigned long ports;
3137         enum MBOX_CMD_TYPE response;
3138
3139         mutex_lock(&tegra->mbox_lock);
3140
3141         /* get the mbox message from firmware */
3142         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
3143
3144         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3145         if (data_in) {
3146                 dev_warn(&tegra->pdev->dev, "%s data_in 0x%x\n",
3147                         __func__, data_in);
3148                 mutex_unlock(&tegra->mbox_lock);
3149                 return;
3150         }
3151
3152         /* get cmd type and cmd data */
3153         tegra->cmd_type = (fw_msg >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
3154         tegra->cmd_data = (fw_msg >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
3155
3156         /* decode the message and make appropriate requests to
3157          * clock or powergating module.
3158          */
3159
3160         switch (tegra->cmd_type) {
3161         case MBOX_CMD_INC_FALC_CLOCK:
3162         case MBOX_CMD_DEC_FALC_CLOCK:
3163                 ret = tegra_xusb_request_clk_rate(
3164                                 tegra,
3165                                 tegra->falc_clk,
3166                                 tegra->cmd_data,
3167                                 &sw_resp);
3168                 if (ret)
3169                         xhci_err(xhci, "%s: could not set required falc rate\n",
3170                                 __func__);
3171                 goto send_sw_response;
3172         case MBOX_CMD_INC_SSPI_CLOCK:
3173         case MBOX_CMD_DEC_SSPI_CLOCK:
3174                 ret = tegra_xusb_request_clk_rate(
3175                                 tegra,
3176                                 tegra->ss_src_clk,
3177                                 tegra->cmd_data,
3178                                 &sw_resp);
3179                 if (ret)
3180                         xhci_err(xhci, "%s: could not set required ss rate.\n",
3181                                 __func__);
3182                 goto send_sw_response;
3183
3184         case MBOX_CMD_SET_BW:
3185                 /* fw sends BW request in MByte/sec */
3186                 mutex_lock(&tegra->sync_lock);
3187                 tegra_xusb_set_bw(tegra, tegra->cmd_data << 10);
3188                 mutex_unlock(&tegra->sync_lock);
3189                 break;
3190
3191         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
3192                 tegra_xhci_save_dfe_context(tegra, tegra->cmd_data);
3193                 tegra_xhci_save_ctle_context(tegra, tegra->cmd_data);
3194                 sw_resp = CMD_DATA(tegra->cmd_data) | CMD_TYPE(MBOX_CMD_ACK);
3195                 goto send_sw_response;
3196
3197         case MBOX_CMD_STAR_HSIC_IDLE:
3198                 ports = tegra->cmd_data;
3199                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3200                         pad = port_to_hsic_pad(port - 1);
3201                         mutex_lock(&tegra->sync_lock);
3202                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
3203                         mutex_unlock(&tegra->sync_lock);
3204                         if (ret)
3205                                 break;
3206                 }
3207
3208                 sw_resp = CMD_DATA(tegra->cmd_data);
3209                 if (!ret)
3210                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3211                 else
3212                         sw_resp |= CMD_TYPE(MBOX_CMD_NACK);
3213
3214                 goto send_sw_response;
3215
3216         case MBOX_CMD_STOP_HSIC_IDLE:
3217                 ports = tegra->cmd_data;
3218                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3219                         pad = port_to_hsic_pad(port - 1);
3220                         mutex_lock(&tegra->sync_lock);
3221                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_DISABLE);
3222                         mutex_unlock(&tegra->sync_lock);
3223                         if (ret)
3224                                 break;
3225                 }
3226
3227                 sw_resp = CMD_DATA(tegra->cmd_data);
3228                 if (!ret)
3229                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3230                 else
3231                         sw_resp |= CMD_TYPE(MBOX_CMD_NACK);
3232                 goto send_sw_response;
3233
3234         case MBOX_CMD_ACK:
3235                 xhci_dbg(xhci, "%s firmware responds with ACK\n", __func__);
3236                 break;
3237         case MBOX_CMD_NACK:
3238                 xhci_warn(xhci, "%s firmware responds with NACK\n", __func__);
3239                 break;
3240         default:
3241                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
3242                                 __func__, tegra->cmd_type);
3243         }
3244
3245         /* clear MBOX_SMI_INT_EN bit */
3246         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3247         cmd &= ~MBOX_SMI_INT_EN;
3248         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3249
3250         /* clear mailbox ownership */
3251         writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
3252
3253         mutex_unlock(&tegra->mbox_lock);
3254         return;
3255
3256 send_sw_response:
3257         response = (sw_resp >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
3258         if (response == MBOX_CMD_NACK)
3259                 xhci_warn(xhci, "%s respond fw message 0x%x with NACK\n",
3260                         __func__, fw_msg);
3261         else if (response == MBOX_CMD_ACK)
3262                 xhci_dbg(xhci, "%s respond fw message 0x%x with ACK\n",
3263                         __func__, fw_msg);
3264         else
3265                 xhci_err(xhci, "%s respond fw message 0x%x with %d\n",
3266                 __func__, fw_msg, response);
3267
3268         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3269         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3270         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
3271         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3272
3273         mutex_unlock(&tegra->mbox_lock);
3274 }
3275
3276 static irqreturn_t pmc_usb_phy_wake_isr(int irq, void *data)
3277 {
3278         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) data;
3279         struct xhci_hcd *xhci = tegra->xhci;
3280
3281         xhci_dbg(xhci, "%s irq %d", __func__, irq);
3282         return IRQ_HANDLED;
3283 }
3284
3285 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
3286 {
3287         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3288         struct xhci_hcd *xhci = tegra->xhci;
3289         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3290         u32 elpg_program0 = 0;
3291
3292         spin_lock(&tegra->lock);
3293
3294         tegra->last_jiffies = jiffies;
3295
3296         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
3297         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
3298
3299         /* Clear the interrupt cause. We already read the intr status. */
3300         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3301         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3302
3303         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
3304         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
3305                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
3306         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
3307                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
3308         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
3309                 __func__,
3310                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad0_ctl0_0));
3311         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
3312                 __func__,
3313                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad1_ctl0_0));
3314         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
3315                 __func__,
3316                 readl(tegra->padctl_base + padregs->usb2_bchrg_bias_pad_0));
3317
3318         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
3319                 tegra->ss_wake_event = true;
3320         else if (elpg_program0 & (USB2_PORT0_WAKEUP_EVENT |
3321                         USB2_PORT1_WAKEUP_EVENT |
3322                         USB2_PORT2_WAKEUP_EVENT |
3323                         USB2_HSIC_PORT0_WAKEUP_EVENT |
3324                         USB2_HSIC_PORT1_WAKEUP_EVENT))
3325                 tegra->hs_wake_event = true;
3326
3327         if (tegra->ss_wake_event || tegra->hs_wake_event) {
3328                 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
3329                         xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
3330                         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3331                 } else if (tegra->ss_pwr_gated
3332                                 && tegra->host_pwr_gated) {
3333                         xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
3334                                 __func__);
3335                         schedule_work(&tegra->host_elpg_exit_work);
3336                 }
3337         } else {
3338                 xhci_err(xhci, "error: wake due to no hs/ss event\n");
3339                 tegra_usb_pad_reg_write(padregs->elpg_program_0, 0xffffffff);
3340         }
3341         spin_unlock(&tegra->lock);
3342         return IRQ_HANDLED;
3343 }
3344
3345 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
3346 {
3347         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3348         u32 temp;
3349
3350         spin_lock(&tegra->lock);
3351
3352         /* clear the mbox intr status 1st thing. Other
3353          * bits are W1C bits, so just write to SMI bit.
3354          */
3355
3356         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3357
3358         /* write 1 to clear SMI INTR en bit ( bit 3 ) */
3359         temp = MBOX_SMI_INTR_EN;
3360         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3361
3362         schedule_work(&tegra->mbox_work);
3363
3364         spin_unlock(&tegra->lock);
3365         return IRQ_HANDLED;
3366 }
3367
3368 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
3369 {
3370         /*
3371          * As of now platform drivers don't provide MSI support so we ensure
3372          * here that the generic code does not try to make a pci_dev from our
3373          * dev struct in order to setup MSI
3374          */
3375         xhci->quirks |= XHCI_PLAT;
3376         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
3377 }
3378
3379 /* called during probe() after chip reset completes */
3380 static int xhci_plat_setup(struct usb_hcd *hcd)
3381 {
3382         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
3383 }
3384
3385 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
3386         int num, void __iomem **region)
3387 {
3388         struct resource *res;
3389         void __iomem *mem;
3390
3391         res = platform_get_resource(pdev, IORESOURCE_MEM, num);
3392         if (!res) {
3393                 dev_err(&pdev->dev, "memory resource %d doesn't exist\n", num);
3394                 return -ENODEV;
3395         }
3396
3397         mem = devm_request_and_ioremap(&pdev->dev, res);
3398         if (!mem) {
3399                 dev_err(&pdev->dev, "failed to ioremap for %d\n", num);
3400                 return -EFAULT;
3401         }
3402         *region = mem;
3403
3404         return 0;
3405 }
3406
3407 static int tegra_xhci_request_irq(struct platform_device *pdev,
3408         int num, irq_handler_t handler, unsigned long irqflags,
3409         const char *devname, int *irq_no)
3410 {
3411         int ret;
3412         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3413         struct resource *res;
3414
3415         res = platform_get_resource(pdev, IORESOURCE_IRQ, num);
3416         if (!res) {
3417                 dev_err(&pdev->dev, "irq resource %d doesn't exist\n", num);
3418                 return -ENODEV;
3419         }
3420
3421         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
3422                         devname, tegra);
3423         if (ret != 0) {
3424                 dev_err(&pdev->dev,
3425                         "failed to request_irq for %s (irq %d), error = %d\n",
3426                         devname, (int)res->start, ret);
3427                 return ret;
3428         }
3429         *irq_no = res->start;
3430
3431         return 0;
3432 }
3433
3434 #ifdef CONFIG_PM
3435
3436 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
3437 {
3438         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3439         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3440         int err = 0;
3441         unsigned long flags;
3442
3443         mutex_lock(&tegra->sync_lock);
3444
3445         if (xhci->shared_hcd == hcd) {
3446                 tegra->usb3_rh_suspend = true;
3447                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3448         } else if (xhci->main_hcd == hcd) {
3449                 tegra->usb2_rh_suspend = true;
3450                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3451         }
3452
3453         WARN_ON(tegra->hc_in_elpg);
3454
3455         /* suspend xhci bus. This will also set remote mask */
3456         err = xhci_bus_suspend(hcd);
3457         if (err) {
3458                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
3459                                 __func__, err);
3460                 goto xhci_bus_suspend_failed;
3461         }
3462
3463         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
3464                 goto done; /* one of the root hubs is still working */
3465
3466         spin_lock_irqsave(&tegra->lock, flags);
3467         tegra->hc_in_elpg = true;
3468         spin_unlock_irqrestore(&tegra->lock, flags);
3469
3470         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3471
3472         /* save xhci spec ctx. Already done by xhci_suspend */
3473         err = xhci_suspend(tegra->xhci);
3474         if (err) {
3475                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
3476                 goto xhci_suspend_failed;
3477         }
3478
3479         /* Powergate host. Include ss power gate if not already done */
3480         err = tegra_xhci_host_elpg_entry(tegra);
3481         if (err) {
3482                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
3483                                 __func__, err);
3484                 goto tegra_xhci_host_elpg_entry_failed;
3485         }
3486
3487         /* At this point,ensure ss/hs intr enables are always on */
3488         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
3489         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
3490
3491         /* In ELPG, firmware log context is gone. Rewind shared log buffer. */
3492         if (fw_log_wait_empty_timeout(tegra, 100))
3493                 xhci_warn(xhci, "%s still has logs\n", __func__);
3494         tegra->log.dequeue = tegra->log.virt_addr;
3495         tegra->log.seq = 0;
3496
3497 done:
3498         /* pads are disabled only if usb2 root hub in xusb is idle */
3499         /* pads will actually be disabled only when all usb2 ports are idle */
3500         if (xhci->main_hcd == hcd) {
3501                 utmi_phy_pad_disable();
3502                 utmi_phy_iddq_override(true);
3503         }
3504         mutex_unlock(&tegra->sync_lock);
3505         return 0;
3506
3507 tegra_xhci_host_elpg_entry_failed:
3508
3509 xhci_suspend_failed:
3510         tegra->hc_in_elpg = false;
3511 xhci_bus_suspend_failed:
3512         if (xhci->shared_hcd == hcd)
3513                 tegra->usb3_rh_suspend = false;
3514         else if (xhci->main_hcd == hcd)
3515                 tegra->usb2_rh_suspend = false;
3516
3517         mutex_unlock(&tegra->sync_lock);
3518         return err;
3519 }
3520
3521 /* First, USB2HCD and then USB3HCD resume will be called */
3522 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
3523 {
3524         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3525         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3526         int err = 0;
3527
3528         mutex_lock(&tegra->sync_lock);
3529
3530         tegra->host_resume_req = true;
3531
3532         if (xhci->shared_hcd == hcd)
3533                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3534         else if (xhci->main_hcd == hcd)
3535                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3536
3537         /* pads are disabled only if usb2 root hub in xusb is idle */
3538         /* pads will actually be disabled only when all usb2 ports are idle */
3539         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
3540                 utmi_phy_pad_enable();
3541                 utmi_phy_iddq_override(false);
3542         }
3543         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
3544                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
3545                         tegra_xhci_host_partition_elpg_exit(tegra);
3546         }
3547
3548          /* handle remote wakeup before resuming bus */
3549         wait_remote_wakeup_ports(hcd);
3550
3551         err = xhci_bus_resume(hcd);
3552         if (err) {
3553                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
3554                                 __func__, err);
3555                 goto xhci_bus_resume_failed;
3556         }
3557
3558         if (xhci->shared_hcd == hcd)
3559                 tegra->usb3_rh_suspend = false;
3560         else if (xhci->main_hcd == hcd)
3561                 tegra->usb2_rh_suspend = false;
3562
3563         mutex_unlock(&tegra->sync_lock);
3564         return 0;
3565
3566 xhci_bus_resume_failed:
3567         /* TODO: reverse elpg? */
3568         mutex_unlock(&tegra->sync_lock);
3569         return err;
3570 }
3571 #endif
3572
3573 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
3574 {
3575         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3576         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3577         irqreturn_t iret = IRQ_HANDLED;
3578         u32 status;
3579
3580         spin_lock(&tegra->lock);
3581         if (tegra->hc_in_elpg) {
3582                 spin_lock(&xhci->lock);
3583                 if (HCD_HW_ACCESSIBLE(hcd)) {
3584                         status = xhci_readl(xhci, &xhci->op_regs->status);
3585                         status |= STS_EINT;
3586                         xhci_writel(xhci, status, &xhci->op_regs->status);
3587                 }
3588                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
3589                                 __func__);
3590                 schedule_work(&tegra->host_elpg_exit_work);
3591                 spin_unlock(&xhci->lock);
3592         } else
3593                 iret = xhci_irq(hcd);
3594         spin_unlock(&tegra->lock);
3595
3596         wake_up_interruptible(&tegra->log.intr_wait);
3597
3598         return iret;
3599 }
3600
3601
3602 static const struct hc_driver tegra_plat_xhci_driver = {
3603         .description =          "tegra-xhci",
3604         .product_desc =         "Nvidia xHCI Host Controller",
3605         .hcd_priv_size =        sizeof(struct xhci_hcd *),
3606
3607         /*
3608          * generic hardware linkage
3609          */
3610         .irq =                  tegra_xhci_irq,
3611         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
3612
3613         /*
3614          * basic lifecycle operations
3615          */
3616         .reset =                xhci_plat_setup,
3617         .start =                xhci_run,
3618         .stop =                 xhci_stop,
3619         .shutdown =             xhci_shutdown,
3620
3621         /*
3622          * managing i/o requests and associated device resources
3623          */
3624         .urb_enqueue =          xhci_urb_enqueue,
3625         .urb_dequeue =          xhci_urb_dequeue,
3626         .alloc_dev =            xhci_alloc_dev,
3627         .free_dev =             xhci_free_dev,
3628         .alloc_streams =        xhci_alloc_streams,
3629         .free_streams =         xhci_free_streams,
3630         .add_endpoint =         xhci_add_endpoint,
3631         .drop_endpoint =        xhci_drop_endpoint,
3632         .endpoint_reset =       xhci_endpoint_reset,
3633         .check_bandwidth =      xhci_check_bandwidth,
3634         .reset_bandwidth =      xhci_reset_bandwidth,
3635         .address_device =       xhci_address_device,
3636         .update_hub_device =    xhci_update_hub_device,
3637         .reset_device =         xhci_discover_or_reset_device,
3638
3639         /*
3640          * scheduling support
3641          */
3642         .get_frame_number =     xhci_get_frame,
3643
3644         /* Root hub support */
3645         .hub_control =          xhci_hub_control,
3646         .hub_status_data =      xhci_hub_status_data,
3647
3648 #ifdef CONFIG_PM
3649         .bus_suspend =          tegra_xhci_bus_suspend,
3650         .bus_resume =           tegra_xhci_bus_resume,
3651 #endif
3652 };
3653
3654 #ifdef CONFIG_PM
3655 static int
3656 tegra_xhci_suspend(struct platform_device *pdev,
3657                                                 pm_message_t state)
3658 {
3659         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3660         struct xhci_hcd *xhci = tegra->xhci;
3661
3662         int ret = 0;
3663
3664         mutex_lock(&tegra->sync_lock);
3665         if (!tegra->init_done) {
3666                 xhci_warn(xhci, "%s: xhci probe not done\n",
3667                                 __func__);
3668                 mutex_unlock(&tegra->sync_lock);
3669                 return -EBUSY;
3670         }
3671         if (!tegra->hc_in_elpg) {
3672                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
3673                                 __func__);
3674                 mutex_unlock(&tegra->sync_lock);
3675                 return -EBUSY;
3676         }
3677         mutex_unlock(&tegra->sync_lock);
3678
3679         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3680         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3681
3682         /* enable_irq_wake for ss ports */
3683         ret = enable_irq_wake(tegra->padctl_irq);
3684         if (ret < 0) {
3685                 xhci_err(xhci,
3686                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
3687                 __func__, tegra->padctl_irq, ret);
3688         }
3689
3690         /* enable_irq_wake for utmip/uhisc wakes */
3691         ret = enable_irq_wake(tegra->usb3_irq);
3692         if (ret < 0) {
3693                 xhci_err(xhci,
3694                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3695                 __func__, tegra->usb3_irq, ret);
3696         }
3697
3698         /* enable_irq_wake for utmip/uhisc wakes */
3699         ret = enable_irq_wake(tegra->usb2_irq);
3700         if (ret < 0) {
3701                 xhci_err(xhci,
3702                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3703                 __func__, tegra->usb2_irq, ret);
3704         }
3705
3706         regulator_disable(tegra->xusb_s1p8v_reg);
3707         regulator_disable(tegra->xusb_s1p05v_reg);
3708         tegra_usb2_clocks_deinit(tegra);
3709
3710         return ret;
3711 }
3712
3713 static int
3714 tegra_xhci_resume(struct platform_device *pdev)
3715 {
3716         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3717         struct xhci_hcd *xhci = tegra->xhci;
3718
3719         dev_dbg(&pdev->dev, "%s\n", __func__);
3720
3721         mutex_lock(&tegra->sync_lock);
3722         if (!tegra->init_done) {
3723                 xhci_warn(xhci, "%s: xhci probe not done\n",
3724                                 __func__);
3725                 mutex_unlock(&tegra->sync_lock);
3726                 return -EBUSY;
3727         }
3728         mutex_unlock(&tegra->sync_lock);
3729
3730         tegra->last_jiffies = jiffies;
3731
3732         disable_irq_wake(tegra->padctl_irq);
3733         disable_irq_wake(tegra->usb3_irq);
3734         disable_irq_wake(tegra->usb2_irq);
3735         tegra->lp0_exit = true;
3736
3737         regulator_enable(tegra->xusb_s1p05v_reg);
3738         regulator_enable(tegra->xusb_s1p8v_reg);
3739         tegra_usb2_clocks_init(tegra);
3740
3741         return 0;
3742 }
3743 #endif
3744
3745 static int init_filesystem_firmware(struct tegra_xhci_hcd *tegra)
3746 {
3747         struct platform_device *pdev = tegra->pdev;
3748         int ret;
3749
3750         ret = request_firmware_nowait(THIS_MODULE, true, firmware_file,
3751                 &pdev->dev, GFP_KERNEL, tegra, init_filesystem_firmware_done);
3752         if (ret < 0) {
3753                 dev_err(&pdev->dev, "request_firmware failed %d\n", ret);
3754                 return ret;
3755         }
3756
3757         return ret;
3758 }
3759
3760 static void init_filesystem_firmware_done(const struct firmware *fw,
3761                                         void *context)
3762 {
3763         struct tegra_xhci_hcd *tegra = context;
3764         struct platform_device *pdev = tegra->pdev;
3765         struct cfgtbl *fw_cfgtbl;
3766         size_t fw_size;
3767         void *fw_data;
3768         dma_addr_t fw_dma;
3769         int ret;
3770
3771         mutex_lock(&tegra->sync_lock);
3772
3773         if (fw == NULL) {
3774                 dev_err(&pdev->dev,
3775                         "failed to init firmware from filesystem: %s\n",
3776                         firmware_file);
3777                 goto err_firmware_done;
3778         }
3779
3780         fw_cfgtbl = (struct cfgtbl *) fw->data;
3781         fw_size = fw_cfgtbl->fwimg_len;
3782         dev_info(&pdev->dev, "Firmware File: %s (%d Bytes)\n",
3783                         firmware_file, fw_size);
3784
3785         fw_data = dma_alloc_coherent(&pdev->dev, fw_size,
3786                         &fw_dma, GFP_KERNEL);
3787         if (!fw_data) {
3788                 dev_err(&pdev->dev, "%s: dma_alloc_coherent failed\n",
3789                         __func__);
3790                 goto err_firmware_done;
3791         }
3792
3793         memcpy(fw_data, fw->data, fw_size);
3794         dev_info(&pdev->dev,
3795                 "Firmware DMA Memory: dma 0x%p mapped 0x%p (%d Bytes)\n",
3796                 (void *) fw_dma, fw_data, fw_size);
3797
3798         /* all set and ready to go */
3799         tegra->firmware.data = fw_data;
3800         tegra->firmware.dma = fw_dma;
3801         tegra->firmware.size = fw_size;
3802
3803         ret = tegra_xhci_probe2(tegra);
3804         if (ret < 0) {
3805                 dev_err(&pdev->dev, "%s: failed to probe: %d\n", __func__, ret);
3806                 goto err_firmware_done;
3807         }
3808
3809         release_firmware(fw);
3810         mutex_unlock(&tegra->sync_lock);
3811         return;
3812
3813 err_firmware_done:
3814         release_firmware(fw);
3815         mutex_unlock(&tegra->sync_lock);
3816         device_release_driver(&pdev->dev);
3817 }
3818
3819 static void deinit_filesystem_firmware(struct tegra_xhci_hcd *tegra)
3820 {
3821         struct platform_device *pdev = tegra->pdev;
3822
3823         if (tegra->firmware.data) {
3824                 dma_free_coherent(&pdev->dev, tegra->firmware.size,
3825                         tegra->firmware.data, tegra->firmware.dma);
3826         }
3827
3828         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
3829 }
3830 static int init_firmware(struct tegra_xhci_hcd *tegra)
3831 {
3832         return init_filesystem_firmware(tegra);
3833 }
3834
3835 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
3836 {
3837         return deinit_filesystem_firmware(tegra);
3838 }
3839
3840 static int tegra_enable_xusb_clk(struct tegra_xhci_hcd *tegra,
3841                 struct platform_device *pdev)
3842 {
3843         int err = 0;
3844         /* enable ss clock */
3845         err = clk_enable(tegra->host_clk);
3846         if (err) {
3847                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
3848                 goto enable_host_clk_failed;
3849         }
3850
3851         err = clk_enable(tegra->ss_clk);
3852         if (err) {
3853                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
3854                 goto eanble_ss_clk_failed;
3855         }
3856
3857         err = clk_enable(tegra->emc_clk);
3858         if (err) {
3859                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
3860                 goto eanble_emc_clk_failed;
3861         }
3862
3863         return 0;
3864
3865 eanble_emc_clk_failed:
3866         clk_disable(tegra->ss_clk);
3867
3868 eanble_ss_clk_failed:
3869         clk_disable(tegra->host_clk);
3870
3871 enable_host_clk_failed:
3872         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
3873                 clk_disable(tegra->pll_re_vco_clk);
3874         return err;
3875 }
3876
3877 static struct tegra_xusb_padctl_regs t114_padregs_offset = {
3878         .boot_media_0                   = 0x0,
3879         .usb2_pad_mux_0                 = 0x4,
3880         .usb2_port_cap_0                = 0x8,
3881         .snps_oc_map_0                  = 0xc,
3882         .usb2_oc_map_0                  = 0x10,
3883         .ss_port_map_0                  = 0x14,
3884         .oc_det_0                       = 0x18,
3885         .elpg_program_0                 = 0x1c,
3886         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3887         .usb2_bchrg_otgpad0_ctl1_0      = 0xffff,
3888         .usb2_bchrg_otgpad1_ctl0_0      = 0x24,
3889         .usb2_bchrg_otgpad1_ctl1_0      = 0xffff,
3890         .usb2_bchrg_otgpad2_ctl0_0      = 0xffff,
3891         .usb2_bchrg_otgpad2_ctl1_0      = 0xffff,
3892         .usb2_bchrg_bias_pad_0          = 0x28,
3893         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
3894         .iophy_pll_p0_ctl1_0            = 0x30,
3895         .iophy_pll_p0_ctl2_0            = 0x34,
3896         .iophy_pll_p0_ctl3_0            = 0x38,
3897         .iophy_pll_p0_ctl4_0            = 0x3c,
3898         .iophy_usb3_pad0_ctl1_0         = 0x40,
3899         .iophy_usb3_pad1_ctl1_0         = 0x44,
3900         .iophy_usb3_pad0_ctl2_0         = 0x48,
3901         .iophy_usb3_pad1_ctl2_0         = 0x4c,
3902         .iophy_usb3_pad0_ctl3_0         = 0x50,
3903         .iophy_usb3_pad1_ctl3_0         = 0x54,
3904         .iophy_usb3_pad0_ctl4_0         = 0x58,
3905         .iophy_usb3_pad1_ctl4_0         = 0x5c,
3906         .iophy_misc_pad_p0_ctl1_0       = 0x60,
3907         .iophy_misc_pad_p1_ctl1_0       = 0x64,
3908         .iophy_misc_pad_p0_ctl2_0       = 0x68,
3909         .iophy_misc_pad_p1_ctl2_0       = 0x6c,
3910         .iophy_misc_pad_p0_ctl3_0       = 0x70,
3911         .iophy_misc_pad_p1_ctl3_0       = 0x74,
3912         .iophy_misc_pad_p0_ctl4_0       = 0x78,
3913         .iophy_misc_pad_p1_ctl4_0       = 0x7c,
3914         .iophy_misc_pad_p0_ctl5_0       = 0x80,
3915         .iophy_misc_pad_p1_ctl5_0       = 0x84,
3916         .iophy_misc_pad_p0_ctl6_0       = 0x88,
3917         .iophy_misc_pad_p1_ctl6_0       = 0x8c,
3918         .usb2_otg_pad0_ctl0_0           = 0x90,
3919         .usb2_otg_pad1_ctl0_0           = 0x94,
3920         .usb2_otg_pad2_ctl0_0           = 0xffff,
3921         .usb2_otg_pad0_ctl1_0           = 0x98,
3922         .usb2_otg_pad1_ctl1_0           = 0x9c,
3923         .usb2_otg_pad2_ctl1_0           = 0xffff,
3924         .usb2_bias_pad_ctl0_0           = 0xa0,
3925         .usb2_bias_pad_ctl1_0           = 0xa4,
3926         .usb2_hsic_pad0_ctl0_0          = 0xa8,
3927         .usb2_hsic_pad1_ctl0_0          = 0xac,
3928         .usb2_hsic_pad0_ctl1_0          = 0xb0,
3929         .usb2_hsic_pad1_ctl1_0          = 0xb4,
3930         .usb2_hsic_pad0_ctl2_0          = 0xb8,
3931         .usb2_hsic_pad1_ctl2_0          = 0xbc,
3932         .ulpi_link_trim_ctl0            = 0xc0,
3933         .ulpi_null_clk_trim_ctl0        = 0xc4,
3934         .hsic_strb_trim_ctl0            = 0xc8,
3935         .wake_ctl0                      = 0xcc,
3936         .pm_spare0                      = 0xd0,
3937         .iophy_misc_pad_p2_ctl1_0       = 0xffff,
3938         .iophy_misc_pad_p3_ctl1_0       = 0xffff,
3939         .iophy_misc_pad_p4_ctl1_0       = 0xffff,
3940         .iophy_misc_pad_p2_ctl2_0       = 0xffff,
3941         .iophy_misc_pad_p3_ctl2_0       = 0xffff,
3942         .iophy_misc_pad_p4_ctl2_0       = 0xffff,
3943         .iophy_misc_pad_p2_ctl3_0       = 0xffff,
3944         .iophy_misc_pad_p3_ctl3_0       = 0xffff,
3945         .iophy_misc_pad_p4_ctl3_0       = 0xffff,
3946         .iophy_misc_pad_p2_ctl4_0       = 0xffff,
3947         .iophy_misc_pad_p3_ctl4_0       = 0xffff,
3948         .iophy_misc_pad_p4_ctl4_0       = 0xffff,
3949         .iophy_misc_pad_p2_ctl5_0       = 0xffff,
3950         .iophy_misc_pad_p3_ctl5_0       = 0xffff,
3951         .iophy_misc_pad_p4_ctl5_0       = 0xffff,
3952         .iophy_misc_pad_p2_ctl6_0       = 0xffff,
3953         .iophy_misc_pad_p3_ctl6_0       = 0xffff,
3954         .iophy_misc_pad_p4_ctl6_0       = 0xffff,
3955         .usb3_pad_mux_0                 = 0xffff,
3956         .iophy_pll_s0_ctl1_0            = 0xffff,
3957         .iophy_pll_s0_ctl2_0            = 0xffff,
3958         .iophy_pll_s0_ctl3_0            = 0xffff,
3959         .iophy_pll_s0_ctl4_0            = 0xffff,
3960         .iophy_misc_pad_s0_ctl1_0       = 0xffff,
3961         .iophy_misc_pad_s0_ctl2_0       = 0xffff,
3962         .iophy_misc_pad_s0_ctl3_0       = 0xffff,
3963         .iophy_misc_pad_s0_ctl4_0       = 0xffff,
3964         .iophy_misc_pad_s0_ctl5_0       = 0xffff,
3965         .iophy_misc_pad_s0_ctl6_0       = 0xffff,
3966 };
3967
3968 static struct tegra_xusb_padctl_regs t124_padregs_offset = {
3969         .boot_media_0                   = 0x0,
3970         .usb2_pad_mux_0                 = 0x4,
3971         .usb2_port_cap_0                = 0x8,
3972         .snps_oc_map_0                  = 0xc,
3973         .usb2_oc_map_0                  = 0x10,
3974         .ss_port_map_0                  = 0x14,
3975         .oc_det_0                       = 0x18,
3976         .elpg_program_0                 = 0x1c,
3977         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3978         .usb2_bchrg_otgpad0_ctl1_0      = 0x24,
3979         .usb2_bchrg_otgpad1_ctl0_0      = 0x28,
3980         .usb2_bchrg_otgpad1_ctl1_0      = 0x2c,
3981         .usb2_bchrg_otgpad2_ctl0_0      = 0x30,
3982         .usb2_bchrg_otgpad2_ctl1_0      = 0x34,
3983         .usb2_bchrg_bias_pad_0          = 0x38,
3984         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
3985         .iophy_pll_p0_ctl1_0            = 0x40,
3986         .iophy_pll_p0_ctl2_0            = 0x44,
3987         .iophy_pll_p0_ctl3_0            = 0x48,
3988         .iophy_pll_p0_ctl4_0            = 0x4c,
3989         .iophy_usb3_pad0_ctl1_0         = 0x50,
3990         .iophy_usb3_pad1_ctl1_0         = 0x54,
3991         .iophy_usb3_pad0_ctl2_0         = 0x58,
3992         .iophy_usb3_pad1_ctl2_0         = 0x5c,
3993         .iophy_usb3_pad0_ctl3_0         = 0x60,
3994         .iophy_usb3_pad1_ctl3_0         = 0x64,
3995         .iophy_usb3_pad0_ctl4_0         = 0x68,
3996         .iophy_usb3_pad1_ctl4_0         = 0x6c,
3997         .iophy_misc_pad_p0_ctl1_0       = 0x70,
3998         .iophy_misc_pad_p1_ctl1_0       = 0x74,
3999         .iophy_misc_pad_p0_ctl2_0       = 0x78,
4000         .iophy_misc_pad_p1_ctl2_0       = 0x7c,
4001         .iophy_misc_pad_p0_ctl3_0       = 0x80,
4002         .iophy_misc_pad_p1_ctl3_0       = 0x84,
4003         .iophy_misc_pad_p0_ctl4_0       = 0x88,
4004         .iophy_misc_pad_p1_ctl4_0       = 0x8c,
4005         .iophy_misc_pad_p0_ctl5_0       = 0x90,
4006         .iophy_misc_pad_p1_ctl5_0       = 0x94,
4007         .iophy_misc_pad_p0_ctl6_0       = 0x98,
4008         .iophy_misc_pad_p1_ctl6_0       = 0x9c,
4009         .usb2_otg_pad0_ctl0_0           = 0xa0,
4010         .usb2_otg_pad1_ctl0_0           = 0xa4,
4011         .usb2_otg_pad2_ctl0_0           = 0xa8,
4012         .usb2_otg_pad0_ctl1_0           = 0xac,
4013         .usb2_otg_pad1_ctl1_0           = 0xb0,
4014         .usb2_otg_pad2_ctl1_0           = 0xb4,
4015         .usb2_bias_pad_ctl0_0           = 0xb8,
4016         .usb2_bias_pad_ctl1_0           = 0xbc,
4017         .usb2_hsic_pad0_ctl0_0          = 0xc0,
4018         .usb2_hsic_pad1_ctl0_0          = 0xc4,
4019         .usb2_hsic_pad0_ctl1_0          = 0xc8,
4020         .usb2_hsic_pad1_ctl1_0          = 0xcc,
4021         .usb2_hsic_pad0_ctl2_0          = 0xd0,
4022         .usb2_hsic_pad1_ctl2_0          = 0xd4,
4023         .ulpi_link_trim_ctl0            = 0xd8,
4024         .ulpi_null_clk_trim_ctl0        = 0xdc,
4025         .hsic_strb_trim_ctl0            = 0xe0,
4026         .wake_ctl0                      = 0xe4,
4027         .pm_spare0                      = 0xe8,
4028         .iophy_misc_pad_p2_ctl1_0       = 0xec,
4029         .iophy_misc_pad_p3_ctl1_0       = 0xf0,
4030         .iophy_misc_pad_p4_ctl1_0       = 0xf4,
4031         .iophy_misc_pad_p2_ctl2_0       = 0xf8,
4032         .iophy_misc_pad_p3_ctl2_0       = 0xfc,
4033         .iophy_misc_pad_p4_ctl2_0       = 0x100,
4034         .iophy_misc_pad_p2_ctl3_0       = 0x104,
4035         .iophy_misc_pad_p3_ctl3_0       = 0x108,
4036         .iophy_misc_pad_p4_ctl3_0       = 0x10c,
4037         .iophy_misc_pad_p2_ctl4_0       = 0x110,
4038         .iophy_misc_pad_p3_ctl4_0       = 0x114,
4039         .iophy_misc_pad_p4_ctl4_0       = 0x118,
4040         .iophy_misc_pad_p2_ctl5_0       = 0x11c,
4041         .iophy_misc_pad_p3_ctl5_0       = 0x120,
4042         .iophy_misc_pad_p4_ctl5_0       = 0x124,
4043         .iophy_misc_pad_p2_ctl6_0       = 0x128,
4044         .iophy_misc_pad_p3_ctl6_0       = 0x12c,
4045         .iophy_misc_pad_p4_ctl6_0       = 0x130,
4046         .usb3_pad_mux_0                 = 0x134,
4047         .iophy_pll_s0_ctl1_0            = 0x138,
4048         .iophy_pll_s0_ctl2_0            = 0x13c,
4049         .iophy_pll_s0_ctl3_0            = 0x140,
4050         .iophy_pll_s0_ctl4_0            = 0x144,
4051         .iophy_misc_pad_s0_ctl1_0       = 0x148,
4052         .iophy_misc_pad_s0_ctl2_0       = 0x14c,
4053         .iophy_misc_pad_s0_ctl3_0       = 0x150,
4054         .iophy_misc_pad_s0_ctl4_0       = 0x154,
4055         .iophy_misc_pad_s0_ctl5_0       = 0x158,
4056         .iophy_misc_pad_s0_ctl6_0       = 0x15c,
4057 };
4058
4059 /* FIXME: using notifier to transfer control to host from suspend
4060  * for otg port when xhci is in elpg. Find  better alternative
4061  */
4062 static int tegra_xhci_otg_notify(struct notifier_block *nb,
4063                                    unsigned long event, void *unused)
4064 {
4065         struct tegra_xhci_hcd *tegra = container_of(nb,
4066                                         struct tegra_xhci_hcd, otgnb);
4067
4068         if ((event == USB_EVENT_ID))
4069                 if (tegra->hc_in_elpg) {
4070                         schedule_work(&tegra->host_elpg_exit_work);
4071                         tegra->host_resume_req = true;
4072         }
4073
4074         return NOTIFY_OK;
4075 }
4076
4077 static void tegra_xusb_read_board_data(struct tegra_xhci_hcd *tegra)
4078 {
4079         struct tegra_xusb_board_data *bdata = tegra->bdata;
4080         struct device_node *node = tegra->pdev->dev.of_node;
4081         int ret;
4082
4083         bdata->uses_external_pmic = of_property_read_bool(node,
4084                                         "nvidia,uses_external_pmic");
4085         bdata->gpio_controls_muxed_ss_lanes = of_property_read_bool(node,
4086                                         "nvidia,gpio_controls_muxed_ss_lanes");
4087         ret = of_property_read_u32(node, "nvidia,gpio_ss1_sata",
4088                                         &bdata->gpio_ss1_sata);
4089         ret = of_property_read_u32(node, "nvidia,portmap",
4090                                         &bdata->portmap);
4091         ret = of_property_read_u32(node, "nvidia,ss_portmap",
4092                                         (u32 *) &bdata->ss_portmap);
4093         ret = of_property_read_u32(node, "nvidia,lane_owner",
4094                                         (u32 *) &bdata->lane_owner);
4095         ret = of_property_read_u32(node, "nvidia,ulpicap",
4096                                         (u32 *) &bdata->ulpicap);
4097         ret = of_property_read_string_index(node, "nvidia,supply_utmi_vbuses",
4098                                         0, &bdata->supply.utmi_vbuses[0]);
4099         ret = of_property_read_string_index(node, "nvidia,supply_utmi_vbuses",
4100                                         1, &bdata->supply.utmi_vbuses[1]);
4101         ret = of_property_read_string_index(node, "nvidia,supply_utmi_vbuses",
4102                                         2, &bdata->supply.utmi_vbuses[2]);
4103         ret = of_property_read_string(node, "nvidia,supply_s3p3v",
4104                                         &bdata->supply.s3p3v);
4105         ret = of_property_read_string(node, "nvidia,supply_s1p8v",
4106                                         &bdata->supply.s1p8v);
4107         ret = of_property_read_string(node, "nvidia,supply_vddio_hsic",
4108                                         &bdata->supply.vddio_hsic);
4109         ret = of_property_read_string(node, "nvidia,supply_s1p05v",
4110                                         &bdata->supply.s1p05v);
4111         ret = of_property_read_u8_array(node, "nvidia,hsic0",
4112                                         (u8 *) &bdata->hsic[0],
4113                                         sizeof(bdata->hsic[0]));
4114         ret = of_property_read_u8_array(node, "nvidia,hsic1",
4115                                         (u8 *) &bdata->hsic[1],
4116                                         sizeof(bdata->hsic[0]));
4117         /* TODO: Add error conditions check */
4118 }
4119
4120 static void tegra_xusb_read_calib_data(struct tegra_xhci_hcd *tegra)
4121 {
4122         u32 usb_calib0 = tegra_fuse_readl(FUSE_SKU_USB_CALIB_0);
4123         struct tegra_xusb_chip_calib *cdata = tegra->cdata;
4124
4125         pr_info("tegra_xusb_read_usb_calib: usb_calib0 = 0x%08x\n", usb_calib0);
4126         /*
4127          * read from usb_calib0 and pass to driver
4128          * set HS_CURR_LEVEL (PAD0)     = usb_calib0[5:0]
4129          * set TERM_RANGE_ADJ           = usb_calib0[10:7]
4130          * set HS_SQUELCH_LEVEL         = usb_calib0[12:11]
4131          * set HS_IREF_CAP              = usb_calib0[14:13]
4132          * set HS_CURR_LEVEL (PAD1)     = usb_calib0[20:15]
4133          */
4134
4135         cdata->hs_curr_level_pad0 = (usb_calib0 >> 0) & 0x3f;
4136         cdata->hs_term_range_adj = (usb_calib0 >> 7) & 0xf;
4137         cdata->hs_squelch_level = (usb_calib0 >> 11) & 0x3;
4138         cdata->hs_iref_cap = (usb_calib0 >> 13) & 0x3;
4139         cdata->hs_curr_level_pad1 = (usb_calib0 >> 15) & 0x3f;
4140         cdata->hs_curr_level_pad2 = (usb_calib0 >> 15) & 0x3f;
4141 }
4142
4143 static const struct tegra_xusb_soc_config tegra114_soc_config = {
4144         .pmc_portmap = (TEGRA_XUSB_UTMIP_PMC_PORT0 << 0) |
4145                         (TEGRA_XUSB_UTMIP_PMC_PORT2 << 4),
4146         .quirks = TEGRA_XUSB_USE_HS_SRC_CLOCK2,
4147         .rx_wander = (0x3 << 4),
4148         .rx_eq = (0x3928 << 8),
4149         .cdr_cntl = (0x26 << 24),
4150         .dfe_cntl = 0x002008EE,
4151         .hs_slew = (0xE << 6),
4152         .ls_rslew_pad0 = (0x3 << 14),
4153         .ls_rslew_pad1 = (0x0 << 14),
4154         .hs_disc_lvl = (0x5 << 2),
4155         .spare_in = 0x0,
4156 };
4157
4158 static const struct tegra_xusb_soc_config tegra124_soc_config = {
4159         .pmc_portmap = (TEGRA_XUSB_UTMIP_PMC_PORT0 << 0) |
4160                         (TEGRA_XUSB_UTMIP_PMC_PORT1 << 4) |
4161                         (TEGRA_XUSB_UTMIP_PMC_PORT2 << 8),
4162         .rx_wander = (0xF << 4),
4163         .rx_eq = (0xF070 << 8),
4164         .cdr_cntl = (0x26 << 24),
4165         .dfe_cntl = 0x002008EE,
4166         .hs_slew = (0xE << 6),
4167         .ls_rslew_pad0 = (0x3 << 14),
4168         .ls_rslew_pad1 = (0x0 << 14),
4169         .ls_rslew_pad2 = (0x0 << 14),
4170         .hs_disc_lvl = (0x5 << 2),
4171         .spare_in = 0x1,
4172 };
4173
4174 static struct of_device_id tegra_xhci_of_match[] = {
4175         { .compatible = "nvidia,tegra114-xhci", .data = &tegra114_soc_config },
4176         { .compatible = "nvidia,tegra124-xhci", .data = &tegra124_soc_config },
4177         { },
4178 };
4179
4180 static ssize_t hsic_power_show(struct device *dev,
4181                         struct kobj_attribute *attr, char *buf)
4182 {
4183         struct platform_device *pdev = to_platform_device(dev);
4184         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4185         int pad;
4186
4187         for_each_enabled_hsic_pad(pad, tegra) {
4188                 if (&tegra->hsic_power_attr[pad] == attr)
4189                         return sprintf(buf, "%d\n", pad);
4190         }
4191
4192         return sprintf(buf, "-1\n");
4193 }
4194
4195 static ssize_t hsic_power_store(struct device *dev,
4196                         struct kobj_attribute *attr, const char *buf, size_t n)
4197 {
4198         struct platform_device *pdev = to_platform_device(dev);
4199         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4200         enum MBOX_CMD_TYPE msg;
4201         unsigned int on;
4202         int pad, port;
4203         int ret;
4204
4205         if (sscanf(buf, "%u", &on) != 1)
4206                 return -EINVAL;
4207
4208         if (on)
4209                 msg = MBOX_CMD_AIRPLANE_MODE_DISABLED;
4210         else
4211                 msg = MBOX_CMD_AIRPLANE_MODE_ENABLED;
4212
4213         for_each_enabled_hsic_pad(pad, tegra) {
4214                 port = hsic_pad_to_port(pad);
4215
4216                 if (&tegra->hsic_power_attr[pad] == attr) {
4217                         hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
4218                         ret = fw_message_send(tegra, msg, BIT(port + 1));
4219                 }
4220         }
4221
4222         return n;
4223 }
4224
4225 static void hsic_power_remove_file(struct tegra_xhci_hcd *tegra)
4226 {
4227         struct device *dev = &tegra->pdev->dev;
4228         int p;
4229
4230         for_each_enabled_hsic_pad(p, tegra) {
4231                 if (attr_name(tegra->hsic_power_attr[p])) {
4232                         device_remove_file(dev, &tegra->hsic_power_attr[p]);
4233                         kzfree(attr_name(tegra->hsic_power_attr[p]));
4234                 }
4235         }
4236
4237 }
4238
4239 static int hsic_power_create_file(struct tegra_xhci_hcd *tegra)
4240 {
4241         struct device *dev = &tegra->pdev->dev;
4242         int p;
4243         int err;
4244
4245         for_each_enabled_hsic_pad(p, tegra) {
4246                 attr_name(tegra->hsic_power_attr[p]) = kzalloc(16, GFP_KERNEL);
4247                 if (!attr_name(tegra->hsic_power_attr[p]))
4248                         return -ENOMEM;
4249
4250                 snprintf(attr_name(tegra->hsic_power_attr[p]), 16,
4251                         "hsic%d_power", p);
4252                 tegra->hsic_power_attr[p].show = hsic_power_show;
4253                 tegra->hsic_power_attr[p].store = hsic_power_store;
4254                 tegra->hsic_power_attr[p].attr.mode = (S_IRUGO | S_IWUSR);
4255                 sysfs_attr_init(&tegra->hsic_power_attr[p]);
4256
4257                 err = device_create_file(dev, &tegra->hsic_power_attr[p]);
4258                 if (err) {
4259                         kzfree(attr_name(tegra->hsic_power_attr[p]));
4260                         attr_name(tegra->hsic_power_attr[p]) = 0;
4261                         return err;
4262                 }
4263         }
4264
4265         return 0;
4266 }
4267
4268 /* TODO: we have to refine error handling in tegra_xhci_probe() */
4269 static int tegra_xhci_probe(struct platform_device *pdev)
4270 {
4271         struct tegra_xhci_hcd *tegra;
4272         struct resource *res;
4273         unsigned pad;
4274         u32 val;
4275         int ret;
4276         int irq;
4277         const struct tegra_xusb_soc_config *soc_config;
4278         const struct of_device_id *match;
4279
4280         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
4281
4282         if (usb_disabled())
4283                 return -ENODEV;
4284
4285         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
4286         if (!tegra) {
4287                 dev_err(&pdev->dev, "memory alloc failed\n");
4288                 return -ENOMEM;
4289         }
4290         mutex_init(&tegra->sync_lock);
4291         spin_lock_init(&tegra->lock);
4292         mutex_init(&tegra->mbox_lock);
4293
4294         tegra->init_done = false;
4295
4296         tegra->bdata = devm_kzalloc(&pdev->dev, sizeof(
4297                                         struct tegra_xusb_board_data),
4298                                         GFP_KERNEL);
4299         if (!tegra->bdata) {
4300                 dev_err(&pdev->dev, "memory alloc failed\n");
4301                 return -ENOMEM;
4302         }
4303         tegra->cdata = devm_kzalloc(&pdev->dev, sizeof(
4304                                         struct tegra_xusb_chip_calib),
4305                                         GFP_KERNEL);
4306         if (!tegra->cdata) {
4307                 dev_err(&pdev->dev, "memory alloc failed\n");
4308                 return -ENOMEM;
4309         }
4310         match = of_match_device(tegra_xhci_of_match, &pdev->dev);
4311         if (!match) {
4312                 dev_err(&pdev->dev, "Error: No device match found\n");
4313                 return -ENODEV;
4314         }
4315         soc_config = match->data;
4316         /* Right now device-tree probed devices don't get dma_mask set.
4317          * Since shared usb code relies on it, set it here for now.
4318          * Once we have dma capability bindings this can go away.
4319          */
4320         tegra->tegra_xusb_dmamask = DMA_BIT_MASK(64);
4321         if (!pdev->dev.dma_mask)
4322                 pdev->dev.dma_mask = &tegra->tegra_xusb_dmamask;
4323
4324         tegra->pdev = pdev;
4325         tegra_xusb_read_calib_data(tegra);
4326         tegra_xusb_read_board_data(tegra);
4327         tegra->pdata = dev_get_platdata(&pdev->dev);
4328         tegra->bdata->portmap = tegra->pdata->portmap;
4329         tegra->bdata->hsic[0].pretend_connect =
4330                                 tegra->pdata->pretend_connect_0;
4331         if (tegra->bdata->portmap == NULL)
4332                 return -ENODEV;
4333         tegra->bdata->lane_owner = tegra->pdata->lane_owner;
4334         tegra->soc_config = soc_config;
4335         tegra->ss_pwr_gated = false;
4336         tegra->host_pwr_gated = false;
4337         tegra->hc_in_elpg = false;
4338         tegra->hs_wake_event = false;
4339         tegra->host_resume_req = false;
4340         tegra->lp0_exit = false;
4341
4342         /* request resource padctl base address */
4343         ret = tegra_xhci_request_mem_region(pdev, 3, &tegra->padctl_base);
4344         if (ret) {
4345                 dev_err(&pdev->dev, "failed to map padctl\n");
4346                 return ret;
4347         }
4348
4349         /* request resource fpci base address */
4350         ret = tegra_xhci_request_mem_region(pdev, 1, &tegra->fpci_base);
4351         if (ret) {
4352                 dev_err(&pdev->dev, "failed to map fpci\n");
4353                 return ret;
4354         }
4355
4356         /* request resource ipfs base address */
4357         ret = tegra_xhci_request_mem_region(pdev, 2, &tegra->ipfs_base);
4358         if (ret) {
4359                 dev_err(&pdev->dev, "failed to map ipfs\n");
4360                 return ret;
4361         }
4362
4363         ret = tegra_xusb_partitions_clk_init(tegra);
4364         if (ret) {
4365                 dev_err(&pdev->dev,
4366                         "failed to initialize xusb partitions clocks\n");
4367                 return ret;
4368         }
4369
4370         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) {
4371                 tegra->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
4372                 if (IS_ERR_OR_NULL(tegra->transceiver)) {
4373                         dev_err(&pdev->dev, "failed to get usb phy\n");
4374                         tegra->transceiver = NULL;
4375                 }
4376         }
4377
4378         /* Enable power rails to the PAD,VBUS
4379          * and pull-up voltage.Initialize the regulators
4380          */
4381         ret = tegra_xusb_regulator_init(tegra, pdev);
4382         if (ret) {
4383                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
4384                 if (ret == -ENODEV) {
4385                         ret = -EPROBE_DEFER;
4386                         dev_err(&pdev->dev, "Retry at a later stage\n");
4387                 }
4388                 goto err_deinit_xusb_partition_clk;
4389         }
4390
4391         /* Enable UTMIP, PLLU and PLLE */
4392         ret = tegra_usb2_clocks_init(tegra);
4393         if (ret) {
4394                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
4395                 goto err_deinit_tegra_xusb_regulator;
4396         }
4397
4398         /* tegra_unpowergate_partition also does partition reset deassert */
4399         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
4400         if (ret)
4401                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
4402
4403         /* tegra_unpowergate_partition also does partition reset deassert */
4404         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
4405         if (ret)
4406                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
4407
4408         ret = tegra_enable_xusb_clk(tegra, pdev);
4409         if (ret)
4410                 dev_err(&pdev->dev, "could not enable partition clock\n");
4411
4412         /* reset the pointer back to NULL. driver uses it */
4413         /* platform_set_drvdata(pdev, NULL); */
4414
4415         /* request resource host base address */
4416         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4417         if (!res) {
4418                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
4419                 ret = -ENODEV;
4420                 goto err_deinit_usb2_clocks;
4421         }
4422         tegra->host_phy_base = res->start;
4423         tegra->host_phy_size = resource_size(res);
4424
4425         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
4426                                 res->start, resource_size(res));
4427         if (!tegra->host_phy_virt_base) {
4428                 dev_err(&pdev->dev, "error mapping host phy memory\n");
4429                 ret = -ENOMEM;
4430                 goto err_deinit_usb2_clocks;
4431         }
4432
4433         /* Setup IPFS access and BAR0 space */
4434         tegra_xhci_cfg(tegra);
4435
4436         val = readl(tegra->fpci_base + XUSB_CFG_0);
4437         tegra->device_id = (val >> 16) & 0xffff;
4438
4439         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
4440                 (XUSB_DEVICE_ID_T114 == tegra->device_id) ? "T114" : "T124+");
4441
4442         if (XUSB_DEVICE_ID_T114 == tegra->device_id) {
4443                 tegra->padregs = &t114_padregs_offset;
4444         } else if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
4445                 tegra->padregs = &t124_padregs_offset;
4446         } else {
4447                 dev_info(&pdev->dev, "XUSB device_id neither T114 nor T124!\n");
4448                 dev_info(&pdev->dev, "XUSB using T124 pad register offsets!\n");
4449                 tegra->padregs = &t124_padregs_offset;
4450         }
4451
4452         /* calculate rctrl_val and tctrl_val once at boot time */
4453         /* Issue is only applicable for T114 */
4454         if (XUSB_DEVICE_ID_T114 == tegra->device_id)
4455                 tegra_xhci_war_for_tctrl_rctrl(tegra);
4456
4457         for_each_enabled_hsic_pad(pad, tegra)
4458                 hsic_power_rail_enable(tegra);
4459
4460         /* Program the XUSB pads to take ownership of ports */
4461         tegra_xhci_padctl_portmap_and_caps(tegra);
4462
4463         /* Release XUSB wake logic state latching */
4464         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
4465         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
4466
4467         /* Deassert reset to XUSB host, ss, dev clocks */
4468         tegra_periph_reset_deassert(tegra->host_clk);
4469         tegra_periph_reset_deassert(tegra->ss_clk);
4470
4471         platform_set_drvdata(pdev, tegra);
4472         fw_log_init(tegra);
4473         ret = init_firmware(tegra);
4474         if (ret < 0) {
4475                 dev_err(&pdev->dev, "failed to init firmware\n");
4476                 ret = -ENODEV;
4477                 goto err_deinit_firmware_log;
4478         }
4479
4480         return 0;
4481
4482 err_deinit_firmware_log:
4483         fw_log_deinit(tegra);
4484 err_deinit_usb2_clocks:
4485         tegra_usb2_clocks_deinit(tegra);
4486 err_deinit_tegra_xusb_regulator:
4487         tegra_xusb_regulator_deinit(tegra);
4488 err_deinit_xusb_partition_clk:
4489         if (tegra->transceiver)
4490                 usb_unregister_notifier(tegra->transceiver, &tegra->otgnb);
4491
4492         tegra_xusb_partitions_clk_deinit(tegra);
4493
4494         return ret;
4495 }
4496
4497 static int tegra_xhci_probe2(struct tegra_xhci_hcd *tegra)
4498 {
4499         struct platform_device *pdev = tegra->pdev;
4500         const struct hc_driver *driver;
4501         int ret;
4502         struct resource *res;
4503         int irq;
4504         struct xhci_hcd *xhci;
4505         struct usb_hcd  *hcd;
4506         unsigned port;
4507
4508
4509         ret = load_firmware(tegra, true /* do reset ARU */);
4510         if (ret < 0) {
4511                 dev_err(&pdev->dev, "failed to load firmware\n");
4512                 return -ENODEV;
4513         }
4514         pmc_init(tegra);
4515
4516         device_init_wakeup(&pdev->dev, 1);
4517         driver = &tegra_plat_xhci_driver;
4518
4519         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
4520         if (!hcd) {
4521                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
4522                 return -ENOMEM;
4523         }
4524
4525         /* request resource host base address */
4526         ret = tegra_xhci_request_mem_region(pdev, 0, &hcd->regs);
4527         if (ret) {
4528                 dev_err(&pdev->dev, "failed to map host\n");
4529                 goto err_put_usb2_hcd;
4530         }
4531         hcd->rsrc_start = tegra->host_phy_base;
4532         hcd->rsrc_len = tegra->host_phy_size;
4533
4534         /* Register interrupt handler for HOST */
4535         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
4536         if (!res) {
4537                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
4538                 ret = -ENODEV;
4539                 goto err_put_usb2_hcd;
4540         }
4541
4542         irq = res->start;
4543         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
4544         if (ret) {
4545                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
4546                 goto err_put_usb2_hcd;
4547         }
4548
4549         /* USB 2.0 roothub is stored in the platform_device now. */
4550         hcd = dev_get_drvdata(&pdev->dev);
4551         xhci = hcd_to_xhci(hcd);
4552         tegra->xhci = xhci;
4553         platform_set_drvdata(pdev, tegra);
4554
4555         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) {
4556                 if (!IS_ERR_OR_NULL(tegra->transceiver)) {
4557                         otg_set_host(tegra->transceiver->otg, &hcd->self);
4558                         tegra->otgnb.notifier_call = tegra_xhci_otg_notify;
4559                         usb_register_notifier(tegra->transceiver,
4560                                 &tegra->otgnb);
4561                 }
4562         }
4563
4564         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
4565                                                 dev_name(&pdev->dev), hcd);
4566         if (!xhci->shared_hcd) {
4567                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
4568                 ret = -ENOMEM;
4569                 goto err_remove_usb2_hcd;
4570         }
4571
4572         /*
4573          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
4574          * is called by usb_add_hcd().
4575          */
4576         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
4577
4578         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
4579         if (ret) {
4580                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
4581                 goto err_put_usb3_hcd;
4582         }
4583
4584         device_init_wakeup(&hcd->self.root_hub->dev, 1);
4585         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
4586
4587         /* do mailbox related initializations */
4588         tegra->mbox_owner = 0xffff;
4589         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
4590
4591         tegra_xhci_enable_fw_message(tegra);
4592
4593         /* do ss partition elpg exit related initialization */
4594         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
4595
4596         /* do host partition elpg exit related initialization */
4597         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
4598
4599         /* Register interrupt handler for SMI line to handle mailbox
4600          * interrupt from firmware
4601          */
4602
4603         ret = tegra_xhci_request_irq(pdev, 1, tegra_xhci_smi_irq,
4604                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
4605         if (ret != 0)
4606                 goto err_remove_usb3_hcd;
4607
4608         /* Register interrupt handler for PADCTRL line to
4609          * handle wake on connect irqs interrupt from
4610          * firmware
4611          */
4612         ret = tegra_xhci_request_irq(pdev, 2, tegra_xhci_padctl_irq,
4613                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
4614                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
4615         if (ret != 0)
4616                 goto err_remove_usb3_hcd;
4617
4618         /* Register interrupt wake handler for USB2 */
4619         ret = tegra_xhci_request_irq(pdev, 4, pmc_usb_phy_wake_isr,
4620                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4621                 &tegra->usb2_irq);
4622         if (ret != 0)
4623                 goto err_remove_usb3_hcd;
4624
4625         /* Register interrupt wake handler for USB3 */
4626         ret = tegra_xhci_request_irq(pdev, 3, pmc_usb_phy_wake_isr,
4627                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4628                 &tegra->usb3_irq);
4629         if (ret != 0)
4630                 goto err_remove_usb3_hcd;
4631
4632         for (port = 0; port < XUSB_SS_PORT_COUNT; port++) {
4633                 tegra->ctle_ctx_saved[port] = false;
4634                 tegra->dfe_ctx_saved[port] = false;
4635         }
4636
4637         hsic_pad_pretend_connect(tegra);
4638
4639         tegra_xhci_debug_read_pads(tegra);
4640         utmi_phy_pad_enable();
4641         utmi_phy_iddq_override(false);
4642
4643         tegra_pd_add_device(&pdev->dev);
4644         pm_runtime_enable(&pdev->dev);
4645
4646         hsic_power_create_file(tegra);
4647         tegra->init_done = true;
4648
4649         return 0;
4650
4651 err_remove_usb3_hcd:
4652         usb_remove_hcd(xhci->shared_hcd);
4653 err_put_usb3_hcd:
4654         usb_put_hcd(xhci->shared_hcd);
4655 err_remove_usb2_hcd:
4656         kfree(tegra->xhci);
4657         usb_remove_hcd(hcd);
4658 err_put_usb2_hcd:
4659         usb_put_hcd(hcd);
4660
4661         return ret;
4662 }
4663
4664 static int tegra_xhci_remove(struct platform_device *pdev)
4665 {
4666         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4667         unsigned pad;
4668
4669         if (tegra == NULL)
4670                 return -EINVAL;
4671
4672         mutex_lock(&tegra->sync_lock);
4673
4674         for_each_enabled_hsic_pad(pad, tegra) {
4675                 hsic_pad_disable(tegra, pad);
4676                 hsic_power_rail_disable(tegra);
4677         }
4678
4679         if (tegra->init_done) {
4680                 struct xhci_hcd *xhci = NULL;
4681                 struct usb_hcd *hcd = NULL;
4682
4683                 xhci = tegra->xhci;
4684                 hcd = xhci_to_hcd(xhci);
4685
4686                 devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
4687                 devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
4688                 devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
4689                 usb_remove_hcd(xhci->shared_hcd);
4690                 usb_put_hcd(xhci->shared_hcd);
4691                 usb_remove_hcd(hcd);
4692                 usb_put_hcd(hcd);
4693                 kfree(xhci);
4694         }
4695
4696         deinit_firmware(tegra);
4697         fw_log_deinit(tegra);
4698
4699         tegra_xusb_regulator_deinit(tegra);
4700
4701         if (tegra->transceiver)
4702                 usb_unregister_notifier(tegra->transceiver, &tegra->otgnb);
4703
4704         tegra_usb2_clocks_deinit(tegra);
4705         if (!tegra->hc_in_elpg)
4706                 tegra_xusb_partitions_clk_deinit(tegra);
4707
4708         utmi_phy_pad_disable();
4709         utmi_phy_iddq_override(true);
4710
4711         tegra_pd_remove_device(&pdev->dev);
4712         platform_set_drvdata(pdev, NULL);
4713
4714         hsic_power_remove_file(tegra);
4715         mutex_unlock(&tegra->sync_lock);
4716
4717         return 0;
4718 }
4719
4720 static void tegra_xhci_shutdown(struct platform_device *pdev)
4721 {
4722         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4723         struct xhci_hcd *xhci = NULL;
4724         struct usb_hcd *hcd = NULL;
4725
4726         if (tegra == NULL)
4727                 return;
4728
4729         if (tegra->hc_in_elpg) {
4730                 pmc_disable_bus_ctrl(tegra);
4731         } else {
4732                 xhci = tegra->xhci;
4733                 hcd = xhci_to_hcd(xhci);
4734                 xhci_shutdown(hcd);
4735         }
4736 }
4737
4738 static struct platform_driver tegra_xhci_driver = {
4739         .probe  = tegra_xhci_probe,
4740         .remove = tegra_xhci_remove,
4741         .shutdown = tegra_xhci_shutdown,
4742 #ifdef CONFIG_PM
4743         .suspend = tegra_xhci_suspend,
4744         .resume  = tegra_xhci_resume,
4745 #endif
4746         .driver = {
4747                 .name = "tegra-xhci",
4748                 .of_match_table = tegra_xhci_of_match,
4749         },
4750 };
4751 MODULE_ALIAS("platform:tegra-xhci");
4752
4753 int tegra_xhci_register_plat(void)
4754 {
4755         return platform_driver_register(&tegra_xhci_driver);
4756 }
4757
4758 void tegra_xhci_unregister_plat(void)
4759 {
4760         platform_driver_unregister(&tegra_xhci_driver);
4761 }