usb: xhci: tegra: program lane owner for usb3_ss port
[linux-3.10.git] / drivers / usb / host / xhci-tegra.c
1 /*
2  * xhci-tegra.c - Nvidia xHCI host controller driver
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/clk.h>
24 #include <linux/ioport.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irq.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/uaccess.h>
30
31 #include <mach/powergate.h>
32 #include <mach/clk.h>
33 #include <mach/tegra_usb_pad_ctrl.h>
34 #include <mach/tegra_usb_pmc.h>
35 #include <mach/pm_domains.h>
36 #include <mach/mc.h>
37 #include <mach/xusb.h>
38
39 #include "../../../arch/arm/mach-tegra/iomap.h" /* HACK -- remove */
40 #include "xhci-tegra.h"
41 #include "xhci.h"
42
43 /* macros */
44 #define PAGE_SELECT_MASK                        0xFFFFFE00
45 #define PAGE_SELECT_SHIFT                       9
46 #define PAGE_OFFSET_MASK                        0x000001FF
47 #define CSB_PAGE_SELECT(_addr)                                          \
48         ({                                                              \
49                 typecheck(u32, _addr);                                  \
50                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
51         })
52 #define CSB_PAGE_OFFSET(_addr)                                          \
53         ({                                                              \
54                 typecheck(u32, _addr);                                  \
55                 (_addr & PAGE_OFFSET_MASK);                             \
56         })
57
58 /* PMC register definition */
59 #define PMC_PORT_UTMIP_P0               0
60 #define PMC_PORT_UTMIP_P1               1
61 #define PMC_PORT_UTMIP_P2               2
62 #define PMC_PORT_UHSIC_P0               3
63 #define PMC_PORT_NUM                    4
64
65 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
66 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
67 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
68
69 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
70
71 /* private data types */
72 /* command requests from the firmware */
73 enum MBOX_CMD_TYPE {
74         MBOX_CMD_MSG_ENABLED = 1,
75         MBOX_CMD_INC_FALC_CLOCK,
76         MBOX_CMD_DEC_FALC_CLOCK,
77         MBOX_CMD_INC_SSPI_CLOCK,
78         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
79         MBOX_CMD_SET_BW,
80         MBOX_CMD_SET_SS_PWR_GATING,
81         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
82         MBOX_CMD_SAVE_DFE_CTLE_CTX,
83
84         /* needs to be the last cmd */
85         MBOX_CMD_MAX,
86
87         /* resp msg to ack above commands */
88         MBOX_CMD_ACK = 128,
89         MBOX_CMD_NACK
90 };
91
92 /* Usb3 Firmware Cfg Table */
93 struct cfgtbl {
94         u32 boot_loadaddr_in_imem;
95         u32 boot_codedfi_offset;
96         u32 boot_codetag;
97         u32 boot_codesize;
98
99         /* Physical memory reserved by Bootloader/BIOS */
100         u32 phys_memaddr;
101         u16 reqphys_memsize;
102         u16 alloc_phys_memsize;
103
104         /* .rodata section */
105         u32 rodata_img_offset;
106         u32 rodata_section_start;
107         u32 rodata_section_end;
108         u32 main_fnaddr;
109
110         u32 fwimg_cksum;
111         u32 fwimg_created_time;
112
113         /* Fields that get filled by linker during linking phase
114          * or initialized in the FW code.
115          */
116         u32 imem_resident_start;
117         u32 imem_resident_end;
118         u32 idirect_start;
119         u32 idirect_end;
120         u32 l2_imem_start;
121         u32 l2_imem_end;
122         u32 version_id;
123         u8 init_ddirect;
124         u8 reserved[3];
125         u32 phys_addr_log_buffer;
126         u32 total_log_entries;
127         u32 dequeue_ptr;
128
129         /*      Below two dummy variables are used to replace
130          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
131          *      retain the size of struct _CFG_TBL used by other AP/Module.
132          */
133         u32 dummy_var1;
134         u32 dummy_var2;
135
136         /* fwimg_len */
137         u32 fwimg_len;
138         u8 magic[8];
139         u32 SS_low_power_entry_timeout;
140         u8 padding[140]; /* padding bytes to makeup 256-bytes cfgtbl */
141 };
142
143 struct xusb_save_regs {
144         u32 msi_bar_sz;
145         u32 msi_axi_barst;
146         u32 msi_fpci_barst;
147         u32 msi_vec0;
148         u32 msi_en_vec0;
149         u32 fpci_error_masks;
150         u32 intr_mask;
151         u32 ipfs_intr_enable;
152         u32 ufpci_config;
153         u32 clkgate_hysteresis;
154         u32 xusb_host_mccif_fifo_cntrl;
155
156         /* PG does not mention below */
157         u32 hs_pls;
158         u32 fs_pls;
159         u32 hs_fs_speed;
160         u32 hs_fs_pp;
161         u32 cfg_aru;
162         u32 cfg_order;
163         u32 cfg_fladj;
164         u32 cfg_sid;
165         /* DFE and CTLE */
166         u32 tap1_val[2];
167         u32 amp_val[2];
168         u32 ctle_z_val[2];
169         u32 ctle_g_val[2];
170 };
171
172 struct tegra_xhci_firmware {
173         void *data; /* kernel virtual address */
174         size_t size; /* firmware size */
175         dma_addr_t dma; /* dma address for controller */
176 };
177
178 /* structure to hold the offsets of padctl registers */
179 struct tegra_xusb_padctl_regs {
180         u16 boot_media_0;
181         u16 usb2_pad_mux_0;
182         u16 usb2_port_cap_0;
183         u16 snps_oc_map_0;
184         u16 usb2_oc_map_0;
185         u16 ss_port_map_0;
186         u16 oc_det_0;
187         u16 elpg_program_0;
188         u16 usb2_bchrg_otgpad0_ctl0_0;
189         u16 usb2_bchrg_otgpad0_ctl1_0;
190         u16 usb2_bchrg_otgpad1_ctl0_0;
191         u16 usb2_bchrg_otgpad1_ctl1_0;
192         u16 usb2_bchrg_otgpad2_ctl0_0;
193         u16 usb2_bchrg_otgpad2_ctl1_0;
194         u16 usb2_bchrg_bias_pad_0;
195         u16 usb2_bchrg_tdcd_dbnc_timer_0;
196         u16 iophy_pll_p0_ctl1_0;
197         u16 iophy_pll_p0_ctl2_0;
198         u16 iophy_pll_p0_ctl3_0;
199         u16 iophy_pll_p0_ctl4_0;
200         u16 iophy_usb3_pad0_ctl1_0;
201         u16 iophy_usb3_pad1_ctl1_0;
202         u16 iophy_usb3_pad0_ctl2_0;
203         u16 iophy_usb3_pad1_ctl2_0;
204         u16 iophy_usb3_pad0_ctl3_0;
205         u16 iophy_usb3_pad1_ctl3_0;
206         u16 iophy_usb3_pad0_ctl4_0;
207         u16 iophy_usb3_pad1_ctl4_0;
208         u16 iophy_misc_pad_p0_ctl1_0;
209         u16 iophy_misc_pad_p1_ctl1_0;
210         u16 iophy_misc_pad_p0_ctl2_0;
211         u16 iophy_misc_pad_p1_ctl2_0;
212         u16 iophy_misc_pad_p0_ctl3_0;
213         u16 iophy_misc_pad_p1_ctl3_0;
214         u16 iophy_misc_pad_p0_ctl4_0;
215         u16 iophy_misc_pad_p1_ctl4_0;
216         u16 iophy_misc_pad_p0_ctl5_0;
217         u16 iophy_misc_pad_p1_ctl5_0;
218         u16 iophy_misc_pad_p0_ctl6_0;
219         u16 iophy_misc_pad_p1_ctl6_0;
220         u16 usb2_otg_pad0_ctl0_0;
221         u16 usb2_otg_pad1_ctl0_0;
222         u16 usb2_otg_pad2_ctl0_0;
223         u16 usb2_otg_pad0_ctl1_0;
224         u16 usb2_otg_pad1_ctl1_0;
225         u16 usb2_otg_pad2_ctl1_0;
226         u16 usb2_bias_pad_ctl0_0;
227         u16 usb2_bias_pad_ctl1_0;
228         u16 usb2_hsic_pad0_ctl0_0;
229         u16 usb2_hsic_pad1_ctl0_0;
230         u16 usb2_hsic_pad0_ctl1_0;
231         u16 usb2_hsic_pad1_ctl1_0;
232         u16 usb2_hsic_pad0_ctl2_0;
233         u16 usb2_hsic_pad1_ctl2_0;
234         u16 ulpi_link_trim_ctl0;
235         u16 ulpi_null_clk_trim_ctl0;
236         u16 hsic_strb_trim_ctl0;
237         u16 wake_ctl0;
238         u16 pm_spare0;
239         u16 iophy_misc_pad_p2_ctl1_0;
240         u16 iophy_misc_pad_p3_ctl1_0;
241         u16 iophy_misc_pad_p4_ctl1_0;
242         u16 iophy_misc_pad_p2_ctl2_0;
243         u16 iophy_misc_pad_p3_ctl2_0;
244         u16 iophy_misc_pad_p4_ctl2_0;
245         u16 iophy_misc_pad_p2_ctl3_0;
246         u16 iophy_misc_pad_p3_ctl3_0;
247         u16 iophy_misc_pad_p4_ctl3_0;
248         u16 iophy_misc_pad_p2_ctl4_0;
249         u16 iophy_misc_pad_p3_ctl4_0;
250         u16 iophy_misc_pad_p4_ctl4_0;
251         u16 iophy_misc_pad_p2_ctl5_0;
252         u16 iophy_misc_pad_p3_ctl5_0;
253         u16 iophy_misc_pad_p4_ctl5_0;
254         u16 iophy_misc_pad_p2_ctl6_0;
255         u16 iophy_misc_pad_p3_ctl6_0;
256         u16 iophy_misc_pad_p4_ctl6_0;
257         u16 usb3_pad_mux_0;
258         u16 iophy_pll_s0_ctl1_0;
259         u16 iophy_pll_s0_ctl2_0;
260         u16 iophy_pll_s0_ctl3_0;
261         u16 iophy_pll_s0_ctl4_0;
262         u16 iophy_misc_pad_s0_ctl1_0;
263         u16 iophy_misc_pad_s0_ctl2_0;
264         u16 iophy_misc_pad_s0_ctl3_0;
265         u16 iophy_misc_pad_s0_ctl4_0;
266         u16 iophy_misc_pad_s0_ctl5_0;
267         u16 iophy_misc_pad_s0_ctl6_0;
268 };
269
270 struct tegra_xhci_hcd {
271         struct platform_device *pdev;
272         struct xhci_hcd *xhci;
273         u16 device_id;
274
275         spinlock_t lock;
276         struct mutex sync_lock;
277
278         int smi_irq;
279         int padctl_irq;
280         int usb3_irq;
281
282         bool ss_wake_event;
283         bool ss_pwr_gated;
284         bool host_pwr_gated;
285         bool hs_wake_event;
286         bool host_resume_req;
287         bool lp0_exit;
288         bool dfe_ctle_ctx_saved;
289         unsigned long last_jiffies;
290         unsigned long host_phy_base;
291         void __iomem *host_phy_virt_base;
292
293         void __iomem *padctl_base;
294         void __iomem *fpci_base;
295         void __iomem *ipfs_base;
296
297         struct tegra_xusb_platform_data *pdata;
298         struct tegra_xusb_board_data *bdata;
299         struct tegra_xusb_padctl_regs *padregs;
300
301         /* mailbox variables */
302         struct mutex mbox_lock;
303         u32 mbox_owner;
304         u32 cmd_type;
305         u32 cmd_data;
306
307         struct regulator *xusb_vbus_reg;
308         struct regulator *xusb_avddio_usb3_reg;
309         struct regulator *xusb_hvdd_usb3_reg;
310         struct regulator *xusb_avdd_usb3_pll_reg;
311
312         struct work_struct mbox_work;
313         struct work_struct ss_elpg_exit_work;
314         struct work_struct host_elpg_exit_work;
315
316         struct clk *host_clk;
317         struct clk *ss_clk;
318
319         /* XUSB Falcon SuperSpeed Clock */
320         struct clk *falc_clk;
321
322         /* EMC Clock */
323         struct clk *emc_clk;
324         /* XUSB SS PI Clock */
325         struct clk *ss_src_clk;
326         /* PLLE Clock */
327         struct clk *plle_clk;
328         struct clk *pll_u_480M;
329         struct clk *clk_m;
330         /* refPLLE clk */
331         struct clk *pll_re_vco_clk;
332         /*
333          * XUSB/IPFS specific registers these need to be saved/restored in
334          * addition to spec defined registers
335          */
336         struct xusb_save_regs sregs;
337         bool usb2_rh_suspend;
338         bool usb3_rh_suspend;
339         bool hc_in_elpg;
340
341         unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
342         /* firmware loading related */
343         struct tegra_xhci_firmware firmware;
344 };
345
346 static struct tegra_usb_pmc_data pmc_data;
347
348 /* functions */
349 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
350 {
351         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
352 }
353
354 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
355 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
356 {
357         WARN_ON(tegra->sync_lock.owner != current);
358 }
359 #else
360 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
361 #endif
362
363 static bool is_any_hs_connected(struct xhci_hcd *xhci)
364 {
365         __le32 __iomem *addr;
366         int i;
367         int ports;
368         u32 portsc;
369
370         ports = HCS_MAX_PORTS(xhci->hcs_params1);
371         addr = &xhci->op_regs->port_status_base;
372         for (i = 0; i < ports; i++) {
373                 portsc = xhci_readl(xhci, addr);
374                 if ((portsc & PORT_CONNECT) && DEV_HIGHSPEED(portsc))
375                         return true;
376                 addr += NUM_PORT_REGS;
377         }
378         return false;
379 }
380
381 static void debug_print_portsc(struct xhci_hcd *xhci)
382 {
383         __le32 __iomem *addr;
384         int i;
385         int ports;
386
387         ports = HCS_MAX_PORTS(xhci->hcs_params1);
388         addr = &xhci->op_regs->port_status_base;
389         for (i = 0; i < ports; i++) {
390                 xhci_dbg(xhci, "%p port %d status reg = 0x%x\n",
391                                 addr, i, (unsigned int) xhci_readl(xhci, addr));
392                 addr += NUM_PORT_REGS;
393         }
394 }
395
396 static void update_speed(struct tegra_xhci_hcd *tegra, u8 port)
397 {
398         struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
399         u32 portsc;
400
401         portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port +
402                                                 BAR0_XHCI_OP_PORTSC_UTMIP_0));
403         if (DEV_FULLSPEED(portsc))
404                 pmc_data.port_speed = USB_PMC_PORT_SPEED_FULL;
405         else if (DEV_HIGHSPEED(portsc))
406                 pmc_data.port_speed = USB_PMC_PORT_SPEED_HIGH;
407         else if (DEV_LOWSPEED(portsc))
408                 pmc_data.port_speed = USB_PMC_PORT_SPEED_LOW;
409         else if (DEV_SUPERSPEED(portsc))
410                 pmc_data.port_speed = USB_PMC_PORT_SPEED_SUPER;
411         else
412                 pmc_data.port_speed = USB_PMC_PORT_SPEED_UNKNOWN;
413 }
414
415 static void setup_wake_detect(bool setup_wake)
416 {
417         if (setup_wake)
418                 pmc_data.pmc_ops->setup_pmc_wake_detect(&pmc_data);
419         else
420                 pmc_data.pmc_ops->disable_pmc_bus_ctrl(&pmc_data, 0);
421 }
422
423 static void pmc_init(struct tegra_xhci_hcd *tegra, bool setup_wake)
424 {
425         u32 portmap = tegra->bdata->portmap;
426
427         pmc_data.controller_type = TEGRA_USB_3_0;
428         if (portmap & TEGRA_XUSB_USB2_P0) {
429                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 0) & 0xf;
430                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
431                 update_speed(tegra, pmc_data.instance);
432                 tegra_usb_pmc_init(&pmc_data);
433                 setup_wake_detect(setup_wake);
434         }
435         if (portmap & TEGRA_XUSB_USB2_P1) {
436                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 4) & 0xf;
437                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
438                 update_speed(tegra, pmc_data.instance);
439                 tegra_usb_pmc_init(&pmc_data);
440                 setup_wake_detect(setup_wake);
441         }
442         if (portmap & TEGRA_XUSB_USB2_P2) {
443                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 8) & 0xf;
444                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
445                 update_speed(tegra, pmc_data.instance);
446                 tegra_usb_pmc_init(&pmc_data);
447                 setup_wake_detect(setup_wake);
448         }
449         if (portmap & TEGRA_XUSB_HSIC_P0) {
450                 pmc_data.instance = PMC_PORT_UHSIC_P0;
451                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_HSIC;
452                 update_speed(tegra, pmc_data.instance);
453                 tegra_usb_pmc_init(&pmc_data);
454                 setup_wake_detect(setup_wake);
455         }
456 }
457
458 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
459 {
460         void __iomem *fpci_base = tegra->fpci_base;
461         struct platform_device *pdev = tegra->pdev;
462         u32 input_addr;
463         u32 data;
464         u32 csb_page_select;
465
466         /* to select the appropriate CSB page to write to */
467         csb_page_select = CSB_PAGE_SELECT(addr);
468
469         dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
470                         csb_page_select);
471
472         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
473
474         /* selects the appropriate offset in the page to read from */
475         input_addr = CSB_PAGE_OFFSET(addr);
476         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
477
478         dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
479                         input_addr, data);
480         return data;
481 }
482
483 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
484 {
485         void __iomem *fpci_base = tegra->fpci_base;
486         struct platform_device *pdev = tegra->pdev;
487         u32 input_addr;
488         u32 csb_page_select;
489
490         /* to select the appropriate CSB page to write to */
491         csb_page_select = CSB_PAGE_SELECT(addr);
492
493         dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
494                         csb_page_select);
495
496         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
497
498         /* selects the appropriate offset in the page to write to */
499         input_addr = CSB_PAGE_OFFSET(addr);
500         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
501
502         dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
503                         input_addr, data);
504 }
505
506 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
507 {
508         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
509         struct xhci_hcd *xhci = tegra->xhci;
510         u32 reg;
511
512         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
513         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
514         xhci_info(xhci, " PAD MUX = %x\n", reg);
515         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
516         xhci_info(xhci, " PORT CAP = %x\n", reg);
517         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
518         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
519         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
520         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
521         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
522         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
523         reg = readl(tegra->padctl_base + padregs->oc_det_0);
524         xhci_info(xhci, " OC DET 0= %x\n", reg);
525         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad0_ctl2_0);
526         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
527         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad1_ctl2_0);
528         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
529         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl0_0);
530         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
531         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl0_0);
532         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
533         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl1_0);
534         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
535         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl1_0);
536         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
537         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
538         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
539         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad0_ctl0_0);
540         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
541         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad1_ctl0_0);
542         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
543         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
544 }
545
546 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
547 {
548         u32 reg;
549
550         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
551         reg |= IPFS_EN_FPCI;
552         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
553         udelay(10);
554
555         /* Program Bar0 Space */
556         reg = readl(tegra->fpci_base + XUSB_CFG_4);
557         reg |= tegra->host_phy_base;
558         writel(reg, tegra->fpci_base + XUSB_CFG_4);
559         usleep_range(100, 200);
560
561         /* Enable Bus Master */
562         reg = readl(tegra->fpci_base + XUSB_CFG_1);
563         reg |= 0x7;
564         writel(reg, tegra->fpci_base + XUSB_CFG_1);
565
566         /* Set intr mask to enable intr assertion */
567         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
568         reg |= IPFS_IP_INT_MASK;
569         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
570
571         /* Set hysteris to 0x80 */
572         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
573 }
574
575 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
576                 struct platform_device *pdev)
577 {
578         int err = 0;
579
580         tegra->xusb_hvdd_usb3_reg =
581                         devm_regulator_get(&pdev->dev, "hvdd_usb");
582         if (IS_ERR(tegra->xusb_hvdd_usb3_reg)) {
583                 dev_err(&pdev->dev, "hvdd_usb: regulator not found: %ld."
584                         , PTR_ERR(tegra->xusb_hvdd_usb3_reg));
585                 err = PTR_ERR(tegra->xusb_hvdd_usb3_reg);
586                 goto err_null_regulator;
587         } else {
588                 err = regulator_enable(tegra->xusb_hvdd_usb3_reg);
589                 if (err < 0) {
590                         dev_err(&pdev->dev,
591                                 "hvdd_usb3: regulator enable failed:%d\n", err);
592                         goto err_null_regulator;
593                 }
594         }
595
596         tegra->xusb_vbus_reg = devm_regulator_get(&pdev->dev, "usb_vbus");
597         if (IS_ERR(tegra->xusb_vbus_reg)) {
598                 dev_err(&pdev->dev, "vbus regulator not found: %ld."
599                         , PTR_ERR(tegra->xusb_vbus_reg));
600                 err = PTR_ERR(tegra->xusb_vbus_reg);
601                 goto err_put_hvdd_usb3;
602         } else {
603                 err = regulator_enable(tegra->xusb_vbus_reg);
604                 if (err < 0) {
605                         dev_err(&pdev->dev,
606                                 "vbus: regulator enable failed:%d\n", err);
607                         goto err_put_hvdd_usb3;
608                 }
609         }
610
611         tegra->xusb_avdd_usb3_pll_reg =
612                 devm_regulator_get(&pdev->dev, "avdd_usb_pll");
613         if (IS_ERR(tegra->xusb_avdd_usb3_pll_reg)) {
614                 dev_err(&pdev->dev, "avdd_usb3_pll regulator not found: %ld."
615                         , PTR_ERR(tegra->xusb_avdd_usb3_pll_reg));
616                 err = PTR_ERR(tegra->xusb_avdd_usb3_pll_reg);
617                 goto err_put_vbus;
618         } else {
619                 err = regulator_enable(tegra->xusb_avdd_usb3_pll_reg);
620                 if (err < 0) {
621                         dev_err(&pdev->dev,
622                         "avdd_usb3_pll: regulator enable failed:%d\n", err);
623                         goto err_put_vbus;
624                 }
625         }
626
627         tegra->xusb_avddio_usb3_reg =
628                         devm_regulator_get(&pdev->dev, "avddio_usb");
629         if (IS_ERR(tegra->xusb_avddio_usb3_reg)) {
630                 dev_err(&pdev->dev, "avddio_usb3: regulator not found: %ld."
631                         , PTR_ERR(tegra->xusb_avddio_usb3_reg));
632                 err = PTR_ERR(tegra->xusb_avddio_usb3_reg);
633                 goto err_put_usb3_pll;
634         } else {
635                 err = regulator_enable(tegra->xusb_avddio_usb3_reg);
636                 if (err < 0) {
637                         dev_err(&pdev->dev,
638                         "avddio_usb3: regulator enable failed:%d\n", err);
639                         goto err_put_usb3_pll;
640                 }
641         }
642
643         return err;
644
645 err_put_usb3_pll:
646         regulator_disable(tegra->xusb_avdd_usb3_pll_reg);
647 err_put_vbus:
648         regulator_disable(tegra->xusb_vbus_reg);
649 err_put_hvdd_usb3:
650         regulator_disable(tegra->xusb_hvdd_usb3_reg);
651 err_null_regulator:
652         tegra->xusb_vbus_reg = NULL;
653         tegra->xusb_avddio_usb3_reg = NULL;
654         tegra->xusb_hvdd_usb3_reg = NULL;
655         tegra->xusb_avdd_usb3_pll_reg = NULL;
656         return err;
657 }
658
659 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
660 {
661         regulator_disable(tegra->xusb_avddio_usb3_reg);
662         regulator_disable(tegra->xusb_avdd_usb3_pll_reg);
663         regulator_disable(tegra->xusb_vbus_reg);
664         regulator_disable(tegra->xusb_hvdd_usb3_reg);
665
666         tegra->xusb_avddio_usb3_reg = NULL;
667         tegra->xusb_avdd_usb3_pll_reg = NULL;
668         tegra->xusb_vbus_reg = NULL;
669         tegra->xusb_hvdd_usb3_reg = NULL;
670 }
671
672 /*
673  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
674  * are under hardware control
675  */
676 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
677 {
678         struct platform_device *pdev = tegra->pdev;
679         int err = 0;
680
681         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
682         if (IS_ERR(tegra->plle_clk)) {
683                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
684                 err = PTR_ERR(tegra->plle_clk);
685                 return err;
686         }
687         err = clk_enable(tegra->plle_clk);
688         if (err) {
689                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
690                         __func__);
691                 return err;
692         }
693
694         return err;
695 }
696
697 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
698 {
699         clk_disable(tegra->plle_clk);
700         tegra->plle_clk = NULL;
701 }
702
703 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
704 {
705         struct platform_device *pdev = tegra->pdev;
706         int err = 0;
707
708         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
709         if (IS_ERR(tegra->emc_clk)) {
710                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
711                 return PTR_ERR(tegra->emc_clk);
712         }
713
714         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
715                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
716                 if (IS_ERR(tegra->pll_re_vco_clk)) {
717                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
718                         err = PTR_ERR(tegra->pll_re_vco_clk);
719                         goto get_pll_re_vco_clk_failed;
720                 }
721         }
722
723         /* get the clock handle of 120MHz clock source */
724         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
725         if (IS_ERR(tegra->pll_u_480M)) {
726                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
727                 err = PTR_ERR(tegra->pll_u_480M);
728                 goto get_pll_u_480M_failed;
729         }
730
731         /* get the clock handle of 12MHz clock source */
732         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
733         if (IS_ERR(tegra->clk_m)) {
734                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
735                 err = PTR_ERR(tegra->clk_m);
736                 goto clk_get_clk_m_failed;
737         }
738
739         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
740         if (IS_ERR(tegra->ss_src_clk)) {
741                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
742                 err = PTR_ERR(tegra->ss_src_clk);
743                 tegra->ss_src_clk = NULL;
744                 goto get_ss_src_clk_failed;
745         }
746
747         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
748         if (IS_ERR(tegra->host_clk)) {
749                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
750                 err = PTR_ERR(tegra->host_clk);
751                 tegra->host_clk = NULL;
752                 goto get_host_clk_failed;
753         }
754
755         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
756         if (IS_ERR(tegra->ss_clk)) {
757                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
758                 err = PTR_ERR(tegra->ss_clk);
759                 tegra->ss_clk = NULL;
760                 goto get_ss_clk_failed;
761         }
762
763         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
764                 err = clk_enable(tegra->pll_re_vco_clk);
765                 if (err) {
766                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
767                         goto enable_pll_re_vco_clk_failed;
768                 }
769         }
770         /* enable ss clock */
771         err = clk_enable(tegra->host_clk);
772         if (err) {
773                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
774                 goto enable_host_clk_failed;
775         }
776
777         err = clk_enable(tegra->ss_clk);
778         if (err) {
779                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
780                 goto eanble_ss_clk_failed;
781         }
782
783         err = clk_enable(tegra->emc_clk);
784         if (err) {
785                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
786                 goto eanble_emc_clk_failed;
787         }
788
789         return 0;
790
791 eanble_emc_clk_failed:
792         clk_disable(tegra->ss_clk);
793
794 eanble_ss_clk_failed:
795         clk_disable(tegra->host_clk);
796
797 enable_host_clk_failed:
798         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
799                 clk_disable(tegra->pll_re_vco_clk);
800
801 enable_pll_re_vco_clk_failed:
802         tegra->ss_clk = NULL;
803
804 get_ss_clk_failed:
805         tegra->host_clk = NULL;
806
807 get_host_clk_failed:
808         tegra->ss_src_clk = NULL;
809
810 get_ss_src_clk_failed:
811         tegra->clk_m = NULL;
812
813 clk_get_clk_m_failed:
814         tegra->pll_u_480M = NULL;
815
816 get_pll_u_480M_failed:
817         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
818                 tegra->pll_re_vco_clk = NULL;
819
820 get_pll_re_vco_clk_failed:
821         tegra->emc_clk = NULL;
822
823         return err;
824 }
825
826 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
827 {
828         clk_disable(tegra->ss_clk);
829         clk_disable(tegra->host_clk);
830         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
831                 clk_disable(tegra->pll_re_vco_clk);
832         tegra->ss_clk = NULL;
833         tegra->host_clk = NULL;
834         tegra->ss_src_clk = NULL;
835         tegra->clk_m = NULL;
836         tegra->pll_u_480M = NULL;
837         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
838                 tegra->pll_re_vco_clk = NULL;
839 }
840
841 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
842         bool enable)
843 {
844         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
845         u32 reg;
846
847         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
848                 reg = readl(tegra->padctl_base +
849                         padregs->iophy_misc_pad_p0_ctl3_0);
850                 if (enable) {
851                         reg &= ~RX_IDLE_MODE;
852                         reg |= RX_IDLE_MODE_OVRD;
853                 } else {
854                         reg |= RX_IDLE_MODE;
855                         reg &= ~RX_IDLE_MODE_OVRD;
856                 }
857                 writel(reg, tegra->padctl_base +
858                         padregs->iophy_misc_pad_p0_ctl3_0);
859         }
860
861         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
862                 reg = readl(tegra->padctl_base +
863                         padregs->iophy_misc_pad_p1_ctl3_0);
864                 if (enable) {
865                         reg &= ~RX_IDLE_MODE;
866                         reg |= RX_IDLE_MODE_OVRD;
867                 } else {
868                         reg |= RX_IDLE_MODE;
869                         reg &= ~RX_IDLE_MODE_OVRD;
870                 }
871                 writel(reg, tegra->padctl_base +
872                         padregs->iophy_misc_pad_p1_ctl3_0);
873
874                 /* SATA lane also if USB3_SS port1 mapped to it */
875                 if (XUSB_DEVICE_ID_T124 == tegra->device_id &&
876                                 tegra->bdata->lane_owner & BIT(0)) {
877                         reg = readl(tegra->padctl_base +
878                                 padregs->iophy_misc_pad_s0_ctl3_0);
879                         if (enable) {
880                                 reg &= ~RX_IDLE_MODE;
881                                 reg |= RX_IDLE_MODE_OVRD;
882                         } else {
883                                 reg |= RX_IDLE_MODE;
884                                 reg &= ~RX_IDLE_MODE_OVRD;
885                         }
886                         writel(reg, tegra->padctl_base +
887                                 padregs->iophy_misc_pad_s0_ctl3_0);
888                 }
889         }
890 }
891
892 /* Enable ss clk, host clk, falcon clk,
893  * fs clk, dev clk, plle and refplle
894  */
895
896 static int
897 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
898                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
899 {
900         int ret = 0;
901         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
902         int fw_req_rate = rate, cur_rate;
903
904         /* Do not handle clock change as needed for HS disconnect issue */
905         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
906                 *sw_resp = fw_req_rate | (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
907                 return ret;
908         }
909
910         /* frequency request from firmware is in KHz.
911          * Convert it to MHz
912          */
913
914         /* get current rate of clock */
915         cur_rate = clk_get_rate(clk_handle);
916         cur_rate /= 1000;
917
918         if (fw_req_rate == cur_rate) {
919                 cmd_ack = MBOX_CMD_ACK;
920                 *sw_resp = fw_req_rate;
921         } else {
922
923                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
924                         /* Change SS clock source to CLK_M at 12MHz */
925                         clk_set_parent(clk_handle, tegra->clk_m);
926                         clk_set_rate(clk_handle, fw_req_rate * 1000);
927
928                         /* save leakage power when SS freq is being decreased */
929                         tegra_xhci_rx_idle_mode_override(tegra, true);
930                 } else if (clk_handle == tegra->ss_src_clk &&
931                                 fw_req_rate == 120000) {
932                         /* Change SS clock source to HSIC_480 at 120MHz */
933                         clk_set_rate(clk_handle,  3000 * 1000);
934                         clk_set_parent(clk_handle, tegra->pll_u_480M);
935
936                         /* clear ovrd bits when SS freq is being increased */
937                         tegra_xhci_rx_idle_mode_override(tegra, false);
938                 }
939
940                 *sw_resp = clk_get_rate(clk_handle);
941                 *sw_resp /= 1000;
942
943                 if (*sw_resp != fw_req_rate) {
944                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
945                                 cur_rate, fw_req_rate);
946                         cmd_ack = MBOX_CMD_NACK;
947                 }
948         }
949         *sw_resp |= (cmd_ack << MBOX_CMD_SHIFT);
950         return ret;
951 }
952
953 static void
954 tegra_xhci_ss_wake_on_interrupts(struct tegra_xhci_hcd *tegra, bool enable)
955 {
956         u32 elpg_program0;
957         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
958
959         /* clear any event */
960         elpg_program0 = readl(tegra->padctl_base + padregs->elpg_program_0);
961         elpg_program0 |= (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT);
962         writel(elpg_program0, tegra->padctl_base + padregs->elpg_program_0);
963
964         /* enable ss wake interrupts */
965         elpg_program0 = readl(tegra->padctl_base + padregs->elpg_program_0);
966
967         if (enable) {
968                 /* enable interrupts */
969                 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0)
970                         elpg_program0 |= SS_PORT0_WAKE_INTERRUPT_ENABLE;
971                 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
972                         elpg_program0 |= SS_PORT1_WAKE_INTERRUPT_ENABLE;
973         } else {
974                 /* disable interrupts */
975                 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0)
976                         elpg_program0 &= ~SS_PORT0_WAKE_INTERRUPT_ENABLE;
977                 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
978                         elpg_program0 &= ~SS_PORT1_WAKE_INTERRUPT_ENABLE;
979         }
980         writel(elpg_program0, tegra->padctl_base + padregs->elpg_program_0);
981 }
982
983 static void
984 tegra_xhci_hs_wake_on_interrupts(struct tegra_xhci_hcd *tegra, bool enable)
985 {
986         u32 elpg_program0;
987         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
988
989         elpg_program0 = readl(tegra->padctl_base + padregs->elpg_program_0);
990         elpg_program0 |= (USB2_PORT0_WAKEUP_EVENT |
991                         USB2_PORT1_WAKEUP_EVENT |
992                         USB2_PORT2_WAKEUP_EVENT |
993                         USB2_HSIC_PORT0_WAKEUP_EVENT |
994                         USB2_HSIC_PORT1_WAKEUP_EVENT);
995         writel(elpg_program0, tegra->padctl_base + padregs->elpg_program_0);
996
997         /* Enable the wake interrupts */
998         elpg_program0 = readl(tegra->padctl_base + padregs->elpg_program_0);
999         if (enable) {
1000                 /* enable interrupts */
1001                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1002                         elpg_program0 |= USB2_PORT0_WAKE_INTERRUPT_ENABLE;
1003                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1004                         elpg_program0 |= USB2_PORT1_WAKE_INTERRUPT_ENABLE;
1005                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1006                         elpg_program0 |= USB2_PORT2_WAKE_INTERRUPT_ENABLE;
1007                 if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P0)
1008                         elpg_program0 |= USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE;
1009                 if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P1)
1010                         elpg_program0 |= USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE;
1011         } else {
1012                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1013                         elpg_program0 &= ~USB2_PORT0_WAKE_INTERRUPT_ENABLE;
1014                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1015                         elpg_program0 &= ~USB2_PORT1_WAKE_INTERRUPT_ENABLE;
1016                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1017                         elpg_program0 &= ~USB2_PORT2_WAKE_INTERRUPT_ENABLE;
1018                 if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P0)
1019                         elpg_program0 &= ~USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE;
1020                 if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P1)
1021                         elpg_program0 &= ~USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE;
1022         }
1023         writel(elpg_program0, tegra->padctl_base + padregs->elpg_program_0);
1024 }
1025
1026 static void
1027 tegra_xhci_ss_wake_signal(struct tegra_xhci_hcd *tegra, bool enable)
1028 {
1029         u32 elpg_program0;
1030         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1031
1032         /* DO NOT COMBINE BELOW 2 WRITES */
1033
1034         /* Assert/Deassert clamp_en_early signals to SSP0/1 */
1035         elpg_program0 = readl(tegra->padctl_base + padregs->elpg_program_0);
1036         if (enable) {
1037                 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0)
1038                         elpg_program0 |= SSP0_ELPG_CLAMP_EN_EARLY;
1039                 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
1040                         elpg_program0 |= SSP1_ELPG_CLAMP_EN_EARLY;
1041         } else {
1042                 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0)
1043                         elpg_program0 &= ~SSP0_ELPG_CLAMP_EN_EARLY;
1044                 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
1045                         elpg_program0 &= ~SSP1_ELPG_CLAMP_EN_EARLY;
1046         }
1047         writel(elpg_program0, tegra->padctl_base + padregs->elpg_program_0);
1048
1049         /*
1050          * Check the LP0 figure and leave gap bw writes to
1051          * clamp_en_early and clamp_en
1052          */
1053         usleep_range(100, 200);
1054
1055         /* Assert/Deassert clam_en signal */
1056         elpg_program0 = readl(tegra->padctl_base + padregs->elpg_program_0);
1057
1058         if (enable) {
1059                 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0)
1060                         elpg_program0 |= SSP0_ELPG_CLAMP_EN;
1061                 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
1062                         elpg_program0 |= SSP1_ELPG_CLAMP_EN;
1063         } else {
1064                 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0)
1065                         elpg_program0 &= ~SSP0_ELPG_CLAMP_EN;
1066                 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
1067                         elpg_program0 &= ~SSP1_ELPG_CLAMP_EN;
1068         }
1069
1070         writel(elpg_program0, tegra->padctl_base + padregs->elpg_program_0);
1071
1072         /* wait for 250us for the writes to propogate */
1073         if (enable)
1074                 usleep_range(250, 300);
1075 }
1076
1077 static void
1078 tegra_xhci_ss_vcore(struct tegra_xhci_hcd *tegra, bool enable)
1079 {
1080         u32 elpg_program0;
1081         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1082
1083         /* Assert vcore_off signal */
1084         elpg_program0 = readl(tegra->padctl_base + padregs->elpg_program_0);
1085
1086         if (enable) {
1087                 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0)
1088                         elpg_program0 |= SSP0_ELPG_VCORE_DOWN;
1089                 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
1090                         elpg_program0 |= SSP1_ELPG_VCORE_DOWN;
1091         } else {
1092                 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0)
1093                         elpg_program0 &= ~SSP0_ELPG_VCORE_DOWN;
1094                 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
1095                         elpg_program0 &= ~SSP1_ELPG_VCORE_DOWN;
1096         }
1097         writel(elpg_program0, tegra->padctl_base + padregs->elpg_program_0);
1098 }
1099
1100 static void tegra_xhci_save_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
1101         u8 port)
1102 {
1103         struct xhci_hcd *xhci = tegra->xhci;
1104         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1105         u32 offset;
1106         u32 reg;
1107
1108         xhci_info(xhci, "saving dfe_cntl and ctle context for port %d\n", port);
1109
1110         if (port == 3 /* SATA pad */)
1111                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1112         else
1113                 offset = port ? padregs->iophy_misc_pad_p1_ctl6_0 :
1114                                 padregs->iophy_misc_pad_p0_ctl6_0;
1115
1116         /* save tap1_val[] for the port for dfe_cntl */
1117         reg = readl(tegra->padctl_base + offset);
1118         reg &= ~(0xff << 16);
1119         reg |= (0x32 << 16);
1120         writel(reg, tegra->padctl_base + offset);
1121
1122         reg = readl(tegra->padctl_base + offset);
1123         tegra->sregs.tap1_val[port] = ((reg & (0x1f << 24)) >> 24);
1124
1125         /* save amp_val[] for the port for dfe_cntl */
1126         reg = readl(tegra->padctl_base + offset);
1127         reg &= ~(0xff << 16);
1128         reg |= (0x33 << 16);
1129         writel(reg, tegra->padctl_base + offset);
1130
1131         reg = readl(tegra->padctl_base + offset);
1132         tegra->sregs.amp_val[port] = ((reg & (0x7f << 24)) >> 24);
1133
1134         /* save ctle_z_val[] for the port for ctle */
1135         reg = readl(tegra->padctl_base + offset);
1136         reg &= ~(0xff << 16);
1137         reg |= (0x20 << 16);
1138         writel(reg, tegra->padctl_base + offset);
1139
1140         reg = readl(tegra->padctl_base + offset);
1141         tegra->sregs.ctle_z_val[port] = ((reg & (0x3f << 24)) >> 24);
1142
1143         /* save ctle_g_val[] for the port for ctle */
1144         reg = readl(tegra->padctl_base + offset);
1145         reg &= ~(0xff << 16);
1146         reg |= (0x21 << 16);
1147         writel(reg, tegra->padctl_base + offset);
1148
1149         reg = readl(tegra->padctl_base + offset);
1150         tegra->sregs.ctle_g_val[port] = ((reg & (0x3f << 24)) >> 24);
1151         tegra->dfe_ctle_ctx_saved = true;
1152 }
1153
1154 static void tegra_xhci_restore_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
1155         u8 port)
1156 {
1157         struct xhci_hcd *xhci = tegra->xhci;
1158         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1159         u32 ctl4_offset, ctl2_offset;
1160         u32 reg;
1161
1162         /* don't restore if not saved */
1163         if (tegra->dfe_ctle_ctx_saved == false)
1164                 return;
1165
1166         if (port == 3 /* SATA pad */) {
1167                 ctl4_offset = padregs->iophy_misc_pad_s0_ctl4_0;
1168                 ctl2_offset = padregs->iophy_misc_pad_s0_ctl2_0;
1169         } else {
1170                 ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1171                                 padregs->iophy_usb3_pad0_ctl4_0;
1172                 ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1173                                 padregs->iophy_usb3_pad0_ctl2_0;
1174         }
1175
1176         xhci_info(xhci, "restoring dfe_cntl/ctle context of port %d\n", port);
1177
1178         /* restore dfe_cntl for the port */
1179         reg = readl(tegra->padctl_base + ctl4_offset);
1180         reg &= ~((0x7f << 16) | (0x1f << 24));
1181         reg |= ((tegra->sregs.amp_val[port] << 16) |
1182                 (tegra->sregs.tap1_val[port] << 24));
1183         writel(reg, tegra->padctl_base + ctl4_offset);
1184
1185         /* restore ctle for the port */
1186         reg = readl(tegra->padctl_base + ctl2_offset);
1187         reg &= ~((0x3f << 8) | (0x3f << 16));
1188         reg |= ((tegra->sregs.ctle_g_val[port] << 8) |
1189                 (tegra->sregs.ctle_z_val[port] << 16));
1190         writel(reg, tegra->padctl_base + ctl2_offset);
1191 }
1192
1193 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
1194         u8 port)
1195 {
1196         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1197         u32 reg;
1198
1199         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1200         reg &= ~USB2_ULPI_PAD;
1201         reg |= USB2_ULPI_PAD_OWNER_XUSB;
1202         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1203
1204         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1205         reg &= ~USB2_ULPI_PORT_CAP;
1206         reg |= (tegra->bdata->ulpicap << 24);
1207         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1208         /* FIXME: Program below when more details available
1209          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
1210          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
1211          */
1212 }
1213
1214 static void tegra_xhci_program_hsic_pad(struct tegra_xhci_hcd *tegra,
1215         u8 port)
1216 {
1217         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1218         u32 ctl0_offset;
1219         u32 reg;
1220
1221         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1222         reg &= ~(port ? USB2_HSIC_PAD_PORT1 : USB2_HSIC_PAD_PORT0);
1223         reg |= port ? USB2_HSIC_PAD_P1_OWNER_XUSB :
1224                         USB2_HSIC_PAD_P0_OWNER_XUSB;
1225         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1226
1227         ctl0_offset = port ? padregs->usb2_hsic_pad1_ctl0_0 :
1228                         padregs->usb2_hsic_pad0_ctl0_0;
1229
1230         reg = readl(tegra->padctl_base + ctl0_offset);
1231         reg &= ~(HSIC_TX_SLEWP | HSIC_TX_SLEWN);
1232         writel(reg, tegra->padctl_base + ctl0_offset);
1233
1234         /* FIXME Program below when more details available
1235          * XUSB_PADCTL_HSIC_PAD0_CTL_0_0
1236          * XUSB_PADCTL_HSIC_PAD0_CTL_1_0
1237          * XUSB_PADCTL_HSIC_PAD0_CTL_2_0
1238          * XUSB_PADCTL_HSIC_PAD1_CTL_0_0
1239          * XUSB_PADCTL_HSIC_PAD1_CTL_1_0
1240          * XUSB_PADCTL_HSIC_PAD1_CTL_2_0
1241          * XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0
1242          */
1243 }
1244
1245 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
1246         u8 port)
1247 {
1248         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1249         u32 reg;
1250         u32 ctl0_offset, ctl1_offset;
1251
1252         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1253         reg &= ~USB2_OTG_PAD_PORT_MASK(port);
1254         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
1255         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1256
1257         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1258         reg &= ~USB2_PORT_CAP_MASK(port);
1259         reg |= USB2_PORT_CAP_HOST(port);
1260         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1261
1262         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1263         if (port == 0)
1264                 reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 |
1265                         SNPS_OC_MAP_CTRL3;
1266         else if (port == 1)
1267                 reg |= SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3 |
1268                         SNPS_CTRL1_OC_DETECTED_VBUS_PAD0;
1269         else if (port == 2) /* FIXME: Review when BCT available */
1270                 reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL3 |
1271                         SNPS_CTRL1_OC_DETECTED_VBUS_PAD0;
1272         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
1273         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1274
1275         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1276         if (port == 0)
1277                 reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
1278         else if (port == 1)
1279                 reg |= OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0
1280                         | OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1;
1281         else if (port == 2) /* FIXME: Review when BCT available */
1282                 reg |= OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0
1283                         | OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1;
1284         writel(reg, tegra->padctl_base + padregs->oc_det_0);
1285
1286         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1287         if (port == 0)
1288                 reg |= USB2_OC_MAP_PORT1
1289                         | USB2_OC_MAP_PORT0_OC_DETECTED_VBUS_PAD0;
1290         else if (port == 1)
1291                 reg |= USB2_OC_MAP_PORT0
1292                         | USB2_OC_MAP_PORT1_OC_DETECTED_VBUS_PAD1;
1293         else if (port == 2) /* FIXME: Review when BCT available */
1294                 reg |= USB2_OC_MAP_PORT0
1295                         | USB2_OC_MAP_PORT1_OC_DETECTED_VBUS_PAD1;
1296         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1297
1298         ctl0_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl0_0 :
1299                         port ? padregs->usb2_otg_pad1_ctl0_0 :
1300                                 padregs->usb2_otg_pad0_ctl0_0;
1301         ctl1_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl1_0 :
1302                         port ? padregs->usb2_otg_pad1_ctl1_0 :
1303                                 padregs->usb2_otg_pad0_ctl1_0;
1304
1305         reg = readl(tegra->padctl_base + ctl0_offset);
1306         reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
1307                 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
1308                 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
1309         reg |= tegra->pdata->hs_slew;
1310         reg |= port ? 0 : tegra->pdata->ls_rslew;
1311         reg |= port ? tegra->pdata->hs_curr_level_pad1 :
1312                         tegra->pdata->hs_curr_level_pad0;
1313         writel(reg, tegra->padctl_base + ctl0_offset);
1314
1315         reg = readl(tegra->padctl_base + ctl1_offset);
1316         reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
1317                 | USB2_OTG_PD_CHRP_FORCE_POWERUP
1318                 | USB2_OTG_PD_DISC_FORCE_POWERUP
1319                 | USB2_OTG_PD_DR);
1320         reg |= (tegra->pdata->hs_iref_cap << 9) |
1321                 (tegra->pdata->hs_term_range_adj << 3);
1322         writel(reg, tegra->padctl_base + ctl1_offset);
1323 }
1324
1325 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
1326         u8 port)
1327 {
1328         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1329         u32 ctl2_offset, ctl4_offset;
1330         u32 reg;
1331
1332         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1333                         padregs->iophy_usb3_pad0_ctl2_0;
1334         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1335                         padregs->iophy_usb3_pad0_ctl4_0;
1336
1337         reg = readl(tegra->padctl_base + ctl2_offset);
1338         reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
1339                 IOPHY_USB3_CDRCNTL);
1340         reg |= tegra->pdata->rx_wander | tegra->pdata->rx_eq |
1341                 tegra->pdata->cdr_cntl;
1342         writel(reg, tegra->padctl_base + ctl2_offset);
1343
1344         reg = readl(tegra->padctl_base + ctl4_offset);
1345         reg = tegra->pdata->dfe_cntl;
1346         writel(reg, tegra->padctl_base + ctl4_offset);
1347
1348         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1349         reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
1350         reg |= (tegra->bdata->ss_portmap &
1351                 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
1352         writel(reg, tegra->padctl_base + padregs->ss_port_map_0);
1353
1354         tegra_xhci_restore_dfe_ctle_context(tegra, port);
1355         /* SATA also if USB3_SS port1 mapped to it */
1356         if ((port == 1) && (XUSB_DEVICE_ID_T124 == tegra->device_id) &&
1357                         (tegra->bdata->lane_owner & BIT(0)))
1358                 tegra_xhci_restore_dfe_ctle_context(tegra, 3);
1359 }
1360
1361 /* This function assigns the USB ports to the controllers,
1362  * then programs the port capabilities and pad parameters
1363  * of ports assigned to XUSB after booted to OS.
1364  */
1365 void
1366 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
1367 {
1368         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1369         u32 reg;
1370
1371         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1372         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
1373         reg |= tegra->pdata->hs_squelch_level | tegra->pdata->hs_disc_lvl;
1374         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1375
1376         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1377         reg &= ~(SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3);
1378         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
1379         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1380
1381         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1382         reg &= ~(OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP);
1383         writel(reg, tegra->padctl_base + padregs->oc_det_0);
1384
1385         /* check if over current seen. Clear if present */
1386         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1387         if (reg & (0x3 << 20)) {
1388                 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
1389                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1390
1391                 usleep_range(100, 200);
1392
1393                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1394                 if (reg & (0x3 << 20))
1395                         xhci_info(tegra->xhci, "Over current still present\n");
1396         }
1397
1398         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1399         reg &= ~(USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1);
1400         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1401
1402         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1403                 tegra_xhci_program_utmip_pad(tegra, 0);
1404         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1405                 tegra_xhci_program_utmip_pad(tegra, 1);
1406         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1407                 tegra_xhci_program_utmip_pad(tegra, 2);
1408
1409         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
1410                 tegra_xhci_program_ulpi_pad(tegra, 0);
1411
1412         if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P0)
1413                 tegra_xhci_program_hsic_pad(tegra, 0);
1414         if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P1)
1415                 tegra_xhci_program_hsic_pad(tegra, 1);
1416
1417         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1418                 tegra_xhci_program_ss_pad(tegra, 0);
1419         } else {
1420                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1421                 reg = readl(tegra->padctl_base +
1422                         padregs->iophy_misc_pad_p0_ctl3_0);
1423                 reg &= ~RX_IDLE_MODE;
1424                 reg |= RX_IDLE_MODE_OVRD;
1425                 writel(reg, tegra->padctl_base +
1426                         padregs->iophy_misc_pad_p0_ctl3_0);
1427         }
1428
1429         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1430                 tegra_xhci_program_ss_pad(tegra, 1);
1431         } else {
1432                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1433                 reg = readl(tegra->padctl_base +
1434                         padregs->iophy_misc_pad_p1_ctl3_0);
1435                 reg &= ~RX_IDLE_MODE;
1436                 reg |= RX_IDLE_MODE_OVRD;
1437                 writel(reg, tegra->padctl_base +
1438                         padregs->iophy_misc_pad_p1_ctl3_0);
1439
1440                 /* SATA lane also if USB3_SS port1 mapped to it but unused */
1441                 if (XUSB_DEVICE_ID_T124 == tegra->device_id &&
1442                                 tegra->bdata->lane_owner & BIT(0)) {
1443                         reg = readl(tegra->padctl_base +
1444                                 padregs->iophy_misc_pad_s0_ctl3_0);
1445                         reg &= ~RX_IDLE_MODE;
1446                         reg |= RX_IDLE_MODE_OVRD;
1447                         writel(reg, tegra->padctl_base +
1448                                 padregs->iophy_misc_pad_s0_ctl3_0);
1449                 }
1450         }
1451         if (XUSB_DEVICE_ID_T124 == tegra->device_id)
1452                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
1453
1454 }
1455
1456 /* This function read XUSB registers and stores in device context */
1457 static void
1458 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
1459 {
1460
1461         /* a. Save the IPFS registers */
1462         tegra->sregs.msi_bar_sz =
1463                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
1464
1465         tegra->sregs.msi_axi_barst =
1466                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
1467
1468         tegra->sregs.msi_fpci_barst =
1469                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
1470
1471         tegra->sregs.msi_vec0 =
1472                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
1473
1474         tegra->sregs.msi_en_vec0 =
1475                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
1476
1477         tegra->sregs.fpci_error_masks =
1478                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
1479
1480         tegra->sregs.intr_mask =
1481                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1482
1483         tegra->sregs.ipfs_intr_enable =
1484                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
1485
1486         tegra->sregs.ufpci_config =
1487                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
1488
1489         tegra->sregs.clkgate_hysteresis =
1490                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1491
1492         tegra->sregs.xusb_host_mccif_fifo_cntrl =
1493                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
1494
1495         /* b. Save the CFG registers */
1496
1497         tegra->sregs.hs_pls =
1498                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
1499
1500         tegra->sregs.fs_pls =
1501                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
1502
1503         tegra->sregs.hs_fs_speed =
1504                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
1505
1506         tegra->sregs.hs_fs_pp =
1507                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
1508
1509         tegra->sregs.cfg_aru =
1510                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
1511
1512         tegra->sregs.cfg_order =
1513                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
1514
1515         tegra->sregs.cfg_fladj =
1516                 readl(tegra->fpci_base + XUSB_CFG_24);
1517
1518         tegra->sregs.cfg_sid =
1519                 readl(tegra->fpci_base + XUSB_CFG_16);
1520 }
1521
1522 /* This function restores XUSB registers from device context */
1523 static void
1524 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
1525 {
1526         /* Restore Cfg registers */
1527         writel(tegra->sregs.hs_pls,
1528                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
1529
1530         writel(tegra->sregs.fs_pls,
1531                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
1532
1533         writel(tegra->sregs.hs_fs_speed,
1534                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
1535
1536         writel(tegra->sregs.hs_fs_pp,
1537                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
1538
1539         writel(tegra->sregs.cfg_aru,
1540                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
1541
1542         writel(tegra->sregs.cfg_order,
1543                 tegra->fpci_base + XUSB_CFG_FPCICFG);
1544
1545         writel(tegra->sregs.cfg_fladj,
1546                 tegra->fpci_base + XUSB_CFG_24);
1547
1548         writel(tegra->sregs.cfg_sid,
1549                 tegra->fpci_base + XUSB_CFG_16);
1550
1551         /* Restore IPFS registers */
1552
1553         writel(tegra->sregs.msi_bar_sz,
1554                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
1555
1556         writel(tegra->sregs.msi_axi_barst,
1557                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
1558
1559         writel(tegra->sregs.msi_fpci_barst,
1560                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
1561
1562         writel(tegra->sregs.msi_vec0,
1563                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
1564
1565         writel(tegra->sregs.msi_en_vec0,
1566                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
1567
1568         writel(tegra->sregs.fpci_error_masks,
1569                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
1570
1571         writel(tegra->sregs.intr_mask,
1572                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1573
1574         writel(tegra->sregs.ipfs_intr_enable,
1575                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
1576
1577         writel(tegra->sregs.ufpci_config,
1578                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
1579
1580         writel(tegra->sregs.clkgate_hysteresis,
1581                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1582
1583         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
1584                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
1585 }
1586
1587 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
1588 {
1589         struct platform_device *pdev = tegra->pdev;
1590         u32 reg, timeout = 0xff, cmd;
1591
1592         mutex_lock(&tegra->mbox_lock);
1593
1594         do {
1595                 writel(MBOX_OWNER_SW,
1596                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
1597                 reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
1598                 usleep_range(10, 20);
1599         } while (reg != MBOX_OWNER_SW && timeout--);
1600
1601         if ((timeout == 0) && (reg != MBOX_OWNER_SW)) {
1602                 dev_err(&pdev->dev, "Failed to set mbox message owner ID\n");
1603                 mutex_unlock(&tegra->mbox_lock);
1604                 return;
1605         }
1606
1607         writel((MBOX_CMD_MSG_ENABLED << MBOX_CMD_SHIFT),
1608                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
1609
1610         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1611         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
1612         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1613
1614         mutex_unlock(&tegra->mbox_lock);
1615 }
1616
1617 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
1618 {
1619         struct platform_device *pdev = tegra->pdev;
1620         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
1621         u32 phys_addr_lo;
1622         u32 HwReg;
1623         u16 nblocks;
1624         time_t fw_time;
1625         struct tm fw_tm;
1626         u8 hc_caplength;
1627         u32 usbsts, count = 0xff;
1628         struct xhci_cap_regs __iomem *cap_regs;
1629         struct xhci_op_regs __iomem *op_regs;
1630
1631         /* enable mbox interrupt */
1632         writel(readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD) | MBOX_INT_EN,
1633                 tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1634
1635         /* First thing, reset the ARU. By the time we get to
1636          * loading boot code below, reset would be complete.
1637          * alternatively we can busy wait on rst pending bit.
1638          */
1639         /* Don't reset during ELPG/LP0 exit path */
1640         if (resetARU) {
1641                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
1642                 usleep_range(1000, 2000);
1643         }
1644
1645         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
1646                 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
1647                                 csb_read(tegra, XUSB_FALC_CPUCTL));
1648                 return 0;
1649         }
1650
1651         phys_addr_lo = tegra->firmware.dma;
1652         phys_addr_lo += sizeof(struct cfgtbl);
1653
1654         /* Program the size of DFI into ILOAD_ATTR */
1655         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
1656
1657         /* Boot code of the firmware reads the ILOAD_BASE_LO register
1658          * to get to the start of the dfi in system memory.
1659          */
1660         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
1661
1662         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
1663         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
1664
1665         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
1666         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
1667
1668         /* Invalidate L2IMEM. */
1669         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
1670
1671         /* Initiate fetch of Bootcode from system memory into L2IMEM.
1672          * Program BootCode location and size in system memory.
1673          */
1674         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
1675                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
1676                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
1677         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
1678                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
1679                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
1680         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
1681
1682         /* Trigger L2IMEM Load operation. */
1683         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
1684
1685         /* Setup Falcon Auto-fill */
1686         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
1687         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
1688                 nblocks += 1;
1689         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
1690
1691         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
1692         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
1693                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
1694         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
1695
1696         csb_write(tegra, XUSB_FALC_DMACTL, 0);
1697         msleep(50);
1698
1699         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
1700
1701         /* Start Falcon CPU */
1702         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
1703         usleep_range(1000, 2000);
1704
1705         fw_time = cfg_tbl->fwimg_created_time;
1706         time_to_tm(fw_time, 0, &fw_tm);
1707         dev_info(&pdev->dev,
1708                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
1709                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
1710                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
1711                 fw_tm.tm_min, fw_tm.tm_sec,
1712                 csb_read(tegra, XUSB_FALC_CPUCTL));
1713
1714         /* return fail if firmware status is not good */
1715         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
1716                 return -EFAULT;
1717
1718         cap_regs = IO_ADDRESS(tegra->host_phy_base);
1719         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
1720         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
1721
1722         /* wait for USBSTS_CNR to get set */
1723         do {
1724                 usbsts = ioread32(&op_regs->status);
1725         } while ((usbsts & STS_CNR) && count--);
1726
1727         if (!count && (usbsts & STS_CNR)) {
1728                 dev_err(&pdev->dev, "Controller not ready\n");
1729                 return -EFAULT;
1730         }
1731         return 0;
1732 }
1733
1734 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
1735         bool release)
1736 {
1737         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1738         u32 reg;
1739
1740         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1741         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
1742                         USB2_OTG_PAD_PORT_MASK(2));
1743
1744         if (!release) {
1745                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1746                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
1747                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1748                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
1749                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1750                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
1751         }
1752
1753         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1754 }
1755 /* SS ELPG Entry initiated by fw */
1756 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
1757 {
1758         struct xhci_hcd *xhci = tegra->xhci;
1759         u32 ret = 0;
1760
1761         must_have_sync_lock(tegra);
1762
1763         /* This is SS partition ELPG entry
1764          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
1765          */
1766
1767         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
1768          * only if it is sw initiated one
1769          */
1770
1771         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
1772          * SuperSpeed partition ELPG entry via mailbox protocol
1773          */
1774
1775         /* STEP 2: xHCI PEP driver and XUSB device mode driver
1776          * enable the XUSB wakeup interrupts for the SuperSpeed
1777          * and USB2.0 ports assigned to host.Section 4.1 Step 3
1778          */
1779         tegra_xhci_ss_wake_on_interrupts(tegra, true);
1780
1781         /* STEP 3: xHCI PEP driver initiates the signal sequence
1782          * to enable the XUSB SSwake detection logic for the
1783          * SuperSpeed ports assigned to host.Section 4.1 Step 4
1784          */
1785         tegra_xhci_ss_wake_signal(tegra, true);
1786
1787         /* STEP 4: System Power Management driver asserts reset
1788          * to XUSB SuperSpeed partition then disables its clocks
1789          */
1790         tegra_periph_reset_assert(tegra->ss_clk);
1791         clk_disable(tegra->ss_clk);
1792
1793         usleep_range(100, 200);
1794
1795         /* STEP 5: System Power Management driver disables the
1796          * XUSB SuperSpeed partition power rails.
1797          */
1798         debug_print_portsc(xhci);
1799
1800         /* tegra_powergate_partition also does partition reset assert */
1801         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
1802         if (ret) {
1803                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
1804                                 __func__);
1805                 /* TODO: error recovery? */
1806         }
1807         tegra->ss_pwr_gated = true;
1808
1809         /* STEP 6: xHCI PEP driver initiates the signal sequence
1810          * to enable the XUSB SSwake detection logic for the
1811          * SuperSpeed ports assigned to host.Section 4.1 Step 7
1812          */
1813         tegra_xhci_ss_vcore(tegra, true);
1814
1815         return ret;
1816 }
1817
1818 /* Host ELPG Entry */
1819 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
1820 {
1821         struct xhci_hcd *xhci = tegra->xhci;
1822         u32 ret;
1823
1824         must_have_sync_lock(tegra);
1825
1826         /* If ss is already powergated skip ss ctx save stuff */
1827         if (tegra->ss_pwr_gated) {
1828                 xhci_info(xhci, "%s: SS partition is already powergated\n",
1829                         __func__);
1830         } else {
1831                 ret = tegra_xhci_ss_elpg_entry(tegra);
1832                 if (ret) {
1833                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
1834                                 __func__, ret);
1835                         return ret;
1836                 }
1837         }
1838
1839         /* 1. IS INTR PENDING INT_PENDING=1 ? */
1840
1841         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
1842         tegra_xhci_save_xusb_ctx(tegra);
1843
1844         pmc_init(tegra, 1);
1845
1846         tegra_xhci_hs_wake_on_interrupts(tegra, true);
1847         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
1848                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
1849
1850         /* STEP 4: Assert reset to host clk and disable host clk */
1851         tegra_periph_reset_assert(tegra->host_clk);
1852
1853         clk_disable(tegra->host_clk);
1854
1855         /* wait 150us */
1856         usleep_range(150, 200);
1857
1858         /* flush MC client of XUSB_HOST */
1859         tegra_powergate_mc_flush(TEGRA_POWERGATE_XUSBC);
1860
1861         /* STEP 4: Powergate host partition */
1862         /* tegra_powergate_partition also does partition reset assert */
1863         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
1864         if (ret) {
1865                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
1866                         __func__, ret);
1867                 /* TODO: error handling? */
1868                 return ret;
1869         }
1870         tegra->host_pwr_gated = true;
1871
1872         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1873                 clk_disable(tegra->pll_re_vco_clk);
1874         clk_disable(tegra->emc_clk);
1875         /* set port ownership to SNPS */
1876         tegra_xhci_release_port_ownership(tegra, true);
1877
1878         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
1879                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
1880
1881         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
1882         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
1883                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
1884         return ret;
1885 }
1886
1887 /* SS ELPG Exit triggered by PADCTL irq */
1888 /**
1889  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
1890  *
1891  * This function must be called with tegra->sync_lock acquired.
1892  *
1893  * @tegra: xhci controller context
1894  * @return 0 for success, or error numbers
1895  */
1896 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
1897 {
1898         struct xhci_hcd *xhci = tegra->xhci;
1899         int ret = 0;
1900
1901         must_have_sync_lock(tegra);
1902
1903         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
1904                         tegra->hs_wake_event || tegra->host_resume_req)) {
1905
1906                 /*
1907                  * PWR_UNGATE SS partition. XUSBA
1908                  * tegra_unpowergate_partition also does partition reset
1909                  * deassert
1910                  */
1911                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
1912                 if (ret) {
1913                         xhci_err(xhci,
1914                         "%s: could not unpowergate xusba partition %d\n",
1915                         __func__, ret);
1916                         goto out;
1917                 }
1918                 if (tegra->ss_wake_event)
1919                         tegra->ss_wake_event = false;
1920
1921         } else {
1922                 xhci_info(xhci, "%s: ss already power gated\n",
1923                         __func__);
1924                 return ret;
1925         }
1926
1927         /* Step 3: Enable clock to ss partition */
1928         clk_enable(tegra->ss_clk);
1929
1930         /* Step 4: Disable ss wake detection logic */
1931         tegra_xhci_ss_wake_on_interrupts(tegra, false);
1932
1933         /* Step 4.1: Disable ss wake detection logic */
1934         tegra_xhci_ss_vcore(tegra, false);
1935
1936         /* wait 150us */
1937         usleep_range(150, 200);
1938
1939         /* Step 4.2: Disable ss wake detection logic */
1940         tegra_xhci_ss_wake_signal(tegra, false);
1941
1942         /* Step 6 Deassert reset for ss clks */
1943         tegra_periph_reset_deassert(tegra->ss_clk);
1944
1945         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
1946         tegra->ss_pwr_gated = false;
1947 out:
1948         return ret;
1949 }
1950
1951 static void ss_partition_elpg_exit_work(struct work_struct *work)
1952 {
1953         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
1954                 ss_elpg_exit_work);
1955
1956         mutex_lock(&tegra->sync_lock);
1957         tegra_xhci_ss_partition_elpg_exit(tegra);
1958         mutex_unlock(&tegra->sync_lock);
1959 }
1960
1961 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
1962 static void update_remote_wakeup_ports_pmc(struct tegra_xhci_hcd *tegra)
1963 {
1964         struct xhci_hcd *xhci = tegra->xhci;
1965         u32 wake2_status;
1966
1967 #define PMC_WAKE2_STATUS        0x168
1968 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
1969
1970         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
1971
1972         if (wake2_status & PADCTL_WAKE) {
1973                 /* FIXME: This is customized for Dalmore, find a generic way */
1974                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
1975                 /* clear wake status */
1976                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
1977         }
1978
1979         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
1980                         __func__, tegra->usb3_rh_remote_wakeup_ports);
1981 }
1982
1983 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
1984 {
1985         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1986         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
1987         int port, num_ports;
1988         unsigned long *remote_wakeup_ports;
1989         u32 portsc;
1990         __le32 __iomem  **port_array;
1991         unsigned char *rh;
1992         unsigned int retry = 64;
1993
1994
1995         if (hcd == xhci->shared_hcd) {
1996                 port_array = xhci->usb3_ports;
1997                 num_ports = xhci->num_usb3_ports;
1998                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
1999                 rh = "usb3 roothub";
2000         } else
2001                 return;
2002
2003         while (*remote_wakeup_ports && retry--) {
2004                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
2005                         portsc = xhci_readl(xhci, port_array[port]);
2006
2007                         if (!(portsc & PORT_CONNECT)) {
2008                                 /* nothing to do if already disconnected */
2009                                 clear_bit(port, remote_wakeup_ports);
2010                                 continue;
2011                         }
2012
2013                         if ((portsc & PORT_PLS_MASK) == XDEV_U0)
2014                                 clear_bit(port, remote_wakeup_ports);
2015                         else
2016                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
2017                                                 __func__, rh, port, portsc);
2018                 }
2019
2020                 if (*remote_wakeup_ports)
2021                         msleep(20); /* give some time, irq will direct U0 */
2022         }
2023
2024         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
2025                         *remote_wakeup_ports);
2026 }
2027
2028 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
2029 {
2030         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2031         u32 reg, utmip_rctrl_val, utmip_tctrl_val;
2032
2033         /* Program XUSB as port owner for all usb2 ports */
2034         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2035         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2036                         USB2_OTG_PAD_PORT_MASK(2));
2037         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
2038                 USB2_OTG_PAD_PORT_OWNER_XUSB(1) | USB2_OTG_PAD_PORT_MASK(2);
2039         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2040
2041         /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
2042          * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
2043          */
2044         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2045         reg &= ~((1 << 12) | (1 << 13));
2046         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2047
2048         /* wait 20us */
2049         usleep_range(20, 30);
2050
2051         /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
2052          * :: TCTRL and RCTRL
2053          */
2054         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl1_0);
2055         utmip_rctrl_val = RCTRL(reg);
2056         utmip_tctrl_val = TCTRL(reg);
2057
2058         /*
2059          * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
2060          * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
2061          */
2062         pmc_data.utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
2063         pmc_data.utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
2064
2065         xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
2066                 pmc_data.utmip_rctrl_val, pmc_data.utmip_tctrl_val);
2067
2068         /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
2069          * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
2070          */
2071         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2072         reg |= (1 << 13);
2073         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2074
2075         /* Program these values into PMC regiseter and program the
2076          * PMC override
2077          */
2078         reg = PMC_TCTRL_VAL(pmc_data.utmip_tctrl_val) |
2079                 PMC_RCTRL_VAL(pmc_data.utmip_rctrl_val);
2080         tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG, 0xffffffff, reg);
2081
2082         reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
2083         tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
2084
2085         /* Restore correct port ownership in padctl */
2086         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2087         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2088                         USB2_OTG_PAD_PORT_MASK(2));
2089         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2090                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2091         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2092                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2093         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2094                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2095         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2096 }
2097
2098 /* Host ELPG Exit triggered by PADCTL irq */
2099 /**
2100  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
2101  *
2102  * This function must be called with tegra->sync_lock acquired.
2103  *
2104  * @tegra: xhci controller context
2105  * @return 0 for success, or error numbers
2106  */
2107 static int
2108 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2109 {
2110         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2111         struct xhci_hcd *xhci = tegra->xhci;
2112         int ret = 0;
2113
2114         must_have_sync_lock(tegra);
2115
2116         if (!tegra->hc_in_elpg)
2117                 return 0;
2118
2119         clk_enable(tegra->emc_clk);
2120         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2121                 clk_enable(tegra->pll_re_vco_clk);
2122         /* Step 2: Enable clock to host partition */
2123         clk_enable(tegra->host_clk);
2124
2125         if (tegra->lp0_exit) {
2126                 u32 reg;
2127
2128                 tegra_xhci_war_for_tctrl_rctrl(tegra);
2129                 /* check if over current seen. Clear if present */
2130                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2131                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
2132                 if (reg & (0x3 << 20)) {
2133                         xhci_info(xhci, "Over current detected. Clearing...\n");
2134                         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2135
2136                         usleep_range(100, 200);
2137
2138                         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2139                         if (reg & (0x3 << 20))
2140                                 xhci_info(xhci, "Over current still present\n");
2141                 }
2142                 tegra_xhci_padctl_portmap_and_caps(tegra);
2143                 /* release clamps post deassert */
2144                 tegra->lp0_exit = false;
2145         }
2146
2147         /* Clear FLUSH_ENABLE of MC client */
2148         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
2149
2150         /* set port ownership back to xusb */
2151         tegra_xhci_release_port_ownership(tegra, false);
2152
2153         /*
2154          * PWR_UNGATE Host partition. XUSBC
2155          * tegra_unpowergate_partition also does partition reset deassert
2156          */
2157         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
2158         if (ret) {
2159                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2160                         __func__, ret);
2161                 goto out;
2162         }
2163
2164         /* Step 4: Deassert reset to host partition clk */
2165         tegra_periph_reset_deassert(tegra->host_clk);
2166
2167         /* Step 6.1: IPFS and XUSB BAR initialization */
2168         tegra_xhci_cfg(tegra);
2169
2170         /* Step 6.2: IPFS and XUSB related restore */
2171         tegra_xhci_restore_ctx(tegra);
2172
2173         /* Step 8: xhci spec related ctx restore
2174          * will be done in xhci_resume().Do it here.
2175          */
2176
2177         tegra_xhci_ss_partition_elpg_exit(tegra);
2178
2179         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
2180         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
2181                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
2182                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
2183         }
2184
2185         /* clear ovrd bits */
2186         tegra_xhci_rx_idle_mode_override(tegra, false);
2187
2188         /* Load firmware */
2189         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
2190                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
2191                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
2192                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
2193                         __func__,
2194                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
2195                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
2196                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
2197                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
2198                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
2199                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
2200                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
2201                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
2202                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
2203         debug_print_portsc(xhci);
2204
2205         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
2206         if (ret < 0) {
2207                 xhci_err(xhci, "%s: failed to load firmware %d\n",
2208                         __func__, ret);
2209                 goto out;
2210         }
2211
2212         pmc_init(tegra, 0);
2213
2214         tegra->hc_in_elpg = false;
2215         ret = xhci_resume(tegra->xhci, 0);
2216         if (ret) {
2217                 xhci_err(xhci, "%s: could not resume right %d\n",
2218                                 __func__, ret);
2219                 goto out;
2220         }
2221
2222         update_remote_wakeup_ports_pmc(tegra);
2223
2224         if (tegra->hs_wake_event)
2225                 tegra->hs_wake_event = false;
2226
2227         if (tegra->host_resume_req)
2228                 tegra->host_resume_req = false;
2229
2230         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
2231                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
2232
2233         tegra->host_pwr_gated = false;
2234 out:
2235         return ret;
2236 }
2237
2238 static void host_partition_elpg_exit_work(struct work_struct *work)
2239 {
2240         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2241                 host_elpg_exit_work);
2242
2243         mutex_lock(&tegra->sync_lock);
2244         tegra_xhci_host_partition_elpg_exit(tegra);
2245         mutex_unlock(&tegra->sync_lock);
2246 }
2247
2248 /* Mailbox handling function. This function handles requests
2249  * from firmware and communicates with clock and powergating
2250  * module to alter clock rates and to power gate/ungate xusb
2251  * partitions.
2252  *
2253  * Following is the structure of mailbox messages.
2254  * bit 31:28 - msg type
2255  * bits 27:0 - mbox data
2256  * FIXME:  Check if we can just call clock functions like below
2257  * or should we schedule it for calling later ?
2258  */
2259
2260 static void
2261 tegra_xhci_process_mbox_message(struct work_struct *work)
2262 {
2263         u32 sw_resp = 0, cmd, data_in, fw_msg;
2264         int ret = 0;
2265         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2266                                         mbox_work);
2267         struct xhci_hcd *xhci = tegra->xhci;
2268         unsigned int freq_khz;
2269
2270         mutex_lock(&tegra->mbox_lock);
2271
2272         /* get the owner id */
2273         tegra->mbox_owner = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2274         tegra->mbox_owner &= MBOX_OWNER_ID_MASK;
2275
2276         /* get the mbox message from firmware */
2277         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
2278
2279         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2280         if (data_in) {
2281                 mutex_unlock(&tegra->mbox_lock);
2282                 return;
2283         }
2284
2285         /* get cmd type and cmd data */
2286         tegra->cmd_type = (fw_msg & MBOX_CMD_TYPE_MASK) >> MBOX_CMD_SHIFT;
2287         tegra->cmd_data = (fw_msg & MBOX_CMD_DATA_MASK);
2288
2289         /* decode the message and make appropriate requests to
2290          * clock or powergating module.
2291          */
2292
2293         switch (tegra->cmd_type) {
2294         case MBOX_CMD_INC_FALC_CLOCK:
2295         case MBOX_CMD_DEC_FALC_CLOCK:
2296                 ret = tegra_xusb_request_clk_rate(
2297                                 tegra,
2298                                 tegra->falc_clk,
2299                                 tegra->cmd_data,
2300                                 &sw_resp);
2301                 if (ret)
2302                         xhci_err(xhci, "%s: could not set required falc rate\n",
2303                                 __func__);
2304                 goto send_sw_response;
2305         case MBOX_CMD_INC_SSPI_CLOCK:
2306         case MBOX_CMD_DEC_SSPI_CLOCK:
2307                 ret = tegra_xusb_request_clk_rate(
2308                                 tegra,
2309                                 tegra->ss_src_clk,
2310                                 tegra->cmd_data,
2311                                 &sw_resp);
2312                 if (ret)
2313                         xhci_err(xhci, "%s: could not set required ss rate.\n",
2314                                 __func__);
2315                 goto send_sw_response;
2316         case MBOX_CMD_SET_BW:
2317                 /* fw sends BW request in MByte/sec */
2318                 freq_khz = tegra_emc_bw_to_freq_req(tegra->cmd_data << 10);
2319                 clk_set_rate(tegra->emc_clk, freq_khz * 1000);
2320
2321                 /* clear MBOX_SMI_INT_EN bit */
2322                 cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2323                 cmd &= ~MBOX_SMI_INT_EN;
2324                 writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2325
2326                 /* clear mbox owner as ACK will not be sent for this request */
2327                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2328                 break;
2329         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
2330                 tegra_xhci_save_dfe_ctle_context(tegra, tegra->cmd_data);
2331                 tegra_xhci_restore_dfe_ctle_context(tegra, tegra->cmd_data);
2332                 /* SATA lane also if USB3_SS port1 mapped to it */
2333                 if (tegra->cmd_data == 0x1 &&
2334                         XUSB_DEVICE_ID_T124 == tegra->device_id &&
2335                                 tegra->bdata->lane_owner & BIT(0)) {
2336                         tegra_xhci_save_dfe_ctle_context(tegra, 3);
2337                         tegra_xhci_restore_dfe_ctle_context(tegra, 3);
2338                 }
2339
2340                 sw_resp |= (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
2341                 goto send_sw_response;
2342         case MBOX_CMD_ACK:
2343                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2344                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2345                 break;
2346         case MBOX_CMD_NACK:
2347                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2348                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2349                 break;
2350         default:
2351                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
2352                                 __func__, tegra->cmd_type);
2353         }
2354         mutex_unlock(&tegra->mbox_lock);
2355         return;
2356
2357 send_sw_response:
2358         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2359         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2360         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
2361         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2362
2363         mutex_unlock(&tegra->mbox_lock);
2364 }
2365
2366 static irqreturn_t tegra_xhci_xusb_host_irq(int irq, void *ptrdev)
2367 {
2368         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2369         struct xhci_hcd *xhci = tegra->xhci;
2370
2371         xhci_dbg(xhci, "%s", __func__);
2372         return IRQ_HANDLED;
2373 }
2374
2375 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
2376 {
2377         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2378         struct xhci_hcd *xhci = tegra->xhci;
2379         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2380         u32 elpg_program0 = 0;
2381
2382         spin_lock(&tegra->lock);
2383
2384         tegra->last_jiffies = jiffies;
2385
2386         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
2387         elpg_program0 = readl(tegra->padctl_base + padregs->elpg_program_0);
2388
2389         /* Clear the interrupt cause. We already read the intr status. */
2390         tegra_xhci_ss_wake_on_interrupts(tegra, false);
2391         tegra_xhci_hs_wake_on_interrupts(tegra, false);
2392
2393         xhci_dbg(xhci, "%s: elpg_program0 = %x\n",
2394                 __func__, elpg_program0);
2395         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
2396                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2397         xhci_dbg(xhci, "%s: elpg_program0 = %x\n",
2398                 __func__, readl(tegra->padctl_base + padregs->elpg_program_0));
2399         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
2400                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
2401         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
2402                 __func__,
2403                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad0_ctl0_0));
2404         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
2405                 __func__,
2406                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad1_ctl0_0));
2407         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
2408                 __func__,
2409                 readl(tegra->padctl_base + padregs->usb2_bchrg_bias_pad_0));
2410
2411         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
2412                 tegra->ss_wake_event = true;
2413         else if (elpg_program0 &
2414                         (USB2_PORT0_WAKEUP_EVENT | USB2_PORT1_WAKEUP_EVENT))
2415                 tegra->hs_wake_event = true;
2416
2417         if (tegra->ss_wake_event || tegra->hs_wake_event) {
2418                 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
2419                         xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
2420                         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
2421                 } else if (tegra->ss_pwr_gated
2422                                 && tegra->host_pwr_gated) {
2423                         xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
2424                                 __func__);
2425                         schedule_work(&tegra->host_elpg_exit_work);
2426                 }
2427         } else {
2428                 xhci_err(xhci, "error: wake due to no hs/ss event\n");
2429                 writel(0xffffffff, tegra->padctl_base +
2430                         padregs->elpg_program_0);
2431         }
2432         spin_unlock(&tegra->lock);
2433         return IRQ_HANDLED;
2434 }
2435
2436 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
2437 {
2438         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2439         u32 temp;
2440
2441         spin_lock(&tegra->lock);
2442
2443         /* clear the mbox intr status 1st thing. Other
2444          * bits are W1C bits, so just write to SMI bit.
2445          */
2446
2447         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
2448
2449         /* write 1 to clear SMI INTR en bit ( bit 3 ) */
2450         temp = MBOX_SMI_INTR_EN;
2451         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
2452
2453         schedule_work(&tegra->mbox_work);
2454
2455         spin_unlock(&tegra->lock);
2456         return IRQ_HANDLED;
2457 }
2458
2459 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
2460 {
2461         /*
2462          * As of now platform drivers don't provide MSI support so we ensure
2463          * here that the generic code does not try to make a pci_dev from our
2464          * dev struct in order to setup MSI
2465          */
2466         xhci->quirks |= XHCI_BROKEN_MSI;
2467         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
2468 }
2469
2470 /* called during probe() after chip reset completes */
2471 static int xhci_plat_setup(struct usb_hcd *hcd)
2472 {
2473         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
2474 }
2475
2476 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
2477         const char *name, void __iomem **region)
2478 {
2479         struct resource *res;
2480         void __iomem *mem;
2481
2482         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
2483         if (!res) {
2484                 dev_err(&pdev->dev, "memory resource %s doesn't exist\n", name);
2485                 return -ENODEV;
2486         }
2487
2488         mem = devm_request_and_ioremap(&pdev->dev, res);
2489         if (!mem) {
2490                 dev_err(&pdev->dev, "failed to ioremap for %s\n", name);
2491                 return -EFAULT;
2492         }
2493         *region = mem;
2494
2495         return 0;
2496 }
2497
2498 static int tegra_xhci_request_irq(struct platform_device *pdev,
2499         const char *rscname, irq_handler_t handler, unsigned long irqflags,
2500         const char *devname, int *irq_no)
2501 {
2502         int ret;
2503         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2504         struct resource *res;
2505
2506         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, rscname);
2507         if (!res) {
2508                 dev_err(&pdev->dev, "irq resource %s doesn't exist\n", rscname);
2509                 return -ENODEV;
2510         }
2511
2512         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
2513                         devname, tegra);
2514         if (ret != 0) {
2515                 dev_err(&pdev->dev,
2516                         "failed to request_irq for %s (irq %d), error = %d\n",
2517                         devname, res->start, ret);
2518                 return ret;
2519         }
2520         *irq_no = res->start;
2521
2522         return 0;
2523 }
2524
2525 #ifdef CONFIG_PM
2526
2527 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
2528 {
2529         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2530         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2531         int err = 0;
2532         unsigned long flags;
2533
2534         mutex_lock(&tegra->sync_lock);
2535
2536         if (xhci->shared_hcd == hcd) {
2537                 tegra->usb3_rh_suspend = true;
2538                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
2539         } else if (xhci->main_hcd == hcd) {
2540                 tegra->usb2_rh_suspend = true;
2541                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
2542         }
2543
2544         WARN_ON(tegra->hc_in_elpg);
2545
2546         /* suspend xhci bus. This will also set remote mask */
2547         err = xhci_bus_suspend(hcd);
2548         if (err) {
2549                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
2550                                 __func__, err);
2551                 goto xhci_bus_suspend_failed;
2552         }
2553
2554         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
2555                 goto done; /* one of the root hubs is still working */
2556
2557         spin_lock_irqsave(&tegra->lock, flags);
2558         tegra->hc_in_elpg = true;
2559         spin_unlock_irqrestore(&tegra->lock, flags);
2560
2561         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
2562
2563         /* save xhci spec ctx. Already done by xhci_suspend */
2564         err = xhci_suspend(tegra->xhci);
2565         if (err) {
2566                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
2567                 goto xhci_suspend_failed;
2568         }
2569
2570         /* Powergate host. Include ss power gate if not already done */
2571         err = tegra_xhci_host_elpg_entry(tegra);
2572         if (err) {
2573                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
2574                                 __func__, err);
2575                 goto tegra_xhci_host_elpg_entry_failed;
2576         }
2577
2578         /* At this point,ensure ss/hs intr enables are always on */
2579         tegra_xhci_ss_wake_on_interrupts(tegra, true);
2580         tegra_xhci_hs_wake_on_interrupts(tegra, true);
2581
2582 done:
2583         /* pads are disabled only if usb2 root hub in xusb is idle */
2584         /* pads will actually be disabled only when all usb2 ports are idle */
2585         if (xhci->main_hcd == hcd) {
2586                 utmi_phy_pad_disable();
2587                 utmi_phy_iddq_override(true);
2588                 /* port ownership to SNPS when no HS connected to save power */
2589                 if (!is_any_hs_connected(xhci))
2590                         tegra_xhci_release_port_ownership(tegra, true);
2591         } else if (xhci->shared_hcd == hcd) {
2592                 /* save leakage power when SS not in use.
2593                  * This is also done when fw mbox message is received for freq
2594                  * decrease but on T114 we don't change freq due to sw WAR
2595                  * used for hs disconnect issue.
2596                  */
2597                 tegra_xhci_rx_idle_mode_override(tegra, true);
2598         }
2599         mutex_unlock(&tegra->sync_lock);
2600         return 0;
2601
2602 tegra_xhci_host_elpg_entry_failed:
2603
2604 xhci_suspend_failed:
2605         tegra->hc_in_elpg = false;
2606 xhci_bus_suspend_failed:
2607         if (xhci->shared_hcd == hcd)
2608                 tegra->usb3_rh_suspend = false;
2609         else if (xhci->main_hcd == hcd)
2610                 tegra->usb2_rh_suspend = false;
2611
2612         mutex_unlock(&tegra->sync_lock);
2613         return err;
2614 }
2615
2616 /* First, USB2HCD and then USB3HCD resume will be called */
2617 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
2618 {
2619         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2620         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2621         int err = 0;
2622
2623         mutex_lock(&tegra->sync_lock);
2624
2625         tegra->host_resume_req = true;
2626
2627         if (xhci->shared_hcd == hcd)
2628                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
2629         else if (xhci->main_hcd == hcd)
2630                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
2631
2632         /* pads are disabled only if usb2 root hub in xusb is idle */
2633         /* pads will actually be disabled only when all usb2 ports are idle */
2634         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
2635                 utmi_phy_pad_enable();
2636                 utmi_phy_iddq_override(false);
2637                 tegra_xhci_release_port_ownership(tegra, false);
2638         } else if (xhci->shared_hcd == hcd && tegra->usb3_rh_suspend) {
2639                 /* clear ovrd bits */
2640                 tegra_xhci_rx_idle_mode_override(tegra, false);
2641         }
2642         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
2643                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
2644                         tegra_xhci_host_partition_elpg_exit(tegra);
2645         }
2646
2647          /* handle remote wakeup before resuming bus */
2648         wait_remote_wakeup_ports(hcd);
2649
2650         err = xhci_bus_resume(hcd);
2651         if (err) {
2652                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
2653                                 __func__, err);
2654                 goto xhci_bus_resume_failed;
2655         }
2656
2657         if (xhci->shared_hcd == hcd)
2658                 tegra->usb3_rh_suspend = false;
2659         else if (xhci->main_hcd == hcd)
2660                 tegra->usb2_rh_suspend = false;
2661
2662         mutex_unlock(&tegra->sync_lock);
2663         return 0;
2664
2665 xhci_bus_resume_failed:
2666         /* TODO: reverse elpg? */
2667         mutex_unlock(&tegra->sync_lock);
2668         return err;
2669 }
2670 #endif
2671
2672 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
2673 {
2674         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2675         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2676         irqreturn_t iret = IRQ_HANDLED;
2677         u32 status;
2678
2679         spin_lock(&tegra->lock);
2680         if (tegra->hc_in_elpg) {
2681                 spin_lock(&xhci->lock);
2682                 if (HCD_HW_ACCESSIBLE(hcd)) {
2683                         status = xhci_readl(xhci, &xhci->op_regs->status);
2684                         status |= STS_EINT;
2685                         xhci_writel(xhci, status, &xhci->op_regs->status);
2686                 }
2687                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
2688                                 __func__);
2689                 schedule_work(&tegra->host_elpg_exit_work);
2690                 spin_unlock(&xhci->lock);
2691         } else
2692                 iret = xhci_irq(hcd);
2693         spin_unlock(&tegra->lock);
2694
2695         return iret;
2696 }
2697
2698
2699 static const struct hc_driver tegra_plat_xhci_driver = {
2700         .description =          "tegra-xhci",
2701         .product_desc =         "Nvidia xHCI Host Controller",
2702         .hcd_priv_size =        sizeof(struct xhci_hcd *),
2703
2704         /*
2705          * generic hardware linkage
2706          */
2707         .irq =                  tegra_xhci_irq,
2708         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
2709
2710         /*
2711          * basic lifecycle operations
2712          */
2713         .reset =                xhci_plat_setup,
2714         .start =                xhci_run,
2715         .stop =                 xhci_stop,
2716         .shutdown =             xhci_shutdown,
2717
2718         /*
2719          * managing i/o requests and associated device resources
2720          */
2721         .urb_enqueue =          xhci_urb_enqueue,
2722         .urb_dequeue =          xhci_urb_dequeue,
2723         .alloc_dev =            xhci_alloc_dev,
2724         .free_dev =             xhci_free_dev,
2725         .alloc_streams =        xhci_alloc_streams,
2726         .free_streams =         xhci_free_streams,
2727         .add_endpoint =         xhci_add_endpoint,
2728         .drop_endpoint =        xhci_drop_endpoint,
2729         .endpoint_reset =       xhci_endpoint_reset,
2730         .check_bandwidth =      xhci_check_bandwidth,
2731         .reset_bandwidth =      xhci_reset_bandwidth,
2732         .address_device =       xhci_address_device,
2733         .update_hub_device =    xhci_update_hub_device,
2734         .reset_device =         xhci_discover_or_reset_device,
2735
2736         /*
2737          * scheduling support
2738          */
2739         .get_frame_number =     xhci_get_frame,
2740
2741         /* Root hub support */
2742         .hub_control =          xhci_hub_control,
2743         .hub_status_data =      xhci_hub_status_data,
2744
2745 #ifdef CONFIG_PM
2746         .bus_suspend =          tegra_xhci_bus_suspend,
2747         .bus_resume =           tegra_xhci_bus_resume,
2748 #endif
2749 };
2750
2751 #ifdef CONFIG_PM
2752 static int
2753 tegra_xhci_suspend(struct platform_device *pdev,
2754                                                 pm_message_t state)
2755 {
2756         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2757         struct xhci_hcd *xhci = tegra->xhci;
2758
2759         int ret = 0;
2760
2761         mutex_lock(&tegra->sync_lock);
2762         if (!tegra->hc_in_elpg) {
2763                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
2764                                 __func__);
2765                 mutex_unlock(&tegra->sync_lock);
2766                 return -EBUSY;
2767         }
2768         mutex_unlock(&tegra->sync_lock);
2769
2770         tegra_xhci_ss_wake_on_interrupts(tegra, false);
2771         tegra_xhci_hs_wake_on_interrupts(tegra, false);
2772
2773         /* enable_irq_wake for ss ports */
2774         ret = enable_irq_wake(tegra->padctl_irq);
2775         if (ret < 0) {
2776                 xhci_err(xhci,
2777                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
2778                 __func__, tegra->padctl_irq, ret);
2779         }
2780
2781         /* enable_irq_wake for hs/fs/ls ports */
2782         ret = enable_irq_wake(tegra->usb3_irq);
2783         if (ret < 0) {
2784                 xhci_err(xhci,
2785                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
2786                 __func__, tegra->usb3_irq, ret);
2787         }
2788         regulator_disable(tegra->xusb_avdd_usb3_pll_reg);
2789         regulator_disable(tegra->xusb_avddio_usb3_reg);
2790         tegra_usb2_clocks_deinit(tegra);
2791
2792         return ret;
2793 }
2794
2795 static int
2796 tegra_xhci_resume(struct platform_device *pdev)
2797 {
2798         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2799
2800         dev_dbg(&pdev->dev, "%s\n", __func__);
2801
2802         tegra->last_jiffies = jiffies;
2803
2804         disable_irq_wake(tegra->padctl_irq);
2805         disable_irq_wake(tegra->usb3_irq);
2806         tegra->lp0_exit = true;
2807
2808         regulator_enable(tegra->xusb_avddio_usb3_reg);
2809         regulator_enable(tegra->xusb_avdd_usb3_pll_reg);
2810         tegra_usb2_clocks_init(tegra);
2811
2812         return 0;
2813 }
2814 #endif
2815
2816
2817 static int init_bootloader_firmware(struct tegra_xhci_hcd *tegra)
2818 {
2819         struct platform_device *pdev = tegra->pdev;
2820         void __iomem *fw_mmio_base;
2821         phys_addr_t fw_mem_phy_addr;
2822         size_t fw_size;
2823         dma_addr_t fw_dma;
2824 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2825         int ret;
2826 #endif
2827
2828         /* bootloader saved firmware memory address in PMC SCRATCH34 register */
2829         fw_mem_phy_addr = tegra_usb_pmc_reg_read(PMC_SCRATCH34);
2830
2831         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
2832                         fw_mem_phy_addr, sizeof(struct cfgtbl));
2833
2834         if (!fw_mmio_base) {
2835                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
2836                                         fw_mem_phy_addr);
2837                         return -ENOMEM;
2838         }
2839
2840         fw_size = ioread32(fw_mmio_base + FW_SIZE_OFFSET);
2841         devm_iounmap(&pdev->dev, fw_mmio_base);
2842
2843         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
2844                         fw_mem_phy_addr, fw_size);
2845         if (!fw_mmio_base) {
2846                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
2847                                         fw_mem_phy_addr);
2848                         return -ENOMEM;
2849         }
2850
2851         dev_info(&pdev->dev, "Firmware Memory: phy 0x%x mapped 0x%p (%d Bytes)\n",
2852                         fw_mem_phy_addr, fw_mmio_base, fw_size);
2853
2854 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2855         fw_dma = dma_map_linear(&pdev->dev, fw_mem_phy_addr, fw_size,
2856                         DMA_TO_DEVICE);
2857         if (fw_dma == DMA_ERROR_CODE) {
2858                 dev_err(&pdev->dev, "%s: dma_map_linear failed\n",
2859                                 __func__);
2860                 ret = -ENOMEM;
2861                 goto error_iounmap;
2862         }
2863 #else
2864         fw_dma = fw_mem_phy_addr;
2865 #endif
2866         dev_info(&pdev->dev, "Firmware DMA Memory: dma 0x%p (%d Bytes)\n",
2867                         (void *) fw_dma, fw_size);
2868
2869         /* all set and ready to go */
2870         tegra->firmware.data = fw_mmio_base;
2871         tegra->firmware.dma = fw_dma;
2872         tegra->firmware.size = fw_size;
2873
2874         return 0;
2875
2876 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2877 error_iounmap:
2878         devm_iounmap(&pdev->dev, fw_mmio_base);
2879         return ret;
2880 #endif
2881 }
2882
2883 static void deinit_bootloader_firmware(struct tegra_xhci_hcd *tegra)
2884 {
2885         struct platform_device *pdev = tegra->pdev;
2886         void __iomem *fw_mmio_base = tegra->firmware.data;
2887
2888 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2889         dma_unmap_single(&pdev->dev, tegra->firmware.dma,
2890                         tegra->firmware.size, DMA_TO_DEVICE);
2891 #endif
2892         devm_iounmap(&pdev->dev, fw_mmio_base);
2893
2894         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
2895 }
2896
2897 static int init_firmware(struct tegra_xhci_hcd *tegra)
2898 {
2899         return init_bootloader_firmware(tegra);
2900 }
2901
2902 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
2903 {
2904         deinit_bootloader_firmware(tegra);
2905 }
2906
2907 static struct tegra_xusb_padctl_regs t114_padregs_offset = {
2908         .boot_media_0                   = 0x0,
2909         .usb2_pad_mux_0                 = 0x4,
2910         .usb2_port_cap_0                = 0x8,
2911         .snps_oc_map_0                  = 0xc,
2912         .usb2_oc_map_0                  = 0x10,
2913         .ss_port_map_0                  = 0x14,
2914         .oc_det_0                       = 0x18,
2915         .elpg_program_0                 = 0x1c,
2916         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
2917         .usb2_bchrg_otgpad0_ctl1_0      = 0xffff,
2918         .usb2_bchrg_otgpad1_ctl0_0      = 0x24,
2919         .usb2_bchrg_otgpad1_ctl1_0      = 0xffff,
2920         .usb2_bchrg_otgpad2_ctl0_0      = 0xffff,
2921         .usb2_bchrg_otgpad2_ctl1_0      = 0xffff,
2922         .usb2_bchrg_bias_pad_0          = 0x28,
2923         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
2924         .iophy_pll_p0_ctl1_0            = 0x30,
2925         .iophy_pll_p0_ctl2_0            = 0x34,
2926         .iophy_pll_p0_ctl3_0            = 0x38,
2927         .iophy_pll_p0_ctl4_0            = 0x3c,
2928         .iophy_usb3_pad0_ctl1_0         = 0x40,
2929         .iophy_usb3_pad1_ctl1_0         = 0x44,
2930         .iophy_usb3_pad0_ctl2_0         = 0x48,
2931         .iophy_usb3_pad1_ctl2_0         = 0x4c,
2932         .iophy_usb3_pad0_ctl3_0         = 0x50,
2933         .iophy_usb3_pad1_ctl3_0         = 0x54,
2934         .iophy_usb3_pad0_ctl4_0         = 0x58,
2935         .iophy_usb3_pad1_ctl4_0         = 0x5c,
2936         .iophy_misc_pad_p0_ctl1_0       = 0x60,
2937         .iophy_misc_pad_p1_ctl1_0       = 0x64,
2938         .iophy_misc_pad_p0_ctl2_0       = 0x68,
2939         .iophy_misc_pad_p1_ctl2_0       = 0x6c,
2940         .iophy_misc_pad_p0_ctl3_0       = 0x70,
2941         .iophy_misc_pad_p1_ctl3_0       = 0x74,
2942         .iophy_misc_pad_p0_ctl4_0       = 0x78,
2943         .iophy_misc_pad_p1_ctl4_0       = 0x7c,
2944         .iophy_misc_pad_p0_ctl5_0       = 0x80,
2945         .iophy_misc_pad_p1_ctl5_0       = 0x84,
2946         .iophy_misc_pad_p0_ctl6_0       = 0x88,
2947         .iophy_misc_pad_p1_ctl6_0       = 0x8c,
2948         .usb2_otg_pad0_ctl0_0           = 0x90,
2949         .usb2_otg_pad1_ctl0_0           = 0x94,
2950         .usb2_otg_pad2_ctl0_0           = 0xffff,
2951         .usb2_otg_pad0_ctl1_0           = 0x98,
2952         .usb2_otg_pad1_ctl1_0           = 0x9c,
2953         .usb2_otg_pad2_ctl1_0           = 0xffff,
2954         .usb2_bias_pad_ctl0_0           = 0xa0,
2955         .usb2_bias_pad_ctl1_0           = 0xa4,
2956         .usb2_hsic_pad0_ctl0_0          = 0xa8,
2957         .usb2_hsic_pad1_ctl0_0          = 0xac,
2958         .usb2_hsic_pad0_ctl1_0          = 0xb0,
2959         .usb2_hsic_pad1_ctl1_0          = 0xb4,
2960         .usb2_hsic_pad0_ctl2_0          = 0xb8,
2961         .usb2_hsic_pad1_ctl2_0          = 0xbc,
2962         .ulpi_link_trim_ctl0            = 0xc0,
2963         .ulpi_null_clk_trim_ctl0        = 0xc4,
2964         .hsic_strb_trim_ctl0            = 0xc8,
2965         .wake_ctl0                      = 0xcc,
2966         .pm_spare0                      = 0xd0,
2967         .iophy_misc_pad_p2_ctl1_0       = 0xffff,
2968         .iophy_misc_pad_p3_ctl1_0       = 0xffff,
2969         .iophy_misc_pad_p4_ctl1_0       = 0xffff,
2970         .iophy_misc_pad_p2_ctl2_0       = 0xffff,
2971         .iophy_misc_pad_p3_ctl2_0       = 0xffff,
2972         .iophy_misc_pad_p4_ctl2_0       = 0xffff,
2973         .iophy_misc_pad_p2_ctl3_0       = 0xffff,
2974         .iophy_misc_pad_p3_ctl3_0       = 0xffff,
2975         .iophy_misc_pad_p4_ctl3_0       = 0xffff,
2976         .iophy_misc_pad_p2_ctl4_0       = 0xffff,
2977         .iophy_misc_pad_p3_ctl4_0       = 0xffff,
2978         .iophy_misc_pad_p4_ctl4_0       = 0xffff,
2979         .iophy_misc_pad_p2_ctl5_0       = 0xffff,
2980         .iophy_misc_pad_p3_ctl5_0       = 0xffff,
2981         .iophy_misc_pad_p4_ctl5_0       = 0xffff,
2982         .iophy_misc_pad_p2_ctl6_0       = 0xffff,
2983         .iophy_misc_pad_p3_ctl6_0       = 0xffff,
2984         .iophy_misc_pad_p4_ctl6_0       = 0xffff,
2985         .usb3_pad_mux_0                 = 0xffff,
2986         .iophy_pll_s0_ctl1_0            = 0xffff,
2987         .iophy_pll_s0_ctl2_0            = 0xffff,
2988         .iophy_pll_s0_ctl3_0            = 0xffff,
2989         .iophy_pll_s0_ctl4_0            = 0xffff,
2990         .iophy_misc_pad_s0_ctl1_0       = 0xffff,
2991         .iophy_misc_pad_s0_ctl2_0       = 0xffff,
2992         .iophy_misc_pad_s0_ctl3_0       = 0xffff,
2993         .iophy_misc_pad_s0_ctl4_0       = 0xffff,
2994         .iophy_misc_pad_s0_ctl5_0       = 0xffff,
2995         .iophy_misc_pad_s0_ctl6_0       = 0xffff,
2996 };
2997
2998 static struct tegra_xusb_padctl_regs t124_padregs_offset = {
2999         .boot_media_0                   = 0x0,
3000         .usb2_pad_mux_0                 = 0x4,
3001         .usb2_port_cap_0                = 0x8,
3002         .snps_oc_map_0                  = 0xc,
3003         .usb2_oc_map_0                  = 0x10,
3004         .ss_port_map_0                  = 0x14,
3005         .oc_det_0                       = 0x18,
3006         .elpg_program_0                 = 0x1c,
3007         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3008         .usb2_bchrg_otgpad0_ctl1_0      = 0x24,
3009         .usb2_bchrg_otgpad1_ctl0_0      = 0x28,
3010         .usb2_bchrg_otgpad1_ctl1_0      = 0x2c,
3011         .usb2_bchrg_otgpad2_ctl0_0      = 0x30,
3012         .usb2_bchrg_otgpad2_ctl1_0      = 0x34,
3013         .usb2_bchrg_bias_pad_0          = 0x38,
3014         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
3015         .iophy_pll_p0_ctl1_0            = 0x40,
3016         .iophy_pll_p0_ctl2_0            = 0x44,
3017         .iophy_pll_p0_ctl3_0            = 0x48,
3018         .iophy_pll_p0_ctl4_0            = 0x4c,
3019         .iophy_usb3_pad0_ctl1_0         = 0x50,
3020         .iophy_usb3_pad1_ctl1_0         = 0x54,
3021         .iophy_usb3_pad0_ctl2_0         = 0x58,
3022         .iophy_usb3_pad1_ctl2_0         = 0x5c,
3023         .iophy_usb3_pad0_ctl3_0         = 0x60,
3024         .iophy_usb3_pad1_ctl3_0         = 0x64,
3025         .iophy_usb3_pad0_ctl4_0         = 0x68,
3026         .iophy_usb3_pad1_ctl4_0         = 0x6c,
3027         .iophy_misc_pad_p0_ctl1_0       = 0x70,
3028         .iophy_misc_pad_p1_ctl1_0       = 0x74,
3029         .iophy_misc_pad_p0_ctl2_0       = 0x78,
3030         .iophy_misc_pad_p1_ctl2_0       = 0x7c,
3031         .iophy_misc_pad_p0_ctl3_0       = 0x80,
3032         .iophy_misc_pad_p1_ctl3_0       = 0x84,
3033         .iophy_misc_pad_p0_ctl4_0       = 0x88,
3034         .iophy_misc_pad_p1_ctl4_0       = 0x8c,
3035         .iophy_misc_pad_p0_ctl5_0       = 0x90,
3036         .iophy_misc_pad_p1_ctl5_0       = 0x94,
3037         .iophy_misc_pad_p0_ctl6_0       = 0x98,
3038         .iophy_misc_pad_p1_ctl6_0       = 0x9c,
3039         .usb2_otg_pad0_ctl0_0           = 0xa0,
3040         .usb2_otg_pad1_ctl0_0           = 0xa4,
3041         .usb2_otg_pad2_ctl0_0           = 0xa8,
3042         .usb2_otg_pad0_ctl1_0           = 0xac,
3043         .usb2_otg_pad1_ctl1_0           = 0xb0,
3044         .usb2_otg_pad2_ctl1_0           = 0xb4,
3045         .usb2_bias_pad_ctl0_0           = 0xb8,
3046         .usb2_bias_pad_ctl1_0           = 0xbc,
3047         .usb2_hsic_pad0_ctl0_0          = 0xc0,
3048         .usb2_hsic_pad1_ctl0_0          = 0xc4,
3049         .usb2_hsic_pad0_ctl1_0          = 0xc8,
3050         .usb2_hsic_pad1_ctl1_0          = 0xcc,
3051         .usb2_hsic_pad0_ctl2_0          = 0xd0,
3052         .usb2_hsic_pad1_ctl2_0          = 0xd4,
3053         .ulpi_link_trim_ctl0            = 0xd8,
3054         .ulpi_null_clk_trim_ctl0        = 0xdc,
3055         .hsic_strb_trim_ctl0            = 0xe0,
3056         .wake_ctl0                      = 0xe4,
3057         .pm_spare0                      = 0xe8,
3058         .iophy_misc_pad_p2_ctl1_0       = 0xec,
3059         .iophy_misc_pad_p3_ctl1_0       = 0xf0,
3060         .iophy_misc_pad_p4_ctl1_0       = 0xf4,
3061         .iophy_misc_pad_p2_ctl2_0       = 0xf8,
3062         .iophy_misc_pad_p3_ctl2_0       = 0xfc,
3063         .iophy_misc_pad_p4_ctl2_0       = 0x100,
3064         .iophy_misc_pad_p2_ctl3_0       = 0x104,
3065         .iophy_misc_pad_p3_ctl3_0       = 0x108,
3066         .iophy_misc_pad_p4_ctl3_0       = 0x10c,
3067         .iophy_misc_pad_p2_ctl4_0       = 0x110,
3068         .iophy_misc_pad_p3_ctl4_0       = 0x114,
3069         .iophy_misc_pad_p4_ctl4_0       = 0x118,
3070         .iophy_misc_pad_p2_ctl5_0       = 0x11c,
3071         .iophy_misc_pad_p3_ctl5_0       = 0x120,
3072         .iophy_misc_pad_p4_ctl5_0       = 0x124,
3073         .iophy_misc_pad_p2_ctl6_0       = 0x128,
3074         .iophy_misc_pad_p3_ctl6_0       = 0x12c,
3075         .iophy_misc_pad_p4_ctl6_0       = 0x130,
3076         .usb3_pad_mux_0                 = 0x134,
3077         .iophy_pll_s0_ctl1_0            = 0x138,
3078         .iophy_pll_s0_ctl2_0            = 0x13c,
3079         .iophy_pll_s0_ctl3_0            = 0x140,
3080         .iophy_pll_s0_ctl4_0            = 0x144,
3081         .iophy_misc_pad_s0_ctl1_0       = 0x148,
3082         .iophy_misc_pad_s0_ctl2_0       = 0x14c,
3083         .iophy_misc_pad_s0_ctl3_0       = 0x150,
3084         .iophy_misc_pad_s0_ctl4_0       = 0x154,
3085         .iophy_misc_pad_s0_ctl5_0       = 0x158,
3086         .iophy_misc_pad_s0_ctl6_0       = 0x15c,
3087 };
3088
3089 /* TODO: we have to refine error handling in tegra_xhci_probe() */
3090 static int tegra_xhci_probe(struct platform_device *pdev)
3091 {
3092         const struct hc_driver *driver;
3093         struct xhci_hcd *xhci;
3094         struct tegra_xhci_hcd *tegra;
3095         struct resource *res;
3096         struct usb_hcd  *hcd;
3097         u32 pmc_reg, val;
3098         int ret;
3099         int irq;
3100
3101         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
3102
3103         if (usb_disabled())
3104                 return -ENODEV;
3105
3106         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
3107         if (!tegra) {
3108                 dev_err(&pdev->dev, "memory alloc failed\n");
3109                 return -ENOMEM;
3110         }
3111         tegra->pdev = pdev;
3112         tegra->pdata = dev_get_platdata(&pdev->dev);
3113         tegra->bdata = tegra->pdata->bdata;
3114
3115         ret = tegra_xhci_request_mem_region(pdev, "padctl",
3116                         &tegra->padctl_base);
3117         if (ret) {
3118                 dev_err(&pdev->dev, "failed to map padctl\n");
3119                 return ret;
3120         }
3121
3122         ret = tegra_xhci_request_mem_region(pdev, "fpci", &tegra->fpci_base);
3123         if (ret) {
3124                 dev_err(&pdev->dev, "failed to map fpci\n");
3125                 return ret;
3126         }
3127
3128         ret = tegra_xhci_request_mem_region(pdev, "ipfs", &tegra->ipfs_base);
3129         if (ret) {
3130                 dev_err(&pdev->dev, "failed to map ipfs\n");
3131                 return ret;
3132         }
3133
3134         ret = tegra_xusb_partitions_clk_init(tegra);
3135         if (ret) {
3136                 dev_err(&pdev->dev,
3137                         "failed to initialize xusb partitions clocks\n");
3138                 return ret;
3139         }
3140
3141         /* Enable power rails to the PAD,VBUS
3142          * and pull-up voltage.Initialize the regulators
3143          */
3144         ret = tegra_xusb_regulator_init(tegra, pdev);
3145         if (ret) {
3146                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
3147                 goto err_deinit_xusb_partition_clk;
3148         }
3149
3150         /* Enable UTMIP, PLLU and PLLE */
3151         ret = tegra_usb2_clocks_init(tegra);
3152         if (ret) {
3153                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
3154                 goto err_deinit_tegra_xusb_regulator;
3155         }
3156
3157         /* tegra_unpowergate_partition also does partition reset deassert */
3158         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
3159         if (ret)
3160                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
3161
3162         /* tegra_unpowergate_partition also does partition reset deassert */
3163         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3164         if (ret)
3165                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
3166
3167         /* reset the pointer back to NULL. driver uses it */
3168         /* platform_set_drvdata(pdev, NULL); */
3169
3170         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "host");
3171         if (!res) {
3172                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
3173                 ret = -ENODEV;
3174                 goto err_deinit_usb2_clocks;
3175         }
3176         tegra->host_phy_base = res->start;
3177
3178         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
3179                                 res->start, resource_size(res));
3180         if (!tegra->host_phy_virt_base) {
3181                 dev_err(&pdev->dev, "error mapping host phy memory\n");
3182                 ret = -ENOMEM;
3183                 goto err_deinit_usb2_clocks;
3184         }
3185
3186         /* Setup IPFS access and BAR0 space */
3187         tegra_xhci_cfg(tegra);
3188
3189         val = readl(tegra->fpci_base + XUSB_CFG_0);
3190         tegra->device_id = (val >> 16) & 0xffff;
3191
3192         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
3193                 (XUSB_DEVICE_ID_T114 == tegra->device_id) ? "T114" : "T124+");
3194
3195         if (XUSB_DEVICE_ID_T114 == tegra->device_id) {
3196                 tegra->padregs = &t114_padregs_offset;
3197         } else if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
3198                 tegra->padregs = &t124_padregs_offset;
3199         } else {
3200                 dev_info(&pdev->dev, "XUSB device_id neither T114 nor T124!\n");
3201                 dev_info(&pdev->dev, "XUSB using T124 pad register offsets!\n");
3202                 tegra->padregs = &t124_padregs_offset;
3203         }
3204
3205         /* calculate rctrl_val and tctrl_val once at boot time */
3206         tegra_xhci_war_for_tctrl_rctrl(tegra);
3207
3208         /* Program the XUSB pads to take ownership of ports */
3209         tegra_xhci_padctl_portmap_and_caps(tegra);
3210
3211         /* Release XUSB wake logic state latching */
3212         tegra_xhci_ss_wake_signal(tegra, false);
3213         tegra_xhci_ss_vcore(tegra, false);
3214
3215         /* Deassert reset to XUSB host, ss, dev clocks */
3216         tegra_periph_reset_deassert(tegra->host_clk);
3217         tegra_periph_reset_deassert(tegra->ss_clk);
3218
3219         ret = init_firmware(tegra);
3220         if (ret < 0) {
3221                 dev_err(&pdev->dev, "failed to init firmware\n");
3222                 ret = -ENODEV;
3223                 goto err_deinit_usb2_clocks;
3224         }
3225
3226         ret = load_firmware(tegra, true /* do reset ARU */);
3227         if (ret < 0) {
3228                 dev_err(&pdev->dev, "failed to load firmware\n");
3229                 ret = -ENODEV;
3230                 goto err_deinit_firmware;
3231         }
3232
3233         device_init_wakeup(&pdev->dev, 1);
3234         driver = &tegra_plat_xhci_driver;
3235
3236         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
3237         if (!hcd) {
3238                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
3239                 ret = -ENOMEM;
3240                 goto err_deinit_firmware;
3241         }
3242
3243         ret = tegra_xhci_request_mem_region(pdev, "host", &hcd->regs);
3244         if (ret) {
3245                 dev_err(&pdev->dev, "failed to map host\n");
3246                 goto err_put_usb2_hcd;
3247         }
3248         hcd->rsrc_start = res->start;
3249         hcd->rsrc_len = resource_size(res);
3250
3251         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "host");
3252         if (!res) {
3253                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
3254                 ret = -ENODEV;
3255                 goto err_put_usb2_hcd;
3256         }
3257         irq = res->start;
3258         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
3259         if (ret) {
3260                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
3261                 goto err_put_usb2_hcd;
3262         }
3263
3264         /* USB 2.0 roothub is stored in the platform_device now. */
3265         hcd = dev_get_drvdata(&pdev->dev);
3266         xhci = hcd_to_xhci(hcd);
3267         tegra->xhci = xhci;
3268         platform_set_drvdata(pdev, tegra);
3269
3270         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
3271                                                 dev_name(&pdev->dev), hcd);
3272         if (!xhci->shared_hcd) {
3273                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
3274                 ret = -ENOMEM;
3275                 goto err_remove_usb2_hcd;
3276         }
3277
3278         /*
3279          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
3280          * is called by usb_add_hcd().
3281          */
3282         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
3283
3284         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
3285         if (ret) {
3286                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
3287                 goto err_put_usb3_hcd;
3288         }
3289
3290         device_init_wakeup(&hcd->self.root_hub->dev, 1);
3291         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
3292         spin_lock_init(&tegra->lock);
3293         mutex_init(&tegra->sync_lock);
3294         mutex_init(&tegra->mbox_lock);
3295
3296         /* do mailbox related initializations */
3297         tegra->mbox_owner = 0xffff;
3298         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
3299
3300         tegra_xhci_enable_fw_message(tegra);
3301
3302         /* do ss partition elpg exit related initialization */
3303         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
3304
3305         /* do host partition elpg exit related initialization */
3306         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
3307
3308         /* Register interrupt handler for SMI line to handle mailbox
3309          * interrupt from firmware
3310          */
3311         ret = tegra_xhci_request_irq(pdev, "host-smi", tegra_xhci_smi_irq,
3312                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
3313         if (ret != 0)
3314                 goto err_remove_usb3_hcd;
3315
3316         /* Register interrupt handler for PADCTRL line to
3317          * handle wake on connect irqs interrupt from
3318          * firmware
3319          */
3320         ret = tegra_xhci_request_irq(pdev, "padctl", tegra_xhci_padctl_irq,
3321                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
3322                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
3323         if (ret != 0)
3324                 goto err_remove_usb3_hcd;
3325
3326         ret = tegra_xhci_request_irq(pdev, "usb3", tegra_xhci_xusb_host_irq,
3327                         IRQF_SHARED | IRQF_TRIGGER_HIGH, "xusb_host_irq",
3328                         &tegra->usb3_irq);
3329         if (ret != 0)
3330                 goto err_remove_usb3_hcd;
3331
3332         tegra->ss_pwr_gated = false;
3333         tegra->host_pwr_gated = false;
3334         tegra->hc_in_elpg = false;
3335         tegra->hs_wake_event = false;
3336         tegra->host_resume_req = false;
3337         tegra->lp0_exit = false;
3338         tegra->dfe_ctle_ctx_saved = false;
3339
3340         /* reset wake event to NONE */
3341         pmc_reg = tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0);
3342         pmc_reg |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE);
3343         pmc_reg |= UTMIP_WAKE_VAL(1, WAKE_VAL_NONE);
3344         pmc_reg |= UTMIP_WAKE_VAL(2, WAKE_VAL_NONE);
3345         pmc_reg |= UTMIP_WAKE_VAL(3, WAKE_VAL_NONE);
3346         tegra_usb_pmc_reg_write(PMC_UTMIP_UHSIC_SLEEP_CFG_0, pmc_reg);
3347
3348         tegra_xhci_debug_read_pads(tegra);
3349         utmi_phy_pad_enable();
3350         utmi_phy_iddq_override(false);
3351
3352         tegra_pd_add_device(&pdev->dev);
3353
3354         return 0;
3355
3356 err_remove_usb3_hcd:
3357         usb_remove_hcd(xhci->shared_hcd);
3358 err_put_usb3_hcd:
3359         usb_put_hcd(xhci->shared_hcd);
3360 err_remove_usb2_hcd:
3361         kfree(tegra->xhci);
3362         usb_remove_hcd(hcd);
3363 err_put_usb2_hcd:
3364         usb_put_hcd(hcd);
3365 err_deinit_firmware:
3366         deinit_firmware(tegra);
3367 err_deinit_usb2_clocks:
3368         tegra_usb2_clocks_deinit(tegra);
3369 err_deinit_tegra_xusb_regulator:
3370         tegra_xusb_regulator_deinit(tegra);
3371 err_deinit_xusb_partition_clk:
3372         tegra_xusb_partitions_clk_deinit(tegra);
3373
3374         return ret;
3375 }
3376
3377 static int tegra_xhci_remove(struct platform_device *pdev)
3378 {
3379         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3380         struct xhci_hcd *xhci = NULL;
3381         struct usb_hcd *hcd = NULL;
3382
3383         if (tegra == NULL)
3384                 return -EINVAL;
3385
3386         xhci = tegra->xhci;
3387         hcd = xhci_to_hcd(xhci);
3388
3389         devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
3390         devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
3391         devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
3392         usb_remove_hcd(xhci->shared_hcd);
3393         usb_put_hcd(xhci->shared_hcd);
3394         usb_remove_hcd(hcd);
3395         usb_put_hcd(hcd);
3396         kfree(xhci);
3397
3398         deinit_firmware(tegra);
3399         tegra_xusb_regulator_deinit(tegra);
3400         tegra_usb2_clocks_deinit(tegra);
3401         if (!tegra->hc_in_elpg)
3402                 tegra_xusb_partitions_clk_deinit(tegra);
3403         utmi_phy_pad_disable();
3404         utmi_phy_iddq_override(true);
3405
3406         return 0;
3407 }
3408
3409 static void tegra_xhci_shutdown(struct platform_device *pdev)
3410 {
3411         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3412         struct xhci_hcd *xhci = NULL;
3413         struct usb_hcd *hcd = NULL;
3414
3415         if (tegra == NULL)
3416                 return;
3417
3418         if (tegra->hc_in_elpg) {
3419                 mutex_lock(&tegra->sync_lock);
3420                 tegra_xhci_host_partition_elpg_exit(tegra);
3421                 mutex_unlock(&tegra->sync_lock);
3422         }
3423         xhci = tegra->xhci;
3424         hcd = xhci_to_hcd(xhci);
3425         xhci_shutdown(hcd);
3426 }
3427
3428 static struct platform_driver tegra_xhci_driver = {
3429         .probe  = tegra_xhci_probe,
3430         .remove = tegra_xhci_remove,
3431         .shutdown = tegra_xhci_shutdown,
3432 #ifdef CONFIG_PM
3433         .suspend = tegra_xhci_suspend,
3434         .resume  = tegra_xhci_resume,
3435 #endif
3436         .driver = {
3437                 .name = "tegra-xhci",
3438         },
3439 };
3440 MODULE_ALIAS("platform:tegra-xhci");
3441
3442 int tegra_xhci_register_plat(void)
3443 {
3444         return platform_driver_register(&tegra_xhci_driver);
3445 }
3446
3447 void tegra_xhci_unregister_plat(void)
3448 {
3449         platform_driver_unregister(&tegra_xhci_driver);
3450 }