usb: xhci: tegra: pass regulator name from board file
[linux-3.10.git] / drivers / usb / host / xhci-tegra.c
1 /*
2  * xhci-tegra.c - Nvidia xHCI host controller driver
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/clk.h>
24 #include <linux/ioport.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irq.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/uaccess.h>
30 #include <linux/gpio.h>
31
32 #include <mach/powergate.h>
33 #include <mach/clk.h>
34 #include <mach/tegra_usb_pad_ctrl.h>
35 #include <mach/tegra_usb_pmc.h>
36 #include <mach/pm_domains.h>
37 #include <mach/mc.h>
38 #include <mach/xusb.h>
39
40 #include "../../../arch/arm/mach-tegra/iomap.h" /* HACK -- remove */
41 #include "xhci-tegra.h"
42 #include "xhci.h"
43
44 /* macros */
45 #define PAGE_SELECT_MASK                        0xFFFFFE00
46 #define PAGE_SELECT_SHIFT                       9
47 #define PAGE_OFFSET_MASK                        0x000001FF
48 #define CSB_PAGE_SELECT(_addr)                                          \
49         ({                                                              \
50                 typecheck(u32, _addr);                                  \
51                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
52         })
53 #define CSB_PAGE_OFFSET(_addr)                                          \
54         ({                                                              \
55                 typecheck(u32, _addr);                                  \
56                 (_addr & PAGE_OFFSET_MASK);                             \
57         })
58
59 /* PMC register definition */
60 #define PMC_PORT_UTMIP_P0               0
61 #define PMC_PORT_UTMIP_P1               1
62 #define PMC_PORT_UTMIP_P2               2
63 #define PMC_PORT_UHSIC_P0               3
64 #define PMC_PORT_NUM                    4
65
66 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
67 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
68 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
69
70 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
71
72 /* private data types */
73 /* command requests from the firmware */
74 enum MBOX_CMD_TYPE {
75         MBOX_CMD_MSG_ENABLED = 1,
76         MBOX_CMD_INC_FALC_CLOCK,
77         MBOX_CMD_DEC_FALC_CLOCK,
78         MBOX_CMD_INC_SSPI_CLOCK,
79         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
80         MBOX_CMD_SET_BW,
81         MBOX_CMD_SET_SS_PWR_GATING,
82         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
83         MBOX_CMD_SAVE_DFE_CTLE_CTX,
84
85         /* needs to be the last cmd */
86         MBOX_CMD_MAX,
87
88         /* resp msg to ack above commands */
89         MBOX_CMD_ACK = 128,
90         MBOX_CMD_NACK
91 };
92
93 /* Usb3 Firmware Cfg Table */
94 struct cfgtbl {
95         u32 boot_loadaddr_in_imem;
96         u32 boot_codedfi_offset;
97         u32 boot_codetag;
98         u32 boot_codesize;
99
100         /* Physical memory reserved by Bootloader/BIOS */
101         u32 phys_memaddr;
102         u16 reqphys_memsize;
103         u16 alloc_phys_memsize;
104
105         /* .rodata section */
106         u32 rodata_img_offset;
107         u32 rodata_section_start;
108         u32 rodata_section_end;
109         u32 main_fnaddr;
110
111         u32 fwimg_cksum;
112         u32 fwimg_created_time;
113
114         /* Fields that get filled by linker during linking phase
115          * or initialized in the FW code.
116          */
117         u32 imem_resident_start;
118         u32 imem_resident_end;
119         u32 idirect_start;
120         u32 idirect_end;
121         u32 l2_imem_start;
122         u32 l2_imem_end;
123         u32 version_id;
124         u8 init_ddirect;
125         u8 reserved[3];
126         u32 phys_addr_log_buffer;
127         u32 total_log_entries;
128         u32 dequeue_ptr;
129
130         /*      Below two dummy variables are used to replace
131          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
132          *      retain the size of struct _CFG_TBL used by other AP/Module.
133          */
134         u32 dummy_var1;
135         u32 dummy_var2;
136
137         /* fwimg_len */
138         u32 fwimg_len;
139         u8 magic[8];
140         u32 SS_low_power_entry_timeout;
141         u8 padding[140]; /* padding bytes to makeup 256-bytes cfgtbl */
142 };
143
144 struct xusb_save_regs {
145         u32 msi_bar_sz;
146         u32 msi_axi_barst;
147         u32 msi_fpci_barst;
148         u32 msi_vec0;
149         u32 msi_en_vec0;
150         u32 fpci_error_masks;
151         u32 intr_mask;
152         u32 ipfs_intr_enable;
153         u32 ufpci_config;
154         u32 clkgate_hysteresis;
155         u32 xusb_host_mccif_fifo_cntrl;
156
157         /* PG does not mention below */
158         u32 hs_pls;
159         u32 fs_pls;
160         u32 hs_fs_speed;
161         u32 hs_fs_pp;
162         u32 cfg_aru;
163         u32 cfg_order;
164         u32 cfg_fladj;
165         u32 cfg_sid;
166         /* DFE and CTLE */
167         u32 tap1_val[2];
168         u32 amp_val[2];
169         u32 ctle_z_val[2];
170         u32 ctle_g_val[2];
171 };
172
173 struct tegra_xhci_firmware {
174         void *data; /* kernel virtual address */
175         size_t size; /* firmware size */
176         dma_addr_t dma; /* dma address for controller */
177 };
178
179 /* structure to hold the offsets of padctl registers */
180 struct tegra_xusb_padctl_regs {
181         u16 boot_media_0;
182         u16 usb2_pad_mux_0;
183         u16 usb2_port_cap_0;
184         u16 snps_oc_map_0;
185         u16 usb2_oc_map_0;
186         u16 ss_port_map_0;
187         u16 oc_det_0;
188         u16 elpg_program_0;
189         u16 usb2_bchrg_otgpad0_ctl0_0;
190         u16 usb2_bchrg_otgpad0_ctl1_0;
191         u16 usb2_bchrg_otgpad1_ctl0_0;
192         u16 usb2_bchrg_otgpad1_ctl1_0;
193         u16 usb2_bchrg_otgpad2_ctl0_0;
194         u16 usb2_bchrg_otgpad2_ctl1_0;
195         u16 usb2_bchrg_bias_pad_0;
196         u16 usb2_bchrg_tdcd_dbnc_timer_0;
197         u16 iophy_pll_p0_ctl1_0;
198         u16 iophy_pll_p0_ctl2_0;
199         u16 iophy_pll_p0_ctl3_0;
200         u16 iophy_pll_p0_ctl4_0;
201         u16 iophy_usb3_pad0_ctl1_0;
202         u16 iophy_usb3_pad1_ctl1_0;
203         u16 iophy_usb3_pad0_ctl2_0;
204         u16 iophy_usb3_pad1_ctl2_0;
205         u16 iophy_usb3_pad0_ctl3_0;
206         u16 iophy_usb3_pad1_ctl3_0;
207         u16 iophy_usb3_pad0_ctl4_0;
208         u16 iophy_usb3_pad1_ctl4_0;
209         u16 iophy_misc_pad_p0_ctl1_0;
210         u16 iophy_misc_pad_p1_ctl1_0;
211         u16 iophy_misc_pad_p0_ctl2_0;
212         u16 iophy_misc_pad_p1_ctl2_0;
213         u16 iophy_misc_pad_p0_ctl3_0;
214         u16 iophy_misc_pad_p1_ctl3_0;
215         u16 iophy_misc_pad_p0_ctl4_0;
216         u16 iophy_misc_pad_p1_ctl4_0;
217         u16 iophy_misc_pad_p0_ctl5_0;
218         u16 iophy_misc_pad_p1_ctl5_0;
219         u16 iophy_misc_pad_p0_ctl6_0;
220         u16 iophy_misc_pad_p1_ctl6_0;
221         u16 usb2_otg_pad0_ctl0_0;
222         u16 usb2_otg_pad1_ctl0_0;
223         u16 usb2_otg_pad2_ctl0_0;
224         u16 usb2_otg_pad0_ctl1_0;
225         u16 usb2_otg_pad1_ctl1_0;
226         u16 usb2_otg_pad2_ctl1_0;
227         u16 usb2_bias_pad_ctl0_0;
228         u16 usb2_bias_pad_ctl1_0;
229         u16 usb2_hsic_pad0_ctl0_0;
230         u16 usb2_hsic_pad1_ctl0_0;
231         u16 usb2_hsic_pad0_ctl1_0;
232         u16 usb2_hsic_pad1_ctl1_0;
233         u16 usb2_hsic_pad0_ctl2_0;
234         u16 usb2_hsic_pad1_ctl2_0;
235         u16 ulpi_link_trim_ctl0;
236         u16 ulpi_null_clk_trim_ctl0;
237         u16 hsic_strb_trim_ctl0;
238         u16 wake_ctl0;
239         u16 pm_spare0;
240         u16 iophy_misc_pad_p2_ctl1_0;
241         u16 iophy_misc_pad_p3_ctl1_0;
242         u16 iophy_misc_pad_p4_ctl1_0;
243         u16 iophy_misc_pad_p2_ctl2_0;
244         u16 iophy_misc_pad_p3_ctl2_0;
245         u16 iophy_misc_pad_p4_ctl2_0;
246         u16 iophy_misc_pad_p2_ctl3_0;
247         u16 iophy_misc_pad_p3_ctl3_0;
248         u16 iophy_misc_pad_p4_ctl3_0;
249         u16 iophy_misc_pad_p2_ctl4_0;
250         u16 iophy_misc_pad_p3_ctl4_0;
251         u16 iophy_misc_pad_p4_ctl4_0;
252         u16 iophy_misc_pad_p2_ctl5_0;
253         u16 iophy_misc_pad_p3_ctl5_0;
254         u16 iophy_misc_pad_p4_ctl5_0;
255         u16 iophy_misc_pad_p2_ctl6_0;
256         u16 iophy_misc_pad_p3_ctl6_0;
257         u16 iophy_misc_pad_p4_ctl6_0;
258         u16 usb3_pad_mux_0;
259         u16 iophy_pll_s0_ctl1_0;
260         u16 iophy_pll_s0_ctl2_0;
261         u16 iophy_pll_s0_ctl3_0;
262         u16 iophy_pll_s0_ctl4_0;
263         u16 iophy_misc_pad_s0_ctl1_0;
264         u16 iophy_misc_pad_s0_ctl2_0;
265         u16 iophy_misc_pad_s0_ctl3_0;
266         u16 iophy_misc_pad_s0_ctl4_0;
267         u16 iophy_misc_pad_s0_ctl5_0;
268         u16 iophy_misc_pad_s0_ctl6_0;
269 };
270
271 struct tegra_xhci_hcd {
272         struct platform_device *pdev;
273         struct xhci_hcd *xhci;
274         u16 device_id;
275
276         spinlock_t lock;
277         struct mutex sync_lock;
278
279         int smi_irq;
280         int padctl_irq;
281         int usb3_irq;
282
283         bool ss_wake_event;
284         bool ss_pwr_gated;
285         bool host_pwr_gated;
286         bool hs_wake_event;
287         bool host_resume_req;
288         bool lp0_exit;
289         bool dfe_ctle_ctx_saved;
290         unsigned long last_jiffies;
291         unsigned long host_phy_base;
292         void __iomem *host_phy_virt_base;
293
294         void __iomem *padctl_base;
295         void __iomem *fpci_base;
296         void __iomem *ipfs_base;
297
298         struct tegra_xusb_platform_data *pdata;
299         struct tegra_xusb_board_data *bdata;
300         struct tegra_xusb_padctl_regs *padregs;
301
302         /* mailbox variables */
303         struct mutex mbox_lock;
304         u32 mbox_owner;
305         u32 cmd_type;
306         u32 cmd_data;
307
308         struct regulator *xusb_s5p0v_reg;
309         struct regulator *xusb_s5p0v1_reg;
310         struct regulator *xusb_s5p0v2_reg;
311         struct regulator *xusb_s1p05v_reg;
312         struct regulator *xusb_s3p3v_reg;
313         struct regulator *xusb_s1p8v_reg;
314
315         struct work_struct mbox_work;
316         struct work_struct ss_elpg_exit_work;
317         struct work_struct host_elpg_exit_work;
318
319         struct clk *host_clk;
320         struct clk *ss_clk;
321
322         /* XUSB Falcon SuperSpeed Clock */
323         struct clk *falc_clk;
324
325         /* EMC Clock */
326         struct clk *emc_clk;
327         /* XUSB SS PI Clock */
328         struct clk *ss_src_clk;
329         /* PLLE Clock */
330         struct clk *plle_clk;
331         struct clk *pll_u_480M;
332         struct clk *clk_m;
333         /* refPLLE clk */
334         struct clk *pll_re_vco_clk;
335         /*
336          * XUSB/IPFS specific registers these need to be saved/restored in
337          * addition to spec defined registers
338          */
339         struct xusb_save_regs sregs;
340         bool usb2_rh_suspend;
341         bool usb3_rh_suspend;
342         bool hc_in_elpg;
343
344         unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
345         /* firmware loading related */
346         struct tegra_xhci_firmware firmware;
347 };
348
349 static struct tegra_usb_pmc_data pmc_data;
350
351 /* functions */
352 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
353 {
354         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
355 }
356
357 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
358 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
359 {
360         WARN_ON(tegra->sync_lock.owner != current);
361 }
362 #else
363 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
364 #endif
365
366 static void tegra_xhci_setup_gpio_for_ss_lane(struct tegra_xhci_hcd *tegra)
367 {
368         int err = 0;
369
370         if (!tegra->bdata->gpio_controls_muxed_ss_lanes)
371                 return;
372
373         if (tegra->bdata->lane_owner & BIT(0)) {
374                 /* USB3_SS port1 is using SATA lane so set (MUX_SATA)
375                  * GPIO P11 to '0'
376                  */
377                 err = gpio_request((tegra->bdata->gpio_ss1_sata & 0xffff),
378                         "gpio_ss1_sata");
379                 if (err < 0)
380                         pr_err("%s: gpio_ss1_sata gpio_request failed %d\n",
381                                 __func__, err);
382                 err = gpio_direction_output((tegra->bdata->gpio_ss1_sata
383                         & 0xffff), 1);
384                 if (err < 0)
385                         pr_err("%s: gpio_ss1_sata gpio_direction failed %d\n",
386                                 __func__, err);
387                 __gpio_set_value((tegra->bdata->gpio_ss1_sata & 0xffff),
388                                 ((tegra->bdata->gpio_ss1_sata >> 16)));
389         }
390 }
391
392 static void debug_print_portsc(struct xhci_hcd *xhci)
393 {
394         __le32 __iomem *addr;
395         int i;
396         int ports;
397
398         ports = HCS_MAX_PORTS(xhci->hcs_params1);
399         addr = &xhci->op_regs->port_status_base;
400         for (i = 0; i < ports; i++) {
401                 xhci_dbg(xhci, "%p port %d status reg = 0x%x\n",
402                                 addr, i, (unsigned int) xhci_readl(xhci, addr));
403                 addr += NUM_PORT_REGS;
404         }
405 }
406
407 static void update_speed(struct tegra_xhci_hcd *tegra, u8 port)
408 {
409         struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
410         u32 portsc;
411
412         portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port +
413                                                 BAR0_XHCI_OP_PORTSC_UTMIP_0));
414         if (DEV_FULLSPEED(portsc))
415                 pmc_data.port_speed = USB_PMC_PORT_SPEED_FULL;
416         else if (DEV_HIGHSPEED(portsc))
417                 pmc_data.port_speed = USB_PMC_PORT_SPEED_HIGH;
418         else if (DEV_LOWSPEED(portsc))
419                 pmc_data.port_speed = USB_PMC_PORT_SPEED_LOW;
420         else if (DEV_SUPERSPEED(portsc))
421                 pmc_data.port_speed = USB_PMC_PORT_SPEED_SUPER;
422         else
423                 pmc_data.port_speed = USB_PMC_PORT_SPEED_UNKNOWN;
424 }
425
426 static void setup_wake_detect(bool setup_wake)
427 {
428         if (setup_wake)
429                 pmc_data.pmc_ops->setup_pmc_wake_detect(&pmc_data);
430         else
431                 pmc_data.pmc_ops->disable_pmc_bus_ctrl(&pmc_data, 0);
432 }
433
434 static void pmc_init(struct tegra_xhci_hcd *tegra, bool setup_wake)
435 {
436         u32 portmap = tegra->bdata->portmap;
437
438         pmc_data.controller_type = TEGRA_USB_3_0;
439         if (portmap & TEGRA_XUSB_USB2_P0) {
440                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 0) & 0xf;
441                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
442                 update_speed(tegra, pmc_data.instance);
443                 tegra_usb_pmc_init(&pmc_data);
444                 setup_wake_detect(setup_wake);
445         }
446         if (portmap & TEGRA_XUSB_USB2_P1) {
447                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 4) & 0xf;
448                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
449                 update_speed(tegra, pmc_data.instance);
450                 tegra_usb_pmc_init(&pmc_data);
451                 setup_wake_detect(setup_wake);
452         }
453         if (portmap & TEGRA_XUSB_USB2_P2) {
454                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 8) & 0xf;
455                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
456                 update_speed(tegra, pmc_data.instance);
457                 tegra_usb_pmc_init(&pmc_data);
458                 setup_wake_detect(setup_wake);
459         }
460         if (portmap & TEGRA_XUSB_HSIC_P0) {
461                 pmc_data.instance = PMC_PORT_UHSIC_P0;
462                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_HSIC;
463                 update_speed(tegra, pmc_data.instance);
464                 tegra_usb_pmc_init(&pmc_data);
465                 setup_wake_detect(setup_wake);
466         }
467 }
468
469 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
470 {
471         void __iomem *fpci_base = tegra->fpci_base;
472         struct platform_device *pdev = tegra->pdev;
473         u32 input_addr;
474         u32 data;
475         u32 csb_page_select;
476
477         /* to select the appropriate CSB page to write to */
478         csb_page_select = CSB_PAGE_SELECT(addr);
479
480         dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
481                         csb_page_select);
482
483         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
484
485         /* selects the appropriate offset in the page to read from */
486         input_addr = CSB_PAGE_OFFSET(addr);
487         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
488
489         dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
490                         input_addr, data);
491         return data;
492 }
493
494 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
495 {
496         void __iomem *fpci_base = tegra->fpci_base;
497         struct platform_device *pdev = tegra->pdev;
498         u32 input_addr;
499         u32 csb_page_select;
500
501         /* to select the appropriate CSB page to write to */
502         csb_page_select = CSB_PAGE_SELECT(addr);
503
504         dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
505                         csb_page_select);
506
507         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
508
509         /* selects the appropriate offset in the page to write to */
510         input_addr = CSB_PAGE_OFFSET(addr);
511         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
512
513         dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
514                         input_addr, data);
515 }
516
517 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
518 {
519         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
520         struct xhci_hcd *xhci = tegra->xhci;
521         u32 reg;
522
523         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
524         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
525         xhci_info(xhci, " PAD MUX = %x\n", reg);
526         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
527         xhci_info(xhci, " PORT CAP = %x\n", reg);
528         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
529         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
530         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
531         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
532         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
533         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
534         reg = readl(tegra->padctl_base + padregs->oc_det_0);
535         xhci_info(xhci, " OC DET 0= %x\n", reg);
536         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad0_ctl2_0);
537         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
538         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad1_ctl2_0);
539         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
540         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl0_0);
541         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
542         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl0_0);
543         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
544         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl1_0);
545         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
546         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl1_0);
547         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
548         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
549         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
550         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad0_ctl0_0);
551         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
552         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad1_ctl0_0);
553         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
554         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
555 }
556
557 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
558 {
559         u32 reg;
560
561         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
562         reg |= IPFS_EN_FPCI;
563         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
564         udelay(10);
565
566         /* Program Bar0 Space */
567         reg = readl(tegra->fpci_base + XUSB_CFG_4);
568         reg |= tegra->host_phy_base;
569         writel(reg, tegra->fpci_base + XUSB_CFG_4);
570         usleep_range(100, 200);
571
572         /* Enable Bus Master */
573         reg = readl(tegra->fpci_base + XUSB_CFG_1);
574         reg |= 0x7;
575         writel(reg, tegra->fpci_base + XUSB_CFG_1);
576
577         /* Set intr mask to enable intr assertion */
578         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
579         reg |= IPFS_IP_INT_MASK;
580         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
581
582         /* Set hysteris to 0x80 */
583         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
584 }
585
586 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
587                 struct platform_device *pdev)
588 {
589         struct tegra_xusb_regulator_name *supply = &tegra->bdata->supply;
590         int err = 0;
591
592         tegra->xusb_s3p3v_reg =
593                         devm_regulator_get(&pdev->dev, supply->s3p3v);
594         if (IS_ERR(tegra->xusb_s3p3v_reg)) {
595                 dev_err(&pdev->dev, "3p3v: regulator not found: %ld."
596                         , PTR_ERR(tegra->xusb_s3p3v_reg));
597                 err = PTR_ERR(tegra->xusb_s3p3v_reg);
598                 goto err_null_regulator;
599         } else {
600                 err = regulator_enable(tegra->xusb_s3p3v_reg);
601                 if (err < 0) {
602                         dev_err(&pdev->dev,
603                                 "3p3v: regulator enable failed:%d\n", err);
604                         goto err_null_regulator;
605                 }
606         }
607
608         tegra->xusb_s5p0v_reg = devm_regulator_get(&pdev->dev, supply->s5p0v);
609         if (IS_ERR(tegra->xusb_s5p0v_reg)) {
610                 dev_err(&pdev->dev, "5p0v regulator not found: %ld."
611                         , PTR_ERR(tegra->xusb_s5p0v_reg));
612                 err = PTR_ERR(tegra->xusb_s5p0v_reg);
613                 goto err_put_s3p3v_reg;
614         } else {
615                 err = regulator_enable(tegra->xusb_s5p0v_reg);
616                 if (err < 0) {
617                         dev_err(&pdev->dev,
618                                 "5p0v: regulator enable failed:%d\n", err);
619                         goto err_put_s3p3v_reg;
620                 }
621         }
622
623         tegra->xusb_s1p8v_reg =
624                 devm_regulator_get(&pdev->dev, supply->s1p8v);
625         if (IS_ERR(tegra->xusb_s1p8v_reg)) {
626                 dev_err(&pdev->dev, "1p8v regulator not found: %ld."
627                         , PTR_ERR(tegra->xusb_s1p8v_reg));
628                 err = PTR_ERR(tegra->xusb_s1p8v_reg);
629                 goto err_put_s5p0v_reg;
630         } else {
631                 err = regulator_enable(tegra->xusb_s1p8v_reg);
632                 if (err < 0) {
633                         dev_err(&pdev->dev,
634                         "1p8v: regulator enable failed:%d\n", err);
635                         goto err_put_s5p0v_reg;
636                 }
637         }
638
639         tegra->xusb_s1p05v_reg =
640                         devm_regulator_get(&pdev->dev, supply->s1p05v);
641         if (IS_ERR(tegra->xusb_s1p05v_reg)) {
642                 dev_err(&pdev->dev, "1p05v: regulator not found: %ld."
643                         , PTR_ERR(tegra->xusb_s1p05v_reg));
644                 err = PTR_ERR(tegra->xusb_s1p05v_reg);
645                 goto err_put_s1p8v_reg;
646         } else {
647                 err = regulator_enable(tegra->xusb_s1p05v_reg);
648                 if (err < 0) {
649                         dev_err(&pdev->dev,
650                         "1p05v: regulator enable failed:%d\n", err);
651                         goto err_put_s1p8v_reg;
652                 }
653         }
654
655         if (tegra->bdata->uses_different_vbus_per_port) {
656                 tegra->xusb_s5p0v1_reg = devm_regulator_get(&pdev->dev,
657                                                 supply->s5p0v1);
658                 if (IS_ERR(tegra->xusb_s5p0v1_reg)) {
659                         dev_err(&pdev->dev, "5p0v1 regulator not found: %ld."
660                                 , PTR_ERR(tegra->xusb_s5p0v1_reg));
661                         err = PTR_ERR(tegra->xusb_s5p0v1_reg);
662                         goto err_put_s1p05v_reg;
663                 } else {
664                         err = regulator_enable(tegra->xusb_s5p0v1_reg);
665                         if (err < 0) {
666                                 dev_err(&pdev->dev,
667                                 "5p0v1: regulator enable failed:%d\n", err);
668                                 goto err_put_s1p05v_reg;
669                         }
670                 }
671
672                 tegra->xusb_s5p0v2_reg = devm_regulator_get(&pdev->dev,
673                                                 supply->s5p0v2);
674                 if (IS_ERR(tegra->xusb_s5p0v2_reg)) {
675                         dev_err(&pdev->dev, "5p0v2 regulator not found: %ld."
676                                 , PTR_ERR(tegra->xusb_s5p0v2_reg));
677                         err = PTR_ERR(tegra->xusb_s5p0v2_reg);
678                         goto err_put_s1p5v1_reg;
679                 } else {
680                         err = regulator_enable(tegra->xusb_s5p0v2_reg);
681                         if (err < 0) {
682                                 dev_err(&pdev->dev,
683                                 "5p0v2: regulator enable failed:%d\n", err);
684                                 goto err_put_s1p5v1_reg;
685                         }
686                 }
687         }
688         return err;
689
690 err_put_s1p5v1_reg:
691         if (tegra->bdata->uses_different_vbus_per_port)
692                 regulator_disable(tegra->xusb_s5p0v1_reg);
693 err_put_s1p05v_reg:
694         regulator_disable(tegra->xusb_s1p05v_reg);
695 err_put_s1p8v_reg:
696         regulator_disable(tegra->xusb_s1p8v_reg);
697 err_put_s5p0v_reg:
698         regulator_disable(tegra->xusb_s5p0v_reg);
699 err_put_s3p3v_reg:
700         regulator_disable(tegra->xusb_s3p3v_reg);
701 err_null_regulator:
702         tegra->xusb_s5p0v_reg = NULL;
703         tegra->xusb_s5p0v1_reg = NULL;
704         tegra->xusb_s5p0v2_reg = NULL;
705         tegra->xusb_s1p05v_reg = NULL;
706         tegra->xusb_s3p3v_reg = NULL;
707         tegra->xusb_s1p8v_reg = NULL;
708         return err;
709 }
710
711 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
712 {
713         regulator_disable(tegra->xusb_s1p05v_reg);
714         regulator_disable(tegra->xusb_s1p8v_reg);
715         regulator_disable(tegra->xusb_s5p0v_reg);
716         regulator_disable(tegra->xusb_s3p3v_reg);
717         if (tegra->bdata->uses_different_vbus_per_port) {
718                 regulator_disable(tegra->xusb_s5p0v1_reg);
719                 regulator_disable(tegra->xusb_s5p0v2_reg);
720         }
721
722         tegra->xusb_s1p05v_reg = NULL;
723         tegra->xusb_s1p8v_reg = NULL;
724         tegra->xusb_s5p0v_reg = NULL;
725         tegra->xusb_s5p0v1_reg = NULL;
726         tegra->xusb_s5p0v2_reg = NULL;
727         tegra->xusb_s3p3v_reg = NULL;
728 }
729
730 /*
731  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
732  * are under hardware control
733  */
734 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
735 {
736         struct platform_device *pdev = tegra->pdev;
737         int err = 0;
738
739         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
740         if (IS_ERR(tegra->plle_clk)) {
741                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
742                 err = PTR_ERR(tegra->plle_clk);
743                 return err;
744         }
745         err = clk_enable(tegra->plle_clk);
746         if (err) {
747                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
748                         __func__);
749                 return err;
750         }
751
752         return err;
753 }
754
755 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
756 {
757         clk_disable(tegra->plle_clk);
758         tegra->plle_clk = NULL;
759 }
760
761 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
762 {
763         struct platform_device *pdev = tegra->pdev;
764         int err = 0;
765
766         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
767         if (IS_ERR(tegra->emc_clk)) {
768                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
769                 return PTR_ERR(tegra->emc_clk);
770         }
771
772         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
773                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
774                 if (IS_ERR(tegra->pll_re_vco_clk)) {
775                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
776                         err = PTR_ERR(tegra->pll_re_vco_clk);
777                         goto get_pll_re_vco_clk_failed;
778                 }
779         }
780
781         /* get the clock handle of 120MHz clock source */
782         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
783         if (IS_ERR(tegra->pll_u_480M)) {
784                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
785                 err = PTR_ERR(tegra->pll_u_480M);
786                 goto get_pll_u_480M_failed;
787         }
788
789         /* get the clock handle of 12MHz clock source */
790         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
791         if (IS_ERR(tegra->clk_m)) {
792                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
793                 err = PTR_ERR(tegra->clk_m);
794                 goto clk_get_clk_m_failed;
795         }
796
797         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
798         if (IS_ERR(tegra->ss_src_clk)) {
799                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
800                 err = PTR_ERR(tegra->ss_src_clk);
801                 tegra->ss_src_clk = NULL;
802                 goto get_ss_src_clk_failed;
803         }
804
805         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
806         if (IS_ERR(tegra->host_clk)) {
807                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
808                 err = PTR_ERR(tegra->host_clk);
809                 tegra->host_clk = NULL;
810                 goto get_host_clk_failed;
811         }
812
813         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
814         if (IS_ERR(tegra->ss_clk)) {
815                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
816                 err = PTR_ERR(tegra->ss_clk);
817                 tegra->ss_clk = NULL;
818                 goto get_ss_clk_failed;
819         }
820
821         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
822                 err = clk_enable(tegra->pll_re_vco_clk);
823                 if (err) {
824                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
825                         goto enable_pll_re_vco_clk_failed;
826                 }
827         }
828         /* enable ss clock */
829         err = clk_enable(tegra->host_clk);
830         if (err) {
831                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
832                 goto enable_host_clk_failed;
833         }
834
835         err = clk_enable(tegra->ss_clk);
836         if (err) {
837                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
838                 goto eanble_ss_clk_failed;
839         }
840
841         err = clk_enable(tegra->emc_clk);
842         if (err) {
843                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
844                 goto eanble_emc_clk_failed;
845         }
846
847         return 0;
848
849 eanble_emc_clk_failed:
850         clk_disable(tegra->ss_clk);
851
852 eanble_ss_clk_failed:
853         clk_disable(tegra->host_clk);
854
855 enable_host_clk_failed:
856         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
857                 clk_disable(tegra->pll_re_vco_clk);
858
859 enable_pll_re_vco_clk_failed:
860         tegra->ss_clk = NULL;
861
862 get_ss_clk_failed:
863         tegra->host_clk = NULL;
864
865 get_host_clk_failed:
866         tegra->ss_src_clk = NULL;
867
868 get_ss_src_clk_failed:
869         tegra->clk_m = NULL;
870
871 clk_get_clk_m_failed:
872         tegra->pll_u_480M = NULL;
873
874 get_pll_u_480M_failed:
875         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
876                 tegra->pll_re_vco_clk = NULL;
877
878 get_pll_re_vco_clk_failed:
879         tegra->emc_clk = NULL;
880
881         return err;
882 }
883
884 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
885 {
886         clk_disable(tegra->ss_clk);
887         clk_disable(tegra->host_clk);
888         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
889                 clk_disable(tegra->pll_re_vco_clk);
890         tegra->ss_clk = NULL;
891         tegra->host_clk = NULL;
892         tegra->ss_src_clk = NULL;
893         tegra->clk_m = NULL;
894         tegra->pll_u_480M = NULL;
895         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
896                 tegra->pll_re_vco_clk = NULL;
897 }
898
899 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
900         bool enable)
901 {
902         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
903         u32 reg;
904
905         /* Issue is only applicable for T114 */
906         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
907                 return;
908
909         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
910                 reg = readl(tegra->padctl_base +
911                         padregs->iophy_misc_pad_p0_ctl3_0);
912                 if (enable) {
913                         reg &= ~RX_IDLE_MODE;
914                         reg |= RX_IDLE_MODE_OVRD;
915                 } else {
916                         reg |= RX_IDLE_MODE;
917                         reg &= ~RX_IDLE_MODE_OVRD;
918                 }
919                 writel(reg, tegra->padctl_base +
920                         padregs->iophy_misc_pad_p0_ctl3_0);
921         }
922
923         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
924                 reg = readl(tegra->padctl_base +
925                         padregs->iophy_misc_pad_p1_ctl3_0);
926                 if (enable) {
927                         reg &= ~RX_IDLE_MODE;
928                         reg |= RX_IDLE_MODE_OVRD;
929                 } else {
930                         reg |= RX_IDLE_MODE;
931                         reg &= ~RX_IDLE_MODE_OVRD;
932                 }
933                 writel(reg, tegra->padctl_base +
934                         padregs->iophy_misc_pad_p1_ctl3_0);
935
936                 /* SATA lane also if USB3_SS port1 mapped to it */
937                 if (XUSB_DEVICE_ID_T124 == tegra->device_id &&
938                                 tegra->bdata->lane_owner & BIT(0)) {
939                         reg = readl(tegra->padctl_base +
940                                 padregs->iophy_misc_pad_s0_ctl3_0);
941                         if (enable) {
942                                 reg &= ~RX_IDLE_MODE;
943                                 reg |= RX_IDLE_MODE_OVRD;
944                         } else {
945                                 reg |= RX_IDLE_MODE;
946                                 reg &= ~RX_IDLE_MODE_OVRD;
947                         }
948                         writel(reg, tegra->padctl_base +
949                                 padregs->iophy_misc_pad_s0_ctl3_0);
950                 }
951         }
952 }
953
954 /* Enable ss clk, host clk, falcon clk,
955  * fs clk, dev clk, plle and refplle
956  */
957
958 static int
959 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
960                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
961 {
962         int ret = 0;
963         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
964         int fw_req_rate = rate, cur_rate;
965
966         /* Do not handle clock change as needed for HS disconnect issue */
967         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
968                 *sw_resp = fw_req_rate | (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
969                 return ret;
970         }
971
972         /* frequency request from firmware is in KHz.
973          * Convert it to MHz
974          */
975
976         /* get current rate of clock */
977         cur_rate = clk_get_rate(clk_handle);
978         cur_rate /= 1000;
979
980         if (fw_req_rate == cur_rate) {
981                 cmd_ack = MBOX_CMD_ACK;
982                 *sw_resp = fw_req_rate;
983         } else {
984
985                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
986                         /* Change SS clock source to CLK_M at 12MHz */
987                         clk_set_parent(clk_handle, tegra->clk_m);
988                         clk_set_rate(clk_handle, fw_req_rate * 1000);
989
990                         /* save leakage power when SS freq is being decreased */
991                         tegra_xhci_rx_idle_mode_override(tegra, true);
992                 } else if (clk_handle == tegra->ss_src_clk &&
993                                 fw_req_rate == 120000) {
994                         /* Change SS clock source to HSIC_480 at 120MHz */
995                         clk_set_rate(clk_handle,  3000 * 1000);
996                         clk_set_parent(clk_handle, tegra->pll_u_480M);
997
998                         /* clear ovrd bits when SS freq is being increased */
999                         tegra_xhci_rx_idle_mode_override(tegra, false);
1000                 }
1001
1002                 *sw_resp = clk_get_rate(clk_handle);
1003                 *sw_resp /= 1000;
1004
1005                 if (*sw_resp != fw_req_rate) {
1006                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
1007                                 cur_rate, fw_req_rate);
1008                         cmd_ack = MBOX_CMD_NACK;
1009                 }
1010         }
1011         *sw_resp |= (cmd_ack << MBOX_CMD_SHIFT);
1012         return ret;
1013 }
1014
1015 static void tegra_xhci_save_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
1016         u8 port)
1017 {
1018         struct xhci_hcd *xhci = tegra->xhci;
1019         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1020         u32 offset;
1021         u32 reg;
1022
1023         xhci_info(xhci, "saving dfe_cntl and ctle context for port %d\n", port);
1024
1025         if (port == 3 /* SATA pad */)
1026                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1027         else
1028                 offset = port ? padregs->iophy_misc_pad_p1_ctl6_0 :
1029                                 padregs->iophy_misc_pad_p0_ctl6_0;
1030
1031         /* save tap1_val[] for the port for dfe_cntl */
1032         reg = readl(tegra->padctl_base + offset);
1033         reg &= ~(0xff << 16);
1034         reg |= (0x32 << 16);
1035         writel(reg, tegra->padctl_base + offset);
1036
1037         reg = readl(tegra->padctl_base + offset);
1038         tegra->sregs.tap1_val[port] = ((reg & (0x1f << 24)) >> 24);
1039
1040         /* save amp_val[] for the port for dfe_cntl */
1041         reg = readl(tegra->padctl_base + offset);
1042         reg &= ~(0xff << 16);
1043         reg |= (0x33 << 16);
1044         writel(reg, tegra->padctl_base + offset);
1045
1046         reg = readl(tegra->padctl_base + offset);
1047         tegra->sregs.amp_val[port] = ((reg & (0x7f << 24)) >> 24);
1048
1049         /* save ctle_z_val[] for the port for ctle */
1050         reg = readl(tegra->padctl_base + offset);
1051         reg &= ~(0xff << 16);
1052         reg |= (0x20 << 16);
1053         writel(reg, tegra->padctl_base + offset);
1054
1055         reg = readl(tegra->padctl_base + offset);
1056         tegra->sregs.ctle_z_val[port] = ((reg & (0x3f << 24)) >> 24);
1057
1058         /* save ctle_g_val[] for the port for ctle */
1059         reg = readl(tegra->padctl_base + offset);
1060         reg &= ~(0xff << 16);
1061         reg |= (0x21 << 16);
1062         writel(reg, tegra->padctl_base + offset);
1063
1064         reg = readl(tegra->padctl_base + offset);
1065         tegra->sregs.ctle_g_val[port] = ((reg & (0x3f << 24)) >> 24);
1066         tegra->dfe_ctle_ctx_saved = true;
1067 }
1068
1069 static void tegra_xhci_restore_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
1070         u8 port)
1071 {
1072         struct xhci_hcd *xhci = tegra->xhci;
1073         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1074         u32 ctl4_offset, ctl2_offset;
1075         u32 reg;
1076
1077         /* don't restore if not saved */
1078         if (tegra->dfe_ctle_ctx_saved == false)
1079                 return;
1080
1081         if (port == 3 /* SATA pad */) {
1082                 ctl4_offset = padregs->iophy_misc_pad_s0_ctl4_0;
1083                 ctl2_offset = padregs->iophy_misc_pad_s0_ctl2_0;
1084         } else {
1085                 ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1086                                 padregs->iophy_usb3_pad0_ctl4_0;
1087                 ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1088                                 padregs->iophy_usb3_pad0_ctl2_0;
1089         }
1090
1091         xhci_info(xhci, "restoring dfe_cntl/ctle context of port %d\n", port);
1092
1093         /* restore dfe_cntl for the port */
1094         reg = readl(tegra->padctl_base + ctl4_offset);
1095         reg &= ~((0x7f << 16) | (0x1f << 24));
1096         reg |= ((tegra->sregs.amp_val[port] << 16) |
1097                 (tegra->sregs.tap1_val[port] << 24));
1098         writel(reg, tegra->padctl_base + ctl4_offset);
1099
1100         /* restore ctle for the port */
1101         reg = readl(tegra->padctl_base + ctl2_offset);
1102         reg &= ~((0x3f << 8) | (0x3f << 16));
1103         reg |= ((tegra->sregs.ctle_g_val[port] << 8) |
1104                 (tegra->sregs.ctle_z_val[port] << 16));
1105         writel(reg, tegra->padctl_base + ctl2_offset);
1106 }
1107
1108 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
1109         u8 port)
1110 {
1111         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1112         u32 reg;
1113
1114         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1115         reg &= ~USB2_ULPI_PAD;
1116         reg |= USB2_ULPI_PAD_OWNER_XUSB;
1117         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1118
1119         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1120         reg &= ~USB2_ULPI_PORT_CAP;
1121         reg |= (tegra->bdata->ulpicap << 24);
1122         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1123         /* FIXME: Program below when more details available
1124          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
1125          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
1126          */
1127 }
1128
1129 static void tegra_xhci_program_hsic_pad(struct tegra_xhci_hcd *tegra,
1130         u8 port)
1131 {
1132         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1133         u32 ctl0_offset;
1134         u32 reg;
1135
1136         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1137         reg &= ~(port ? USB2_HSIC_PAD_PORT1 : USB2_HSIC_PAD_PORT0);
1138         reg |= port ? USB2_HSIC_PAD_P1_OWNER_XUSB :
1139                         USB2_HSIC_PAD_P0_OWNER_XUSB;
1140         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1141
1142         ctl0_offset = port ? padregs->usb2_hsic_pad1_ctl0_0 :
1143                         padregs->usb2_hsic_pad0_ctl0_0;
1144
1145         reg = readl(tegra->padctl_base + ctl0_offset);
1146         reg &= ~(HSIC_TX_SLEWP | HSIC_TX_SLEWN);
1147         writel(reg, tegra->padctl_base + ctl0_offset);
1148
1149         /* FIXME Program below when more details available
1150          * XUSB_PADCTL_HSIC_PAD0_CTL_0_0
1151          * XUSB_PADCTL_HSIC_PAD0_CTL_1_0
1152          * XUSB_PADCTL_HSIC_PAD0_CTL_2_0
1153          * XUSB_PADCTL_HSIC_PAD1_CTL_0_0
1154          * XUSB_PADCTL_HSIC_PAD1_CTL_1_0
1155          * XUSB_PADCTL_HSIC_PAD1_CTL_2_0
1156          * XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0
1157          */
1158 }
1159
1160 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
1161         u8 port)
1162 {
1163         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1164         u32 reg;
1165         u32 ctl0_offset, ctl1_offset;
1166
1167         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1168         reg &= ~USB2_OTG_PAD_PORT_MASK(port);
1169         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
1170         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1171
1172         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1173         reg &= ~USB2_PORT_CAP_MASK(port);
1174         reg |= USB2_PORT_CAP_HOST(port);
1175         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1176
1177         /*
1178          * Modify only the bits which belongs to the port
1179          * and enable respective VBUS_PAD for the port
1180          */
1181         if (tegra->bdata->uses_external_pmic == false) {
1182                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1183                 reg &= ~(port == 2 ? OC_DET_VBUS_ENABLE2_OC_MAP :
1184                         port ? OC_DET_VBUS_ENABLE1_OC_MAP :
1185                                 OC_DET_VBUS_ENABLE0_OC_MAP);
1186
1187                 reg |= (port == 2) ? OC_DET_VBUS_EN2_OC_DETECTED_VBUS_PAD2 :
1188                         port ? OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1 :
1189                                 OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0;
1190                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1191         }
1192         /*
1193          * enable respective VBUS_PAD if port is mapped to any SS port
1194          */
1195         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1196         reg &= ~((port == 2) ? USB2_OC_MAP_PORT2 :
1197                 port ? USB2_OC_MAP_PORT1 : USB2_OC_MAP_PORT0);
1198         reg |= (0x4 | port) << (port * 3);
1199         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1200
1201         ctl0_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl0_0 :
1202                         port ? padregs->usb2_otg_pad1_ctl0_0 :
1203                                 padregs->usb2_otg_pad0_ctl0_0;
1204         ctl1_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl1_0 :
1205                         port ? padregs->usb2_otg_pad1_ctl1_0 :
1206                                 padregs->usb2_otg_pad0_ctl1_0;
1207
1208         reg = readl(tegra->padctl_base + ctl0_offset);
1209         reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
1210                 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
1211                 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
1212
1213         reg |= tegra->pdata->hs_slew;
1214         reg |= (port == 2) ? tegra->pdata->ls_rslew_pad2 :
1215                         port ? tegra->pdata->ls_rslew_pad1 :
1216                         tegra->pdata->ls_rslew_pad0;
1217         reg |= (port == 2) ? tegra->pdata->hs_curr_level_pad2 :
1218                         port ? tegra->pdata->hs_curr_level_pad1 :
1219                         tegra->pdata->hs_curr_level_pad0;
1220         writel(reg, tegra->padctl_base + ctl0_offset);
1221
1222         reg = readl(tegra->padctl_base + ctl1_offset);
1223         reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
1224                 | USB2_OTG_PD_CHRP_FORCE_POWERUP
1225                 | USB2_OTG_PD_DISC_FORCE_POWERUP
1226                 | USB2_OTG_PD_DR);
1227         reg |= (tegra->pdata->hs_iref_cap << 9) |
1228                 (tegra->pdata->hs_term_range_adj << 3);
1229         writel(reg, tegra->padctl_base + ctl1_offset);
1230 }
1231
1232 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
1233         u8 port)
1234 {
1235         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1236         u32 ctl2_offset, ctl4_offset;
1237         u32 reg;
1238
1239         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1240                         padregs->iophy_usb3_pad0_ctl2_0;
1241         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1242                         padregs->iophy_usb3_pad0_ctl4_0;
1243
1244         reg = readl(tegra->padctl_base + ctl2_offset);
1245         reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
1246                 IOPHY_USB3_CDRCNTL);
1247         reg |= tegra->pdata->rx_wander | tegra->pdata->rx_eq |
1248                 tegra->pdata->cdr_cntl;
1249         writel(reg, tegra->padctl_base + ctl2_offset);
1250
1251         reg = readl(tegra->padctl_base + ctl4_offset);
1252         reg = tegra->pdata->dfe_cntl;
1253         writel(reg, tegra->padctl_base + ctl4_offset);
1254
1255         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1256         reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
1257         reg |= (tegra->bdata->ss_portmap &
1258                 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
1259         writel(reg, tegra->padctl_base + padregs->ss_port_map_0);
1260
1261         tegra_xhci_restore_dfe_ctle_context(tegra, port);
1262         /* SATA also if USB3_SS port1 mapped to it */
1263         if ((port == 1) && (XUSB_DEVICE_ID_T124 == tegra->device_id) &&
1264                         (tegra->bdata->lane_owner & BIT(0)))
1265                 tegra_xhci_restore_dfe_ctle_context(tegra, 3);
1266 }
1267
1268 /* This function assigns the USB ports to the controllers,
1269  * then programs the port capabilities and pad parameters
1270  * of ports assigned to XUSB after booted to OS.
1271  */
1272 void
1273 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
1274 {
1275         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1276         u32 reg, oc_bits = 0;
1277
1278         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1279         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
1280         reg |= tegra->pdata->hs_squelch_level | tegra->pdata->hs_disc_lvl;
1281         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1282
1283         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1284         reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3;
1285         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
1286         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1287
1288         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1289         reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
1290         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1291                 reg |= OC_DET_VBUS_ENABLE2_OC_MAP;
1292         writel(reg, tegra->padctl_base + padregs->oc_det_0);
1293
1294         /* check if over current seen. Clear if present */
1295         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1296                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
1297         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1298                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
1299         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1300                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
1301
1302         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1303         if (reg & oc_bits) {
1304                 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
1305                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1306
1307                 usleep_range(100, 200);
1308
1309                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1310                 if (reg & oc_bits)
1311                         xhci_info(tegra->xhci, "Over current still present\n");
1312         }
1313
1314         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1315         reg = USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1;
1316         if (XUSB_DEVICE_ID_T124 == tegra->device_id)
1317                 reg |= USB2_OC_MAP_PORT2;
1318         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1319
1320         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1321                 tegra_xhci_program_utmip_pad(tegra, 0);
1322         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1323                 tegra_xhci_program_utmip_pad(tegra, 1);
1324         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1325                 tegra_xhci_program_utmip_pad(tegra, 2);
1326
1327         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
1328                 tegra_xhci_program_ulpi_pad(tegra, 0);
1329
1330         if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P0)
1331                 tegra_xhci_program_hsic_pad(tegra, 0);
1332         if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P1)
1333                 tegra_xhci_program_hsic_pad(tegra, 1);
1334
1335         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1336                 tegra_xhci_program_ss_pad(tegra, 0);
1337         } else {
1338                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1339                 reg = readl(tegra->padctl_base +
1340                         padregs->iophy_misc_pad_p0_ctl3_0);
1341                 reg &= ~RX_IDLE_MODE;
1342                 reg |= RX_IDLE_MODE_OVRD;
1343                 writel(reg, tegra->padctl_base +
1344                         padregs->iophy_misc_pad_p0_ctl3_0);
1345         }
1346
1347         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1348                 tegra_xhci_program_ss_pad(tegra, 1);
1349         } else {
1350                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1351                 reg = readl(tegra->padctl_base +
1352                         padregs->iophy_misc_pad_p1_ctl3_0);
1353                 reg &= ~RX_IDLE_MODE;
1354                 reg |= RX_IDLE_MODE_OVRD;
1355                 writel(reg, tegra->padctl_base +
1356                         padregs->iophy_misc_pad_p1_ctl3_0);
1357
1358                 /* SATA lane also if USB3_SS port1 mapped to it but unused */
1359                 if (XUSB_DEVICE_ID_T124 == tegra->device_id &&
1360                                 tegra->bdata->lane_owner & BIT(0)) {
1361                         reg = readl(tegra->padctl_base +
1362                                 padregs->iophy_misc_pad_s0_ctl3_0);
1363                         reg &= ~RX_IDLE_MODE;
1364                         reg |= RX_IDLE_MODE_OVRD;
1365                         writel(reg, tegra->padctl_base +
1366                                 padregs->iophy_misc_pad_s0_ctl3_0);
1367                 }
1368         }
1369         if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
1370                 tegra_xhci_setup_gpio_for_ss_lane(tegra);
1371                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
1372         }
1373 }
1374
1375 /* This function read XUSB registers and stores in device context */
1376 static void
1377 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
1378 {
1379
1380         /* a. Save the IPFS registers */
1381         tegra->sregs.msi_bar_sz =
1382                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
1383
1384         tegra->sregs.msi_axi_barst =
1385                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
1386
1387         tegra->sregs.msi_fpci_barst =
1388                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
1389
1390         tegra->sregs.msi_vec0 =
1391                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
1392
1393         tegra->sregs.msi_en_vec0 =
1394                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
1395
1396         tegra->sregs.fpci_error_masks =
1397                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
1398
1399         tegra->sregs.intr_mask =
1400                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1401
1402         tegra->sregs.ipfs_intr_enable =
1403                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
1404
1405         tegra->sregs.ufpci_config =
1406                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
1407
1408         tegra->sregs.clkgate_hysteresis =
1409                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1410
1411         tegra->sregs.xusb_host_mccif_fifo_cntrl =
1412                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
1413
1414         /* b. Save the CFG registers */
1415
1416         tegra->sregs.hs_pls =
1417                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
1418
1419         tegra->sregs.fs_pls =
1420                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
1421
1422         tegra->sregs.hs_fs_speed =
1423                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
1424
1425         tegra->sregs.hs_fs_pp =
1426                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
1427
1428         tegra->sregs.cfg_aru =
1429                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
1430
1431         tegra->sregs.cfg_order =
1432                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
1433
1434         tegra->sregs.cfg_fladj =
1435                 readl(tegra->fpci_base + XUSB_CFG_24);
1436
1437         tegra->sregs.cfg_sid =
1438                 readl(tegra->fpci_base + XUSB_CFG_16);
1439 }
1440
1441 /* This function restores XUSB registers from device context */
1442 static void
1443 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
1444 {
1445         /* Restore Cfg registers */
1446         writel(tegra->sregs.hs_pls,
1447                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
1448
1449         writel(tegra->sregs.fs_pls,
1450                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
1451
1452         writel(tegra->sregs.hs_fs_speed,
1453                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
1454
1455         writel(tegra->sregs.hs_fs_pp,
1456                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
1457
1458         writel(tegra->sregs.cfg_aru,
1459                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
1460
1461         writel(tegra->sregs.cfg_order,
1462                 tegra->fpci_base + XUSB_CFG_FPCICFG);
1463
1464         writel(tegra->sregs.cfg_fladj,
1465                 tegra->fpci_base + XUSB_CFG_24);
1466
1467         writel(tegra->sregs.cfg_sid,
1468                 tegra->fpci_base + XUSB_CFG_16);
1469
1470         /* Restore IPFS registers */
1471
1472         writel(tegra->sregs.msi_bar_sz,
1473                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
1474
1475         writel(tegra->sregs.msi_axi_barst,
1476                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
1477
1478         writel(tegra->sregs.msi_fpci_barst,
1479                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
1480
1481         writel(tegra->sregs.msi_vec0,
1482                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
1483
1484         writel(tegra->sregs.msi_en_vec0,
1485                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
1486
1487         writel(tegra->sregs.fpci_error_masks,
1488                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
1489
1490         writel(tegra->sregs.intr_mask,
1491                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1492
1493         writel(tegra->sregs.ipfs_intr_enable,
1494                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
1495
1496         writel(tegra->sregs.ufpci_config,
1497                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
1498
1499         writel(tegra->sregs.clkgate_hysteresis,
1500                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1501
1502         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
1503                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
1504 }
1505
1506 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
1507 {
1508         struct platform_device *pdev = tegra->pdev;
1509         u32 reg, timeout = 0xff, cmd;
1510
1511         mutex_lock(&tegra->mbox_lock);
1512
1513         do {
1514                 writel(MBOX_OWNER_SW,
1515                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
1516                 reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
1517                 usleep_range(10, 20);
1518         } while (reg != MBOX_OWNER_SW && timeout--);
1519
1520         if ((timeout == 0) && (reg != MBOX_OWNER_SW)) {
1521                 dev_err(&pdev->dev, "Failed to set mbox message owner ID\n");
1522                 mutex_unlock(&tegra->mbox_lock);
1523                 return;
1524         }
1525
1526         writel((MBOX_CMD_MSG_ENABLED << MBOX_CMD_SHIFT),
1527                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
1528
1529         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1530         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
1531         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1532
1533         mutex_unlock(&tegra->mbox_lock);
1534 }
1535
1536 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
1537 {
1538         struct platform_device *pdev = tegra->pdev;
1539         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
1540         u32 phys_addr_lo;
1541         u32 HwReg;
1542         u16 nblocks;
1543         time_t fw_time;
1544         struct tm fw_tm;
1545         u8 hc_caplength;
1546         u32 usbsts, count = 0xff;
1547         struct xhci_cap_regs __iomem *cap_regs;
1548         struct xhci_op_regs __iomem *op_regs;
1549
1550         /* enable mbox interrupt */
1551         writel(readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD) | MBOX_INT_EN,
1552                 tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1553
1554         /* First thing, reset the ARU. By the time we get to
1555          * loading boot code below, reset would be complete.
1556          * alternatively we can busy wait on rst pending bit.
1557          */
1558         /* Don't reset during ELPG/LP0 exit path */
1559         if (resetARU) {
1560                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
1561                 usleep_range(1000, 2000);
1562         }
1563
1564         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
1565                 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
1566                                 csb_read(tegra, XUSB_FALC_CPUCTL));
1567                 return 0;
1568         }
1569
1570         phys_addr_lo = tegra->firmware.dma;
1571         phys_addr_lo += sizeof(struct cfgtbl);
1572
1573         /* Program the size of DFI into ILOAD_ATTR */
1574         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
1575
1576         /* Boot code of the firmware reads the ILOAD_BASE_LO register
1577          * to get to the start of the dfi in system memory.
1578          */
1579         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
1580
1581         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
1582         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
1583
1584         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
1585         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
1586
1587         /* Invalidate L2IMEM. */
1588         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
1589
1590         /* Initiate fetch of Bootcode from system memory into L2IMEM.
1591          * Program BootCode location and size in system memory.
1592          */
1593         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
1594                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
1595                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
1596         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
1597                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
1598                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
1599         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
1600
1601         /* Trigger L2IMEM Load operation. */
1602         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
1603
1604         /* Setup Falcon Auto-fill */
1605         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
1606         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
1607                 nblocks += 1;
1608         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
1609
1610         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
1611         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
1612                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
1613         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
1614
1615         csb_write(tegra, XUSB_FALC_DMACTL, 0);
1616         msleep(50);
1617
1618         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
1619
1620         /* Start Falcon CPU */
1621         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
1622         usleep_range(1000, 2000);
1623
1624         fw_time = cfg_tbl->fwimg_created_time;
1625         time_to_tm(fw_time, 0, &fw_tm);
1626         dev_info(&pdev->dev,
1627                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
1628                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
1629                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
1630                 fw_tm.tm_min, fw_tm.tm_sec,
1631                 csb_read(tegra, XUSB_FALC_CPUCTL));
1632
1633         /* return fail if firmware status is not good */
1634         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
1635                 return -EFAULT;
1636
1637         cap_regs = IO_ADDRESS(tegra->host_phy_base);
1638         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
1639         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
1640
1641         /* wait for USBSTS_CNR to get set */
1642         do {
1643                 usbsts = ioread32(&op_regs->status);
1644         } while ((usbsts & STS_CNR) && count--);
1645
1646         if (!count && (usbsts & STS_CNR)) {
1647                 dev_err(&pdev->dev, "Controller not ready\n");
1648                 return -EFAULT;
1649         }
1650         return 0;
1651 }
1652
1653 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
1654         bool release)
1655 {
1656         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1657         u32 reg;
1658
1659         /* Issue is only applicable for T114 */
1660         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
1661                 return;
1662
1663         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1664         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
1665                         USB2_OTG_PAD_PORT_MASK(2));
1666
1667         if (!release) {
1668                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1669                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
1670                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1671                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
1672                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1673                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
1674         }
1675
1676         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1677 }
1678 /* SS ELPG Entry initiated by fw */
1679 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
1680 {
1681         struct xhci_hcd *xhci = tegra->xhci;
1682         u32 ret = 0;
1683
1684         must_have_sync_lock(tegra);
1685
1686         /* This is SS partition ELPG entry
1687          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
1688          */
1689
1690         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
1691          * only if it is sw initiated one
1692          */
1693
1694         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
1695          * SuperSpeed partition ELPG entry via mailbox protocol
1696          */
1697
1698         /* STEP 2: xHCI PEP driver and XUSB device mode driver
1699          * enable the XUSB wakeup interrupts for the SuperSpeed
1700          * and USB2.0 ports assigned to host.Section 4.1 Step 3
1701          */
1702         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
1703
1704         /* STEP 3: xHCI PEP driver initiates the signal sequence
1705          * to enable the XUSB SSwake detection logic for the
1706          * SuperSpeed ports assigned to host.Section 4.1 Step 4
1707          */
1708         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, true);
1709
1710         /* STEP 4: System Power Management driver asserts reset
1711          * to XUSB SuperSpeed partition then disables its clocks
1712          */
1713         tegra_periph_reset_assert(tegra->ss_clk);
1714         clk_disable(tegra->ss_clk);
1715
1716         usleep_range(100, 200);
1717
1718         /* STEP 5: System Power Management driver disables the
1719          * XUSB SuperSpeed partition power rails.
1720          */
1721         debug_print_portsc(xhci);
1722
1723         /* tegra_powergate_partition also does partition reset assert */
1724         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
1725         if (ret) {
1726                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
1727                                 __func__);
1728                 /* TODO: error recovery? */
1729         }
1730         tegra->ss_pwr_gated = true;
1731
1732         /* STEP 6: xHCI PEP driver initiates the signal sequence
1733          * to enable the XUSB SSwake detection logic for the
1734          * SuperSpeed ports assigned to host.Section 4.1 Step 7
1735          */
1736         tegra_xhci_ss_vcore(tegra->bdata->portmap, true);
1737
1738         return ret;
1739 }
1740
1741 /* Host ELPG Entry */
1742 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
1743 {
1744         struct xhci_hcd *xhci = tegra->xhci;
1745         u32 ret;
1746
1747         must_have_sync_lock(tegra);
1748
1749         /* If ss is already powergated skip ss ctx save stuff */
1750         if (tegra->ss_pwr_gated) {
1751                 xhci_info(xhci, "%s: SS partition is already powergated\n",
1752                         __func__);
1753         } else {
1754                 ret = tegra_xhci_ss_elpg_entry(tegra);
1755                 if (ret) {
1756                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
1757                                 __func__, ret);
1758                         return ret;
1759                 }
1760         }
1761
1762         /* 1. IS INTR PENDING INT_PENDING=1 ? */
1763
1764         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
1765         tegra_xhci_save_xusb_ctx(tegra);
1766
1767         pmc_init(tegra, 1);
1768
1769         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
1770         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
1771                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
1772
1773         /* STEP 4: Assert reset to host clk and disable host clk */
1774         tegra_periph_reset_assert(tegra->host_clk);
1775
1776         clk_disable(tegra->host_clk);
1777
1778         /* wait 150us */
1779         usleep_range(150, 200);
1780
1781         /* flush MC client of XUSB_HOST */
1782         tegra_powergate_mc_flush(TEGRA_POWERGATE_XUSBC);
1783
1784         /* STEP 4: Powergate host partition */
1785         /* tegra_powergate_partition also does partition reset assert */
1786         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
1787         if (ret) {
1788                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
1789                         __func__, ret);
1790                 /* TODO: error handling? */
1791                 return ret;
1792         }
1793         tegra->host_pwr_gated = true;
1794
1795         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1796                 clk_disable(tegra->pll_re_vco_clk);
1797         clk_disable(tegra->emc_clk);
1798         /* set port ownership to SNPS */
1799         tegra_xhci_release_port_ownership(tegra, true);
1800
1801         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
1802                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
1803
1804         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
1805         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
1806                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
1807         return ret;
1808 }
1809
1810 /* SS ELPG Exit triggered by PADCTL irq */
1811 /**
1812  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
1813  *
1814  * This function must be called with tegra->sync_lock acquired.
1815  *
1816  * @tegra: xhci controller context
1817  * @return 0 for success, or error numbers
1818  */
1819 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
1820 {
1821         struct xhci_hcd *xhci = tegra->xhci;
1822         int ret = 0;
1823
1824         must_have_sync_lock(tegra);
1825
1826         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
1827                         tegra->hs_wake_event || tegra->host_resume_req)) {
1828
1829                 /*
1830                  * PWR_UNGATE SS partition. XUSBA
1831                  * tegra_unpowergate_partition also does partition reset
1832                  * deassert
1833                  */
1834                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
1835                 if (ret) {
1836                         xhci_err(xhci,
1837                         "%s: could not unpowergate xusba partition %d\n",
1838                         __func__, ret);
1839                         goto out;
1840                 }
1841                 if (tegra->ss_wake_event)
1842                         tegra->ss_wake_event = false;
1843
1844         } else {
1845                 xhci_info(xhci, "%s: ss already power gated\n",
1846                         __func__);
1847                 return ret;
1848         }
1849
1850         /* Step 3: Enable clock to ss partition */
1851         clk_enable(tegra->ss_clk);
1852
1853         /* Step 4: Disable ss wake detection logic */
1854         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
1855
1856         /* Step 4.1: Disable ss wake detection logic */
1857         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
1858
1859         /* wait 150us */
1860         usleep_range(150, 200);
1861
1862         /* Step 4.2: Disable ss wake detection logic */
1863         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
1864
1865         /* Step 6 Deassert reset for ss clks */
1866         tegra_periph_reset_deassert(tegra->ss_clk);
1867
1868         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
1869         tegra->ss_pwr_gated = false;
1870 out:
1871         return ret;
1872 }
1873
1874 static void ss_partition_elpg_exit_work(struct work_struct *work)
1875 {
1876         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
1877                 ss_elpg_exit_work);
1878
1879         mutex_lock(&tegra->sync_lock);
1880         tegra_xhci_ss_partition_elpg_exit(tegra);
1881         mutex_unlock(&tegra->sync_lock);
1882 }
1883
1884 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
1885 static void update_remote_wakeup_ports_pmc(struct tegra_xhci_hcd *tegra)
1886 {
1887         struct xhci_hcd *xhci = tegra->xhci;
1888         u32 wake2_status;
1889
1890 #define PMC_WAKE2_STATUS        0x168
1891 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
1892
1893         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
1894
1895         if (wake2_status & PADCTL_WAKE) {
1896                 /* FIXME: This is customized for Dalmore, find a generic way */
1897                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
1898                 /* clear wake status */
1899                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
1900         }
1901
1902         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
1903                         __func__, tegra->usb3_rh_remote_wakeup_ports);
1904 }
1905
1906 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
1907 {
1908         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1909         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
1910         int port, num_ports;
1911         unsigned long *remote_wakeup_ports;
1912         u32 portsc;
1913         __le32 __iomem  **port_array;
1914         unsigned char *rh;
1915         unsigned int retry = 64;
1916
1917
1918         if (hcd == xhci->shared_hcd) {
1919                 port_array = xhci->usb3_ports;
1920                 num_ports = xhci->num_usb3_ports;
1921                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
1922                 rh = "usb3 roothub";
1923         } else
1924                 return;
1925
1926         while (*remote_wakeup_ports && retry--) {
1927                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
1928                         portsc = xhci_readl(xhci, port_array[port]);
1929
1930                         if (!(portsc & PORT_CONNECT)) {
1931                                 /* nothing to do if already disconnected */
1932                                 clear_bit(port, remote_wakeup_ports);
1933                                 continue;
1934                         }
1935
1936                         if ((portsc & PORT_PLS_MASK) == XDEV_U0)
1937                                 clear_bit(port, remote_wakeup_ports);
1938                         else
1939                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
1940                                                 __func__, rh, port, portsc);
1941                 }
1942
1943                 if (*remote_wakeup_ports)
1944                         msleep(20); /* give some time, irq will direct U0 */
1945         }
1946
1947         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
1948                         *remote_wakeup_ports);
1949 }
1950
1951 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
1952 {
1953         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1954         u32 reg, utmip_rctrl_val, utmip_tctrl_val;
1955
1956         /* Program XUSB as port owner for all usb2 ports */
1957         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1958         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
1959                         USB2_OTG_PAD_PORT_MASK(2));
1960         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
1961                 USB2_OTG_PAD_PORT_OWNER_XUSB(1) | USB2_OTG_PAD_PORT_MASK(2);
1962         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1963
1964         /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
1965          * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
1966          */
1967         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1968         reg &= ~((1 << 12) | (1 << 13));
1969         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1970
1971         /* wait 20us */
1972         usleep_range(20, 30);
1973
1974         /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
1975          * :: TCTRL and RCTRL
1976          */
1977         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl1_0);
1978         utmip_rctrl_val = RCTRL(reg);
1979         utmip_tctrl_val = TCTRL(reg);
1980
1981         /*
1982          * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
1983          * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
1984          */
1985         pmc_data.utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
1986         pmc_data.utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
1987
1988         xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
1989                 pmc_data.utmip_rctrl_val, pmc_data.utmip_tctrl_val);
1990
1991         /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
1992          * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
1993          */
1994         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1995         reg |= (1 << 13);
1996         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1997
1998         /* Program these values into PMC regiseter and program the
1999          * PMC override
2000          */
2001         reg = PMC_TCTRL_VAL(pmc_data.utmip_tctrl_val) |
2002                 PMC_RCTRL_VAL(pmc_data.utmip_rctrl_val);
2003         tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG, 0xffffffff, reg);
2004
2005         reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
2006         tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
2007
2008         /* Restore correct port ownership in padctl */
2009         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2010         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2011                         USB2_OTG_PAD_PORT_MASK(2));
2012         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2013                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2014         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2015                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2016         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2017                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2018         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2019 }
2020
2021 /* Host ELPG Exit triggered by PADCTL irq */
2022 /**
2023  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
2024  *
2025  * This function must be called with tegra->sync_lock acquired.
2026  *
2027  * @tegra: xhci controller context
2028  * @return 0 for success, or error numbers
2029  */
2030 static int
2031 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2032 {
2033         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2034         struct xhci_hcd *xhci = tegra->xhci;
2035         int ret = 0;
2036
2037         must_have_sync_lock(tegra);
2038
2039         if (!tegra->hc_in_elpg)
2040                 return 0;
2041
2042         clk_enable(tegra->emc_clk);
2043         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2044                 clk_enable(tegra->pll_re_vco_clk);
2045         /* Step 2: Enable clock to host partition */
2046         clk_enable(tegra->host_clk);
2047
2048         if (tegra->lp0_exit) {
2049                 u32 reg, oc_bits = 0;
2050
2051                 /* Issue is only applicable for T114 */
2052                 if (XUSB_DEVICE_ID_T114 == tegra->device_id)
2053                         tegra_xhci_war_for_tctrl_rctrl(tegra);
2054                 /* check if over current seen. Clear if present */
2055                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2056                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2057                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2058                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2059                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2060                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2061
2062                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2063                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
2064                 if (reg & oc_bits) {
2065                         xhci_info(xhci, "Over current detected. Clearing...\n");
2066                         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2067
2068                         usleep_range(100, 200);
2069
2070                         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2071                         if (reg & oc_bits)
2072                                 xhci_info(xhci, "Over current still present\n");
2073                 }
2074                 tegra_xhci_padctl_portmap_and_caps(tegra);
2075                 /* release clamps post deassert */
2076                 tegra->lp0_exit = false;
2077         }
2078
2079         /* Clear FLUSH_ENABLE of MC client */
2080         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
2081
2082         /* set port ownership back to xusb */
2083         tegra_xhci_release_port_ownership(tegra, false);
2084
2085         /*
2086          * PWR_UNGATE Host partition. XUSBC
2087          * tegra_unpowergate_partition also does partition reset deassert
2088          */
2089         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
2090         if (ret) {
2091                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2092                         __func__, ret);
2093                 goto out;
2094         }
2095
2096         /* Step 4: Deassert reset to host partition clk */
2097         tegra_periph_reset_deassert(tegra->host_clk);
2098
2099         /* Step 6.1: IPFS and XUSB BAR initialization */
2100         tegra_xhci_cfg(tegra);
2101
2102         /* Step 6.2: IPFS and XUSB related restore */
2103         tegra_xhci_restore_ctx(tegra);
2104
2105         /* Step 8: xhci spec related ctx restore
2106          * will be done in xhci_resume().Do it here.
2107          */
2108
2109         tegra_xhci_ss_partition_elpg_exit(tegra);
2110
2111         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
2112         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
2113                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
2114                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
2115         }
2116
2117         /* clear ovrd bits */
2118         tegra_xhci_rx_idle_mode_override(tegra, false);
2119
2120         /* Load firmware */
2121         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
2122                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
2123                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
2124                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
2125                         __func__,
2126                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
2127                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
2128                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
2129                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
2130                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
2131                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
2132                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
2133                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
2134                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
2135         debug_print_portsc(xhci);
2136
2137         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
2138         if (ret < 0) {
2139                 xhci_err(xhci, "%s: failed to load firmware %d\n",
2140                         __func__, ret);
2141                 goto out;
2142         }
2143
2144         pmc_init(tegra, 0);
2145
2146         tegra->hc_in_elpg = false;
2147         ret = xhci_resume(tegra->xhci, 0);
2148         if (ret) {
2149                 xhci_err(xhci, "%s: could not resume right %d\n",
2150                                 __func__, ret);
2151                 goto out;
2152         }
2153
2154         update_remote_wakeup_ports_pmc(tegra);
2155
2156         if (tegra->hs_wake_event)
2157                 tegra->hs_wake_event = false;
2158
2159         if (tegra->host_resume_req)
2160                 tegra->host_resume_req = false;
2161
2162         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
2163                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
2164
2165         tegra->host_pwr_gated = false;
2166 out:
2167         return ret;
2168 }
2169
2170 static void host_partition_elpg_exit_work(struct work_struct *work)
2171 {
2172         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2173                 host_elpg_exit_work);
2174
2175         mutex_lock(&tegra->sync_lock);
2176         tegra_xhci_host_partition_elpg_exit(tegra);
2177         mutex_unlock(&tegra->sync_lock);
2178 }
2179
2180 /* Mailbox handling function. This function handles requests
2181  * from firmware and communicates with clock and powergating
2182  * module to alter clock rates and to power gate/ungate xusb
2183  * partitions.
2184  *
2185  * Following is the structure of mailbox messages.
2186  * bit 31:28 - msg type
2187  * bits 27:0 - mbox data
2188  * FIXME:  Check if we can just call clock functions like below
2189  * or should we schedule it for calling later ?
2190  */
2191
2192 static void
2193 tegra_xhci_process_mbox_message(struct work_struct *work)
2194 {
2195         u32 sw_resp = 0, cmd, data_in, fw_msg;
2196         int ret = 0;
2197         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2198                                         mbox_work);
2199         struct xhci_hcd *xhci = tegra->xhci;
2200         unsigned int freq_khz;
2201
2202         mutex_lock(&tegra->mbox_lock);
2203
2204         /* get the owner id */
2205         tegra->mbox_owner = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2206         tegra->mbox_owner &= MBOX_OWNER_ID_MASK;
2207
2208         /* get the mbox message from firmware */
2209         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
2210
2211         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2212         if (data_in) {
2213                 mutex_unlock(&tegra->mbox_lock);
2214                 return;
2215         }
2216
2217         /* get cmd type and cmd data */
2218         tegra->cmd_type = (fw_msg & MBOX_CMD_TYPE_MASK) >> MBOX_CMD_SHIFT;
2219         tegra->cmd_data = (fw_msg & MBOX_CMD_DATA_MASK);
2220
2221         /* decode the message and make appropriate requests to
2222          * clock or powergating module.
2223          */
2224
2225         switch (tegra->cmd_type) {
2226         case MBOX_CMD_INC_FALC_CLOCK:
2227         case MBOX_CMD_DEC_FALC_CLOCK:
2228                 ret = tegra_xusb_request_clk_rate(
2229                                 tegra,
2230                                 tegra->falc_clk,
2231                                 tegra->cmd_data,
2232                                 &sw_resp);
2233                 if (ret)
2234                         xhci_err(xhci, "%s: could not set required falc rate\n",
2235                                 __func__);
2236                 goto send_sw_response;
2237         case MBOX_CMD_INC_SSPI_CLOCK:
2238         case MBOX_CMD_DEC_SSPI_CLOCK:
2239                 ret = tegra_xusb_request_clk_rate(
2240                                 tegra,
2241                                 tegra->ss_src_clk,
2242                                 tegra->cmd_data,
2243                                 &sw_resp);
2244                 if (ret)
2245                         xhci_err(xhci, "%s: could not set required ss rate.\n",
2246                                 __func__);
2247                 goto send_sw_response;
2248         case MBOX_CMD_SET_BW:
2249                 /* fw sends BW request in MByte/sec */
2250                 freq_khz = tegra_emc_bw_to_freq_req(tegra->cmd_data << 10);
2251                 clk_set_rate(tegra->emc_clk, freq_khz * 1000);
2252
2253                 /* clear MBOX_SMI_INT_EN bit */
2254                 cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2255                 cmd &= ~MBOX_SMI_INT_EN;
2256                 writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2257
2258                 /* clear mbox owner as ACK will not be sent for this request */
2259                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2260                 break;
2261         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
2262                 tegra_xhci_save_dfe_ctle_context(tegra, tegra->cmd_data);
2263                 tegra_xhci_restore_dfe_ctle_context(tegra, tegra->cmd_data);
2264                 /* SATA lane also if USB3_SS port1 mapped to it */
2265                 if (tegra->cmd_data == 0x1 &&
2266                         XUSB_DEVICE_ID_T124 == tegra->device_id &&
2267                                 tegra->bdata->lane_owner & BIT(0)) {
2268                         tegra_xhci_save_dfe_ctle_context(tegra, 3);
2269                         tegra_xhci_restore_dfe_ctle_context(tegra, 3);
2270                 }
2271
2272                 sw_resp |= (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
2273                 goto send_sw_response;
2274         case MBOX_CMD_ACK:
2275                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2276                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2277                 break;
2278         case MBOX_CMD_NACK:
2279                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2280                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2281                 break;
2282         default:
2283                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
2284                                 __func__, tegra->cmd_type);
2285         }
2286         mutex_unlock(&tegra->mbox_lock);
2287         return;
2288
2289 send_sw_response:
2290         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2291         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2292         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
2293         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2294
2295         mutex_unlock(&tegra->mbox_lock);
2296 }
2297
2298 static irqreturn_t tegra_xhci_xusb_host_irq(int irq, void *ptrdev)
2299 {
2300         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2301         struct xhci_hcd *xhci = tegra->xhci;
2302
2303         xhci_dbg(xhci, "%s", __func__);
2304         return IRQ_HANDLED;
2305 }
2306
2307 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
2308 {
2309         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2310         struct xhci_hcd *xhci = tegra->xhci;
2311         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2312         u32 elpg_program0 = 0;
2313
2314         spin_lock(&tegra->lock);
2315
2316         tegra->last_jiffies = jiffies;
2317
2318         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
2319         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
2320
2321         /* Clear the interrupt cause. We already read the intr status. */
2322         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2323         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
2324
2325         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
2326         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
2327                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2328         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
2329                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
2330         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
2331                 __func__,
2332                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad0_ctl0_0));
2333         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
2334                 __func__,
2335                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad1_ctl0_0));
2336         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
2337                 __func__,
2338                 readl(tegra->padctl_base + padregs->usb2_bchrg_bias_pad_0));
2339
2340         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
2341                 tegra->ss_wake_event = true;
2342         else if (elpg_program0 &
2343                         (USB2_PORT0_WAKEUP_EVENT | USB2_PORT1_WAKEUP_EVENT))
2344                 tegra->hs_wake_event = true;
2345
2346         if (tegra->ss_wake_event || tegra->hs_wake_event) {
2347                 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
2348                         xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
2349                         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
2350                 } else if (tegra->ss_pwr_gated
2351                                 && tegra->host_pwr_gated) {
2352                         xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
2353                                 __func__);
2354                         schedule_work(&tegra->host_elpg_exit_work);
2355                 }
2356         } else {
2357                 xhci_err(xhci, "error: wake due to no hs/ss event\n");
2358                 tegra_usb_pad_reg_write(padregs->elpg_program_0, 0xffffffff);
2359         }
2360         spin_unlock(&tegra->lock);
2361         return IRQ_HANDLED;
2362 }
2363
2364 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
2365 {
2366         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2367         u32 temp;
2368
2369         spin_lock(&tegra->lock);
2370
2371         /* clear the mbox intr status 1st thing. Other
2372          * bits are W1C bits, so just write to SMI bit.
2373          */
2374
2375         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
2376
2377         /* write 1 to clear SMI INTR en bit ( bit 3 ) */
2378         temp = MBOX_SMI_INTR_EN;
2379         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
2380
2381         schedule_work(&tegra->mbox_work);
2382
2383         spin_unlock(&tegra->lock);
2384         return IRQ_HANDLED;
2385 }
2386
2387 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
2388 {
2389         /*
2390          * As of now platform drivers don't provide MSI support so we ensure
2391          * here that the generic code does not try to make a pci_dev from our
2392          * dev struct in order to setup MSI
2393          */
2394         xhci->quirks |= XHCI_BROKEN_MSI;
2395         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
2396 }
2397
2398 /* called during probe() after chip reset completes */
2399 static int xhci_plat_setup(struct usb_hcd *hcd)
2400 {
2401         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
2402 }
2403
2404 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
2405         const char *name, void __iomem **region)
2406 {
2407         struct resource *res;
2408         void __iomem *mem;
2409
2410         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
2411         if (!res) {
2412                 dev_err(&pdev->dev, "memory resource %s doesn't exist\n", name);
2413                 return -ENODEV;
2414         }
2415
2416         mem = devm_request_and_ioremap(&pdev->dev, res);
2417         if (!mem) {
2418                 dev_err(&pdev->dev, "failed to ioremap for %s\n", name);
2419                 return -EFAULT;
2420         }
2421         *region = mem;
2422
2423         return 0;
2424 }
2425
2426 static int tegra_xhci_request_irq(struct platform_device *pdev,
2427         const char *rscname, irq_handler_t handler, unsigned long irqflags,
2428         const char *devname, int *irq_no)
2429 {
2430         int ret;
2431         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2432         struct resource *res;
2433
2434         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, rscname);
2435         if (!res) {
2436                 dev_err(&pdev->dev, "irq resource %s doesn't exist\n", rscname);
2437                 return -ENODEV;
2438         }
2439
2440         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
2441                         devname, tegra);
2442         if (ret != 0) {
2443                 dev_err(&pdev->dev,
2444                         "failed to request_irq for %s (irq %d), error = %d\n",
2445                         devname, res->start, ret);
2446                 return ret;
2447         }
2448         *irq_no = res->start;
2449
2450         return 0;
2451 }
2452
2453 #ifdef CONFIG_PM
2454
2455 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
2456 {
2457         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2458         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2459         int err = 0;
2460         unsigned long flags;
2461
2462         mutex_lock(&tegra->sync_lock);
2463
2464         if (xhci->shared_hcd == hcd) {
2465                 tegra->usb3_rh_suspend = true;
2466                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
2467         } else if (xhci->main_hcd == hcd) {
2468                 tegra->usb2_rh_suspend = true;
2469                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
2470         }
2471
2472         WARN_ON(tegra->hc_in_elpg);
2473
2474         /* suspend xhci bus. This will also set remote mask */
2475         err = xhci_bus_suspend(hcd);
2476         if (err) {
2477                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
2478                                 __func__, err);
2479                 goto xhci_bus_suspend_failed;
2480         }
2481
2482         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
2483                 goto done; /* one of the root hubs is still working */
2484
2485         spin_lock_irqsave(&tegra->lock, flags);
2486         tegra->hc_in_elpg = true;
2487         spin_unlock_irqrestore(&tegra->lock, flags);
2488
2489         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
2490
2491         /* save xhci spec ctx. Already done by xhci_suspend */
2492         err = xhci_suspend(tegra->xhci);
2493         if (err) {
2494                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
2495                 goto xhci_suspend_failed;
2496         }
2497
2498         /* Powergate host. Include ss power gate if not already done */
2499         err = tegra_xhci_host_elpg_entry(tegra);
2500         if (err) {
2501                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
2502                                 __func__, err);
2503                 goto tegra_xhci_host_elpg_entry_failed;
2504         }
2505
2506         /* At this point,ensure ss/hs intr enables are always on */
2507         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2508         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2509
2510 done:
2511         /* pads are disabled only if usb2 root hub in xusb is idle */
2512         /* pads will actually be disabled only when all usb2 ports are idle */
2513         if (xhci->main_hcd == hcd) {
2514                 utmi_phy_pad_disable();
2515                 utmi_phy_iddq_override(true);
2516         }
2517         mutex_unlock(&tegra->sync_lock);
2518         return 0;
2519
2520 tegra_xhci_host_elpg_entry_failed:
2521
2522 xhci_suspend_failed:
2523         tegra->hc_in_elpg = false;
2524 xhci_bus_suspend_failed:
2525         if (xhci->shared_hcd == hcd)
2526                 tegra->usb3_rh_suspend = false;
2527         else if (xhci->main_hcd == hcd)
2528                 tegra->usb2_rh_suspend = false;
2529
2530         mutex_unlock(&tegra->sync_lock);
2531         return err;
2532 }
2533
2534 /* First, USB2HCD and then USB3HCD resume will be called */
2535 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
2536 {
2537         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2538         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2539         int err = 0;
2540
2541         mutex_lock(&tegra->sync_lock);
2542
2543         tegra->host_resume_req = true;
2544
2545         if (xhci->shared_hcd == hcd)
2546                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
2547         else if (xhci->main_hcd == hcd)
2548                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
2549
2550         /* pads are disabled only if usb2 root hub in xusb is idle */
2551         /* pads will actually be disabled only when all usb2 ports are idle */
2552         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
2553                 utmi_phy_pad_enable();
2554                 utmi_phy_iddq_override(false);
2555         }
2556         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
2557                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
2558                         tegra_xhci_host_partition_elpg_exit(tegra);
2559         }
2560
2561          /* handle remote wakeup before resuming bus */
2562         wait_remote_wakeup_ports(hcd);
2563
2564         err = xhci_bus_resume(hcd);
2565         if (err) {
2566                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
2567                                 __func__, err);
2568                 goto xhci_bus_resume_failed;
2569         }
2570
2571         if (xhci->shared_hcd == hcd)
2572                 tegra->usb3_rh_suspend = false;
2573         else if (xhci->main_hcd == hcd)
2574                 tegra->usb2_rh_suspend = false;
2575
2576         mutex_unlock(&tegra->sync_lock);
2577         return 0;
2578
2579 xhci_bus_resume_failed:
2580         /* TODO: reverse elpg? */
2581         mutex_unlock(&tegra->sync_lock);
2582         return err;
2583 }
2584 #endif
2585
2586 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
2587 {
2588         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2589         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2590         irqreturn_t iret = IRQ_HANDLED;
2591         u32 status;
2592
2593         spin_lock(&tegra->lock);
2594         if (tegra->hc_in_elpg) {
2595                 spin_lock(&xhci->lock);
2596                 if (HCD_HW_ACCESSIBLE(hcd)) {
2597                         status = xhci_readl(xhci, &xhci->op_regs->status);
2598                         status |= STS_EINT;
2599                         xhci_writel(xhci, status, &xhci->op_regs->status);
2600                 }
2601                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
2602                                 __func__);
2603                 schedule_work(&tegra->host_elpg_exit_work);
2604                 spin_unlock(&xhci->lock);
2605         } else
2606                 iret = xhci_irq(hcd);
2607         spin_unlock(&tegra->lock);
2608
2609         return iret;
2610 }
2611
2612
2613 static const struct hc_driver tegra_plat_xhci_driver = {
2614         .description =          "tegra-xhci",
2615         .product_desc =         "Nvidia xHCI Host Controller",
2616         .hcd_priv_size =        sizeof(struct xhci_hcd *),
2617
2618         /*
2619          * generic hardware linkage
2620          */
2621         .irq =                  tegra_xhci_irq,
2622         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
2623
2624         /*
2625          * basic lifecycle operations
2626          */
2627         .reset =                xhci_plat_setup,
2628         .start =                xhci_run,
2629         .stop =                 xhci_stop,
2630         .shutdown =             xhci_shutdown,
2631
2632         /*
2633          * managing i/o requests and associated device resources
2634          */
2635         .urb_enqueue =          xhci_urb_enqueue,
2636         .urb_dequeue =          xhci_urb_dequeue,
2637         .alloc_dev =            xhci_alloc_dev,
2638         .free_dev =             xhci_free_dev,
2639         .alloc_streams =        xhci_alloc_streams,
2640         .free_streams =         xhci_free_streams,
2641         .add_endpoint =         xhci_add_endpoint,
2642         .drop_endpoint =        xhci_drop_endpoint,
2643         .endpoint_reset =       xhci_endpoint_reset,
2644         .check_bandwidth =      xhci_check_bandwidth,
2645         .reset_bandwidth =      xhci_reset_bandwidth,
2646         .address_device =       xhci_address_device,
2647         .update_hub_device =    xhci_update_hub_device,
2648         .reset_device =         xhci_discover_or_reset_device,
2649
2650         /*
2651          * scheduling support
2652          */
2653         .get_frame_number =     xhci_get_frame,
2654
2655         /* Root hub support */
2656         .hub_control =          xhci_hub_control,
2657         .hub_status_data =      xhci_hub_status_data,
2658
2659 #ifdef CONFIG_PM
2660         .bus_suspend =          tegra_xhci_bus_suspend,
2661         .bus_resume =           tegra_xhci_bus_resume,
2662 #endif
2663 };
2664
2665 #ifdef CONFIG_PM
2666 static int
2667 tegra_xhci_suspend(struct platform_device *pdev,
2668                                                 pm_message_t state)
2669 {
2670         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2671         struct xhci_hcd *xhci = tegra->xhci;
2672
2673         int ret = 0;
2674
2675         mutex_lock(&tegra->sync_lock);
2676         if (!tegra->hc_in_elpg) {
2677                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
2678                                 __func__);
2679                 mutex_unlock(&tegra->sync_lock);
2680                 return -EBUSY;
2681         }
2682         mutex_unlock(&tegra->sync_lock);
2683
2684         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2685         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
2686
2687         /* enable_irq_wake for ss ports */
2688         ret = enable_irq_wake(tegra->padctl_irq);
2689         if (ret < 0) {
2690                 xhci_err(xhci,
2691                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
2692                 __func__, tegra->padctl_irq, ret);
2693         }
2694
2695         /* enable_irq_wake for hs/fs/ls ports */
2696         ret = enable_irq_wake(tegra->usb3_irq);
2697         if (ret < 0) {
2698                 xhci_err(xhci,
2699                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
2700                 __func__, tegra->usb3_irq, ret);
2701         }
2702         regulator_disable(tegra->xusb_s1p8v_reg);
2703         regulator_disable(tegra->xusb_s1p05v_reg);
2704         tegra_usb2_clocks_deinit(tegra);
2705
2706         return ret;
2707 }
2708
2709 static int
2710 tegra_xhci_resume(struct platform_device *pdev)
2711 {
2712         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2713
2714         dev_dbg(&pdev->dev, "%s\n", __func__);
2715
2716         tegra->last_jiffies = jiffies;
2717
2718         disable_irq_wake(tegra->padctl_irq);
2719         disable_irq_wake(tegra->usb3_irq);
2720         tegra->lp0_exit = true;
2721
2722         regulator_enable(tegra->xusb_s1p05v_reg);
2723         regulator_enable(tegra->xusb_s1p8v_reg);
2724         tegra_usb2_clocks_init(tegra);
2725
2726         return 0;
2727 }
2728 #endif
2729
2730
2731 static int init_bootloader_firmware(struct tegra_xhci_hcd *tegra)
2732 {
2733         struct platform_device *pdev = tegra->pdev;
2734         void __iomem *fw_mmio_base;
2735         phys_addr_t fw_mem_phy_addr;
2736         size_t fw_size;
2737         dma_addr_t fw_dma;
2738 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2739         int ret;
2740 #endif
2741
2742         /* bootloader saved firmware memory address in PMC SCRATCH34 register */
2743         fw_mem_phy_addr = tegra_usb_pmc_reg_read(PMC_SCRATCH34);
2744
2745         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
2746                         fw_mem_phy_addr, sizeof(struct cfgtbl));
2747
2748         if (!fw_mmio_base) {
2749                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
2750                                         fw_mem_phy_addr);
2751                         return -ENOMEM;
2752         }
2753
2754         fw_size = ioread32(fw_mmio_base + FW_SIZE_OFFSET);
2755         devm_iounmap(&pdev->dev, fw_mmio_base);
2756
2757         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
2758                         fw_mem_phy_addr, fw_size);
2759         if (!fw_mmio_base) {
2760                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
2761                                         fw_mem_phy_addr);
2762                         return -ENOMEM;
2763         }
2764
2765         dev_info(&pdev->dev, "Firmware Memory: phy 0x%x mapped 0x%p (%d Bytes)\n",
2766                         fw_mem_phy_addr, fw_mmio_base, fw_size);
2767
2768 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2769         fw_dma = dma_map_linear(&pdev->dev, fw_mem_phy_addr, fw_size,
2770                         DMA_TO_DEVICE);
2771         if (fw_dma == DMA_ERROR_CODE) {
2772                 dev_err(&pdev->dev, "%s: dma_map_linear failed\n",
2773                                 __func__);
2774                 ret = -ENOMEM;
2775                 goto error_iounmap;
2776         }
2777 #else
2778         fw_dma = fw_mem_phy_addr;
2779 #endif
2780         dev_info(&pdev->dev, "Firmware DMA Memory: dma 0x%p (%d Bytes)\n",
2781                         (void *) fw_dma, fw_size);
2782
2783         /* all set and ready to go */
2784         tegra->firmware.data = fw_mmio_base;
2785         tegra->firmware.dma = fw_dma;
2786         tegra->firmware.size = fw_size;
2787
2788         return 0;
2789
2790 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2791 error_iounmap:
2792         devm_iounmap(&pdev->dev, fw_mmio_base);
2793         return ret;
2794 #endif
2795 }
2796
2797 static void deinit_bootloader_firmware(struct tegra_xhci_hcd *tegra)
2798 {
2799         struct platform_device *pdev = tegra->pdev;
2800         void __iomem *fw_mmio_base = tegra->firmware.data;
2801
2802 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2803         dma_unmap_single(&pdev->dev, tegra->firmware.dma,
2804                         tegra->firmware.size, DMA_TO_DEVICE);
2805 #endif
2806         devm_iounmap(&pdev->dev, fw_mmio_base);
2807
2808         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
2809 }
2810
2811 static int init_firmware(struct tegra_xhci_hcd *tegra)
2812 {
2813         return init_bootloader_firmware(tegra);
2814 }
2815
2816 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
2817 {
2818         deinit_bootloader_firmware(tegra);
2819 }
2820
2821 static struct tegra_xusb_padctl_regs t114_padregs_offset = {
2822         .boot_media_0                   = 0x0,
2823         .usb2_pad_mux_0                 = 0x4,
2824         .usb2_port_cap_0                = 0x8,
2825         .snps_oc_map_0                  = 0xc,
2826         .usb2_oc_map_0                  = 0x10,
2827         .ss_port_map_0                  = 0x14,
2828         .oc_det_0                       = 0x18,
2829         .elpg_program_0                 = 0x1c,
2830         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
2831         .usb2_bchrg_otgpad0_ctl1_0      = 0xffff,
2832         .usb2_bchrg_otgpad1_ctl0_0      = 0x24,
2833         .usb2_bchrg_otgpad1_ctl1_0      = 0xffff,
2834         .usb2_bchrg_otgpad2_ctl0_0      = 0xffff,
2835         .usb2_bchrg_otgpad2_ctl1_0      = 0xffff,
2836         .usb2_bchrg_bias_pad_0          = 0x28,
2837         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
2838         .iophy_pll_p0_ctl1_0            = 0x30,
2839         .iophy_pll_p0_ctl2_0            = 0x34,
2840         .iophy_pll_p0_ctl3_0            = 0x38,
2841         .iophy_pll_p0_ctl4_0            = 0x3c,
2842         .iophy_usb3_pad0_ctl1_0         = 0x40,
2843         .iophy_usb3_pad1_ctl1_0         = 0x44,
2844         .iophy_usb3_pad0_ctl2_0         = 0x48,
2845         .iophy_usb3_pad1_ctl2_0         = 0x4c,
2846         .iophy_usb3_pad0_ctl3_0         = 0x50,
2847         .iophy_usb3_pad1_ctl3_0         = 0x54,
2848         .iophy_usb3_pad0_ctl4_0         = 0x58,
2849         .iophy_usb3_pad1_ctl4_0         = 0x5c,
2850         .iophy_misc_pad_p0_ctl1_0       = 0x60,
2851         .iophy_misc_pad_p1_ctl1_0       = 0x64,
2852         .iophy_misc_pad_p0_ctl2_0       = 0x68,
2853         .iophy_misc_pad_p1_ctl2_0       = 0x6c,
2854         .iophy_misc_pad_p0_ctl3_0       = 0x70,
2855         .iophy_misc_pad_p1_ctl3_0       = 0x74,
2856         .iophy_misc_pad_p0_ctl4_0       = 0x78,
2857         .iophy_misc_pad_p1_ctl4_0       = 0x7c,
2858         .iophy_misc_pad_p0_ctl5_0       = 0x80,
2859         .iophy_misc_pad_p1_ctl5_0       = 0x84,
2860         .iophy_misc_pad_p0_ctl6_0       = 0x88,
2861         .iophy_misc_pad_p1_ctl6_0       = 0x8c,
2862         .usb2_otg_pad0_ctl0_0           = 0x90,
2863         .usb2_otg_pad1_ctl0_0           = 0x94,
2864         .usb2_otg_pad2_ctl0_0           = 0xffff,
2865         .usb2_otg_pad0_ctl1_0           = 0x98,
2866         .usb2_otg_pad1_ctl1_0           = 0x9c,
2867         .usb2_otg_pad2_ctl1_0           = 0xffff,
2868         .usb2_bias_pad_ctl0_0           = 0xa0,
2869         .usb2_bias_pad_ctl1_0           = 0xa4,
2870         .usb2_hsic_pad0_ctl0_0          = 0xa8,
2871         .usb2_hsic_pad1_ctl0_0          = 0xac,
2872         .usb2_hsic_pad0_ctl1_0          = 0xb0,
2873         .usb2_hsic_pad1_ctl1_0          = 0xb4,
2874         .usb2_hsic_pad0_ctl2_0          = 0xb8,
2875         .usb2_hsic_pad1_ctl2_0          = 0xbc,
2876         .ulpi_link_trim_ctl0            = 0xc0,
2877         .ulpi_null_clk_trim_ctl0        = 0xc4,
2878         .hsic_strb_trim_ctl0            = 0xc8,
2879         .wake_ctl0                      = 0xcc,
2880         .pm_spare0                      = 0xd0,
2881         .iophy_misc_pad_p2_ctl1_0       = 0xffff,
2882         .iophy_misc_pad_p3_ctl1_0       = 0xffff,
2883         .iophy_misc_pad_p4_ctl1_0       = 0xffff,
2884         .iophy_misc_pad_p2_ctl2_0       = 0xffff,
2885         .iophy_misc_pad_p3_ctl2_0       = 0xffff,
2886         .iophy_misc_pad_p4_ctl2_0       = 0xffff,
2887         .iophy_misc_pad_p2_ctl3_0       = 0xffff,
2888         .iophy_misc_pad_p3_ctl3_0       = 0xffff,
2889         .iophy_misc_pad_p4_ctl3_0       = 0xffff,
2890         .iophy_misc_pad_p2_ctl4_0       = 0xffff,
2891         .iophy_misc_pad_p3_ctl4_0       = 0xffff,
2892         .iophy_misc_pad_p4_ctl4_0       = 0xffff,
2893         .iophy_misc_pad_p2_ctl5_0       = 0xffff,
2894         .iophy_misc_pad_p3_ctl5_0       = 0xffff,
2895         .iophy_misc_pad_p4_ctl5_0       = 0xffff,
2896         .iophy_misc_pad_p2_ctl6_0       = 0xffff,
2897         .iophy_misc_pad_p3_ctl6_0       = 0xffff,
2898         .iophy_misc_pad_p4_ctl6_0       = 0xffff,
2899         .usb3_pad_mux_0                 = 0xffff,
2900         .iophy_pll_s0_ctl1_0            = 0xffff,
2901         .iophy_pll_s0_ctl2_0            = 0xffff,
2902         .iophy_pll_s0_ctl3_0            = 0xffff,
2903         .iophy_pll_s0_ctl4_0            = 0xffff,
2904         .iophy_misc_pad_s0_ctl1_0       = 0xffff,
2905         .iophy_misc_pad_s0_ctl2_0       = 0xffff,
2906         .iophy_misc_pad_s0_ctl3_0       = 0xffff,
2907         .iophy_misc_pad_s0_ctl4_0       = 0xffff,
2908         .iophy_misc_pad_s0_ctl5_0       = 0xffff,
2909         .iophy_misc_pad_s0_ctl6_0       = 0xffff,
2910 };
2911
2912 static struct tegra_xusb_padctl_regs t124_padregs_offset = {
2913         .boot_media_0                   = 0x0,
2914         .usb2_pad_mux_0                 = 0x4,
2915         .usb2_port_cap_0                = 0x8,
2916         .snps_oc_map_0                  = 0xc,
2917         .usb2_oc_map_0                  = 0x10,
2918         .ss_port_map_0                  = 0x14,
2919         .oc_det_0                       = 0x18,
2920         .elpg_program_0                 = 0x1c,
2921         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
2922         .usb2_bchrg_otgpad0_ctl1_0      = 0x24,
2923         .usb2_bchrg_otgpad1_ctl0_0      = 0x28,
2924         .usb2_bchrg_otgpad1_ctl1_0      = 0x2c,
2925         .usb2_bchrg_otgpad2_ctl0_0      = 0x30,
2926         .usb2_bchrg_otgpad2_ctl1_0      = 0x34,
2927         .usb2_bchrg_bias_pad_0          = 0x38,
2928         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
2929         .iophy_pll_p0_ctl1_0            = 0x40,
2930         .iophy_pll_p0_ctl2_0            = 0x44,
2931         .iophy_pll_p0_ctl3_0            = 0x48,
2932         .iophy_pll_p0_ctl4_0            = 0x4c,
2933         .iophy_usb3_pad0_ctl1_0         = 0x50,
2934         .iophy_usb3_pad1_ctl1_0         = 0x54,
2935         .iophy_usb3_pad0_ctl2_0         = 0x58,
2936         .iophy_usb3_pad1_ctl2_0         = 0x5c,
2937         .iophy_usb3_pad0_ctl3_0         = 0x60,
2938         .iophy_usb3_pad1_ctl3_0         = 0x64,
2939         .iophy_usb3_pad0_ctl4_0         = 0x68,
2940         .iophy_usb3_pad1_ctl4_0         = 0x6c,
2941         .iophy_misc_pad_p0_ctl1_0       = 0x70,
2942         .iophy_misc_pad_p1_ctl1_0       = 0x74,
2943         .iophy_misc_pad_p0_ctl2_0       = 0x78,
2944         .iophy_misc_pad_p1_ctl2_0       = 0x7c,
2945         .iophy_misc_pad_p0_ctl3_0       = 0x80,
2946         .iophy_misc_pad_p1_ctl3_0       = 0x84,
2947         .iophy_misc_pad_p0_ctl4_0       = 0x88,
2948         .iophy_misc_pad_p1_ctl4_0       = 0x8c,
2949         .iophy_misc_pad_p0_ctl5_0       = 0x90,
2950         .iophy_misc_pad_p1_ctl5_0       = 0x94,
2951         .iophy_misc_pad_p0_ctl6_0       = 0x98,
2952         .iophy_misc_pad_p1_ctl6_0       = 0x9c,
2953         .usb2_otg_pad0_ctl0_0           = 0xa0,
2954         .usb2_otg_pad1_ctl0_0           = 0xa4,
2955         .usb2_otg_pad2_ctl0_0           = 0xa8,
2956         .usb2_otg_pad0_ctl1_0           = 0xac,
2957         .usb2_otg_pad1_ctl1_0           = 0xb0,
2958         .usb2_otg_pad2_ctl1_0           = 0xb4,
2959         .usb2_bias_pad_ctl0_0           = 0xb8,
2960         .usb2_bias_pad_ctl1_0           = 0xbc,
2961         .usb2_hsic_pad0_ctl0_0          = 0xc0,
2962         .usb2_hsic_pad1_ctl0_0          = 0xc4,
2963         .usb2_hsic_pad0_ctl1_0          = 0xc8,
2964         .usb2_hsic_pad1_ctl1_0          = 0xcc,
2965         .usb2_hsic_pad0_ctl2_0          = 0xd0,
2966         .usb2_hsic_pad1_ctl2_0          = 0xd4,
2967         .ulpi_link_trim_ctl0            = 0xd8,
2968         .ulpi_null_clk_trim_ctl0        = 0xdc,
2969         .hsic_strb_trim_ctl0            = 0xe0,
2970         .wake_ctl0                      = 0xe4,
2971         .pm_spare0                      = 0xe8,
2972         .iophy_misc_pad_p2_ctl1_0       = 0xec,
2973         .iophy_misc_pad_p3_ctl1_0       = 0xf0,
2974         .iophy_misc_pad_p4_ctl1_0       = 0xf4,
2975         .iophy_misc_pad_p2_ctl2_0       = 0xf8,
2976         .iophy_misc_pad_p3_ctl2_0       = 0xfc,
2977         .iophy_misc_pad_p4_ctl2_0       = 0x100,
2978         .iophy_misc_pad_p2_ctl3_0       = 0x104,
2979         .iophy_misc_pad_p3_ctl3_0       = 0x108,
2980         .iophy_misc_pad_p4_ctl3_0       = 0x10c,
2981         .iophy_misc_pad_p2_ctl4_0       = 0x110,
2982         .iophy_misc_pad_p3_ctl4_0       = 0x114,
2983         .iophy_misc_pad_p4_ctl4_0       = 0x118,
2984         .iophy_misc_pad_p2_ctl5_0       = 0x11c,
2985         .iophy_misc_pad_p3_ctl5_0       = 0x120,
2986         .iophy_misc_pad_p4_ctl5_0       = 0x124,
2987         .iophy_misc_pad_p2_ctl6_0       = 0x128,
2988         .iophy_misc_pad_p3_ctl6_0       = 0x12c,
2989         .iophy_misc_pad_p4_ctl6_0       = 0x130,
2990         .usb3_pad_mux_0                 = 0x134,
2991         .iophy_pll_s0_ctl1_0            = 0x138,
2992         .iophy_pll_s0_ctl2_0            = 0x13c,
2993         .iophy_pll_s0_ctl3_0            = 0x140,
2994         .iophy_pll_s0_ctl4_0            = 0x144,
2995         .iophy_misc_pad_s0_ctl1_0       = 0x148,
2996         .iophy_misc_pad_s0_ctl2_0       = 0x14c,
2997         .iophy_misc_pad_s0_ctl3_0       = 0x150,
2998         .iophy_misc_pad_s0_ctl4_0       = 0x154,
2999         .iophy_misc_pad_s0_ctl5_0       = 0x158,
3000         .iophy_misc_pad_s0_ctl6_0       = 0x15c,
3001 };
3002
3003 /* TODO: we have to refine error handling in tegra_xhci_probe() */
3004 static int tegra_xhci_probe(struct platform_device *pdev)
3005 {
3006         const struct hc_driver *driver;
3007         struct xhci_hcd *xhci;
3008         struct tegra_xhci_hcd *tegra;
3009         struct resource *res;
3010         struct usb_hcd  *hcd;
3011         u32 pmc_reg, val;
3012         int ret;
3013         int irq;
3014
3015         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
3016
3017         if (usb_disabled())
3018                 return -ENODEV;
3019
3020         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
3021         if (!tegra) {
3022                 dev_err(&pdev->dev, "memory alloc failed\n");
3023                 return -ENOMEM;
3024         }
3025         tegra->pdev = pdev;
3026         tegra->pdata = dev_get_platdata(&pdev->dev);
3027         tegra->bdata = tegra->pdata->bdata;
3028
3029         ret = tegra_xhci_request_mem_region(pdev, "padctl",
3030                         &tegra->padctl_base);
3031         if (ret) {
3032                 dev_err(&pdev->dev, "failed to map padctl\n");
3033                 return ret;
3034         }
3035
3036         ret = tegra_xhci_request_mem_region(pdev, "fpci", &tegra->fpci_base);
3037         if (ret) {
3038                 dev_err(&pdev->dev, "failed to map fpci\n");
3039                 return ret;
3040         }
3041
3042         ret = tegra_xhci_request_mem_region(pdev, "ipfs", &tegra->ipfs_base);
3043         if (ret) {
3044                 dev_err(&pdev->dev, "failed to map ipfs\n");
3045                 return ret;
3046         }
3047
3048         ret = tegra_xusb_partitions_clk_init(tegra);
3049         if (ret) {
3050                 dev_err(&pdev->dev,
3051                         "failed to initialize xusb partitions clocks\n");
3052                 return ret;
3053         }
3054
3055         /* Enable power rails to the PAD,VBUS
3056          * and pull-up voltage.Initialize the regulators
3057          */
3058         ret = tegra_xusb_regulator_init(tegra, pdev);
3059         if (ret) {
3060                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
3061                 goto err_deinit_xusb_partition_clk;
3062         }
3063
3064         /* Enable UTMIP, PLLU and PLLE */
3065         ret = tegra_usb2_clocks_init(tegra);
3066         if (ret) {
3067                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
3068                 goto err_deinit_tegra_xusb_regulator;
3069         }
3070
3071         /* tegra_unpowergate_partition also does partition reset deassert */
3072         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
3073         if (ret)
3074                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
3075
3076         /* tegra_unpowergate_partition also does partition reset deassert */
3077         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3078         if (ret)
3079                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
3080
3081         /* reset the pointer back to NULL. driver uses it */
3082         /* platform_set_drvdata(pdev, NULL); */
3083
3084         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "host");
3085         if (!res) {
3086                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
3087                 ret = -ENODEV;
3088                 goto err_deinit_usb2_clocks;
3089         }
3090         tegra->host_phy_base = res->start;
3091
3092         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
3093                                 res->start, resource_size(res));
3094         if (!tegra->host_phy_virt_base) {
3095                 dev_err(&pdev->dev, "error mapping host phy memory\n");
3096                 ret = -ENOMEM;
3097                 goto err_deinit_usb2_clocks;
3098         }
3099
3100         /* Setup IPFS access and BAR0 space */
3101         tegra_xhci_cfg(tegra);
3102
3103         val = readl(tegra->fpci_base + XUSB_CFG_0);
3104         tegra->device_id = (val >> 16) & 0xffff;
3105
3106         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
3107                 (XUSB_DEVICE_ID_T114 == tegra->device_id) ? "T114" : "T124+");
3108
3109         if (XUSB_DEVICE_ID_T114 == tegra->device_id) {
3110                 tegra->padregs = &t114_padregs_offset;
3111         } else if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
3112                 tegra->padregs = &t124_padregs_offset;
3113         } else {
3114                 dev_info(&pdev->dev, "XUSB device_id neither T114 nor T124!\n");
3115                 dev_info(&pdev->dev, "XUSB using T124 pad register offsets!\n");
3116                 tegra->padregs = &t124_padregs_offset;
3117         }
3118
3119         /* calculate rctrl_val and tctrl_val once at boot time */
3120         tegra_xhci_war_for_tctrl_rctrl(tegra);
3121
3122         /* Program the XUSB pads to take ownership of ports */
3123         tegra_xhci_padctl_portmap_and_caps(tegra);
3124
3125         /* Release XUSB wake logic state latching */
3126         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
3127         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
3128
3129         /* Deassert reset to XUSB host, ss, dev clocks */
3130         tegra_periph_reset_deassert(tegra->host_clk);
3131         tegra_periph_reset_deassert(tegra->ss_clk);
3132
3133         ret = init_firmware(tegra);
3134         if (ret < 0) {
3135                 dev_err(&pdev->dev, "failed to init firmware\n");
3136                 ret = -ENODEV;
3137                 goto err_deinit_usb2_clocks;
3138         }
3139
3140         ret = load_firmware(tegra, true /* do reset ARU */);
3141         if (ret < 0) {
3142                 dev_err(&pdev->dev, "failed to load firmware\n");
3143                 ret = -ENODEV;
3144                 goto err_deinit_firmware;
3145         }
3146
3147         device_init_wakeup(&pdev->dev, 1);
3148         driver = &tegra_plat_xhci_driver;
3149
3150         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
3151         if (!hcd) {
3152                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
3153                 ret = -ENOMEM;
3154                 goto err_deinit_firmware;
3155         }
3156
3157         ret = tegra_xhci_request_mem_region(pdev, "host", &hcd->regs);
3158         if (ret) {
3159                 dev_err(&pdev->dev, "failed to map host\n");
3160                 goto err_put_usb2_hcd;
3161         }
3162         hcd->rsrc_start = res->start;
3163         hcd->rsrc_len = resource_size(res);
3164
3165         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "host");
3166         if (!res) {
3167                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
3168                 ret = -ENODEV;
3169                 goto err_put_usb2_hcd;
3170         }
3171         irq = res->start;
3172         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
3173         if (ret) {
3174                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
3175                 goto err_put_usb2_hcd;
3176         }
3177
3178         /* USB 2.0 roothub is stored in the platform_device now. */
3179         hcd = dev_get_drvdata(&pdev->dev);
3180         xhci = hcd_to_xhci(hcd);
3181         tegra->xhci = xhci;
3182         platform_set_drvdata(pdev, tegra);
3183
3184         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
3185                                                 dev_name(&pdev->dev), hcd);
3186         if (!xhci->shared_hcd) {
3187                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
3188                 ret = -ENOMEM;
3189                 goto err_remove_usb2_hcd;
3190         }
3191
3192         /*
3193          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
3194          * is called by usb_add_hcd().
3195          */
3196         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
3197
3198         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
3199         if (ret) {
3200                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
3201                 goto err_put_usb3_hcd;
3202         }
3203
3204         device_init_wakeup(&hcd->self.root_hub->dev, 1);
3205         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
3206         spin_lock_init(&tegra->lock);
3207         mutex_init(&tegra->sync_lock);
3208         mutex_init(&tegra->mbox_lock);
3209
3210         /* do mailbox related initializations */
3211         tegra->mbox_owner = 0xffff;
3212         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
3213
3214         tegra_xhci_enable_fw_message(tegra);
3215
3216         /* do ss partition elpg exit related initialization */
3217         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
3218
3219         /* do host partition elpg exit related initialization */
3220         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
3221
3222         /* Register interrupt handler for SMI line to handle mailbox
3223          * interrupt from firmware
3224          */
3225         ret = tegra_xhci_request_irq(pdev, "host-smi", tegra_xhci_smi_irq,
3226                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
3227         if (ret != 0)
3228                 goto err_remove_usb3_hcd;
3229
3230         /* Register interrupt handler for PADCTRL line to
3231          * handle wake on connect irqs interrupt from
3232          * firmware
3233          */
3234         ret = tegra_xhci_request_irq(pdev, "padctl", tegra_xhci_padctl_irq,
3235                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
3236                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
3237         if (ret != 0)
3238                 goto err_remove_usb3_hcd;
3239
3240         ret = tegra_xhci_request_irq(pdev, "usb3", tegra_xhci_xusb_host_irq,
3241                         IRQF_SHARED | IRQF_TRIGGER_HIGH, "xusb_host_irq",
3242                         &tegra->usb3_irq);
3243         if (ret != 0)
3244                 goto err_remove_usb3_hcd;
3245
3246         tegra->ss_pwr_gated = false;
3247         tegra->host_pwr_gated = false;
3248         tegra->hc_in_elpg = false;
3249         tegra->hs_wake_event = false;
3250         tegra->host_resume_req = false;
3251         tegra->lp0_exit = false;
3252         tegra->dfe_ctle_ctx_saved = false;
3253
3254         /* reset wake event to NONE */
3255         pmc_reg = tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0);
3256         pmc_reg |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE);
3257         pmc_reg |= UTMIP_WAKE_VAL(1, WAKE_VAL_NONE);
3258         pmc_reg |= UTMIP_WAKE_VAL(2, WAKE_VAL_NONE);
3259         pmc_reg |= UTMIP_WAKE_VAL(3, WAKE_VAL_NONE);
3260         tegra_usb_pmc_reg_write(PMC_UTMIP_UHSIC_SLEEP_CFG_0, pmc_reg);
3261
3262         tegra_xhci_debug_read_pads(tegra);
3263         utmi_phy_pad_enable();
3264         utmi_phy_iddq_override(false);
3265
3266         tegra_pd_add_device(&pdev->dev);
3267
3268         return 0;
3269
3270 err_remove_usb3_hcd:
3271         usb_remove_hcd(xhci->shared_hcd);
3272 err_put_usb3_hcd:
3273         usb_put_hcd(xhci->shared_hcd);
3274 err_remove_usb2_hcd:
3275         kfree(tegra->xhci);
3276         usb_remove_hcd(hcd);
3277 err_put_usb2_hcd:
3278         usb_put_hcd(hcd);
3279 err_deinit_firmware:
3280         deinit_firmware(tegra);
3281 err_deinit_usb2_clocks:
3282         tegra_usb2_clocks_deinit(tegra);
3283 err_deinit_tegra_xusb_regulator:
3284         tegra_xusb_regulator_deinit(tegra);
3285 err_deinit_xusb_partition_clk:
3286         tegra_xusb_partitions_clk_deinit(tegra);
3287
3288         return ret;
3289 }
3290
3291 static int tegra_xhci_remove(struct platform_device *pdev)
3292 {
3293         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3294         struct xhci_hcd *xhci = NULL;
3295         struct usb_hcd *hcd = NULL;
3296
3297         if (tegra == NULL)
3298                 return -EINVAL;
3299
3300         xhci = tegra->xhci;
3301         hcd = xhci_to_hcd(xhci);
3302
3303         devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
3304         devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
3305         devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
3306         usb_remove_hcd(xhci->shared_hcd);
3307         usb_put_hcd(xhci->shared_hcd);
3308         usb_remove_hcd(hcd);
3309         usb_put_hcd(hcd);
3310         kfree(xhci);
3311
3312         deinit_firmware(tegra);
3313         tegra_xusb_regulator_deinit(tegra);
3314         tegra_usb2_clocks_deinit(tegra);
3315         if (!tegra->hc_in_elpg)
3316                 tegra_xusb_partitions_clk_deinit(tegra);
3317         utmi_phy_pad_disable();
3318         utmi_phy_iddq_override(true);
3319
3320         return 0;
3321 }
3322
3323 static void tegra_xhci_shutdown(struct platform_device *pdev)
3324 {
3325         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3326         struct xhci_hcd *xhci = NULL;
3327         struct usb_hcd *hcd = NULL;
3328
3329         if (tegra == NULL)
3330                 return;
3331
3332         if (tegra->hc_in_elpg) {
3333                 mutex_lock(&tegra->sync_lock);
3334                 tegra_xhci_host_partition_elpg_exit(tegra);
3335                 mutex_unlock(&tegra->sync_lock);
3336         }
3337         xhci = tegra->xhci;
3338         hcd = xhci_to_hcd(xhci);
3339         xhci_shutdown(hcd);
3340 }
3341
3342 static struct platform_driver tegra_xhci_driver = {
3343         .probe  = tegra_xhci_probe,
3344         .remove = tegra_xhci_remove,
3345         .shutdown = tegra_xhci_shutdown,
3346 #ifdef CONFIG_PM
3347         .suspend = tegra_xhci_suspend,
3348         .resume  = tegra_xhci_resume,
3349 #endif
3350         .driver = {
3351                 .name = "tegra-xhci",
3352         },
3353 };
3354 MODULE_ALIAS("platform:tegra-xhci");
3355
3356 int tegra_xhci_register_plat(void)
3357 {
3358         return platform_driver_register(&tegra_xhci_driver);
3359 }
3360
3361 void tegra_xhci_unregister_plat(void)
3362 {
3363         platform_driver_unregister(&tegra_xhci_driver);
3364 }