usb: xhci: tegra: Fix pmc & regulator for dalmore
[linux-3.10.git] / drivers / usb / host / xhci-tegra.c
1 /*
2  * xhci-tegra.c - Nvidia xHCI host controller driver
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/clk.h>
24 #include <linux/ioport.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irq.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/uaccess.h>
30 #include <linux/circ_buf.h>
31 #include <linux/vmalloc.h>
32 #include <linux/debugfs.h>
33 #include <linux/kthread.h>
34 #include <linux/gpio.h>
35 #include <linux/usb/otg.h>
36 #include <linux/clk/tegra.h>
37 #include <linux/tegra-powergate.h>
38 #include <linux/firmware.h>
39 #include <linux/pm_runtime.h>
40 #include <mach/tegra_usb_pad_ctrl.h>
41 #include <mach/tegra_usb_pmc.h>
42 #include <mach/pm_domains.h>
43 #include <mach/mc.h>
44 #include <mach/xusb.h>
45
46 #include "../../../arch/arm/mach-tegra/iomap.h" /* HACK -- remove */
47 #include "xhci-tegra.h"
48 #include "xhci.h"
49
50 /* macros */
51 #define FW_IOCTL_LOG_DEQUEUE_LOW        (4)
52 #define FW_IOCTL_LOG_DEQUEUE_HIGH       (5)
53 #define FW_IOCTL_DATA_SHIFT             (0)
54 #define FW_IOCTL_DATA_MASK              (0x00ffffff)
55 #define FW_IOCTL_TYPE_SHIFT             (24)
56 #define FW_IOCTL_TYPE_MASK              (0xff000000)
57 #define FW_LOG_SIZE                     (sizeof(struct log_entry))
58 #define FW_LOG_COUNT                    (4096)
59 #define FW_LOG_RING_SIZE                (FW_LOG_SIZE * FW_LOG_COUNT)
60 #define FW_LOG_PAYLOAD_SIZE             (27)
61 #define DRIVER                          (0x01)
62 #define CIRC_BUF_SIZE                   (4 * (1 << 20)) /* 4MB */
63 #define FW_LOG_THREAD_RELAX             (msecs_to_jiffies(100))
64
65 /* tegra_xhci_firmware_log.flags bits */
66 #define FW_LOG_CONTEXT_VALID            (0)
67 #define FW_LOG_FILE_OPENED              (1)
68
69 #define PAGE_SELECT_MASK                        0xFFFFFE00
70 #define PAGE_SELECT_SHIFT                       9
71 #define PAGE_OFFSET_MASK                        0x000001FF
72 #define CSB_PAGE_SELECT(_addr)                                          \
73         ({                                                              \
74                 typecheck(u32, _addr);                                  \
75                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
76         })
77 #define CSB_PAGE_OFFSET(_addr)                                          \
78         ({                                                              \
79                 typecheck(u32, _addr);                                  \
80                 (_addr & PAGE_OFFSET_MASK);                             \
81         })
82
83 #define reg_dump(_dev, _base, _reg)                                     \
84         dev_dbg(_dev, "%s: %s @%x = 0x%x\n", __func__, #_reg,           \
85                 _reg, readl(_base + _reg))
86
87 #define PMC_PORTMAP_MASK(map, pad)      (((map) >> 4*(pad)) & 0xF)
88
89 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
90 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
91 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
92
93 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
94
95 /* private data types */
96 /* command requests from the firmware */
97 enum MBOX_CMD_TYPE {
98         MBOX_CMD_MSG_ENABLED = 1,
99         MBOX_CMD_INC_FALC_CLOCK,
100         MBOX_CMD_DEC_FALC_CLOCK,
101         MBOX_CMD_INC_SSPI_CLOCK,
102         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
103         MBOX_CMD_SET_BW,
104         MBOX_CMD_SET_SS_PWR_GATING,
105         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
106         MBOX_CMD_SAVE_DFE_CTLE_CTX,
107         MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
108         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* 11, unused */
109         MBOX_CMD_STAR_HSIC_IDLE,
110         MBOX_CMD_STOP_HSIC_IDLE,
111         MBOX_CMD_DBC_WAKE_STACK, /* unused */
112         MBOX_CMD_HSIC_PRETEND_CONNECT,
113
114         /* needs to be the last cmd */
115         MBOX_CMD_MAX,
116
117         /* resp msg to ack above commands */
118         MBOX_CMD_ACK = 128,
119         MBOX_CMD_NACK
120 };
121
122 struct log_entry {
123         u32 sequence_no;
124         u8 data[FW_LOG_PAYLOAD_SIZE];
125         u8 owner;
126 };
127
128 /* Usb3 Firmware Cfg Table */
129 struct cfgtbl {
130         u32 boot_loadaddr_in_imem;
131         u32 boot_codedfi_offset;
132         u32 boot_codetag;
133         u32 boot_codesize;
134
135         /* Physical memory reserved by Bootloader/BIOS */
136         u32 phys_memaddr;
137         u16 reqphys_memsize;
138         u16 alloc_phys_memsize;
139
140         /* .rodata section */
141         u32 rodata_img_offset;
142         u32 rodata_section_start;
143         u32 rodata_section_end;
144         u32 main_fnaddr;
145
146         u32 fwimg_cksum;
147         u32 fwimg_created_time;
148
149         /* Fields that get filled by linker during linking phase
150          * or initialized in the FW code.
151          */
152         u32 imem_resident_start;
153         u32 imem_resident_end;
154         u32 idirect_start;
155         u32 idirect_end;
156         u32 l2_imem_start;
157         u32 l2_imem_end;
158         u32 version_id;
159         u8 init_ddirect;
160         u8 reserved[3];
161         u32 phys_addr_log_buffer;
162         u32 total_log_entries;
163         u32 dequeue_ptr;
164
165         /*      Below two dummy variables are used to replace
166          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
167          *      retain the size of struct _CFG_TBL used by other AP/Module.
168          */
169         u32 dummy_var1;
170         u32 dummy_var2;
171
172         /* fwimg_len */
173         u32 fwimg_len;
174         u8 magic[8];
175         u32 SS_low_power_entry_timeout;
176         u8 num_hsic_port;
177         u8 padding[139]; /* padding bytes to makeup 256-bytes cfgtbl */
178 };
179
180 struct xusb_save_regs {
181         u32 msi_bar_sz;
182         u32 msi_axi_barst;
183         u32 msi_fpci_barst;
184         u32 msi_vec0;
185         u32 msi_en_vec0;
186         u32 fpci_error_masks;
187         u32 intr_mask;
188         u32 ipfs_intr_enable;
189         u32 ufpci_config;
190         u32 clkgate_hysteresis;
191         u32 xusb_host_mccif_fifo_cntrl;
192
193         /* PG does not mention below */
194         u32 hs_pls;
195         u32 fs_pls;
196         u32 hs_fs_speed;
197         u32 hs_fs_pp;
198         u32 cfg_aru;
199         u32 cfg_order;
200         u32 cfg_fladj;
201         u32 cfg_sid;
202         /* DFE and CTLE */
203         u32 tap1_val[XUSB_SS_PORT_COUNT];
204         u32 amp_val[XUSB_SS_PORT_COUNT];
205         u32 ctle_z_val[XUSB_SS_PORT_COUNT];
206         u32 ctle_g_val[XUSB_SS_PORT_COUNT];
207 };
208
209 struct tegra_xhci_firmware {
210         void *data; /* kernel virtual address */
211         size_t size; /* firmware size */
212         dma_addr_t dma; /* dma address for controller */
213 };
214
215 struct tegra_xhci_firmware_log {
216         dma_addr_t phys_addr;           /* dma-able address */
217         void *virt_addr;                /* kernel va of the shared log buffer */
218         struct log_entry *dequeue;      /* current dequeue pointer (va) */
219         struct circ_buf circ;           /* big circular buffer */
220         u32 seq;                        /* log sequence number */
221
222         struct task_struct *thread;     /* a thread to consume log */
223         struct mutex mutex;
224         wait_queue_head_t read_wait;
225         wait_queue_head_t write_wait;
226         wait_queue_head_t intr_wait;
227         struct dentry *path;
228         struct dentry *log_file;
229         unsigned long flags;
230 };
231
232 /* structure to hold the offsets of padctl registers */
233 struct tegra_xusb_padctl_regs {
234         u16 boot_media_0;
235         u16 usb2_pad_mux_0;
236         u16 usb2_port_cap_0;
237         u16 snps_oc_map_0;
238         u16 usb2_oc_map_0;
239         u16 ss_port_map_0;
240         u16 oc_det_0;
241         u16 elpg_program_0;
242         u16 usb2_bchrg_otgpad0_ctl0_0;
243         u16 usb2_bchrg_otgpad0_ctl1_0;
244         u16 usb2_bchrg_otgpad1_ctl0_0;
245         u16 usb2_bchrg_otgpad1_ctl1_0;
246         u16 usb2_bchrg_otgpad2_ctl0_0;
247         u16 usb2_bchrg_otgpad2_ctl1_0;
248         u16 usb2_bchrg_bias_pad_0;
249         u16 usb2_bchrg_tdcd_dbnc_timer_0;
250         u16 iophy_pll_p0_ctl1_0;
251         u16 iophy_pll_p0_ctl2_0;
252         u16 iophy_pll_p0_ctl3_0;
253         u16 iophy_pll_p0_ctl4_0;
254         u16 iophy_usb3_pad0_ctl1_0;
255         u16 iophy_usb3_pad1_ctl1_0;
256         u16 iophy_usb3_pad0_ctl2_0;
257         u16 iophy_usb3_pad1_ctl2_0;
258         u16 iophy_usb3_pad0_ctl3_0;
259         u16 iophy_usb3_pad1_ctl3_0;
260         u16 iophy_usb3_pad0_ctl4_0;
261         u16 iophy_usb3_pad1_ctl4_0;
262         u16 iophy_misc_pad_p0_ctl1_0;
263         u16 iophy_misc_pad_p1_ctl1_0;
264         u16 iophy_misc_pad_p0_ctl2_0;
265         u16 iophy_misc_pad_p1_ctl2_0;
266         u16 iophy_misc_pad_p0_ctl3_0;
267         u16 iophy_misc_pad_p1_ctl3_0;
268         u16 iophy_misc_pad_p0_ctl4_0;
269         u16 iophy_misc_pad_p1_ctl4_0;
270         u16 iophy_misc_pad_p0_ctl5_0;
271         u16 iophy_misc_pad_p1_ctl5_0;
272         u16 iophy_misc_pad_p0_ctl6_0;
273         u16 iophy_misc_pad_p1_ctl6_0;
274         u16 usb2_otg_pad0_ctl0_0;
275         u16 usb2_otg_pad1_ctl0_0;
276         u16 usb2_otg_pad2_ctl0_0;
277         u16 usb2_otg_pad0_ctl1_0;
278         u16 usb2_otg_pad1_ctl1_0;
279         u16 usb2_otg_pad2_ctl1_0;
280         u16 usb2_bias_pad_ctl0_0;
281         u16 usb2_bias_pad_ctl1_0;
282         u16 usb2_hsic_pad0_ctl0_0;
283         u16 usb2_hsic_pad1_ctl0_0;
284         u16 usb2_hsic_pad0_ctl1_0;
285         u16 usb2_hsic_pad1_ctl1_0;
286         u16 usb2_hsic_pad0_ctl2_0;
287         u16 usb2_hsic_pad1_ctl2_0;
288         u16 ulpi_link_trim_ctl0;
289         u16 ulpi_null_clk_trim_ctl0;
290         u16 hsic_strb_trim_ctl0;
291         u16 wake_ctl0;
292         u16 pm_spare0;
293         u16 iophy_misc_pad_p2_ctl1_0;
294         u16 iophy_misc_pad_p3_ctl1_0;
295         u16 iophy_misc_pad_p4_ctl1_0;
296         u16 iophy_misc_pad_p2_ctl2_0;
297         u16 iophy_misc_pad_p3_ctl2_0;
298         u16 iophy_misc_pad_p4_ctl2_0;
299         u16 iophy_misc_pad_p2_ctl3_0;
300         u16 iophy_misc_pad_p3_ctl3_0;
301         u16 iophy_misc_pad_p4_ctl3_0;
302         u16 iophy_misc_pad_p2_ctl4_0;
303         u16 iophy_misc_pad_p3_ctl4_0;
304         u16 iophy_misc_pad_p4_ctl4_0;
305         u16 iophy_misc_pad_p2_ctl5_0;
306         u16 iophy_misc_pad_p3_ctl5_0;
307         u16 iophy_misc_pad_p4_ctl5_0;
308         u16 iophy_misc_pad_p2_ctl6_0;
309         u16 iophy_misc_pad_p3_ctl6_0;
310         u16 iophy_misc_pad_p4_ctl6_0;
311         u16 usb3_pad_mux_0;
312         u16 iophy_pll_s0_ctl1_0;
313         u16 iophy_pll_s0_ctl2_0;
314         u16 iophy_pll_s0_ctl3_0;
315         u16 iophy_pll_s0_ctl4_0;
316         u16 iophy_misc_pad_s0_ctl1_0;
317         u16 iophy_misc_pad_s0_ctl2_0;
318         u16 iophy_misc_pad_s0_ctl3_0;
319         u16 iophy_misc_pad_s0_ctl4_0;
320         u16 iophy_misc_pad_s0_ctl5_0;
321         u16 iophy_misc_pad_s0_ctl6_0;
322 };
323
324 struct tegra_xhci_hcd {
325         struct platform_device *pdev;
326         struct xhci_hcd *xhci;
327         u16 device_id;
328
329         spinlock_t lock;
330         struct mutex sync_lock;
331
332         int smi_irq;
333         int padctl_irq;
334         int usb3_irq;
335         int usb2_irq;
336
337         bool ss_wake_event;
338         bool ss_pwr_gated;
339         bool host_pwr_gated;
340         bool hs_wake_event;
341         bool host_resume_req;
342         bool lp0_exit;
343         bool dfe_ctx_saved[XUSB_SS_PORT_COUNT];
344         bool ctle_ctx_saved[XUSB_SS_PORT_COUNT];
345         unsigned long last_jiffies;
346         unsigned long host_phy_base;
347         unsigned long host_phy_size;
348         void __iomem *host_phy_virt_base;
349
350         void __iomem *padctl_base;
351         void __iomem *fpci_base;
352         void __iomem *ipfs_base;
353
354         struct tegra_xusb_platform_data *pdata;
355         struct tegra_xusb_board_data *bdata;
356         struct tegra_xusb_padctl_regs *padregs;
357
358         /* mailbox variables */
359         struct mutex mbox_lock;
360         u32 mbox_owner;
361         u32 cmd_type;
362         u32 cmd_data;
363
364         struct regulator *xusb_utmi_vbus_regs[XUSB_UTMI_COUNT];
365
366         struct regulator *xusb_s1p05v_reg;
367         struct regulator *xusb_s3p3v_reg;
368         struct regulator *xusb_s1p8v_reg;
369         struct regulator *vddio_hsic_reg;
370         int vddio_hsic_refcnt;
371
372         struct work_struct mbox_work;
373         struct work_struct ss_elpg_exit_work;
374         struct work_struct host_elpg_exit_work;
375
376         struct clk *host_clk;
377         struct clk *ss_clk;
378
379         /* XUSB Falcon SuperSpeed Clock */
380         struct clk *falc_clk;
381
382         /* EMC Clock */
383         struct clk *emc_clk;
384         /* XUSB SS PI Clock */
385         struct clk *ss_src_clk;
386         /* PLLE Clock */
387         struct clk *plle_clk;
388         struct clk *pll_u_480M;
389         struct clk *clk_m;
390         /* refPLLE clk */
391         struct clk *pll_re_vco_clk;
392         /*
393          * XUSB/IPFS specific registers these need to be saved/restored in
394          * addition to spec defined registers
395          */
396         struct xusb_save_regs sregs;
397         bool usb2_rh_suspend;
398         bool usb3_rh_suspend;
399         bool hc_in_elpg;
400
401         /* otg transceiver */
402         struct usb_phy *transceiver;
403         struct notifier_block otgnb;
404
405         unsigned long usb2_rh_remote_wakeup_ports; /* one bit per port */
406         unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
407         /* firmware loading related */
408         struct tegra_xhci_firmware firmware;
409
410         struct tegra_xhci_firmware_log log;
411
412         bool init_done;
413 };
414
415 static int tegra_xhci_probe2(struct tegra_xhci_hcd *tegra);
416 static int tegra_xhci_remove(struct platform_device *pdev);
417 static void init_filesystem_firmware_done(const struct firmware *fw,
418                                         void *context);
419
420 static struct tegra_usb_pmc_data pmc_data[XUSB_UTMI_COUNT];
421 static struct tegra_usb_pmc_data pmc_hsic_data[XUSB_HSIC_COUNT];
422 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
423         u8 port)  __attribute__ ((unused));
424
425 #ifdef CONFIG_TEGRA_XUSB_USB_BOOTLOADER_FIRMWARE
426 static bool use_bootloader_firmware = true;
427 #else
428 static bool use_bootloader_firmware;
429 #endif
430 module_param(use_bootloader_firmware, bool, S_IRUGO);
431 MODULE_PARM_DESC(use_bootloader_firmware, "take bootloader initialized firmware");
432
433 #define FIRMWARE_FILE CONFIG_TEGRA_XUSB_FIRMWARE_FILE
434 static char *firmware_file = FIRMWARE_FILE;
435 #define FIRMWARE_FILE_HELP      \
436         "used to specify firmware file of Tegra XHCI host controller. "\
437         "This takes effect only if \"use_bootloader_firmware\" is \"N\". " \
438         "Default value is \"" FIRMWARE_FILE "\"."
439
440 module_param(firmware_file, charp, S_IRUGO);
441 MODULE_PARM_DESC(firmware_file, FIRMWARE_FILE_HELP);
442
443 /* functions */
444 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
445 {
446         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
447 }
448
449 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
450 {
451 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
452         WARN_ON(tegra->sync_lock.owner != current);
453 #endif
454 }
455
456 #define for_each_enabled_hsic_pad(_pad, _tegra_xhci_hcd)                \
457         for (_pad = find_next_enabled_hsic_pad(_tegra_xhci_hcd, 0);     \
458             (_pad < XUSB_HSIC_COUNT) && (_pad >= 0);                    \
459             _pad = find_next_enabled_hsic_pad(_tegra_xhci_hcd, _pad + 1))
460
461 static inline int find_next_enabled_pad(struct tegra_xhci_hcd *tegra,
462                                                 int start, int last)
463 {
464         unsigned long portmap = tegra->bdata->portmap;
465         return find_next_bit(&portmap, last , start);
466 }
467
468 static inline int find_next_enabled_hsic_pad(struct tegra_xhci_hcd *tegra,
469                                                 int curr_pad)
470 {
471         int start = XUSB_HSIC_INDEX + curr_pad;
472         int last = XUSB_HSIC_INDEX + XUSB_HSIC_COUNT;
473
474         if ((curr_pad < 0) || (curr_pad >= XUSB_HSIC_COUNT))
475                 return -1;
476
477         return find_next_enabled_pad(tegra, start, last) - XUSB_HSIC_INDEX;
478 }
479
480 static void tegra_xhci_setup_gpio_for_ss_lane(struct tegra_xhci_hcd *tegra)
481 {
482         int err = 0;
483
484         if (!tegra->bdata->gpio_controls_muxed_ss_lanes)
485                 return;
486
487         if (tegra->bdata->lane_owner & BIT(0)) {
488                 /* USB3_SS port1 is using SATA lane so set (MUX_SATA)
489                  * GPIO P11 to '0'
490                  */
491                 err = gpio_request((tegra->bdata->gpio_ss1_sata & 0xffff),
492                         "gpio_ss1_sata");
493                 if (err < 0)
494                         pr_err("%s: gpio_ss1_sata gpio_request failed %d\n",
495                                 __func__, err);
496                 err = gpio_direction_output((tegra->bdata->gpio_ss1_sata
497                         & 0xffff), 1);
498                 if (err < 0)
499                         pr_err("%s: gpio_ss1_sata gpio_direction failed %d\n",
500                                 __func__, err);
501                 __gpio_set_value((tegra->bdata->gpio_ss1_sata & 0xffff),
502                                 ((tegra->bdata->gpio_ss1_sata >> 16)));
503         }
504 }
505
506 static u32 xhci_read_portsc(struct xhci_hcd *xhci, unsigned int port)
507 {
508         int num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
509         __le32 __iomem *addr;
510
511         if (port >= num_ports) {
512                 xhci_err(xhci, "%s invalid port %u\n", __func__, port);
513                 return -1;
514         }
515
516         addr = &xhci->op_regs->port_status_base + (NUM_PORT_REGS * port);
517         return xhci_readl(xhci, addr);
518 }
519
520 static void debug_print_portsc(struct xhci_hcd *xhci)
521 {
522         __le32 __iomem *addr = &xhci->op_regs->port_status_base;
523         u32 reg;
524         int i;
525         int ports;
526
527         ports = HCS_MAX_PORTS(xhci->hcs_params1);
528         for (i = 0; i < ports; i++) {
529                 reg = xhci_read_portsc(xhci, i);
530                 xhci_dbg(xhci, "@%p port %d status reg = 0x%x\n",
531                                 addr, i, (unsigned int) reg);
532                 addr += NUM_PORT_REGS;
533         }
534 }
535 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra);
536
537 static bool is_otg_host(struct tegra_xhci_hcd *tegra)
538 {
539         if (!tegra->transceiver)
540                 return true;
541         else if (tegra->transceiver->state == OTG_STATE_A_HOST)
542                 return true;
543         else
544                 return false;
545 }
546
547 static int update_speed(struct tegra_xhci_hcd *tegra, u8 port)
548 {
549         struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
550         u32 portsc;
551
552         portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port));
553         if (DEV_FULLSPEED(portsc))
554                 return USB_PMC_PORT_SPEED_FULL;
555         else if (DEV_HIGHSPEED(portsc))
556                 return USB_PMC_PORT_SPEED_HIGH;
557         else if (DEV_LOWSPEED(portsc))
558                 return USB_PMC_PORT_SPEED_LOW;
559         else if (DEV_SUPERSPEED(portsc))
560                 return USB_PMC_PORT_SPEED_SUPER;
561         else
562                 return USB_PMC_PORT_SPEED_UNKNOWN;
563 }
564
565 static void pmc_init(struct tegra_xhci_hcd *tegra)
566 {
567         struct tegra_usb_pmc_data *pmc;
568         struct device *dev = &tegra->pdev->dev;
569         int pad;
570
571         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
572                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
573                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
574                         pmc = &pmc_data[pad];
575                         if (tegra->pdata->pmc_portmap)
576                                 pmc->instance = PMC_PORTMAP_MASK(
577                                                 tegra->pdata->pmc_portmap,
578                                                 pad);
579                         else
580                                 pmc->instance = pad;
581                         pmc->phy_type = TEGRA_USB_PHY_INTF_UTMI;
582                         pmc->port_speed = USB_PMC_PORT_SPEED_UNKNOWN;
583                         pmc->controller_type = TEGRA_USB_3_0;
584                         tegra_usb_pmc_init(pmc);
585                 }
586         }
587
588         for_each_enabled_hsic_pad(pad, tegra) {
589                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
590                 pmc = &pmc_hsic_data[pad];
591                 pmc->instance = pad + 1;
592                 pmc->phy_type = TEGRA_USB_PHY_INTF_HSIC;
593                 pmc->port_speed = USB_PMC_PORT_SPEED_HIGH;
594                 pmc->controller_type = TEGRA_USB_3_0;
595                 tegra_usb_pmc_init(pmc);
596         }
597 }
598
599 static void pmc_setup_wake_detect(struct tegra_xhci_hcd *tegra)
600 {
601         struct tegra_usb_pmc_data *pmc;
602         struct device *dev = &tegra->pdev->dev;
603         u32 portsc;
604         int port;
605         int pad;
606
607         for_each_enabled_hsic_pad(pad, tegra) {
608                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
609
610                 pmc = &pmc_hsic_data[pad];
611                 port = hsic_pad_to_port(pad);
612                 portsc = xhci_read_portsc(tegra->xhci, port);
613                 dev_dbg(dev, "%s hsic pad %d portsc 0x%x\n",
614                         __func__, pad, portsc);
615
616                 if (((int) portsc != -1) && (portsc & PORT_CONNECT))
617                         pmc->pmc_ops->setup_pmc_wake_detect(pmc);
618         }
619
620         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
621                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
622                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
623                         pmc = &pmc_data[pad];
624                         pmc->port_speed = update_speed(tegra, pad);
625                         if (pad == 0) {
626                                 if (is_otg_host(tegra))
627                                         pmc->pmc_ops->setup_pmc_wake_detect(
628                                                                         pmc);
629                         } else
630                                 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
631                 }
632         }
633 }
634
635 static void pmc_disable_bus_ctrl(struct tegra_xhci_hcd *tegra)
636 {
637         struct tegra_usb_pmc_data *pmc;
638         struct device *dev = &tegra->pdev->dev;
639         int pad;
640
641         for_each_enabled_hsic_pad(pad, tegra) {
642                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
643
644                 pmc = &pmc_hsic_data[pad];
645                 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
646         }
647
648         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
649                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
650                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
651                         pmc = &pmc_data[pad];
652                         pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
653                 }
654         }
655 }
656
657 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
658 {
659         void __iomem *fpci_base = tegra->fpci_base;
660         struct platform_device *pdev = tegra->pdev;
661         u32 input_addr;
662         u32 data;
663         u32 csb_page_select;
664
665         /* to select the appropriate CSB page to write to */
666         csb_page_select = CSB_PAGE_SELECT(addr);
667
668         dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
669                         csb_page_select);
670
671         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
672
673         /* selects the appropriate offset in the page to read from */
674         input_addr = CSB_PAGE_OFFSET(addr);
675         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
676
677         dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
678                         input_addr, data);
679         return data;
680 }
681
682 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
683 {
684         void __iomem *fpci_base = tegra->fpci_base;
685         struct platform_device *pdev = tegra->pdev;
686         u32 input_addr;
687         u32 csb_page_select;
688
689         /* to select the appropriate CSB page to write to */
690         csb_page_select = CSB_PAGE_SELECT(addr);
691
692         dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
693                         csb_page_select);
694
695         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
696
697         /* selects the appropriate offset in the page to write to */
698         input_addr = CSB_PAGE_OFFSET(addr);
699         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
700
701         dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
702                         input_addr, data);
703 }
704
705 static int fw_message_send(struct tegra_xhci_hcd *tegra,
706         enum MBOX_CMD_TYPE type, u32 data)
707 {
708         struct device *dev = &tegra->pdev->dev;
709         void __iomem *base = tegra->fpci_base;
710         unsigned long target;
711         u32 reg;
712
713         dev_dbg(dev, "%s type %d data 0x%x\n", __func__, type, data);
714
715         mutex_lock(&tegra->mbox_lock);
716
717         target = jiffies + msecs_to_jiffies(20);
718         /* wait mailbox to become idle, timeout in 20ms */
719         while (((reg = readl(base + XUSB_CFG_ARU_MBOX_OWNER)) != 0) &&
720                 time_is_after_jiffies(target)) {
721                 mutex_unlock(&tegra->mbox_lock);
722                 usleep_range(100, 200);
723                 mutex_lock(&tegra->mbox_lock);
724         }
725
726         if (reg != 0) {
727                 dev_err(dev, "%s mailbox is still busy\n", __func__);
728                 goto timeout;
729         }
730
731         target = jiffies + msecs_to_jiffies(10);
732         /* acquire mailbox , timeout in 10ms */
733         writel(MBOX_OWNER_SW, base + XUSB_CFG_ARU_MBOX_OWNER);
734         while (((reg = readl(base + XUSB_CFG_ARU_MBOX_OWNER)) != MBOX_OWNER_SW)
735                 && time_is_after_jiffies(target)) {
736                 mutex_unlock(&tegra->mbox_lock);
737                 usleep_range(100, 200);
738                 mutex_lock(&tegra->mbox_lock);
739                 writel(MBOX_OWNER_SW, base + XUSB_CFG_ARU_MBOX_OWNER);
740         }
741
742         if (reg != MBOX_OWNER_SW) {
743                 dev_err(dev, "%s acquire mailbox timeout\n", __func__);
744                 goto timeout;
745         }
746
747         reg = CMD_TYPE(type) | CMD_DATA(data);
748         writel(reg, base + XUSB_CFG_ARU_MBOX_DATA_IN);
749
750         reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
751         reg |= MBOX_INT_EN | MBOX_FALC_INT_EN;
752         writel(reg, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
753
754         mutex_unlock(&tegra->mbox_lock);
755         return 0;
756
757 timeout:
758         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_CMD);
759         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_DATA_IN);
760         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_DATA_OUT);
761         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_OWNER);
762         mutex_unlock(&tegra->mbox_lock);
763         return -ETIMEDOUT;
764 }
765
766 /**
767  * fw_log_next - find next log entry in a tegra_xhci_firmware_log context.
768  *      This function takes care of wrapping. That means when current log entry
769  *      is the last one, it returns with the first one.
770  *
771  * @param log   The tegra_xhci_firmware_log context.
772  * @param this  The current log entry.
773  * @return      The log entry which is next to the current one.
774  */
775 static inline struct log_entry *fw_log_next(
776                 struct tegra_xhci_firmware_log *log, struct log_entry *this)
777 {
778         struct log_entry *first = (struct log_entry *) log->virt_addr;
779         struct log_entry *last = first + FW_LOG_COUNT - 1;
780
781         WARN((this < first) || (this > last), "%s: invalid input\n", __func__);
782
783         return (this == last) ? first : (this + 1);
784 }
785
786 /**
787  * fw_log_update_dequeue_pointer - update dequeue pointer to both firmware and
788  *      tegra_xhci_firmware_log.dequeue.
789  *
790  * @param log   The tegra_xhci_firmware_log context.
791  * @param n     Counts of log entries to fast-forward.
792  */
793 static inline void fw_log_update_deq_pointer(
794                 struct tegra_xhci_firmware_log *log, int n)
795 {
796         struct tegra_xhci_hcd *tegra =
797                         container_of(log, struct tegra_xhci_hcd, log);
798         struct device *dev = &tegra->pdev->dev;
799         struct log_entry *deq = tegra->log.dequeue;
800         dma_addr_t physical_addr;
801         u32 reg;
802
803         dev_dbg(dev, "curr 0x%p fast-forward %d entries\n", deq, n);
804         while (n-- > 0)
805                 deq = fw_log_next(log, deq);
806
807         tegra->log.dequeue = deq;
808         physical_addr = tegra->log.phys_addr +
809                         ((u8 *)deq - (u8 *)tegra->log.virt_addr);
810
811         /* update dequeue pointer to firmware */
812         reg = (FW_IOCTL_LOG_DEQUEUE_LOW << FW_IOCTL_TYPE_SHIFT);
813         reg |= (physical_addr & 0xffff); /* lower 16-bits */
814         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
815
816         reg = (FW_IOCTL_LOG_DEQUEUE_HIGH << FW_IOCTL_TYPE_SHIFT);
817         reg |= ((physical_addr >> 16) & 0xffff); /* higher 16-bits */
818         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
819
820         dev_dbg(dev, "new 0x%p physical addr 0x%x\n", deq, physical_addr);
821 }
822
823 static inline bool circ_buffer_full(struct circ_buf *circ)
824 {
825         int space = CIRC_SPACE(circ->head, circ->tail, CIRC_BUF_SIZE);
826
827         return (space <= FW_LOG_SIZE);
828 }
829
830 static inline bool fw_log_available(struct tegra_xhci_hcd *tegra)
831 {
832         return (tegra->log.dequeue->owner == DRIVER);
833 }
834
835 /**
836  * fw_log_wait_empty_timeout - wait firmware log thread to clean up shared
837  *      log buffer.
838  * @param tegra:        tegra_xhci_hcd context
839  * @param msec:         timeout value in millisecond
840  * @return true:        shared log buffer is empty,
841  *         false:       shared log buffer isn't empty.
842  */
843 static inline bool fw_log_wait_empty_timeout(struct tegra_xhci_hcd *tegra,
844                 unsigned timeout)
845 {
846         unsigned long target = jiffies + msecs_to_jiffies(timeout);
847         bool ret;
848
849         mutex_lock(&tegra->log.mutex);
850
851         while (fw_log_available(tegra) && time_is_after_jiffies(target)) {
852                 mutex_unlock(&tegra->log.mutex);
853                 usleep_range(1000, 2000);
854                 mutex_lock(&tegra->log.mutex);
855         }
856
857         ret = fw_log_available(tegra);
858         mutex_unlock(&tegra->log.mutex);
859
860         return ret;
861 }
862
863 /**
864  * fw_log_copy - copy firmware log from device's buffer to driver's circular
865  *      buffer.
866  * @param tegra tegra_xhci_hcd context
867  * @return true,        We still have firmware log in device's buffer to copy.
868  *                      This function returned due the driver's circular buffer
869  *                      is full. Caller should invoke this function again as
870  *                      soon as there is space in driver's circular buffer.
871  *         false,       Device's buffer is empty.
872  */
873 static inline bool fw_log_copy(struct tegra_xhci_hcd *tegra)
874 {
875         struct device *dev = &tegra->pdev->dev;
876         struct circ_buf *circ = &tegra->log.circ;
877         int head, tail;
878         int buffer_len, copy_len;
879         struct log_entry *entry;
880         struct log_entry *first = tegra->log.virt_addr;
881
882         while (fw_log_available(tegra)) {
883
884                 /* calculate maximum contiguous driver buffer length */
885                 head = circ->head;
886                 tail = ACCESS_ONCE(circ->tail);
887                 buffer_len = CIRC_SPACE_TO_END(head, tail, CIRC_BUF_SIZE);
888                 /* round down to FW_LOG_SIZE */
889                 buffer_len -= (buffer_len % FW_LOG_SIZE);
890                 if (!buffer_len)
891                         return true; /* log available but no space left */
892
893                 /* calculate maximum contiguous log copy length */
894                 entry = tegra->log.dequeue;
895                 copy_len = 0;
896                 do {
897                         if (tegra->log.seq != entry->sequence_no) {
898                                 dev_warn(dev,
899                                 "%s: discontinuous seq no, expect %u get %u\n",
900                                 __func__, tegra->log.seq, entry->sequence_no);
901                         }
902                         tegra->log.seq = entry->sequence_no + 1;
903
904                         copy_len += FW_LOG_SIZE;
905                         buffer_len -= FW_LOG_SIZE;
906                         if (!buffer_len)
907                                 break; /* no space left */
908                         entry = fw_log_next(&tegra->log, entry);
909                 } while ((entry->owner == DRIVER) && (entry != first));
910
911                 memcpy(&circ->buf[head], tegra->log.dequeue, copy_len);
912                 memset(tegra->log.dequeue, 0, copy_len);
913                 circ->head = (circ->head + copy_len) & (CIRC_BUF_SIZE - 1);
914
915                 mb();
916
917                 fw_log_update_deq_pointer(&tegra->log, copy_len/FW_LOG_SIZE);
918
919                 dev_dbg(dev, "copied %d entries, new dequeue 0x%p\n",
920                                 copy_len/FW_LOG_SIZE, tegra->log.dequeue);
921                 wake_up_interruptible(&tegra->log.read_wait);
922         }
923
924         return false;
925 }
926
927 static int fw_log_thread(void *data)
928 {
929         struct tegra_xhci_hcd *tegra = data;
930         struct device *dev = &tegra->pdev->dev;
931         struct circ_buf *circ = &tegra->log.circ;
932         bool logs_left;
933
934         dev_dbg(dev, "start firmware log thread\n");
935
936         do {
937                 mutex_lock(&tegra->log.mutex);
938                 if (circ_buffer_full(circ)) {
939                         mutex_unlock(&tegra->log.mutex);
940                         dev_info(dev, "%s: circ buffer full\n", __func__);
941                         wait_event_interruptible(tegra->log.write_wait,
942                             kthread_should_stop() || !circ_buffer_full(circ));
943                         mutex_lock(&tegra->log.mutex);
944                 }
945
946                 logs_left = fw_log_copy(tegra);
947                 mutex_unlock(&tegra->log.mutex);
948
949                 /* relax if no logs left  */
950                 if (!logs_left)
951                         wait_event_interruptible_timeout(tegra->log.intr_wait,
952                                 fw_log_available(tegra), FW_LOG_THREAD_RELAX);
953         } while (!kthread_should_stop());
954
955         dev_dbg(dev, "stop firmware log thread\n");
956         return 0;
957 }
958
959 static inline bool circ_buffer_empty(struct circ_buf *circ)
960 {
961         return (CIRC_CNT(circ->head, circ->tail, CIRC_BUF_SIZE) == 0);
962 }
963
964 static ssize_t fw_log_file_read(struct file *file, char __user *buf,
965                 size_t count, loff_t *offp)
966 {
967         struct tegra_xhci_hcd *tegra = file->private_data;
968         struct platform_device *pdev = tegra->pdev;
969         struct circ_buf *circ = &tegra->log.circ;
970         int head, tail;
971         size_t n = 0;
972         int s;
973
974         mutex_lock(&tegra->log.mutex);
975
976         while (circ_buffer_empty(circ)) {
977                 mutex_unlock(&tegra->log.mutex);
978                 if (file->f_flags & O_NONBLOCK)
979                         return -EAGAIN; /* non-blocking read */
980
981                 dev_dbg(&pdev->dev, "%s: nothing to read\n", __func__);
982
983                 if (wait_event_interruptible(tegra->log.read_wait,
984                                 !circ_buffer_empty(circ)))
985                         return -ERESTARTSYS;
986
987                 if (mutex_lock_interruptible(&tegra->log.mutex))
988                         return -ERESTARTSYS;
989         }
990
991         while (count > 0) {
992                 head = ACCESS_ONCE(circ->head);
993                 tail = circ->tail;
994                 s = min_t(int, count,
995                                 CIRC_CNT_TO_END(head, tail, CIRC_BUF_SIZE));
996
997                 if (s > 0) {
998                         if (copy_to_user(&buf[n], &circ->buf[tail], s)) {
999                                 dev_warn(&pdev->dev, "copy_to_user failed\n");
1000                                 mutex_unlock(&tegra->log.mutex);
1001                                 return -EFAULT;
1002                         }
1003                         circ->tail = (circ->tail + s) & (CIRC_BUF_SIZE - 1);
1004
1005                         count -= s;
1006                         n += s;
1007                 } else
1008                         break;
1009         }
1010
1011         mutex_unlock(&tegra->log.mutex);
1012
1013         wake_up_interruptible(&tegra->log.write_wait);
1014
1015         dev_dbg(&pdev->dev, "%s: %d bytes\n", __func__, n);
1016
1017         return n;
1018 }
1019
1020 static int fw_log_file_open(struct inode *inode, struct file *file)
1021 {
1022         struct tegra_xhci_hcd *tegra;
1023         file->private_data = inode->i_private;
1024         tegra = file->private_data;
1025
1026         if (test_and_set_bit(FW_LOG_FILE_OPENED, &tegra->log.flags)) {
1027                 dev_info(&tegra->pdev->dev, "%s: already opened\n", __func__);
1028                 return -EBUSY;
1029         }
1030
1031         return 0;
1032 }
1033
1034 static int fw_log_file_close(struct inode *inode, struct file *file)
1035 {
1036         struct tegra_xhci_hcd *tegra = file->private_data;
1037
1038         clear_bit(FW_LOG_FILE_OPENED, &tegra->log.flags);
1039
1040         return 0;
1041 }
1042
1043 static const struct file_operations firmware_log_fops = {
1044                 .open           = fw_log_file_open,
1045                 .release        = fw_log_file_close,
1046                 .read           = fw_log_file_read,
1047                 .owner          = THIS_MODULE,
1048 };
1049
1050 static int fw_log_init(struct tegra_xhci_hcd *tegra)
1051 {
1052         struct platform_device *pdev = tegra->pdev;
1053         int rc = 0;
1054
1055         /* allocate buffer to be shared between driver and firmware */
1056         tegra->log.virt_addr = dma_alloc_writecombine(&pdev->dev,
1057                         FW_LOG_RING_SIZE, &tegra->log.phys_addr, GFP_KERNEL);
1058
1059         if (!tegra->log.virt_addr) {
1060                 dev_err(&pdev->dev, "dma_alloc_writecombine() size %d failed\n",
1061                                 FW_LOG_RING_SIZE);
1062                 return -ENOMEM;
1063         }
1064
1065         dev_info(&pdev->dev, "%d bytes log buffer physical 0x%u virtual 0x%p\n",
1066                 FW_LOG_RING_SIZE, tegra->log.phys_addr, tegra->log.virt_addr);
1067
1068         memset(tegra->log.virt_addr, 0, FW_LOG_RING_SIZE);
1069         tegra->log.dequeue = tegra->log.virt_addr;
1070
1071         tegra->log.circ.buf = vmalloc(CIRC_BUF_SIZE);
1072         if (!tegra->log.circ.buf) {
1073                 dev_err(&pdev->dev, "vmalloc size %d failed\n", CIRC_BUF_SIZE);
1074                 rc = -ENOMEM;
1075                 goto error_free_dma;
1076         }
1077
1078         tegra->log.circ.head = 0;
1079         tegra->log.circ.tail = 0;
1080
1081         init_waitqueue_head(&tegra->log.read_wait);
1082         init_waitqueue_head(&tegra->log.write_wait);
1083         init_waitqueue_head(&tegra->log.intr_wait);
1084
1085         mutex_init(&tegra->log.mutex);
1086
1087         tegra->log.path = debugfs_create_dir("tegra_xhci", NULL);
1088         if (IS_ERR_OR_NULL(tegra->log.path)) {
1089                 dev_warn(&pdev->dev, "debugfs_create_dir() failed\n");
1090                 rc = -ENOMEM;
1091                 goto error_free_mem;
1092         }
1093
1094         tegra->log.log_file = debugfs_create_file("firmware_log",
1095                         S_IRUGO, tegra->log.path, tegra, &firmware_log_fops);
1096         if ((!tegra->log.log_file) ||
1097                         (tegra->log.log_file == ERR_PTR(-ENODEV))) {
1098                 dev_warn(&pdev->dev, "debugfs_create_file() failed\n");
1099                 rc = -ENOMEM;
1100                 goto error_remove_debugfs_path;
1101         }
1102
1103         tegra->log.thread = kthread_run(fw_log_thread, tegra, "xusb-fw-log");
1104         if (IS_ERR(tegra->log.thread)) {
1105                 dev_warn(&pdev->dev, "kthread_run() failed\n");
1106                 rc = -ENOMEM;
1107                 goto error_remove_debugfs_file;
1108         }
1109
1110         set_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags);
1111         return rc;
1112
1113 error_remove_debugfs_file:
1114         debugfs_remove(tegra->log.log_file);
1115 error_remove_debugfs_path:
1116         debugfs_remove(tegra->log.path);
1117 error_free_mem:
1118         vfree(tegra->log.circ.buf);
1119 error_free_dma:
1120         dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1121                         tegra->log.virt_addr, tegra->log.phys_addr);
1122         memset(&tegra->log, sizeof(tegra->log), 0);
1123         return rc;
1124 }
1125
1126 static void fw_log_deinit(struct tegra_xhci_hcd *tegra)
1127 {
1128         struct platform_device *pdev = tegra->pdev;
1129
1130         if (test_and_clear_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
1131
1132                 debugfs_remove(tegra->log.log_file);
1133                 debugfs_remove(tegra->log.path);
1134
1135                 wake_up_interruptible(&tegra->log.read_wait);
1136                 wake_up_interruptible(&tegra->log.write_wait);
1137                 kthread_stop(tegra->log.thread);
1138
1139                 mutex_lock(&tegra->log.mutex);
1140                 dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1141                         tegra->log.virt_addr, tegra->log.phys_addr);
1142                 vfree(tegra->log.circ.buf);
1143                 tegra->log.circ.head = tegra->log.circ.tail = 0;
1144                 mutex_unlock(&tegra->log.mutex);
1145
1146                 mutex_destroy(&tegra->log.mutex);
1147         }
1148 }
1149
1150 /* hsic pad operations */
1151 /*
1152  * HSIC pads need VDDIO_HSIC power rail turned on to be functional. There is
1153  * only one VDDIO_HSIC power rail shared by all HSIC pads.
1154  */
1155 static int hsic_power_rail_enable(struct tegra_xhci_hcd *tegra)
1156 {
1157         struct device *dev = &tegra->pdev->dev;
1158         struct tegra_xusb_regulator_name *supply = &tegra->pdata->bdata->supply;
1159         int ret;
1160
1161         if (tegra->vddio_hsic_reg)
1162                 goto done;
1163
1164         tegra->vddio_hsic_reg = devm_regulator_get(dev, supply->vddio_hsic);
1165         if (IS_ERR_OR_NULL(tegra->vddio_hsic_reg)) {
1166                 dev_err(dev, "%s get vddio_hsic failed\n", __func__);
1167                 ret = PTR_ERR(tegra->vddio_hsic_reg);
1168                 goto get_failed;
1169         }
1170
1171         dev_dbg(dev, "%s regulator_enable vddio_hsic\n", __func__);
1172         ret = regulator_enable(tegra->vddio_hsic_reg);
1173         if (ret < 0) {
1174                 dev_err(dev, "%s enable vddio_hsic failed\n", __func__);
1175                 goto enable_failed;
1176         }
1177
1178 done:
1179         tegra->vddio_hsic_refcnt++;
1180         WARN(tegra->vddio_hsic_refcnt > XUSB_HSIC_COUNT,
1181                         "vddio_hsic_refcnt exceeds\n");
1182         return 0;
1183
1184 enable_failed:
1185         devm_regulator_put(tegra->vddio_hsic_reg);
1186 get_failed:
1187         tegra->vddio_hsic_reg = NULL;
1188         return ret;
1189 }
1190
1191 static int hsic_power_rail_disable(struct tegra_xhci_hcd *tegra)
1192 {
1193         struct device *dev = &tegra->pdev->dev;
1194         int ret;
1195
1196         WARN_ON(!tegra->vddio_hsic_reg || !tegra->vddio_hsic_refcnt);
1197
1198         tegra->vddio_hsic_refcnt--;
1199         if (tegra->vddio_hsic_refcnt)
1200                 return 0;
1201
1202         dev_dbg(dev, "%s regulator_disable vddio_hsic\n", __func__);
1203         ret = regulator_disable(tegra->vddio_hsic_reg);
1204         if (ret < 0) {
1205                 dev_err(dev, "%s disable vddio_hsic failed\n", __func__);
1206                 tegra->vddio_hsic_refcnt++;
1207                 return ret;
1208         }
1209
1210         devm_regulator_put(tegra->vddio_hsic_reg);
1211         tegra->vddio_hsic_reg = NULL;
1212
1213         return 0;
1214 }
1215
1216 static int hsic_pad_enable(struct tegra_xhci_hcd *tegra, unsigned pad)
1217 {
1218         struct device *dev = &tegra->pdev->dev;
1219         void __iomem *base = tegra->padctl_base;
1220         struct tegra_xusb_hsic_config *hsic = &tegra->bdata->hsic[pad];
1221         u32 reg;
1222
1223         if (pad >= XUSB_HSIC_COUNT) {
1224                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1225                 return -EINVAL;
1226         }
1227
1228         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1229
1230         reg = readl(base + HSIC_PAD_CTL_2(pad));
1231         reg &= ~(RX_STROBE_TRIM(~0) | RX_DATA_TRIM(~0));
1232         reg |= RX_STROBE_TRIM(hsic->rx_strobe_trim);
1233         reg |= RX_DATA_TRIM(hsic->rx_data_trim);
1234         writel(reg, base + HSIC_PAD_CTL_2(pad));
1235
1236         reg = readl(base + HSIC_PAD_CTL_0(pad));
1237         reg &= ~(TX_RTUNEP(~0) | TX_RTUNEN(~0) | TX_SLEWP(~0) | TX_SLEWN(~0));
1238         reg |= TX_RTUNEP(hsic->tx_rtune_p);
1239         reg |= TX_RTUNEN(hsic->tx_rtune_n);
1240         reg |= TX_SLEWP(hsic->tx_slew_p);
1241         reg |= TX_SLEWN(hsic->tx_slew_n);
1242         writel(reg, base + HSIC_PAD_CTL_0(pad));
1243
1244         reg = readl(base + HSIC_PAD_CTL_1(pad));
1245         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1246         reg |= (RPD_DATA | RPU_STROBE); /* keep HSIC in IDLE */
1247         if (hsic->auto_term_en)
1248                 reg |= AUTO_TERM_EN;
1249         else
1250                 reg &= ~AUTO_TERM_EN;
1251         reg &= ~(PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1252         writel(reg, base + HSIC_PAD_CTL_1(pad));
1253
1254         reg = readl(base + HSIC_STRB_TRIM_CONTROL);
1255         reg &= ~(STRB_TRIM_VAL(~0));
1256         reg |= STRB_TRIM_VAL(hsic->strb_trim_val);
1257         writel(reg, base + HSIC_STRB_TRIM_CONTROL);
1258
1259         reg = readl(base + USB2_PAD_MUX);
1260         reg |= USB2_HSIC_PAD_PORT(pad);
1261         writel(reg, base + USB2_PAD_MUX);
1262
1263         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1264         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1265         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1266         reg_dump(dev, base, HSIC_STRB_TRIM_CONTROL);
1267         reg_dump(dev, base, USB2_PAD_MUX);
1268         return 0;
1269 }
1270
1271 static void hsic_pad_pretend_connect(struct tegra_xhci_hcd *tegra)
1272 {
1273         struct device *dev = &tegra->pdev->dev;
1274         struct tegra_xusb_hsic_config *hsic;
1275         struct usb_device *hs_root_hub = tegra->xhci->main_hcd->self.root_hub;
1276         int pad;
1277         u32 portsc;
1278         int port;
1279         int enabled_pads = 0;
1280         unsigned long wait_ports = 0;
1281         unsigned long target;
1282
1283         for_each_enabled_hsic_pad(pad, tegra) {
1284                 hsic = &tegra->bdata->hsic[pad];
1285                 if (hsic->pretend_connect)
1286                         enabled_pads++;
1287         }
1288
1289         if (enabled_pads == 0) {
1290                 dev_dbg(dev, "%s no hsic pretend_connect enabled\n", __func__);
1291                 return;
1292         }
1293
1294         usb_disable_autosuspend(hs_root_hub);
1295
1296         for_each_enabled_hsic_pad(pad, tegra) {
1297                 hsic = &tegra->bdata->hsic[pad];
1298                 if (!hsic->pretend_connect)
1299                         continue;
1300
1301                 port = hsic_pad_to_port(pad);
1302                 portsc = xhci_read_portsc(tegra->xhci, port);
1303                 dev_dbg(dev, "%s pad %u portsc 0x%x\n", __func__, pad, portsc);
1304
1305                 if (!(portsc & PORT_CONNECT)) {
1306                         /* firmware wants 1-based port index */
1307                         fw_message_send(tegra,
1308                                 MBOX_CMD_HSIC_PRETEND_CONNECT, BIT(port + 1));
1309                 }
1310
1311                 set_bit(port, &wait_ports);
1312         }
1313
1314         /* wait till port reaches U0 */
1315         target = jiffies + msecs_to_jiffies(500);
1316         do {
1317                 for_each_set_bit(port, &wait_ports, BITS_PER_LONG) {
1318                         portsc = xhci_read_portsc(tegra->xhci, port);
1319                         pad = port_to_hsic_pad(port);
1320                         dev_dbg(dev, "%s pad %u portsc 0x%x\n", __func__,
1321                                 pad, portsc);
1322                         if ((PORT_PLS_MASK & portsc) == XDEV_U0)
1323                                 clear_bit(port, &wait_ports);
1324                 }
1325
1326                 if (wait_ports)
1327                         usleep_range(1000, 5000);
1328         } while (wait_ports && time_is_after_jiffies(target));
1329
1330         if (wait_ports)
1331                 dev_warn(dev, "%s HSIC pad(s) didn't reach U0.\n", __func__);
1332
1333         usb_enable_autosuspend(hs_root_hub);
1334
1335         return;
1336 }
1337
1338 static int hsic_pad_disable(struct tegra_xhci_hcd *tegra, unsigned pad)
1339 {
1340         struct device *dev = &tegra->pdev->dev;
1341         void __iomem *base = tegra->padctl_base;
1342         u32 reg;
1343
1344         if (pad >= XUSB_HSIC_COUNT) {
1345                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1346                 return -EINVAL;
1347         }
1348
1349         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1350
1351         reg = readl(base + USB2_PAD_MUX);
1352         reg &= ~USB2_HSIC_PAD_PORT(pad);
1353         writel(reg, base + USB2_PAD_MUX);
1354
1355         reg = readl(base + HSIC_PAD_CTL_1(pad));
1356         reg |= (PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1357         writel(reg, base + HSIC_PAD_CTL_1(pad));
1358
1359         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1360         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1361         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1362         reg_dump(dev, base, USB2_PAD_MUX);
1363         return 0;
1364 }
1365
1366 enum hsic_pad_pupd {
1367         PUPD_DISABLE = 0,
1368         PUPD_IDLE,
1369         PUPD_RESET
1370 };
1371
1372 static int hsic_pad_pupd_set(struct tegra_xhci_hcd *tegra, unsigned pad,
1373         enum hsic_pad_pupd pupd)
1374 {
1375         struct device *dev = &tegra->pdev->dev;
1376         void __iomem *base = tegra->padctl_base;
1377         u32 reg;
1378
1379         if (pad >= XUSB_HSIC_COUNT) {
1380                 dev_err(dev, "%s invalid HSIC pad number %u\n", __func__, pad);
1381                 return -EINVAL;
1382         }
1383
1384         dev_dbg(dev, "%s pad %u pupd %d\n", __func__, pad, pupd);
1385
1386         reg = readl(base + HSIC_PAD_CTL_1(pad));
1387         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1388
1389         if (pupd == PUPD_IDLE)
1390                 reg |= (RPD_DATA | RPU_STROBE);
1391         else if (pupd == PUPD_RESET)
1392                 reg |= (RPD_DATA | RPD_STROBE);
1393         else if (pupd != PUPD_DISABLE) {
1394                 dev_err(dev, "%s invalid pupd %d\n", __func__, pupd);
1395                 return -EINVAL;
1396         }
1397
1398         writel(reg, base + HSIC_PAD_CTL_1(pad));
1399
1400         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1401
1402         return 0;
1403 }
1404
1405
1406 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
1407 {
1408         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1409         struct xhci_hcd *xhci = tegra->xhci;
1410         u32 reg;
1411
1412         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
1413         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1414         xhci_info(xhci, " PAD MUX = %x\n", reg);
1415         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1416         xhci_info(xhci, " PORT CAP = %x\n", reg);
1417         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1418         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
1419         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1420         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
1421         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1422         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
1423         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1424         xhci_info(xhci, " OC DET 0= %x\n", reg);
1425         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad0_ctl2_0);
1426         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
1427         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad1_ctl2_0);
1428         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
1429         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl0_0);
1430         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
1431         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl0_0);
1432         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
1433         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl1_0);
1434         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
1435         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl1_0);
1436         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
1437         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1438         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
1439         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad0_ctl0_0);
1440         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
1441         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad1_ctl0_0);
1442         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
1443         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
1444 }
1445
1446 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
1447 {
1448         u32 reg;
1449
1450         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1451         reg |= IPFS_EN_FPCI;
1452         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1453         udelay(10);
1454
1455         /* Program Bar0 Space */
1456         reg = readl(tegra->fpci_base + XUSB_CFG_4);
1457         reg |= tegra->host_phy_base;
1458         writel(reg, tegra->fpci_base + XUSB_CFG_4);
1459         usleep_range(100, 200);
1460
1461         /* Enable Bus Master */
1462         reg = readl(tegra->fpci_base + XUSB_CFG_1);
1463         reg |= 0x7;
1464         writel(reg, tegra->fpci_base + XUSB_CFG_1);
1465
1466         /* Set intr mask to enable intr assertion */
1467         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1468         reg |= IPFS_IP_INT_MASK;
1469         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1470
1471         /* Set hysteris to 0x80 */
1472         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1473 }
1474
1475 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
1476                 struct platform_device *pdev)
1477 {
1478         struct tegra_xusb_regulator_name *supply = &tegra->bdata->supply;
1479         int i;
1480         int err = 0;
1481
1482         tegra->xusb_s3p3v_reg =
1483                         devm_regulator_get(&pdev->dev, supply->s3p3v);
1484         if (IS_ERR(tegra->xusb_s3p3v_reg)) {
1485                 dev_err(&pdev->dev, "3p3v: regulator not found: %ld."
1486                         , PTR_ERR(tegra->xusb_s3p3v_reg));
1487                 err = PTR_ERR(tegra->xusb_s3p3v_reg);
1488                 goto err_null_regulator;
1489         } else {
1490                 err = regulator_enable(tegra->xusb_s3p3v_reg);
1491                 if (err < 0) {
1492                         dev_err(&pdev->dev,
1493                                 "3p3v: regulator enable failed:%d\n", err);
1494                         goto err_null_regulator;
1495                 }
1496         }
1497
1498         /* enable utmi vbuses */
1499         memset(tegra->xusb_utmi_vbus_regs, 0,
1500                         sizeof(tegra->xusb_utmi_vbus_regs));
1501         for (i = 0; i < XUSB_UTMI_COUNT; i++) {
1502                 struct regulator *reg = NULL;
1503                 const char *reg_name = supply->utmi_vbuses[i];
1504                 if (BIT(XUSB_UTMI_INDEX + i) & tegra->bdata->portmap) {
1505                         if (i == 0 && tegra->transceiver)
1506                                 continue;
1507                         reg = devm_regulator_get(&pdev->dev, reg_name);
1508                         if (IS_ERR(reg)) {
1509                                 dev_err(&pdev->dev,
1510                                         "%s regulator not found: %ld.",
1511                                         reg_name, PTR_ERR(reg));
1512                                 err = PTR_ERR(reg);
1513                         } else {
1514                                 err = regulator_enable(reg);
1515                                 if (err < 0) {
1516                                         dev_err(&pdev->dev,
1517                                         "%s: regulator enable failed: %d\n",
1518                                         reg_name, err);
1519                                 }
1520                         }
1521                         if (err)
1522                                 goto err_put_utmi_vbus_reg;
1523                 }
1524                 tegra->xusb_utmi_vbus_regs[i] = reg;
1525         }
1526
1527         tegra->xusb_s1p8v_reg =
1528                 devm_regulator_get(&pdev->dev, supply->s1p8v);
1529         if (IS_ERR(tegra->xusb_s1p8v_reg)) {
1530                 dev_err(&pdev->dev, "1p8v regulator not found: %ld."
1531                         , PTR_ERR(tegra->xusb_s1p8v_reg));
1532                 err = PTR_ERR(tegra->xusb_s1p8v_reg);
1533                 goto err_put_utmi_vbus_reg;
1534         } else {
1535                 err = regulator_enable(tegra->xusb_s1p8v_reg);
1536                 if (err < 0) {
1537                         dev_err(&pdev->dev,
1538                         "1p8v: regulator enable failed:%d\n", err);
1539                         goto err_put_utmi_vbus_reg;
1540                 }
1541         }
1542
1543         tegra->xusb_s1p05v_reg =
1544                         devm_regulator_get(&pdev->dev, supply->s1p05v);
1545         if (IS_ERR(tegra->xusb_s1p05v_reg)) {
1546                 dev_err(&pdev->dev, "1p05v: regulator not found: %ld."
1547                         , PTR_ERR(tegra->xusb_s1p05v_reg));
1548                 err = PTR_ERR(tegra->xusb_s1p05v_reg);
1549                 goto err_put_s1p8v_reg;
1550         } else {
1551                 err = regulator_enable(tegra->xusb_s1p05v_reg);
1552                 if (err < 0) {
1553                         dev_err(&pdev->dev,
1554                         "1p05v: regulator enable failed:%d\n", err);
1555                         goto err_put_s1p8v_reg;
1556                 }
1557         }
1558
1559         return err;
1560
1561 err_put_s1p8v_reg:
1562         regulator_disable(tegra->xusb_s1p8v_reg);
1563 err_put_utmi_vbus_reg:
1564         for (i = 0; i < XUSB_UTMI_COUNT; i++) {
1565                 struct regulator *reg = tegra->xusb_utmi_vbus_regs[i];
1566                 if (!IS_ERR_OR_NULL(reg))
1567                         regulator_disable(reg);
1568         }
1569         regulator_disable(tegra->xusb_s3p3v_reg);
1570 err_null_regulator:
1571         for (i = 0; i < XUSB_UTMI_COUNT; i++)
1572                 tegra->xusb_utmi_vbus_regs[i] = NULL;
1573         tegra->xusb_s1p05v_reg = NULL;
1574         tegra->xusb_s3p3v_reg = NULL;
1575         tegra->xusb_s1p8v_reg = NULL;
1576         return err;
1577 }
1578
1579 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
1580 {
1581         int i;
1582
1583         regulator_disable(tegra->xusb_s1p05v_reg);
1584         regulator_disable(tegra->xusb_s1p8v_reg);
1585
1586         for (i = 0; i < XUSB_UTMI_COUNT; i++) {
1587                 if (BIT(XUSB_UTMI_INDEX + i) & tegra->bdata->portmap) {
1588                         struct regulator *reg = tegra->xusb_utmi_vbus_regs[i];
1589                         if (!IS_ERR_OR_NULL(reg))
1590                                 regulator_disable(reg);
1591                         tegra->xusb_utmi_vbus_regs[i] = NULL;
1592                 }
1593         }
1594
1595         regulator_disable(tegra->xusb_s3p3v_reg);
1596
1597         tegra->xusb_s1p05v_reg = NULL;
1598         tegra->xusb_s1p8v_reg = NULL;
1599         tegra->xusb_s3p3v_reg = NULL;
1600 }
1601
1602 /*
1603  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
1604  * are under hardware control
1605  */
1606 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
1607 {
1608         struct platform_device *pdev = tegra->pdev;
1609         int err = 0;
1610
1611         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
1612         if (IS_ERR(tegra->plle_clk)) {
1613                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
1614                 err = PTR_ERR(tegra->plle_clk);
1615                 return err;
1616         }
1617         err = clk_enable(tegra->plle_clk);
1618         if (err) {
1619                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
1620                         __func__);
1621                 return err;
1622         }
1623
1624         return err;
1625 }
1626
1627 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
1628 {
1629         clk_disable(tegra->plle_clk);
1630         tegra->plle_clk = NULL;
1631 }
1632
1633 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
1634 {
1635         struct platform_device *pdev = tegra->pdev;
1636         int err = 0;
1637
1638         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
1639         if (IS_ERR(tegra->emc_clk)) {
1640                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
1641                 return PTR_ERR(tegra->emc_clk);
1642         }
1643
1644         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1645                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
1646                 if (IS_ERR(tegra->pll_re_vco_clk)) {
1647                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
1648                         err = PTR_ERR(tegra->pll_re_vco_clk);
1649                         goto get_pll_re_vco_clk_failed;
1650                 }
1651         }
1652
1653         /* get the clock handle of 120MHz clock source */
1654         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
1655         if (IS_ERR(tegra->pll_u_480M)) {
1656                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
1657                 err = PTR_ERR(tegra->pll_u_480M);
1658                 goto get_pll_u_480M_failed;
1659         }
1660
1661         /* get the clock handle of 12MHz clock source */
1662         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1663         if (IS_ERR(tegra->clk_m)) {
1664                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
1665                 err = PTR_ERR(tegra->clk_m);
1666                 goto clk_get_clk_m_failed;
1667         }
1668
1669         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
1670         if (IS_ERR(tegra->ss_src_clk)) {
1671                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
1672                 err = PTR_ERR(tegra->ss_src_clk);
1673                 tegra->ss_src_clk = NULL;
1674                 goto get_ss_src_clk_failed;
1675         }
1676
1677         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
1678         if (IS_ERR(tegra->host_clk)) {
1679                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
1680                 err = PTR_ERR(tegra->host_clk);
1681                 tegra->host_clk = NULL;
1682                 goto get_host_clk_failed;
1683         }
1684
1685         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
1686         if (IS_ERR(tegra->ss_clk)) {
1687                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
1688                 err = PTR_ERR(tegra->ss_clk);
1689                 tegra->ss_clk = NULL;
1690                 goto get_ss_clk_failed;
1691         }
1692
1693         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1694                 err = clk_enable(tegra->pll_re_vco_clk);
1695                 if (err) {
1696                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
1697                         goto enable_pll_re_vco_clk_failed;
1698                 }
1699         }
1700         return 0;
1701
1702 enable_pll_re_vco_clk_failed:
1703         tegra->ss_clk = NULL;
1704
1705 get_ss_clk_failed:
1706         tegra->host_clk = NULL;
1707
1708 get_host_clk_failed:
1709         tegra->ss_src_clk = NULL;
1710
1711 get_ss_src_clk_failed:
1712         tegra->clk_m = NULL;
1713
1714 clk_get_clk_m_failed:
1715         tegra->pll_u_480M = NULL;
1716
1717 get_pll_u_480M_failed:
1718         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1719                 tegra->pll_re_vco_clk = NULL;
1720
1721 get_pll_re_vco_clk_failed:
1722         tegra->emc_clk = NULL;
1723
1724         return err;
1725 }
1726
1727 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
1728 {
1729         clk_disable(tegra->ss_clk);
1730         clk_disable(tegra->host_clk);
1731         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1732                 clk_disable(tegra->pll_re_vco_clk);
1733         tegra->ss_clk = NULL;
1734         tegra->host_clk = NULL;
1735         tegra->ss_src_clk = NULL;
1736         tegra->clk_m = NULL;
1737         tegra->pll_u_480M = NULL;
1738         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1739                 tegra->pll_re_vco_clk = NULL;
1740 }
1741
1742 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
1743         bool enable)
1744 {
1745         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1746         u32 reg;
1747
1748         /* Issue is only applicable for T114 */
1749         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
1750                 return;
1751
1752         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1753                 reg = readl(tegra->padctl_base +
1754                         padregs->iophy_misc_pad_p0_ctl3_0);
1755                 if (enable) {
1756                         reg &= ~RX_IDLE_MODE;
1757                         reg |= RX_IDLE_MODE_OVRD;
1758                 } else {
1759                         reg |= RX_IDLE_MODE;
1760                         reg &= ~RX_IDLE_MODE_OVRD;
1761                 }
1762                 writel(reg, tegra->padctl_base +
1763                         padregs->iophy_misc_pad_p0_ctl3_0);
1764         }
1765
1766         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1767                 reg = readl(tegra->padctl_base +
1768                         padregs->iophy_misc_pad_p1_ctl3_0);
1769                 if (enable) {
1770                         reg &= ~RX_IDLE_MODE;
1771                         reg |= RX_IDLE_MODE_OVRD;
1772                 } else {
1773                         reg |= RX_IDLE_MODE;
1774                         reg &= ~RX_IDLE_MODE_OVRD;
1775                 }
1776                 writel(reg, tegra->padctl_base +
1777                         padregs->iophy_misc_pad_p1_ctl3_0);
1778
1779                 /* SATA lane also if USB3_SS port1 mapped to it */
1780                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
1781                                 tegra->bdata->lane_owner & BIT(0)) {
1782                         reg = readl(tegra->padctl_base +
1783                                 padregs->iophy_misc_pad_s0_ctl3_0);
1784                         if (enable) {
1785                                 reg &= ~RX_IDLE_MODE;
1786                                 reg |= RX_IDLE_MODE_OVRD;
1787                         } else {
1788                                 reg |= RX_IDLE_MODE;
1789                                 reg &= ~RX_IDLE_MODE_OVRD;
1790                         }
1791                         writel(reg, tegra->padctl_base +
1792                                 padregs->iophy_misc_pad_s0_ctl3_0);
1793                 }
1794         }
1795 }
1796
1797 /* Enable ss clk, host clk, falcon clk,
1798  * fs clk, dev clk, plle and refplle
1799  */
1800
1801 static int
1802 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
1803                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
1804 {
1805         int ret = 0;
1806         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
1807         int fw_req_rate = rate, cur_rate;
1808
1809         /* Do not handle clock change as needed for HS disconnect issue */
1810         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1811                 *sw_resp = CMD_DATA(fw_req_rate) | CMD_TYPE(MBOX_CMD_ACK);
1812                 return ret;
1813         }
1814
1815         /* frequency request from firmware is in KHz.
1816          * Convert it to MHz
1817          */
1818
1819         /* get current rate of clock */
1820         cur_rate = clk_get_rate(clk_handle);
1821         cur_rate /= 1000;
1822
1823         if (fw_req_rate == cur_rate) {
1824                 cmd_ack = MBOX_CMD_ACK;
1825
1826         } else {
1827
1828                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
1829                         /* Change SS clock source to CLK_M at 12MHz */
1830                         clk_set_parent(clk_handle, tegra->clk_m);
1831                         clk_set_rate(clk_handle, fw_req_rate * 1000);
1832
1833                         /* save leakage power when SS freq is being decreased */
1834                         tegra_xhci_rx_idle_mode_override(tegra, true);
1835                 } else if (clk_handle == tegra->ss_src_clk &&
1836                                 fw_req_rate == 120000) {
1837                         /* Change SS clock source to HSIC_480 at 120MHz */
1838                         clk_set_rate(clk_handle,  3000 * 1000);
1839                         clk_set_parent(clk_handle, tegra->pll_u_480M);
1840
1841                         /* clear ovrd bits when SS freq is being increased */
1842                         tegra_xhci_rx_idle_mode_override(tegra, false);
1843                 }
1844
1845                 cur_rate = (clk_get_rate(clk_handle) / 1000);
1846
1847                 if (cur_rate != fw_req_rate) {
1848                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
1849                                 cur_rate, fw_req_rate);
1850                         cmd_ack = MBOX_CMD_NACK;
1851                 }
1852         }
1853         *sw_resp = CMD_DATA(cur_rate) | CMD_TYPE(cmd_ack);
1854         return ret;
1855 }
1856
1857 static void tegra_xusb_set_bw(struct tegra_xhci_hcd *tegra, unsigned int bw)
1858 {
1859         unsigned int freq_khz;
1860
1861         freq_khz = tegra_emc_bw_to_freq_req(bw);
1862         clk_set_rate(tegra->emc_clk, freq_khz * 1000);
1863 }
1864
1865 static void tegra_xhci_save_dfe_context(struct tegra_xhci_hcd *tegra,
1866         u8 port)
1867 {
1868         struct xhci_hcd *xhci = tegra->xhci;
1869         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1870         u32 offset;
1871         u32 reg;
1872
1873         if (port > (XUSB_SS_PORT_COUNT - 1)) {
1874                 pr_err("%s invalid SS port number %u\n", __func__, port);
1875                 return;
1876         }
1877
1878         xhci_info(xhci, "saving restore DFE context for port %d\n", port);
1879
1880         /* if port1 is mapped to SATA lane then read from SATA register */
1881         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1882                         tegra->bdata->lane_owner & BIT(0))
1883                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1884         else
1885                 offset = MISC_PAD_CTL_6_0(port);
1886
1887         /*
1888          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
1889          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
1890          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
1891          */
1892         reg = readl(tegra->padctl_base + offset);
1893         reg &= ~MISC_OUT_SEL(~0);
1894         reg |= MISC_OUT_SEL(0x32);
1895         writel(reg, tegra->padctl_base + offset);
1896
1897         reg = readl(tegra->padctl_base + offset);
1898         tegra->sregs.tap1_val[port] = MISC_OUT_TAP_VAL(reg);
1899
1900         reg = readl(tegra->padctl_base + offset);
1901         reg &= ~MISC_OUT_SEL(~0);
1902         reg |= MISC_OUT_SEL(0x33);
1903         writel(reg, tegra->padctl_base + offset);
1904
1905         reg = readl(tegra->padctl_base + offset);
1906         tegra->sregs.amp_val[port] = MISC_OUT_AMP_VAL(reg);
1907
1908         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1909         reg &= ~DFE_CNTL_TAP_VAL(~0);
1910         reg |= DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
1911         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1912
1913         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1914         reg &= ~DFE_CNTL_AMP_VAL(~0);
1915         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]);
1916         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1917
1918         tegra->dfe_ctx_saved[port] = true;
1919 }
1920
1921 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
1922         u8 port)
1923 {
1924         struct xhci_hcd *xhci = tegra->xhci;
1925         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1926         u32 offset;
1927         u32 reg;
1928
1929         if (port > (XUSB_SS_PORT_COUNT - 1)) {
1930                 pr_err("%s invalid SS port number %u\n", __func__, port);
1931                 return;
1932         }
1933
1934         xhci_info(xhci, "saving restore CTLE context for port %d\n", port);
1935
1936         /* if port1 is mapped to SATA lane then read from SATA register */
1937         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1938                         tegra->bdata->lane_owner & BIT(0))
1939                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1940         else
1941                 offset = MISC_PAD_CTL_6_0(port);
1942
1943         /*
1944          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
1945          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
1946          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
1947          */
1948         reg = readl(tegra->padctl_base + offset);
1949         reg &= ~MISC_OUT_SEL(~0);
1950         reg |= MISC_OUT_SEL(0xa1);
1951         writel(reg, tegra->padctl_base + offset);
1952
1953         reg = readl(tegra->padctl_base + offset);
1954         reg &= ~MISC_OUT_SEL(~0);
1955         reg |= MISC_OUT_SEL(0x21);
1956         writel(reg, tegra->padctl_base + offset);
1957
1958         reg = readl(tegra->padctl_base + offset);
1959         tegra->sregs.ctle_g_val[port] = MISC_OUT_G_Z_VAL(reg);
1960
1961         reg = readl(tegra->padctl_base + offset);
1962         reg &= ~MISC_OUT_SEL(~0);
1963         reg |= MISC_OUT_SEL(0x48);
1964         writel(reg, tegra->padctl_base + offset);
1965
1966         reg = readl(tegra->padctl_base + offset);
1967         tegra->sregs.ctle_z_val[port] = MISC_OUT_G_Z_VAL(reg);
1968
1969         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1970         reg &= ~RX_EQ_Z_VAL(~0);
1971         reg |= RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]);
1972         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1973
1974         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1975         reg &= ~RX_EQ_G_VAL(~0);
1976         reg |= RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]);
1977         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1978
1979         tegra->ctle_ctx_saved[port] = true;
1980 }
1981
1982 static void tegra_xhci_restore_dfe_context(struct tegra_xhci_hcd *tegra,
1983         u8 port)
1984 {
1985         struct xhci_hcd *xhci = tegra->xhci;
1986         u32 reg;
1987
1988         /* don't restore if not saved */
1989         if (tegra->dfe_ctx_saved[port] == false)
1990                 return;
1991
1992         xhci_info(xhci, "restoring dfe context of port %d\n", port);
1993
1994         /* restore dfe_cntl for the port */
1995         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1996         reg &= ~(DFE_CNTL_AMP_VAL(~0) |
1997                         DFE_CNTL_TAP_VAL(~0));
1998         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]) |
1999                 DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
2000         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
2001 }
2002
2003 void restore_ctle_context(struct tegra_xhci_hcd *tegra,
2004         u8 port)
2005 {
2006         struct xhci_hcd *xhci = tegra->xhci;
2007         u32 reg;
2008
2009         /* don't restore if not saved */
2010         if (tegra->ctle_ctx_saved[port] == false)
2011                 return;
2012
2013         xhci_info(xhci, "restoring CTLE context of port %d\n", port);
2014
2015         /* restore ctle for the port */
2016         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
2017         reg &= ~(RX_EQ_Z_VAL(~0) |
2018                         RX_EQ_G_VAL(~0));
2019         reg |= (RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]) |
2020                 RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]));
2021         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
2022 }
2023
2024 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
2025         u8 port)
2026 {
2027         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2028         u32 reg;
2029
2030         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2031         reg &= ~USB2_ULPI_PAD;
2032         reg |= USB2_ULPI_PAD_OWNER_XUSB;
2033         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2034
2035         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
2036         reg &= ~USB2_ULPI_PORT_CAP;
2037         reg |= (tegra->bdata->ulpicap << 24);
2038         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
2039         /* FIXME: Program below when more details available
2040          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
2041          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
2042          */
2043 }
2044
2045 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
2046         u8 port)
2047 {
2048         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2049         u32 reg;
2050         u32 ctl0_offset, ctl1_offset;
2051
2052         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2053         reg &= ~USB2_OTG_PAD_PORT_MASK(port);
2054         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
2055         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2056
2057         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
2058         reg &= ~USB2_PORT_CAP_MASK(port);
2059         reg |= USB2_PORT_CAP_HOST(port);
2060         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
2061
2062         /*
2063          * Modify only the bits which belongs to the port
2064          * and enable respective VBUS_PAD for the port
2065          */
2066         if (tegra->bdata->uses_external_pmic == false) {
2067                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2068                 reg &= ~(port == 2 ? OC_DET_VBUS_ENABLE2_OC_MAP :
2069                         port ? OC_DET_VBUS_ENABLE1_OC_MAP :
2070                                 OC_DET_VBUS_ENABLE0_OC_MAP);
2071
2072                 reg |= (port == 2) ? OC_DET_VBUS_EN2_OC_DETECTED_VBUS_PAD2 :
2073                         port ? OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1 :
2074                                 OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0;
2075                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
2076         }
2077         /*
2078          * enable respective VBUS_PAD if port is mapped to any SS port
2079          */
2080         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
2081         reg &= ~((port == 2) ? USB2_OC_MAP_PORT2 :
2082                 port ? USB2_OC_MAP_PORT1 : USB2_OC_MAP_PORT0);
2083         reg |= (0x4 | port) << (port * 3);
2084         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
2085
2086         ctl0_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl0_0 :
2087                         port ? padregs->usb2_otg_pad1_ctl0_0 :
2088                                 padregs->usb2_otg_pad0_ctl0_0;
2089         ctl1_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl1_0 :
2090                         port ? padregs->usb2_otg_pad1_ctl1_0 :
2091                                 padregs->usb2_otg_pad0_ctl1_0;
2092
2093         reg = readl(tegra->padctl_base + ctl0_offset);
2094         reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
2095                 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
2096                 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
2097
2098         reg |= tegra->pdata->hs_slew;
2099         reg |= (port == 2) ? tegra->pdata->ls_rslew_pad2 :
2100                         port ? tegra->pdata->ls_rslew_pad1 :
2101                         tegra->pdata->ls_rslew_pad0;
2102         reg |= (port == 2) ? tegra->pdata->hs_curr_level_pad2 :
2103                         port ? tegra->pdata->hs_curr_level_pad1 :
2104                         tegra->pdata->hs_curr_level_pad0;
2105         writel(reg, tegra->padctl_base + ctl0_offset);
2106
2107         reg = readl(tegra->padctl_base + ctl1_offset);
2108         reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
2109                 | USB2_OTG_PD_CHRP_FORCE_POWERUP
2110                 | USB2_OTG_PD_DISC_FORCE_POWERUP
2111                 | USB2_OTG_PD_DR);
2112         reg |= (tegra->pdata->hs_iref_cap << 9) |
2113                 (tegra->pdata->hs_term_range_adj << 3);
2114         writel(reg, tegra->padctl_base + ctl1_offset);
2115
2116         /*Release OTG port if not in host mode*/
2117
2118         if ((port == 0) && !is_otg_host(tegra))
2119                 tegra_xhci_release_otg_port(true);
2120 }
2121
2122 static inline bool xusb_use_sata_lane(struct tegra_xhci_hcd *tegra)
2123 {
2124         return ((XUSB_DEVICE_ID_T114 == tegra->device_id) ? false
2125         : ((tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
2126                 && (tegra->bdata->lane_owner & BIT(0))));
2127 }
2128
2129 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
2130         u8 port)
2131 {
2132         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2133         u32 ctl2_offset, ctl4_offset, ctl5_offset;
2134         u32 reg;
2135
2136         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
2137                         padregs->iophy_usb3_pad0_ctl2_0;
2138         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
2139                         padregs->iophy_usb3_pad0_ctl4_0;
2140         ctl5_offset = port ? padregs->iophy_misc_pad_p1_ctl5_0 :
2141                         padregs->iophy_misc_pad_p0_ctl5_0;
2142
2143         reg = readl(tegra->padctl_base + ctl2_offset);
2144         reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
2145                 IOPHY_USB3_CDRCNTL);
2146         reg |= tegra->pdata->rx_wander | tegra->pdata->rx_eq |
2147                 tegra->pdata->cdr_cntl;
2148         writel(reg, tegra->padctl_base + ctl2_offset);
2149
2150         reg = readl(tegra->padctl_base + ctl4_offset);
2151         reg = tegra->pdata->dfe_cntl;
2152         writel(reg, tegra->padctl_base + ctl4_offset);
2153
2154         reg = readl(tegra->padctl_base + ctl5_offset);
2155         reg |= RX_QEYE_EN;
2156         writel(reg, tegra->padctl_base + ctl5_offset);
2157
2158         reg = readl(tegra->padctl_base + MISC_PAD_CTL_2_0(port));
2159         reg &= ~SPARE_IN(~0);
2160         reg |= SPARE_IN(tegra->pdata->spare_in);
2161         writel(reg, tegra->padctl_base + MISC_PAD_CTL_2_0(port));
2162
2163         if (xusb_use_sata_lane(tegra)) {
2164                 reg = readl(tegra->padctl_base + MISC_PAD_S0_CTL_5_0);
2165                 reg |= RX_QEYE_EN;
2166                 writel(reg, tegra->padctl_base + MISC_PAD_S0_CTL_5_0);
2167
2168                 reg = readl(tegra->padctl_base + MISC_PAD_S0_CTL_2_0);
2169                 reg &= ~SPARE_IN(~0);
2170                 reg |= SPARE_IN(tegra->pdata->spare_in);
2171                 writel(reg, tegra->padctl_base + MISC_PAD_S0_CTL_2_0);
2172         }
2173
2174         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
2175         reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
2176         reg |= (tegra->bdata->ss_portmap &
2177                 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
2178         writel(reg, tegra->padctl_base + padregs->ss_port_map_0);
2179
2180         tegra_xhci_restore_dfe_context(tegra, port);
2181         tegra_xhci_restore_ctle_context(tegra, port);
2182 }
2183
2184 /* This function assigns the USB ports to the controllers,
2185  * then programs the port capabilities and pad parameters
2186  * of ports assigned to XUSB after booted to OS.
2187  */
2188 void
2189 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
2190 {
2191         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2192         u32 reg, oc_bits = 0;
2193         unsigned pad;
2194
2195         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2196         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
2197         reg |= tegra->pdata->hs_squelch_level | tegra->pdata->hs_disc_lvl;
2198         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2199
2200         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
2201         reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3;
2202         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
2203         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
2204
2205         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2206         reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
2207         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2208                 reg |= OC_DET_VBUS_ENABLE2_OC_MAP;
2209         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2210
2211         /* check if over current seen. Clear if present */
2212         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2213                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2214         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2215                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2216         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2217                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2218
2219         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2220         if (reg & oc_bits) {
2221                 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
2222                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
2223
2224                 usleep_range(100, 200);
2225
2226                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2227                 if (reg & oc_bits)
2228                         xhci_info(tegra->xhci, "Over current still present\n");
2229         }
2230
2231         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
2232         reg = USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1;
2233         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2234                 reg |= USB2_OC_MAP_PORT2;
2235         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
2236
2237         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2238                 tegra_xhci_program_utmip_pad(tegra, 0);
2239         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2240                 tegra_xhci_program_utmip_pad(tegra, 1);
2241         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2242                 tegra_xhci_program_utmip_pad(tegra, 2);
2243
2244         for_each_enabled_hsic_pad(pad, tegra)
2245                 hsic_pad_enable(tegra, pad);
2246
2247         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
2248                 tegra_xhci_program_ulpi_pad(tegra, 0);
2249
2250         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
2251                 tegra_xhci_program_ss_pad(tegra, 0);
2252         } else {
2253                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
2254                 reg = readl(tegra->padctl_base +
2255                         padregs->iophy_misc_pad_p0_ctl3_0);
2256                 reg &= ~RX_IDLE_MODE;
2257                 reg |= RX_IDLE_MODE_OVRD;
2258                 writel(reg, tegra->padctl_base +
2259                         padregs->iophy_misc_pad_p0_ctl3_0);
2260         }
2261
2262         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
2263                 tegra_xhci_program_ss_pad(tegra, 1);
2264         } else {
2265                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
2266                 reg = readl(tegra->padctl_base +
2267                         padregs->iophy_misc_pad_p1_ctl3_0);
2268                 reg &= ~RX_IDLE_MODE;
2269                 reg |= RX_IDLE_MODE_OVRD;
2270                 writel(reg, tegra->padctl_base +
2271                         padregs->iophy_misc_pad_p1_ctl3_0);
2272
2273                 /* SATA lane also if USB3_SS port1 mapped to it but unused */
2274                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
2275                                 tegra->bdata->lane_owner & BIT(0)) {
2276                         reg = readl(tegra->padctl_base +
2277                                 padregs->iophy_misc_pad_s0_ctl3_0);
2278                         reg &= ~RX_IDLE_MODE;
2279                         reg |= RX_IDLE_MODE_OVRD;
2280                         writel(reg, tegra->padctl_base +
2281                                 padregs->iophy_misc_pad_s0_ctl3_0);
2282                 }
2283         }
2284         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2285                 tegra_xhci_setup_gpio_for_ss_lane(tegra);
2286                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
2287         }
2288 }
2289
2290 /* This function read XUSB registers and stores in device context */
2291 static void
2292 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
2293 {
2294
2295         /* a. Save the IPFS registers */
2296         tegra->sregs.msi_bar_sz =
2297                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2298
2299         tegra->sregs.msi_axi_barst =
2300                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2301
2302         tegra->sregs.msi_fpci_barst =
2303                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2304
2305         tegra->sregs.msi_vec0 =
2306                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2307
2308         tegra->sregs.msi_en_vec0 =
2309                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2310
2311         tegra->sregs.fpci_error_masks =
2312                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2313
2314         tegra->sregs.intr_mask =
2315                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2316
2317         tegra->sregs.ipfs_intr_enable =
2318                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2319
2320         tegra->sregs.ufpci_config =
2321                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2322
2323         tegra->sregs.clkgate_hysteresis =
2324                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2325
2326         tegra->sregs.xusb_host_mccif_fifo_cntrl =
2327                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2328
2329         /* b. Save the CFG registers */
2330
2331         tegra->sregs.hs_pls =
2332                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2333
2334         tegra->sregs.fs_pls =
2335                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2336
2337         tegra->sregs.hs_fs_speed =
2338                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2339
2340         tegra->sregs.hs_fs_pp =
2341                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2342
2343         tegra->sregs.cfg_aru =
2344                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2345
2346         tegra->sregs.cfg_order =
2347                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
2348
2349         tegra->sregs.cfg_fladj =
2350                 readl(tegra->fpci_base + XUSB_CFG_24);
2351
2352         tegra->sregs.cfg_sid =
2353                 readl(tegra->fpci_base + XUSB_CFG_16);
2354 }
2355
2356 /* This function restores XUSB registers from device context */
2357 static void
2358 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
2359 {
2360         /* Restore Cfg registers */
2361         writel(tegra->sregs.hs_pls,
2362                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2363
2364         writel(tegra->sregs.fs_pls,
2365                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2366
2367         writel(tegra->sregs.hs_fs_speed,
2368                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2369
2370         writel(tegra->sregs.hs_fs_pp,
2371                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2372
2373         writel(tegra->sregs.cfg_aru,
2374                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2375
2376         writel(tegra->sregs.cfg_order,
2377                 tegra->fpci_base + XUSB_CFG_FPCICFG);
2378
2379         writel(tegra->sregs.cfg_fladj,
2380                 tegra->fpci_base + XUSB_CFG_24);
2381
2382         writel(tegra->sregs.cfg_sid,
2383                 tegra->fpci_base + XUSB_CFG_16);
2384
2385         /* Restore IPFS registers */
2386
2387         writel(tegra->sregs.msi_bar_sz,
2388                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2389
2390         writel(tegra->sregs.msi_axi_barst,
2391                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2392
2393         writel(tegra->sregs.msi_fpci_barst,
2394                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2395
2396         writel(tegra->sregs.msi_vec0,
2397                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2398
2399         writel(tegra->sregs.msi_en_vec0,
2400                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2401
2402         writel(tegra->sregs.fpci_error_masks,
2403                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2404
2405         writel(tegra->sregs.intr_mask,
2406                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2407
2408         writel(tegra->sregs.ipfs_intr_enable,
2409                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2410
2411         writel(tegra->sregs.ufpci_config,
2412                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2413
2414         writel(tegra->sregs.clkgate_hysteresis,
2415                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2416
2417         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
2418                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2419 }
2420
2421 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
2422 {
2423         fw_message_send(tegra, MBOX_CMD_MSG_ENABLED, 0 /* no data needed */);
2424 }
2425
2426 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
2427 {
2428         struct platform_device *pdev = tegra->pdev;
2429         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
2430         u32 phys_addr_lo;
2431         u32 HwReg;
2432         u16 nblocks;
2433         time_t fw_time;
2434         struct tm fw_tm;
2435         u8 hc_caplength;
2436         u32 usbsts, count = 0xff;
2437         struct xhci_cap_regs __iomem *cap_regs;
2438         struct xhci_op_regs __iomem *op_regs;
2439
2440         /* enable mbox interrupt */
2441         writel(readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD) | MBOX_INT_EN,
2442                 tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2443
2444         /* First thing, reset the ARU. By the time we get to
2445          * loading boot code below, reset would be complete.
2446          * alternatively we can busy wait on rst pending bit.
2447          */
2448         /* Don't reset during ELPG/LP0 exit path */
2449         if (resetARU) {
2450                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
2451                 usleep_range(1000, 2000);
2452         }
2453
2454         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
2455                 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
2456                                 csb_read(tegra, XUSB_FALC_CPUCTL));
2457                 return 0;
2458         }
2459
2460         /* update the phys_log_buffer and total_entries here */
2461         cfg_tbl->phys_addr_log_buffer = tegra->log.phys_addr;
2462         cfg_tbl->total_log_entries = FW_LOG_COUNT;
2463
2464         phys_addr_lo = tegra->firmware.dma;
2465         phys_addr_lo += sizeof(struct cfgtbl);
2466
2467         /* Program the size of DFI into ILOAD_ATTR */
2468         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
2469
2470         /* Boot code of the firmware reads the ILOAD_BASE_LO register
2471          * to get to the start of the dfi in system memory.
2472          */
2473         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
2474
2475         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
2476         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
2477
2478         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
2479         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
2480
2481         /* Invalidate L2IMEM. */
2482         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
2483
2484         /* Initiate fetch of Bootcode from system memory into L2IMEM.
2485          * Program BootCode location and size in system memory.
2486          */
2487         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
2488                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
2489                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
2490         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
2491                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
2492                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
2493         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
2494
2495         /* Trigger L2IMEM Load operation. */
2496         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
2497
2498         /* Setup Falcon Auto-fill */
2499         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
2500         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
2501                 nblocks += 1;
2502         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
2503
2504         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
2505         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
2506                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
2507         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
2508
2509         csb_write(tegra, XUSB_FALC_DMACTL, 0);
2510         msleep(50);
2511
2512         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
2513
2514         /* Start Falcon CPU */
2515         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
2516         usleep_range(1000, 2000);
2517
2518         fw_time = cfg_tbl->fwimg_created_time;
2519         time_to_tm(fw_time, 0, &fw_tm);
2520         dev_info(&pdev->dev,
2521                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
2522                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
2523                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
2524                 fw_tm.tm_min, fw_tm.tm_sec,
2525                 csb_read(tegra, XUSB_FALC_CPUCTL));
2526
2527         dev_dbg(&pdev->dev, "num_hsic_port %d\n", cfg_tbl->num_hsic_port);
2528
2529         /* return fail if firmware status is not good */
2530         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
2531                 return -EFAULT;
2532
2533         cap_regs = IO_ADDRESS(tegra->host_phy_base);
2534         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
2535         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
2536
2537         /* wait for USBSTS_CNR to get set */
2538         do {
2539                 usbsts = ioread32(&op_regs->status);
2540         } while ((usbsts & STS_CNR) && count--);
2541
2542         if (!count && (usbsts & STS_CNR)) {
2543                 dev_err(&pdev->dev, "Controller not ready\n");
2544                 return -EFAULT;
2545         }
2546
2547         return 0;
2548 }
2549
2550 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
2551         bool release)
2552 {
2553         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2554         u32 reg;
2555
2556         /* Issue is only applicable for T114 */
2557         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
2558                 return;
2559
2560         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2561         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2562                         USB2_OTG_PAD_PORT_MASK(2));
2563
2564         if (!release) {
2565                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2566                         if (is_otg_host(tegra))
2567                                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2568                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2569                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2570                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2571                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2572         }
2573
2574         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2575 }
2576 /* SS ELPG Entry initiated by fw */
2577 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
2578 {
2579         struct xhci_hcd *xhci = tegra->xhci;
2580         u32 ret = 0;
2581
2582         must_have_sync_lock(tegra);
2583
2584         /* update maximum BW requirement to 0 */
2585         tegra_xusb_set_bw(tegra, 0);
2586
2587         /* This is SS partition ELPG entry
2588          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
2589          */
2590
2591         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
2592          * only if it is sw initiated one
2593          */
2594
2595         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
2596          * SuperSpeed partition ELPG entry via mailbox protocol
2597          */
2598
2599         /* STEP 2: xHCI PEP driver and XUSB device mode driver
2600          * enable the XUSB wakeup interrupts for the SuperSpeed
2601          * and USB2.0 ports assigned to host.Section 4.1 Step 3
2602          */
2603         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2604
2605         /* STEP 3: xHCI PEP driver initiates the signal sequence
2606          * to enable the XUSB SSwake detection logic for the
2607          * SuperSpeed ports assigned to host.Section 4.1 Step 4
2608          */
2609         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, true);
2610
2611         /* STEP 4: System Power Management driver asserts reset
2612          * to XUSB SuperSpeed partition then disables its clocks
2613          */
2614         tegra_periph_reset_assert(tegra->ss_clk);
2615         clk_disable(tegra->ss_clk);
2616
2617         usleep_range(100, 200);
2618
2619         /* STEP 5: System Power Management driver disables the
2620          * XUSB SuperSpeed partition power rails.
2621          */
2622         debug_print_portsc(xhci);
2623
2624         /* tegra_powergate_partition also does partition reset assert */
2625         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
2626         if (ret) {
2627                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
2628                                 __func__);
2629                 /* TODO: error recovery? */
2630         }
2631         tegra->ss_pwr_gated = true;
2632
2633         /* STEP 6: xHCI PEP driver initiates the signal sequence
2634          * to enable the XUSB SSwake detection logic for the
2635          * SuperSpeed ports assigned to host.Section 4.1 Step 7
2636          */
2637         tegra_xhci_ss_vcore(tegra->bdata->portmap, true);
2638
2639         return ret;
2640 }
2641
2642 /* Host ELPG Entry */
2643 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
2644 {
2645         struct xhci_hcd *xhci = tegra->xhci;
2646         u32 ret;
2647
2648         must_have_sync_lock(tegra);
2649
2650         /* If ss is already powergated skip ss ctx save stuff */
2651         if (tegra->ss_pwr_gated) {
2652                 xhci_info(xhci, "%s: SS partition is already powergated\n",
2653                         __func__);
2654         } else {
2655                 ret = tegra_xhci_ss_elpg_entry(tegra);
2656                 if (ret) {
2657                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
2658                                 __func__, ret);
2659                         return ret;
2660                 }
2661         }
2662
2663         /* 1. IS INTR PENDING INT_PENDING=1 ? */
2664
2665         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
2666         tegra_xhci_save_xusb_ctx(tegra);
2667
2668         /* calculate rctrl_val and tctrl_val */
2669         tegra_xhci_war_for_tctrl_rctrl(tegra);
2670
2671         pmc_setup_wake_detect(tegra);
2672
2673         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2674         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2675                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2676
2677         /* tegra_powergate_partition also does partition reset assert */
2678         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
2679         if (ret) {
2680                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2681                         __func__, ret);
2682                 /* TODO: error handling? */
2683                 return ret;
2684         }
2685         tegra->host_pwr_gated = true;
2686         clk_disable(tegra->host_clk);
2687
2688         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2689                 clk_disable(tegra->pll_re_vco_clk);
2690         clk_disable(tegra->emc_clk);
2691         /* set port ownership to SNPS */
2692         tegra_xhci_release_port_ownership(tegra, true);
2693
2694         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2695                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2696
2697         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
2698         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
2699                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
2700         return ret;
2701 }
2702
2703 /* SS ELPG Exit triggered by PADCTL irq */
2704 /**
2705  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
2706  *
2707  * This function must be called with tegra->sync_lock acquired.
2708  *
2709  * @tegra: xhci controller context
2710  * @return 0 for success, or error numbers
2711  */
2712 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2713 {
2714         struct xhci_hcd *xhci = tegra->xhci;
2715         int ret = 0;
2716
2717         must_have_sync_lock(tegra);
2718
2719         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
2720                         tegra->hs_wake_event || tegra->host_resume_req)) {
2721
2722                 /*
2723                  * PWR_UNGATE SS partition. XUSBA
2724                  * tegra_unpowergate_partition also does partition reset
2725                  * deassert
2726                  */
2727                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
2728                 if (ret) {
2729                         xhci_err(xhci,
2730                         "%s: could not unpowergate xusba partition %d\n",
2731                         __func__, ret);
2732                         goto out;
2733                 }
2734                 if (tegra->ss_wake_event)
2735                         tegra->ss_wake_event = false;
2736
2737         } else {
2738                 xhci_info(xhci, "%s: ss already power gated\n",
2739                         __func__);
2740                 return ret;
2741         }
2742
2743         /* Step 3: Enable clock to ss partition */
2744         clk_enable(tegra->ss_clk);
2745
2746         /* Step 4: Disable ss wake detection logic */
2747         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2748
2749         /* Step 4.1: Disable ss wake detection logic */
2750         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
2751
2752         /* wait 150us */
2753         usleep_range(150, 200);
2754
2755         /* Step 4.2: Disable ss wake detection logic */
2756         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
2757
2758         /* Step 6 Deassert reset for ss clks */
2759         tegra_periph_reset_deassert(tegra->ss_clk);
2760
2761         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
2762         tegra->ss_pwr_gated = false;
2763 out:
2764         return ret;
2765 }
2766
2767 static void ss_partition_elpg_exit_work(struct work_struct *work)
2768 {
2769         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2770                 ss_elpg_exit_work);
2771
2772         mutex_lock(&tegra->sync_lock);
2773         tegra_xhci_ss_partition_elpg_exit(tegra);
2774         mutex_unlock(&tegra->sync_lock);
2775 }
2776
2777 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
2778 static void update_remote_wakeup_ports(struct tegra_xhci_hcd *tegra)
2779 {
2780         struct xhci_hcd *xhci = tegra->xhci;
2781         u32 wake2_status;
2782         int port;
2783
2784 #define PMC_WAKE2_STATUS        0x168
2785 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
2786
2787         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
2788
2789         if (wake2_status & PADCTL_WAKE) {
2790                 /* FIXME: This is customized for Dalmore, find a generic way */
2791                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
2792                 /* clear wake status */
2793                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
2794         }
2795
2796         /* set all usb2 ports with RESUME link state as wakup ports  */
2797         for (port = 0; port < xhci->num_usb2_ports; port++) {
2798                 u32 portsc = xhci_readl(xhci, xhci->usb2_ports[port]);
2799                 if ((portsc & PORT_PLS_MASK) == XDEV_RESUME)
2800                         set_bit(port, &tegra->usb2_rh_remote_wakeup_ports);
2801         }
2802
2803         xhci_dbg(xhci, "%s: usb2 roothub remote_wakeup_ports 0x%lx\n",
2804                         __func__, tegra->usb2_rh_remote_wakeup_ports);
2805         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
2806                         __func__, tegra->usb3_rh_remote_wakeup_ports);
2807 }
2808
2809 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
2810 {
2811         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2812         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2813         int port, num_ports;
2814         unsigned long *remote_wakeup_ports;
2815         u32 portsc;
2816         __le32 __iomem  **port_array;
2817         unsigned char *rh;
2818         unsigned int retry = 64;
2819         struct xhci_bus_state *bus_state;
2820
2821         bus_state = &xhci->bus_state[hcd_index(hcd)];
2822
2823         if (hcd == xhci->shared_hcd) {
2824                 port_array = xhci->usb3_ports;
2825                 num_ports = xhci->num_usb3_ports;
2826                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
2827                 rh = "usb3 roothub";
2828         } else {
2829                 port_array = xhci->usb2_ports;
2830                 num_ports = xhci->num_usb2_ports;
2831                 remote_wakeup_ports = &tegra->usb2_rh_remote_wakeup_ports;
2832                 rh = "usb2 roothub";
2833         }
2834
2835         while (*remote_wakeup_ports && retry--) {
2836                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
2837                         bool can_continue;
2838
2839                         portsc = xhci_readl(xhci, port_array[port]);
2840
2841                         if (!(portsc & PORT_CONNECT)) {
2842                                 /* nothing to do if already disconnected */
2843                                 clear_bit(port, remote_wakeup_ports);
2844                                 continue;
2845                         }
2846
2847                         if (hcd == xhci->shared_hcd) {
2848                                 can_continue =
2849                                         (portsc & PORT_PLS_MASK) == XDEV_U0;
2850                         } else {
2851                                 unsigned long flags;
2852
2853                                 spin_lock_irqsave(&xhci->lock, flags);
2854                                 can_continue =
2855                                 test_bit(port, &bus_state->resuming_ports);
2856                                 spin_unlock_irqrestore(&xhci->lock, flags);
2857                         }
2858
2859                         if (can_continue)
2860                                 clear_bit(port, remote_wakeup_ports);
2861                         else
2862                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
2863                                         __func__, rh, port, portsc);
2864                 }
2865
2866                 if (*remote_wakeup_ports)
2867                         msleep(20); /* give some time, irq will direct U0 */
2868         }
2869
2870         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
2871                         *remote_wakeup_ports);
2872 }
2873
2874 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
2875 {
2876         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2877         u32 reg, utmip_rctrl_val, utmip_tctrl_val, pad_mux, portmux, portowner;
2878         int port;
2879
2880         portmux = USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1);
2881         portowner = USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
2882                         USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2883
2884         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2885                 portmux |= USB2_OTG_PAD_PORT_MASK(2);
2886                 portowner |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2887         }
2888
2889         /* Use xusb padctl space only when xusb owns all UTMIP port */
2890         pad_mux = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2891         if ((pad_mux & portmux) == portowner) {
2892                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
2893                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
2894                  */
2895                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2896                 reg &= ~((1 << 12) | (1 << 13));
2897                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2898
2899                 /* wait 20us */
2900                 usleep_range(20, 30);
2901
2902                 /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
2903                  * :: TCTRL and RCTRL
2904                  */
2905                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl1_0);
2906                 utmip_rctrl_val = RCTRL(reg);
2907                 utmip_tctrl_val = TCTRL(reg);
2908
2909                 /*
2910                  * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
2911                  * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
2912                  */
2913                 utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
2914                 utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
2915                 utmi_phy_update_trking_data(utmip_tctrl_val, utmip_rctrl_val);
2916                 xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
2917                                         utmip_rctrl_val, utmip_tctrl_val);
2918
2919                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
2920                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
2921                  */
2922                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2923                 reg |= (1 << 13);
2924                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2925
2926                 /* Program these values into PMC regiseter and program the
2927                  * PMC override.
2928                  */
2929                 reg = PMC_TCTRL_VAL(utmip_tctrl_val) |
2930                                 PMC_RCTRL_VAL(utmip_rctrl_val);
2931                 tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG,
2932                                         0xffffffff, reg);
2933                 reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
2934                 tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
2935         } else {
2936                 /* Use common PMC API to use SNPS register space */
2937                 utmi_phy_set_snps_trking_data();
2938         }
2939 }
2940
2941 /* Host ELPG Exit triggered by PADCTL irq */
2942 /**
2943  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
2944  *
2945  * This function must be called with tegra->sync_lock acquired.
2946  *
2947  * @tegra: xhci controller context
2948  * @return 0 for success, or error numbers
2949  */
2950 static int
2951 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2952 {
2953         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2954         struct xhci_hcd *xhci = tegra->xhci;
2955         int ret = 0;
2956
2957         must_have_sync_lock(tegra);
2958
2959         if (!tegra->hc_in_elpg)
2960                 return 0;
2961
2962         clk_enable(tegra->emc_clk);
2963         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2964                 clk_enable(tegra->pll_re_vco_clk);
2965
2966         if (tegra->lp0_exit) {
2967                 u32 reg, oc_bits = 0;
2968
2969                 /* Issue is only applicable for T114 */
2970                 if (XUSB_DEVICE_ID_T114 == tegra->device_id)
2971                         tegra_xhci_war_for_tctrl_rctrl(tegra);
2972                 /* check if over current seen. Clear if present */
2973                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2974                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2975                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2976                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2977                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2978                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2979
2980                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2981                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
2982                 if (reg & oc_bits) {
2983                         xhci_info(xhci, "Over current detected. Clearing...\n");
2984                         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2985
2986                         usleep_range(100, 200);
2987
2988                         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2989                         if (reg & oc_bits)
2990                                 xhci_info(xhci, "Over current still present\n");
2991                 }
2992                 tegra_xhci_padctl_portmap_and_caps(tegra);
2993                 /* release clamps post deassert */
2994                 tegra->lp0_exit = false;
2995         }
2996
2997         /* Clear FLUSH_ENABLE of MC client */
2998         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
2999
3000         /* set port ownership back to xusb */
3001         tegra_xhci_release_port_ownership(tegra, false);
3002
3003         /*
3004          * PWR_UNGATE Host partition. XUSBC
3005          * tegra_unpowergate_partition also does partition reset deassert
3006          */
3007         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3008         if (ret) {
3009                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
3010                         __func__, ret);
3011                 goto out;
3012         }
3013         clk_enable(tegra->host_clk);
3014
3015         /* Step 4: Deassert reset to host partition clk */
3016         tegra_periph_reset_deassert(tegra->host_clk);
3017
3018         /* Step 6.1: IPFS and XUSB BAR initialization */
3019         tegra_xhci_cfg(tegra);
3020
3021         /* Step 6.2: IPFS and XUSB related restore */
3022         tegra_xhci_restore_ctx(tegra);
3023
3024         /* Step 8: xhci spec related ctx restore
3025          * will be done in xhci_resume().Do it here.
3026          */
3027
3028         tegra_xhci_ss_partition_elpg_exit(tegra);
3029
3030         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
3031         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
3032                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
3033                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
3034         }
3035
3036         /* clear ovrd bits */
3037         tegra_xhci_rx_idle_mode_override(tegra, false);
3038
3039         /* Load firmware */
3040         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
3041                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
3042                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
3043                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
3044                         __func__,
3045                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
3046                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
3047                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
3048                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
3049                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
3050                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
3051                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
3052                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
3053                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
3054         debug_print_portsc(xhci);
3055
3056         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
3057         if (ret < 0) {
3058                 xhci_err(xhci, "%s: failed to load firmware %d\n",
3059                         __func__, ret);
3060                 goto out;
3061         }
3062
3063         pmc_disable_bus_ctrl(tegra);
3064
3065         tegra->hc_in_elpg = false;
3066         ret = xhci_resume(tegra->xhci, 0);
3067         if (ret) {
3068                 xhci_err(xhci, "%s: could not resume right %d\n",
3069                                 __func__, ret);
3070                 goto out;
3071         }
3072
3073         update_remote_wakeup_ports(tegra);
3074
3075         if (tegra->hs_wake_event)
3076                 tegra->hs_wake_event = false;
3077
3078         if (tegra->host_resume_req)
3079                 tegra->host_resume_req = false;
3080
3081         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
3082                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
3083
3084         tegra->host_pwr_gated = false;
3085 out:
3086         return ret;
3087 }
3088
3089 static void host_partition_elpg_exit_work(struct work_struct *work)
3090 {
3091         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3092                 host_elpg_exit_work);
3093
3094         mutex_lock(&tegra->sync_lock);
3095         tegra_xhci_host_partition_elpg_exit(tegra);
3096         mutex_unlock(&tegra->sync_lock);
3097 }
3098
3099 /* Mailbox handling function. This function handles requests
3100  * from firmware and communicates with clock and powergating
3101  * module to alter clock rates and to power gate/ungate xusb
3102  * partitions.
3103  *
3104  * Following is the structure of mailbox messages.
3105  * bit 31:28 - msg type
3106  * bits 27:0 - mbox data
3107  * FIXME:  Check if we can just call clock functions like below
3108  * or should we schedule it for calling later ?
3109  */
3110
3111 static void
3112 tegra_xhci_process_mbox_message(struct work_struct *work)
3113 {
3114         u32 sw_resp = 0, cmd, data_in, fw_msg;
3115         int ret = 0;
3116         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3117                                         mbox_work);
3118         struct xhci_hcd *xhci = tegra->xhci;
3119         int pad, port;
3120         unsigned long ports;
3121
3122         mutex_lock(&tegra->mbox_lock);
3123
3124         /* get the mbox message from firmware */
3125         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
3126
3127         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3128         if (data_in) {
3129                 dev_warn(&tegra->pdev->dev, "%s data_in 0x%x\n",
3130                         __func__, data_in);
3131                 mutex_unlock(&tegra->mbox_lock);
3132                 return;
3133         }
3134
3135         /* get cmd type and cmd data */
3136         tegra->cmd_type = (fw_msg >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
3137         tegra->cmd_data = (fw_msg >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
3138
3139         /* decode the message and make appropriate requests to
3140          * clock or powergating module.
3141          */
3142
3143         switch (tegra->cmd_type) {
3144         case MBOX_CMD_INC_FALC_CLOCK:
3145         case MBOX_CMD_DEC_FALC_CLOCK:
3146                 ret = tegra_xusb_request_clk_rate(
3147                                 tegra,
3148                                 tegra->falc_clk,
3149                                 tegra->cmd_data,
3150                                 &sw_resp);
3151                 if (ret)
3152                         xhci_err(xhci, "%s: could not set required falc rate\n",
3153                                 __func__);
3154                 goto send_sw_response;
3155         case MBOX_CMD_INC_SSPI_CLOCK:
3156         case MBOX_CMD_DEC_SSPI_CLOCK:
3157                 ret = tegra_xusb_request_clk_rate(
3158                                 tegra,
3159                                 tegra->ss_src_clk,
3160                                 tegra->cmd_data,
3161                                 &sw_resp);
3162                 if (ret)
3163                         xhci_err(xhci, "%s: could not set required ss rate.\n",
3164                                 __func__);
3165                 goto send_sw_response;
3166
3167         case MBOX_CMD_SET_BW:
3168                 /* fw sends BW request in MByte/sec */
3169                 mutex_lock(&tegra->sync_lock);
3170                 tegra_xusb_set_bw(tegra, tegra->cmd_data << 10);
3171                 mutex_unlock(&tegra->sync_lock);
3172                 break;
3173
3174         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
3175                 tegra_xhci_save_dfe_context(tegra, tegra->cmd_data);
3176                 tegra_xhci_save_ctle_context(tegra, tegra->cmd_data);
3177                 sw_resp = CMD_DATA(tegra->cmd_data) | CMD_TYPE(MBOX_CMD_ACK);
3178                 goto send_sw_response;
3179
3180         case MBOX_CMD_STAR_HSIC_IDLE:
3181                 ports = tegra->cmd_data;
3182                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3183                         pad = port_to_hsic_pad(port - 1);
3184                         mutex_lock(&tegra->sync_lock);
3185                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
3186                         mutex_unlock(&tegra->sync_lock);
3187                         if (ret)
3188                                 break;
3189                 }
3190
3191                 sw_resp = CMD_DATA(tegra->cmd_data);
3192                 if (!ret)
3193                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3194                 else
3195                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3196
3197                 goto send_sw_response;
3198
3199         case MBOX_CMD_STOP_HSIC_IDLE:
3200                 ports = tegra->cmd_data;
3201                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3202                         pad = port_to_hsic_pad(port - 1);
3203                         mutex_lock(&tegra->sync_lock);
3204                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_DISABLE);
3205                         mutex_unlock(&tegra->sync_lock);
3206                         if (ret)
3207                                 break;
3208                 }
3209
3210                 sw_resp = CMD_DATA(tegra->cmd_data);
3211                 if (!ret)
3212                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3213                 else
3214                         sw_resp |= CMD_TYPE(MBOX_CMD_NACK);
3215                 goto send_sw_response;
3216
3217         case MBOX_CMD_ACK:
3218                 xhci_dbg(xhci, "%s firmware responds with ACK\n", __func__);
3219                 break;
3220         case MBOX_CMD_NACK:
3221                 xhci_warn(xhci, "%s firmware responds with NACK\n", __func__);
3222                 break;
3223         default:
3224                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
3225                                 __func__, tegra->cmd_type);
3226         }
3227
3228         /* clear MBOX_SMI_INT_EN bit */
3229         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3230         cmd &= ~MBOX_SMI_INT_EN;
3231         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3232
3233         /* clear mailbox ownership */
3234         writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
3235
3236         mutex_unlock(&tegra->mbox_lock);
3237         return;
3238
3239 send_sw_response:
3240         if (((sw_resp >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK) == MBOX_CMD_NACK)
3241                 xhci_err(xhci, "%s respond fw message 0x%x with NAK\n",
3242                                 __func__, fw_msg);
3243
3244         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3245         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3246         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
3247         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3248
3249         mutex_unlock(&tegra->mbox_lock);
3250 }
3251
3252 static irqreturn_t pmc_usb_phy_wake_isr(int irq, void *data)
3253 {
3254         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) data;
3255         struct xhci_hcd *xhci = tegra->xhci;
3256
3257         xhci_dbg(xhci, "%s irq %d", __func__, irq);
3258         return IRQ_HANDLED;
3259 }
3260
3261 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
3262 {
3263         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3264         struct xhci_hcd *xhci = tegra->xhci;
3265         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3266         u32 elpg_program0 = 0;
3267
3268         spin_lock(&tegra->lock);
3269
3270         tegra->last_jiffies = jiffies;
3271
3272         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
3273         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
3274
3275         /* Clear the interrupt cause. We already read the intr status. */
3276         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3277         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3278
3279         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
3280         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
3281                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
3282         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
3283                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
3284         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
3285                 __func__,
3286                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad0_ctl0_0));
3287         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
3288                 __func__,
3289                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad1_ctl0_0));
3290         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
3291                 __func__,
3292                 readl(tegra->padctl_base + padregs->usb2_bchrg_bias_pad_0));
3293
3294         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
3295                 tegra->ss_wake_event = true;
3296         else if (elpg_program0 & (USB2_PORT0_WAKEUP_EVENT |
3297                         USB2_PORT1_WAKEUP_EVENT |
3298                         USB2_PORT2_WAKEUP_EVENT |
3299                         USB2_HSIC_PORT0_WAKEUP_EVENT |
3300                         USB2_HSIC_PORT1_WAKEUP_EVENT))
3301                 tegra->hs_wake_event = true;
3302
3303         if (tegra->ss_wake_event || tegra->hs_wake_event) {
3304                 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
3305                         xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
3306                         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3307                 } else if (tegra->ss_pwr_gated
3308                                 && tegra->host_pwr_gated) {
3309                         xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
3310                                 __func__);
3311                         schedule_work(&tegra->host_elpg_exit_work);
3312                 }
3313         } else {
3314                 xhci_err(xhci, "error: wake due to no hs/ss event\n");
3315                 tegra_usb_pad_reg_write(padregs->elpg_program_0, 0xffffffff);
3316         }
3317         spin_unlock(&tegra->lock);
3318         return IRQ_HANDLED;
3319 }
3320
3321 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
3322 {
3323         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3324         u32 temp;
3325
3326         spin_lock(&tegra->lock);
3327
3328         /* clear the mbox intr status 1st thing. Other
3329          * bits are W1C bits, so just write to SMI bit.
3330          */
3331
3332         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3333
3334         /* write 1 to clear SMI INTR en bit ( bit 3 ) */
3335         temp = MBOX_SMI_INTR_EN;
3336         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3337
3338         schedule_work(&tegra->mbox_work);
3339
3340         spin_unlock(&tegra->lock);
3341         return IRQ_HANDLED;
3342 }
3343
3344 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
3345 {
3346         /*
3347          * As of now platform drivers don't provide MSI support so we ensure
3348          * here that the generic code does not try to make a pci_dev from our
3349          * dev struct in order to setup MSI
3350          */
3351         xhci->quirks |= XHCI_PLAT;
3352         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
3353 }
3354
3355 /* called during probe() after chip reset completes */
3356 static int xhci_plat_setup(struct usb_hcd *hcd)
3357 {
3358         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
3359 }
3360
3361 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
3362         const char *name, void __iomem **region)
3363 {
3364         struct resource *res;
3365         void __iomem *mem;
3366
3367         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
3368         if (!res) {
3369                 dev_err(&pdev->dev, "memory resource %s doesn't exist\n", name);
3370                 return -ENODEV;
3371         }
3372
3373         mem = devm_request_and_ioremap(&pdev->dev, res);
3374         if (!mem) {
3375                 dev_err(&pdev->dev, "failed to ioremap for %s\n", name);
3376                 return -EFAULT;
3377         }
3378         *region = mem;
3379
3380         return 0;
3381 }
3382
3383 static int tegra_xhci_request_irq(struct platform_device *pdev,
3384         const char *rscname, irq_handler_t handler, unsigned long irqflags,
3385         const char *devname, int *irq_no)
3386 {
3387         int ret;
3388         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3389         struct resource *res;
3390
3391         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, rscname);
3392         if (!res) {
3393                 dev_err(&pdev->dev, "irq resource %s doesn't exist\n", rscname);
3394                 return -ENODEV;
3395         }
3396
3397         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
3398                         devname, tegra);
3399         if (ret != 0) {
3400                 dev_err(&pdev->dev,
3401                         "failed to request_irq for %s (irq %d), error = %d\n",
3402                         devname, res->start, ret);
3403                 return ret;
3404         }
3405         *irq_no = res->start;
3406
3407         return 0;
3408 }
3409
3410 #ifdef CONFIG_PM
3411
3412 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
3413 {
3414         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3415         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3416         int err = 0;
3417         unsigned long flags;
3418
3419         mutex_lock(&tegra->sync_lock);
3420
3421         if (xhci->shared_hcd == hcd) {
3422                 tegra->usb3_rh_suspend = true;
3423                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3424         } else if (xhci->main_hcd == hcd) {
3425                 tegra->usb2_rh_suspend = true;
3426                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3427         }
3428
3429         WARN_ON(tegra->hc_in_elpg);
3430
3431         /* suspend xhci bus. This will also set remote mask */
3432         err = xhci_bus_suspend(hcd);
3433         if (err) {
3434                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
3435                                 __func__, err);
3436                 goto xhci_bus_suspend_failed;
3437         }
3438
3439         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
3440                 goto done; /* one of the root hubs is still working */
3441
3442         spin_lock_irqsave(&tegra->lock, flags);
3443         tegra->hc_in_elpg = true;
3444         spin_unlock_irqrestore(&tegra->lock, flags);
3445
3446         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3447
3448         /* save xhci spec ctx. Already done by xhci_suspend */
3449         err = xhci_suspend(tegra->xhci);
3450         if (err) {
3451                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
3452                 goto xhci_suspend_failed;
3453         }
3454
3455         /* Powergate host. Include ss power gate if not already done */
3456         err = tegra_xhci_host_elpg_entry(tegra);
3457         if (err) {
3458                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
3459                                 __func__, err);
3460                 goto tegra_xhci_host_elpg_entry_failed;
3461         }
3462
3463         /* At this point,ensure ss/hs intr enables are always on */
3464         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
3465         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
3466
3467         /* In ELPG, firmware log context is gone. Rewind shared log buffer. */
3468         if (fw_log_wait_empty_timeout(tegra, 100))
3469                 xhci_warn(xhci, "%s still has logs\n", __func__);
3470         tegra->log.dequeue = tegra->log.virt_addr;
3471         tegra->log.seq = 0;
3472
3473 done:
3474         /* pads are disabled only if usb2 root hub in xusb is idle */
3475         /* pads will actually be disabled only when all usb2 ports are idle */
3476         if (xhci->main_hcd == hcd) {
3477                 utmi_phy_pad_disable();
3478                 utmi_phy_iddq_override(true);
3479         }
3480         mutex_unlock(&tegra->sync_lock);
3481         return 0;
3482
3483 tegra_xhci_host_elpg_entry_failed:
3484
3485 xhci_suspend_failed:
3486         tegra->hc_in_elpg = false;
3487 xhci_bus_suspend_failed:
3488         if (xhci->shared_hcd == hcd)
3489                 tegra->usb3_rh_suspend = false;
3490         else if (xhci->main_hcd == hcd)
3491                 tegra->usb2_rh_suspend = false;
3492
3493         mutex_unlock(&tegra->sync_lock);
3494         return err;
3495 }
3496
3497 /* First, USB2HCD and then USB3HCD resume will be called */
3498 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
3499 {
3500         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3501         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3502         int err = 0;
3503
3504         mutex_lock(&tegra->sync_lock);
3505
3506         tegra->host_resume_req = true;
3507
3508         if (xhci->shared_hcd == hcd)
3509                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3510         else if (xhci->main_hcd == hcd)
3511                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3512
3513         /* pads are disabled only if usb2 root hub in xusb is idle */
3514         /* pads will actually be disabled only when all usb2 ports are idle */
3515         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
3516                 utmi_phy_pad_enable();
3517                 utmi_phy_iddq_override(false);
3518         }
3519         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
3520                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
3521                         tegra_xhci_host_partition_elpg_exit(tegra);
3522         }
3523
3524          /* handle remote wakeup before resuming bus */
3525         wait_remote_wakeup_ports(hcd);
3526
3527         err = xhci_bus_resume(hcd);
3528         if (err) {
3529                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
3530                                 __func__, err);
3531                 goto xhci_bus_resume_failed;
3532         }
3533
3534         if (xhci->shared_hcd == hcd)
3535                 tegra->usb3_rh_suspend = false;
3536         else if (xhci->main_hcd == hcd)
3537                 tegra->usb2_rh_suspend = false;
3538
3539         mutex_unlock(&tegra->sync_lock);
3540         return 0;
3541
3542 xhci_bus_resume_failed:
3543         /* TODO: reverse elpg? */
3544         mutex_unlock(&tegra->sync_lock);
3545         return err;
3546 }
3547 #endif
3548
3549 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
3550 {
3551         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3552         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3553         irqreturn_t iret = IRQ_HANDLED;
3554         u32 status;
3555
3556         spin_lock(&tegra->lock);
3557         if (tegra->hc_in_elpg) {
3558                 spin_lock(&xhci->lock);
3559                 if (HCD_HW_ACCESSIBLE(hcd)) {
3560                         status = xhci_readl(xhci, &xhci->op_regs->status);
3561                         status |= STS_EINT;
3562                         xhci_writel(xhci, status, &xhci->op_regs->status);
3563                 }
3564                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
3565                                 __func__);
3566                 schedule_work(&tegra->host_elpg_exit_work);
3567                 spin_unlock(&xhci->lock);
3568         } else
3569                 iret = xhci_irq(hcd);
3570         spin_unlock(&tegra->lock);
3571
3572         wake_up_interruptible(&tegra->log.intr_wait);
3573
3574         return iret;
3575 }
3576
3577
3578 static const struct hc_driver tegra_plat_xhci_driver = {
3579         .description =          "tegra-xhci",
3580         .product_desc =         "Nvidia xHCI Host Controller",
3581         .hcd_priv_size =        sizeof(struct xhci_hcd *),
3582
3583         /*
3584          * generic hardware linkage
3585          */
3586         .irq =                  tegra_xhci_irq,
3587         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
3588
3589         /*
3590          * basic lifecycle operations
3591          */
3592         .reset =                xhci_plat_setup,
3593         .start =                xhci_run,
3594         .stop =                 xhci_stop,
3595         .shutdown =             xhci_shutdown,
3596
3597         /*
3598          * managing i/o requests and associated device resources
3599          */
3600         .urb_enqueue =          xhci_urb_enqueue,
3601         .urb_dequeue =          xhci_urb_dequeue,
3602         .alloc_dev =            xhci_alloc_dev,
3603         .free_dev =             xhci_free_dev,
3604         .alloc_streams =        xhci_alloc_streams,
3605         .free_streams =         xhci_free_streams,
3606         .add_endpoint =         xhci_add_endpoint,
3607         .drop_endpoint =        xhci_drop_endpoint,
3608         .endpoint_reset =       xhci_endpoint_reset,
3609         .check_bandwidth =      xhci_check_bandwidth,
3610         .reset_bandwidth =      xhci_reset_bandwidth,
3611         .address_device =       xhci_address_device,
3612         .update_hub_device =    xhci_update_hub_device,
3613         .reset_device =         xhci_discover_or_reset_device,
3614
3615         /*
3616          * scheduling support
3617          */
3618         .get_frame_number =     xhci_get_frame,
3619
3620         /* Root hub support */
3621         .hub_control =          xhci_hub_control,
3622         .hub_status_data =      xhci_hub_status_data,
3623
3624 #ifdef CONFIG_PM
3625         .bus_suspend =          tegra_xhci_bus_suspend,
3626         .bus_resume =           tegra_xhci_bus_resume,
3627 #endif
3628 };
3629
3630 #ifdef CONFIG_PM
3631 static int
3632 tegra_xhci_suspend(struct platform_device *pdev,
3633                                                 pm_message_t state)
3634 {
3635         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3636         struct xhci_hcd *xhci = tegra->xhci;
3637
3638         int ret = 0;
3639
3640         mutex_lock(&tegra->sync_lock);
3641         if (!tegra->init_done) {
3642                 xhci_warn(xhci, "%s: xhci probe not done\n",
3643                                 __func__);
3644                 mutex_unlock(&tegra->sync_lock);
3645                 return -EBUSY;
3646         }
3647         if (!tegra->hc_in_elpg) {
3648                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
3649                                 __func__);
3650                 mutex_unlock(&tegra->sync_lock);
3651                 return -EBUSY;
3652         }
3653         mutex_unlock(&tegra->sync_lock);
3654
3655         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3656         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3657
3658         /* enable_irq_wake for ss ports */
3659         ret = enable_irq_wake(tegra->padctl_irq);
3660         if (ret < 0) {
3661                 xhci_err(xhci,
3662                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
3663                 __func__, tegra->padctl_irq, ret);
3664         }
3665
3666         /* enable_irq_wake for utmip/uhisc wakes */
3667         ret = enable_irq_wake(tegra->usb3_irq);
3668         if (ret < 0) {
3669                 xhci_err(xhci,
3670                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3671                 __func__, tegra->usb3_irq, ret);
3672         }
3673
3674         /* enable_irq_wake for utmip/uhisc wakes */
3675         ret = enable_irq_wake(tegra->usb2_irq);
3676         if (ret < 0) {
3677                 xhci_err(xhci,
3678                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3679                 __func__, tegra->usb2_irq, ret);
3680         }
3681
3682         regulator_disable(tegra->xusb_s1p8v_reg);
3683         regulator_disable(tegra->xusb_s1p05v_reg);
3684         tegra_usb2_clocks_deinit(tegra);
3685
3686         return ret;
3687 }
3688
3689 static int
3690 tegra_xhci_resume(struct platform_device *pdev)
3691 {
3692         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3693         struct xhci_hcd *xhci = tegra->xhci;
3694
3695         dev_dbg(&pdev->dev, "%s\n", __func__);
3696
3697         mutex_lock(&tegra->sync_lock);
3698         if (!tegra->init_done) {
3699                 xhci_warn(xhci, "%s: xhci probe not done\n",
3700                                 __func__);
3701                 mutex_unlock(&tegra->sync_lock);
3702                 return -EBUSY;
3703         }
3704         mutex_unlock(&tegra->sync_lock);
3705
3706         tegra->last_jiffies = jiffies;
3707
3708         disable_irq_wake(tegra->padctl_irq);
3709         disable_irq_wake(tegra->usb3_irq);
3710         disable_irq_wake(tegra->usb2_irq);
3711         tegra->lp0_exit = true;
3712
3713         regulator_enable(tegra->xusb_s1p05v_reg);
3714         regulator_enable(tegra->xusb_s1p8v_reg);
3715         tegra_usb2_clocks_init(tegra);
3716
3717         return 0;
3718 }
3719 #endif
3720
3721
3722 static int init_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3723 {
3724         struct platform_device *pdev = tegra->pdev;
3725         void __iomem *fw_mmio_base;
3726         phys_addr_t fw_mem_phy_addr;
3727         size_t fw_size;
3728         dma_addr_t fw_dma;
3729 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3730         int ret;
3731         DEFINE_DMA_ATTRS(attrs);
3732 #endif
3733
3734         /* bootloader saved firmware memory address in PMC SCRATCH34 register */
3735         fw_mem_phy_addr = tegra_usb_pmc_reg_read(PMC_SCRATCH34);
3736
3737         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3738                         fw_mem_phy_addr, sizeof(struct cfgtbl));
3739
3740         if (!fw_mmio_base) {
3741                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3742                                         fw_mem_phy_addr);
3743                         return -ENOMEM;
3744         }
3745
3746         fw_size = ioread32(fw_mmio_base + FW_SIZE_OFFSET);
3747         devm_iounmap(&pdev->dev, fw_mmio_base);
3748
3749         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3750                         fw_mem_phy_addr, fw_size);
3751         if (!fw_mmio_base) {
3752                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3753                                         fw_mem_phy_addr);
3754                         return -ENOMEM;
3755         }
3756
3757         dev_info(&pdev->dev, "Firmware Memory: phy 0x%x mapped 0x%p (%d Bytes)\n",
3758                         (u32) fw_mem_phy_addr, fw_mmio_base, fw_size);
3759
3760 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3761         dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
3762         fw_dma = dma_map_linear_attrs(&pdev->dev, fw_mem_phy_addr, fw_size,
3763                         DMA_TO_DEVICE, &attrs);
3764
3765         if (fw_dma == DMA_ERROR_CODE) {
3766                 dev_err(&pdev->dev, "%s: dma_map_linear failed\n",
3767                                 __func__);
3768                 ret = -ENOMEM;
3769                 goto error_iounmap;
3770         }
3771 #else
3772         fw_dma = fw_mem_phy_addr;
3773 #endif
3774         dev_info(&pdev->dev, "Firmware DMA Memory: dma 0x%p (%d Bytes)\n",
3775                         (void *) fw_dma, fw_size);
3776
3777         /* all set and ready to go */
3778         tegra->firmware.data = fw_mmio_base;
3779         tegra->firmware.dma = fw_dma;
3780         tegra->firmware.size = fw_size;
3781
3782         return 0;
3783
3784 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3785 error_iounmap:
3786         devm_iounmap(&pdev->dev, fw_mmio_base);
3787         return ret;
3788 #endif
3789 }
3790
3791 static void deinit_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3792 {
3793         struct platform_device *pdev = tegra->pdev;
3794         void __iomem *fw_mmio_base = tegra->firmware.data;
3795
3796 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3797         dma_unmap_single(&pdev->dev, tegra->firmware.dma,
3798                         tegra->firmware.size, DMA_TO_DEVICE);
3799 #endif
3800         devm_iounmap(&pdev->dev, fw_mmio_base);
3801
3802         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
3803 }
3804
3805 static int init_filesystem_firmware(struct tegra_xhci_hcd *tegra)
3806 {
3807         struct platform_device *pdev = tegra->pdev;
3808         int ret;
3809
3810         ret = request_firmware_nowait(THIS_MODULE, true, firmware_file,
3811                 &pdev->dev, GFP_KERNEL, tegra, init_filesystem_firmware_done);
3812         if (ret < 0) {
3813                 dev_err(&pdev->dev, "request_firmware failed %d\n", ret);
3814                 return ret;
3815         }
3816
3817         return ret;
3818 }
3819
3820 static void init_filesystem_firmware_done(const struct firmware *fw,
3821                                         void *context)
3822 {
3823         struct tegra_xhci_hcd *tegra = context;
3824         struct platform_device *pdev = tegra->pdev;
3825         struct cfgtbl *fw_cfgtbl;
3826         size_t fw_size;
3827         void *fw_data;
3828         dma_addr_t fw_dma;
3829         int ret;
3830
3831         mutex_lock(&tegra->sync_lock);
3832
3833         if (fw == NULL) {
3834                 dev_err(&pdev->dev,
3835                         "failed to init firmware from filesystem: %s\n",
3836                         firmware_file);
3837                 goto err_firmware_done;
3838         }
3839
3840         fw_cfgtbl = (struct cfgtbl *) fw->data;
3841         fw_size = fw_cfgtbl->fwimg_len;
3842         dev_info(&pdev->dev, "Firmware File: %s (%d Bytes)\n",
3843                         firmware_file, fw_size);
3844
3845         fw_data = dma_alloc_coherent(&pdev->dev, fw_size,
3846                         &fw_dma, GFP_KERNEL);
3847         if (!fw_data) {
3848                 dev_err(&pdev->dev, "%s: dma_alloc_coherent failed\n",
3849                         __func__);
3850                 goto err_firmware_done;
3851         }
3852
3853         memcpy(fw_data, fw->data, fw_size);
3854         dev_info(&pdev->dev,
3855                 "Firmware DMA Memory: dma 0x%p mapped 0x%p (%d Bytes)\n",
3856                 (void *) fw_dma, fw_data, fw_size);
3857
3858         /* all set and ready to go */
3859         tegra->firmware.data = fw_data;
3860         tegra->firmware.dma = fw_dma;
3861         tegra->firmware.size = fw_size;
3862
3863         ret = tegra_xhci_probe2(tegra);
3864         if (ret < 0) {
3865                 dev_err(&pdev->dev, "%s: failed to probe: %d\n", __func__, ret);
3866                 goto err_firmware_done;
3867         }
3868
3869         release_firmware(fw);
3870         mutex_unlock(&tegra->sync_lock);
3871         return;
3872
3873 err_firmware_done:
3874         release_firmware(fw);
3875         mutex_unlock(&tegra->sync_lock);
3876         tegra_xhci_remove(pdev);
3877 }
3878
3879 static void deinit_filesystem_firmware(struct tegra_xhci_hcd *tegra)
3880 {
3881         struct platform_device *pdev = tegra->pdev;
3882
3883         if (tegra->firmware.data) {
3884                 dma_free_coherent(&pdev->dev, tegra->firmware.size,
3885                         tegra->firmware.data, tegra->firmware.dma);
3886         }
3887
3888         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
3889 }
3890 static int init_firmware(struct tegra_xhci_hcd *tegra)
3891 {
3892         if (use_bootloader_firmware)
3893                 return init_bootloader_firmware(tegra);
3894         else
3895                 return init_filesystem_firmware(tegra);
3896 }
3897
3898 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
3899 {
3900         if (use_bootloader_firmware)
3901                 return deinit_bootloader_firmware(tegra);
3902         else
3903                 return deinit_filesystem_firmware(tegra);
3904 }
3905
3906 static int tegra_enable_xusb_clk(struct tegra_xhci_hcd *tegra,
3907                 struct platform_device *pdev)
3908 {
3909         int err = 0;
3910         /* enable ss clock */
3911         err = clk_enable(tegra->host_clk);
3912         if (err) {
3913                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
3914                 goto enable_host_clk_failed;
3915         }
3916
3917         err = clk_enable(tegra->ss_clk);
3918         if (err) {
3919                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
3920                 goto eanble_ss_clk_failed;
3921         }
3922
3923         err = clk_enable(tegra->emc_clk);
3924         if (err) {
3925                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
3926                 goto eanble_emc_clk_failed;
3927         }
3928
3929         return 0;
3930
3931 eanble_emc_clk_failed:
3932         clk_disable(tegra->ss_clk);
3933
3934 eanble_ss_clk_failed:
3935         clk_disable(tegra->host_clk);
3936
3937 enable_host_clk_failed:
3938         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
3939                 clk_disable(tegra->pll_re_vco_clk);
3940         return err;
3941 }
3942
3943 static struct tegra_xusb_padctl_regs t114_padregs_offset = {
3944         .boot_media_0                   = 0x0,
3945         .usb2_pad_mux_0                 = 0x4,
3946         .usb2_port_cap_0                = 0x8,
3947         .snps_oc_map_0                  = 0xc,
3948         .usb2_oc_map_0                  = 0x10,
3949         .ss_port_map_0                  = 0x14,
3950         .oc_det_0                       = 0x18,
3951         .elpg_program_0                 = 0x1c,
3952         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3953         .usb2_bchrg_otgpad0_ctl1_0      = 0xffff,
3954         .usb2_bchrg_otgpad1_ctl0_0      = 0x24,
3955         .usb2_bchrg_otgpad1_ctl1_0      = 0xffff,
3956         .usb2_bchrg_otgpad2_ctl0_0      = 0xffff,
3957         .usb2_bchrg_otgpad2_ctl1_0      = 0xffff,
3958         .usb2_bchrg_bias_pad_0          = 0x28,
3959         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
3960         .iophy_pll_p0_ctl1_0            = 0x30,
3961         .iophy_pll_p0_ctl2_0            = 0x34,
3962         .iophy_pll_p0_ctl3_0            = 0x38,
3963         .iophy_pll_p0_ctl4_0            = 0x3c,
3964         .iophy_usb3_pad0_ctl1_0         = 0x40,
3965         .iophy_usb3_pad1_ctl1_0         = 0x44,
3966         .iophy_usb3_pad0_ctl2_0         = 0x48,
3967         .iophy_usb3_pad1_ctl2_0         = 0x4c,
3968         .iophy_usb3_pad0_ctl3_0         = 0x50,
3969         .iophy_usb3_pad1_ctl3_0         = 0x54,
3970         .iophy_usb3_pad0_ctl4_0         = 0x58,
3971         .iophy_usb3_pad1_ctl4_0         = 0x5c,
3972         .iophy_misc_pad_p0_ctl1_0       = 0x60,
3973         .iophy_misc_pad_p1_ctl1_0       = 0x64,
3974         .iophy_misc_pad_p0_ctl2_0       = 0x68,
3975         .iophy_misc_pad_p1_ctl2_0       = 0x6c,
3976         .iophy_misc_pad_p0_ctl3_0       = 0x70,
3977         .iophy_misc_pad_p1_ctl3_0       = 0x74,
3978         .iophy_misc_pad_p0_ctl4_0       = 0x78,
3979         .iophy_misc_pad_p1_ctl4_0       = 0x7c,
3980         .iophy_misc_pad_p0_ctl5_0       = 0x80,
3981         .iophy_misc_pad_p1_ctl5_0       = 0x84,
3982         .iophy_misc_pad_p0_ctl6_0       = 0x88,
3983         .iophy_misc_pad_p1_ctl6_0       = 0x8c,
3984         .usb2_otg_pad0_ctl0_0           = 0x90,
3985         .usb2_otg_pad1_ctl0_0           = 0x94,
3986         .usb2_otg_pad2_ctl0_0           = 0xffff,
3987         .usb2_otg_pad0_ctl1_0           = 0x98,
3988         .usb2_otg_pad1_ctl1_0           = 0x9c,
3989         .usb2_otg_pad2_ctl1_0           = 0xffff,
3990         .usb2_bias_pad_ctl0_0           = 0xa0,
3991         .usb2_bias_pad_ctl1_0           = 0xa4,
3992         .usb2_hsic_pad0_ctl0_0          = 0xa8,
3993         .usb2_hsic_pad1_ctl0_0          = 0xac,
3994         .usb2_hsic_pad0_ctl1_0          = 0xb0,
3995         .usb2_hsic_pad1_ctl1_0          = 0xb4,
3996         .usb2_hsic_pad0_ctl2_0          = 0xb8,
3997         .usb2_hsic_pad1_ctl2_0          = 0xbc,
3998         .ulpi_link_trim_ctl0            = 0xc0,
3999         .ulpi_null_clk_trim_ctl0        = 0xc4,
4000         .hsic_strb_trim_ctl0            = 0xc8,
4001         .wake_ctl0                      = 0xcc,
4002         .pm_spare0                      = 0xd0,
4003         .iophy_misc_pad_p2_ctl1_0       = 0xffff,
4004         .iophy_misc_pad_p3_ctl1_0       = 0xffff,
4005         .iophy_misc_pad_p4_ctl1_0       = 0xffff,
4006         .iophy_misc_pad_p2_ctl2_0       = 0xffff,
4007         .iophy_misc_pad_p3_ctl2_0       = 0xffff,
4008         .iophy_misc_pad_p4_ctl2_0       = 0xffff,
4009         .iophy_misc_pad_p2_ctl3_0       = 0xffff,
4010         .iophy_misc_pad_p3_ctl3_0       = 0xffff,
4011         .iophy_misc_pad_p4_ctl3_0       = 0xffff,
4012         .iophy_misc_pad_p2_ctl4_0       = 0xffff,
4013         .iophy_misc_pad_p3_ctl4_0       = 0xffff,
4014         .iophy_misc_pad_p4_ctl4_0       = 0xffff,
4015         .iophy_misc_pad_p2_ctl5_0       = 0xffff,
4016         .iophy_misc_pad_p3_ctl5_0       = 0xffff,
4017         .iophy_misc_pad_p4_ctl5_0       = 0xffff,
4018         .iophy_misc_pad_p2_ctl6_0       = 0xffff,
4019         .iophy_misc_pad_p3_ctl6_0       = 0xffff,
4020         .iophy_misc_pad_p4_ctl6_0       = 0xffff,
4021         .usb3_pad_mux_0                 = 0xffff,
4022         .iophy_pll_s0_ctl1_0            = 0xffff,
4023         .iophy_pll_s0_ctl2_0            = 0xffff,
4024         .iophy_pll_s0_ctl3_0            = 0xffff,
4025         .iophy_pll_s0_ctl4_0            = 0xffff,
4026         .iophy_misc_pad_s0_ctl1_0       = 0xffff,
4027         .iophy_misc_pad_s0_ctl2_0       = 0xffff,
4028         .iophy_misc_pad_s0_ctl3_0       = 0xffff,
4029         .iophy_misc_pad_s0_ctl4_0       = 0xffff,
4030         .iophy_misc_pad_s0_ctl5_0       = 0xffff,
4031         .iophy_misc_pad_s0_ctl6_0       = 0xffff,
4032 };
4033
4034 static struct tegra_xusb_padctl_regs t124_padregs_offset = {
4035         .boot_media_0                   = 0x0,
4036         .usb2_pad_mux_0                 = 0x4,
4037         .usb2_port_cap_0                = 0x8,
4038         .snps_oc_map_0                  = 0xc,
4039         .usb2_oc_map_0                  = 0x10,
4040         .ss_port_map_0                  = 0x14,
4041         .oc_det_0                       = 0x18,
4042         .elpg_program_0                 = 0x1c,
4043         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
4044         .usb2_bchrg_otgpad0_ctl1_0      = 0x24,
4045         .usb2_bchrg_otgpad1_ctl0_0      = 0x28,
4046         .usb2_bchrg_otgpad1_ctl1_0      = 0x2c,
4047         .usb2_bchrg_otgpad2_ctl0_0      = 0x30,
4048         .usb2_bchrg_otgpad2_ctl1_0      = 0x34,
4049         .usb2_bchrg_bias_pad_0          = 0x38,
4050         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
4051         .iophy_pll_p0_ctl1_0            = 0x40,
4052         .iophy_pll_p0_ctl2_0            = 0x44,
4053         .iophy_pll_p0_ctl3_0            = 0x48,
4054         .iophy_pll_p0_ctl4_0            = 0x4c,
4055         .iophy_usb3_pad0_ctl1_0         = 0x50,
4056         .iophy_usb3_pad1_ctl1_0         = 0x54,
4057         .iophy_usb3_pad0_ctl2_0         = 0x58,
4058         .iophy_usb3_pad1_ctl2_0         = 0x5c,
4059         .iophy_usb3_pad0_ctl3_0         = 0x60,
4060         .iophy_usb3_pad1_ctl3_0         = 0x64,
4061         .iophy_usb3_pad0_ctl4_0         = 0x68,
4062         .iophy_usb3_pad1_ctl4_0         = 0x6c,
4063         .iophy_misc_pad_p0_ctl1_0       = 0x70,
4064         .iophy_misc_pad_p1_ctl1_0       = 0x74,
4065         .iophy_misc_pad_p0_ctl2_0       = 0x78,
4066         .iophy_misc_pad_p1_ctl2_0       = 0x7c,
4067         .iophy_misc_pad_p0_ctl3_0       = 0x80,
4068         .iophy_misc_pad_p1_ctl3_0       = 0x84,
4069         .iophy_misc_pad_p0_ctl4_0       = 0x88,
4070         .iophy_misc_pad_p1_ctl4_0       = 0x8c,
4071         .iophy_misc_pad_p0_ctl5_0       = 0x90,
4072         .iophy_misc_pad_p1_ctl5_0       = 0x94,
4073         .iophy_misc_pad_p0_ctl6_0       = 0x98,
4074         .iophy_misc_pad_p1_ctl6_0       = 0x9c,
4075         .usb2_otg_pad0_ctl0_0           = 0xa0,
4076         .usb2_otg_pad1_ctl0_0           = 0xa4,
4077         .usb2_otg_pad2_ctl0_0           = 0xa8,
4078         .usb2_otg_pad0_ctl1_0           = 0xac,
4079         .usb2_otg_pad1_ctl1_0           = 0xb0,
4080         .usb2_otg_pad2_ctl1_0           = 0xb4,
4081         .usb2_bias_pad_ctl0_0           = 0xb8,
4082         .usb2_bias_pad_ctl1_0           = 0xbc,
4083         .usb2_hsic_pad0_ctl0_0          = 0xc0,
4084         .usb2_hsic_pad1_ctl0_0          = 0xc4,
4085         .usb2_hsic_pad0_ctl1_0          = 0xc8,
4086         .usb2_hsic_pad1_ctl1_0          = 0xcc,
4087         .usb2_hsic_pad0_ctl2_0          = 0xd0,
4088         .usb2_hsic_pad1_ctl2_0          = 0xd4,
4089         .ulpi_link_trim_ctl0            = 0xd8,
4090         .ulpi_null_clk_trim_ctl0        = 0xdc,
4091         .hsic_strb_trim_ctl0            = 0xe0,
4092         .wake_ctl0                      = 0xe4,
4093         .pm_spare0                      = 0xe8,
4094         .iophy_misc_pad_p2_ctl1_0       = 0xec,
4095         .iophy_misc_pad_p3_ctl1_0       = 0xf0,
4096         .iophy_misc_pad_p4_ctl1_0       = 0xf4,
4097         .iophy_misc_pad_p2_ctl2_0       = 0xf8,
4098         .iophy_misc_pad_p3_ctl2_0       = 0xfc,
4099         .iophy_misc_pad_p4_ctl2_0       = 0x100,
4100         .iophy_misc_pad_p2_ctl3_0       = 0x104,
4101         .iophy_misc_pad_p3_ctl3_0       = 0x108,
4102         .iophy_misc_pad_p4_ctl3_0       = 0x10c,
4103         .iophy_misc_pad_p2_ctl4_0       = 0x110,
4104         .iophy_misc_pad_p3_ctl4_0       = 0x114,
4105         .iophy_misc_pad_p4_ctl4_0       = 0x118,
4106         .iophy_misc_pad_p2_ctl5_0       = 0x11c,
4107         .iophy_misc_pad_p3_ctl5_0       = 0x120,
4108         .iophy_misc_pad_p4_ctl5_0       = 0x124,
4109         .iophy_misc_pad_p2_ctl6_0       = 0x128,
4110         .iophy_misc_pad_p3_ctl6_0       = 0x12c,
4111         .iophy_misc_pad_p4_ctl6_0       = 0x130,
4112         .usb3_pad_mux_0                 = 0x134,
4113         .iophy_pll_s0_ctl1_0            = 0x138,
4114         .iophy_pll_s0_ctl2_0            = 0x13c,
4115         .iophy_pll_s0_ctl3_0            = 0x140,
4116         .iophy_pll_s0_ctl4_0            = 0x144,
4117         .iophy_misc_pad_s0_ctl1_0       = 0x148,
4118         .iophy_misc_pad_s0_ctl2_0       = 0x14c,
4119         .iophy_misc_pad_s0_ctl3_0       = 0x150,
4120         .iophy_misc_pad_s0_ctl4_0       = 0x154,
4121         .iophy_misc_pad_s0_ctl5_0       = 0x158,
4122         .iophy_misc_pad_s0_ctl6_0       = 0x15c,
4123 };
4124
4125 /* FIXME: using notifier to transfer control to host from suspend
4126  * for otg port when xhci is in elpg. Find  better alternative
4127  */
4128 static int tegra_xhci_otg_notify(struct notifier_block *nb,
4129                                    unsigned long event, void *unused)
4130 {
4131         struct tegra_xhci_hcd *tegra = container_of(nb,
4132                                         struct tegra_xhci_hcd, otgnb);
4133
4134         if ((event == USB_EVENT_ID))
4135                 if (tegra->hc_in_elpg) {
4136                         schedule_work(&tegra->host_elpg_exit_work);
4137                         tegra->host_resume_req = true;
4138         }
4139
4140         return NOTIFY_OK;
4141 }
4142
4143 /* TODO: we have to refine error handling in tegra_xhci_probe() */
4144 static int tegra_xhci_probe(struct platform_device *pdev)
4145 {
4146         struct tegra_xhci_hcd *tegra;
4147         struct resource *res;
4148         unsigned pad;
4149         u32 val;
4150         int ret;
4151
4152         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
4153
4154         if (usb_disabled())
4155                 return -ENODEV;
4156
4157         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
4158         if (!tegra) {
4159                 dev_err(&pdev->dev, "memory alloc failed\n");
4160                 return -ENOMEM;
4161         }
4162         mutex_init(&tegra->sync_lock);
4163         spin_lock_init(&tegra->lock);
4164         mutex_init(&tegra->mbox_lock);
4165
4166         tegra->init_done = false;
4167         tegra->pdev = pdev;
4168         tegra->pdata = dev_get_platdata(&pdev->dev);
4169         tegra->bdata = tegra->pdata->bdata;
4170         tegra->ss_pwr_gated = false;
4171         tegra->host_pwr_gated = false;
4172         tegra->hc_in_elpg = false;
4173         tegra->hs_wake_event = false;
4174         tegra->host_resume_req = false;
4175         tegra->lp0_exit = false;
4176
4177         ret = tegra_xhci_request_mem_region(pdev, "padctl",
4178                         &tegra->padctl_base);
4179         if (ret) {
4180                 dev_err(&pdev->dev, "failed to map padctl\n");
4181                 return ret;
4182         }
4183
4184         ret = tegra_xhci_request_mem_region(pdev, "fpci", &tegra->fpci_base);
4185         if (ret) {
4186                 dev_err(&pdev->dev, "failed to map fpci\n");
4187                 return ret;
4188         }
4189
4190         ret = tegra_xhci_request_mem_region(pdev, "ipfs", &tegra->ipfs_base);
4191         if (ret) {
4192                 dev_err(&pdev->dev, "failed to map ipfs\n");
4193                 return ret;
4194         }
4195
4196         ret = tegra_xusb_partitions_clk_init(tegra);
4197         if (ret) {
4198                 dev_err(&pdev->dev,
4199                         "failed to initialize xusb partitions clocks\n");
4200                 return ret;
4201         }
4202
4203         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) {
4204                 tegra->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
4205                 if (IS_ERR_OR_NULL(tegra->transceiver)) {
4206                         dev_err(&pdev->dev, "failed to get usb phy\n");
4207                         tegra->transceiver = NULL;
4208                 }
4209         }
4210
4211         /* Enable power rails to the PAD,VBUS
4212          * and pull-up voltage.Initialize the regulators
4213          */
4214         ret = tegra_xusb_regulator_init(tegra, pdev);
4215         if (ret) {
4216                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
4217                 goto err_deinit_xusb_partition_clk;
4218         }
4219
4220         /* Enable UTMIP, PLLU and PLLE */
4221         ret = tegra_usb2_clocks_init(tegra);
4222         if (ret) {
4223                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
4224                 goto err_deinit_tegra_xusb_regulator;
4225         }
4226
4227         /* tegra_unpowergate_partition also does partition reset deassert */
4228         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
4229         if (ret)
4230                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
4231
4232         /* tegra_unpowergate_partition also does partition reset deassert */
4233         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
4234         if (ret)
4235                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
4236
4237         ret = tegra_enable_xusb_clk(tegra, pdev);
4238         if (ret)
4239                 dev_err(&pdev->dev, "could not enable partition clock\n");
4240
4241         /* reset the pointer back to NULL. driver uses it */
4242         /* platform_set_drvdata(pdev, NULL); */
4243
4244         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "host");
4245         if (!res) {
4246                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
4247                 ret = -ENODEV;
4248                 goto err_deinit_usb2_clocks;
4249         }
4250         tegra->host_phy_base = res->start;
4251         tegra->host_phy_size = resource_size(res);
4252
4253         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
4254                                 res->start, resource_size(res));
4255         if (!tegra->host_phy_virt_base) {
4256                 dev_err(&pdev->dev, "error mapping host phy memory\n");
4257                 ret = -ENOMEM;
4258                 goto err_deinit_usb2_clocks;
4259         }
4260
4261         /* Setup IPFS access and BAR0 space */
4262         tegra_xhci_cfg(tegra);
4263
4264         val = readl(tegra->fpci_base + XUSB_CFG_0);
4265         tegra->device_id = (val >> 16) & 0xffff;
4266
4267         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
4268                 (XUSB_DEVICE_ID_T114 == tegra->device_id) ? "T114" : "T124+");
4269
4270         if (XUSB_DEVICE_ID_T114 == tegra->device_id) {
4271                 tegra->padregs = &t114_padregs_offset;
4272         } else if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
4273                 tegra->padregs = &t124_padregs_offset;
4274         } else {
4275                 dev_info(&pdev->dev, "XUSB device_id neither T114 nor T124!\n");
4276                 dev_info(&pdev->dev, "XUSB using T124 pad register offsets!\n");
4277                 tegra->padregs = &t124_padregs_offset;
4278         }
4279
4280         /* calculate rctrl_val and tctrl_val once at boot time */
4281         /* Issue is only applicable for T114 */
4282         if (XUSB_DEVICE_ID_T114 == tegra->device_id)
4283                 tegra_xhci_war_for_tctrl_rctrl(tegra);
4284
4285         for_each_enabled_hsic_pad(pad, tegra)
4286                 hsic_power_rail_enable(tegra);
4287
4288         /* Program the XUSB pads to take ownership of ports */
4289         tegra_xhci_padctl_portmap_and_caps(tegra);
4290
4291         /* Release XUSB wake logic state latching */
4292         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
4293         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
4294
4295         /* Deassert reset to XUSB host, ss, dev clocks */
4296         tegra_periph_reset_deassert(tegra->host_clk);
4297         tegra_periph_reset_deassert(tegra->ss_clk);
4298
4299         platform_set_drvdata(pdev, tegra);
4300         fw_log_init(tegra);
4301         ret = init_firmware(tegra);
4302         if (ret < 0) {
4303                 dev_err(&pdev->dev, "failed to init firmware\n");
4304                 ret = -ENODEV;
4305                 goto err_deinit_firmware_log;
4306         }
4307
4308         if (use_bootloader_firmware) {
4309                 ret = tegra_xhci_probe2(tegra);
4310                 if (ret < 0) {
4311                         ret = -ENODEV;
4312                         goto err_deinit_firmware;
4313                 }
4314         }
4315
4316         return 0;
4317
4318 err_deinit_firmware:
4319         deinit_firmware(tegra);
4320 err_deinit_firmware_log:
4321         fw_log_deinit(tegra);
4322 err_deinit_usb2_clocks:
4323         tegra_usb2_clocks_deinit(tegra);
4324 err_deinit_tegra_xusb_regulator:
4325         tegra_xusb_regulator_deinit(tegra);
4326 err_deinit_xusb_partition_clk:
4327         if (tegra->transceiver)
4328                 usb_unregister_notifier(tegra->transceiver, &tegra->otgnb);
4329
4330         tegra_xusb_partitions_clk_deinit(tegra);
4331
4332         return ret;
4333 }
4334
4335 static int tegra_xhci_probe2(struct tegra_xhci_hcd *tegra)
4336 {
4337         struct platform_device *pdev = tegra->pdev;
4338         const struct hc_driver *driver;
4339         int ret;
4340         struct resource *res;
4341         int irq;
4342         struct xhci_hcd *xhci;
4343         struct usb_hcd  *hcd;
4344         unsigned port;
4345
4346
4347         ret = load_firmware(tegra, true /* do reset ARU */);
4348         if (ret < 0) {
4349                 dev_err(&pdev->dev, "failed to load firmware\n");
4350                 return -ENODEV;
4351         }
4352         pmc_init(tegra);
4353
4354         device_init_wakeup(&pdev->dev, 1);
4355         driver = &tegra_plat_xhci_driver;
4356
4357         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
4358         if (!hcd) {
4359                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
4360                 return -ENOMEM;
4361         }
4362
4363         ret = tegra_xhci_request_mem_region(pdev, "host", &hcd->regs);
4364         if (ret) {
4365                 dev_err(&pdev->dev, "failed to map host\n");
4366                 goto err_put_usb2_hcd;
4367         }
4368         hcd->rsrc_start = tegra->host_phy_base;
4369         hcd->rsrc_len = tegra->host_phy_size;
4370
4371         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "host");
4372         if (!res) {
4373                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
4374                 ret = -ENODEV;
4375                 goto err_put_usb2_hcd;
4376         }
4377
4378         irq = res->start;
4379         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
4380         if (ret) {
4381                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
4382                 goto err_put_usb2_hcd;
4383         }
4384
4385         /* USB 2.0 roothub is stored in the platform_device now. */
4386         hcd = dev_get_drvdata(&pdev->dev);
4387         xhci = hcd_to_xhci(hcd);
4388         tegra->xhci = xhci;
4389         platform_set_drvdata(pdev, tegra);
4390
4391         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) {
4392                 if (!IS_ERR_OR_NULL(tegra->transceiver)) {
4393                         otg_set_host(tegra->transceiver->otg, &hcd->self);
4394                         tegra->otgnb.notifier_call = tegra_xhci_otg_notify;
4395                         usb_register_notifier(tegra->transceiver,
4396                                 &tegra->otgnb);
4397                 }
4398         }
4399
4400         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
4401                                                 dev_name(&pdev->dev), hcd);
4402         if (!xhci->shared_hcd) {
4403                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
4404                 ret = -ENOMEM;
4405                 goto err_remove_usb2_hcd;
4406         }
4407
4408         /*
4409          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
4410          * is called by usb_add_hcd().
4411          */
4412         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
4413
4414         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
4415         if (ret) {
4416                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
4417                 goto err_put_usb3_hcd;
4418         }
4419
4420         device_init_wakeup(&hcd->self.root_hub->dev, 1);
4421         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
4422
4423         /* do mailbox related initializations */
4424         tegra->mbox_owner = 0xffff;
4425         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
4426
4427         tegra_xhci_enable_fw_message(tegra);
4428
4429         /* do ss partition elpg exit related initialization */
4430         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
4431
4432         /* do host partition elpg exit related initialization */
4433         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
4434
4435         /* Register interrupt handler for SMI line to handle mailbox
4436          * interrupt from firmware
4437          */
4438         ret = tegra_xhci_request_irq(pdev, "host-smi", tegra_xhci_smi_irq,
4439                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
4440         if (ret != 0)
4441                 goto err_remove_usb3_hcd;
4442
4443         /* Register interrupt handler for PADCTRL line to
4444          * handle wake on connect irqs interrupt from
4445          * firmware
4446          */
4447         ret = tegra_xhci_request_irq(pdev, "padctl", tegra_xhci_padctl_irq,
4448                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
4449                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
4450         if (ret != 0)
4451                 goto err_remove_usb3_hcd;
4452
4453         ret = tegra_xhci_request_irq(pdev, "usb2", pmc_usb_phy_wake_isr,
4454                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4455                 &tegra->usb2_irq);
4456         if (ret != 0)
4457                 goto err_remove_usb3_hcd;
4458
4459         ret = tegra_xhci_request_irq(pdev, "usb3", pmc_usb_phy_wake_isr,
4460                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4461                 &tegra->usb3_irq);
4462         if (ret != 0)
4463                 goto err_remove_usb3_hcd;
4464
4465         for (port = 0; port < XUSB_SS_PORT_COUNT; port++) {
4466                 tegra->ctle_ctx_saved[port] = false;
4467                 tegra->dfe_ctx_saved[port] = false;
4468         }
4469
4470         hsic_pad_pretend_connect(tegra);
4471
4472         tegra_xhci_debug_read_pads(tegra);
4473         utmi_phy_pad_enable();
4474         utmi_phy_iddq_override(false);
4475
4476         tegra_pd_add_device(&pdev->dev);
4477         pm_runtime_enable(&pdev->dev);
4478
4479         tegra->init_done = true;
4480
4481         return 0;
4482
4483 err_remove_usb3_hcd:
4484         usb_remove_hcd(xhci->shared_hcd);
4485 err_put_usb3_hcd:
4486         usb_put_hcd(xhci->shared_hcd);
4487 err_remove_usb2_hcd:
4488         kfree(tegra->xhci);
4489         usb_remove_hcd(hcd);
4490 err_put_usb2_hcd:
4491         usb_put_hcd(hcd);
4492
4493         return ret;
4494 }
4495
4496 static int tegra_xhci_remove(struct platform_device *pdev)
4497 {
4498         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4499         unsigned pad;
4500
4501         if (tegra == NULL)
4502                 return -EINVAL;
4503
4504         mutex_lock(&tegra->sync_lock);
4505
4506         for_each_enabled_hsic_pad(pad, tegra) {
4507                 hsic_pad_disable(tegra, pad);
4508                 hsic_power_rail_disable(tegra);
4509         }
4510
4511         if (tegra->init_done) {
4512                 struct xhci_hcd *xhci = NULL;
4513                 struct usb_hcd *hcd = NULL;
4514
4515                 xhci = tegra->xhci;
4516                 hcd = xhci_to_hcd(xhci);
4517
4518                 devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
4519                 devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
4520                 devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
4521                 usb_remove_hcd(xhci->shared_hcd);
4522                 usb_put_hcd(xhci->shared_hcd);
4523                 usb_remove_hcd(hcd);
4524                 usb_put_hcd(hcd);
4525                 kfree(xhci);
4526         }
4527
4528         deinit_firmware(tegra);
4529         fw_log_deinit(tegra);
4530
4531         tegra_xusb_regulator_deinit(tegra);
4532
4533         if (tegra->transceiver)
4534                 usb_unregister_notifier(tegra->transceiver, &tegra->otgnb);
4535
4536         tegra_usb2_clocks_deinit(tegra);
4537         if (!tegra->hc_in_elpg)
4538                 tegra_xusb_partitions_clk_deinit(tegra);
4539
4540         utmi_phy_pad_disable();
4541         utmi_phy_iddq_override(true);
4542
4543         tegra_pd_remove_device(&pdev->dev);
4544         platform_set_drvdata(pdev, NULL);
4545
4546         mutex_unlock(&tegra->sync_lock);
4547
4548         return 0;
4549 }
4550
4551 static void tegra_xhci_shutdown(struct platform_device *pdev)
4552 {
4553         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4554         struct xhci_hcd *xhci = NULL;
4555         struct usb_hcd *hcd = NULL;
4556
4557         if (tegra == NULL)
4558                 return;
4559
4560         if (tegra->hc_in_elpg) {
4561                 pmc_disable_bus_ctrl(tegra);
4562         } else {
4563                 xhci = tegra->xhci;
4564                 hcd = xhci_to_hcd(xhci);
4565                 xhci_shutdown(hcd);
4566         }
4567 }
4568
4569 static struct platform_driver tegra_xhci_driver = {
4570         .probe  = tegra_xhci_probe,
4571         .remove = tegra_xhci_remove,
4572         .shutdown = tegra_xhci_shutdown,
4573 #ifdef CONFIG_PM
4574         .suspend = tegra_xhci_suspend,
4575         .resume  = tegra_xhci_resume,
4576 #endif
4577         .driver = {
4578                 .name = "tegra-xhci",
4579         },
4580 };
4581 MODULE_ALIAS("platform:tegra-xhci");
4582
4583 int tegra_xhci_register_plat(void)
4584 {
4585         return platform_driver_register(&tegra_xhci_driver);
4586 }
4587
4588 void tegra_xhci_unregister_plat(void)
4589 {
4590         platform_driver_unregister(&tegra_xhci_driver);
4591 }