usb: xhci: tegra: support hsic dt config
[linux-3.10.git] / drivers / usb / host / xhci-tegra.c
1 /*
2  * xhci-tegra.c - Nvidia xHCI host controller driver
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/clk.h>
24 #include <linux/ioport.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irq.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/uaccess.h>
30 #include <linux/circ_buf.h>
31 #include <linux/vmalloc.h>
32 #include <linux/debugfs.h>
33 #include <linux/kthread.h>
34 #include <linux/gpio.h>
35 #include <linux/usb/otg.h>
36 #include <linux/clk/tegra.h>
37 #include <linux/tegra-powergate.h>
38 #include <linux/firmware.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/of.h>
41 #include <linux/of_device.h>
42 #include <linux/of_gpio.h>
43 #include <linux/tegra-fuse.h>
44
45 #include <mach/tegra_usb_pad_ctrl.h>
46 #include <mach/tegra_usb_pmc.h>
47 #include <mach/pm_domains.h>
48 #include <mach/mc.h>
49 #include <mach/xusb.h>
50
51 #include "xhci-tegra.h"
52 #include "xhci.h"
53 #include "../../../arch/arm/mach-tegra/iomap.h"
54
55 /* macros */
56 #define FW_IOCTL_LOG_DEQUEUE_LOW        (4)
57 #define FW_IOCTL_LOG_DEQUEUE_HIGH       (5)
58 #define FW_IOCTL_DATA_SHIFT             (0)
59 #define FW_IOCTL_DATA_MASK              (0x00ffffff)
60 #define FW_IOCTL_TYPE_SHIFT             (24)
61 #define FW_IOCTL_TYPE_MASK              (0xff000000)
62 #define FW_LOG_SIZE                     (sizeof(struct log_entry))
63 #define FW_LOG_COUNT                    (4096)
64 #define FW_LOG_RING_SIZE                (FW_LOG_SIZE * FW_LOG_COUNT)
65 #define FW_LOG_PAYLOAD_SIZE             (27)
66 #define DRIVER                          (0x01)
67 #define CIRC_BUF_SIZE                   (4 * (1 << 20)) /* 4MB */
68 #define FW_LOG_THREAD_RELAX             (msecs_to_jiffies(100))
69
70 /* tegra_xhci_firmware_log.flags bits */
71 #define FW_LOG_CONTEXT_VALID            (0)
72 #define FW_LOG_FILE_OPENED              (1)
73
74 #define PAGE_SELECT_MASK                        0xFFFFFE00
75 #define PAGE_SELECT_SHIFT                       9
76 #define PAGE_OFFSET_MASK                        0x000001FF
77 #define CSB_PAGE_SELECT(_addr)                                          \
78         ({                                                              \
79                 typecheck(u32, _addr);                                  \
80                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
81         })
82 #define CSB_PAGE_OFFSET(_addr)                                          \
83         ({                                                              \
84                 typecheck(u32, _addr);                                  \
85                 (_addr & PAGE_OFFSET_MASK);                             \
86         })
87
88 #define reg_dump(_dev, _base, _reg)                                     \
89         dev_dbg(_dev, "%s: %s @%x = 0x%x\n", __func__, #_reg,           \
90                 _reg, readl(_base + _reg))
91
92 #define PMC_PORTMAP_MASK(map, pad)      (((map) >> 4*(pad)) & 0xF)
93
94 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
95 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
96 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
97
98 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
99
100 /* private data types */
101 /* command requests from the firmware */
102 enum MBOX_CMD_TYPE {
103         MBOX_CMD_MSG_ENABLED = 1,
104         MBOX_CMD_INC_FALC_CLOCK,
105         MBOX_CMD_DEC_FALC_CLOCK,
106         MBOX_CMD_INC_SSPI_CLOCK,
107         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
108         MBOX_CMD_SET_BW,
109         MBOX_CMD_SET_SS_PWR_GATING,
110         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
111         MBOX_CMD_SAVE_DFE_CTLE_CTX,
112         MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
113         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* 11, unused */
114         MBOX_CMD_STAR_HSIC_IDLE,
115         MBOX_CMD_STOP_HSIC_IDLE,
116         MBOX_CMD_DBC_WAKE_STACK, /* unused */
117         MBOX_CMD_HSIC_PRETEND_CONNECT,
118
119         /* needs to be the last cmd */
120         MBOX_CMD_MAX,
121
122         /* resp msg to ack above commands */
123         MBOX_CMD_ACK = 128,
124         MBOX_CMD_NACK
125 };
126
127 struct log_entry {
128         u32 sequence_no;
129         u8 data[FW_LOG_PAYLOAD_SIZE];
130         u8 owner;
131 };
132
133 /* Usb3 Firmware Cfg Table */
134 struct cfgtbl {
135         u32 boot_loadaddr_in_imem;
136         u32 boot_codedfi_offset;
137         u32 boot_codetag;
138         u32 boot_codesize;
139
140         /* Physical memory reserved by Bootloader/BIOS */
141         u32 phys_memaddr;
142         u16 reqphys_memsize;
143         u16 alloc_phys_memsize;
144
145         /* .rodata section */
146         u32 rodata_img_offset;
147         u32 rodata_section_start;
148         u32 rodata_section_end;
149         u32 main_fnaddr;
150
151         u32 fwimg_cksum;
152         u32 fwimg_created_time;
153
154         /* Fields that get filled by linker during linking phase
155          * or initialized in the FW code.
156          */
157         u32 imem_resident_start;
158         u32 imem_resident_end;
159         u32 idirect_start;
160         u32 idirect_end;
161         u32 l2_imem_start;
162         u32 l2_imem_end;
163         u32 version_id;
164         u8 init_ddirect;
165         u8 reserved[3];
166         u32 phys_addr_log_buffer;
167         u32 total_log_entries;
168         u32 dequeue_ptr;
169
170         /*      Below two dummy variables are used to replace
171          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
172          *      retain the size of struct _CFG_TBL used by other AP/Module.
173          */
174         u32 dummy_var1;
175         u32 dummy_var2;
176
177         /* fwimg_len */
178         u32 fwimg_len;
179         u8 magic[8];
180         u32 SS_low_power_entry_timeout;
181         u8 num_hsic_port;
182         u8 padding[139]; /* padding bytes to makeup 256-bytes cfgtbl */
183 };
184
185 struct xusb_save_regs {
186         u32 msi_bar_sz;
187         u32 msi_axi_barst;
188         u32 msi_fpci_barst;
189         u32 msi_vec0;
190         u32 msi_en_vec0;
191         u32 fpci_error_masks;
192         u32 intr_mask;
193         u32 ipfs_intr_enable;
194         u32 ufpci_config;
195         u32 clkgate_hysteresis;
196         u32 xusb_host_mccif_fifo_cntrl;
197
198         /* PG does not mention below */
199         u32 hs_pls;
200         u32 fs_pls;
201         u32 hs_fs_speed;
202         u32 hs_fs_pp;
203         u32 cfg_aru;
204         u32 cfg_order;
205         u32 cfg_fladj;
206         u32 cfg_sid;
207         /* DFE and CTLE */
208         u32 tap1_val[XUSB_SS_PORT_COUNT];
209         u32 amp_val[XUSB_SS_PORT_COUNT];
210         u32 ctle_z_val[XUSB_SS_PORT_COUNT];
211         u32 ctle_g_val[XUSB_SS_PORT_COUNT];
212 };
213
214 struct tegra_xhci_firmware {
215         void *data; /* kernel virtual address */
216         size_t size; /* firmware size */
217         dma_addr_t dma; /* dma address for controller */
218 };
219
220 struct tegra_xhci_firmware_log {
221         dma_addr_t phys_addr;           /* dma-able address */
222         void *virt_addr;                /* kernel va of the shared log buffer */
223         struct log_entry *dequeue;      /* current dequeue pointer (va) */
224         struct circ_buf circ;           /* big circular buffer */
225         u32 seq;                        /* log sequence number */
226
227         struct task_struct *thread;     /* a thread to consume log */
228         struct mutex mutex;
229         wait_queue_head_t read_wait;
230         wait_queue_head_t write_wait;
231         wait_queue_head_t intr_wait;
232         struct dentry *path;
233         struct dentry *log_file;
234         unsigned long flags;
235 };
236
237 /* structure to hold the offsets of padctl registers */
238 struct tegra_xusb_padctl_regs {
239         u16 boot_media_0;
240         u16 usb2_pad_mux_0;
241         u16 usb2_port_cap_0;
242         u16 snps_oc_map_0;
243         u16 usb2_oc_map_0;
244         u16 ss_port_map_0;
245         u16 oc_det_0;
246         u16 elpg_program_0;
247         u16 usb2_bchrg_otgpad0_ctl0_0;
248         u16 usb2_bchrg_otgpad0_ctl1_0;
249         u16 usb2_bchrg_otgpad1_ctl0_0;
250         u16 usb2_bchrg_otgpad1_ctl1_0;
251         u16 usb2_bchrg_otgpad2_ctl0_0;
252         u16 usb2_bchrg_otgpad2_ctl1_0;
253         u16 usb2_bchrg_bias_pad_0;
254         u16 usb2_bchrg_tdcd_dbnc_timer_0;
255         u16 iophy_pll_p0_ctl1_0;
256         u16 iophy_pll_p0_ctl2_0;
257         u16 iophy_pll_p0_ctl3_0;
258         u16 iophy_pll_p0_ctl4_0;
259         u16 iophy_usb3_pad0_ctl1_0;
260         u16 iophy_usb3_pad1_ctl1_0;
261         u16 iophy_usb3_pad0_ctl2_0;
262         u16 iophy_usb3_pad1_ctl2_0;
263         u16 iophy_usb3_pad0_ctl3_0;
264         u16 iophy_usb3_pad1_ctl3_0;
265         u16 iophy_usb3_pad0_ctl4_0;
266         u16 iophy_usb3_pad1_ctl4_0;
267         u16 iophy_misc_pad_p0_ctl1_0;
268         u16 iophy_misc_pad_p1_ctl1_0;
269         u16 iophy_misc_pad_p0_ctl2_0;
270         u16 iophy_misc_pad_p1_ctl2_0;
271         u16 iophy_misc_pad_p0_ctl3_0;
272         u16 iophy_misc_pad_p1_ctl3_0;
273         u16 iophy_misc_pad_p0_ctl4_0;
274         u16 iophy_misc_pad_p1_ctl4_0;
275         u16 iophy_misc_pad_p0_ctl5_0;
276         u16 iophy_misc_pad_p1_ctl5_0;
277         u16 iophy_misc_pad_p0_ctl6_0;
278         u16 iophy_misc_pad_p1_ctl6_0;
279         u16 usb2_otg_pad0_ctl0_0;
280         u16 usb2_otg_pad1_ctl0_0;
281         u16 usb2_otg_pad2_ctl0_0;
282         u16 usb2_otg_pad0_ctl1_0;
283         u16 usb2_otg_pad1_ctl1_0;
284         u16 usb2_otg_pad2_ctl1_0;
285         u16 usb2_bias_pad_ctl0_0;
286         u16 usb2_bias_pad_ctl1_0;
287         u16 usb2_hsic_pad0_ctl0_0;
288         u16 usb2_hsic_pad1_ctl0_0;
289         u16 usb2_hsic_pad0_ctl1_0;
290         u16 usb2_hsic_pad1_ctl1_0;
291         u16 usb2_hsic_pad0_ctl2_0;
292         u16 usb2_hsic_pad1_ctl2_0;
293         u16 ulpi_link_trim_ctl0;
294         u16 ulpi_null_clk_trim_ctl0;
295         u16 hsic_strb_trim_ctl0;
296         u16 wake_ctl0;
297         u16 pm_spare0;
298         u16 iophy_misc_pad_p2_ctl1_0;
299         u16 iophy_misc_pad_p3_ctl1_0;
300         u16 iophy_misc_pad_p4_ctl1_0;
301         u16 iophy_misc_pad_p2_ctl2_0;
302         u16 iophy_misc_pad_p3_ctl2_0;
303         u16 iophy_misc_pad_p4_ctl2_0;
304         u16 iophy_misc_pad_p2_ctl3_0;
305         u16 iophy_misc_pad_p3_ctl3_0;
306         u16 iophy_misc_pad_p4_ctl3_0;
307         u16 iophy_misc_pad_p2_ctl4_0;
308         u16 iophy_misc_pad_p3_ctl4_0;
309         u16 iophy_misc_pad_p4_ctl4_0;
310         u16 iophy_misc_pad_p2_ctl5_0;
311         u16 iophy_misc_pad_p3_ctl5_0;
312         u16 iophy_misc_pad_p4_ctl5_0;
313         u16 iophy_misc_pad_p2_ctl6_0;
314         u16 iophy_misc_pad_p3_ctl6_0;
315         u16 iophy_misc_pad_p4_ctl6_0;
316         u16 usb3_pad_mux_0;
317         u16 iophy_pll_s0_ctl1_0;
318         u16 iophy_pll_s0_ctl2_0;
319         u16 iophy_pll_s0_ctl3_0;
320         u16 iophy_pll_s0_ctl4_0;
321         u16 iophy_misc_pad_s0_ctl1_0;
322         u16 iophy_misc_pad_s0_ctl2_0;
323         u16 iophy_misc_pad_s0_ctl3_0;
324         u16 iophy_misc_pad_s0_ctl4_0;
325         u16 iophy_misc_pad_s0_ctl5_0;
326         u16 iophy_misc_pad_s0_ctl6_0;
327 };
328
329 struct tegra_xhci_hcd {
330         struct platform_device *pdev;
331         struct xhci_hcd *xhci;
332         u16 device_id;
333
334         spinlock_t lock;
335         struct mutex sync_lock;
336
337         int smi_irq;
338         int padctl_irq;
339         int usb3_irq;
340         int usb2_irq;
341
342         bool ss_wake_event;
343         bool ss_pwr_gated;
344         bool host_pwr_gated;
345         bool hs_wake_event;
346         bool host_resume_req;
347         bool lp0_exit;
348         bool dfe_ctx_saved[XUSB_SS_PORT_COUNT];
349         bool ctle_ctx_saved[XUSB_SS_PORT_COUNT];
350         unsigned long last_jiffies;
351         unsigned long host_phy_base;
352         unsigned long host_phy_size;
353         void __iomem *host_phy_virt_base;
354
355         void __iomem *padctl_base;
356         void __iomem *fpci_base;
357         void __iomem *ipfs_base;
358
359         struct tegra_xusb_platform_data *pdata;
360         struct tegra_xusb_board_data *bdata;
361         struct tegra_xusb_chip_calib *cdata;
362         struct tegra_xusb_padctl_regs *padregs;
363         const struct tegra_xusb_soc_config *soc_config;
364         u64 tegra_xusb_dmamask;
365
366         /* mailbox variables */
367         struct mutex mbox_lock;
368         u32 mbox_owner;
369         u32 cmd_type;
370         u32 cmd_data;
371
372         struct regulator *xusb_utmi_vbus_regs[XUSB_UTMI_COUNT];
373
374         struct regulator *xusb_s1p05v_reg;
375         struct regulator *xusb_s3p3v_reg;
376         struct regulator *xusb_s1p8v_reg;
377         struct regulator *vddio_hsic_reg;
378         int vddio_hsic_refcnt;
379
380         struct work_struct mbox_work;
381         struct work_struct ss_elpg_exit_work;
382         struct work_struct host_elpg_exit_work;
383
384         struct clk *host_clk;
385         struct clk *ss_clk;
386
387         /* XUSB Falcon SuperSpeed Clock */
388         struct clk *falc_clk;
389
390         /* EMC Clock */
391         struct clk *emc_clk;
392         /* XUSB SS PI Clock */
393         struct clk *ss_src_clk;
394         /* PLLE Clock */
395         struct clk *plle_clk;
396         struct clk *pll_u_480M;
397         struct clk *clk_m;
398         /* refPLLE clk */
399         struct clk *pll_re_vco_clk;
400         /*
401          * XUSB/IPFS specific registers these need to be saved/restored in
402          * addition to spec defined registers
403          */
404         struct xusb_save_regs sregs;
405         bool usb2_rh_suspend;
406         bool usb3_rh_suspend;
407         bool hc_in_elpg;
408
409         /* otg transceiver */
410         struct usb_phy *transceiver;
411         struct notifier_block otgnb;
412
413         unsigned long usb2_rh_remote_wakeup_ports; /* one bit per port */
414         unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
415         /* firmware loading related */
416         struct tegra_xhci_firmware firmware;
417
418         struct tegra_xhci_firmware_log log;
419
420         bool init_done;
421 };
422
423 static int tegra_xhci_probe2(struct tegra_xhci_hcd *tegra);
424 static int tegra_xhci_remove(struct platform_device *pdev);
425 static void init_filesystem_firmware_done(const struct firmware *fw,
426                                         void *context);
427
428 static struct tegra_usb_pmc_data pmc_data[XUSB_UTMI_COUNT];
429 static struct tegra_usb_pmc_data pmc_hsic_data[XUSB_HSIC_COUNT];
430 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
431         u8 port)  __attribute__ ((unused));
432
433 #ifdef CONFIG_TEGRA_XUSB_USB_BOOTLOADER_FIRMWARE
434 static bool use_bootloader_firmware = true;
435 #else
436 static bool use_bootloader_firmware;
437 #endif
438 module_param(use_bootloader_firmware, bool, S_IRUGO);
439 MODULE_PARM_DESC(use_bootloader_firmware, "take bootloader initialized firmware");
440
441 #define FIRMWARE_FILE CONFIG_TEGRA_XUSB_FIRMWARE_FILE
442 static char *firmware_file = FIRMWARE_FILE;
443 #define FIRMWARE_FILE_HELP      \
444         "used to specify firmware file of Tegra XHCI host controller. "\
445         "This takes effect only if \"use_bootloader_firmware\" is \"N\". " \
446         "Default value is \"" FIRMWARE_FILE "\"."
447
448 module_param(firmware_file, charp, S_IRUGO);
449 MODULE_PARM_DESC(firmware_file, FIRMWARE_FILE_HELP);
450
451 /* functions */
452 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
453 {
454         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
455 }
456
457 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
458 {
459 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
460         WARN_ON(tegra->sync_lock.owner != current);
461 #endif
462 }
463
464 #define for_each_enabled_hsic_pad(_pad, _tegra_xhci_hcd)                \
465         for (_pad = find_next_enabled_hsic_pad(_tegra_xhci_hcd, 0);     \
466             (_pad < XUSB_HSIC_COUNT) && (_pad >= 0);                    \
467             _pad = find_next_enabled_hsic_pad(_tegra_xhci_hcd, _pad + 1))
468
469 static inline int find_next_enabled_pad(struct tegra_xhci_hcd *tegra,
470                                                 int start, int last)
471 {
472         unsigned long portmap = tegra->bdata->portmap;
473         return find_next_bit(&portmap, last , start);
474 }
475
476 static inline int find_next_enabled_hsic_pad(struct tegra_xhci_hcd *tegra,
477                                                 int curr_pad)
478 {
479         int start = XUSB_HSIC_INDEX + curr_pad;
480         int last = XUSB_HSIC_INDEX + XUSB_HSIC_COUNT;
481
482         if ((curr_pad < 0) || (curr_pad >= XUSB_HSIC_COUNT))
483                 return -1;
484
485         return find_next_enabled_pad(tegra, start, last) - XUSB_HSIC_INDEX;
486 }
487
488 static void tegra_xhci_setup_gpio_for_ss_lane(struct tegra_xhci_hcd *tegra)
489 {
490         int err = 0;
491
492         if (!tegra->bdata->gpio_controls_muxed_ss_lanes)
493                 return;
494
495         if (tegra->bdata->lane_owner & BIT(0)) {
496                 /* USB3_SS port1 is using SATA lane so set (MUX_SATA)
497                  * GPIO P11 to '0'
498                  */
499                 err = gpio_request((tegra->bdata->gpio_ss1_sata & 0xffff),
500                         "gpio_ss1_sata");
501                 if (err < 0)
502                         pr_err("%s: gpio_ss1_sata gpio_request failed %d\n",
503                                 __func__, err);
504                 err = gpio_direction_output((tegra->bdata->gpio_ss1_sata
505                         & 0xffff), 1);
506                 if (err < 0)
507                         pr_err("%s: gpio_ss1_sata gpio_direction failed %d\n",
508                                 __func__, err);
509                 __gpio_set_value((tegra->bdata->gpio_ss1_sata & 0xffff),
510                                 ((tegra->bdata->gpio_ss1_sata >> 16)));
511         }
512 }
513
514 static u32 xhci_read_portsc(struct xhci_hcd *xhci, unsigned int port)
515 {
516         int num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
517         __le32 __iomem *addr;
518
519         if (port >= num_ports) {
520                 xhci_err(xhci, "%s invalid port %u\n", __func__, port);
521                 return -1;
522         }
523
524         addr = &xhci->op_regs->port_status_base + (NUM_PORT_REGS * port);
525         return xhci_readl(xhci, addr);
526 }
527
528 static void debug_print_portsc(struct xhci_hcd *xhci)
529 {
530         __le32 __iomem *addr = &xhci->op_regs->port_status_base;
531         u32 reg;
532         int i;
533         int ports;
534
535         ports = HCS_MAX_PORTS(xhci->hcs_params1);
536         for (i = 0; i < ports; i++) {
537                 reg = xhci_read_portsc(xhci, i);
538                 xhci_dbg(xhci, "@%p port %d status reg = 0x%x\n",
539                                 addr, i, (unsigned int) reg);
540                 addr += NUM_PORT_REGS;
541         }
542 }
543 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra);
544
545 static bool is_otg_host(struct tegra_xhci_hcd *tegra)
546 {
547         if (!tegra->transceiver)
548                 return true;
549         else if (tegra->transceiver->state == OTG_STATE_A_HOST)
550                 return true;
551         else
552                 return false;
553 }
554
555 static int update_speed(struct tegra_xhci_hcd *tegra, u8 port)
556 {
557         struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
558         u32 portsc;
559
560         portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port));
561         if (DEV_FULLSPEED(portsc))
562                 return USB_PMC_PORT_SPEED_FULL;
563         else if (DEV_HIGHSPEED(portsc))
564                 return USB_PMC_PORT_SPEED_HIGH;
565         else if (DEV_LOWSPEED(portsc))
566                 return USB_PMC_PORT_SPEED_LOW;
567         else if (DEV_SUPERSPEED(portsc))
568                 return USB_PMC_PORT_SPEED_SUPER;
569         else
570                 return USB_PMC_PORT_SPEED_UNKNOWN;
571 }
572
573 static void pmc_init(struct tegra_xhci_hcd *tegra)
574 {
575         struct tegra_usb_pmc_data *pmc;
576         struct device *dev = &tegra->pdev->dev;
577         int pad;
578
579         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
580                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
581                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
582                         pmc = &pmc_data[pad];
583                         if (tegra->soc_config->pmc_portmap)
584                                 pmc->instance = PMC_PORTMAP_MASK(
585                                                 tegra->soc_config->pmc_portmap,
586                                                 pad);
587                         else
588                                 pmc->instance = pad;
589                         pmc->phy_type = TEGRA_USB_PHY_INTF_UTMI;
590                         pmc->port_speed = USB_PMC_PORT_SPEED_UNKNOWN;
591                         pmc->controller_type = TEGRA_USB_3_0;
592                         tegra_usb_pmc_init(pmc);
593                 }
594         }
595
596         for_each_enabled_hsic_pad(pad, tegra) {
597                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
598                 pmc = &pmc_hsic_data[pad];
599                 pmc->instance = pad + 1;
600                 pmc->phy_type = TEGRA_USB_PHY_INTF_HSIC;
601                 pmc->port_speed = USB_PMC_PORT_SPEED_HIGH;
602                 pmc->controller_type = TEGRA_USB_3_0;
603                 tegra_usb_pmc_init(pmc);
604         }
605 }
606
607 static void pmc_setup_wake_detect(struct tegra_xhci_hcd *tegra)
608 {
609         struct tegra_usb_pmc_data *pmc;
610         struct device *dev = &tegra->pdev->dev;
611         u32 portsc;
612         int port;
613         int pad;
614
615         for_each_enabled_hsic_pad(pad, tegra) {
616                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
617
618                 pmc = &pmc_hsic_data[pad];
619                 port = hsic_pad_to_port(pad);
620                 portsc = xhci_read_portsc(tegra->xhci, port);
621                 dev_dbg(dev, "%s hsic pad %d portsc 0x%x\n",
622                         __func__, pad, portsc);
623
624                 if (((int) portsc != -1) && (portsc & PORT_CONNECT))
625                         pmc->pmc_ops->setup_pmc_wake_detect(pmc);
626         }
627
628         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
629                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
630                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
631                         pmc = &pmc_data[pad];
632                         pmc->port_speed = update_speed(tegra, pad);
633                         if (pad == 0) {
634                                 if (is_otg_host(tegra))
635                                         pmc->pmc_ops->setup_pmc_wake_detect(
636                                                                         pmc);
637                         } else
638                                 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
639                 }
640         }
641 }
642
643 static void pmc_disable_bus_ctrl(struct tegra_xhci_hcd *tegra)
644 {
645         struct tegra_usb_pmc_data *pmc;
646         struct device *dev = &tegra->pdev->dev;
647         int pad;
648
649         for_each_enabled_hsic_pad(pad, tegra) {
650                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
651
652                 pmc = &pmc_hsic_data[pad];
653                 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
654         }
655
656         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
657                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
658                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
659                         pmc = &pmc_data[pad];
660                         pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
661                 }
662         }
663 }
664
665 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
666 {
667         void __iomem *fpci_base = tegra->fpci_base;
668         struct platform_device *pdev = tegra->pdev;
669         u32 input_addr;
670         u32 data;
671         u32 csb_page_select;
672
673         /* to select the appropriate CSB page to write to */
674         csb_page_select = CSB_PAGE_SELECT(addr);
675
676         dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
677                         csb_page_select);
678
679         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
680
681         /* selects the appropriate offset in the page to read from */
682         input_addr = CSB_PAGE_OFFSET(addr);
683         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
684
685         dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
686                         input_addr, data);
687         return data;
688 }
689
690 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
691 {
692         void __iomem *fpci_base = tegra->fpci_base;
693         struct platform_device *pdev = tegra->pdev;
694         u32 input_addr;
695         u32 csb_page_select;
696
697         /* to select the appropriate CSB page to write to */
698         csb_page_select = CSB_PAGE_SELECT(addr);
699
700         dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
701                         csb_page_select);
702
703         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
704
705         /* selects the appropriate offset in the page to write to */
706         input_addr = CSB_PAGE_OFFSET(addr);
707         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
708
709         dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
710                         input_addr, data);
711 }
712
713 static int fw_message_send(struct tegra_xhci_hcd *tegra,
714         enum MBOX_CMD_TYPE type, u32 data)
715 {
716         struct device *dev = &tegra->pdev->dev;
717         void __iomem *base = tegra->fpci_base;
718         unsigned long target;
719         u32 reg;
720
721         dev_dbg(dev, "%s type %d data 0x%x\n", __func__, type, data);
722
723         mutex_lock(&tegra->mbox_lock);
724
725         target = jiffies + msecs_to_jiffies(20);
726         /* wait mailbox to become idle, timeout in 20ms */
727         while (((reg = readl(base + XUSB_CFG_ARU_MBOX_OWNER)) != 0) &&
728                 time_is_after_jiffies(target)) {
729                 mutex_unlock(&tegra->mbox_lock);
730                 usleep_range(100, 200);
731                 mutex_lock(&tegra->mbox_lock);
732         }
733
734         if (reg != 0) {
735                 dev_err(dev, "%s mailbox is still busy\n", __func__);
736                 goto timeout;
737         }
738
739         target = jiffies + msecs_to_jiffies(10);
740         /* acquire mailbox , timeout in 10ms */
741         writel(MBOX_OWNER_SW, base + XUSB_CFG_ARU_MBOX_OWNER);
742         while (((reg = readl(base + XUSB_CFG_ARU_MBOX_OWNER)) != MBOX_OWNER_SW)
743                 && time_is_after_jiffies(target)) {
744                 mutex_unlock(&tegra->mbox_lock);
745                 usleep_range(100, 200);
746                 mutex_lock(&tegra->mbox_lock);
747                 writel(MBOX_OWNER_SW, base + XUSB_CFG_ARU_MBOX_OWNER);
748         }
749
750         if (reg != MBOX_OWNER_SW) {
751                 dev_err(dev, "%s acquire mailbox timeout\n", __func__);
752                 goto timeout;
753         }
754
755         reg = CMD_TYPE(type) | CMD_DATA(data);
756         writel(reg, base + XUSB_CFG_ARU_MBOX_DATA_IN);
757
758         reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
759         reg |= MBOX_INT_EN | MBOX_FALC_INT_EN;
760         writel(reg, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
761
762         mutex_unlock(&tegra->mbox_lock);
763         return 0;
764
765 timeout:
766         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_CMD);
767         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_DATA_IN);
768         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_DATA_OUT);
769         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_OWNER);
770         mutex_unlock(&tegra->mbox_lock);
771         return -ETIMEDOUT;
772 }
773
774 /**
775  * fw_log_next - find next log entry in a tegra_xhci_firmware_log context.
776  *      This function takes care of wrapping. That means when current log entry
777  *      is the last one, it returns with the first one.
778  *
779  * @param log   The tegra_xhci_firmware_log context.
780  * @param this  The current log entry.
781  * @return      The log entry which is next to the current one.
782  */
783 static inline struct log_entry *fw_log_next(
784                 struct tegra_xhci_firmware_log *log, struct log_entry *this)
785 {
786         struct log_entry *first = (struct log_entry *) log->virt_addr;
787         struct log_entry *last = first + FW_LOG_COUNT - 1;
788
789         WARN((this < first) || (this > last), "%s: invalid input\n", __func__);
790
791         return (this == last) ? first : (this + 1);
792 }
793
794 /**
795  * fw_log_update_dequeue_pointer - update dequeue pointer to both firmware and
796  *      tegra_xhci_firmware_log.dequeue.
797  *
798  * @param log   The tegra_xhci_firmware_log context.
799  * @param n     Counts of log entries to fast-forward.
800  */
801 static inline void fw_log_update_deq_pointer(
802                 struct tegra_xhci_firmware_log *log, int n)
803 {
804         struct tegra_xhci_hcd *tegra =
805                         container_of(log, struct tegra_xhci_hcd, log);
806         struct device *dev = &tegra->pdev->dev;
807         struct log_entry *deq = tegra->log.dequeue;
808         dma_addr_t physical_addr;
809         u32 reg;
810
811         dev_dbg(dev, "curr 0x%p fast-forward %d entries\n", deq, n);
812         while (n-- > 0)
813                 deq = fw_log_next(log, deq);
814
815         tegra->log.dequeue = deq;
816         physical_addr = tegra->log.phys_addr +
817                         ((u8 *)deq - (u8 *)tegra->log.virt_addr);
818
819         /* update dequeue pointer to firmware */
820         reg = (FW_IOCTL_LOG_DEQUEUE_LOW << FW_IOCTL_TYPE_SHIFT);
821         reg |= (physical_addr & 0xffff); /* lower 16-bits */
822         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
823
824         reg = (FW_IOCTL_LOG_DEQUEUE_HIGH << FW_IOCTL_TYPE_SHIFT);
825         reg |= ((physical_addr >> 16) & 0xffff); /* higher 16-bits */
826         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
827
828         dev_dbg(dev, "new 0x%p physical addr 0x%x\n", deq, (u32)physical_addr);
829 }
830
831 static inline bool circ_buffer_full(struct circ_buf *circ)
832 {
833         int space = CIRC_SPACE(circ->head, circ->tail, CIRC_BUF_SIZE);
834
835         return (space <= FW_LOG_SIZE);
836 }
837
838 static inline bool fw_log_available(struct tegra_xhci_hcd *tegra)
839 {
840         return (tegra->log.dequeue->owner == DRIVER);
841 }
842
843 /**
844  * fw_log_wait_empty_timeout - wait firmware log thread to clean up shared
845  *      log buffer.
846  * @param tegra:        tegra_xhci_hcd context
847  * @param msec:         timeout value in millisecond
848  * @return true:        shared log buffer is empty,
849  *         false:       shared log buffer isn't empty.
850  */
851 static inline bool fw_log_wait_empty_timeout(struct tegra_xhci_hcd *tegra,
852                 unsigned timeout)
853 {
854         unsigned long target = jiffies + msecs_to_jiffies(timeout);
855         bool ret;
856
857         mutex_lock(&tegra->log.mutex);
858
859         while (fw_log_available(tegra) && time_is_after_jiffies(target)) {
860                 mutex_unlock(&tegra->log.mutex);
861                 usleep_range(1000, 2000);
862                 mutex_lock(&tegra->log.mutex);
863         }
864
865         ret = fw_log_available(tegra);
866         mutex_unlock(&tegra->log.mutex);
867
868         return ret;
869 }
870
871 /**
872  * fw_log_copy - copy firmware log from device's buffer to driver's circular
873  *      buffer.
874  * @param tegra tegra_xhci_hcd context
875  * @return true,        We still have firmware log in device's buffer to copy.
876  *                      This function returned due the driver's circular buffer
877  *                      is full. Caller should invoke this function again as
878  *                      soon as there is space in driver's circular buffer.
879  *         false,       Device's buffer is empty.
880  */
881 static inline bool fw_log_copy(struct tegra_xhci_hcd *tegra)
882 {
883         struct device *dev = &tegra->pdev->dev;
884         struct circ_buf *circ = &tegra->log.circ;
885         int head, tail;
886         int buffer_len, copy_len;
887         struct log_entry *entry;
888         struct log_entry *first = tegra->log.virt_addr;
889
890         while (fw_log_available(tegra)) {
891
892                 /* calculate maximum contiguous driver buffer length */
893                 head = circ->head;
894                 tail = ACCESS_ONCE(circ->tail);
895                 buffer_len = CIRC_SPACE_TO_END(head, tail, CIRC_BUF_SIZE);
896                 /* round down to FW_LOG_SIZE */
897                 buffer_len -= (buffer_len % FW_LOG_SIZE);
898                 if (!buffer_len)
899                         return true; /* log available but no space left */
900
901                 /* calculate maximum contiguous log copy length */
902                 entry = tegra->log.dequeue;
903                 copy_len = 0;
904                 do {
905                         if (tegra->log.seq != entry->sequence_no) {
906                                 dev_warn(dev,
907                                 "%s: discontinuous seq no, expect %u get %u\n",
908                                 __func__, tegra->log.seq, entry->sequence_no);
909                         }
910                         tegra->log.seq = entry->sequence_no + 1;
911
912                         copy_len += FW_LOG_SIZE;
913                         buffer_len -= FW_LOG_SIZE;
914                         if (!buffer_len)
915                                 break; /* no space left */
916                         entry = fw_log_next(&tegra->log, entry);
917                 } while ((entry->owner == DRIVER) && (entry != first));
918
919                 memcpy(&circ->buf[head], tegra->log.dequeue, copy_len);
920                 memset(tegra->log.dequeue, 0, copy_len);
921                 circ->head = (circ->head + copy_len) & (CIRC_BUF_SIZE - 1);
922
923                 mb();
924
925                 fw_log_update_deq_pointer(&tegra->log, copy_len/FW_LOG_SIZE);
926
927                 dev_dbg(dev, "copied %d entries, new dequeue 0x%p\n",
928                                 copy_len/FW_LOG_SIZE, tegra->log.dequeue);
929                 wake_up_interruptible(&tegra->log.read_wait);
930         }
931
932         return false;
933 }
934
935 static int fw_log_thread(void *data)
936 {
937         struct tegra_xhci_hcd *tegra = data;
938         struct device *dev = &tegra->pdev->dev;
939         struct circ_buf *circ = &tegra->log.circ;
940         bool logs_left;
941
942         dev_dbg(dev, "start firmware log thread\n");
943
944         do {
945                 mutex_lock(&tegra->log.mutex);
946                 if (circ_buffer_full(circ)) {
947                         mutex_unlock(&tegra->log.mutex);
948                         dev_info(dev, "%s: circ buffer full\n", __func__);
949                         wait_event_interruptible(tegra->log.write_wait,
950                             kthread_should_stop() || !circ_buffer_full(circ));
951                         mutex_lock(&tegra->log.mutex);
952                 }
953
954                 logs_left = fw_log_copy(tegra);
955                 mutex_unlock(&tegra->log.mutex);
956
957                 /* relax if no logs left  */
958                 if (!logs_left)
959                         wait_event_interruptible_timeout(tegra->log.intr_wait,
960                                 fw_log_available(tegra), FW_LOG_THREAD_RELAX);
961         } while (!kthread_should_stop());
962
963         dev_dbg(dev, "stop firmware log thread\n");
964         return 0;
965 }
966
967 static inline bool circ_buffer_empty(struct circ_buf *circ)
968 {
969         return (CIRC_CNT(circ->head, circ->tail, CIRC_BUF_SIZE) == 0);
970 }
971
972 static ssize_t fw_log_file_read(struct file *file, char __user *buf,
973                 size_t count, loff_t *offp)
974 {
975         struct tegra_xhci_hcd *tegra = file->private_data;
976         struct platform_device *pdev = tegra->pdev;
977         struct circ_buf *circ = &tegra->log.circ;
978         int head, tail;
979         size_t n = 0;
980         int s;
981
982         mutex_lock(&tegra->log.mutex);
983
984         while (circ_buffer_empty(circ)) {
985                 mutex_unlock(&tegra->log.mutex);
986                 if (file->f_flags & O_NONBLOCK)
987                         return -EAGAIN; /* non-blocking read */
988
989                 dev_dbg(&pdev->dev, "%s: nothing to read\n", __func__);
990
991                 if (wait_event_interruptible(tegra->log.read_wait,
992                                 !circ_buffer_empty(circ)))
993                         return -ERESTARTSYS;
994
995                 if (mutex_lock_interruptible(&tegra->log.mutex))
996                         return -ERESTARTSYS;
997         }
998
999         while (count > 0) {
1000                 head = ACCESS_ONCE(circ->head);
1001                 tail = circ->tail;
1002                 s = min_t(int, count,
1003                                 CIRC_CNT_TO_END(head, tail, CIRC_BUF_SIZE));
1004
1005                 if (s > 0) {
1006                         if (copy_to_user(&buf[n], &circ->buf[tail], s)) {
1007                                 dev_warn(&pdev->dev, "copy_to_user failed\n");
1008                                 mutex_unlock(&tegra->log.mutex);
1009                                 return -EFAULT;
1010                         }
1011                         circ->tail = (circ->tail + s) & (CIRC_BUF_SIZE - 1);
1012
1013                         count -= s;
1014                         n += s;
1015                 } else
1016                         break;
1017         }
1018
1019         mutex_unlock(&tegra->log.mutex);
1020
1021         wake_up_interruptible(&tegra->log.write_wait);
1022
1023         dev_dbg(&pdev->dev, "%s: %d bytes\n", __func__, n);
1024
1025         return n;
1026 }
1027
1028 static int fw_log_file_open(struct inode *inode, struct file *file)
1029 {
1030         struct tegra_xhci_hcd *tegra;
1031         file->private_data = inode->i_private;
1032         tegra = file->private_data;
1033
1034         if (test_and_set_bit(FW_LOG_FILE_OPENED, &tegra->log.flags)) {
1035                 dev_info(&tegra->pdev->dev, "%s: already opened\n", __func__);
1036                 return -EBUSY;
1037         }
1038
1039         return 0;
1040 }
1041
1042 static int fw_log_file_close(struct inode *inode, struct file *file)
1043 {
1044         struct tegra_xhci_hcd *tegra = file->private_data;
1045
1046         clear_bit(FW_LOG_FILE_OPENED, &tegra->log.flags);
1047
1048         return 0;
1049 }
1050
1051 static const struct file_operations firmware_log_fops = {
1052                 .open           = fw_log_file_open,
1053                 .release        = fw_log_file_close,
1054                 .read           = fw_log_file_read,
1055                 .owner          = THIS_MODULE,
1056 };
1057
1058 static int fw_log_init(struct tegra_xhci_hcd *tegra)
1059 {
1060         struct platform_device *pdev = tegra->pdev;
1061         int rc = 0;
1062
1063         /* allocate buffer to be shared between driver and firmware */
1064         tegra->log.virt_addr = dma_alloc_writecombine(&pdev->dev,
1065                         FW_LOG_RING_SIZE, &tegra->log.phys_addr, GFP_KERNEL);
1066
1067         if (!tegra->log.virt_addr) {
1068                 dev_err(&pdev->dev, "dma_alloc_writecombine() size %d failed\n",
1069                                 FW_LOG_RING_SIZE);
1070                 return -ENOMEM;
1071         }
1072
1073         dev_info(&pdev->dev,
1074                 "%d bytes log buffer physical 0x%u virtual 0x%p\n",
1075                 FW_LOG_RING_SIZE, (u32)tegra->log.phys_addr,
1076                 tegra->log.virt_addr);
1077
1078         memset(tegra->log.virt_addr, 0, FW_LOG_RING_SIZE);
1079         tegra->log.dequeue = tegra->log.virt_addr;
1080
1081         tegra->log.circ.buf = vmalloc(CIRC_BUF_SIZE);
1082         if (!tegra->log.circ.buf) {
1083                 dev_err(&pdev->dev, "vmalloc size %d failed\n", CIRC_BUF_SIZE);
1084                 rc = -ENOMEM;
1085                 goto error_free_dma;
1086         }
1087
1088         tegra->log.circ.head = 0;
1089         tegra->log.circ.tail = 0;
1090
1091         init_waitqueue_head(&tegra->log.read_wait);
1092         init_waitqueue_head(&tegra->log.write_wait);
1093         init_waitqueue_head(&tegra->log.intr_wait);
1094
1095         mutex_init(&tegra->log.mutex);
1096
1097         tegra->log.path = debugfs_create_dir("tegra_xhci", NULL);
1098         if (IS_ERR_OR_NULL(tegra->log.path)) {
1099                 dev_warn(&pdev->dev, "debugfs_create_dir() failed\n");
1100                 rc = -ENOMEM;
1101                 goto error_free_mem;
1102         }
1103
1104         tegra->log.log_file = debugfs_create_file("firmware_log",
1105                         S_IRUGO, tegra->log.path, tegra, &firmware_log_fops);
1106         if ((!tegra->log.log_file) ||
1107                         (tegra->log.log_file == ERR_PTR(-ENODEV))) {
1108                 dev_warn(&pdev->dev, "debugfs_create_file() failed\n");
1109                 rc = -ENOMEM;
1110                 goto error_remove_debugfs_path;
1111         }
1112
1113         tegra->log.thread = kthread_run(fw_log_thread, tegra, "xusb-fw-log");
1114         if (IS_ERR(tegra->log.thread)) {
1115                 dev_warn(&pdev->dev, "kthread_run() failed\n");
1116                 rc = -ENOMEM;
1117                 goto error_remove_debugfs_file;
1118         }
1119
1120         set_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags);
1121         return rc;
1122
1123 error_remove_debugfs_file:
1124         debugfs_remove(tegra->log.log_file);
1125 error_remove_debugfs_path:
1126         debugfs_remove(tegra->log.path);
1127 error_free_mem:
1128         vfree(tegra->log.circ.buf);
1129 error_free_dma:
1130         dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1131                         tegra->log.virt_addr, tegra->log.phys_addr);
1132         memset(&tegra->log, sizeof(tegra->log), 0);
1133         return rc;
1134 }
1135
1136 static void fw_log_deinit(struct tegra_xhci_hcd *tegra)
1137 {
1138         struct platform_device *pdev = tegra->pdev;
1139
1140         if (test_and_clear_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
1141
1142                 debugfs_remove(tegra->log.log_file);
1143                 debugfs_remove(tegra->log.path);
1144
1145                 wake_up_interruptible(&tegra->log.read_wait);
1146                 wake_up_interruptible(&tegra->log.write_wait);
1147                 kthread_stop(tegra->log.thread);
1148
1149                 mutex_lock(&tegra->log.mutex);
1150                 dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1151                         tegra->log.virt_addr, tegra->log.phys_addr);
1152                 vfree(tegra->log.circ.buf);
1153                 tegra->log.circ.head = tegra->log.circ.tail = 0;
1154                 mutex_unlock(&tegra->log.mutex);
1155
1156                 mutex_destroy(&tegra->log.mutex);
1157         }
1158 }
1159
1160 /* hsic pad operations */
1161 /*
1162  * HSIC pads need VDDIO_HSIC power rail turned on to be functional. There is
1163  * only one VDDIO_HSIC power rail shared by all HSIC pads.
1164  */
1165 static int hsic_power_rail_enable(struct tegra_xhci_hcd *tegra)
1166 {
1167         struct device *dev = &tegra->pdev->dev;
1168         struct tegra_xusb_regulator_name *supply = &tegra->bdata->supply;
1169         int ret;
1170
1171         if (tegra->vddio_hsic_reg)
1172                 goto done;
1173
1174         tegra->vddio_hsic_reg = devm_regulator_get(dev, supply->vddio_hsic);
1175         if (IS_ERR_OR_NULL(tegra->vddio_hsic_reg)) {
1176                 dev_err(dev, "%s get vddio_hsic failed\n", __func__);
1177                 ret = PTR_ERR(tegra->vddio_hsic_reg);
1178                 goto get_failed;
1179         }
1180
1181         dev_dbg(dev, "%s regulator_enable vddio_hsic\n", __func__);
1182         ret = regulator_enable(tegra->vddio_hsic_reg);
1183         if (ret < 0) {
1184                 dev_err(dev, "%s enable vddio_hsic failed\n", __func__);
1185                 goto enable_failed;
1186         }
1187
1188 done:
1189         tegra->vddio_hsic_refcnt++;
1190         WARN(tegra->vddio_hsic_refcnt > XUSB_HSIC_COUNT,
1191                         "vddio_hsic_refcnt exceeds\n");
1192         return 0;
1193
1194 enable_failed:
1195         devm_regulator_put(tegra->vddio_hsic_reg);
1196 get_failed:
1197         tegra->vddio_hsic_reg = NULL;
1198         return ret;
1199 }
1200
1201 static int hsic_power_rail_disable(struct tegra_xhci_hcd *tegra)
1202 {
1203         struct device *dev = &tegra->pdev->dev;
1204         int ret;
1205
1206         WARN_ON(!tegra->vddio_hsic_reg || !tegra->vddio_hsic_refcnt);
1207
1208         tegra->vddio_hsic_refcnt--;
1209         if (tegra->vddio_hsic_refcnt)
1210                 return 0;
1211
1212         dev_dbg(dev, "%s regulator_disable vddio_hsic\n", __func__);
1213         ret = regulator_disable(tegra->vddio_hsic_reg);
1214         if (ret < 0) {
1215                 dev_err(dev, "%s disable vddio_hsic failed\n", __func__);
1216                 tegra->vddio_hsic_refcnt++;
1217                 return ret;
1218         }
1219
1220         devm_regulator_put(tegra->vddio_hsic_reg);
1221         tegra->vddio_hsic_reg = NULL;
1222
1223         return 0;
1224 }
1225
1226 static int hsic_pad_enable(struct tegra_xhci_hcd *tegra, unsigned pad)
1227 {
1228         struct device *dev = &tegra->pdev->dev;
1229         void __iomem *base = tegra->padctl_base;
1230         struct tegra_xusb_hsic_config *hsic = &tegra->bdata->hsic[pad];
1231         u32 reg;
1232
1233         if (pad >= XUSB_HSIC_COUNT) {
1234                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1235                 return -EINVAL;
1236         }
1237
1238         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1239
1240         reg = readl(base + HSIC_PAD_CTL_2(pad));
1241         reg &= ~(RX_STROBE_TRIM(~0) | RX_DATA_TRIM(~0));
1242         reg |= RX_STROBE_TRIM(hsic->rx_strobe_trim);
1243         reg |= RX_DATA_TRIM(hsic->rx_data_trim);
1244         writel(reg, base + HSIC_PAD_CTL_2(pad));
1245
1246         reg = readl(base + HSIC_PAD_CTL_0(pad));
1247         reg &= ~(TX_RTUNEP(~0) | TX_RTUNEN(~0) | TX_SLEWP(~0) | TX_SLEWN(~0));
1248         reg |= TX_RTUNEP(hsic->tx_rtune_p);
1249         reg |= TX_RTUNEN(hsic->tx_rtune_n);
1250         reg |= TX_SLEWP(hsic->tx_slew_p);
1251         reg |= TX_SLEWN(hsic->tx_slew_n);
1252         writel(reg, base + HSIC_PAD_CTL_0(pad));
1253
1254         reg = readl(base + HSIC_PAD_CTL_1(pad));
1255         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1256         reg |= (RPD_DATA | RPU_STROBE); /* keep HSIC in IDLE */
1257         if (hsic->auto_term_en)
1258                 reg |= AUTO_TERM_EN;
1259         else
1260                 reg &= ~AUTO_TERM_EN;
1261         reg &= ~(PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1262         writel(reg, base + HSIC_PAD_CTL_1(pad));
1263
1264         reg = readl(base + HSIC_STRB_TRIM_CONTROL);
1265         reg &= ~(STRB_TRIM_VAL(~0));
1266         reg |= STRB_TRIM_VAL(hsic->strb_trim_val);
1267         writel(reg, base + HSIC_STRB_TRIM_CONTROL);
1268
1269         reg = readl(base + USB2_PAD_MUX);
1270         reg |= USB2_HSIC_PAD_PORT(pad);
1271         writel(reg, base + USB2_PAD_MUX);
1272
1273         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1274         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1275         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1276         reg_dump(dev, base, HSIC_STRB_TRIM_CONTROL);
1277         reg_dump(dev, base, USB2_PAD_MUX);
1278         return 0;
1279 }
1280
1281 static void hsic_pad_pretend_connect(struct tegra_xhci_hcd *tegra)
1282 {
1283         struct device *dev = &tegra->pdev->dev;
1284         struct tegra_xusb_hsic_config *hsic;
1285         struct usb_device *hs_root_hub = tegra->xhci->main_hcd->self.root_hub;
1286         int pad;
1287         u32 portsc;
1288         int port;
1289         int enabled_pads = 0;
1290         unsigned long wait_ports = 0;
1291         unsigned long target;
1292
1293         for_each_enabled_hsic_pad(pad, tegra) {
1294                 hsic = &tegra->bdata->hsic[pad];
1295                 if (hsic->pretend_connect)
1296                         enabled_pads++;
1297         }
1298
1299         if (enabled_pads == 0) {
1300                 dev_dbg(dev, "%s no hsic pretend_connect enabled\n", __func__);
1301                 return;
1302         }
1303
1304         usb_disable_autosuspend(hs_root_hub);
1305
1306         for_each_enabled_hsic_pad(pad, tegra) {
1307                 hsic = &tegra->bdata->hsic[pad];
1308                 if (!hsic->pretend_connect)
1309                         continue;
1310
1311                 port = hsic_pad_to_port(pad);
1312                 portsc = xhci_read_portsc(tegra->xhci, port);
1313                 dev_dbg(dev, "%s pad %u portsc 0x%x\n", __func__, pad, portsc);
1314
1315                 if (!(portsc & PORT_CONNECT)) {
1316                         /* firmware wants 1-based port index */
1317                         fw_message_send(tegra,
1318                                 MBOX_CMD_HSIC_PRETEND_CONNECT, BIT(port + 1));
1319                 }
1320
1321                 set_bit(port, &wait_ports);
1322         }
1323
1324         /* wait till port reaches U0 */
1325         target = jiffies + msecs_to_jiffies(500);
1326         do {
1327                 for_each_set_bit(port, &wait_ports, BITS_PER_LONG) {
1328                         portsc = xhci_read_portsc(tegra->xhci, port);
1329                         pad = port_to_hsic_pad(port);
1330                         dev_dbg(dev, "%s pad %u portsc 0x%x\n", __func__,
1331                                 pad, portsc);
1332                         if ((PORT_PLS_MASK & portsc) == XDEV_U0)
1333                                 clear_bit(port, &wait_ports);
1334                 }
1335
1336                 if (wait_ports)
1337                         usleep_range(1000, 5000);
1338         } while (wait_ports && time_is_after_jiffies(target));
1339
1340         if (wait_ports)
1341                 dev_warn(dev, "%s HSIC pad(s) didn't reach U0.\n", __func__);
1342
1343         usb_enable_autosuspend(hs_root_hub);
1344
1345         return;
1346 }
1347
1348 static int hsic_pad_disable(struct tegra_xhci_hcd *tegra, unsigned pad)
1349 {
1350         struct device *dev = &tegra->pdev->dev;
1351         void __iomem *base = tegra->padctl_base;
1352         u32 reg;
1353
1354         if (pad >= XUSB_HSIC_COUNT) {
1355                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1356                 return -EINVAL;
1357         }
1358
1359         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1360
1361         reg = readl(base + USB2_PAD_MUX);
1362         reg &= ~USB2_HSIC_PAD_PORT(pad);
1363         writel(reg, base + USB2_PAD_MUX);
1364
1365         reg = readl(base + HSIC_PAD_CTL_1(pad));
1366         reg |= (PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1367         writel(reg, base + HSIC_PAD_CTL_1(pad));
1368
1369         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1370         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1371         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1372         reg_dump(dev, base, USB2_PAD_MUX);
1373         return 0;
1374 }
1375
1376 enum hsic_pad_pupd {
1377         PUPD_DISABLE = 0,
1378         PUPD_IDLE,
1379         PUPD_RESET
1380 };
1381
1382 static int hsic_pad_pupd_set(struct tegra_xhci_hcd *tegra, unsigned pad,
1383         enum hsic_pad_pupd pupd)
1384 {
1385         struct device *dev = &tegra->pdev->dev;
1386         void __iomem *base = tegra->padctl_base;
1387         u32 reg;
1388
1389         if (pad >= XUSB_HSIC_COUNT) {
1390                 dev_err(dev, "%s invalid HSIC pad number %u\n", __func__, pad);
1391                 return -EINVAL;
1392         }
1393
1394         dev_dbg(dev, "%s pad %u pupd %d\n", __func__, pad, pupd);
1395
1396         reg = readl(base + HSIC_PAD_CTL_1(pad));
1397         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1398
1399         if (pupd == PUPD_IDLE)
1400                 reg |= (RPD_DATA | RPU_STROBE);
1401         else if (pupd == PUPD_RESET)
1402                 reg |= (RPD_DATA | RPD_STROBE);
1403         else if (pupd != PUPD_DISABLE) {
1404                 dev_err(dev, "%s invalid pupd %d\n", __func__, pupd);
1405                 return -EINVAL;
1406         }
1407
1408         writel(reg, base + HSIC_PAD_CTL_1(pad));
1409
1410         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1411
1412         return 0;
1413 }
1414
1415
1416 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
1417 {
1418         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1419         struct xhci_hcd *xhci = tegra->xhci;
1420         u32 reg;
1421
1422         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
1423         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1424         xhci_info(xhci, " PAD MUX = %x\n", reg);
1425         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1426         xhci_info(xhci, " PORT CAP = %x\n", reg);
1427         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1428         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
1429         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1430         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
1431         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1432         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
1433         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1434         xhci_info(xhci, " OC DET 0= %x\n", reg);
1435         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad0_ctl2_0);
1436         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
1437         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad1_ctl2_0);
1438         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
1439         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl0_0);
1440         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
1441         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl0_0);
1442         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
1443         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl1_0);
1444         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
1445         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl1_0);
1446         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
1447         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1448         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
1449         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad0_ctl0_0);
1450         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
1451         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad1_ctl0_0);
1452         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
1453         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
1454 }
1455
1456 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
1457 {
1458         u32 reg;
1459
1460         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1461         reg |= IPFS_EN_FPCI;
1462         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1463         udelay(10);
1464
1465         /* Program Bar0 Space */
1466         reg = readl(tegra->fpci_base + XUSB_CFG_4);
1467         reg |= tegra->host_phy_base;
1468         writel(reg, tegra->fpci_base + XUSB_CFG_4);
1469         usleep_range(100, 200);
1470
1471         /* Enable Bus Master */
1472         reg = readl(tegra->fpci_base + XUSB_CFG_1);
1473         reg |= 0x7;
1474         writel(reg, tegra->fpci_base + XUSB_CFG_1);
1475
1476         /* Set intr mask to enable intr assertion */
1477         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1478         reg |= IPFS_IP_INT_MASK;
1479         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1480
1481         /* Set hysteris to 0x80 */
1482         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1483 }
1484
1485 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
1486                 struct platform_device *pdev)
1487 {
1488         struct tegra_xusb_regulator_name *supply = &tegra->bdata->supply;
1489         int i;
1490         int err = 0;
1491
1492         tegra->xusb_s3p3v_reg =
1493                         devm_regulator_get(&pdev->dev, supply->s3p3v);
1494         if (IS_ERR(tegra->xusb_s3p3v_reg)) {
1495                 dev_err(&pdev->dev, "3p3v: regulator not found: %ld."
1496                         , PTR_ERR(tegra->xusb_s3p3v_reg));
1497                 err = PTR_ERR(tegra->xusb_s3p3v_reg);
1498                 goto err_null_regulator;
1499         } else {
1500                 err = regulator_enable(tegra->xusb_s3p3v_reg);
1501                 if (err < 0) {
1502                         dev_err(&pdev->dev,
1503                                 "3p3v: regulator enable failed:%d\n", err);
1504                         goto err_null_regulator;
1505                 }
1506         }
1507
1508         /* enable utmi vbuses */
1509         memset(tegra->xusb_utmi_vbus_regs, 0,
1510                         sizeof(tegra->xusb_utmi_vbus_regs));
1511         for (i = 0; i < XUSB_UTMI_COUNT; i++) {
1512                 struct regulator *reg = NULL;
1513                 const char *reg_name = supply->utmi_vbuses[i];
1514                 if (BIT(XUSB_UTMI_INDEX + i) & tegra->bdata->portmap) {
1515                         if (i == 0 && tegra->transceiver)
1516                                 continue;
1517                         reg = devm_regulator_get(&pdev->dev, reg_name);
1518                         if (IS_ERR(reg)) {
1519                                 dev_err(&pdev->dev,
1520                                         "%s regulator not found: %ld.",
1521                                         reg_name, PTR_ERR(reg));
1522                                 err = PTR_ERR(reg);
1523                         } else {
1524                                 err = regulator_enable(reg);
1525                                 if (err < 0) {
1526                                         dev_err(&pdev->dev,
1527                                         "%s: regulator enable failed: %d\n",
1528                                         reg_name, err);
1529                                 }
1530                         }
1531                         if (err)
1532                                 goto err_put_utmi_vbus_reg;
1533                 }
1534                 tegra->xusb_utmi_vbus_regs[i] = reg;
1535         }
1536
1537         tegra->xusb_s1p8v_reg =
1538                 devm_regulator_get(&pdev->dev, supply->s1p8v);
1539         if (IS_ERR(tegra->xusb_s1p8v_reg)) {
1540                 dev_err(&pdev->dev, "1p8v regulator not found: %ld."
1541                         , PTR_ERR(tegra->xusb_s1p8v_reg));
1542                 err = PTR_ERR(tegra->xusb_s1p8v_reg);
1543                 goto err_put_utmi_vbus_reg;
1544         } else {
1545                 err = regulator_enable(tegra->xusb_s1p8v_reg);
1546                 if (err < 0) {
1547                         dev_err(&pdev->dev,
1548                         "1p8v: regulator enable failed:%d\n", err);
1549                         goto err_put_utmi_vbus_reg;
1550                 }
1551         }
1552
1553         tegra->xusb_s1p05v_reg =
1554                         devm_regulator_get(&pdev->dev, supply->s1p05v);
1555         if (IS_ERR(tegra->xusb_s1p05v_reg)) {
1556                 dev_err(&pdev->dev, "1p05v: regulator not found: %ld."
1557                         , PTR_ERR(tegra->xusb_s1p05v_reg));
1558                 err = PTR_ERR(tegra->xusb_s1p05v_reg);
1559                 goto err_put_s1p8v_reg;
1560         } else {
1561                 err = regulator_enable(tegra->xusb_s1p05v_reg);
1562                 if (err < 0) {
1563                         dev_err(&pdev->dev,
1564                         "1p05v: regulator enable failed:%d\n", err);
1565                         goto err_put_s1p8v_reg;
1566                 }
1567         }
1568
1569         return err;
1570
1571 err_put_s1p8v_reg:
1572         regulator_disable(tegra->xusb_s1p8v_reg);
1573 err_put_utmi_vbus_reg:
1574         for (i = 0; i < XUSB_UTMI_COUNT; i++) {
1575                 struct regulator *reg = tegra->xusb_utmi_vbus_regs[i];
1576                 if (!IS_ERR_OR_NULL(reg))
1577                         regulator_disable(reg);
1578         }
1579         regulator_disable(tegra->xusb_s3p3v_reg);
1580 err_null_regulator:
1581         for (i = 0; i < XUSB_UTMI_COUNT; i++)
1582                 tegra->xusb_utmi_vbus_regs[i] = NULL;
1583         tegra->xusb_s1p05v_reg = NULL;
1584         tegra->xusb_s3p3v_reg = NULL;
1585         tegra->xusb_s1p8v_reg = NULL;
1586         return err;
1587 }
1588
1589 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
1590 {
1591         int i;
1592
1593         regulator_disable(tegra->xusb_s1p05v_reg);
1594         regulator_disable(tegra->xusb_s1p8v_reg);
1595
1596         for (i = 0; i < XUSB_UTMI_COUNT; i++) {
1597                 if (BIT(XUSB_UTMI_INDEX + i) & tegra->bdata->portmap) {
1598                         struct regulator *reg = tegra->xusb_utmi_vbus_regs[i];
1599                         if (!IS_ERR_OR_NULL(reg))
1600                                 regulator_disable(reg);
1601                         tegra->xusb_utmi_vbus_regs[i] = NULL;
1602                 }
1603         }
1604
1605         regulator_disable(tegra->xusb_s3p3v_reg);
1606
1607         tegra->xusb_s1p05v_reg = NULL;
1608         tegra->xusb_s1p8v_reg = NULL;
1609         tegra->xusb_s3p3v_reg = NULL;
1610 }
1611
1612 /*
1613  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
1614  * are under hardware control
1615  */
1616 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
1617 {
1618         struct platform_device *pdev = tegra->pdev;
1619         int err = 0;
1620
1621         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
1622         if (IS_ERR(tegra->plle_clk)) {
1623                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
1624                 err = PTR_ERR(tegra->plle_clk);
1625                 return err;
1626         }
1627         err = clk_enable(tegra->plle_clk);
1628         if (err) {
1629                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
1630                         __func__);
1631                 return err;
1632         }
1633
1634         return err;
1635 }
1636
1637 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
1638 {
1639         clk_disable(tegra->plle_clk);
1640         tegra->plle_clk = NULL;
1641 }
1642
1643 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
1644 {
1645         struct platform_device *pdev = tegra->pdev;
1646         int err = 0;
1647
1648         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
1649         if (IS_ERR(tegra->emc_clk)) {
1650                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
1651                 return PTR_ERR(tegra->emc_clk);
1652         }
1653
1654         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1655                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
1656                 if (IS_ERR(tegra->pll_re_vco_clk)) {
1657                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
1658                         err = PTR_ERR(tegra->pll_re_vco_clk);
1659                         goto get_pll_re_vco_clk_failed;
1660                 }
1661         }
1662
1663         /* get the clock handle of 120MHz clock source */
1664         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
1665         if (IS_ERR(tegra->pll_u_480M)) {
1666                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
1667                 err = PTR_ERR(tegra->pll_u_480M);
1668                 goto get_pll_u_480M_failed;
1669         }
1670
1671         /* get the clock handle of 12MHz clock source */
1672         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1673         if (IS_ERR(tegra->clk_m)) {
1674                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
1675                 err = PTR_ERR(tegra->clk_m);
1676                 goto clk_get_clk_m_failed;
1677         }
1678
1679         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
1680         if (IS_ERR(tegra->ss_src_clk)) {
1681                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
1682                 err = PTR_ERR(tegra->ss_src_clk);
1683                 tegra->ss_src_clk = NULL;
1684                 goto get_ss_src_clk_failed;
1685         }
1686
1687         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
1688         if (IS_ERR(tegra->host_clk)) {
1689                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
1690                 err = PTR_ERR(tegra->host_clk);
1691                 tegra->host_clk = NULL;
1692                 goto get_host_clk_failed;
1693         }
1694
1695         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
1696         if (IS_ERR(tegra->ss_clk)) {
1697                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
1698                 err = PTR_ERR(tegra->ss_clk);
1699                 tegra->ss_clk = NULL;
1700                 goto get_ss_clk_failed;
1701         }
1702
1703         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1704                 err = clk_enable(tegra->pll_re_vco_clk);
1705                 if (err) {
1706                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
1707                         goto enable_pll_re_vco_clk_failed;
1708                 }
1709         }
1710         return 0;
1711
1712 enable_pll_re_vco_clk_failed:
1713         tegra->ss_clk = NULL;
1714
1715 get_ss_clk_failed:
1716         tegra->host_clk = NULL;
1717
1718 get_host_clk_failed:
1719         tegra->ss_src_clk = NULL;
1720
1721 get_ss_src_clk_failed:
1722         tegra->clk_m = NULL;
1723
1724 clk_get_clk_m_failed:
1725         tegra->pll_u_480M = NULL;
1726
1727 get_pll_u_480M_failed:
1728         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1729                 tegra->pll_re_vco_clk = NULL;
1730
1731 get_pll_re_vco_clk_failed:
1732         tegra->emc_clk = NULL;
1733
1734         return err;
1735 }
1736
1737 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
1738 {
1739         clk_disable(tegra->ss_clk);
1740         clk_disable(tegra->host_clk);
1741         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1742                 clk_disable(tegra->pll_re_vco_clk);
1743         tegra->ss_clk = NULL;
1744         tegra->host_clk = NULL;
1745         tegra->ss_src_clk = NULL;
1746         tegra->clk_m = NULL;
1747         tegra->pll_u_480M = NULL;
1748         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1749                 tegra->pll_re_vco_clk = NULL;
1750 }
1751
1752 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
1753         bool enable)
1754 {
1755         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1756         u32 reg;
1757
1758         /* Issue is only applicable for T114 */
1759         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
1760                 return;
1761
1762         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1763                 reg = readl(tegra->padctl_base +
1764                         padregs->iophy_misc_pad_p0_ctl3_0);
1765                 if (enable) {
1766                         reg &= ~RX_IDLE_MODE;
1767                         reg |= RX_IDLE_MODE_OVRD;
1768                 } else {
1769                         reg |= RX_IDLE_MODE;
1770                         reg &= ~RX_IDLE_MODE_OVRD;
1771                 }
1772                 writel(reg, tegra->padctl_base +
1773                         padregs->iophy_misc_pad_p0_ctl3_0);
1774         }
1775
1776         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1777                 reg = readl(tegra->padctl_base +
1778                         padregs->iophy_misc_pad_p1_ctl3_0);
1779                 if (enable) {
1780                         reg &= ~RX_IDLE_MODE;
1781                         reg |= RX_IDLE_MODE_OVRD;
1782                 } else {
1783                         reg |= RX_IDLE_MODE;
1784                         reg &= ~RX_IDLE_MODE_OVRD;
1785                 }
1786                 writel(reg, tegra->padctl_base +
1787                         padregs->iophy_misc_pad_p1_ctl3_0);
1788
1789                 /* SATA lane also if USB3_SS port1 mapped to it */
1790                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
1791                                 tegra->bdata->lane_owner & BIT(0)) {
1792                         reg = readl(tegra->padctl_base +
1793                                 padregs->iophy_misc_pad_s0_ctl3_0);
1794                         if (enable) {
1795                                 reg &= ~RX_IDLE_MODE;
1796                                 reg |= RX_IDLE_MODE_OVRD;
1797                         } else {
1798                                 reg |= RX_IDLE_MODE;
1799                                 reg &= ~RX_IDLE_MODE_OVRD;
1800                         }
1801                         writel(reg, tegra->padctl_base +
1802                                 padregs->iophy_misc_pad_s0_ctl3_0);
1803                 }
1804         }
1805 }
1806
1807 /* Enable ss clk, host clk, falcon clk,
1808  * fs clk, dev clk, plle and refplle
1809  */
1810
1811 static int
1812 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
1813                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
1814 {
1815         int ret = 0;
1816         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
1817         int fw_req_rate = rate, cur_rate;
1818
1819         /* Do not handle clock change as needed for HS disconnect issue */
1820         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1821                 *sw_resp = CMD_DATA(fw_req_rate) | CMD_TYPE(MBOX_CMD_ACK);
1822                 return ret;
1823         }
1824
1825         /* frequency request from firmware is in KHz.
1826          * Convert it to MHz
1827          */
1828
1829         /* get current rate of clock */
1830         cur_rate = clk_get_rate(clk_handle);
1831         cur_rate /= 1000;
1832
1833         if (fw_req_rate == cur_rate) {
1834                 cmd_ack = MBOX_CMD_ACK;
1835
1836         } else {
1837
1838                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
1839                         /* Change SS clock source to CLK_M at 12MHz */
1840                         clk_set_parent(clk_handle, tegra->clk_m);
1841                         clk_set_rate(clk_handle, fw_req_rate * 1000);
1842
1843                         /* save leakage power when SS freq is being decreased */
1844                         tegra_xhci_rx_idle_mode_override(tegra, true);
1845                 } else if (clk_handle == tegra->ss_src_clk &&
1846                                 fw_req_rate == 120000) {
1847                         /* Change SS clock source to HSIC_480 at 120MHz */
1848                         clk_set_rate(clk_handle,  3000 * 1000);
1849                         clk_set_parent(clk_handle, tegra->pll_u_480M);
1850
1851                         /* clear ovrd bits when SS freq is being increased */
1852                         tegra_xhci_rx_idle_mode_override(tegra, false);
1853                 }
1854
1855                 cur_rate = (clk_get_rate(clk_handle) / 1000);
1856
1857                 if (cur_rate != fw_req_rate) {
1858                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
1859                                 cur_rate, fw_req_rate);
1860                         cmd_ack = MBOX_CMD_NACK;
1861                 }
1862         }
1863         *sw_resp = CMD_DATA(cur_rate) | CMD_TYPE(cmd_ack);
1864         return ret;
1865 }
1866
1867 static void tegra_xusb_set_bw(struct tegra_xhci_hcd *tegra, unsigned int bw)
1868 {
1869         unsigned int freq_khz;
1870
1871         freq_khz = tegra_emc_bw_to_freq_req(bw);
1872         clk_set_rate(tegra->emc_clk, freq_khz * 1000);
1873 }
1874
1875 static void tegra_xhci_save_dfe_context(struct tegra_xhci_hcd *tegra,
1876         u8 port)
1877 {
1878         struct xhci_hcd *xhci = tegra->xhci;
1879         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1880         u32 offset;
1881         u32 reg;
1882
1883         if (port > (XUSB_SS_PORT_COUNT - 1)) {
1884                 pr_err("%s invalid SS port number %u\n", __func__, port);
1885                 return;
1886         }
1887
1888         xhci_info(xhci, "saving restore DFE context for port %d\n", port);
1889
1890         /* if port1 is mapped to SATA lane then read from SATA register */
1891         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1892                         tegra->bdata->lane_owner & BIT(0))
1893                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1894         else
1895                 offset = MISC_PAD_CTL_6_0(port);
1896
1897         /*
1898          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
1899          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
1900          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
1901          */
1902         reg = readl(tegra->padctl_base + offset);
1903         reg &= ~MISC_OUT_SEL(~0);
1904         reg |= MISC_OUT_SEL(0x32);
1905         writel(reg, tegra->padctl_base + offset);
1906
1907         reg = readl(tegra->padctl_base + offset);
1908         tegra->sregs.tap1_val[port] = MISC_OUT_TAP_VAL(reg);
1909
1910         reg = readl(tegra->padctl_base + offset);
1911         reg &= ~MISC_OUT_SEL(~0);
1912         reg |= MISC_OUT_SEL(0x33);
1913         writel(reg, tegra->padctl_base + offset);
1914
1915         reg = readl(tegra->padctl_base + offset);
1916         tegra->sregs.amp_val[port] = MISC_OUT_AMP_VAL(reg);
1917
1918         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1919         reg &= ~DFE_CNTL_TAP_VAL(~0);
1920         reg |= DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
1921         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1922
1923         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1924         reg &= ~DFE_CNTL_AMP_VAL(~0);
1925         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]);
1926         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1927
1928         tegra->dfe_ctx_saved[port] = true;
1929 }
1930
1931 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
1932         u8 port)
1933 {
1934         struct xhci_hcd *xhci = tegra->xhci;
1935         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1936         u32 offset;
1937         u32 reg;
1938
1939         if (port > (XUSB_SS_PORT_COUNT - 1)) {
1940                 pr_err("%s invalid SS port number %u\n", __func__, port);
1941                 return;
1942         }
1943
1944         xhci_info(xhci, "saving restore CTLE context for port %d\n", port);
1945
1946         /* if port1 is mapped to SATA lane then read from SATA register */
1947         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1948                         tegra->bdata->lane_owner & BIT(0))
1949                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1950         else
1951                 offset = MISC_PAD_CTL_6_0(port);
1952
1953         /*
1954          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
1955          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
1956          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
1957          */
1958         reg = readl(tegra->padctl_base + offset);
1959         reg &= ~MISC_OUT_SEL(~0);
1960         reg |= MISC_OUT_SEL(0xa1);
1961         writel(reg, tegra->padctl_base + offset);
1962
1963         reg = readl(tegra->padctl_base + offset);
1964         reg &= ~MISC_OUT_SEL(~0);
1965         reg |= MISC_OUT_SEL(0x21);
1966         writel(reg, tegra->padctl_base + offset);
1967
1968         reg = readl(tegra->padctl_base + offset);
1969         tegra->sregs.ctle_g_val[port] = MISC_OUT_G_Z_VAL(reg);
1970
1971         reg = readl(tegra->padctl_base + offset);
1972         reg &= ~MISC_OUT_SEL(~0);
1973         reg |= MISC_OUT_SEL(0x48);
1974         writel(reg, tegra->padctl_base + offset);
1975
1976         reg = readl(tegra->padctl_base + offset);
1977         tegra->sregs.ctle_z_val[port] = MISC_OUT_G_Z_VAL(reg);
1978
1979         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1980         reg &= ~RX_EQ_Z_VAL(~0);
1981         reg |= RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]);
1982         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1983
1984         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1985         reg &= ~RX_EQ_G_VAL(~0);
1986         reg |= RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]);
1987         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1988
1989         tegra->ctle_ctx_saved[port] = true;
1990 }
1991
1992 static void tegra_xhci_restore_dfe_context(struct tegra_xhci_hcd *tegra,
1993         u8 port)
1994 {
1995         struct xhci_hcd *xhci = tegra->xhci;
1996         u32 reg;
1997
1998         /* don't restore if not saved */
1999         if (tegra->dfe_ctx_saved[port] == false)
2000                 return;
2001
2002         xhci_info(xhci, "restoring dfe context of port %d\n", port);
2003
2004         /* restore dfe_cntl for the port */
2005         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
2006         reg &= ~(DFE_CNTL_AMP_VAL(~0) |
2007                         DFE_CNTL_TAP_VAL(~0));
2008         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]) |
2009                 DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
2010         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
2011 }
2012
2013 void restore_ctle_context(struct tegra_xhci_hcd *tegra,
2014         u8 port)
2015 {
2016         struct xhci_hcd *xhci = tegra->xhci;
2017         u32 reg;
2018
2019         /* don't restore if not saved */
2020         if (tegra->ctle_ctx_saved[port] == false)
2021                 return;
2022
2023         xhci_info(xhci, "restoring CTLE context of port %d\n", port);
2024
2025         /* restore ctle for the port */
2026         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
2027         reg &= ~(RX_EQ_Z_VAL(~0) |
2028                         RX_EQ_G_VAL(~0));
2029         reg |= (RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]) |
2030                 RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]));
2031         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
2032 }
2033
2034 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
2035         u8 port)
2036 {
2037         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2038         u32 reg;
2039
2040         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2041         reg &= ~USB2_ULPI_PAD;
2042         reg |= USB2_ULPI_PAD_OWNER_XUSB;
2043         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2044
2045         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
2046         reg &= ~USB2_ULPI_PORT_CAP;
2047         reg |= (tegra->bdata->ulpicap << 24);
2048         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
2049         /* FIXME: Program below when more details available
2050          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
2051          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
2052          */
2053 }
2054
2055 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
2056         u8 port)
2057 {
2058         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2059         u32 reg;
2060         u32 ctl0_offset, ctl1_offset;
2061
2062         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2063         reg &= ~USB2_OTG_PAD_PORT_MASK(port);
2064         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
2065         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2066
2067         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
2068         reg &= ~USB2_PORT_CAP_MASK(port);
2069         reg |= USB2_PORT_CAP_HOST(port);
2070         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
2071
2072         /*
2073          * Modify only the bits which belongs to the port
2074          * and enable respective VBUS_PAD for the port
2075          */
2076         if (tegra->bdata->uses_external_pmic == false) {
2077                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2078                 reg &= ~(port == 2 ? OC_DET_VBUS_ENABLE2_OC_MAP :
2079                         port ? OC_DET_VBUS_ENABLE1_OC_MAP :
2080                                 OC_DET_VBUS_ENABLE0_OC_MAP);
2081
2082                 reg |= (port == 2) ? OC_DET_VBUS_EN2_OC_DETECTED_VBUS_PAD2 :
2083                         port ? OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1 :
2084                                 OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0;
2085                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
2086         }
2087         /*
2088          * enable respective VBUS_PAD if port is mapped to any SS port
2089          */
2090         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
2091         reg &= ~((port == 2) ? USB2_OC_MAP_PORT2 :
2092                 port ? USB2_OC_MAP_PORT1 : USB2_OC_MAP_PORT0);
2093         reg |= (0x4 | port) << (port * 3);
2094         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
2095
2096         ctl0_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl0_0 :
2097                         port ? padregs->usb2_otg_pad1_ctl0_0 :
2098                                 padregs->usb2_otg_pad0_ctl0_0;
2099         ctl1_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl1_0 :
2100                         port ? padregs->usb2_otg_pad1_ctl1_0 :
2101                                 padregs->usb2_otg_pad0_ctl1_0;
2102
2103         reg = readl(tegra->padctl_base + ctl0_offset);
2104         reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
2105                 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
2106                 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
2107
2108         reg |= tegra->soc_config->hs_slew;
2109         reg |= (port == 2) ? tegra->soc_config->ls_rslew_pad2 :
2110                         port ? tegra->soc_config->ls_rslew_pad1 :
2111                         tegra->soc_config->ls_rslew_pad0;
2112         reg |= (port == 2) ? tegra->cdata->hs_curr_level_pad2 :
2113                         port ? tegra->cdata->hs_curr_level_pad1 :
2114                         tegra->cdata->hs_curr_level_pad0;
2115         writel(reg, tegra->padctl_base + ctl0_offset);
2116
2117         reg = readl(tegra->padctl_base + ctl1_offset);
2118         reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
2119                 | USB2_OTG_PD_CHRP_FORCE_POWERUP
2120                 | USB2_OTG_PD_DISC_FORCE_POWERUP
2121                 | USB2_OTG_PD_DR);
2122         reg |= (tegra->cdata->hs_iref_cap << 9) |
2123                 (tegra->cdata->hs_term_range_adj << 3);
2124         writel(reg, tegra->padctl_base + ctl1_offset);
2125
2126         /*Release OTG port if not in host mode*/
2127
2128         if ((port == 0) && !is_otg_host(tegra))
2129                 tegra_xhci_release_otg_port(true);
2130 }
2131
2132 static inline bool xusb_use_sata_lane(struct tegra_xhci_hcd *tegra)
2133 {
2134         return ((XUSB_DEVICE_ID_T114 == tegra->device_id) ? false
2135         : ((tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
2136                 && (tegra->bdata->lane_owner & BIT(0))));
2137 }
2138
2139 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
2140         u8 port)
2141 {
2142         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2143         u32 ctl2_offset, ctl4_offset, ctl5_offset;
2144         u32 reg;
2145
2146         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
2147                         padregs->iophy_usb3_pad0_ctl2_0;
2148         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
2149                         padregs->iophy_usb3_pad0_ctl4_0;
2150         ctl5_offset = port ? padregs->iophy_misc_pad_p1_ctl5_0 :
2151                         padregs->iophy_misc_pad_p0_ctl5_0;
2152
2153         reg = readl(tegra->padctl_base + ctl2_offset);
2154         reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
2155                 IOPHY_USB3_CDRCNTL);
2156         reg |= tegra->soc_config->rx_wander | tegra->soc_config->rx_eq |
2157                 tegra->soc_config->cdr_cntl;
2158         writel(reg, tegra->padctl_base + ctl2_offset);
2159
2160         reg = readl(tegra->padctl_base + ctl4_offset);
2161         reg = tegra->soc_config->dfe_cntl;
2162         writel(reg, tegra->padctl_base + ctl4_offset);
2163
2164         reg = readl(tegra->padctl_base + ctl5_offset);
2165         reg |= RX_QEYE_EN;
2166         writel(reg, tegra->padctl_base + ctl5_offset);
2167
2168         reg = readl(tegra->padctl_base + MISC_PAD_CTL_2_0(port));
2169         reg &= ~SPARE_IN(~0);
2170         reg |= SPARE_IN(tegra->soc_config->spare_in);
2171         writel(reg, tegra->padctl_base + MISC_PAD_CTL_2_0(port));
2172
2173         if (xusb_use_sata_lane(tegra)) {
2174                 reg = readl(tegra->padctl_base + MISC_PAD_S0_CTL_5_0);
2175                 reg |= RX_QEYE_EN;
2176                 writel(reg, tegra->padctl_base + MISC_PAD_S0_CTL_5_0);
2177
2178                 reg = readl(tegra->padctl_base + MISC_PAD_S0_CTL_2_0);
2179                 reg &= ~SPARE_IN(~0);
2180                 reg |= SPARE_IN(tegra->soc_config->spare_in);
2181                 writel(reg, tegra->padctl_base + MISC_PAD_S0_CTL_2_0);
2182         }
2183
2184         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
2185         reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
2186         reg |= (tegra->bdata->ss_portmap &
2187                 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
2188         writel(reg, tegra->padctl_base + padregs->ss_port_map_0);
2189
2190         tegra_xhci_restore_dfe_context(tegra, port);
2191         tegra_xhci_restore_ctle_context(tegra, port);
2192 }
2193
2194 /* This function assigns the USB ports to the controllers,
2195  * then programs the port capabilities and pad parameters
2196  * of ports assigned to XUSB after booted to OS.
2197  */
2198 void
2199 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
2200 {
2201         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2202         u32 reg, oc_bits = 0;
2203         unsigned pad;
2204
2205         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2206         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
2207         reg |= tegra->cdata->hs_squelch_level | tegra->soc_config->hs_disc_lvl;
2208         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2209
2210         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
2211         reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3;
2212         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
2213         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
2214
2215         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2216         reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
2217         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2218                 reg |= OC_DET_VBUS_ENABLE2_OC_MAP;
2219         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2220
2221         /* check if over current seen. Clear if present */
2222         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2223                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2224         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2225                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2226         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2227                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2228
2229         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2230         if (reg & oc_bits) {
2231                 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
2232                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
2233
2234                 usleep_range(100, 200);
2235
2236                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2237                 if (reg & oc_bits)
2238                         xhci_info(tegra->xhci, "Over current still present\n");
2239         }
2240
2241         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
2242         reg = USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1;
2243         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2244                 reg |= USB2_OC_MAP_PORT2;
2245         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
2246
2247         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2248                 tegra_xhci_program_utmip_pad(tegra, 0);
2249         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2250                 tegra_xhci_program_utmip_pad(tegra, 1);
2251         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2252                 tegra_xhci_program_utmip_pad(tegra, 2);
2253
2254         for_each_enabled_hsic_pad(pad, tegra)
2255                 hsic_pad_enable(tegra, pad);
2256
2257         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
2258                 tegra_xhci_program_ulpi_pad(tegra, 0);
2259
2260         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
2261                 tegra_xhci_program_ss_pad(tegra, 0);
2262         } else {
2263                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
2264                 reg = readl(tegra->padctl_base +
2265                         padregs->iophy_misc_pad_p0_ctl3_0);
2266                 reg &= ~RX_IDLE_MODE;
2267                 reg |= RX_IDLE_MODE_OVRD;
2268                 writel(reg, tegra->padctl_base +
2269                         padregs->iophy_misc_pad_p0_ctl3_0);
2270         }
2271
2272         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
2273                 tegra_xhci_program_ss_pad(tegra, 1);
2274         } else {
2275                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
2276                 reg = readl(tegra->padctl_base +
2277                         padregs->iophy_misc_pad_p1_ctl3_0);
2278                 reg &= ~RX_IDLE_MODE;
2279                 reg |= RX_IDLE_MODE_OVRD;
2280                 writel(reg, tegra->padctl_base +
2281                         padregs->iophy_misc_pad_p1_ctl3_0);
2282
2283                 /* SATA lane also if USB3_SS port1 mapped to it but unused */
2284                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
2285                                 tegra->bdata->lane_owner & BIT(0)) {
2286                         reg = readl(tegra->padctl_base +
2287                                 padregs->iophy_misc_pad_s0_ctl3_0);
2288                         reg &= ~RX_IDLE_MODE;
2289                         reg |= RX_IDLE_MODE_OVRD;
2290                         writel(reg, tegra->padctl_base +
2291                                 padregs->iophy_misc_pad_s0_ctl3_0);
2292                 }
2293         }
2294         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2295                 tegra_xhci_setup_gpio_for_ss_lane(tegra);
2296                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
2297         }
2298 }
2299
2300 /* This function read XUSB registers and stores in device context */
2301 static void
2302 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
2303 {
2304
2305         /* a. Save the IPFS registers */
2306         tegra->sregs.msi_bar_sz =
2307                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2308
2309         tegra->sregs.msi_axi_barst =
2310                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2311
2312         tegra->sregs.msi_fpci_barst =
2313                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2314
2315         tegra->sregs.msi_vec0 =
2316                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2317
2318         tegra->sregs.msi_en_vec0 =
2319                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2320
2321         tegra->sregs.fpci_error_masks =
2322                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2323
2324         tegra->sregs.intr_mask =
2325                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2326
2327         tegra->sregs.ipfs_intr_enable =
2328                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2329
2330         tegra->sregs.ufpci_config =
2331                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2332
2333         tegra->sregs.clkgate_hysteresis =
2334                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2335
2336         tegra->sregs.xusb_host_mccif_fifo_cntrl =
2337                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2338
2339         /* b. Save the CFG registers */
2340
2341         tegra->sregs.hs_pls =
2342                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2343
2344         tegra->sregs.fs_pls =
2345                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2346
2347         tegra->sregs.hs_fs_speed =
2348                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2349
2350         tegra->sregs.hs_fs_pp =
2351                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2352
2353         tegra->sregs.cfg_aru =
2354                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2355
2356         tegra->sregs.cfg_order =
2357                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
2358
2359         tegra->sregs.cfg_fladj =
2360                 readl(tegra->fpci_base + XUSB_CFG_24);
2361
2362         tegra->sregs.cfg_sid =
2363                 readl(tegra->fpci_base + XUSB_CFG_16);
2364 }
2365
2366 /* This function restores XUSB registers from device context */
2367 static void
2368 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
2369 {
2370         /* Restore Cfg registers */
2371         writel(tegra->sregs.hs_pls,
2372                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2373
2374         writel(tegra->sregs.fs_pls,
2375                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2376
2377         writel(tegra->sregs.hs_fs_speed,
2378                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2379
2380         writel(tegra->sregs.hs_fs_pp,
2381                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2382
2383         writel(tegra->sregs.cfg_aru,
2384                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2385
2386         writel(tegra->sregs.cfg_order,
2387                 tegra->fpci_base + XUSB_CFG_FPCICFG);
2388
2389         writel(tegra->sregs.cfg_fladj,
2390                 tegra->fpci_base + XUSB_CFG_24);
2391
2392         writel(tegra->sregs.cfg_sid,
2393                 tegra->fpci_base + XUSB_CFG_16);
2394
2395         /* Restore IPFS registers */
2396
2397         writel(tegra->sregs.msi_bar_sz,
2398                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2399
2400         writel(tegra->sregs.msi_axi_barst,
2401                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2402
2403         writel(tegra->sregs.msi_fpci_barst,
2404                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2405
2406         writel(tegra->sregs.msi_vec0,
2407                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2408
2409         writel(tegra->sregs.msi_en_vec0,
2410                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2411
2412         writel(tegra->sregs.fpci_error_masks,
2413                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2414
2415         writel(tegra->sregs.intr_mask,
2416                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2417
2418         writel(tegra->sregs.ipfs_intr_enable,
2419                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2420
2421         writel(tegra->sregs.ufpci_config,
2422                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2423
2424         writel(tegra->sregs.clkgate_hysteresis,
2425                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2426
2427         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
2428                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2429 }
2430
2431 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
2432 {
2433         fw_message_send(tegra, MBOX_CMD_MSG_ENABLED, 0 /* no data needed */);
2434 }
2435
2436 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
2437 {
2438         struct platform_device *pdev = tegra->pdev;
2439         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
2440         u32 phys_addr_lo;
2441         u32 HwReg;
2442         u16 nblocks;
2443         time_t fw_time;
2444         struct tm fw_tm;
2445         u8 hc_caplength;
2446         u32 usbsts, count = 0xff;
2447         struct xhci_cap_regs __iomem *cap_regs;
2448         struct xhci_op_regs __iomem *op_regs;
2449
2450         /* enable mbox interrupt */
2451         writel(readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD) | MBOX_INT_EN,
2452                 tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2453
2454         /* First thing, reset the ARU. By the time we get to
2455          * loading boot code below, reset would be complete.
2456          * alternatively we can busy wait on rst pending bit.
2457          */
2458         /* Don't reset during ELPG/LP0 exit path */
2459         if (resetARU) {
2460                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
2461                 usleep_range(1000, 2000);
2462         }
2463
2464         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
2465                 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
2466                                 csb_read(tegra, XUSB_FALC_CPUCTL));
2467                 return 0;
2468         }
2469
2470         /* update the phys_log_buffer and total_entries here */
2471         cfg_tbl->phys_addr_log_buffer = tegra->log.phys_addr;
2472         cfg_tbl->total_log_entries = FW_LOG_COUNT;
2473
2474         phys_addr_lo = tegra->firmware.dma;
2475         phys_addr_lo += sizeof(struct cfgtbl);
2476
2477         /* Program the size of DFI into ILOAD_ATTR */
2478         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
2479
2480         /* Boot code of the firmware reads the ILOAD_BASE_LO register
2481          * to get to the start of the dfi in system memory.
2482          */
2483         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
2484
2485         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
2486         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
2487
2488         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
2489         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
2490
2491         /* Invalidate L2IMEM. */
2492         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
2493
2494         /* Initiate fetch of Bootcode from system memory into L2IMEM.
2495          * Program BootCode location and size in system memory.
2496          */
2497         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
2498                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
2499                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
2500         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
2501                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
2502                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
2503         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
2504
2505         /* Trigger L2IMEM Load operation. */
2506         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
2507
2508         /* Setup Falcon Auto-fill */
2509         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
2510         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
2511                 nblocks += 1;
2512         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
2513
2514         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
2515         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
2516                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
2517         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
2518
2519         csb_write(tegra, XUSB_FALC_DMACTL, 0);
2520         msleep(50);
2521
2522         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
2523
2524         /* Start Falcon CPU */
2525         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
2526         usleep_range(1000, 2000);
2527
2528         fw_time = cfg_tbl->fwimg_created_time;
2529         time_to_tm(fw_time, 0, &fw_tm);
2530         dev_info(&pdev->dev,
2531                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
2532                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
2533                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
2534                 fw_tm.tm_min, fw_tm.tm_sec,
2535                 csb_read(tegra, XUSB_FALC_CPUCTL));
2536
2537         dev_dbg(&pdev->dev, "num_hsic_port %d\n", cfg_tbl->num_hsic_port);
2538
2539         /* return fail if firmware status is not good */
2540         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
2541                 return -EFAULT;
2542
2543         cap_regs = IO_ADDRESS(tegra->host_phy_base);
2544         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
2545         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
2546
2547         /* wait for USBSTS_CNR to get set */
2548         do {
2549                 usbsts = ioread32(&op_regs->status);
2550         } while ((usbsts & STS_CNR) && count--);
2551
2552         if (!count && (usbsts & STS_CNR)) {
2553                 dev_err(&pdev->dev, "Controller not ready\n");
2554                 return -EFAULT;
2555         }
2556
2557         return 0;
2558 }
2559
2560 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
2561         bool release)
2562 {
2563         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2564         u32 reg;
2565
2566         /* Issue is only applicable for T114 */
2567         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
2568                 return;
2569
2570         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2571         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2572                         USB2_OTG_PAD_PORT_MASK(2));
2573
2574         if (!release) {
2575                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2576                         if (is_otg_host(tegra))
2577                                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2578                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2579                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2580                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2581                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2582         }
2583
2584         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2585 }
2586 /* SS ELPG Entry initiated by fw */
2587 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
2588 {
2589         struct xhci_hcd *xhci = tegra->xhci;
2590         u32 ret = 0;
2591
2592         must_have_sync_lock(tegra);
2593
2594         /* update maximum BW requirement to 0 */
2595         tegra_xusb_set_bw(tegra, 0);
2596
2597         /* This is SS partition ELPG entry
2598          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
2599          */
2600
2601         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
2602          * only if it is sw initiated one
2603          */
2604
2605         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
2606          * SuperSpeed partition ELPG entry via mailbox protocol
2607          */
2608
2609         /* STEP 2: xHCI PEP driver and XUSB device mode driver
2610          * enable the XUSB wakeup interrupts for the SuperSpeed
2611          * and USB2.0 ports assigned to host.Section 4.1 Step 3
2612          */
2613         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2614
2615         /* STEP 3: xHCI PEP driver initiates the signal sequence
2616          * to enable the XUSB SSwake detection logic for the
2617          * SuperSpeed ports assigned to host.Section 4.1 Step 4
2618          */
2619         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, true);
2620
2621         /* STEP 4: System Power Management driver asserts reset
2622          * to XUSB SuperSpeed partition then disables its clocks
2623          */
2624         tegra_periph_reset_assert(tegra->ss_clk);
2625         clk_disable(tegra->ss_clk);
2626
2627         usleep_range(100, 200);
2628
2629         /* STEP 5: System Power Management driver disables the
2630          * XUSB SuperSpeed partition power rails.
2631          */
2632         debug_print_portsc(xhci);
2633
2634         /* tegra_powergate_partition also does partition reset assert */
2635         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
2636         if (ret) {
2637                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
2638                                 __func__);
2639                 /* TODO: error recovery? */
2640         }
2641         tegra->ss_pwr_gated = true;
2642
2643         /* STEP 6: xHCI PEP driver initiates the signal sequence
2644          * to enable the XUSB SSwake detection logic for the
2645          * SuperSpeed ports assigned to host.Section 4.1 Step 7
2646          */
2647         tegra_xhci_ss_vcore(tegra->bdata->portmap, true);
2648
2649         return ret;
2650 }
2651
2652 /* Host ELPG Entry */
2653 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
2654 {
2655         struct xhci_hcd *xhci = tegra->xhci;
2656         u32 ret;
2657
2658         must_have_sync_lock(tegra);
2659
2660         /* If ss is already powergated skip ss ctx save stuff */
2661         if (tegra->ss_pwr_gated) {
2662                 xhci_info(xhci, "%s: SS partition is already powergated\n",
2663                         __func__);
2664         } else {
2665                 ret = tegra_xhci_ss_elpg_entry(tegra);
2666                 if (ret) {
2667                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
2668                                 __func__, ret);
2669                         return ret;
2670                 }
2671         }
2672
2673         /* 1. IS INTR PENDING INT_PENDING=1 ? */
2674
2675         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
2676         tegra_xhci_save_xusb_ctx(tegra);
2677
2678         /* calculate rctrl_val and tctrl_val */
2679         tegra_xhci_war_for_tctrl_rctrl(tegra);
2680
2681         pmc_setup_wake_detect(tegra);
2682
2683         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2684         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2685                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2686
2687         /* tegra_powergate_partition also does partition reset assert */
2688         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
2689         if (ret) {
2690                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2691                         __func__, ret);
2692                 /* TODO: error handling? */
2693                 return ret;
2694         }
2695         tegra->host_pwr_gated = true;
2696         clk_disable(tegra->host_clk);
2697
2698         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2699                 clk_disable(tegra->pll_re_vco_clk);
2700         clk_disable(tegra->emc_clk);
2701         /* set port ownership to SNPS */
2702         tegra_xhci_release_port_ownership(tegra, true);
2703
2704         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2705                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2706
2707         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
2708         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
2709                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
2710         return ret;
2711 }
2712
2713 /* SS ELPG Exit triggered by PADCTL irq */
2714 /**
2715  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
2716  *
2717  * This function must be called with tegra->sync_lock acquired.
2718  *
2719  * @tegra: xhci controller context
2720  * @return 0 for success, or error numbers
2721  */
2722 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2723 {
2724         struct xhci_hcd *xhci = tegra->xhci;
2725         int ret = 0;
2726
2727         must_have_sync_lock(tegra);
2728
2729         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
2730                         tegra->hs_wake_event || tegra->host_resume_req)) {
2731
2732                 /*
2733                  * PWR_UNGATE SS partition. XUSBA
2734                  * tegra_unpowergate_partition also does partition reset
2735                  * deassert
2736                  */
2737                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
2738                 if (ret) {
2739                         xhci_err(xhci,
2740                         "%s: could not unpowergate xusba partition %d\n",
2741                         __func__, ret);
2742                         goto out;
2743                 }
2744                 if (tegra->ss_wake_event)
2745                         tegra->ss_wake_event = false;
2746
2747         } else {
2748                 xhci_info(xhci, "%s: ss already power gated\n",
2749                         __func__);
2750                 return ret;
2751         }
2752
2753         /* Step 3: Enable clock to ss partition */
2754         clk_enable(tegra->ss_clk);
2755
2756         /* Step 4: Disable ss wake detection logic */
2757         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2758
2759         /* Step 4.1: Disable ss wake detection logic */
2760         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
2761
2762         /* wait 150us */
2763         usleep_range(150, 200);
2764
2765         /* Step 4.2: Disable ss wake detection logic */
2766         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
2767
2768         /* Step 6 Deassert reset for ss clks */
2769         tegra_periph_reset_deassert(tegra->ss_clk);
2770
2771         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
2772         tegra->ss_pwr_gated = false;
2773 out:
2774         return ret;
2775 }
2776
2777 static void ss_partition_elpg_exit_work(struct work_struct *work)
2778 {
2779         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2780                 ss_elpg_exit_work);
2781
2782         mutex_lock(&tegra->sync_lock);
2783         tegra_xhci_ss_partition_elpg_exit(tegra);
2784         mutex_unlock(&tegra->sync_lock);
2785 }
2786
2787 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
2788 static void update_remote_wakeup_ports(struct tegra_xhci_hcd *tegra)
2789 {
2790         struct xhci_hcd *xhci = tegra->xhci;
2791         u32 wake2_status;
2792         int port;
2793
2794 #define PMC_WAKE2_STATUS        0x168
2795 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
2796
2797         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
2798
2799         if (wake2_status & PADCTL_WAKE) {
2800                 /* FIXME: This is customized for Dalmore, find a generic way */
2801                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
2802                 /* clear wake status */
2803                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
2804         }
2805
2806         /* set all usb2 ports with RESUME link state as wakup ports  */
2807         for (port = 0; port < xhci->num_usb2_ports; port++) {
2808                 u32 portsc = xhci_readl(xhci, xhci->usb2_ports[port]);
2809                 if ((portsc & PORT_PLS_MASK) == XDEV_RESUME)
2810                         set_bit(port, &tegra->usb2_rh_remote_wakeup_ports);
2811         }
2812
2813         xhci_dbg(xhci, "%s: usb2 roothub remote_wakeup_ports 0x%lx\n",
2814                         __func__, tegra->usb2_rh_remote_wakeup_ports);
2815         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
2816                         __func__, tegra->usb3_rh_remote_wakeup_ports);
2817 }
2818
2819 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
2820 {
2821         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2822         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2823         int port, num_ports;
2824         unsigned long *remote_wakeup_ports;
2825         u32 portsc;
2826         __le32 __iomem  **port_array;
2827         unsigned char *rh;
2828         unsigned int retry = 64;
2829         struct xhci_bus_state *bus_state;
2830
2831         bus_state = &xhci->bus_state[hcd_index(hcd)];
2832
2833         if (hcd == xhci->shared_hcd) {
2834                 port_array = xhci->usb3_ports;
2835                 num_ports = xhci->num_usb3_ports;
2836                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
2837                 rh = "usb3 roothub";
2838         } else {
2839                 port_array = xhci->usb2_ports;
2840                 num_ports = xhci->num_usb2_ports;
2841                 remote_wakeup_ports = &tegra->usb2_rh_remote_wakeup_ports;
2842                 rh = "usb2 roothub";
2843         }
2844
2845         while (*remote_wakeup_ports && retry--) {
2846                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
2847                         bool can_continue;
2848
2849                         portsc = xhci_readl(xhci, port_array[port]);
2850
2851                         if (!(portsc & PORT_CONNECT)) {
2852                                 /* nothing to do if already disconnected */
2853                                 clear_bit(port, remote_wakeup_ports);
2854                                 continue;
2855                         }
2856
2857                         if (hcd == xhci->shared_hcd) {
2858                                 can_continue =
2859                                         (portsc & PORT_PLS_MASK) == XDEV_U0;
2860                         } else {
2861                                 unsigned long flags;
2862
2863                                 spin_lock_irqsave(&xhci->lock, flags);
2864                                 can_continue =
2865                                 test_bit(port, &bus_state->resuming_ports);
2866                                 spin_unlock_irqrestore(&xhci->lock, flags);
2867                         }
2868
2869                         if (can_continue)
2870                                 clear_bit(port, remote_wakeup_ports);
2871                         else
2872                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
2873                                         __func__, rh, port, portsc);
2874                 }
2875
2876                 if (*remote_wakeup_ports)
2877                         msleep(20); /* give some time, irq will direct U0 */
2878         }
2879
2880         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
2881                         *remote_wakeup_ports);
2882 }
2883
2884 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
2885 {
2886         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2887         u32 reg, utmip_rctrl_val, utmip_tctrl_val, pad_mux, portmux, portowner;
2888
2889         portmux = USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1);
2890         portowner = USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
2891                         USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2892
2893         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2894                 portmux |= USB2_OTG_PAD_PORT_MASK(2);
2895                 portowner |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2896         }
2897
2898         /* Use xusb padctl space only when xusb owns all UTMIP port */
2899         pad_mux = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2900         if ((pad_mux & portmux) == portowner) {
2901                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
2902                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
2903                  */
2904                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2905                 reg &= ~((1 << 12) | (1 << 13));
2906                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2907
2908                 /* wait 20us */
2909                 usleep_range(20, 30);
2910
2911                 /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
2912                  * :: TCTRL and RCTRL
2913                  */
2914                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl1_0);
2915                 utmip_rctrl_val = RCTRL(reg);
2916                 utmip_tctrl_val = TCTRL(reg);
2917
2918                 /*
2919                  * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
2920                  * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
2921                  */
2922                 utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
2923                 utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
2924                 utmi_phy_update_trking_data(utmip_tctrl_val, utmip_rctrl_val);
2925                 xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
2926                                         utmip_rctrl_val, utmip_tctrl_val);
2927
2928                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
2929                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
2930                  */
2931                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2932                 reg |= (1 << 13);
2933                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2934
2935                 /* Program these values into PMC regiseter and program the
2936                  * PMC override.
2937                  */
2938                 reg = PMC_TCTRL_VAL(utmip_tctrl_val) |
2939                                 PMC_RCTRL_VAL(utmip_rctrl_val);
2940                 tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG,
2941                                         0xffffffff, reg);
2942                 reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
2943                 tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
2944         } else {
2945                 /* Use common PMC API to use SNPS register space */
2946                 utmi_phy_set_snps_trking_data();
2947         }
2948 }
2949
2950 /* Host ELPG Exit triggered by PADCTL irq */
2951 /**
2952  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
2953  *
2954  * This function must be called with tegra->sync_lock acquired.
2955  *
2956  * @tegra: xhci controller context
2957  * @return 0 for success, or error numbers
2958  */
2959 static int
2960 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2961 {
2962         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2963         struct xhci_hcd *xhci = tegra->xhci;
2964         int ret = 0;
2965
2966         must_have_sync_lock(tegra);
2967
2968         if (!tegra->hc_in_elpg)
2969                 return 0;
2970
2971         clk_enable(tegra->emc_clk);
2972         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2973                 clk_enable(tegra->pll_re_vco_clk);
2974
2975         if (tegra->lp0_exit) {
2976                 u32 reg, oc_bits = 0;
2977
2978                 /* Issue is only applicable for T114 */
2979                 if (XUSB_DEVICE_ID_T114 == tegra->device_id)
2980                         tegra_xhci_war_for_tctrl_rctrl(tegra);
2981                 /* check if over current seen. Clear if present */
2982                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2983                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2984                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2985                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2986                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2987                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2988
2989                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2990                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
2991                 if (reg & oc_bits) {
2992                         xhci_info(xhci, "Over current detected. Clearing...\n");
2993                         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2994
2995                         usleep_range(100, 200);
2996
2997                         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2998                         if (reg & oc_bits)
2999                                 xhci_info(xhci, "Over current still present\n");
3000                 }
3001                 tegra_xhci_padctl_portmap_and_caps(tegra);
3002                 /* release clamps post deassert */
3003                 tegra->lp0_exit = false;
3004         }
3005
3006         /* Clear FLUSH_ENABLE of MC client */
3007         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
3008
3009         /* set port ownership back to xusb */
3010         tegra_xhci_release_port_ownership(tegra, false);
3011
3012         /*
3013          * PWR_UNGATE Host partition. XUSBC
3014          * tegra_unpowergate_partition also does partition reset deassert
3015          */
3016         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3017         if (ret) {
3018                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
3019                         __func__, ret);
3020                 goto out;
3021         }
3022         clk_enable(tegra->host_clk);
3023
3024         /* Step 4: Deassert reset to host partition clk */
3025         tegra_periph_reset_deassert(tegra->host_clk);
3026
3027         /* Step 6.1: IPFS and XUSB BAR initialization */
3028         tegra_xhci_cfg(tegra);
3029
3030         /* Step 6.2: IPFS and XUSB related restore */
3031         tegra_xhci_restore_ctx(tegra);
3032
3033         /* Step 8: xhci spec related ctx restore
3034          * will be done in xhci_resume().Do it here.
3035          */
3036
3037         tegra_xhci_ss_partition_elpg_exit(tegra);
3038
3039         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
3040         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
3041                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
3042                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
3043         }
3044
3045         /* clear ovrd bits */
3046         tegra_xhci_rx_idle_mode_override(tegra, false);
3047
3048         /* Load firmware */
3049         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
3050                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
3051                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
3052                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
3053                         __func__,
3054                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
3055                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
3056                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
3057                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
3058                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
3059                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
3060                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
3061                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
3062                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
3063         debug_print_portsc(xhci);
3064
3065         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
3066         if (ret < 0) {
3067                 xhci_err(xhci, "%s: failed to load firmware %d\n",
3068                         __func__, ret);
3069                 goto out;
3070         }
3071
3072         pmc_disable_bus_ctrl(tegra);
3073
3074         tegra->hc_in_elpg = false;
3075         ret = xhci_resume(tegra->xhci, 0);
3076         if (ret) {
3077                 xhci_err(xhci, "%s: could not resume right %d\n",
3078                                 __func__, ret);
3079                 goto out;
3080         }
3081
3082         update_remote_wakeup_ports(tegra);
3083
3084         if (tegra->hs_wake_event)
3085                 tegra->hs_wake_event = false;
3086
3087         if (tegra->host_resume_req)
3088                 tegra->host_resume_req = false;
3089
3090         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
3091                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
3092
3093         tegra->host_pwr_gated = false;
3094 out:
3095         return ret;
3096 }
3097
3098 static void host_partition_elpg_exit_work(struct work_struct *work)
3099 {
3100         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3101                 host_elpg_exit_work);
3102
3103         mutex_lock(&tegra->sync_lock);
3104         tegra_xhci_host_partition_elpg_exit(tegra);
3105         mutex_unlock(&tegra->sync_lock);
3106 }
3107
3108 /* Mailbox handling function. This function handles requests
3109  * from firmware and communicates with clock and powergating
3110  * module to alter clock rates and to power gate/ungate xusb
3111  * partitions.
3112  *
3113  * Following is the structure of mailbox messages.
3114  * bit 31:28 - msg type
3115  * bits 27:0 - mbox data
3116  * FIXME:  Check if we can just call clock functions like below
3117  * or should we schedule it for calling later ?
3118  */
3119
3120 static void
3121 tegra_xhci_process_mbox_message(struct work_struct *work)
3122 {
3123         u32 sw_resp = 0, cmd, data_in, fw_msg;
3124         int ret = 0;
3125         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3126                                         mbox_work);
3127         struct xhci_hcd *xhci = tegra->xhci;
3128         int pad, port;
3129         unsigned long ports;
3130
3131         mutex_lock(&tegra->mbox_lock);
3132
3133         /* get the mbox message from firmware */
3134         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
3135
3136         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3137         if (data_in) {
3138                 dev_warn(&tegra->pdev->dev, "%s data_in 0x%x\n",
3139                         __func__, data_in);
3140                 mutex_unlock(&tegra->mbox_lock);
3141                 return;
3142         }
3143
3144         /* get cmd type and cmd data */
3145         tegra->cmd_type = (fw_msg >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
3146         tegra->cmd_data = (fw_msg >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
3147
3148         /* decode the message and make appropriate requests to
3149          * clock or powergating module.
3150          */
3151
3152         switch (tegra->cmd_type) {
3153         case MBOX_CMD_INC_FALC_CLOCK:
3154         case MBOX_CMD_DEC_FALC_CLOCK:
3155                 ret = tegra_xusb_request_clk_rate(
3156                                 tegra,
3157                                 tegra->falc_clk,
3158                                 tegra->cmd_data,
3159                                 &sw_resp);
3160                 if (ret)
3161                         xhci_err(xhci, "%s: could not set required falc rate\n",
3162                                 __func__);
3163                 goto send_sw_response;
3164         case MBOX_CMD_INC_SSPI_CLOCK:
3165         case MBOX_CMD_DEC_SSPI_CLOCK:
3166                 ret = tegra_xusb_request_clk_rate(
3167                                 tegra,
3168                                 tegra->ss_src_clk,
3169                                 tegra->cmd_data,
3170                                 &sw_resp);
3171                 if (ret)
3172                         xhci_err(xhci, "%s: could not set required ss rate.\n",
3173                                 __func__);
3174                 goto send_sw_response;
3175
3176         case MBOX_CMD_SET_BW:
3177                 /* fw sends BW request in MByte/sec */
3178                 mutex_lock(&tegra->sync_lock);
3179                 tegra_xusb_set_bw(tegra, tegra->cmd_data << 10);
3180                 mutex_unlock(&tegra->sync_lock);
3181                 break;
3182
3183         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
3184                 tegra_xhci_save_dfe_context(tegra, tegra->cmd_data);
3185                 tegra_xhci_save_ctle_context(tegra, tegra->cmd_data);
3186                 sw_resp = CMD_DATA(tegra->cmd_data) | CMD_TYPE(MBOX_CMD_ACK);
3187                 goto send_sw_response;
3188
3189         case MBOX_CMD_STAR_HSIC_IDLE:
3190                 ports = tegra->cmd_data;
3191                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3192                         pad = port_to_hsic_pad(port - 1);
3193                         mutex_lock(&tegra->sync_lock);
3194                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
3195                         mutex_unlock(&tegra->sync_lock);
3196                         if (ret)
3197                                 break;
3198                 }
3199
3200                 sw_resp = CMD_DATA(tegra->cmd_data);
3201                 if (!ret)
3202                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3203                 else
3204                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3205
3206                 goto send_sw_response;
3207
3208         case MBOX_CMD_STOP_HSIC_IDLE:
3209                 ports = tegra->cmd_data;
3210                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3211                         pad = port_to_hsic_pad(port - 1);
3212                         mutex_lock(&tegra->sync_lock);
3213                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_DISABLE);
3214                         mutex_unlock(&tegra->sync_lock);
3215                         if (ret)
3216                                 break;
3217                 }
3218
3219                 sw_resp = CMD_DATA(tegra->cmd_data);
3220                 if (!ret)
3221                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3222                 else
3223                         sw_resp |= CMD_TYPE(MBOX_CMD_NACK);
3224                 goto send_sw_response;
3225
3226         case MBOX_CMD_ACK:
3227                 xhci_dbg(xhci, "%s firmware responds with ACK\n", __func__);
3228                 break;
3229         case MBOX_CMD_NACK:
3230                 xhci_warn(xhci, "%s firmware responds with NACK\n", __func__);
3231                 break;
3232         default:
3233                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
3234                                 __func__, tegra->cmd_type);
3235         }
3236
3237         /* clear MBOX_SMI_INT_EN bit */
3238         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3239         cmd &= ~MBOX_SMI_INT_EN;
3240         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3241
3242         /* clear mailbox ownership */
3243         writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
3244
3245         mutex_unlock(&tegra->mbox_lock);
3246         return;
3247
3248 send_sw_response:
3249         if (((sw_resp >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK) == MBOX_CMD_NACK)
3250                 xhci_err(xhci, "%s respond fw message 0x%x with NAK\n",
3251                                 __func__, fw_msg);
3252
3253         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3254         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3255         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
3256         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3257
3258         mutex_unlock(&tegra->mbox_lock);
3259 }
3260
3261 static irqreturn_t pmc_usb_phy_wake_isr(int irq, void *data)
3262 {
3263         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) data;
3264         struct xhci_hcd *xhci = tegra->xhci;
3265
3266         xhci_dbg(xhci, "%s irq %d", __func__, irq);
3267         return IRQ_HANDLED;
3268 }
3269
3270 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
3271 {
3272         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3273         struct xhci_hcd *xhci = tegra->xhci;
3274         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3275         u32 elpg_program0 = 0;
3276
3277         spin_lock(&tegra->lock);
3278
3279         tegra->last_jiffies = jiffies;
3280
3281         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
3282         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
3283
3284         /* Clear the interrupt cause. We already read the intr status. */
3285         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3286         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3287
3288         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
3289         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
3290                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
3291         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
3292                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
3293         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
3294                 __func__,
3295                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad0_ctl0_0));
3296         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
3297                 __func__,
3298                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad1_ctl0_0));
3299         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
3300                 __func__,
3301                 readl(tegra->padctl_base + padregs->usb2_bchrg_bias_pad_0));
3302
3303         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
3304                 tegra->ss_wake_event = true;
3305         else if (elpg_program0 & (USB2_PORT0_WAKEUP_EVENT |
3306                         USB2_PORT1_WAKEUP_EVENT |
3307                         USB2_PORT2_WAKEUP_EVENT |
3308                         USB2_HSIC_PORT0_WAKEUP_EVENT |
3309                         USB2_HSIC_PORT1_WAKEUP_EVENT))
3310                 tegra->hs_wake_event = true;
3311
3312         if (tegra->ss_wake_event || tegra->hs_wake_event) {
3313                 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
3314                         xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
3315                         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3316                 } else if (tegra->ss_pwr_gated
3317                                 && tegra->host_pwr_gated) {
3318                         xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
3319                                 __func__);
3320                         schedule_work(&tegra->host_elpg_exit_work);
3321                 }
3322         } else {
3323                 xhci_err(xhci, "error: wake due to no hs/ss event\n");
3324                 tegra_usb_pad_reg_write(padregs->elpg_program_0, 0xffffffff);
3325         }
3326         spin_unlock(&tegra->lock);
3327         return IRQ_HANDLED;
3328 }
3329
3330 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
3331 {
3332         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3333         u32 temp;
3334
3335         spin_lock(&tegra->lock);
3336
3337         /* clear the mbox intr status 1st thing. Other
3338          * bits are W1C bits, so just write to SMI bit.
3339          */
3340
3341         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3342
3343         /* write 1 to clear SMI INTR en bit ( bit 3 ) */
3344         temp = MBOX_SMI_INTR_EN;
3345         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3346
3347         schedule_work(&tegra->mbox_work);
3348
3349         spin_unlock(&tegra->lock);
3350         return IRQ_HANDLED;
3351 }
3352
3353 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
3354 {
3355         /*
3356          * As of now platform drivers don't provide MSI support so we ensure
3357          * here that the generic code does not try to make a pci_dev from our
3358          * dev struct in order to setup MSI
3359          */
3360         xhci->quirks |= XHCI_PLAT;
3361         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
3362 }
3363
3364 /* called during probe() after chip reset completes */
3365 static int xhci_plat_setup(struct usb_hcd *hcd)
3366 {
3367         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
3368 }
3369
3370 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
3371         int num, void __iomem **region)
3372 {
3373         struct resource *res;
3374         void __iomem *mem;
3375
3376         res = platform_get_resource(pdev, IORESOURCE_MEM, num);
3377         if (!res) {
3378                 dev_err(&pdev->dev, "memory resource %d doesn't exist\n", num);
3379                 return -ENODEV;
3380         }
3381
3382         mem = devm_request_and_ioremap(&pdev->dev, res);
3383         if (!mem) {
3384                 dev_err(&pdev->dev, "failed to ioremap for %d\n", num);
3385                 return -EFAULT;
3386         }
3387         *region = mem;
3388
3389         return 0;
3390 }
3391
3392 static int tegra_xhci_request_irq(struct platform_device *pdev,
3393         int num, irq_handler_t handler, unsigned long irqflags,
3394         const char *devname, int *irq_no)
3395 {
3396         int ret;
3397         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3398         struct resource *res;
3399
3400         res = platform_get_resource(pdev, IORESOURCE_IRQ, num);
3401         if (!res) {
3402                 dev_err(&pdev->dev, "irq resource %d doesn't exist\n", num);
3403                 return -ENODEV;
3404         }
3405
3406         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
3407                         devname, tegra);
3408         if (ret != 0) {
3409                 dev_err(&pdev->dev,
3410                         "failed to request_irq for %s (irq %d), error = %d\n",
3411                         devname, (int)res->start, ret);
3412                 return ret;
3413         }
3414         *irq_no = res->start;
3415
3416         return 0;
3417 }
3418
3419 #ifdef CONFIG_PM
3420
3421 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
3422 {
3423         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3424         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3425         int err = 0;
3426         unsigned long flags;
3427
3428         mutex_lock(&tegra->sync_lock);
3429
3430         if (xhci->shared_hcd == hcd) {
3431                 tegra->usb3_rh_suspend = true;
3432                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3433         } else if (xhci->main_hcd == hcd) {
3434                 tegra->usb2_rh_suspend = true;
3435                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3436         }
3437
3438         WARN_ON(tegra->hc_in_elpg);
3439
3440         /* suspend xhci bus. This will also set remote mask */
3441         err = xhci_bus_suspend(hcd);
3442         if (err) {
3443                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
3444                                 __func__, err);
3445                 goto xhci_bus_suspend_failed;
3446         }
3447
3448         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
3449                 goto done; /* one of the root hubs is still working */
3450
3451         spin_lock_irqsave(&tegra->lock, flags);
3452         tegra->hc_in_elpg = true;
3453         spin_unlock_irqrestore(&tegra->lock, flags);
3454
3455         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3456
3457         /* save xhci spec ctx. Already done by xhci_suspend */
3458         err = xhci_suspend(tegra->xhci);
3459         if (err) {
3460                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
3461                 goto xhci_suspend_failed;
3462         }
3463
3464         /* Powergate host. Include ss power gate if not already done */
3465         err = tegra_xhci_host_elpg_entry(tegra);
3466         if (err) {
3467                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
3468                                 __func__, err);
3469                 goto tegra_xhci_host_elpg_entry_failed;
3470         }
3471
3472         /* At this point,ensure ss/hs intr enables are always on */
3473         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
3474         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
3475
3476         /* In ELPG, firmware log context is gone. Rewind shared log buffer. */
3477         if (fw_log_wait_empty_timeout(tegra, 100))
3478                 xhci_warn(xhci, "%s still has logs\n", __func__);
3479         tegra->log.dequeue = tegra->log.virt_addr;
3480         tegra->log.seq = 0;
3481
3482 done:
3483         /* pads are disabled only if usb2 root hub in xusb is idle */
3484         /* pads will actually be disabled only when all usb2 ports are idle */
3485         if (xhci->main_hcd == hcd) {
3486                 utmi_phy_pad_disable();
3487                 utmi_phy_iddq_override(true);
3488         }
3489         mutex_unlock(&tegra->sync_lock);
3490         return 0;
3491
3492 tegra_xhci_host_elpg_entry_failed:
3493
3494 xhci_suspend_failed:
3495         tegra->hc_in_elpg = false;
3496 xhci_bus_suspend_failed:
3497         if (xhci->shared_hcd == hcd)
3498                 tegra->usb3_rh_suspend = false;
3499         else if (xhci->main_hcd == hcd)
3500                 tegra->usb2_rh_suspend = false;
3501
3502         mutex_unlock(&tegra->sync_lock);
3503         return err;
3504 }
3505
3506 /* First, USB2HCD and then USB3HCD resume will be called */
3507 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
3508 {
3509         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3510         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3511         int err = 0;
3512
3513         mutex_lock(&tegra->sync_lock);
3514
3515         tegra->host_resume_req = true;
3516
3517         if (xhci->shared_hcd == hcd)
3518                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3519         else if (xhci->main_hcd == hcd)
3520                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3521
3522         /* pads are disabled only if usb2 root hub in xusb is idle */
3523         /* pads will actually be disabled only when all usb2 ports are idle */
3524         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
3525                 utmi_phy_pad_enable();
3526                 utmi_phy_iddq_override(false);
3527         }
3528         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
3529                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
3530                         tegra_xhci_host_partition_elpg_exit(tegra);
3531         }
3532
3533          /* handle remote wakeup before resuming bus */
3534         wait_remote_wakeup_ports(hcd);
3535
3536         err = xhci_bus_resume(hcd);
3537         if (err) {
3538                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
3539                                 __func__, err);
3540                 goto xhci_bus_resume_failed;
3541         }
3542
3543         if (xhci->shared_hcd == hcd)
3544                 tegra->usb3_rh_suspend = false;
3545         else if (xhci->main_hcd == hcd)
3546                 tegra->usb2_rh_suspend = false;
3547
3548         mutex_unlock(&tegra->sync_lock);
3549         return 0;
3550
3551 xhci_bus_resume_failed:
3552         /* TODO: reverse elpg? */
3553         mutex_unlock(&tegra->sync_lock);
3554         return err;
3555 }
3556 #endif
3557
3558 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
3559 {
3560         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3561         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3562         irqreturn_t iret = IRQ_HANDLED;
3563         u32 status;
3564
3565         spin_lock(&tegra->lock);
3566         if (tegra->hc_in_elpg) {
3567                 spin_lock(&xhci->lock);
3568                 if (HCD_HW_ACCESSIBLE(hcd)) {
3569                         status = xhci_readl(xhci, &xhci->op_regs->status);
3570                         status |= STS_EINT;
3571                         xhci_writel(xhci, status, &xhci->op_regs->status);
3572                 }
3573                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
3574                                 __func__);
3575                 schedule_work(&tegra->host_elpg_exit_work);
3576                 spin_unlock(&xhci->lock);
3577         } else
3578                 iret = xhci_irq(hcd);
3579         spin_unlock(&tegra->lock);
3580
3581         wake_up_interruptible(&tegra->log.intr_wait);
3582
3583         return iret;
3584 }
3585
3586
3587 static const struct hc_driver tegra_plat_xhci_driver = {
3588         .description =          "tegra-xhci",
3589         .product_desc =         "Nvidia xHCI Host Controller",
3590         .hcd_priv_size =        sizeof(struct xhci_hcd *),
3591
3592         /*
3593          * generic hardware linkage
3594          */
3595         .irq =                  tegra_xhci_irq,
3596         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
3597
3598         /*
3599          * basic lifecycle operations
3600          */
3601         .reset =                xhci_plat_setup,
3602         .start =                xhci_run,
3603         .stop =                 xhci_stop,
3604         .shutdown =             xhci_shutdown,
3605
3606         /*
3607          * managing i/o requests and associated device resources
3608          */
3609         .urb_enqueue =          xhci_urb_enqueue,
3610         .urb_dequeue =          xhci_urb_dequeue,
3611         .alloc_dev =            xhci_alloc_dev,
3612         .free_dev =             xhci_free_dev,
3613         .alloc_streams =        xhci_alloc_streams,
3614         .free_streams =         xhci_free_streams,
3615         .add_endpoint =         xhci_add_endpoint,
3616         .drop_endpoint =        xhci_drop_endpoint,
3617         .endpoint_reset =       xhci_endpoint_reset,
3618         .check_bandwidth =      xhci_check_bandwidth,
3619         .reset_bandwidth =      xhci_reset_bandwidth,
3620         .address_device =       xhci_address_device,
3621         .update_hub_device =    xhci_update_hub_device,
3622         .reset_device =         xhci_discover_or_reset_device,
3623
3624         /*
3625          * scheduling support
3626          */
3627         .get_frame_number =     xhci_get_frame,
3628
3629         /* Root hub support */
3630         .hub_control =          xhci_hub_control,
3631         .hub_status_data =      xhci_hub_status_data,
3632
3633 #ifdef CONFIG_PM
3634         .bus_suspend =          tegra_xhci_bus_suspend,
3635         .bus_resume =           tegra_xhci_bus_resume,
3636 #endif
3637 };
3638
3639 #ifdef CONFIG_PM
3640 static int
3641 tegra_xhci_suspend(struct platform_device *pdev,
3642                                                 pm_message_t state)
3643 {
3644         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3645         struct xhci_hcd *xhci = tegra->xhci;
3646
3647         int ret = 0;
3648
3649         mutex_lock(&tegra->sync_lock);
3650         if (!tegra->init_done) {
3651                 xhci_warn(xhci, "%s: xhci probe not done\n",
3652                                 __func__);
3653                 mutex_unlock(&tegra->sync_lock);
3654                 return -EBUSY;
3655         }
3656         if (!tegra->hc_in_elpg) {
3657                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
3658                                 __func__);
3659                 mutex_unlock(&tegra->sync_lock);
3660                 return -EBUSY;
3661         }
3662         mutex_unlock(&tegra->sync_lock);
3663
3664         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3665         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3666
3667         /* enable_irq_wake for ss ports */
3668         ret = enable_irq_wake(tegra->padctl_irq);
3669         if (ret < 0) {
3670                 xhci_err(xhci,
3671                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
3672                 __func__, tegra->padctl_irq, ret);
3673         }
3674
3675         /* enable_irq_wake for utmip/uhisc wakes */
3676         ret = enable_irq_wake(tegra->usb3_irq);
3677         if (ret < 0) {
3678                 xhci_err(xhci,
3679                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3680                 __func__, tegra->usb3_irq, ret);
3681         }
3682
3683         /* enable_irq_wake for utmip/uhisc wakes */
3684         ret = enable_irq_wake(tegra->usb2_irq);
3685         if (ret < 0) {
3686                 xhci_err(xhci,
3687                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3688                 __func__, tegra->usb2_irq, ret);
3689         }
3690
3691         regulator_disable(tegra->xusb_s1p8v_reg);
3692         regulator_disable(tegra->xusb_s1p05v_reg);
3693         tegra_usb2_clocks_deinit(tegra);
3694
3695         return ret;
3696 }
3697
3698 static int
3699 tegra_xhci_resume(struct platform_device *pdev)
3700 {
3701         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3702         struct xhci_hcd *xhci = tegra->xhci;
3703
3704         dev_dbg(&pdev->dev, "%s\n", __func__);
3705
3706         mutex_lock(&tegra->sync_lock);
3707         if (!tegra->init_done) {
3708                 xhci_warn(xhci, "%s: xhci probe not done\n",
3709                                 __func__);
3710                 mutex_unlock(&tegra->sync_lock);
3711                 return -EBUSY;
3712         }
3713         mutex_unlock(&tegra->sync_lock);
3714
3715         tegra->last_jiffies = jiffies;
3716
3717         disable_irq_wake(tegra->padctl_irq);
3718         disable_irq_wake(tegra->usb3_irq);
3719         disable_irq_wake(tegra->usb2_irq);
3720         tegra->lp0_exit = true;
3721
3722         regulator_enable(tegra->xusb_s1p05v_reg);
3723         regulator_enable(tegra->xusb_s1p8v_reg);
3724         tegra_usb2_clocks_init(tegra);
3725
3726         return 0;
3727 }
3728 #endif
3729
3730
3731 static int init_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3732 {
3733         struct platform_device *pdev = tegra->pdev;
3734         void __iomem *fw_mmio_base;
3735         phys_addr_t fw_mem_phy_addr;
3736         size_t fw_size;
3737         dma_addr_t fw_dma;
3738 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3739         int ret;
3740         DEFINE_DMA_ATTRS(attrs);
3741 #endif
3742
3743         /* bootloader saved firmware memory address in PMC SCRATCH34 register */
3744         fw_mem_phy_addr = tegra_usb_pmc_reg_read(PMC_SCRATCH34);
3745
3746         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3747                         fw_mem_phy_addr, sizeof(struct cfgtbl));
3748
3749         if (!fw_mmio_base) {
3750                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3751                                         (u32)fw_mem_phy_addr);
3752                         return -ENOMEM;
3753         }
3754
3755         fw_size = ioread32(fw_mmio_base + FW_SIZE_OFFSET);
3756         devm_iounmap(&pdev->dev, fw_mmio_base);
3757
3758         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3759                         fw_mem_phy_addr, fw_size);
3760         if (!fw_mmio_base) {
3761                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3762                                         (u32)fw_mem_phy_addr);
3763                         return -ENOMEM;
3764         }
3765
3766         dev_info(&pdev->dev, "Firmware Memory: phy 0x%x mapped 0x%p (%d Bytes)\n",
3767                         (u32) fw_mem_phy_addr, fw_mmio_base, fw_size);
3768
3769 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3770         dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
3771         fw_dma = dma_map_linear_attrs(&pdev->dev, fw_mem_phy_addr, fw_size,
3772                         DMA_TO_DEVICE, &attrs);
3773
3774         if (fw_dma == DMA_ERROR_CODE) {
3775                 dev_err(&pdev->dev, "%s: dma_map_linear failed\n",
3776                                 __func__);
3777                 ret = -ENOMEM;
3778                 goto error_iounmap;
3779         }
3780 #else
3781         fw_dma = fw_mem_phy_addr;
3782 #endif
3783         dev_info(&pdev->dev, "Firmware DMA Memory: dma 0x%p (%d Bytes)\n",
3784                         (void *) fw_dma, fw_size);
3785
3786         /* all set and ready to go */
3787         tegra->firmware.data = fw_mmio_base;
3788         tegra->firmware.dma = fw_dma;
3789         tegra->firmware.size = fw_size;
3790
3791         return 0;
3792
3793 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3794 error_iounmap:
3795         devm_iounmap(&pdev->dev, fw_mmio_base);
3796         return ret;
3797 #endif
3798 }
3799
3800 static void deinit_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3801 {
3802         struct platform_device *pdev = tegra->pdev;
3803         void __iomem *fw_mmio_base = tegra->firmware.data;
3804
3805 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3806         dma_unmap_single(&pdev->dev, tegra->firmware.dma,
3807                         tegra->firmware.size, DMA_TO_DEVICE);
3808 #endif
3809         devm_iounmap(&pdev->dev, fw_mmio_base);
3810
3811         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
3812 }
3813
3814 static int init_filesystem_firmware(struct tegra_xhci_hcd *tegra)
3815 {
3816         struct platform_device *pdev = tegra->pdev;
3817         int ret;
3818
3819         ret = request_firmware_nowait(THIS_MODULE, true, firmware_file,
3820                 &pdev->dev, GFP_KERNEL, tegra, init_filesystem_firmware_done);
3821         if (ret < 0) {
3822                 dev_err(&pdev->dev, "request_firmware failed %d\n", ret);
3823                 return ret;
3824         }
3825
3826         return ret;
3827 }
3828
3829 static void init_filesystem_firmware_done(const struct firmware *fw,
3830                                         void *context)
3831 {
3832         struct tegra_xhci_hcd *tegra = context;
3833         struct platform_device *pdev = tegra->pdev;
3834         struct cfgtbl *fw_cfgtbl;
3835         size_t fw_size;
3836         void *fw_data;
3837         dma_addr_t fw_dma;
3838         int ret;
3839
3840         mutex_lock(&tegra->sync_lock);
3841
3842         if (fw == NULL) {
3843                 dev_err(&pdev->dev,
3844                         "failed to init firmware from filesystem: %s\n",
3845                         firmware_file);
3846                 goto err_firmware_done;
3847         }
3848
3849         fw_cfgtbl = (struct cfgtbl *) fw->data;
3850         fw_size = fw_cfgtbl->fwimg_len;
3851         dev_info(&pdev->dev, "Firmware File: %s (%d Bytes)\n",
3852                         firmware_file, fw_size);
3853
3854         fw_data = dma_alloc_coherent(&pdev->dev, fw_size,
3855                         &fw_dma, GFP_KERNEL);
3856         if (!fw_data) {
3857                 dev_err(&pdev->dev, "%s: dma_alloc_coherent failed\n",
3858                         __func__);
3859                 goto err_firmware_done;
3860         }
3861
3862         memcpy(fw_data, fw->data, fw_size);
3863         dev_info(&pdev->dev,
3864                 "Firmware DMA Memory: dma 0x%p mapped 0x%p (%d Bytes)\n",
3865                 (void *) fw_dma, fw_data, fw_size);
3866
3867         /* all set and ready to go */
3868         tegra->firmware.data = fw_data;
3869         tegra->firmware.dma = fw_dma;
3870         tegra->firmware.size = fw_size;
3871
3872         ret = tegra_xhci_probe2(tegra);
3873         if (ret < 0) {
3874                 dev_err(&pdev->dev, "%s: failed to probe: %d\n", __func__, ret);
3875                 goto err_firmware_done;
3876         }
3877
3878         release_firmware(fw);
3879         mutex_unlock(&tegra->sync_lock);
3880         return;
3881
3882 err_firmware_done:
3883         release_firmware(fw);
3884         mutex_unlock(&tegra->sync_lock);
3885         tegra_xhci_remove(pdev);
3886 }
3887
3888 static void deinit_filesystem_firmware(struct tegra_xhci_hcd *tegra)
3889 {
3890         struct platform_device *pdev = tegra->pdev;
3891
3892         if (tegra->firmware.data) {
3893                 dma_free_coherent(&pdev->dev, tegra->firmware.size,
3894                         tegra->firmware.data, tegra->firmware.dma);
3895         }
3896
3897         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
3898 }
3899 static int init_firmware(struct tegra_xhci_hcd *tegra)
3900 {
3901         if (use_bootloader_firmware)
3902                 return init_bootloader_firmware(tegra);
3903         else
3904                 return init_filesystem_firmware(tegra);
3905 }
3906
3907 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
3908 {
3909         if (use_bootloader_firmware)
3910                 return deinit_bootloader_firmware(tegra);
3911         else
3912                 return deinit_filesystem_firmware(tegra);
3913 }
3914
3915 static int tegra_enable_xusb_clk(struct tegra_xhci_hcd *tegra,
3916                 struct platform_device *pdev)
3917 {
3918         int err = 0;
3919         /* enable ss clock */
3920         err = clk_enable(tegra->host_clk);
3921         if (err) {
3922                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
3923                 goto enable_host_clk_failed;
3924         }
3925
3926         err = clk_enable(tegra->ss_clk);
3927         if (err) {
3928                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
3929                 goto eanble_ss_clk_failed;
3930         }
3931
3932         err = clk_enable(tegra->emc_clk);
3933         if (err) {
3934                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
3935                 goto eanble_emc_clk_failed;
3936         }
3937
3938         return 0;
3939
3940 eanble_emc_clk_failed:
3941         clk_disable(tegra->ss_clk);
3942
3943 eanble_ss_clk_failed:
3944         clk_disable(tegra->host_clk);
3945
3946 enable_host_clk_failed:
3947         if (tegra->soc_config->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
3948                 clk_disable(tegra->pll_re_vco_clk);
3949         return err;
3950 }
3951
3952 static struct tegra_xusb_padctl_regs t114_padregs_offset = {
3953         .boot_media_0                   = 0x0,
3954         .usb2_pad_mux_0                 = 0x4,
3955         .usb2_port_cap_0                = 0x8,
3956         .snps_oc_map_0                  = 0xc,
3957         .usb2_oc_map_0                  = 0x10,
3958         .ss_port_map_0                  = 0x14,
3959         .oc_det_0                       = 0x18,
3960         .elpg_program_0                 = 0x1c,
3961         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3962         .usb2_bchrg_otgpad0_ctl1_0      = 0xffff,
3963         .usb2_bchrg_otgpad1_ctl0_0      = 0x24,
3964         .usb2_bchrg_otgpad1_ctl1_0      = 0xffff,
3965         .usb2_bchrg_otgpad2_ctl0_0      = 0xffff,
3966         .usb2_bchrg_otgpad2_ctl1_0      = 0xffff,
3967         .usb2_bchrg_bias_pad_0          = 0x28,
3968         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
3969         .iophy_pll_p0_ctl1_0            = 0x30,
3970         .iophy_pll_p0_ctl2_0            = 0x34,
3971         .iophy_pll_p0_ctl3_0            = 0x38,
3972         .iophy_pll_p0_ctl4_0            = 0x3c,
3973         .iophy_usb3_pad0_ctl1_0         = 0x40,
3974         .iophy_usb3_pad1_ctl1_0         = 0x44,
3975         .iophy_usb3_pad0_ctl2_0         = 0x48,
3976         .iophy_usb3_pad1_ctl2_0         = 0x4c,
3977         .iophy_usb3_pad0_ctl3_0         = 0x50,
3978         .iophy_usb3_pad1_ctl3_0         = 0x54,
3979         .iophy_usb3_pad0_ctl4_0         = 0x58,
3980         .iophy_usb3_pad1_ctl4_0         = 0x5c,
3981         .iophy_misc_pad_p0_ctl1_0       = 0x60,
3982         .iophy_misc_pad_p1_ctl1_0       = 0x64,
3983         .iophy_misc_pad_p0_ctl2_0       = 0x68,
3984         .iophy_misc_pad_p1_ctl2_0       = 0x6c,
3985         .iophy_misc_pad_p0_ctl3_0       = 0x70,
3986         .iophy_misc_pad_p1_ctl3_0       = 0x74,
3987         .iophy_misc_pad_p0_ctl4_0       = 0x78,
3988         .iophy_misc_pad_p1_ctl4_0       = 0x7c,
3989         .iophy_misc_pad_p0_ctl5_0       = 0x80,
3990         .iophy_misc_pad_p1_ctl5_0       = 0x84,
3991         .iophy_misc_pad_p0_ctl6_0       = 0x88,
3992         .iophy_misc_pad_p1_ctl6_0       = 0x8c,
3993         .usb2_otg_pad0_ctl0_0           = 0x90,
3994         .usb2_otg_pad1_ctl0_0           = 0x94,
3995         .usb2_otg_pad2_ctl0_0           = 0xffff,
3996         .usb2_otg_pad0_ctl1_0           = 0x98,
3997         .usb2_otg_pad1_ctl1_0           = 0x9c,
3998         .usb2_otg_pad2_ctl1_0           = 0xffff,
3999         .usb2_bias_pad_ctl0_0           = 0xa0,
4000         .usb2_bias_pad_ctl1_0           = 0xa4,
4001         .usb2_hsic_pad0_ctl0_0          = 0xa8,
4002         .usb2_hsic_pad1_ctl0_0          = 0xac,
4003         .usb2_hsic_pad0_ctl1_0          = 0xb0,
4004         .usb2_hsic_pad1_ctl1_0          = 0xb4,
4005         .usb2_hsic_pad0_ctl2_0          = 0xb8,
4006         .usb2_hsic_pad1_ctl2_0          = 0xbc,
4007         .ulpi_link_trim_ctl0            = 0xc0,
4008         .ulpi_null_clk_trim_ctl0        = 0xc4,
4009         .hsic_strb_trim_ctl0            = 0xc8,
4010         .wake_ctl0                      = 0xcc,
4011         .pm_spare0                      = 0xd0,
4012         .iophy_misc_pad_p2_ctl1_0       = 0xffff,
4013         .iophy_misc_pad_p3_ctl1_0       = 0xffff,
4014         .iophy_misc_pad_p4_ctl1_0       = 0xffff,
4015         .iophy_misc_pad_p2_ctl2_0       = 0xffff,
4016         .iophy_misc_pad_p3_ctl2_0       = 0xffff,
4017         .iophy_misc_pad_p4_ctl2_0       = 0xffff,
4018         .iophy_misc_pad_p2_ctl3_0       = 0xffff,
4019         .iophy_misc_pad_p3_ctl3_0       = 0xffff,
4020         .iophy_misc_pad_p4_ctl3_0       = 0xffff,
4021         .iophy_misc_pad_p2_ctl4_0       = 0xffff,
4022         .iophy_misc_pad_p3_ctl4_0       = 0xffff,
4023         .iophy_misc_pad_p4_ctl4_0       = 0xffff,
4024         .iophy_misc_pad_p2_ctl5_0       = 0xffff,
4025         .iophy_misc_pad_p3_ctl5_0       = 0xffff,
4026         .iophy_misc_pad_p4_ctl5_0       = 0xffff,
4027         .iophy_misc_pad_p2_ctl6_0       = 0xffff,
4028         .iophy_misc_pad_p3_ctl6_0       = 0xffff,
4029         .iophy_misc_pad_p4_ctl6_0       = 0xffff,
4030         .usb3_pad_mux_0                 = 0xffff,
4031         .iophy_pll_s0_ctl1_0            = 0xffff,
4032         .iophy_pll_s0_ctl2_0            = 0xffff,
4033         .iophy_pll_s0_ctl3_0            = 0xffff,
4034         .iophy_pll_s0_ctl4_0            = 0xffff,
4035         .iophy_misc_pad_s0_ctl1_0       = 0xffff,
4036         .iophy_misc_pad_s0_ctl2_0       = 0xffff,
4037         .iophy_misc_pad_s0_ctl3_0       = 0xffff,
4038         .iophy_misc_pad_s0_ctl4_0       = 0xffff,
4039         .iophy_misc_pad_s0_ctl5_0       = 0xffff,
4040         .iophy_misc_pad_s0_ctl6_0       = 0xffff,
4041 };
4042
4043 static struct tegra_xusb_padctl_regs t124_padregs_offset = {
4044         .boot_media_0                   = 0x0,
4045         .usb2_pad_mux_0                 = 0x4,
4046         .usb2_port_cap_0                = 0x8,
4047         .snps_oc_map_0                  = 0xc,
4048         .usb2_oc_map_0                  = 0x10,
4049         .ss_port_map_0                  = 0x14,
4050         .oc_det_0                       = 0x18,
4051         .elpg_program_0                 = 0x1c,
4052         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
4053         .usb2_bchrg_otgpad0_ctl1_0      = 0x24,
4054         .usb2_bchrg_otgpad1_ctl0_0      = 0x28,
4055         .usb2_bchrg_otgpad1_ctl1_0      = 0x2c,
4056         .usb2_bchrg_otgpad2_ctl0_0      = 0x30,
4057         .usb2_bchrg_otgpad2_ctl1_0      = 0x34,
4058         .usb2_bchrg_bias_pad_0          = 0x38,
4059         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
4060         .iophy_pll_p0_ctl1_0            = 0x40,
4061         .iophy_pll_p0_ctl2_0            = 0x44,
4062         .iophy_pll_p0_ctl3_0            = 0x48,
4063         .iophy_pll_p0_ctl4_0            = 0x4c,
4064         .iophy_usb3_pad0_ctl1_0         = 0x50,
4065         .iophy_usb3_pad1_ctl1_0         = 0x54,
4066         .iophy_usb3_pad0_ctl2_0         = 0x58,
4067         .iophy_usb3_pad1_ctl2_0         = 0x5c,
4068         .iophy_usb3_pad0_ctl3_0         = 0x60,
4069         .iophy_usb3_pad1_ctl3_0         = 0x64,
4070         .iophy_usb3_pad0_ctl4_0         = 0x68,
4071         .iophy_usb3_pad1_ctl4_0         = 0x6c,
4072         .iophy_misc_pad_p0_ctl1_0       = 0x70,
4073         .iophy_misc_pad_p1_ctl1_0       = 0x74,
4074         .iophy_misc_pad_p0_ctl2_0       = 0x78,
4075         .iophy_misc_pad_p1_ctl2_0       = 0x7c,
4076         .iophy_misc_pad_p0_ctl3_0       = 0x80,
4077         .iophy_misc_pad_p1_ctl3_0       = 0x84,
4078         .iophy_misc_pad_p0_ctl4_0       = 0x88,
4079         .iophy_misc_pad_p1_ctl4_0       = 0x8c,
4080         .iophy_misc_pad_p0_ctl5_0       = 0x90,
4081         .iophy_misc_pad_p1_ctl5_0       = 0x94,
4082         .iophy_misc_pad_p0_ctl6_0       = 0x98,
4083         .iophy_misc_pad_p1_ctl6_0       = 0x9c,
4084         .usb2_otg_pad0_ctl0_0           = 0xa0,
4085         .usb2_otg_pad1_ctl0_0           = 0xa4,
4086         .usb2_otg_pad2_ctl0_0           = 0xa8,
4087         .usb2_otg_pad0_ctl1_0           = 0xac,
4088         .usb2_otg_pad1_ctl1_0           = 0xb0,
4089         .usb2_otg_pad2_ctl1_0           = 0xb4,
4090         .usb2_bias_pad_ctl0_0           = 0xb8,
4091         .usb2_bias_pad_ctl1_0           = 0xbc,
4092         .usb2_hsic_pad0_ctl0_0          = 0xc0,
4093         .usb2_hsic_pad1_ctl0_0          = 0xc4,
4094         .usb2_hsic_pad0_ctl1_0          = 0xc8,
4095         .usb2_hsic_pad1_ctl1_0          = 0xcc,
4096         .usb2_hsic_pad0_ctl2_0          = 0xd0,
4097         .usb2_hsic_pad1_ctl2_0          = 0xd4,
4098         .ulpi_link_trim_ctl0            = 0xd8,
4099         .ulpi_null_clk_trim_ctl0        = 0xdc,
4100         .hsic_strb_trim_ctl0            = 0xe0,
4101         .wake_ctl0                      = 0xe4,
4102         .pm_spare0                      = 0xe8,
4103         .iophy_misc_pad_p2_ctl1_0       = 0xec,
4104         .iophy_misc_pad_p3_ctl1_0       = 0xf0,
4105         .iophy_misc_pad_p4_ctl1_0       = 0xf4,
4106         .iophy_misc_pad_p2_ctl2_0       = 0xf8,
4107         .iophy_misc_pad_p3_ctl2_0       = 0xfc,
4108         .iophy_misc_pad_p4_ctl2_0       = 0x100,
4109         .iophy_misc_pad_p2_ctl3_0       = 0x104,
4110         .iophy_misc_pad_p3_ctl3_0       = 0x108,
4111         .iophy_misc_pad_p4_ctl3_0       = 0x10c,
4112         .iophy_misc_pad_p2_ctl4_0       = 0x110,
4113         .iophy_misc_pad_p3_ctl4_0       = 0x114,
4114         .iophy_misc_pad_p4_ctl4_0       = 0x118,
4115         .iophy_misc_pad_p2_ctl5_0       = 0x11c,
4116         .iophy_misc_pad_p3_ctl5_0       = 0x120,
4117         .iophy_misc_pad_p4_ctl5_0       = 0x124,
4118         .iophy_misc_pad_p2_ctl6_0       = 0x128,
4119         .iophy_misc_pad_p3_ctl6_0       = 0x12c,
4120         .iophy_misc_pad_p4_ctl6_0       = 0x130,
4121         .usb3_pad_mux_0                 = 0x134,
4122         .iophy_pll_s0_ctl1_0            = 0x138,
4123         .iophy_pll_s0_ctl2_0            = 0x13c,
4124         .iophy_pll_s0_ctl3_0            = 0x140,
4125         .iophy_pll_s0_ctl4_0            = 0x144,
4126         .iophy_misc_pad_s0_ctl1_0       = 0x148,
4127         .iophy_misc_pad_s0_ctl2_0       = 0x14c,
4128         .iophy_misc_pad_s0_ctl3_0       = 0x150,
4129         .iophy_misc_pad_s0_ctl4_0       = 0x154,
4130         .iophy_misc_pad_s0_ctl5_0       = 0x158,
4131         .iophy_misc_pad_s0_ctl6_0       = 0x15c,
4132 };
4133
4134 /* FIXME: using notifier to transfer control to host from suspend
4135  * for otg port when xhci is in elpg. Find  better alternative
4136  */
4137 static int tegra_xhci_otg_notify(struct notifier_block *nb,
4138                                    unsigned long event, void *unused)
4139 {
4140         struct tegra_xhci_hcd *tegra = container_of(nb,
4141                                         struct tegra_xhci_hcd, otgnb);
4142
4143         if ((event == USB_EVENT_ID))
4144                 if (tegra->hc_in_elpg) {
4145                         schedule_work(&tegra->host_elpg_exit_work);
4146                         tegra->host_resume_req = true;
4147         }
4148
4149         return NOTIFY_OK;
4150 }
4151
4152 static void tegra_xusb_read_board_data(struct tegra_xhci_hcd *tegra)
4153 {
4154         struct tegra_xusb_board_data *bdata = tegra->bdata;
4155         struct device_node *node = tegra->pdev->dev.of_node;
4156         int ret;
4157
4158         bdata->uses_external_pmic = of_property_read_bool(node,
4159                                         "nvidia,uses_external_pmic");
4160         bdata->gpio_controls_muxed_ss_lanes = of_property_read_bool(node,
4161                                         "nvidia,gpio_controls_muxed_ss_lanes");
4162         ret = of_property_read_u32(node, "nvidia,gpio_ss1_sata",
4163                                         &bdata->gpio_ss1_sata);
4164         ret = of_property_read_u32(node, "nvidia,portmap",
4165                                         &bdata->portmap);
4166         ret = of_property_read_u8(node, "nvidia,ss_portmap",
4167                                         &bdata->ss_portmap);
4168         ret = of_property_read_u8(node, "nvidia,lane_owner",
4169                                         &bdata->lane_owner);
4170         ret = of_property_read_u8(node, "nvidia,ulpicap",
4171                                         &bdata->ulpicap);
4172         ret = of_property_read_string_index(node, "nvidia,supply_utmi_vbuses",
4173                                         0, &bdata->supply.utmi_vbuses[0]);
4174         ret = of_property_read_string_index(node, "nvidia,supply_utmi_vbuses",
4175                                         1, &bdata->supply.utmi_vbuses[1]);
4176         ret = of_property_read_string_index(node, "nvidia,supply_utmi_vbuses",
4177                                         2, &bdata->supply.utmi_vbuses[2]);
4178         ret = of_property_read_string(node, "nvidia,supply_s3p3v",
4179                                         &bdata->supply.s3p3v);
4180         ret = of_property_read_string(node, "nvidia,supply_s1p8v",
4181                                         &bdata->supply.s1p8v);
4182         ret = of_property_read_string(node, "nvidia,supply_vddio_hsic",
4183                                         &bdata->supply.vddio_hsic);
4184         ret = of_property_read_string(node, "nvidia,supply_s1p05v",
4185                                         &bdata->supply.s1p05v);
4186         ret = of_property_read_u8_array(node, "nvidia,hsic0",
4187                                         (u8 *) &bdata->hsic[0],
4188                                         sizeof(bdata->hsic[0]));
4189         ret = of_property_read_u8_array(node, "nvidia,hsic1",
4190                                         (u8 *) &bdata->hsic[1],
4191                                         sizeof(bdata->hsic[0]));
4192         /* TODO: Add error conditions check */
4193 }
4194
4195 static void tegra_xusb_read_calib_data(struct tegra_xhci_hcd *tegra)
4196 {
4197         u32 usb_calib0 = tegra_fuse_readl(FUSE_SKU_USB_CALIB_0);
4198         struct tegra_xusb_chip_calib *cdata = tegra->cdata;
4199
4200         pr_info("tegra_xusb_read_usb_calib: usb_calib0 = 0x%08x\n", usb_calib0);
4201         /*
4202          * read from usb_calib0 and pass to driver
4203          * set HS_CURR_LEVEL (PAD0)     = usb_calib0[5:0]
4204          * set TERM_RANGE_ADJ           = usb_calib0[10:7]
4205          * set HS_SQUELCH_LEVEL         = usb_calib0[12:11]
4206          * set HS_IREF_CAP              = usb_calib0[14:13]
4207          * set HS_CURR_LEVEL (PAD1)     = usb_calib0[20:15]
4208          */
4209
4210         cdata->hs_curr_level_pad0 = (usb_calib0 >> 0) & 0x3f;
4211         cdata->hs_term_range_adj = (usb_calib0 >> 7) & 0xf;
4212         cdata->hs_squelch_level = (usb_calib0 >> 11) & 0x3;
4213         cdata->hs_iref_cap = (usb_calib0 >> 13) & 0x3;
4214         cdata->hs_curr_level_pad1 = (usb_calib0 >> 15) & 0x3f;
4215         cdata->hs_curr_level_pad2 = (usb_calib0 >> 15) & 0x3f;
4216 }
4217
4218 static const struct tegra_xusb_soc_config tegra114_soc_config = {
4219         .pmc_portmap = (TEGRA_XUSB_UTMIP_PMC_PORT0 << 0) |
4220                         (TEGRA_XUSB_UTMIP_PMC_PORT2 << 4),
4221         .quirks = TEGRA_XUSB_USE_HS_SRC_CLOCK2,
4222         .rx_wander = (0x3 << 4),
4223         .rx_eq = (0x3928 << 8),
4224         .cdr_cntl = (0x26 << 24),
4225         .dfe_cntl = 0x002008EE,
4226         .hs_slew = (0xE << 6),
4227         .ls_rslew_pad0 = (0x3 << 14),
4228         .ls_rslew_pad1 = (0x0 << 14),
4229         .hs_disc_lvl = (0x5 << 2),
4230         .spare_in = 0x0,
4231 };
4232
4233 static const struct tegra_xusb_soc_config tegra124_soc_config = {
4234         .pmc_portmap = (TEGRA_XUSB_UTMIP_PMC_PORT0 << 0) |
4235                         (TEGRA_XUSB_UTMIP_PMC_PORT1 << 4) |
4236                         (TEGRA_XUSB_UTMIP_PMC_PORT2 << 8),
4237         .rx_wander = (0xF << 4),
4238         .rx_eq = (0xF070 << 8),
4239         .cdr_cntl = (0x26 << 24),
4240         .dfe_cntl = 0x002008EE,
4241         .hs_slew = (0xE << 6),
4242         .ls_rslew_pad0 = (0x3 << 14),
4243         .ls_rslew_pad1 = (0x0 << 14),
4244         .ls_rslew_pad2 = (0x0 << 14),
4245         .hs_disc_lvl = (0x5 << 2),
4246         .spare_in = 0x1,
4247 };
4248
4249 static struct of_device_id tegra_xhci_of_match[] = {
4250         { .compatible = "nvidia,tegra114-xhci", .data = &tegra114_soc_config },
4251         { .compatible = "nvidia,tegra124-xhci", .data = &tegra124_soc_config },
4252         { },
4253 };
4254
4255 /* TODO: we have to refine error handling in tegra_xhci_probe() */
4256 static int tegra_xhci_probe(struct platform_device *pdev)
4257 {
4258         struct tegra_xhci_hcd *tegra;
4259         struct resource *res;
4260         unsigned pad;
4261         u32 val;
4262         int ret;
4263         int irq;
4264         const struct tegra_xusb_soc_config *soc_config;
4265         const struct of_device_id *match;
4266
4267         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
4268
4269         if (usb_disabled())
4270                 return -ENODEV;
4271
4272         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
4273         if (!tegra) {
4274                 dev_err(&pdev->dev, "memory alloc failed\n");
4275                 return -ENOMEM;
4276         }
4277         mutex_init(&tegra->sync_lock);
4278         spin_lock_init(&tegra->lock);
4279         mutex_init(&tegra->mbox_lock);
4280
4281         tegra->init_done = false;
4282
4283         tegra->bdata = devm_kzalloc(&pdev->dev, sizeof(
4284                                         struct tegra_xusb_board_data),
4285                                         GFP_KERNEL);
4286         if (!tegra->bdata) {
4287                 dev_err(&pdev->dev, "memory alloc failed\n");
4288                 return -ENOMEM;
4289         }
4290         tegra->cdata = devm_kzalloc(&pdev->dev, sizeof(
4291                                         struct tegra_xusb_chip_calib),
4292                                         GFP_KERNEL);
4293         if (!tegra->cdata) {
4294                 dev_err(&pdev->dev, "memory alloc failed\n");
4295                 return -ENOMEM;
4296         }
4297         match = of_match_device(tegra_xhci_of_match, &pdev->dev);
4298         if (!match) {
4299                 dev_err(&pdev->dev, "Error: No device match found\n");
4300                 return -ENODEV;
4301         }
4302         soc_config = match->data;
4303         /* Right now device-tree probed devices don't get dma_mask set.
4304          * Since shared usb code relies on it, set it here for now.
4305          * Once we have dma capability bindings this can go away.
4306          */
4307         tegra->tegra_xusb_dmamask = DMA_BIT_MASK(64);
4308         if (!pdev->dev.dma_mask)
4309                 pdev->dev.dma_mask = &tegra->tegra_xusb_dmamask;
4310
4311         tegra->pdev = pdev;
4312         tegra_xusb_read_calib_data(tegra);
4313         tegra_xusb_read_board_data(tegra);
4314         tegra->pdata = dev_get_platdata(&pdev->dev);
4315         tegra->bdata->portmap = tegra->pdata->portmap;
4316         tegra->bdata->hsic[0].pretend_connect =
4317                                 tegra->pdata->pretend_connect_0;
4318         if (tegra->bdata->portmap == NULL)
4319                 return -ENODEV;
4320         tegra->bdata->lane_owner = tegra->pdata->lane_owner;
4321         tegra->soc_config = soc_config;
4322         tegra->ss_pwr_gated = false;
4323         tegra->host_pwr_gated = false;
4324         tegra->hc_in_elpg = false;
4325         tegra->hs_wake_event = false;
4326         tegra->host_resume_req = false;
4327         tegra->lp0_exit = false;
4328
4329         /* request resource padctl base address */
4330         ret = tegra_xhci_request_mem_region(pdev, 3, &tegra->padctl_base);
4331         if (ret) {
4332                 dev_err(&pdev->dev, "failed to map padctl\n");
4333                 return ret;
4334         }
4335
4336         /* request resource fpci base address */
4337         ret = tegra_xhci_request_mem_region(pdev, 1, &tegra->fpci_base);
4338         if (ret) {
4339                 dev_err(&pdev->dev, "failed to map fpci\n");
4340                 return ret;
4341         }
4342
4343         /* request resource ipfs base address */
4344         ret = tegra_xhci_request_mem_region(pdev, 2, &tegra->ipfs_base);
4345         if (ret) {
4346                 dev_err(&pdev->dev, "failed to map ipfs\n");
4347                 return ret;
4348         }
4349
4350         ret = tegra_xusb_partitions_clk_init(tegra);
4351         if (ret) {
4352                 dev_err(&pdev->dev,
4353                         "failed to initialize xusb partitions clocks\n");
4354                 return ret;
4355         }
4356
4357         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) {
4358                 tegra->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
4359                 if (IS_ERR_OR_NULL(tegra->transceiver)) {
4360                         dev_err(&pdev->dev, "failed to get usb phy\n");
4361                         tegra->transceiver = NULL;
4362                 }
4363         }
4364
4365         /* Enable power rails to the PAD,VBUS
4366          * and pull-up voltage.Initialize the regulators
4367          */
4368         ret = tegra_xusb_regulator_init(tegra, pdev);
4369         if (ret) {
4370                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
4371                 goto err_deinit_xusb_partition_clk;
4372         }
4373
4374         /* Enable UTMIP, PLLU and PLLE */
4375         ret = tegra_usb2_clocks_init(tegra);
4376         if (ret) {
4377                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
4378                 goto err_deinit_tegra_xusb_regulator;
4379         }
4380
4381         /* tegra_unpowergate_partition also does partition reset deassert */
4382         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
4383         if (ret)
4384                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
4385
4386         /* tegra_unpowergate_partition also does partition reset deassert */
4387         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
4388         if (ret)
4389                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
4390
4391         ret = tegra_enable_xusb_clk(tegra, pdev);
4392         if (ret)
4393                 dev_err(&pdev->dev, "could not enable partition clock\n");
4394
4395         /* reset the pointer back to NULL. driver uses it */
4396         /* platform_set_drvdata(pdev, NULL); */
4397
4398         /* request resource host base address */
4399         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4400         if (!res) {
4401                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
4402                 ret = -ENODEV;
4403                 goto err_deinit_usb2_clocks;
4404         }
4405         tegra->host_phy_base = res->start;
4406         tegra->host_phy_size = resource_size(res);
4407
4408         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
4409                                 res->start, resource_size(res));
4410         if (!tegra->host_phy_virt_base) {
4411                 dev_err(&pdev->dev, "error mapping host phy memory\n");
4412                 ret = -ENOMEM;
4413                 goto err_deinit_usb2_clocks;
4414         }
4415
4416         /* Setup IPFS access and BAR0 space */
4417         tegra_xhci_cfg(tegra);
4418
4419         val = readl(tegra->fpci_base + XUSB_CFG_0);
4420         tegra->device_id = (val >> 16) & 0xffff;
4421
4422         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
4423                 (XUSB_DEVICE_ID_T114 == tegra->device_id) ? "T114" : "T124+");
4424
4425         if (XUSB_DEVICE_ID_T114 == tegra->device_id) {
4426                 tegra->padregs = &t114_padregs_offset;
4427         } else if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
4428                 tegra->padregs = &t124_padregs_offset;
4429         } else {
4430                 dev_info(&pdev->dev, "XUSB device_id neither T114 nor T124!\n");
4431                 dev_info(&pdev->dev, "XUSB using T124 pad register offsets!\n");
4432                 tegra->padregs = &t124_padregs_offset;
4433         }
4434
4435         /* calculate rctrl_val and tctrl_val once at boot time */
4436         /* Issue is only applicable for T114 */
4437         if (XUSB_DEVICE_ID_T114 == tegra->device_id)
4438                 tegra_xhci_war_for_tctrl_rctrl(tegra);
4439
4440         for_each_enabled_hsic_pad(pad, tegra)
4441                 hsic_power_rail_enable(tegra);
4442
4443         /* Program the XUSB pads to take ownership of ports */
4444         tegra_xhci_padctl_portmap_and_caps(tegra);
4445
4446         /* Release XUSB wake logic state latching */
4447         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
4448         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
4449
4450         /* Deassert reset to XUSB host, ss, dev clocks */
4451         tegra_periph_reset_deassert(tegra->host_clk);
4452         tegra_periph_reset_deassert(tegra->ss_clk);
4453
4454         platform_set_drvdata(pdev, tegra);
4455         fw_log_init(tegra);
4456         ret = init_firmware(tegra);
4457         if (ret < 0) {
4458                 dev_err(&pdev->dev, "failed to init firmware\n");
4459                 ret = -ENODEV;
4460                 goto err_deinit_firmware_log;
4461         }
4462
4463         if (use_bootloader_firmware) {
4464                 ret = tegra_xhci_probe2(tegra);
4465                 if (ret < 0) {
4466                         ret = -ENODEV;
4467                         goto err_deinit_firmware;
4468                 }
4469         }
4470
4471         return 0;
4472
4473 err_deinit_firmware:
4474         deinit_firmware(tegra);
4475 err_deinit_firmware_log:
4476         fw_log_deinit(tegra);
4477 err_deinit_usb2_clocks:
4478         tegra_usb2_clocks_deinit(tegra);
4479 err_deinit_tegra_xusb_regulator:
4480         tegra_xusb_regulator_deinit(tegra);
4481 err_deinit_xusb_partition_clk:
4482         if (tegra->transceiver)
4483                 usb_unregister_notifier(tegra->transceiver, &tegra->otgnb);
4484
4485         tegra_xusb_partitions_clk_deinit(tegra);
4486
4487         return ret;
4488 }
4489
4490 static int tegra_xhci_probe2(struct tegra_xhci_hcd *tegra)
4491 {
4492         struct platform_device *pdev = tegra->pdev;
4493         const struct hc_driver *driver;
4494         int ret;
4495         struct resource *res;
4496         int irq;
4497         struct xhci_hcd *xhci;
4498         struct usb_hcd  *hcd;
4499         unsigned port;
4500
4501
4502         ret = load_firmware(tegra, true /* do reset ARU */);
4503         if (ret < 0) {
4504                 dev_err(&pdev->dev, "failed to load firmware\n");
4505                 return -ENODEV;
4506         }
4507         pmc_init(tegra);
4508
4509         device_init_wakeup(&pdev->dev, 1);
4510         driver = &tegra_plat_xhci_driver;
4511
4512         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
4513         if (!hcd) {
4514                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
4515                 return -ENOMEM;
4516         }
4517
4518         /* request resource host base address */
4519         ret = tegra_xhci_request_mem_region(pdev, 0, &hcd->regs);
4520         if (ret) {
4521                 dev_err(&pdev->dev, "failed to map host\n");
4522                 goto err_put_usb2_hcd;
4523         }
4524         hcd->rsrc_start = tegra->host_phy_base;
4525         hcd->rsrc_len = tegra->host_phy_size;
4526
4527         /* Register interrupt handler for HOST */
4528         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
4529         if (!res) {
4530                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
4531                 ret = -ENODEV;
4532                 goto err_put_usb2_hcd;
4533         }
4534
4535         irq = res->start;
4536         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
4537         if (ret) {
4538                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
4539                 goto err_put_usb2_hcd;
4540         }
4541
4542         /* USB 2.0 roothub is stored in the platform_device now. */
4543         hcd = dev_get_drvdata(&pdev->dev);
4544         xhci = hcd_to_xhci(hcd);
4545         tegra->xhci = xhci;
4546         platform_set_drvdata(pdev, tegra);
4547
4548         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) {
4549                 if (!IS_ERR_OR_NULL(tegra->transceiver)) {
4550                         otg_set_host(tegra->transceiver->otg, &hcd->self);
4551                         tegra->otgnb.notifier_call = tegra_xhci_otg_notify;
4552                         usb_register_notifier(tegra->transceiver,
4553                                 &tegra->otgnb);
4554                 }
4555         }
4556
4557         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
4558                                                 dev_name(&pdev->dev), hcd);
4559         if (!xhci->shared_hcd) {
4560                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
4561                 ret = -ENOMEM;
4562                 goto err_remove_usb2_hcd;
4563         }
4564
4565         /*
4566          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
4567          * is called by usb_add_hcd().
4568          */
4569         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
4570
4571         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
4572         if (ret) {
4573                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
4574                 goto err_put_usb3_hcd;
4575         }
4576
4577         device_init_wakeup(&hcd->self.root_hub->dev, 1);
4578         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
4579
4580         /* do mailbox related initializations */
4581         tegra->mbox_owner = 0xffff;
4582         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
4583
4584         tegra_xhci_enable_fw_message(tegra);
4585
4586         /* do ss partition elpg exit related initialization */
4587         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
4588
4589         /* do host partition elpg exit related initialization */
4590         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
4591
4592         /* Register interrupt handler for SMI line to handle mailbox
4593          * interrupt from firmware
4594          */
4595
4596         ret = tegra_xhci_request_irq(pdev, 1, tegra_xhci_smi_irq,
4597                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
4598         if (ret != 0)
4599                 goto err_remove_usb3_hcd;
4600
4601         /* Register interrupt handler for PADCTRL line to
4602          * handle wake on connect irqs interrupt from
4603          * firmware
4604          */
4605         ret = tegra_xhci_request_irq(pdev, 2, tegra_xhci_padctl_irq,
4606                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
4607                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
4608         if (ret != 0)
4609                 goto err_remove_usb3_hcd;
4610
4611         /* Register interrupt wake handler for USB2 */
4612         ret = tegra_xhci_request_irq(pdev, 4, pmc_usb_phy_wake_isr,
4613                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4614                 &tegra->usb2_irq);
4615         if (ret != 0)
4616                 goto err_remove_usb3_hcd;
4617
4618         /* Register interrupt wake handler for USB3 */
4619         ret = tegra_xhci_request_irq(pdev, 3, pmc_usb_phy_wake_isr,
4620                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4621                 &tegra->usb3_irq);
4622         if (ret != 0)
4623                 goto err_remove_usb3_hcd;
4624
4625         for (port = 0; port < XUSB_SS_PORT_COUNT; port++) {
4626                 tegra->ctle_ctx_saved[port] = false;
4627                 tegra->dfe_ctx_saved[port] = false;
4628         }
4629
4630         hsic_pad_pretend_connect(tegra);
4631
4632         tegra_xhci_debug_read_pads(tegra);
4633         utmi_phy_pad_enable();
4634         utmi_phy_iddq_override(false);
4635
4636         tegra_pd_add_device(&pdev->dev);
4637         pm_runtime_enable(&pdev->dev);
4638
4639         tegra->init_done = true;
4640
4641         return 0;
4642
4643 err_remove_usb3_hcd:
4644         usb_remove_hcd(xhci->shared_hcd);
4645 err_put_usb3_hcd:
4646         usb_put_hcd(xhci->shared_hcd);
4647 err_remove_usb2_hcd:
4648         kfree(tegra->xhci);
4649         usb_remove_hcd(hcd);
4650 err_put_usb2_hcd:
4651         usb_put_hcd(hcd);
4652
4653         return ret;
4654 }
4655
4656 static int tegra_xhci_remove(struct platform_device *pdev)
4657 {
4658         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4659         unsigned pad;
4660
4661         if (tegra == NULL)
4662                 return -EINVAL;
4663
4664         mutex_lock(&tegra->sync_lock);
4665
4666         for_each_enabled_hsic_pad(pad, tegra) {
4667                 hsic_pad_disable(tegra, pad);
4668                 hsic_power_rail_disable(tegra);
4669         }
4670
4671         if (tegra->init_done) {
4672                 struct xhci_hcd *xhci = NULL;
4673                 struct usb_hcd *hcd = NULL;
4674
4675                 xhci = tegra->xhci;
4676                 hcd = xhci_to_hcd(xhci);
4677
4678                 devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
4679                 devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
4680                 devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
4681                 usb_remove_hcd(xhci->shared_hcd);
4682                 usb_put_hcd(xhci->shared_hcd);
4683                 usb_remove_hcd(hcd);
4684                 usb_put_hcd(hcd);
4685                 kfree(xhci);
4686         }
4687
4688         deinit_firmware(tegra);
4689         fw_log_deinit(tegra);
4690
4691         tegra_xusb_regulator_deinit(tegra);
4692
4693         if (tegra->transceiver)
4694                 usb_unregister_notifier(tegra->transceiver, &tegra->otgnb);
4695
4696         tegra_usb2_clocks_deinit(tegra);
4697         if (!tegra->hc_in_elpg)
4698                 tegra_xusb_partitions_clk_deinit(tegra);
4699
4700         utmi_phy_pad_disable();
4701         utmi_phy_iddq_override(true);
4702
4703         tegra_pd_remove_device(&pdev->dev);
4704         platform_set_drvdata(pdev, NULL);
4705
4706         mutex_unlock(&tegra->sync_lock);
4707
4708         return 0;
4709 }
4710
4711 static void tegra_xhci_shutdown(struct platform_device *pdev)
4712 {
4713         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4714         struct xhci_hcd *xhci = NULL;
4715         struct usb_hcd *hcd = NULL;
4716
4717         if (tegra == NULL)
4718                 return;
4719
4720         if (tegra->hc_in_elpg) {
4721                 pmc_disable_bus_ctrl(tegra);
4722         } else {
4723                 xhci = tegra->xhci;
4724                 hcd = xhci_to_hcd(xhci);
4725                 xhci_shutdown(hcd);
4726         }
4727 }
4728
4729 static struct platform_driver tegra_xhci_driver = {
4730         .probe  = tegra_xhci_probe,
4731         .remove = tegra_xhci_remove,
4732         .shutdown = tegra_xhci_shutdown,
4733 #ifdef CONFIG_PM
4734         .suspend = tegra_xhci_suspend,
4735         .resume  = tegra_xhci_resume,
4736 #endif
4737         .driver = {
4738                 .name = "tegra-xhci",
4739                 .of_match_table = tegra_xhci_of_match,
4740         },
4741 };
4742 MODULE_ALIAS("platform:tegra-xhci");
4743
4744 int tegra_xhci_register_plat(void)
4745 {
4746         return platform_driver_register(&tegra_xhci_driver);
4747 }
4748
4749 void tegra_xhci_unregister_plat(void)
4750 {
4751         platform_driver_unregister(&tegra_xhci_driver);
4752 }