xhci: tegra: Reset EMC bandwidth before elpg
[linux-3.10.git] / drivers / usb / host / xhci-tegra.c
1 /*
2  * xhci-tegra.c - Nvidia xHCI host controller driver
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/clk.h>
24 #include <linux/ioport.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irq.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/uaccess.h>
30 #include <linux/circ_buf.h>
31 #include <linux/vmalloc.h>
32 #include <linux/debugfs.h>
33 #include <linux/kthread.h>
34 #include <linux/gpio.h>
35 #include <linux/usb/otg.h>
36 #include <linux/clk/tegra.h>
37 #include <linux/tegra-powergate.h>
38 #include <linux/firmware.h>
39 #include <mach/tegra_usb_pad_ctrl.h>
40 #include <mach/tegra_usb_pmc.h>
41 #include <mach/pm_domains.h>
42 #include <mach/mc.h>
43 #include <mach/xusb.h>
44
45 #include "../../../arch/arm/mach-tegra/iomap.h" /* HACK -- remove */
46 #include "xhci-tegra.h"
47 #include "xhci.h"
48
49 /* macros */
50 #define FW_IOCTL_LOG_DEQUEUE_LOW        (4)
51 #define FW_IOCTL_LOG_DEQUEUE_HIGH       (5)
52 #define FW_IOCTL_DATA_SHIFT             (0)
53 #define FW_IOCTL_DATA_MASK              (0x00ffffff)
54 #define FW_IOCTL_TYPE_SHIFT             (24)
55 #define FW_IOCTL_TYPE_MASK              (0xff000000)
56 #define FW_LOG_SIZE                     (sizeof(struct log_entry))
57 #define FW_LOG_COUNT                    (4096)
58 #define FW_LOG_RING_SIZE                (FW_LOG_SIZE * FW_LOG_COUNT)
59 #define FW_LOG_PAYLOAD_SIZE             (27)
60 #define DRIVER                          (0x01)
61 #define CIRC_BUF_SIZE                   (4 * (1 << 20)) /* 4MB */
62 #define FW_LOG_THREAD_RELAX             (msecs_to_jiffies(100))
63
64 /* tegra_xhci_firmware_log.flags bits */
65 #define FW_LOG_CONTEXT_VALID            (0)
66 #define FW_LOG_FILE_OPENED              (1)
67
68 #define PAGE_SELECT_MASK                        0xFFFFFE00
69 #define PAGE_SELECT_SHIFT                       9
70 #define PAGE_OFFSET_MASK                        0x000001FF
71 #define CSB_PAGE_SELECT(_addr)                                          \
72         ({                                                              \
73                 typecheck(u32, _addr);                                  \
74                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
75         })
76 #define CSB_PAGE_OFFSET(_addr)                                          \
77         ({                                                              \
78                 typecheck(u32, _addr);                                  \
79                 (_addr & PAGE_OFFSET_MASK);                             \
80         })
81
82 #define reg_dump(_dev, _base, _reg)                                     \
83         dev_dbg(_dev, "%s: %s @%x = 0x%x\n", __func__, #_reg,           \
84                 _reg, readl(_base + _reg))
85
86 /* PMC register definition */
87 #define PMC_PORT_UTMIP_P0               0
88 #define PMC_PORT_UTMIP_P1               1
89 #define PMC_PORT_UTMIP_P2               2
90 #define PMC_PORT_UHSIC_P0               3
91 #define PMC_PORT_NUM                    4
92
93 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
94 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
95 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
96
97 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
98
99 /* private data types */
100 /* command requests from the firmware */
101 enum MBOX_CMD_TYPE {
102         MBOX_CMD_MSG_ENABLED = 1,
103         MBOX_CMD_INC_FALC_CLOCK,
104         MBOX_CMD_DEC_FALC_CLOCK,
105         MBOX_CMD_INC_SSPI_CLOCK,
106         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
107         MBOX_CMD_SET_BW,
108         MBOX_CMD_SET_SS_PWR_GATING,
109         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
110         MBOX_CMD_SAVE_DFE_CTLE_CTX,
111         MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
112         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* 11, unused */
113         MBOX_CMD_STAR_HSIC_IDLE,
114         MBOX_CMD_STOP_HSIC_IDLE,
115         MBOX_CMD_DBC_WAKE_STACK, /* unused */
116         MBOX_CMD_HSIC_PRETEND_CONNECT,
117
118         /* needs to be the last cmd */
119         MBOX_CMD_MAX,
120
121         /* resp msg to ack above commands */
122         MBOX_CMD_ACK = 128,
123         MBOX_CMD_NACK
124 };
125
126 struct log_entry {
127         u32 sequence_no;
128         u8 data[FW_LOG_PAYLOAD_SIZE];
129         u8 owner;
130 };
131
132 /* Usb3 Firmware Cfg Table */
133 struct cfgtbl {
134         u32 boot_loadaddr_in_imem;
135         u32 boot_codedfi_offset;
136         u32 boot_codetag;
137         u32 boot_codesize;
138
139         /* Physical memory reserved by Bootloader/BIOS */
140         u32 phys_memaddr;
141         u16 reqphys_memsize;
142         u16 alloc_phys_memsize;
143
144         /* .rodata section */
145         u32 rodata_img_offset;
146         u32 rodata_section_start;
147         u32 rodata_section_end;
148         u32 main_fnaddr;
149
150         u32 fwimg_cksum;
151         u32 fwimg_created_time;
152
153         /* Fields that get filled by linker during linking phase
154          * or initialized in the FW code.
155          */
156         u32 imem_resident_start;
157         u32 imem_resident_end;
158         u32 idirect_start;
159         u32 idirect_end;
160         u32 l2_imem_start;
161         u32 l2_imem_end;
162         u32 version_id;
163         u8 init_ddirect;
164         u8 reserved[3];
165         u32 phys_addr_log_buffer;
166         u32 total_log_entries;
167         u32 dequeue_ptr;
168
169         /*      Below two dummy variables are used to replace
170          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
171          *      retain the size of struct _CFG_TBL used by other AP/Module.
172          */
173         u32 dummy_var1;
174         u32 dummy_var2;
175
176         /* fwimg_len */
177         u32 fwimg_len;
178         u8 magic[8];
179         u32 SS_low_power_entry_timeout;
180         u8 num_hsic_port;
181         u8 padding[139]; /* padding bytes to makeup 256-bytes cfgtbl */
182 };
183
184 struct xusb_save_regs {
185         u32 msi_bar_sz;
186         u32 msi_axi_barst;
187         u32 msi_fpci_barst;
188         u32 msi_vec0;
189         u32 msi_en_vec0;
190         u32 fpci_error_masks;
191         u32 intr_mask;
192         u32 ipfs_intr_enable;
193         u32 ufpci_config;
194         u32 clkgate_hysteresis;
195         u32 xusb_host_mccif_fifo_cntrl;
196
197         /* PG does not mention below */
198         u32 hs_pls;
199         u32 fs_pls;
200         u32 hs_fs_speed;
201         u32 hs_fs_pp;
202         u32 cfg_aru;
203         u32 cfg_order;
204         u32 cfg_fladj;
205         u32 cfg_sid;
206         /* DFE and CTLE */
207         u32 tap1_val[XUSB_SS_PORT_COUNT];
208         u32 amp_val[XUSB_SS_PORT_COUNT];
209         u32 ctle_z_val[XUSB_SS_PORT_COUNT];
210         u32 ctle_g_val[XUSB_SS_PORT_COUNT];
211 };
212
213 struct tegra_xhci_firmware {
214         void *data; /* kernel virtual address */
215         size_t size; /* firmware size */
216         dma_addr_t dma; /* dma address for controller */
217 };
218
219 struct tegra_xhci_firmware_log {
220         dma_addr_t phys_addr;           /* dma-able address */
221         void *virt_addr;                /* kernel va of the shared log buffer */
222         struct log_entry *dequeue;      /* current dequeue pointer (va) */
223         struct circ_buf circ;           /* big circular buffer */
224         u32 seq;                        /* log sequence number */
225
226         struct task_struct *thread;     /* a thread to consume log */
227         struct mutex mutex;
228         wait_queue_head_t read_wait;
229         wait_queue_head_t write_wait;
230         wait_queue_head_t intr_wait;
231         struct dentry *path;
232         struct dentry *log_file;
233         unsigned long flags;
234 };
235
236 /* structure to hold the offsets of padctl registers */
237 struct tegra_xusb_padctl_regs {
238         u16 boot_media_0;
239         u16 usb2_pad_mux_0;
240         u16 usb2_port_cap_0;
241         u16 snps_oc_map_0;
242         u16 usb2_oc_map_0;
243         u16 ss_port_map_0;
244         u16 oc_det_0;
245         u16 elpg_program_0;
246         u16 usb2_bchrg_otgpad0_ctl0_0;
247         u16 usb2_bchrg_otgpad0_ctl1_0;
248         u16 usb2_bchrg_otgpad1_ctl0_0;
249         u16 usb2_bchrg_otgpad1_ctl1_0;
250         u16 usb2_bchrg_otgpad2_ctl0_0;
251         u16 usb2_bchrg_otgpad2_ctl1_0;
252         u16 usb2_bchrg_bias_pad_0;
253         u16 usb2_bchrg_tdcd_dbnc_timer_0;
254         u16 iophy_pll_p0_ctl1_0;
255         u16 iophy_pll_p0_ctl2_0;
256         u16 iophy_pll_p0_ctl3_0;
257         u16 iophy_pll_p0_ctl4_0;
258         u16 iophy_usb3_pad0_ctl1_0;
259         u16 iophy_usb3_pad1_ctl1_0;
260         u16 iophy_usb3_pad0_ctl2_0;
261         u16 iophy_usb3_pad1_ctl2_0;
262         u16 iophy_usb3_pad0_ctl3_0;
263         u16 iophy_usb3_pad1_ctl3_0;
264         u16 iophy_usb3_pad0_ctl4_0;
265         u16 iophy_usb3_pad1_ctl4_0;
266         u16 iophy_misc_pad_p0_ctl1_0;
267         u16 iophy_misc_pad_p1_ctl1_0;
268         u16 iophy_misc_pad_p0_ctl2_0;
269         u16 iophy_misc_pad_p1_ctl2_0;
270         u16 iophy_misc_pad_p0_ctl3_0;
271         u16 iophy_misc_pad_p1_ctl3_0;
272         u16 iophy_misc_pad_p0_ctl4_0;
273         u16 iophy_misc_pad_p1_ctl4_0;
274         u16 iophy_misc_pad_p0_ctl5_0;
275         u16 iophy_misc_pad_p1_ctl5_0;
276         u16 iophy_misc_pad_p0_ctl6_0;
277         u16 iophy_misc_pad_p1_ctl6_0;
278         u16 usb2_otg_pad0_ctl0_0;
279         u16 usb2_otg_pad1_ctl0_0;
280         u16 usb2_otg_pad2_ctl0_0;
281         u16 usb2_otg_pad0_ctl1_0;
282         u16 usb2_otg_pad1_ctl1_0;
283         u16 usb2_otg_pad2_ctl1_0;
284         u16 usb2_bias_pad_ctl0_0;
285         u16 usb2_bias_pad_ctl1_0;
286         u16 usb2_hsic_pad0_ctl0_0;
287         u16 usb2_hsic_pad1_ctl0_0;
288         u16 usb2_hsic_pad0_ctl1_0;
289         u16 usb2_hsic_pad1_ctl1_0;
290         u16 usb2_hsic_pad0_ctl2_0;
291         u16 usb2_hsic_pad1_ctl2_0;
292         u16 ulpi_link_trim_ctl0;
293         u16 ulpi_null_clk_trim_ctl0;
294         u16 hsic_strb_trim_ctl0;
295         u16 wake_ctl0;
296         u16 pm_spare0;
297         u16 iophy_misc_pad_p2_ctl1_0;
298         u16 iophy_misc_pad_p3_ctl1_0;
299         u16 iophy_misc_pad_p4_ctl1_0;
300         u16 iophy_misc_pad_p2_ctl2_0;
301         u16 iophy_misc_pad_p3_ctl2_0;
302         u16 iophy_misc_pad_p4_ctl2_0;
303         u16 iophy_misc_pad_p2_ctl3_0;
304         u16 iophy_misc_pad_p3_ctl3_0;
305         u16 iophy_misc_pad_p4_ctl3_0;
306         u16 iophy_misc_pad_p2_ctl4_0;
307         u16 iophy_misc_pad_p3_ctl4_0;
308         u16 iophy_misc_pad_p4_ctl4_0;
309         u16 iophy_misc_pad_p2_ctl5_0;
310         u16 iophy_misc_pad_p3_ctl5_0;
311         u16 iophy_misc_pad_p4_ctl5_0;
312         u16 iophy_misc_pad_p2_ctl6_0;
313         u16 iophy_misc_pad_p3_ctl6_0;
314         u16 iophy_misc_pad_p4_ctl6_0;
315         u16 usb3_pad_mux_0;
316         u16 iophy_pll_s0_ctl1_0;
317         u16 iophy_pll_s0_ctl2_0;
318         u16 iophy_pll_s0_ctl3_0;
319         u16 iophy_pll_s0_ctl4_0;
320         u16 iophy_misc_pad_s0_ctl1_0;
321         u16 iophy_misc_pad_s0_ctl2_0;
322         u16 iophy_misc_pad_s0_ctl3_0;
323         u16 iophy_misc_pad_s0_ctl4_0;
324         u16 iophy_misc_pad_s0_ctl5_0;
325         u16 iophy_misc_pad_s0_ctl6_0;
326 };
327
328 struct tegra_xhci_hcd {
329         struct platform_device *pdev;
330         struct xhci_hcd *xhci;
331         u16 device_id;
332
333         spinlock_t lock;
334         struct mutex sync_lock;
335
336         int smi_irq;
337         int padctl_irq;
338         int usb3_irq;
339         int usb2_irq;
340
341         bool ss_wake_event;
342         bool ss_pwr_gated;
343         bool host_pwr_gated;
344         bool hs_wake_event;
345         bool host_resume_req;
346         bool lp0_exit;
347         bool dfe_ctx_saved[XUSB_SS_PORT_COUNT];
348         bool ctle_ctx_saved[XUSB_SS_PORT_COUNT];
349         unsigned long last_jiffies;
350         unsigned long host_phy_base;
351         void __iomem *host_phy_virt_base;
352
353         void __iomem *padctl_base;
354         void __iomem *fpci_base;
355         void __iomem *ipfs_base;
356
357         struct tegra_xusb_platform_data *pdata;
358         struct tegra_xusb_board_data *bdata;
359         struct tegra_xusb_padctl_regs *padregs;
360
361         /* mailbox variables */
362         struct mutex mbox_lock;
363         u32 mbox_owner;
364         u32 cmd_type;
365         u32 cmd_data;
366
367         struct regulator *xusb_utmi_vbus_regs[XUSB_UTMI_COUNT];
368
369         struct regulator *xusb_s1p05v_reg;
370         struct regulator *xusb_s3p3v_reg;
371         struct regulator *xusb_s1p8v_reg;
372         struct regulator *vddio_hsic_reg;
373         int vddio_hsic_refcnt;
374
375         struct work_struct mbox_work;
376         struct work_struct ss_elpg_exit_work;
377         struct work_struct host_elpg_exit_work;
378
379         struct clk *host_clk;
380         struct clk *ss_clk;
381
382         /* XUSB Falcon SuperSpeed Clock */
383         struct clk *falc_clk;
384
385         /* EMC Clock */
386         struct clk *emc_clk;
387         /* XUSB SS PI Clock */
388         struct clk *ss_src_clk;
389         /* PLLE Clock */
390         struct clk *plle_clk;
391         struct clk *pll_u_480M;
392         struct clk *clk_m;
393         /* refPLLE clk */
394         struct clk *pll_re_vco_clk;
395         /*
396          * XUSB/IPFS specific registers these need to be saved/restored in
397          * addition to spec defined registers
398          */
399         struct xusb_save_regs sregs;
400         bool usb2_rh_suspend;
401         bool usb3_rh_suspend;
402         bool hc_in_elpg;
403
404         /* otg transceiver */
405         struct usb_phy *transceiver;
406         struct notifier_block otgnb;
407
408         unsigned long usb2_rh_remote_wakeup_ports; /* one bit per port */
409         unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
410         /* firmware loading related */
411         struct tegra_xhci_firmware firmware;
412
413         struct tegra_xhci_firmware_log log;
414 };
415
416 static struct tegra_usb_pmc_data pmc_data[XUSB_UTMI_COUNT];
417 static struct tegra_usb_pmc_data pmc_hsic_data[XUSB_HSIC_COUNT];
418 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
419         u8 port)  __attribute__ ((unused));
420
421 static bool use_bootloader_firmware = true;
422 module_param(use_bootloader_firmware, bool, S_IRUGO);
423 MODULE_PARM_DESC(use_bootloader_firmware, "take bootloader initialized firmware");
424
425 #define FIRMWARE_FILE "xusb_sil_rel_fw"
426 static char *firmware_file = FIRMWARE_FILE;
427 #define FIRMWARE_FILE_HELP      \
428         "used to specify firmware file of Tegra XHCI host controller. "\
429         "This takes effect only if \"use_bootloader_firmware\" is \"N\". " \
430         "Default value is \"" FIRMWARE_FILE "\"."
431
432 module_param(firmware_file, charp, S_IRUGO);
433 MODULE_PARM_DESC(firmware_file, FIRMWARE_FILE_HELP);
434
435 /* functions */
436 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
437 {
438         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
439 }
440
441 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
442 {
443 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
444         WARN_ON(tegra->sync_lock.owner != current);
445 #endif
446 }
447
448 #define for_each_enabled_hsic_pad(_pad, _tegra_xhci_hcd)                \
449         for (_pad = find_next_enabled_hsic_pad(_tegra_xhci_hcd, 0);     \
450             (_pad < XUSB_HSIC_COUNT) && (_pad >= 0);                    \
451             _pad = find_next_enabled_hsic_pad(_tegra_xhci_hcd, _pad + 1))
452
453 static inline int find_next_enabled_pad(struct tegra_xhci_hcd *tegra,
454                                                 int start, int last)
455 {
456         unsigned long portmap = tegra->bdata->portmap;
457         return find_next_bit(&portmap, last , start);
458 }
459
460 static inline int find_next_enabled_hsic_pad(struct tegra_xhci_hcd *tegra,
461                                                 int curr_pad)
462 {
463         int start = XUSB_HSIC_INDEX + curr_pad;
464         int last = XUSB_HSIC_INDEX + XUSB_HSIC_COUNT;
465
466         if ((curr_pad < 0) || (curr_pad >= XUSB_HSIC_COUNT))
467                 return -1;
468
469         return find_next_enabled_pad(tegra, start, last) - XUSB_HSIC_INDEX;
470 }
471
472 static void tegra_xhci_setup_gpio_for_ss_lane(struct tegra_xhci_hcd *tegra)
473 {
474         int err = 0;
475
476         if (!tegra->bdata->gpio_controls_muxed_ss_lanes)
477                 return;
478
479         if (tegra->bdata->lane_owner & BIT(0)) {
480                 /* USB3_SS port1 is using SATA lane so set (MUX_SATA)
481                  * GPIO P11 to '0'
482                  */
483                 err = gpio_request((tegra->bdata->gpio_ss1_sata & 0xffff),
484                         "gpio_ss1_sata");
485                 if (err < 0)
486                         pr_err("%s: gpio_ss1_sata gpio_request failed %d\n",
487                                 __func__, err);
488                 err = gpio_direction_output((tegra->bdata->gpio_ss1_sata
489                         & 0xffff), 1);
490                 if (err < 0)
491                         pr_err("%s: gpio_ss1_sata gpio_direction failed %d\n",
492                                 __func__, err);
493                 __gpio_set_value((tegra->bdata->gpio_ss1_sata & 0xffff),
494                                 ((tegra->bdata->gpio_ss1_sata >> 16)));
495         }
496 }
497
498 static u32 xhci_read_portsc(struct xhci_hcd *xhci, unsigned int port)
499 {
500         int num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
501         __le32 __iomem *addr;
502
503         if (port >= num_ports) {
504                 xhci_err(xhci, "%s invalid port %u\n", __func__, port);
505                 return -1;
506         }
507
508         addr = &xhci->op_regs->port_status_base + (NUM_PORT_REGS * port);
509         return xhci_readl(xhci, addr);
510 }
511
512 static void debug_print_portsc(struct xhci_hcd *xhci)
513 {
514         __le32 __iomem *addr = &xhci->op_regs->port_status_base;
515         u32 reg;
516         int i;
517         int ports;
518
519         ports = HCS_MAX_PORTS(xhci->hcs_params1);
520         for (i = 0; i < ports; i++) {
521                 reg = xhci_read_portsc(xhci, i);
522                 xhci_dbg(xhci, "@%p port %d status reg = 0x%x\n",
523                                 addr, i, (unsigned int) reg);
524                 addr += NUM_PORT_REGS;
525         }
526 }
527 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra);
528
529 static bool is_otg_host(struct tegra_xhci_hcd *tegra)
530 {
531         if (!tegra->transceiver)
532                 return true;
533         else if (tegra->transceiver->state == OTG_STATE_A_HOST)
534                 return true;
535         else
536                 return false;
537 }
538
539 static int update_speed(struct tegra_xhci_hcd *tegra, u8 port)
540 {
541         struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
542         u32 portsc;
543
544         portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port));
545         if (DEV_FULLSPEED(portsc))
546                 return USB_PMC_PORT_SPEED_FULL;
547         else if (DEV_HIGHSPEED(portsc))
548                 return USB_PMC_PORT_SPEED_HIGH;
549         else if (DEV_LOWSPEED(portsc))
550                 return USB_PMC_PORT_SPEED_LOW;
551         else if (DEV_SUPERSPEED(portsc))
552                 return USB_PMC_PORT_SPEED_SUPER;
553         else
554                 return USB_PMC_PORT_SPEED_UNKNOWN;
555 }
556
557 static void pmc_init(struct tegra_xhci_hcd *tegra)
558 {
559         struct tegra_usb_pmc_data *pmc;
560         struct device *dev = &tegra->pdev->dev;
561         int pad;
562
563         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
564                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
565                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
566                         pmc = &pmc_data[pad];
567                         pmc->instance = pad;
568                         pmc->phy_type = TEGRA_USB_PHY_INTF_UTMI;
569                         pmc->port_speed = USB_PMC_PORT_SPEED_HIGH;
570                         pmc->controller_type = TEGRA_USB_3_0;
571                         tegra_usb_pmc_init(pmc);
572                 }
573         }
574
575         for_each_enabled_hsic_pad(pad, tegra) {
576                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
577                 pmc = &pmc_hsic_data[pad];
578                 pmc->instance = pad + 1;
579                 pmc->phy_type = TEGRA_USB_PHY_INTF_HSIC;
580                 pmc->port_speed = USB_PMC_PORT_SPEED_HIGH;
581                 pmc->controller_type = TEGRA_USB_3_0;
582                 tegra_usb_pmc_init(pmc);
583         }
584 }
585
586 static void pmc_setup_wake_detect(struct tegra_xhci_hcd *tegra)
587 {
588         struct tegra_usb_pmc_data *pmc;
589         struct device *dev = &tegra->pdev->dev;
590         u32 portsc;
591         int port;
592         int pad;
593
594         for_each_enabled_hsic_pad(pad, tegra) {
595                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
596
597                 pmc = &pmc_hsic_data[pad];
598                 port = hsic_pad_to_port(pad);
599                 portsc = xhci_read_portsc(tegra->xhci, port);
600                 dev_dbg(dev, "%s hsic pad %d portsc 0x%x\n",
601                         __func__, pad, portsc);
602
603                 if (((int) portsc != -1) && (portsc & PORT_CONNECT))
604                         pmc->pmc_ops->setup_pmc_wake_detect(pmc);
605         }
606
607         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
608                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
609                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
610                         pmc = &pmc_data[pad];
611                         pmc->port_speed = update_speed(tegra, pad);
612                         if (pad == 0) {
613                                 if (is_otg_host(tegra))
614                                         pmc->pmc_ops->setup_pmc_wake_detect(
615                                                                         pmc);
616                         } else
617                                 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
618                 }
619         }
620 }
621
622 static void pmc_disable_bus_ctrl(struct tegra_xhci_hcd *tegra)
623 {
624         struct tegra_usb_pmc_data *pmc;
625         struct device *dev = &tegra->pdev->dev;
626         int pad;
627
628         for_each_enabled_hsic_pad(pad, tegra) {
629                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
630
631                 pmc = &pmc_hsic_data[pad];
632                 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
633         }
634
635         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
636                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
637                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
638                         pmc = &pmc_data[pad];
639                         pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
640                 }
641         }
642 }
643
644 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
645 {
646         void __iomem *fpci_base = tegra->fpci_base;
647         struct platform_device *pdev = tegra->pdev;
648         u32 input_addr;
649         u32 data;
650         u32 csb_page_select;
651
652         /* to select the appropriate CSB page to write to */
653         csb_page_select = CSB_PAGE_SELECT(addr);
654
655         dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
656                         csb_page_select);
657
658         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
659
660         /* selects the appropriate offset in the page to read from */
661         input_addr = CSB_PAGE_OFFSET(addr);
662         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
663
664         dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
665                         input_addr, data);
666         return data;
667 }
668
669 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
670 {
671         void __iomem *fpci_base = tegra->fpci_base;
672         struct platform_device *pdev = tegra->pdev;
673         u32 input_addr;
674         u32 csb_page_select;
675
676         /* to select the appropriate CSB page to write to */
677         csb_page_select = CSB_PAGE_SELECT(addr);
678
679         dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
680                         csb_page_select);
681
682         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
683
684         /* selects the appropriate offset in the page to write to */
685         input_addr = CSB_PAGE_OFFSET(addr);
686         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
687
688         dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
689                         input_addr, data);
690 }
691
692 static int fw_message_send(struct tegra_xhci_hcd *tegra,
693         enum MBOX_CMD_TYPE type, u32 data)
694 {
695         struct device *dev = &tegra->pdev->dev;
696         void __iomem *base = tegra->fpci_base;
697         unsigned long target;
698         u32 reg;
699
700         dev_dbg(dev, "%s type %d data 0x%x\n", __func__, type, data);
701
702         mutex_lock(&tegra->mbox_lock);
703
704         target = jiffies + msecs_to_jiffies(20);
705         /* wait mailbox to become idle, timeout in 20ms */
706         while (((reg = readl(base + XUSB_CFG_ARU_MBOX_OWNER)) != 0) &&
707                 time_is_after_jiffies(target)) {
708                 mutex_unlock(&tegra->mbox_lock);
709                 usleep_range(100, 200);
710                 mutex_lock(&tegra->mbox_lock);
711         }
712
713         if (reg != 0) {
714                 dev_err(dev, "%s mailbox is still busy\n", __func__);
715                 goto timeout;
716         }
717
718         target = jiffies + msecs_to_jiffies(10);
719         /* acquire mailbox , timeout in 10ms */
720         writel(MBOX_OWNER_SW, base + XUSB_CFG_ARU_MBOX_OWNER);
721         while (((reg = readl(base + XUSB_CFG_ARU_MBOX_OWNER)) != MBOX_OWNER_SW)
722                 && time_is_after_jiffies(target)) {
723                 mutex_unlock(&tegra->mbox_lock);
724                 usleep_range(100, 200);
725                 mutex_lock(&tegra->mbox_lock);
726                 writel(MBOX_OWNER_SW, base + XUSB_CFG_ARU_MBOX_OWNER);
727         }
728
729         if (reg != MBOX_OWNER_SW) {
730                 dev_err(dev, "%s acquire mailbox timeout\n", __func__);
731                 goto timeout;
732         }
733
734         reg = CMD_TYPE(type) | CMD_DATA(data);
735         writel(reg, base + XUSB_CFG_ARU_MBOX_DATA_IN);
736
737         reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
738         reg |= MBOX_INT_EN | MBOX_FALC_INT_EN;
739         writel(reg, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
740
741         mutex_unlock(&tegra->mbox_lock);
742         return 0;
743
744 timeout:
745         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_CMD);
746         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_DATA_IN);
747         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_DATA_OUT);
748         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_OWNER);
749         mutex_unlock(&tegra->mbox_lock);
750         return -ETIMEDOUT;
751 }
752
753 /**
754  * fw_log_next - find next log entry in a tegra_xhci_firmware_log context.
755  *      This function takes care of wrapping. That means when current log entry
756  *      is the last one, it returns with the first one.
757  *
758  * @param log   The tegra_xhci_firmware_log context.
759  * @param this  The current log entry.
760  * @return      The log entry which is next to the current one.
761  */
762 static inline struct log_entry *fw_log_next(
763                 struct tegra_xhci_firmware_log *log, struct log_entry *this)
764 {
765         struct log_entry *first = (struct log_entry *) log->virt_addr;
766         struct log_entry *last = first + FW_LOG_COUNT - 1;
767
768         WARN((this < first) || (this > last), "%s: invalid input\n", __func__);
769
770         return (this == last) ? first : (this + 1);
771 }
772
773 /**
774  * fw_log_update_dequeue_pointer - update dequeue pointer to both firmware and
775  *      tegra_xhci_firmware_log.dequeue.
776  *
777  * @param log   The tegra_xhci_firmware_log context.
778  * @param n     Counts of log entries to fast-forward.
779  */
780 static inline void fw_log_update_deq_pointer(
781                 struct tegra_xhci_firmware_log *log, int n)
782 {
783         struct tegra_xhci_hcd *tegra =
784                         container_of(log, struct tegra_xhci_hcd, log);
785         struct device *dev = &tegra->pdev->dev;
786         struct log_entry *deq = tegra->log.dequeue;
787         dma_addr_t physical_addr;
788         u32 reg;
789
790         dev_dbg(dev, "curr 0x%p fast-forward %d entries\n", deq, n);
791         while (n-- > 0)
792                 deq = fw_log_next(log, deq);
793
794         tegra->log.dequeue = deq;
795         physical_addr = tegra->log.phys_addr +
796                         ((u8 *)deq - (u8 *)tegra->log.virt_addr);
797
798         /* update dequeue pointer to firmware */
799         reg = (FW_IOCTL_LOG_DEQUEUE_LOW << FW_IOCTL_TYPE_SHIFT);
800         reg |= (physical_addr & 0xffff); /* lower 16-bits */
801         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
802
803         reg = (FW_IOCTL_LOG_DEQUEUE_HIGH << FW_IOCTL_TYPE_SHIFT);
804         reg |= ((physical_addr >> 16) & 0xffff); /* higher 16-bits */
805         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
806
807         dev_dbg(dev, "new 0x%p physical addr 0x%x\n", deq, physical_addr);
808 }
809
810 static inline bool circ_buffer_full(struct circ_buf *circ)
811 {
812         int space = CIRC_SPACE(circ->head, circ->tail, CIRC_BUF_SIZE);
813
814         return (space <= FW_LOG_SIZE);
815 }
816
817 static inline bool fw_log_available(struct tegra_xhci_hcd *tegra)
818 {
819         return (tegra->log.dequeue->owner == DRIVER);
820 }
821
822 /**
823  * fw_log_wait_empty_timeout - wait firmware log thread to clean up shared
824  *      log buffer.
825  * @param tegra:        tegra_xhci_hcd context
826  * @param msec:         timeout value in millisecond
827  * @return true:        shared log buffer is empty,
828  *         false:       shared log buffer isn't empty.
829  */
830 static inline bool fw_log_wait_empty_timeout(struct tegra_xhci_hcd *tegra,
831                 unsigned timeout)
832 {
833         unsigned long target = jiffies + msecs_to_jiffies(timeout);
834         bool ret;
835
836         mutex_lock(&tegra->log.mutex);
837
838         while (fw_log_available(tegra) && time_is_after_jiffies(target)) {
839                 mutex_unlock(&tegra->log.mutex);
840                 usleep_range(1000, 2000);
841                 mutex_lock(&tegra->log.mutex);
842         }
843
844         ret = fw_log_available(tegra);
845         mutex_unlock(&tegra->log.mutex);
846
847         return ret;
848 }
849
850 /**
851  * fw_log_copy - copy firmware log from device's buffer to driver's circular
852  *      buffer.
853  * @param tegra tegra_xhci_hcd context
854  * @return true,        We still have firmware log in device's buffer to copy.
855  *                      This function returned due the driver's circular buffer
856  *                      is full. Caller should invoke this function again as
857  *                      soon as there is space in driver's circular buffer.
858  *         false,       Device's buffer is empty.
859  */
860 static inline bool fw_log_copy(struct tegra_xhci_hcd *tegra)
861 {
862         struct device *dev = &tegra->pdev->dev;
863         struct circ_buf *circ = &tegra->log.circ;
864         int head, tail;
865         int buffer_len, copy_len;
866         struct log_entry *entry;
867         struct log_entry *first = tegra->log.virt_addr;
868
869         while (fw_log_available(tegra)) {
870
871                 /* calculate maximum contiguous driver buffer length */
872                 head = circ->head;
873                 tail = ACCESS_ONCE(circ->tail);
874                 buffer_len = CIRC_SPACE_TO_END(head, tail, CIRC_BUF_SIZE);
875                 /* round down to FW_LOG_SIZE */
876                 buffer_len -= (buffer_len % FW_LOG_SIZE);
877                 if (!buffer_len)
878                         return true; /* log available but no space left */
879
880                 /* calculate maximum contiguous log copy length */
881                 entry = tegra->log.dequeue;
882                 copy_len = 0;
883                 do {
884                         if (tegra->log.seq != entry->sequence_no) {
885                                 dev_warn(dev,
886                                 "%s: discontinuous seq no, expect %u get %u\n",
887                                 __func__, tegra->log.seq, entry->sequence_no);
888                         }
889                         tegra->log.seq = entry->sequence_no + 1;
890
891                         copy_len += FW_LOG_SIZE;
892                         buffer_len -= FW_LOG_SIZE;
893                         if (!buffer_len)
894                                 break; /* no space left */
895                         entry = fw_log_next(&tegra->log, entry);
896                 } while ((entry->owner == DRIVER) && (entry != first));
897
898                 memcpy(&circ->buf[head], tegra->log.dequeue, copy_len);
899                 memset(tegra->log.dequeue, 0, copy_len);
900                 circ->head = (circ->head + copy_len) & (CIRC_BUF_SIZE - 1);
901
902                 mb();
903
904                 fw_log_update_deq_pointer(&tegra->log, copy_len/FW_LOG_SIZE);
905
906                 dev_dbg(dev, "copied %d entries, new dequeue 0x%p\n",
907                                 copy_len/FW_LOG_SIZE, tegra->log.dequeue);
908                 wake_up_interruptible(&tegra->log.read_wait);
909         }
910
911         return false;
912 }
913
914 static int fw_log_thread(void *data)
915 {
916         struct tegra_xhci_hcd *tegra = data;
917         struct device *dev = &tegra->pdev->dev;
918         struct circ_buf *circ = &tegra->log.circ;
919         bool logs_left;
920
921         dev_dbg(dev, "start firmware log thread\n");
922
923         do {
924                 mutex_lock(&tegra->log.mutex);
925                 if (circ_buffer_full(circ)) {
926                         mutex_unlock(&tegra->log.mutex);
927                         dev_info(dev, "%s: circ buffer full\n", __func__);
928                         wait_event_interruptible(tegra->log.write_wait,
929                             kthread_should_stop() || !circ_buffer_full(circ));
930                         mutex_lock(&tegra->log.mutex);
931                 }
932
933                 logs_left = fw_log_copy(tegra);
934                 mutex_unlock(&tegra->log.mutex);
935
936                 /* relax if no logs left  */
937                 if (!logs_left)
938                         wait_event_interruptible_timeout(tegra->log.intr_wait,
939                                 fw_log_available(tegra), FW_LOG_THREAD_RELAX);
940         } while (!kthread_should_stop());
941
942         dev_dbg(dev, "stop firmware log thread\n");
943         return 0;
944 }
945
946 static inline bool circ_buffer_empty(struct circ_buf *circ)
947 {
948         return (CIRC_CNT(circ->head, circ->tail, CIRC_BUF_SIZE) == 0);
949 }
950
951 static ssize_t fw_log_file_read(struct file *file, char __user *buf,
952                 size_t count, loff_t *offp)
953 {
954         struct tegra_xhci_hcd *tegra = file->private_data;
955         struct platform_device *pdev = tegra->pdev;
956         struct circ_buf *circ = &tegra->log.circ;
957         int head, tail;
958         size_t n = 0;
959         int s;
960
961         mutex_lock(&tegra->log.mutex);
962
963         while (circ_buffer_empty(circ)) {
964                 mutex_unlock(&tegra->log.mutex);
965                 if (file->f_flags & O_NONBLOCK)
966                         return -EAGAIN; /* non-blocking read */
967
968                 dev_dbg(&pdev->dev, "%s: nothing to read\n", __func__);
969
970                 if (wait_event_interruptible(tegra->log.read_wait,
971                                 !circ_buffer_empty(circ)))
972                         return -ERESTARTSYS;
973
974                 if (mutex_lock_interruptible(&tegra->log.mutex))
975                         return -ERESTARTSYS;
976         }
977
978         while (count > 0) {
979                 head = ACCESS_ONCE(circ->head);
980                 tail = circ->tail;
981                 s = min_t(int, count,
982                                 CIRC_CNT_TO_END(head, tail, CIRC_BUF_SIZE));
983
984                 if (s > 0) {
985                         if (copy_to_user(&buf[n], &circ->buf[tail], s)) {
986                                 dev_warn(&pdev->dev, "copy_to_user failed\n");
987                                 mutex_unlock(&tegra->log.mutex);
988                                 return -EFAULT;
989                         }
990                         circ->tail = (circ->tail + s) & (CIRC_BUF_SIZE - 1);
991
992                         count -= s;
993                         n += s;
994                 } else
995                         break;
996         }
997
998         mutex_unlock(&tegra->log.mutex);
999
1000         wake_up_interruptible(&tegra->log.write_wait);
1001
1002         dev_dbg(&pdev->dev, "%s: %d bytes\n", __func__, n);
1003
1004         return n;
1005 }
1006
1007 static int fw_log_file_open(struct inode *inode, struct file *file)
1008 {
1009         struct tegra_xhci_hcd *tegra;
1010         file->private_data = inode->i_private;
1011         tegra = file->private_data;
1012
1013         if (test_and_set_bit(FW_LOG_FILE_OPENED, &tegra->log.flags)) {
1014                 dev_info(&tegra->pdev->dev, "%s: already opened\n", __func__);
1015                 return -EBUSY;
1016         }
1017
1018         return 0;
1019 }
1020
1021 static int fw_log_file_close(struct inode *inode, struct file *file)
1022 {
1023         struct tegra_xhci_hcd *tegra = file->private_data;
1024
1025         clear_bit(FW_LOG_FILE_OPENED, &tegra->log.flags);
1026
1027         return 0;
1028 }
1029
1030 static const struct file_operations firmware_log_fops = {
1031                 .open           = fw_log_file_open,
1032                 .release        = fw_log_file_close,
1033                 .read           = fw_log_file_read,
1034                 .owner          = THIS_MODULE,
1035 };
1036
1037 static int fw_log_init(struct tegra_xhci_hcd *tegra)
1038 {
1039         struct platform_device *pdev = tegra->pdev;
1040         int rc = 0;
1041
1042         /* allocate buffer to be shared between driver and firmware */
1043         tegra->log.virt_addr = dma_alloc_writecombine(&pdev->dev,
1044                         FW_LOG_RING_SIZE, &tegra->log.phys_addr, GFP_KERNEL);
1045
1046         if (!tegra->log.virt_addr) {
1047                 dev_err(&pdev->dev, "dma_alloc_writecombine() size %d failed\n",
1048                                 FW_LOG_RING_SIZE);
1049                 return -ENOMEM;
1050         }
1051
1052         dev_info(&pdev->dev, "%d bytes log buffer physical 0x%u virtual 0x%p\n",
1053                 FW_LOG_RING_SIZE, tegra->log.phys_addr, tegra->log.virt_addr);
1054
1055         memset(tegra->log.virt_addr, 0, FW_LOG_RING_SIZE);
1056         tegra->log.dequeue = tegra->log.virt_addr;
1057
1058         tegra->log.circ.buf = vmalloc(CIRC_BUF_SIZE);
1059         if (!tegra->log.circ.buf) {
1060                 dev_err(&pdev->dev, "vmalloc size %d failed\n", CIRC_BUF_SIZE);
1061                 rc = -ENOMEM;
1062                 goto error_free_dma;
1063         }
1064
1065         tegra->log.circ.head = 0;
1066         tegra->log.circ.tail = 0;
1067
1068         init_waitqueue_head(&tegra->log.read_wait);
1069         init_waitqueue_head(&tegra->log.write_wait);
1070         init_waitqueue_head(&tegra->log.intr_wait);
1071
1072         mutex_init(&tegra->log.mutex);
1073
1074         tegra->log.path = debugfs_create_dir("tegra_xhci", NULL);
1075         if (IS_ERR_OR_NULL(tegra->log.path)) {
1076                 dev_warn(&pdev->dev, "debugfs_create_dir() failed\n");
1077                 rc = -ENOMEM;
1078                 goto error_free_mem;
1079         }
1080
1081         tegra->log.log_file = debugfs_create_file("firmware_log",
1082                         S_IRUGO, tegra->log.path, tegra, &firmware_log_fops);
1083         if ((!tegra->log.log_file) ||
1084                         (tegra->log.log_file == ERR_PTR(-ENODEV))) {
1085                 dev_warn(&pdev->dev, "debugfs_create_file() failed\n");
1086                 rc = -ENOMEM;
1087                 goto error_remove_debugfs_path;
1088         }
1089
1090         tegra->log.thread = kthread_run(fw_log_thread, tegra, "xusb-fw-log");
1091         if (IS_ERR(tegra->log.thread)) {
1092                 dev_warn(&pdev->dev, "kthread_run() failed\n");
1093                 rc = -ENOMEM;
1094                 goto error_remove_debugfs_file;
1095         }
1096
1097         set_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags);
1098         return rc;
1099
1100 error_remove_debugfs_file:
1101         debugfs_remove(tegra->log.log_file);
1102 error_remove_debugfs_path:
1103         debugfs_remove(tegra->log.path);
1104 error_free_mem:
1105         vfree(tegra->log.circ.buf);
1106 error_free_dma:
1107         dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1108                         tegra->log.virt_addr, tegra->log.phys_addr);
1109         memset(&tegra->log, sizeof(tegra->log), 0);
1110         return rc;
1111 }
1112
1113 static void fw_log_deinit(struct tegra_xhci_hcd *tegra)
1114 {
1115         struct platform_device *pdev = tegra->pdev;
1116
1117         if (test_and_clear_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
1118
1119                 debugfs_remove(tegra->log.log_file);
1120                 debugfs_remove(tegra->log.path);
1121
1122                 wake_up_interruptible(&tegra->log.read_wait);
1123                 wake_up_interruptible(&tegra->log.write_wait);
1124                 kthread_stop(tegra->log.thread);
1125
1126                 mutex_lock(&tegra->log.mutex);
1127                 dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1128                         tegra->log.virt_addr, tegra->log.phys_addr);
1129                 vfree(tegra->log.circ.buf);
1130                 tegra->log.circ.head = tegra->log.circ.tail = 0;
1131                 mutex_unlock(&tegra->log.mutex);
1132
1133                 mutex_destroy(&tegra->log.mutex);
1134         }
1135 }
1136
1137 /* hsic pad operations */
1138 /*
1139  * HSIC pads need VDDIO_HSIC power rail turned on to be functional. There is
1140  * only one VDDIO_HSIC power rail shared by all HSIC pads.
1141  */
1142 static int hsic_power_rail_enable(struct tegra_xhci_hcd *tegra)
1143 {
1144         struct device *dev = &tegra->pdev->dev;
1145         struct tegra_xusb_regulator_name *supply = &tegra->pdata->bdata->supply;
1146         int ret;
1147
1148         if (tegra->vddio_hsic_reg)
1149                 goto done;
1150
1151         tegra->vddio_hsic_reg = devm_regulator_get(dev, supply->vddio_hsic);
1152         if (IS_ERR_OR_NULL(tegra->vddio_hsic_reg)) {
1153                 dev_err(dev, "%s get vddio_hsic failed\n", __func__);
1154                 ret = PTR_ERR(tegra->vddio_hsic_reg);
1155                 goto get_failed;
1156         }
1157
1158         dev_dbg(dev, "%s regulator_enable vddio_hsic\n", __func__);
1159         ret = regulator_enable(tegra->vddio_hsic_reg);
1160         if (ret < 0) {
1161                 dev_err(dev, "%s enable vddio_hsic failed\n", __func__);
1162                 goto enable_failed;
1163         }
1164
1165 done:
1166         tegra->vddio_hsic_refcnt++;
1167         WARN(tegra->vddio_hsic_refcnt > XUSB_HSIC_COUNT,
1168                         "vddio_hsic_refcnt exceeds\n");
1169         return 0;
1170
1171 enable_failed:
1172         devm_regulator_put(tegra->vddio_hsic_reg);
1173 get_failed:
1174         tegra->vddio_hsic_reg = NULL;
1175         return ret;
1176 }
1177
1178 static int hsic_power_rail_disable(struct tegra_xhci_hcd *tegra)
1179 {
1180         struct device *dev = &tegra->pdev->dev;
1181         int ret;
1182
1183         WARN_ON(!tegra->vddio_hsic_reg || !tegra->vddio_hsic_refcnt);
1184
1185         tegra->vddio_hsic_refcnt--;
1186         if (tegra->vddio_hsic_refcnt)
1187                 return 0;
1188
1189         dev_dbg(dev, "%s regulator_disable vddio_hsic\n", __func__);
1190         ret = regulator_disable(tegra->vddio_hsic_reg);
1191         if (ret < 0) {
1192                 dev_err(dev, "%s disable vddio_hsic failed\n", __func__);
1193                 tegra->vddio_hsic_refcnt++;
1194                 return ret;
1195         }
1196
1197         devm_regulator_put(tegra->vddio_hsic_reg);
1198         tegra->vddio_hsic_reg = NULL;
1199
1200         return 0;
1201 }
1202
1203 static int hsic_pad_enable(struct tegra_xhci_hcd *tegra, unsigned pad)
1204 {
1205         struct device *dev = &tegra->pdev->dev;
1206         void __iomem *base = tegra->padctl_base;
1207         struct tegra_xusb_hsic_config *hsic = &tegra->bdata->hsic[pad];
1208         u32 reg;
1209
1210         if (pad >= XUSB_HSIC_COUNT) {
1211                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1212                 return -EINVAL;
1213         }
1214
1215         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1216
1217         reg = readl(base + HSIC_PAD_CTL_2(pad));
1218         reg &= ~(RX_STROBE_TRIM(~0) | RX_DATA_TRIM(~0));
1219         reg |= RX_STROBE_TRIM(hsic->rx_strobe_trim);
1220         reg |= RX_DATA_TRIM(hsic->rx_data_trim);
1221         writel(reg, base + HSIC_PAD_CTL_2(pad));
1222
1223         reg = readl(base + HSIC_PAD_CTL_0(pad));
1224         reg &= ~(TX_RTUNEP(~0) | TX_RTUNEN(~0) | TX_SLEWP(~0) | TX_SLEWN(~0));
1225         reg |= TX_RTUNEP(hsic->tx_rtune_p);
1226         reg |= TX_RTUNEN(hsic->tx_rtune_n);
1227         reg |= TX_SLEWP(hsic->tx_slew_p);
1228         reg |= TX_SLEWN(hsic->tx_slew_n);
1229         writel(reg, base + HSIC_PAD_CTL_0(pad));
1230
1231         reg = readl(base + HSIC_PAD_CTL_1(pad));
1232         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1233         reg |= (RPD_DATA | RPU_STROBE); /* keep HSIC in IDLE */
1234         if (hsic->auto_term_en)
1235                 reg |= AUTO_TERM_EN;
1236         else
1237                 reg &= ~AUTO_TERM_EN;
1238         reg &= ~(PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1239         writel(reg, base + HSIC_PAD_CTL_1(pad));
1240
1241         reg = readl(base + HSIC_STRB_TRIM_CONTROL);
1242         reg &= ~(STRB_TRIM_VAL(~0));
1243         reg |= STRB_TRIM_VAL(hsic->strb_trim_val);
1244         writel(reg, base + HSIC_STRB_TRIM_CONTROL);
1245
1246         reg = readl(base + USB2_PAD_MUX);
1247         reg |= USB2_HSIC_PAD_PORT(pad);
1248         writel(reg, base + USB2_PAD_MUX);
1249
1250         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1251         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1252         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1253         reg_dump(dev, base, HSIC_STRB_TRIM_CONTROL);
1254         reg_dump(dev, base, USB2_PAD_MUX);
1255         return 0;
1256 }
1257
1258 static void hsic_pad_pretend_connect(struct tegra_xhci_hcd *tegra)
1259 {
1260         struct device *dev = &tegra->pdev->dev;
1261         struct tegra_xusb_hsic_config *hsic;
1262         struct usb_device *hs_root_hub = tegra->xhci->main_hcd->self.root_hub;
1263         int pad;
1264         u32 portsc;
1265         int port;
1266         int enabled_pads = 0;
1267         unsigned long wait_ports = 0;
1268         unsigned long target;
1269
1270         for_each_enabled_hsic_pad(pad, tegra) {
1271                 hsic = &tegra->bdata->hsic[pad];
1272                 if (hsic->pretend_connect)
1273                         enabled_pads++;
1274         }
1275
1276         if (enabled_pads == 0) {
1277                 dev_dbg(dev, "%s no hsic pretend_connect enabled\n", __func__);
1278                 return;
1279         }
1280
1281         usb_disable_autosuspend(hs_root_hub);
1282
1283         for_each_enabled_hsic_pad(pad, tegra) {
1284                 hsic = &tegra->bdata->hsic[pad];
1285                 if (!hsic->pretend_connect)
1286                         continue;
1287
1288                 port = hsic_pad_to_port(pad);
1289                 portsc = xhci_read_portsc(tegra->xhci, port);
1290                 dev_dbg(dev, "%s pad %u portsc 0x%x\n", __func__, pad, portsc);
1291
1292                 if (!(portsc & PORT_CONNECT)) {
1293                         /* firmware wants 1-based port index */
1294                         fw_message_send(tegra,
1295                                 MBOX_CMD_HSIC_PRETEND_CONNECT, BIT(port + 1));
1296                 }
1297
1298                 set_bit(port, &wait_ports);
1299         }
1300
1301         /* wait till port reaches U0 */
1302         target = jiffies + msecs_to_jiffies(500);
1303         do {
1304                 for_each_set_bit(port, &wait_ports, BITS_PER_LONG) {
1305                         portsc = xhci_read_portsc(tegra->xhci, port);
1306                         pad = port_to_hsic_pad(port);
1307                         dev_dbg(dev, "%s pad %u portsc 0x%x\n", __func__,
1308                                 pad, portsc);
1309                         if ((PORT_PLS_MASK & portsc) == XDEV_U0)
1310                                 clear_bit(port, &wait_ports);
1311                 }
1312
1313                 if (wait_ports)
1314                         usleep_range(1000, 5000);
1315         } while (wait_ports && time_is_after_jiffies(target));
1316
1317         if (wait_ports)
1318                 dev_warn(dev, "%s HSIC pad(s) didn't reach U0.\n", __func__);
1319
1320         usb_enable_autosuspend(hs_root_hub);
1321
1322         return;
1323 }
1324
1325 static int hsic_pad_disable(struct tegra_xhci_hcd *tegra, unsigned pad)
1326 {
1327         struct device *dev = &tegra->pdev->dev;
1328         void __iomem *base = tegra->padctl_base;
1329         u32 reg;
1330
1331         if (pad >= XUSB_HSIC_COUNT) {
1332                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1333                 return -EINVAL;
1334         }
1335
1336         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1337
1338         reg = readl(base + USB2_PAD_MUX);
1339         reg &= ~USB2_HSIC_PAD_PORT(pad);
1340         writel(reg, base + USB2_PAD_MUX);
1341
1342         reg = readl(base + HSIC_PAD_CTL_1(pad));
1343         reg |= (PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1344         writel(reg, base + HSIC_PAD_CTL_1(pad));
1345
1346         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1347         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1348         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1349         reg_dump(dev, base, USB2_PAD_MUX);
1350         return 0;
1351 }
1352
1353 enum hsic_pad_pupd {
1354         PUPD_DISABLE = 0,
1355         PUPD_IDLE,
1356         PUPD_RESET
1357 };
1358
1359 static int hsic_pad_pupd_set(struct tegra_xhci_hcd *tegra, unsigned pad,
1360         enum hsic_pad_pupd pupd)
1361 {
1362         struct device *dev = &tegra->pdev->dev;
1363         void __iomem *base = tegra->padctl_base;
1364         u32 reg;
1365
1366         if (pad >= XUSB_HSIC_COUNT) {
1367                 dev_err(dev, "%s invalid HSIC pad number %u\n", __func__, pad);
1368                 return -EINVAL;
1369         }
1370
1371         dev_dbg(dev, "%s pad %u pupd %d\n", __func__, pad, pupd);
1372
1373         reg = readl(base + HSIC_PAD_CTL_1(pad));
1374         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1375
1376         if (pupd == PUPD_IDLE)
1377                 reg |= (RPD_DATA | RPU_STROBE);
1378         else if (pupd == PUPD_RESET)
1379                 reg |= (RPD_DATA | RPD_STROBE);
1380         else if (pupd != PUPD_DISABLE) {
1381                 dev_err(dev, "%s invalid pupd %d\n", __func__, pupd);
1382                 return -EINVAL;
1383         }
1384
1385         writel(reg, base + HSIC_PAD_CTL_1(pad));
1386
1387         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1388
1389         return 0;
1390 }
1391
1392
1393 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
1394 {
1395         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1396         struct xhci_hcd *xhci = tegra->xhci;
1397         u32 reg;
1398
1399         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
1400         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1401         xhci_info(xhci, " PAD MUX = %x\n", reg);
1402         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1403         xhci_info(xhci, " PORT CAP = %x\n", reg);
1404         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1405         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
1406         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1407         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
1408         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1409         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
1410         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1411         xhci_info(xhci, " OC DET 0= %x\n", reg);
1412         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad0_ctl2_0);
1413         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
1414         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad1_ctl2_0);
1415         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
1416         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl0_0);
1417         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
1418         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl0_0);
1419         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
1420         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl1_0);
1421         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
1422         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl1_0);
1423         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
1424         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1425         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
1426         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad0_ctl0_0);
1427         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
1428         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad1_ctl0_0);
1429         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
1430         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
1431 }
1432
1433 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
1434 {
1435         u32 reg;
1436
1437         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1438         reg |= IPFS_EN_FPCI;
1439         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1440         udelay(10);
1441
1442         /* Program Bar0 Space */
1443         reg = readl(tegra->fpci_base + XUSB_CFG_4);
1444         reg |= tegra->host_phy_base;
1445         writel(reg, tegra->fpci_base + XUSB_CFG_4);
1446         usleep_range(100, 200);
1447
1448         /* Enable Bus Master */
1449         reg = readl(tegra->fpci_base + XUSB_CFG_1);
1450         reg |= 0x7;
1451         writel(reg, tegra->fpci_base + XUSB_CFG_1);
1452
1453         /* Set intr mask to enable intr assertion */
1454         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1455         reg |= IPFS_IP_INT_MASK;
1456         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1457
1458         /* Set hysteris to 0x80 */
1459         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1460 }
1461
1462 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
1463                 struct platform_device *pdev)
1464 {
1465         struct tegra_xusb_regulator_name *supply = &tegra->bdata->supply;
1466         int i;
1467         int err = 0;
1468
1469         tegra->xusb_s3p3v_reg =
1470                         devm_regulator_get(&pdev->dev, supply->s3p3v);
1471         if (IS_ERR(tegra->xusb_s3p3v_reg)) {
1472                 dev_err(&pdev->dev, "3p3v: regulator not found: %ld."
1473                         , PTR_ERR(tegra->xusb_s3p3v_reg));
1474                 err = PTR_ERR(tegra->xusb_s3p3v_reg);
1475                 goto err_null_regulator;
1476         } else {
1477                 err = regulator_enable(tegra->xusb_s3p3v_reg);
1478                 if (err < 0) {
1479                         dev_err(&pdev->dev,
1480                                 "3p3v: regulator enable failed:%d\n", err);
1481                         goto err_null_regulator;
1482                 }
1483         }
1484
1485         /* enable utmi vbuses */
1486         memset(tegra->xusb_utmi_vbus_regs, 0,
1487                         sizeof(tegra->xusb_utmi_vbus_regs));
1488         for (i = 0; i < XUSB_UTMI_COUNT; i++) {
1489                 struct regulator *reg = NULL;
1490                 const char *reg_name = supply->utmi_vbuses[i];
1491                 if (BIT(XUSB_UTMI_INDEX + i) & tegra->bdata->portmap) {
1492                         if (i == 0 && tegra->transceiver)
1493                                 continue;
1494                         reg = devm_regulator_get(&pdev->dev, reg_name);
1495                         if (IS_ERR(reg)) {
1496                                 dev_err(&pdev->dev,
1497                                         "%s regulator not found: %ld.",
1498                                         reg_name, PTR_ERR(reg));
1499                                 err = PTR_ERR(reg);
1500                         } else {
1501                                 err = regulator_enable(reg);
1502                                 if (err < 0) {
1503                                         dev_err(&pdev->dev,
1504                                         "%s: regulator enable failed: %d\n",
1505                                         reg_name, err);
1506                                 }
1507                         }
1508                         if (err)
1509                                 goto err_put_utmi_vbus_reg;
1510                 }
1511                 tegra->xusb_utmi_vbus_regs[i] = reg;
1512         }
1513
1514         tegra->xusb_s1p8v_reg =
1515                 devm_regulator_get(&pdev->dev, supply->s1p8v);
1516         if (IS_ERR(tegra->xusb_s1p8v_reg)) {
1517                 dev_err(&pdev->dev, "1p8v regulator not found: %ld."
1518                         , PTR_ERR(tegra->xusb_s1p8v_reg));
1519                 err = PTR_ERR(tegra->xusb_s1p8v_reg);
1520                 goto err_put_utmi_vbus_reg;
1521         } else {
1522                 err = regulator_enable(tegra->xusb_s1p8v_reg);
1523                 if (err < 0) {
1524                         dev_err(&pdev->dev,
1525                         "1p8v: regulator enable failed:%d\n", err);
1526                         goto err_put_utmi_vbus_reg;
1527                 }
1528         }
1529
1530         tegra->xusb_s1p05v_reg =
1531                         devm_regulator_get(&pdev->dev, supply->s1p05v);
1532         if (IS_ERR(tegra->xusb_s1p05v_reg)) {
1533                 dev_err(&pdev->dev, "1p05v: regulator not found: %ld."
1534                         , PTR_ERR(tegra->xusb_s1p05v_reg));
1535                 err = PTR_ERR(tegra->xusb_s1p05v_reg);
1536                 goto err_put_s1p8v_reg;
1537         } else {
1538                 err = regulator_enable(tegra->xusb_s1p05v_reg);
1539                 if (err < 0) {
1540                         dev_err(&pdev->dev,
1541                         "1p05v: regulator enable failed:%d\n", err);
1542                         goto err_put_s1p8v_reg;
1543                 }
1544         }
1545
1546         return err;
1547
1548 err_put_s1p8v_reg:
1549         regulator_disable(tegra->xusb_s1p8v_reg);
1550 err_put_utmi_vbus_reg:
1551         for (i = 0; i < XUSB_UTMI_COUNT; i++) {
1552                 struct regulator *reg = tegra->xusb_utmi_vbus_regs[i];
1553                 if (!IS_ERR_OR_NULL(reg))
1554                         regulator_disable(reg);
1555         }
1556         regulator_disable(tegra->xusb_s3p3v_reg);
1557 err_null_regulator:
1558         for (i = 0; i < XUSB_UTMI_COUNT; i++)
1559                 tegra->xusb_utmi_vbus_regs[i] = NULL;
1560         tegra->xusb_s1p05v_reg = NULL;
1561         tegra->xusb_s3p3v_reg = NULL;
1562         tegra->xusb_s1p8v_reg = NULL;
1563         return err;
1564 }
1565
1566 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
1567 {
1568         int i;
1569
1570         regulator_disable(tegra->xusb_s1p05v_reg);
1571         regulator_disable(tegra->xusb_s1p8v_reg);
1572
1573         for (i = 0; i < XUSB_UTMI_COUNT; i++) {
1574                 if (BIT(XUSB_UTMI_INDEX + i) & tegra->bdata->portmap) {
1575                         struct regulator *reg = tegra->xusb_utmi_vbus_regs[i];
1576                         if (!IS_ERR_OR_NULL(reg))
1577                                 regulator_disable(reg);
1578                         tegra->xusb_utmi_vbus_regs[i] = NULL;
1579                 }
1580         }
1581
1582         regulator_disable(tegra->xusb_s3p3v_reg);
1583
1584         tegra->xusb_s1p05v_reg = NULL;
1585         tegra->xusb_s1p8v_reg = NULL;
1586         tegra->xusb_s3p3v_reg = NULL;
1587 }
1588
1589 /*
1590  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
1591  * are under hardware control
1592  */
1593 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
1594 {
1595         struct platform_device *pdev = tegra->pdev;
1596         int err = 0;
1597
1598         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
1599         if (IS_ERR(tegra->plle_clk)) {
1600                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
1601                 err = PTR_ERR(tegra->plle_clk);
1602                 return err;
1603         }
1604         err = clk_enable(tegra->plle_clk);
1605         if (err) {
1606                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
1607                         __func__);
1608                 return err;
1609         }
1610
1611         return err;
1612 }
1613
1614 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
1615 {
1616         clk_disable(tegra->plle_clk);
1617         tegra->plle_clk = NULL;
1618 }
1619
1620 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
1621 {
1622         struct platform_device *pdev = tegra->pdev;
1623         int err = 0;
1624
1625         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
1626         if (IS_ERR(tegra->emc_clk)) {
1627                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
1628                 return PTR_ERR(tegra->emc_clk);
1629         }
1630
1631         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1632                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
1633                 if (IS_ERR(tegra->pll_re_vco_clk)) {
1634                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
1635                         err = PTR_ERR(tegra->pll_re_vco_clk);
1636                         goto get_pll_re_vco_clk_failed;
1637                 }
1638         }
1639
1640         /* get the clock handle of 120MHz clock source */
1641         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
1642         if (IS_ERR(tegra->pll_u_480M)) {
1643                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
1644                 err = PTR_ERR(tegra->pll_u_480M);
1645                 goto get_pll_u_480M_failed;
1646         }
1647
1648         /* get the clock handle of 12MHz clock source */
1649         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1650         if (IS_ERR(tegra->clk_m)) {
1651                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
1652                 err = PTR_ERR(tegra->clk_m);
1653                 goto clk_get_clk_m_failed;
1654         }
1655
1656         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
1657         if (IS_ERR(tegra->ss_src_clk)) {
1658                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
1659                 err = PTR_ERR(tegra->ss_src_clk);
1660                 tegra->ss_src_clk = NULL;
1661                 goto get_ss_src_clk_failed;
1662         }
1663
1664         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
1665         if (IS_ERR(tegra->host_clk)) {
1666                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
1667                 err = PTR_ERR(tegra->host_clk);
1668                 tegra->host_clk = NULL;
1669                 goto get_host_clk_failed;
1670         }
1671
1672         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
1673         if (IS_ERR(tegra->ss_clk)) {
1674                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
1675                 err = PTR_ERR(tegra->ss_clk);
1676                 tegra->ss_clk = NULL;
1677                 goto get_ss_clk_failed;
1678         }
1679
1680         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1681                 err = clk_enable(tegra->pll_re_vco_clk);
1682                 if (err) {
1683                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
1684                         goto enable_pll_re_vco_clk_failed;
1685                 }
1686         }
1687         return 0;
1688
1689 enable_pll_re_vco_clk_failed:
1690         tegra->ss_clk = NULL;
1691
1692 get_ss_clk_failed:
1693         tegra->host_clk = NULL;
1694
1695 get_host_clk_failed:
1696         tegra->ss_src_clk = NULL;
1697
1698 get_ss_src_clk_failed:
1699         tegra->clk_m = NULL;
1700
1701 clk_get_clk_m_failed:
1702         tegra->pll_u_480M = NULL;
1703
1704 get_pll_u_480M_failed:
1705         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1706                 tegra->pll_re_vco_clk = NULL;
1707
1708 get_pll_re_vco_clk_failed:
1709         tegra->emc_clk = NULL;
1710
1711         return err;
1712 }
1713
1714 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
1715 {
1716         clk_disable(tegra->ss_clk);
1717         clk_disable(tegra->host_clk);
1718         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1719                 clk_disable(tegra->pll_re_vco_clk);
1720         tegra->ss_clk = NULL;
1721         tegra->host_clk = NULL;
1722         tegra->ss_src_clk = NULL;
1723         tegra->clk_m = NULL;
1724         tegra->pll_u_480M = NULL;
1725         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1726                 tegra->pll_re_vco_clk = NULL;
1727 }
1728
1729 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
1730         bool enable)
1731 {
1732         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1733         u32 reg;
1734
1735         /* Issue is only applicable for T114 */
1736         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
1737                 return;
1738
1739         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1740                 reg = readl(tegra->padctl_base +
1741                         padregs->iophy_misc_pad_p0_ctl3_0);
1742                 if (enable) {
1743                         reg &= ~RX_IDLE_MODE;
1744                         reg |= RX_IDLE_MODE_OVRD;
1745                 } else {
1746                         reg |= RX_IDLE_MODE;
1747                         reg &= ~RX_IDLE_MODE_OVRD;
1748                 }
1749                 writel(reg, tegra->padctl_base +
1750                         padregs->iophy_misc_pad_p0_ctl3_0);
1751         }
1752
1753         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1754                 reg = readl(tegra->padctl_base +
1755                         padregs->iophy_misc_pad_p1_ctl3_0);
1756                 if (enable) {
1757                         reg &= ~RX_IDLE_MODE;
1758                         reg |= RX_IDLE_MODE_OVRD;
1759                 } else {
1760                         reg |= RX_IDLE_MODE;
1761                         reg &= ~RX_IDLE_MODE_OVRD;
1762                 }
1763                 writel(reg, tegra->padctl_base +
1764                         padregs->iophy_misc_pad_p1_ctl3_0);
1765
1766                 /* SATA lane also if USB3_SS port1 mapped to it */
1767                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
1768                                 tegra->bdata->lane_owner & BIT(0)) {
1769                         reg = readl(tegra->padctl_base +
1770                                 padregs->iophy_misc_pad_s0_ctl3_0);
1771                         if (enable) {
1772                                 reg &= ~RX_IDLE_MODE;
1773                                 reg |= RX_IDLE_MODE_OVRD;
1774                         } else {
1775                                 reg |= RX_IDLE_MODE;
1776                                 reg &= ~RX_IDLE_MODE_OVRD;
1777                         }
1778                         writel(reg, tegra->padctl_base +
1779                                 padregs->iophy_misc_pad_s0_ctl3_0);
1780                 }
1781         }
1782 }
1783
1784 /* Enable ss clk, host clk, falcon clk,
1785  * fs clk, dev clk, plle and refplle
1786  */
1787
1788 static int
1789 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
1790                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
1791 {
1792         int ret = 0;
1793         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
1794         int fw_req_rate = rate, cur_rate;
1795
1796         /* Do not handle clock change as needed for HS disconnect issue */
1797         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1798                 *sw_resp = CMD_DATA(fw_req_rate) | CMD_TYPE(MBOX_CMD_ACK);
1799                 return ret;
1800         }
1801
1802         /* frequency request from firmware is in KHz.
1803          * Convert it to MHz
1804          */
1805
1806         /* get current rate of clock */
1807         cur_rate = clk_get_rate(clk_handle);
1808         cur_rate /= 1000;
1809
1810         if (fw_req_rate == cur_rate) {
1811                 cmd_ack = MBOX_CMD_ACK;
1812
1813         } else {
1814
1815                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
1816                         /* Change SS clock source to CLK_M at 12MHz */
1817                         clk_set_parent(clk_handle, tegra->clk_m);
1818                         clk_set_rate(clk_handle, fw_req_rate * 1000);
1819
1820                         /* save leakage power when SS freq is being decreased */
1821                         tegra_xhci_rx_idle_mode_override(tegra, true);
1822                 } else if (clk_handle == tegra->ss_src_clk &&
1823                                 fw_req_rate == 120000) {
1824                         /* Change SS clock source to HSIC_480 at 120MHz */
1825                         clk_set_rate(clk_handle,  3000 * 1000);
1826                         clk_set_parent(clk_handle, tegra->pll_u_480M);
1827
1828                         /* clear ovrd bits when SS freq is being increased */
1829                         tegra_xhci_rx_idle_mode_override(tegra, false);
1830                 }
1831
1832                 cur_rate = (clk_get_rate(clk_handle) / 1000);
1833
1834                 if (cur_rate != fw_req_rate) {
1835                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
1836                                 cur_rate, fw_req_rate);
1837                         cmd_ack = MBOX_CMD_NACK;
1838                 }
1839         }
1840         *sw_resp = CMD_DATA(cur_rate) | CMD_TYPE(cmd_ack);
1841         return ret;
1842 }
1843
1844 static void tegra_xusb_set_bw(struct tegra_xhci_hcd *tegra, unsigned int bw)
1845 {
1846         unsigned int freq_khz;
1847
1848         freq_khz = tegra_emc_bw_to_freq_req(bw);
1849         clk_set_rate(tegra->emc_clk, freq_khz * 1000);
1850 }
1851
1852 static void tegra_xhci_save_dfe_context(struct tegra_xhci_hcd *tegra,
1853         u8 port)
1854 {
1855         struct xhci_hcd *xhci = tegra->xhci;
1856         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1857         u32 offset;
1858         u32 reg;
1859
1860         if (port > (XUSB_SS_PORT_COUNT - 1)) {
1861                 pr_err("%s invalid SS port number %u\n", __func__, port);
1862                 return;
1863         }
1864
1865         xhci_info(xhci, "saving restore DFE context for port %d\n", port);
1866
1867         /* if port1 is mapped to SATA lane then read from SATA register */
1868         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1869                         tegra->bdata->lane_owner & BIT(0))
1870                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1871         else
1872                 offset = MISC_PAD_CTL_6_0(port);
1873
1874         /*
1875          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
1876          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
1877          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
1878          */
1879         reg = readl(tegra->padctl_base + offset);
1880         reg &= ~MISC_OUT_SEL(~0);
1881         reg |= MISC_OUT_SEL(0x32);
1882         writel(reg, tegra->padctl_base + offset);
1883
1884         reg = readl(tegra->padctl_base + offset);
1885         tegra->sregs.tap1_val[port] = MISC_OUT_TAP_VAL(reg);
1886
1887         reg = readl(tegra->padctl_base + offset);
1888         reg &= ~MISC_OUT_SEL(~0);
1889         reg |= MISC_OUT_SEL(0x33);
1890         writel(reg, tegra->padctl_base + offset);
1891
1892         reg = readl(tegra->padctl_base + offset);
1893         tegra->sregs.amp_val[port] = MISC_OUT_AMP_VAL(reg);
1894
1895         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1896         reg &= ~DFE_CNTL_TAP_VAL(~0);
1897         reg |= DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
1898         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1899
1900         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1901         reg &= ~DFE_CNTL_AMP_VAL(~0);
1902         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]);
1903         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1904
1905         tegra->dfe_ctx_saved[port] = true;
1906 }
1907
1908 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
1909         u8 port)
1910 {
1911         struct xhci_hcd *xhci = tegra->xhci;
1912         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1913         u32 offset;
1914         u32 reg;
1915
1916         if (port > (XUSB_SS_PORT_COUNT - 1)) {
1917                 pr_err("%s invalid SS port number %u\n", __func__, port);
1918                 return;
1919         }
1920
1921         xhci_info(xhci, "saving restore CTLE context for port %d\n", port);
1922
1923         /* if port1 is mapped to SATA lane then read from SATA register */
1924         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1925                         tegra->bdata->lane_owner & BIT(0))
1926                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1927         else
1928                 offset = MISC_PAD_CTL_6_0(port);
1929
1930         /*
1931          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
1932          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
1933          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
1934          */
1935         reg = readl(tegra->padctl_base + offset);
1936         reg &= ~MISC_OUT_SEL(~0);
1937         reg |= MISC_OUT_SEL(0xa1);
1938         writel(reg, tegra->padctl_base + offset);
1939
1940         reg = readl(tegra->padctl_base + offset);
1941         reg &= ~MISC_OUT_SEL(~0);
1942         reg |= MISC_OUT_SEL(0x21);
1943         writel(reg, tegra->padctl_base + offset);
1944
1945         reg = readl(tegra->padctl_base + offset);
1946         tegra->sregs.ctle_g_val[port] = MISC_OUT_G_Z_VAL(reg);
1947
1948         reg = readl(tegra->padctl_base + offset);
1949         reg &= ~MISC_OUT_SEL(~0);
1950         reg |= MISC_OUT_SEL(0x48);
1951         writel(reg, tegra->padctl_base + offset);
1952
1953         reg = readl(tegra->padctl_base + offset);
1954         tegra->sregs.ctle_z_val[port] = MISC_OUT_G_Z_VAL(reg);
1955
1956         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1957         reg &= ~RX_EQ_Z_VAL(~0);
1958         reg |= RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]);
1959         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1960
1961         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1962         reg &= ~RX_EQ_G_VAL(~0);
1963         reg |= RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]);
1964         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1965
1966         tegra->ctle_ctx_saved[port] = true;
1967 }
1968
1969 static void tegra_xhci_restore_dfe_context(struct tegra_xhci_hcd *tegra,
1970         u8 port)
1971 {
1972         struct xhci_hcd *xhci = tegra->xhci;
1973         u32 reg;
1974
1975         /* don't restore if not saved */
1976         if (tegra->dfe_ctx_saved[port] == false)
1977                 return;
1978
1979         xhci_info(xhci, "restoring dfe context of port %d\n", port);
1980
1981         /* restore dfe_cntl for the port */
1982         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1983         reg &= ~(DFE_CNTL_AMP_VAL(~0) |
1984                         DFE_CNTL_TAP_VAL(~0));
1985         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]) |
1986                 DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
1987         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1988 }
1989
1990 void restore_ctle_context(struct tegra_xhci_hcd *tegra,
1991         u8 port)
1992 {
1993         struct xhci_hcd *xhci = tegra->xhci;
1994         u32 reg;
1995
1996         /* don't restore if not saved */
1997         if (tegra->ctle_ctx_saved[port] == false)
1998                 return;
1999
2000         xhci_info(xhci, "restoring CTLE context of port %d\n", port);
2001
2002         /* restore ctle for the port */
2003         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
2004         reg &= ~(RX_EQ_Z_VAL(~0) |
2005                         RX_EQ_G_VAL(~0));
2006         reg |= (RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]) |
2007                 RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]));
2008         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
2009 }
2010
2011 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
2012         u8 port)
2013 {
2014         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2015         u32 reg;
2016
2017         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2018         reg &= ~USB2_ULPI_PAD;
2019         reg |= USB2_ULPI_PAD_OWNER_XUSB;
2020         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2021
2022         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
2023         reg &= ~USB2_ULPI_PORT_CAP;
2024         reg |= (tegra->bdata->ulpicap << 24);
2025         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
2026         /* FIXME: Program below when more details available
2027          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
2028          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
2029          */
2030 }
2031
2032 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
2033         u8 port)
2034 {
2035         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2036         u32 reg;
2037         u32 ctl0_offset, ctl1_offset;
2038
2039         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2040         reg &= ~USB2_OTG_PAD_PORT_MASK(port);
2041         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
2042         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2043
2044         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
2045         reg &= ~USB2_PORT_CAP_MASK(port);
2046         reg |= USB2_PORT_CAP_HOST(port);
2047         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
2048
2049         /*
2050          * Modify only the bits which belongs to the port
2051          * and enable respective VBUS_PAD for the port
2052          */
2053         if (tegra->bdata->uses_external_pmic == false) {
2054                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2055                 reg &= ~(port == 2 ? OC_DET_VBUS_ENABLE2_OC_MAP :
2056                         port ? OC_DET_VBUS_ENABLE1_OC_MAP :
2057                                 OC_DET_VBUS_ENABLE0_OC_MAP);
2058
2059                 reg |= (port == 2) ? OC_DET_VBUS_EN2_OC_DETECTED_VBUS_PAD2 :
2060                         port ? OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1 :
2061                                 OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0;
2062                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
2063         }
2064         /*
2065          * enable respective VBUS_PAD if port is mapped to any SS port
2066          */
2067         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
2068         reg &= ~((port == 2) ? USB2_OC_MAP_PORT2 :
2069                 port ? USB2_OC_MAP_PORT1 : USB2_OC_MAP_PORT0);
2070         reg |= (0x4 | port) << (port * 3);
2071         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
2072
2073         ctl0_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl0_0 :
2074                         port ? padregs->usb2_otg_pad1_ctl0_0 :
2075                                 padregs->usb2_otg_pad0_ctl0_0;
2076         ctl1_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl1_0 :
2077                         port ? padregs->usb2_otg_pad1_ctl1_0 :
2078                                 padregs->usb2_otg_pad0_ctl1_0;
2079
2080         reg = readl(tegra->padctl_base + ctl0_offset);
2081         reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
2082                 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
2083                 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
2084
2085         reg |= tegra->pdata->hs_slew;
2086         reg |= (port == 2) ? tegra->pdata->ls_rslew_pad2 :
2087                         port ? tegra->pdata->ls_rslew_pad1 :
2088                         tegra->pdata->ls_rslew_pad0;
2089         reg |= (port == 2) ? tegra->pdata->hs_curr_level_pad2 :
2090                         port ? tegra->pdata->hs_curr_level_pad1 :
2091                         tegra->pdata->hs_curr_level_pad0;
2092         writel(reg, tegra->padctl_base + ctl0_offset);
2093
2094         reg = readl(tegra->padctl_base + ctl1_offset);
2095         reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
2096                 | USB2_OTG_PD_CHRP_FORCE_POWERUP
2097                 | USB2_OTG_PD_DISC_FORCE_POWERUP
2098                 | USB2_OTG_PD_DR);
2099         reg |= (tegra->pdata->hs_iref_cap << 9) |
2100                 (tegra->pdata->hs_term_range_adj << 3);
2101         writel(reg, tegra->padctl_base + ctl1_offset);
2102
2103         /*Release OTG port if not in host mode*/
2104
2105         if ((port == 0) && !is_otg_host(tegra))
2106                 tegra_xhci_release_otg_port(true);
2107 }
2108
2109 static inline bool xusb_use_sata_lane(struct tegra_xhci_hcd *tegra)
2110 {
2111         return ((XUSB_DEVICE_ID_T114 == tegra->device_id) ? false
2112         : ((tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
2113                 && (tegra->bdata->lane_owner & BIT(0))));
2114 }
2115
2116 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
2117         u8 port)
2118 {
2119         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2120         u32 ctl2_offset, ctl4_offset, ctl5_offset;
2121         u32 reg;
2122
2123         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
2124                         padregs->iophy_usb3_pad0_ctl2_0;
2125         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
2126                         padregs->iophy_usb3_pad0_ctl4_0;
2127         ctl5_offset = port ? padregs->iophy_misc_pad_p1_ctl5_0 :
2128                         padregs->iophy_misc_pad_p0_ctl5_0;
2129
2130         reg = readl(tegra->padctl_base + ctl2_offset);
2131         reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
2132                 IOPHY_USB3_CDRCNTL);
2133         reg |= tegra->pdata->rx_wander | tegra->pdata->rx_eq |
2134                 tegra->pdata->cdr_cntl;
2135         writel(reg, tegra->padctl_base + ctl2_offset);
2136
2137         reg = readl(tegra->padctl_base + ctl4_offset);
2138         reg = tegra->pdata->dfe_cntl;
2139         writel(reg, tegra->padctl_base + ctl4_offset);
2140
2141         reg = readl(tegra->padctl_base + ctl5_offset);
2142         reg |= RX_QEYE_EN;
2143         writel(reg, tegra->padctl_base + ctl5_offset);
2144
2145         reg = readl(tegra->padctl_base + MISC_PAD_CTL_2_0(port));
2146         reg &= ~SPARE_IN(~0);
2147         reg |= SPARE_IN(tegra->pdata->spare_in);
2148         writel(reg, tegra->padctl_base + MISC_PAD_CTL_2_0(port));
2149
2150         if (xusb_use_sata_lane(tegra)) {
2151                 reg = readl(tegra->padctl_base + MISC_PAD_S0_CTL_5_0);
2152                 reg |= RX_QEYE_EN;
2153                 writel(reg, tegra->padctl_base + MISC_PAD_S0_CTL_5_0);
2154
2155                 reg = readl(tegra->padctl_base + MISC_PAD_S0_CTL_2_0);
2156                 reg &= ~SPARE_IN(~0);
2157                 reg |= SPARE_IN(tegra->pdata->spare_in);
2158                 writel(reg, tegra->padctl_base + MISC_PAD_S0_CTL_2_0);
2159         }
2160
2161         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
2162         reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
2163         reg |= (tegra->bdata->ss_portmap &
2164                 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
2165         writel(reg, tegra->padctl_base + padregs->ss_port_map_0);
2166
2167         tegra_xhci_restore_dfe_context(tegra, port);
2168         tegra_xhci_restore_ctle_context(tegra, port);
2169 }
2170
2171 /* This function assigns the USB ports to the controllers,
2172  * then programs the port capabilities and pad parameters
2173  * of ports assigned to XUSB after booted to OS.
2174  */
2175 void
2176 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
2177 {
2178         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2179         u32 reg, oc_bits = 0;
2180         unsigned pad;
2181
2182         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2183         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
2184         reg |= tegra->pdata->hs_squelch_level | tegra->pdata->hs_disc_lvl;
2185         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2186
2187         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
2188         reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3;
2189         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
2190         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
2191
2192         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2193         reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
2194         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2195                 reg |= OC_DET_VBUS_ENABLE2_OC_MAP;
2196         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2197
2198         /* check if over current seen. Clear if present */
2199         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2200                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2201         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2202                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2203         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2204                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2205
2206         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2207         if (reg & oc_bits) {
2208                 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
2209                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
2210
2211                 usleep_range(100, 200);
2212
2213                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2214                 if (reg & oc_bits)
2215                         xhci_info(tegra->xhci, "Over current still present\n");
2216         }
2217
2218         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
2219         reg = USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1;
2220         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2221                 reg |= USB2_OC_MAP_PORT2;
2222         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
2223
2224         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2225                 tegra_xhci_program_utmip_pad(tegra, 0);
2226         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2227                 tegra_xhci_program_utmip_pad(tegra, 1);
2228         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2229                 tegra_xhci_program_utmip_pad(tegra, 2);
2230
2231         for_each_enabled_hsic_pad(pad, tegra)
2232                 hsic_pad_enable(tegra, pad);
2233
2234         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
2235                 tegra_xhci_program_ulpi_pad(tegra, 0);
2236
2237         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
2238                 tegra_xhci_program_ss_pad(tegra, 0);
2239         } else {
2240                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
2241                 reg = readl(tegra->padctl_base +
2242                         padregs->iophy_misc_pad_p0_ctl3_0);
2243                 reg &= ~RX_IDLE_MODE;
2244                 reg |= RX_IDLE_MODE_OVRD;
2245                 writel(reg, tegra->padctl_base +
2246                         padregs->iophy_misc_pad_p0_ctl3_0);
2247         }
2248
2249         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
2250                 tegra_xhci_program_ss_pad(tegra, 1);
2251         } else {
2252                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
2253                 reg = readl(tegra->padctl_base +
2254                         padregs->iophy_misc_pad_p1_ctl3_0);
2255                 reg &= ~RX_IDLE_MODE;
2256                 reg |= RX_IDLE_MODE_OVRD;
2257                 writel(reg, tegra->padctl_base +
2258                         padregs->iophy_misc_pad_p1_ctl3_0);
2259
2260                 /* SATA lane also if USB3_SS port1 mapped to it but unused */
2261                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
2262                                 tegra->bdata->lane_owner & BIT(0)) {
2263                         reg = readl(tegra->padctl_base +
2264                                 padregs->iophy_misc_pad_s0_ctl3_0);
2265                         reg &= ~RX_IDLE_MODE;
2266                         reg |= RX_IDLE_MODE_OVRD;
2267                         writel(reg, tegra->padctl_base +
2268                                 padregs->iophy_misc_pad_s0_ctl3_0);
2269                 }
2270         }
2271         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2272                 tegra_xhci_setup_gpio_for_ss_lane(tegra);
2273                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
2274         }
2275 }
2276
2277 /* This function read XUSB registers and stores in device context */
2278 static void
2279 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
2280 {
2281
2282         /* a. Save the IPFS registers */
2283         tegra->sregs.msi_bar_sz =
2284                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2285
2286         tegra->sregs.msi_axi_barst =
2287                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2288
2289         tegra->sregs.msi_fpci_barst =
2290                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2291
2292         tegra->sregs.msi_vec0 =
2293                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2294
2295         tegra->sregs.msi_en_vec0 =
2296                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2297
2298         tegra->sregs.fpci_error_masks =
2299                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2300
2301         tegra->sregs.intr_mask =
2302                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2303
2304         tegra->sregs.ipfs_intr_enable =
2305                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2306
2307         tegra->sregs.ufpci_config =
2308                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2309
2310         tegra->sregs.clkgate_hysteresis =
2311                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2312
2313         tegra->sregs.xusb_host_mccif_fifo_cntrl =
2314                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2315
2316         /* b. Save the CFG registers */
2317
2318         tegra->sregs.hs_pls =
2319                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2320
2321         tegra->sregs.fs_pls =
2322                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2323
2324         tegra->sregs.hs_fs_speed =
2325                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2326
2327         tegra->sregs.hs_fs_pp =
2328                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2329
2330         tegra->sregs.cfg_aru =
2331                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2332
2333         tegra->sregs.cfg_order =
2334                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
2335
2336         tegra->sregs.cfg_fladj =
2337                 readl(tegra->fpci_base + XUSB_CFG_24);
2338
2339         tegra->sregs.cfg_sid =
2340                 readl(tegra->fpci_base + XUSB_CFG_16);
2341 }
2342
2343 /* This function restores XUSB registers from device context */
2344 static void
2345 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
2346 {
2347         /* Restore Cfg registers */
2348         writel(tegra->sregs.hs_pls,
2349                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2350
2351         writel(tegra->sregs.fs_pls,
2352                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2353
2354         writel(tegra->sregs.hs_fs_speed,
2355                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2356
2357         writel(tegra->sregs.hs_fs_pp,
2358                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2359
2360         writel(tegra->sregs.cfg_aru,
2361                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2362
2363         writel(tegra->sregs.cfg_order,
2364                 tegra->fpci_base + XUSB_CFG_FPCICFG);
2365
2366         writel(tegra->sregs.cfg_fladj,
2367                 tegra->fpci_base + XUSB_CFG_24);
2368
2369         writel(tegra->sregs.cfg_sid,
2370                 tegra->fpci_base + XUSB_CFG_16);
2371
2372         /* Restore IPFS registers */
2373
2374         writel(tegra->sregs.msi_bar_sz,
2375                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2376
2377         writel(tegra->sregs.msi_axi_barst,
2378                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2379
2380         writel(tegra->sregs.msi_fpci_barst,
2381                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2382
2383         writel(tegra->sregs.msi_vec0,
2384                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2385
2386         writel(tegra->sregs.msi_en_vec0,
2387                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2388
2389         writel(tegra->sregs.fpci_error_masks,
2390                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2391
2392         writel(tegra->sregs.intr_mask,
2393                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2394
2395         writel(tegra->sregs.ipfs_intr_enable,
2396                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2397
2398         writel(tegra->sregs.ufpci_config,
2399                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2400
2401         writel(tegra->sregs.clkgate_hysteresis,
2402                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2403
2404         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
2405                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2406 }
2407
2408 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
2409 {
2410         fw_message_send(tegra, MBOX_CMD_MSG_ENABLED, 0 /* no data needed */);
2411 }
2412
2413 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
2414 {
2415         struct platform_device *pdev = tegra->pdev;
2416         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
2417         u32 phys_addr_lo;
2418         u32 HwReg;
2419         u16 nblocks;
2420         time_t fw_time;
2421         struct tm fw_tm;
2422         u8 hc_caplength;
2423         u32 usbsts, count = 0xff;
2424         struct xhci_cap_regs __iomem *cap_regs;
2425         struct xhci_op_regs __iomem *op_regs;
2426
2427         /* enable mbox interrupt */
2428         writel(readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD) | MBOX_INT_EN,
2429                 tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2430
2431         /* First thing, reset the ARU. By the time we get to
2432          * loading boot code below, reset would be complete.
2433          * alternatively we can busy wait on rst pending bit.
2434          */
2435         /* Don't reset during ELPG/LP0 exit path */
2436         if (resetARU) {
2437                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
2438                 usleep_range(1000, 2000);
2439         }
2440
2441         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
2442                 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
2443                                 csb_read(tegra, XUSB_FALC_CPUCTL));
2444                 return 0;
2445         }
2446
2447         /* update the phys_log_buffer and total_entries here */
2448         cfg_tbl->phys_addr_log_buffer = tegra->log.phys_addr;
2449         cfg_tbl->total_log_entries = FW_LOG_COUNT;
2450
2451         phys_addr_lo = tegra->firmware.dma;
2452         phys_addr_lo += sizeof(struct cfgtbl);
2453
2454         /* Program the size of DFI into ILOAD_ATTR */
2455         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
2456
2457         /* Boot code of the firmware reads the ILOAD_BASE_LO register
2458          * to get to the start of the dfi in system memory.
2459          */
2460         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
2461
2462         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
2463         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
2464
2465         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
2466         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
2467
2468         /* Invalidate L2IMEM. */
2469         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
2470
2471         /* Initiate fetch of Bootcode from system memory into L2IMEM.
2472          * Program BootCode location and size in system memory.
2473          */
2474         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
2475                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
2476                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
2477         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
2478                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
2479                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
2480         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
2481
2482         /* Trigger L2IMEM Load operation. */
2483         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
2484
2485         /* Setup Falcon Auto-fill */
2486         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
2487         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
2488                 nblocks += 1;
2489         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
2490
2491         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
2492         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
2493                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
2494         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
2495
2496         csb_write(tegra, XUSB_FALC_DMACTL, 0);
2497         msleep(50);
2498
2499         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
2500
2501         /* Start Falcon CPU */
2502         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
2503         usleep_range(1000, 2000);
2504
2505         fw_time = cfg_tbl->fwimg_created_time;
2506         time_to_tm(fw_time, 0, &fw_tm);
2507         dev_info(&pdev->dev,
2508                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
2509                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
2510                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
2511                 fw_tm.tm_min, fw_tm.tm_sec,
2512                 csb_read(tegra, XUSB_FALC_CPUCTL));
2513
2514         dev_dbg(&pdev->dev, "num_hsic_port %d\n", cfg_tbl->num_hsic_port);
2515
2516         /* return fail if firmware status is not good */
2517         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
2518                 return -EFAULT;
2519
2520         cap_regs = IO_ADDRESS(tegra->host_phy_base);
2521         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
2522         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
2523
2524         /* wait for USBSTS_CNR to get set */
2525         do {
2526                 usbsts = ioread32(&op_regs->status);
2527         } while ((usbsts & STS_CNR) && count--);
2528
2529         if (!count && (usbsts & STS_CNR)) {
2530                 dev_err(&pdev->dev, "Controller not ready\n");
2531                 return -EFAULT;
2532         }
2533
2534         /* TODO move this into firmware to avoid race */
2535         writel(0x0, tegra->fpci_base + XUSB_CFG_ARU_C11PAGESEL0);
2536         writel(0x1000, tegra->fpci_base + XUSB_CFG_ARU_C11PAGESEL1);
2537         writel(0x10, tegra->fpci_base + XUSB_CFG_HSPX_CORE_HSICWRAP);
2538         reg_dump(&pdev->dev, tegra->fpci_base, XUSB_CFG_ARU_C11PAGESEL0);
2539         reg_dump(&pdev->dev, tegra->fpci_base, XUSB_CFG_ARU_C11PAGESEL1);
2540         reg_dump(&pdev->dev, tegra->fpci_base, XUSB_CFG_HSPX_CORE_HSICWRAP);
2541
2542         return 0;
2543 }
2544
2545 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
2546         bool release)
2547 {
2548         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2549         u32 reg;
2550
2551         /* Issue is only applicable for T114 */
2552         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
2553                 return;
2554
2555         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2556         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2557                         USB2_OTG_PAD_PORT_MASK(2));
2558
2559         if (!release) {
2560                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2561                         if (is_otg_host(tegra))
2562                                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2563                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2564                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2565                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2566                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2567         }
2568
2569         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2570 }
2571 /* SS ELPG Entry initiated by fw */
2572 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
2573 {
2574         struct xhci_hcd *xhci = tegra->xhci;
2575         u32 ret = 0;
2576
2577         must_have_sync_lock(tegra);
2578
2579         /* update maximum BW requirement to 0 */
2580         tegra_xusb_set_bw(tegra, 0);
2581
2582         /* This is SS partition ELPG entry
2583          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
2584          */
2585
2586         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
2587          * only if it is sw initiated one
2588          */
2589
2590         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
2591          * SuperSpeed partition ELPG entry via mailbox protocol
2592          */
2593
2594         /* STEP 2: xHCI PEP driver and XUSB device mode driver
2595          * enable the XUSB wakeup interrupts for the SuperSpeed
2596          * and USB2.0 ports assigned to host.Section 4.1 Step 3
2597          */
2598         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2599
2600         /* STEP 3: xHCI PEP driver initiates the signal sequence
2601          * to enable the XUSB SSwake detection logic for the
2602          * SuperSpeed ports assigned to host.Section 4.1 Step 4
2603          */
2604         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, true);
2605
2606         /* STEP 4: System Power Management driver asserts reset
2607          * to XUSB SuperSpeed partition then disables its clocks
2608          */
2609         tegra_periph_reset_assert(tegra->ss_clk);
2610         clk_disable(tegra->ss_clk);
2611
2612         usleep_range(100, 200);
2613
2614         /* STEP 5: System Power Management driver disables the
2615          * XUSB SuperSpeed partition power rails.
2616          */
2617         debug_print_portsc(xhci);
2618
2619         /* tegra_powergate_partition also does partition reset assert */
2620         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
2621         if (ret) {
2622                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
2623                                 __func__);
2624                 /* TODO: error recovery? */
2625         }
2626         tegra->ss_pwr_gated = true;
2627
2628         /* STEP 6: xHCI PEP driver initiates the signal sequence
2629          * to enable the XUSB SSwake detection logic for the
2630          * SuperSpeed ports assigned to host.Section 4.1 Step 7
2631          */
2632         tegra_xhci_ss_vcore(tegra->bdata->portmap, true);
2633
2634         return ret;
2635 }
2636
2637 /* Host ELPG Entry */
2638 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
2639 {
2640         struct xhci_hcd *xhci = tegra->xhci;
2641         u32 ret;
2642
2643         must_have_sync_lock(tegra);
2644
2645         /* If ss is already powergated skip ss ctx save stuff */
2646         if (tegra->ss_pwr_gated) {
2647                 xhci_info(xhci, "%s: SS partition is already powergated\n",
2648                         __func__);
2649         } else {
2650                 ret = tegra_xhci_ss_elpg_entry(tegra);
2651                 if (ret) {
2652                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
2653                                 __func__, ret);
2654                         return ret;
2655                 }
2656         }
2657
2658         /* 1. IS INTR PENDING INT_PENDING=1 ? */
2659
2660         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
2661         tegra_xhci_save_xusb_ctx(tegra);
2662
2663         /* calculate rctrl_val and tctrl_val */
2664         tegra_xhci_war_for_tctrl_rctrl(tegra);
2665
2666         pmc_setup_wake_detect(tegra);
2667
2668         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2669         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2670                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2671
2672         /* tegra_powergate_partition also does partition reset assert */
2673         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
2674         if (ret) {
2675                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2676                         __func__, ret);
2677                 /* TODO: error handling? */
2678                 return ret;
2679         }
2680         tegra->host_pwr_gated = true;
2681         clk_disable(tegra->host_clk);
2682
2683         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2684                 clk_disable(tegra->pll_re_vco_clk);
2685         clk_disable(tegra->emc_clk);
2686         /* set port ownership to SNPS */
2687         tegra_xhci_release_port_ownership(tegra, true);
2688
2689         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2690                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2691
2692         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
2693         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
2694                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
2695         return ret;
2696 }
2697
2698 /* SS ELPG Exit triggered by PADCTL irq */
2699 /**
2700  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
2701  *
2702  * This function must be called with tegra->sync_lock acquired.
2703  *
2704  * @tegra: xhci controller context
2705  * @return 0 for success, or error numbers
2706  */
2707 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2708 {
2709         struct xhci_hcd *xhci = tegra->xhci;
2710         int ret = 0;
2711
2712         must_have_sync_lock(tegra);
2713
2714         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
2715                         tegra->hs_wake_event || tegra->host_resume_req)) {
2716
2717                 /*
2718                  * PWR_UNGATE SS partition. XUSBA
2719                  * tegra_unpowergate_partition also does partition reset
2720                  * deassert
2721                  */
2722                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
2723                 if (ret) {
2724                         xhci_err(xhci,
2725                         "%s: could not unpowergate xusba partition %d\n",
2726                         __func__, ret);
2727                         goto out;
2728                 }
2729                 if (tegra->ss_wake_event)
2730                         tegra->ss_wake_event = false;
2731
2732         } else {
2733                 xhci_info(xhci, "%s: ss already power gated\n",
2734                         __func__);
2735                 return ret;
2736         }
2737
2738         /* Step 3: Enable clock to ss partition */
2739         clk_enable(tegra->ss_clk);
2740
2741         /* Step 4: Disable ss wake detection logic */
2742         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2743
2744         /* Step 4.1: Disable ss wake detection logic */
2745         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
2746
2747         /* wait 150us */
2748         usleep_range(150, 200);
2749
2750         /* Step 4.2: Disable ss wake detection logic */
2751         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
2752
2753         /* Step 6 Deassert reset for ss clks */
2754         tegra_periph_reset_deassert(tegra->ss_clk);
2755
2756         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
2757         tegra->ss_pwr_gated = false;
2758 out:
2759         return ret;
2760 }
2761
2762 static void ss_partition_elpg_exit_work(struct work_struct *work)
2763 {
2764         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2765                 ss_elpg_exit_work);
2766
2767         mutex_lock(&tegra->sync_lock);
2768         tegra_xhci_ss_partition_elpg_exit(tegra);
2769         mutex_unlock(&tegra->sync_lock);
2770 }
2771
2772 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
2773 static void update_remote_wakeup_ports(struct tegra_xhci_hcd *tegra)
2774 {
2775         struct xhci_hcd *xhci = tegra->xhci;
2776         u32 wake2_status;
2777         int port;
2778
2779 #define PMC_WAKE2_STATUS        0x168
2780 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
2781
2782         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
2783
2784         if (wake2_status & PADCTL_WAKE) {
2785                 /* FIXME: This is customized for Dalmore, find a generic way */
2786                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
2787                 /* clear wake status */
2788                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
2789         }
2790
2791         /* set all usb2 ports with RESUME link state as wakup ports  */
2792         for (port = 0; port < xhci->num_usb2_ports; port++) {
2793                 u32 portsc = xhci_readl(xhci, xhci->usb2_ports[port]);
2794                 if ((portsc & PORT_PLS_MASK) == XDEV_RESUME)
2795                         set_bit(port, &tegra->usb2_rh_remote_wakeup_ports);
2796         }
2797
2798         xhci_dbg(xhci, "%s: usb2 roothub remote_wakeup_ports 0x%lx\n",
2799                         __func__, tegra->usb2_rh_remote_wakeup_ports);
2800         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
2801                         __func__, tegra->usb3_rh_remote_wakeup_ports);
2802 }
2803
2804 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
2805 {
2806         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2807         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2808         int port, num_ports;
2809         unsigned long *remote_wakeup_ports;
2810         u32 portsc;
2811         __le32 __iomem  **port_array;
2812         unsigned char *rh;
2813         unsigned int retry = 64;
2814         struct xhci_bus_state *bus_state;
2815
2816         bus_state = &xhci->bus_state[hcd_index(hcd)];
2817
2818         if (hcd == xhci->shared_hcd) {
2819                 port_array = xhci->usb3_ports;
2820                 num_ports = xhci->num_usb3_ports;
2821                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
2822                 rh = "usb3 roothub";
2823         } else {
2824                 port_array = xhci->usb2_ports;
2825                 num_ports = xhci->num_usb2_ports;
2826                 remote_wakeup_ports = &tegra->usb2_rh_remote_wakeup_ports;
2827                 rh = "usb2 roothub";
2828         }
2829
2830         while (*remote_wakeup_ports && retry--) {
2831                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
2832                         bool can_continue;
2833
2834                         portsc = xhci_readl(xhci, port_array[port]);
2835
2836                         if (!(portsc & PORT_CONNECT)) {
2837                                 /* nothing to do if already disconnected */
2838                                 clear_bit(port, remote_wakeup_ports);
2839                                 continue;
2840                         }
2841
2842                         if (hcd == xhci->shared_hcd) {
2843                                 can_continue =
2844                                         (portsc & PORT_PLS_MASK) == XDEV_U0;
2845                         } else {
2846                                 unsigned long flags;
2847
2848                                 spin_lock_irqsave(&xhci->lock, flags);
2849                                 can_continue =
2850                                 test_bit(port, &bus_state->resuming_ports);
2851                                 spin_unlock_irqrestore(&xhci->lock, flags);
2852                         }
2853
2854                         if (can_continue)
2855                                 clear_bit(port, remote_wakeup_ports);
2856                         else
2857                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
2858                                         __func__, rh, port, portsc);
2859                 }
2860
2861                 if (*remote_wakeup_ports)
2862                         msleep(20); /* give some time, irq will direct U0 */
2863         }
2864
2865         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
2866                         *remote_wakeup_ports);
2867 }
2868
2869 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
2870 {
2871         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2872         u32 reg, utmip_rctrl_val, utmip_tctrl_val, pad_mux, portmux, portowner;
2873         int port;
2874
2875         portmux = USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1);
2876         portowner = USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
2877                         USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2878
2879         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2880                 portmux |= USB2_OTG_PAD_PORT_MASK(2);
2881                 portowner |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2882         }
2883
2884         /* Use xusb padctl space only when xusb owns all UTMIP port */
2885         pad_mux = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2886         if ((pad_mux & portmux) == portowner) {
2887                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
2888                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
2889                  */
2890                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2891                 reg &= ~((1 << 12) | (1 << 13));
2892                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2893
2894                 /* wait 20us */
2895                 usleep_range(20, 30);
2896
2897                 /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
2898                  * :: TCTRL and RCTRL
2899                  */
2900                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl1_0);
2901                 utmip_rctrl_val = RCTRL(reg);
2902                 utmip_tctrl_val = TCTRL(reg);
2903
2904                 /*
2905                  * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
2906                  * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
2907                  */
2908                 utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
2909                 utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
2910                 utmi_phy_update_trking_data(utmip_tctrl_val, utmip_rctrl_val);
2911                 xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
2912                                         utmip_rctrl_val, utmip_tctrl_val);
2913
2914                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
2915                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
2916                  */
2917                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2918                 reg |= (1 << 13);
2919                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2920
2921                 /* Program these values into PMC regiseter and program the
2922                  * PMC override.
2923                  */
2924                 reg = PMC_TCTRL_VAL(utmip_tctrl_val) |
2925                                 PMC_RCTRL_VAL(utmip_rctrl_val);
2926                 tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG,
2927                                         0xffffffff, reg);
2928                 reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
2929                 tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
2930         } else {
2931                 /* Use common PMC API to use SNPS register space */
2932                 utmi_phy_set_snps_trking_data();
2933         }
2934 }
2935
2936 /* Host ELPG Exit triggered by PADCTL irq */
2937 /**
2938  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
2939  *
2940  * This function must be called with tegra->sync_lock acquired.
2941  *
2942  * @tegra: xhci controller context
2943  * @return 0 for success, or error numbers
2944  */
2945 static int
2946 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2947 {
2948         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2949         struct xhci_hcd *xhci = tegra->xhci;
2950         int ret = 0;
2951
2952         must_have_sync_lock(tegra);
2953
2954         if (!tegra->hc_in_elpg)
2955                 return 0;
2956
2957         clk_enable(tegra->emc_clk);
2958         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2959                 clk_enable(tegra->pll_re_vco_clk);
2960
2961         if (tegra->lp0_exit) {
2962                 u32 reg, oc_bits = 0;
2963
2964                 /* Issue is only applicable for T114 */
2965                 if (XUSB_DEVICE_ID_T114 == tegra->device_id)
2966                         tegra_xhci_war_for_tctrl_rctrl(tegra);
2967                 /* check if over current seen. Clear if present */
2968                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2969                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2970                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2971                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2972                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2973                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2974
2975                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2976                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
2977                 if (reg & oc_bits) {
2978                         xhci_info(xhci, "Over current detected. Clearing...\n");
2979                         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2980
2981                         usleep_range(100, 200);
2982
2983                         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2984                         if (reg & oc_bits)
2985                                 xhci_info(xhci, "Over current still present\n");
2986                 }
2987                 tegra_xhci_padctl_portmap_and_caps(tegra);
2988                 /* release clamps post deassert */
2989                 tegra->lp0_exit = false;
2990         }
2991
2992         /* Clear FLUSH_ENABLE of MC client */
2993         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
2994
2995         /* set port ownership back to xusb */
2996         tegra_xhci_release_port_ownership(tegra, false);
2997
2998         /*
2999          * PWR_UNGATE Host partition. XUSBC
3000          * tegra_unpowergate_partition also does partition reset deassert
3001          */
3002         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3003         if (ret) {
3004                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
3005                         __func__, ret);
3006                 goto out;
3007         }
3008         clk_enable(tegra->host_clk);
3009
3010         /* Step 4: Deassert reset to host partition clk */
3011         tegra_periph_reset_deassert(tegra->host_clk);
3012
3013         /* Step 6.1: IPFS and XUSB BAR initialization */
3014         tegra_xhci_cfg(tegra);
3015
3016         /* Step 6.2: IPFS and XUSB related restore */
3017         tegra_xhci_restore_ctx(tegra);
3018
3019         /* Step 8: xhci spec related ctx restore
3020          * will be done in xhci_resume().Do it here.
3021          */
3022
3023         tegra_xhci_ss_partition_elpg_exit(tegra);
3024
3025         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
3026         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
3027                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
3028                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
3029         }
3030
3031         /* clear ovrd bits */
3032         tegra_xhci_rx_idle_mode_override(tegra, false);
3033
3034         /* Load firmware */
3035         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
3036                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
3037                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
3038                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
3039                         __func__,
3040                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
3041                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
3042                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
3043                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
3044                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
3045                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
3046                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
3047                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
3048                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
3049         debug_print_portsc(xhci);
3050
3051         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
3052         if (ret < 0) {
3053                 xhci_err(xhci, "%s: failed to load firmware %d\n",
3054                         __func__, ret);
3055                 goto out;
3056         }
3057
3058         pmc_disable_bus_ctrl(tegra);
3059
3060         tegra->hc_in_elpg = false;
3061         ret = xhci_resume(tegra->xhci, 0);
3062         if (ret) {
3063                 xhci_err(xhci, "%s: could not resume right %d\n",
3064                                 __func__, ret);
3065                 goto out;
3066         }
3067
3068         update_remote_wakeup_ports(tegra);
3069
3070         if (tegra->hs_wake_event)
3071                 tegra->hs_wake_event = false;
3072
3073         if (tegra->host_resume_req)
3074                 tegra->host_resume_req = false;
3075
3076         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
3077                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
3078
3079         tegra->host_pwr_gated = false;
3080 out:
3081         return ret;
3082 }
3083
3084 static void host_partition_elpg_exit_work(struct work_struct *work)
3085 {
3086         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3087                 host_elpg_exit_work);
3088
3089         mutex_lock(&tegra->sync_lock);
3090         tegra_xhci_host_partition_elpg_exit(tegra);
3091         mutex_unlock(&tegra->sync_lock);
3092 }
3093
3094 /* Mailbox handling function. This function handles requests
3095  * from firmware and communicates with clock and powergating
3096  * module to alter clock rates and to power gate/ungate xusb
3097  * partitions.
3098  *
3099  * Following is the structure of mailbox messages.
3100  * bit 31:28 - msg type
3101  * bits 27:0 - mbox data
3102  * FIXME:  Check if we can just call clock functions like below
3103  * or should we schedule it for calling later ?
3104  */
3105
3106 static void
3107 tegra_xhci_process_mbox_message(struct work_struct *work)
3108 {
3109         u32 sw_resp = 0, cmd, data_in, fw_msg;
3110         int ret = 0;
3111         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3112                                         mbox_work);
3113         struct xhci_hcd *xhci = tegra->xhci;
3114         int pad, port;
3115         unsigned long ports;
3116
3117         mutex_lock(&tegra->mbox_lock);
3118
3119         /* get the mbox message from firmware */
3120         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
3121
3122         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3123         if (data_in) {
3124                 dev_warn(&tegra->pdev->dev, "%s data_in 0x%x\n",
3125                         __func__, data_in);
3126                 mutex_unlock(&tegra->mbox_lock);
3127                 return;
3128         }
3129
3130         /* get cmd type and cmd data */
3131         tegra->cmd_type = (fw_msg >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
3132         tegra->cmd_data = (fw_msg >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
3133
3134         /* decode the message and make appropriate requests to
3135          * clock or powergating module.
3136          */
3137
3138         switch (tegra->cmd_type) {
3139         case MBOX_CMD_INC_FALC_CLOCK:
3140         case MBOX_CMD_DEC_FALC_CLOCK:
3141                 ret = tegra_xusb_request_clk_rate(
3142                                 tegra,
3143                                 tegra->falc_clk,
3144                                 tegra->cmd_data,
3145                                 &sw_resp);
3146                 if (ret)
3147                         xhci_err(xhci, "%s: could not set required falc rate\n",
3148                                 __func__);
3149                 goto send_sw_response;
3150         case MBOX_CMD_INC_SSPI_CLOCK:
3151         case MBOX_CMD_DEC_SSPI_CLOCK:
3152                 ret = tegra_xusb_request_clk_rate(
3153                                 tegra,
3154                                 tegra->ss_src_clk,
3155                                 tegra->cmd_data,
3156                                 &sw_resp);
3157                 if (ret)
3158                         xhci_err(xhci, "%s: could not set required ss rate.\n",
3159                                 __func__);
3160                 goto send_sw_response;
3161
3162         case MBOX_CMD_SET_BW:
3163                 /* fw sends BW request in MByte/sec */
3164                 mutex_lock(&tegra->sync_lock);
3165                 tegra_xusb_set_bw(tegra, tegra->cmd_data << 10);
3166                 mutex_unlock(&tegra->sync_lock);
3167                 break;
3168
3169         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
3170                 tegra_xhci_save_dfe_context(tegra, tegra->cmd_data);
3171                 tegra_xhci_save_ctle_context(tegra, tegra->cmd_data);
3172                 sw_resp = CMD_DATA(tegra->cmd_data) | CMD_TYPE(MBOX_CMD_ACK);
3173                 goto send_sw_response;
3174
3175         case MBOX_CMD_STAR_HSIC_IDLE:
3176                 ports = tegra->cmd_data;
3177                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3178                         pad = port_to_hsic_pad(port - 1);
3179                         mutex_lock(&tegra->sync_lock);
3180                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
3181                         mutex_unlock(&tegra->sync_lock);
3182                         if (ret)
3183                                 break;
3184                 }
3185
3186                 sw_resp = CMD_DATA(tegra->cmd_data);
3187                 if (!ret)
3188                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3189                 else
3190                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3191
3192                 goto send_sw_response;
3193
3194         case MBOX_CMD_STOP_HSIC_IDLE:
3195                 ports = tegra->cmd_data;
3196                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3197                         pad = port_to_hsic_pad(port - 1);
3198                         mutex_lock(&tegra->sync_lock);
3199                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_DISABLE);
3200                         mutex_unlock(&tegra->sync_lock);
3201                         if (ret)
3202                                 break;
3203                 }
3204
3205                 sw_resp = CMD_DATA(tegra->cmd_data);
3206                 if (!ret)
3207                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3208                 else
3209                         sw_resp |= CMD_TYPE(MBOX_CMD_NACK);
3210                 goto send_sw_response;
3211
3212         case MBOX_CMD_ACK:
3213                 xhci_dbg(xhci, "%s firmware responds with ACK\n", __func__);
3214                 break;
3215         case MBOX_CMD_NACK:
3216                 xhci_warn(xhci, "%s firmware responds with NACK\n", __func__);
3217                 break;
3218         default:
3219                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
3220                                 __func__, tegra->cmd_type);
3221         }
3222
3223         /* clear MBOX_SMI_INT_EN bit */
3224         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3225         cmd &= ~MBOX_SMI_INT_EN;
3226         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3227
3228         /* clear mailbox ownership */
3229         writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
3230
3231         mutex_unlock(&tegra->mbox_lock);
3232         return;
3233
3234 send_sw_response:
3235         if (((sw_resp >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK) == MBOX_CMD_NACK)
3236                 xhci_err(xhci, "%s respond fw message 0x%x with NAK\n",
3237                                 __func__, fw_msg);
3238
3239         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3240         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3241         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
3242         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3243
3244         mutex_unlock(&tegra->mbox_lock);
3245 }
3246
3247 static irqreturn_t pmc_usb_phy_wake_isr(int irq, void *data)
3248 {
3249         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) data;
3250         struct xhci_hcd *xhci = tegra->xhci;
3251
3252         xhci_dbg(xhci, "%s irq %d", __func__, irq);
3253         return IRQ_HANDLED;
3254 }
3255
3256 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
3257 {
3258         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3259         struct xhci_hcd *xhci = tegra->xhci;
3260         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3261         u32 elpg_program0 = 0;
3262
3263         spin_lock(&tegra->lock);
3264
3265         tegra->last_jiffies = jiffies;
3266
3267         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
3268         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
3269
3270         /* Clear the interrupt cause. We already read the intr status. */
3271         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3272         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3273
3274         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
3275         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
3276                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
3277         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
3278                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
3279         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
3280                 __func__,
3281                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad0_ctl0_0));
3282         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
3283                 __func__,
3284                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad1_ctl0_0));
3285         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
3286                 __func__,
3287                 readl(tegra->padctl_base + padregs->usb2_bchrg_bias_pad_0));
3288
3289         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
3290                 tegra->ss_wake_event = true;
3291         else if (elpg_program0 & (USB2_PORT0_WAKEUP_EVENT |
3292                         USB2_PORT1_WAKEUP_EVENT |
3293                         USB2_PORT2_WAKEUP_EVENT |
3294                         USB2_HSIC_PORT0_WAKEUP_EVENT |
3295                         USB2_HSIC_PORT1_WAKEUP_EVENT))
3296                 tegra->hs_wake_event = true;
3297
3298         if (tegra->ss_wake_event || tegra->hs_wake_event) {
3299                 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
3300                         xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
3301                         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3302                 } else if (tegra->ss_pwr_gated
3303                                 && tegra->host_pwr_gated) {
3304                         xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
3305                                 __func__);
3306                         schedule_work(&tegra->host_elpg_exit_work);
3307                 }
3308         } else {
3309                 xhci_err(xhci, "error: wake due to no hs/ss event\n");
3310                 tegra_usb_pad_reg_write(padregs->elpg_program_0, 0xffffffff);
3311         }
3312         spin_unlock(&tegra->lock);
3313         return IRQ_HANDLED;
3314 }
3315
3316 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
3317 {
3318         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3319         u32 temp;
3320
3321         spin_lock(&tegra->lock);
3322
3323         /* clear the mbox intr status 1st thing. Other
3324          * bits are W1C bits, so just write to SMI bit.
3325          */
3326
3327         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3328
3329         /* write 1 to clear SMI INTR en bit ( bit 3 ) */
3330         temp = MBOX_SMI_INTR_EN;
3331         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3332
3333         schedule_work(&tegra->mbox_work);
3334
3335         spin_unlock(&tegra->lock);
3336         return IRQ_HANDLED;
3337 }
3338
3339 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
3340 {
3341         /*
3342          * As of now platform drivers don't provide MSI support so we ensure
3343          * here that the generic code does not try to make a pci_dev from our
3344          * dev struct in order to setup MSI
3345          */
3346         xhci->quirks |= XHCI_BROKEN_MSI;
3347         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
3348 }
3349
3350 /* called during probe() after chip reset completes */
3351 static int xhci_plat_setup(struct usb_hcd *hcd)
3352 {
3353         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
3354 }
3355
3356 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
3357         const char *name, void __iomem **region)
3358 {
3359         struct resource *res;
3360         void __iomem *mem;
3361
3362         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
3363         if (!res) {
3364                 dev_err(&pdev->dev, "memory resource %s doesn't exist\n", name);
3365                 return -ENODEV;
3366         }
3367
3368         mem = devm_request_and_ioremap(&pdev->dev, res);
3369         if (!mem) {
3370                 dev_err(&pdev->dev, "failed to ioremap for %s\n", name);
3371                 return -EFAULT;
3372         }
3373         *region = mem;
3374
3375         return 0;
3376 }
3377
3378 static int tegra_xhci_request_irq(struct platform_device *pdev,
3379         const char *rscname, irq_handler_t handler, unsigned long irqflags,
3380         const char *devname, int *irq_no)
3381 {
3382         int ret;
3383         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3384         struct resource *res;
3385
3386         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, rscname);
3387         if (!res) {
3388                 dev_err(&pdev->dev, "irq resource %s doesn't exist\n", rscname);
3389                 return -ENODEV;
3390         }
3391
3392         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
3393                         devname, tegra);
3394         if (ret != 0) {
3395                 dev_err(&pdev->dev,
3396                         "failed to request_irq for %s (irq %d), error = %d\n",
3397                         devname, res->start, ret);
3398                 return ret;
3399         }
3400         *irq_no = res->start;
3401
3402         return 0;
3403 }
3404
3405 #ifdef CONFIG_PM
3406
3407 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
3408 {
3409         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3410         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3411         int err = 0;
3412         unsigned long flags;
3413
3414         mutex_lock(&tegra->sync_lock);
3415
3416         if (xhci->shared_hcd == hcd) {
3417                 tegra->usb3_rh_suspend = true;
3418                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3419         } else if (xhci->main_hcd == hcd) {
3420                 tegra->usb2_rh_suspend = true;
3421                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3422         }
3423
3424         WARN_ON(tegra->hc_in_elpg);
3425
3426         /* suspend xhci bus. This will also set remote mask */
3427         err = xhci_bus_suspend(hcd);
3428         if (err) {
3429                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
3430                                 __func__, err);
3431                 goto xhci_bus_suspend_failed;
3432         }
3433
3434         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
3435                 goto done; /* one of the root hubs is still working */
3436
3437         spin_lock_irqsave(&tegra->lock, flags);
3438         tegra->hc_in_elpg = true;
3439         spin_unlock_irqrestore(&tegra->lock, flags);
3440
3441         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3442
3443         /* save xhci spec ctx. Already done by xhci_suspend */
3444         err = xhci_suspend(tegra->xhci);
3445         if (err) {
3446                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
3447                 goto xhci_suspend_failed;
3448         }
3449
3450         /* Powergate host. Include ss power gate if not already done */
3451         err = tegra_xhci_host_elpg_entry(tegra);
3452         if (err) {
3453                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
3454                                 __func__, err);
3455                 goto tegra_xhci_host_elpg_entry_failed;
3456         }
3457
3458         /* At this point,ensure ss/hs intr enables are always on */
3459         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
3460         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
3461
3462         /* In ELPG, firmware log context is gone. Rewind shared log buffer. */
3463         if (fw_log_wait_empty_timeout(tegra, 100))
3464                 xhci_warn(xhci, "%s still has logs\n", __func__);
3465         tegra->log.dequeue = tegra->log.virt_addr;
3466         tegra->log.seq = 0;
3467
3468 done:
3469         /* pads are disabled only if usb2 root hub in xusb is idle */
3470         /* pads will actually be disabled only when all usb2 ports are idle */
3471         if (xhci->main_hcd == hcd) {
3472                 utmi_phy_pad_disable();
3473                 utmi_phy_iddq_override(true);
3474         }
3475         mutex_unlock(&tegra->sync_lock);
3476         return 0;
3477
3478 tegra_xhci_host_elpg_entry_failed:
3479
3480 xhci_suspend_failed:
3481         tegra->hc_in_elpg = false;
3482 xhci_bus_suspend_failed:
3483         if (xhci->shared_hcd == hcd)
3484                 tegra->usb3_rh_suspend = false;
3485         else if (xhci->main_hcd == hcd)
3486                 tegra->usb2_rh_suspend = false;
3487
3488         mutex_unlock(&tegra->sync_lock);
3489         return err;
3490 }
3491
3492 /* First, USB2HCD and then USB3HCD resume will be called */
3493 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
3494 {
3495         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3496         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3497         int err = 0;
3498
3499         mutex_lock(&tegra->sync_lock);
3500
3501         tegra->host_resume_req = true;
3502
3503         if (xhci->shared_hcd == hcd)
3504                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3505         else if (xhci->main_hcd == hcd)
3506                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3507
3508         /* pads are disabled only if usb2 root hub in xusb is idle */
3509         /* pads will actually be disabled only when all usb2 ports are idle */
3510         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
3511                 utmi_phy_pad_enable();
3512                 utmi_phy_iddq_override(false);
3513         }
3514         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
3515                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
3516                         tegra_xhci_host_partition_elpg_exit(tegra);
3517         }
3518
3519          /* handle remote wakeup before resuming bus */
3520         wait_remote_wakeup_ports(hcd);
3521
3522         err = xhci_bus_resume(hcd);
3523         if (err) {
3524                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
3525                                 __func__, err);
3526                 goto xhci_bus_resume_failed;
3527         }
3528
3529         if (xhci->shared_hcd == hcd)
3530                 tegra->usb3_rh_suspend = false;
3531         else if (xhci->main_hcd == hcd)
3532                 tegra->usb2_rh_suspend = false;
3533
3534         mutex_unlock(&tegra->sync_lock);
3535         return 0;
3536
3537 xhci_bus_resume_failed:
3538         /* TODO: reverse elpg? */
3539         mutex_unlock(&tegra->sync_lock);
3540         return err;
3541 }
3542 #endif
3543
3544 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
3545 {
3546         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3547         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3548         irqreturn_t iret = IRQ_HANDLED;
3549         u32 status;
3550
3551         spin_lock(&tegra->lock);
3552         if (tegra->hc_in_elpg) {
3553                 spin_lock(&xhci->lock);
3554                 if (HCD_HW_ACCESSIBLE(hcd)) {
3555                         status = xhci_readl(xhci, &xhci->op_regs->status);
3556                         status |= STS_EINT;
3557                         xhci_writel(xhci, status, &xhci->op_regs->status);
3558                 }
3559                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
3560                                 __func__);
3561                 schedule_work(&tegra->host_elpg_exit_work);
3562                 spin_unlock(&xhci->lock);
3563         } else
3564                 iret = xhci_irq(hcd);
3565         spin_unlock(&tegra->lock);
3566
3567         wake_up_interruptible(&tegra->log.intr_wait);
3568
3569         return iret;
3570 }
3571
3572
3573 static const struct hc_driver tegra_plat_xhci_driver = {
3574         .description =          "tegra-xhci",
3575         .product_desc =         "Nvidia xHCI Host Controller",
3576         .hcd_priv_size =        sizeof(struct xhci_hcd *),
3577
3578         /*
3579          * generic hardware linkage
3580          */
3581         .irq =                  tegra_xhci_irq,
3582         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
3583
3584         /*
3585          * basic lifecycle operations
3586          */
3587         .reset =                xhci_plat_setup,
3588         .start =                xhci_run,
3589         .stop =                 xhci_stop,
3590         .shutdown =             xhci_shutdown,
3591
3592         /*
3593          * managing i/o requests and associated device resources
3594          */
3595         .urb_enqueue =          xhci_urb_enqueue,
3596         .urb_dequeue =          xhci_urb_dequeue,
3597         .alloc_dev =            xhci_alloc_dev,
3598         .free_dev =             xhci_free_dev,
3599         .alloc_streams =        xhci_alloc_streams,
3600         .free_streams =         xhci_free_streams,
3601         .add_endpoint =         xhci_add_endpoint,
3602         .drop_endpoint =        xhci_drop_endpoint,
3603         .endpoint_reset =       xhci_endpoint_reset,
3604         .check_bandwidth =      xhci_check_bandwidth,
3605         .reset_bandwidth =      xhci_reset_bandwidth,
3606         .address_device =       xhci_address_device,
3607         .update_hub_device =    xhci_update_hub_device,
3608         .reset_device =         xhci_discover_or_reset_device,
3609
3610         /*
3611          * scheduling support
3612          */
3613         .get_frame_number =     xhci_get_frame,
3614
3615         /* Root hub support */
3616         .hub_control =          xhci_hub_control,
3617         .hub_status_data =      xhci_hub_status_data,
3618
3619 #ifdef CONFIG_PM
3620         .bus_suspend =          tegra_xhci_bus_suspend,
3621         .bus_resume =           tegra_xhci_bus_resume,
3622 #endif
3623 };
3624
3625 #ifdef CONFIG_PM
3626 static int
3627 tegra_xhci_suspend(struct platform_device *pdev,
3628                                                 pm_message_t state)
3629 {
3630         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3631         struct xhci_hcd *xhci = tegra->xhci;
3632
3633         int ret = 0;
3634
3635         mutex_lock(&tegra->sync_lock);
3636         if (!tegra->hc_in_elpg) {
3637                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
3638                                 __func__);
3639                 mutex_unlock(&tegra->sync_lock);
3640                 return -EBUSY;
3641         }
3642         mutex_unlock(&tegra->sync_lock);
3643
3644         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3645         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3646
3647         /* enable_irq_wake for ss ports */
3648         ret = enable_irq_wake(tegra->padctl_irq);
3649         if (ret < 0) {
3650                 xhci_err(xhci,
3651                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
3652                 __func__, tegra->padctl_irq, ret);
3653         }
3654
3655         /* enable_irq_wake for utmip/uhisc wakes */
3656         ret = enable_irq_wake(tegra->usb3_irq);
3657         if (ret < 0) {
3658                 xhci_err(xhci,
3659                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3660                 __func__, tegra->usb3_irq, ret);
3661         }
3662
3663         /* enable_irq_wake for utmip/uhisc wakes */
3664         ret = enable_irq_wake(tegra->usb2_irq);
3665         if (ret < 0) {
3666                 xhci_err(xhci,
3667                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3668                 __func__, tegra->usb2_irq, ret);
3669         }
3670
3671         regulator_disable(tegra->xusb_s1p8v_reg);
3672         regulator_disable(tegra->xusb_s1p05v_reg);
3673         tegra_usb2_clocks_deinit(tegra);
3674
3675         return ret;
3676 }
3677
3678 static int
3679 tegra_xhci_resume(struct platform_device *pdev)
3680 {
3681         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3682
3683         dev_dbg(&pdev->dev, "%s\n", __func__);
3684
3685         tegra->last_jiffies = jiffies;
3686
3687         disable_irq_wake(tegra->padctl_irq);
3688         disable_irq_wake(tegra->usb3_irq);
3689         disable_irq_wake(tegra->usb2_irq);
3690         tegra->lp0_exit = true;
3691
3692         regulator_enable(tegra->xusb_s1p05v_reg);
3693         regulator_enable(tegra->xusb_s1p8v_reg);
3694         tegra_usb2_clocks_init(tegra);
3695
3696         return 0;
3697 }
3698 #endif
3699
3700
3701 static int init_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3702 {
3703         struct platform_device *pdev = tegra->pdev;
3704         void __iomem *fw_mmio_base;
3705         phys_addr_t fw_mem_phy_addr;
3706         size_t fw_size;
3707         dma_addr_t fw_dma;
3708 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3709         int ret;
3710         DEFINE_DMA_ATTRS(attrs);
3711 #endif
3712
3713         /* bootloader saved firmware memory address in PMC SCRATCH34 register */
3714         fw_mem_phy_addr = tegra_usb_pmc_reg_read(PMC_SCRATCH34);
3715
3716         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3717                         fw_mem_phy_addr, sizeof(struct cfgtbl));
3718
3719         if (!fw_mmio_base) {
3720                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3721                                         fw_mem_phy_addr);
3722                         return -ENOMEM;
3723         }
3724
3725         fw_size = ioread32(fw_mmio_base + FW_SIZE_OFFSET);
3726         devm_iounmap(&pdev->dev, fw_mmio_base);
3727
3728         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3729                         fw_mem_phy_addr, fw_size);
3730         if (!fw_mmio_base) {
3731                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3732                                         fw_mem_phy_addr);
3733                         return -ENOMEM;
3734         }
3735
3736         dev_info(&pdev->dev, "Firmware Memory: phy 0x%x mapped 0x%p (%d Bytes)\n",
3737                         fw_mem_phy_addr, fw_mmio_base, fw_size);
3738
3739 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3740         dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
3741         fw_dma = dma_map_linear_attrs(&pdev->dev, fw_mem_phy_addr, fw_size,
3742                         DMA_TO_DEVICE, &attrs);
3743
3744         if (fw_dma == DMA_ERROR_CODE) {
3745                 dev_err(&pdev->dev, "%s: dma_map_linear failed\n",
3746                                 __func__);
3747                 ret = -ENOMEM;
3748                 goto error_iounmap;
3749         }
3750 #else
3751         fw_dma = fw_mem_phy_addr;
3752 #endif
3753         dev_info(&pdev->dev, "Firmware DMA Memory: dma 0x%p (%d Bytes)\n",
3754                         (void *) fw_dma, fw_size);
3755
3756         /* all set and ready to go */
3757         tegra->firmware.data = fw_mmio_base;
3758         tegra->firmware.dma = fw_dma;
3759         tegra->firmware.size = fw_size;
3760
3761         return 0;
3762
3763 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3764 error_iounmap:
3765         devm_iounmap(&pdev->dev, fw_mmio_base);
3766         return ret;
3767 #endif
3768 }
3769
3770 static void deinit_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3771 {
3772         struct platform_device *pdev = tegra->pdev;
3773         void __iomem *fw_mmio_base = tegra->firmware.data;
3774
3775 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3776         dma_unmap_single(&pdev->dev, tegra->firmware.dma,
3777                         tegra->firmware.size, DMA_TO_DEVICE);
3778 #endif
3779         devm_iounmap(&pdev->dev, fw_mmio_base);
3780
3781         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
3782 }
3783
3784 static int init_filesystem_firmware(struct tegra_xhci_hcd *tegra)
3785 {
3786         struct platform_device *pdev = tegra->pdev;
3787         const struct firmware *fw;
3788         struct cfgtbl *fw_cfgtbl;
3789         size_t fw_size;
3790         void *fw_data;
3791         dma_addr_t fw_dma;
3792         int ret;
3793
3794         ret = request_firmware(&fw, firmware_file, &pdev->dev);
3795         if (ret < 0) {
3796                 dev_err(&pdev->dev, "request_firmware failed %d\n", ret);
3797                 return ret;
3798         }
3799
3800         fw_cfgtbl = (struct cfgtbl *) fw->data;
3801         fw_size = fw_cfgtbl->fwimg_len;
3802         dev_info(&pdev->dev, "Firmware File: %s (%d Bytes)\n",
3803                         firmware_file, fw_size);
3804
3805         fw_data = dma_alloc_coherent(&pdev->dev, fw_size,
3806                         &fw_dma, GFP_KERNEL);
3807         if (!fw_data) {
3808                 dev_err(&pdev->dev, "%s: dma_alloc_coherent failed\n",
3809                                 __func__);
3810                 ret = -ENOMEM;
3811                 goto error_release_firmware;
3812         }
3813
3814         memcpy(fw_data, fw->data, fw_size);
3815         dev_info(&pdev->dev, "Firmware DMA Memory: dma 0x%p mapped 0x%p (%d Bytes)\n",
3816                         (void *) fw_dma, fw_data, fw_size);
3817
3818         release_firmware(fw);
3819
3820         /* all set and ready to go */
3821         tegra->firmware.data = fw_data;
3822         tegra->firmware.dma = fw_dma;
3823         tegra->firmware.size = fw_size;
3824         return 0;
3825
3826 error_release_firmware:
3827         release_firmware(fw);
3828         return ret;
3829 }
3830
3831 static void deinit_filesystem_firmware(struct tegra_xhci_hcd *tegra)
3832 {
3833         struct platform_device *pdev = tegra->pdev;
3834
3835         if (tegra->firmware.data) {
3836                 dma_free_coherent(&pdev->dev, tegra->firmware.size,
3837                         tegra->firmware.data, tegra->firmware.dma);
3838         }
3839
3840         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
3841 }
3842 static int init_firmware(struct tegra_xhci_hcd *tegra)
3843 {
3844         if (use_bootloader_firmware)
3845                 return init_bootloader_firmware(tegra);
3846         else
3847                 return init_filesystem_firmware(tegra);
3848 }
3849
3850 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
3851 {
3852         if (use_bootloader_firmware)
3853                 return deinit_bootloader_firmware(tegra);
3854         else
3855                 return deinit_filesystem_firmware(tegra);
3856 }
3857
3858 static int tegra_enable_xusb_clk(struct tegra_xhci_hcd *tegra,
3859                 struct platform_device *pdev)
3860 {
3861         int err = 0;
3862         /* enable ss clock */
3863         err = clk_enable(tegra->host_clk);
3864         if (err) {
3865                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
3866                 goto enable_host_clk_failed;
3867         }
3868
3869         err = clk_enable(tegra->ss_clk);
3870         if (err) {
3871                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
3872                 goto eanble_ss_clk_failed;
3873         }
3874
3875         err = clk_enable(tegra->emc_clk);
3876         if (err) {
3877                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
3878                 goto eanble_emc_clk_failed;
3879         }
3880
3881         return 0;
3882
3883 eanble_emc_clk_failed:
3884         clk_disable(tegra->ss_clk);
3885
3886 eanble_ss_clk_failed:
3887         clk_disable(tegra->host_clk);
3888
3889 enable_host_clk_failed:
3890         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
3891                 clk_disable(tegra->pll_re_vco_clk);
3892         return err;
3893 }
3894
3895 static struct tegra_xusb_padctl_regs t114_padregs_offset = {
3896         .boot_media_0                   = 0x0,
3897         .usb2_pad_mux_0                 = 0x4,
3898         .usb2_port_cap_0                = 0x8,
3899         .snps_oc_map_0                  = 0xc,
3900         .usb2_oc_map_0                  = 0x10,
3901         .ss_port_map_0                  = 0x14,
3902         .oc_det_0                       = 0x18,
3903         .elpg_program_0                 = 0x1c,
3904         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3905         .usb2_bchrg_otgpad0_ctl1_0      = 0xffff,
3906         .usb2_bchrg_otgpad1_ctl0_0      = 0x24,
3907         .usb2_bchrg_otgpad1_ctl1_0      = 0xffff,
3908         .usb2_bchrg_otgpad2_ctl0_0      = 0xffff,
3909         .usb2_bchrg_otgpad2_ctl1_0      = 0xffff,
3910         .usb2_bchrg_bias_pad_0          = 0x28,
3911         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
3912         .iophy_pll_p0_ctl1_0            = 0x30,
3913         .iophy_pll_p0_ctl2_0            = 0x34,
3914         .iophy_pll_p0_ctl3_0            = 0x38,
3915         .iophy_pll_p0_ctl4_0            = 0x3c,
3916         .iophy_usb3_pad0_ctl1_0         = 0x40,
3917         .iophy_usb3_pad1_ctl1_0         = 0x44,
3918         .iophy_usb3_pad0_ctl2_0         = 0x48,
3919         .iophy_usb3_pad1_ctl2_0         = 0x4c,
3920         .iophy_usb3_pad0_ctl3_0         = 0x50,
3921         .iophy_usb3_pad1_ctl3_0         = 0x54,
3922         .iophy_usb3_pad0_ctl4_0         = 0x58,
3923         .iophy_usb3_pad1_ctl4_0         = 0x5c,
3924         .iophy_misc_pad_p0_ctl1_0       = 0x60,
3925         .iophy_misc_pad_p1_ctl1_0       = 0x64,
3926         .iophy_misc_pad_p0_ctl2_0       = 0x68,
3927         .iophy_misc_pad_p1_ctl2_0       = 0x6c,
3928         .iophy_misc_pad_p0_ctl3_0       = 0x70,
3929         .iophy_misc_pad_p1_ctl3_0       = 0x74,
3930         .iophy_misc_pad_p0_ctl4_0       = 0x78,
3931         .iophy_misc_pad_p1_ctl4_0       = 0x7c,
3932         .iophy_misc_pad_p0_ctl5_0       = 0x80,
3933         .iophy_misc_pad_p1_ctl5_0       = 0x84,
3934         .iophy_misc_pad_p0_ctl6_0       = 0x88,
3935         .iophy_misc_pad_p1_ctl6_0       = 0x8c,
3936         .usb2_otg_pad0_ctl0_0           = 0x90,
3937         .usb2_otg_pad1_ctl0_0           = 0x94,
3938         .usb2_otg_pad2_ctl0_0           = 0xffff,
3939         .usb2_otg_pad0_ctl1_0           = 0x98,
3940         .usb2_otg_pad1_ctl1_0           = 0x9c,
3941         .usb2_otg_pad2_ctl1_0           = 0xffff,
3942         .usb2_bias_pad_ctl0_0           = 0xa0,
3943         .usb2_bias_pad_ctl1_0           = 0xa4,
3944         .usb2_hsic_pad0_ctl0_0          = 0xa8,
3945         .usb2_hsic_pad1_ctl0_0          = 0xac,
3946         .usb2_hsic_pad0_ctl1_0          = 0xb0,
3947         .usb2_hsic_pad1_ctl1_0          = 0xb4,
3948         .usb2_hsic_pad0_ctl2_0          = 0xb8,
3949         .usb2_hsic_pad1_ctl2_0          = 0xbc,
3950         .ulpi_link_trim_ctl0            = 0xc0,
3951         .ulpi_null_clk_trim_ctl0        = 0xc4,
3952         .hsic_strb_trim_ctl0            = 0xc8,
3953         .wake_ctl0                      = 0xcc,
3954         .pm_spare0                      = 0xd0,
3955         .iophy_misc_pad_p2_ctl1_0       = 0xffff,
3956         .iophy_misc_pad_p3_ctl1_0       = 0xffff,
3957         .iophy_misc_pad_p4_ctl1_0       = 0xffff,
3958         .iophy_misc_pad_p2_ctl2_0       = 0xffff,
3959         .iophy_misc_pad_p3_ctl2_0       = 0xffff,
3960         .iophy_misc_pad_p4_ctl2_0       = 0xffff,
3961         .iophy_misc_pad_p2_ctl3_0       = 0xffff,
3962         .iophy_misc_pad_p3_ctl3_0       = 0xffff,
3963         .iophy_misc_pad_p4_ctl3_0       = 0xffff,
3964         .iophy_misc_pad_p2_ctl4_0       = 0xffff,
3965         .iophy_misc_pad_p3_ctl4_0       = 0xffff,
3966         .iophy_misc_pad_p4_ctl4_0       = 0xffff,
3967         .iophy_misc_pad_p2_ctl5_0       = 0xffff,
3968         .iophy_misc_pad_p3_ctl5_0       = 0xffff,
3969         .iophy_misc_pad_p4_ctl5_0       = 0xffff,
3970         .iophy_misc_pad_p2_ctl6_0       = 0xffff,
3971         .iophy_misc_pad_p3_ctl6_0       = 0xffff,
3972         .iophy_misc_pad_p4_ctl6_0       = 0xffff,
3973         .usb3_pad_mux_0                 = 0xffff,
3974         .iophy_pll_s0_ctl1_0            = 0xffff,
3975         .iophy_pll_s0_ctl2_0            = 0xffff,
3976         .iophy_pll_s0_ctl3_0            = 0xffff,
3977         .iophy_pll_s0_ctl4_0            = 0xffff,
3978         .iophy_misc_pad_s0_ctl1_0       = 0xffff,
3979         .iophy_misc_pad_s0_ctl2_0       = 0xffff,
3980         .iophy_misc_pad_s0_ctl3_0       = 0xffff,
3981         .iophy_misc_pad_s0_ctl4_0       = 0xffff,
3982         .iophy_misc_pad_s0_ctl5_0       = 0xffff,
3983         .iophy_misc_pad_s0_ctl6_0       = 0xffff,
3984 };
3985
3986 static struct tegra_xusb_padctl_regs t124_padregs_offset = {
3987         .boot_media_0                   = 0x0,
3988         .usb2_pad_mux_0                 = 0x4,
3989         .usb2_port_cap_0                = 0x8,
3990         .snps_oc_map_0                  = 0xc,
3991         .usb2_oc_map_0                  = 0x10,
3992         .ss_port_map_0                  = 0x14,
3993         .oc_det_0                       = 0x18,
3994         .elpg_program_0                 = 0x1c,
3995         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3996         .usb2_bchrg_otgpad0_ctl1_0      = 0x24,
3997         .usb2_bchrg_otgpad1_ctl0_0      = 0x28,
3998         .usb2_bchrg_otgpad1_ctl1_0      = 0x2c,
3999         .usb2_bchrg_otgpad2_ctl0_0      = 0x30,
4000         .usb2_bchrg_otgpad2_ctl1_0      = 0x34,
4001         .usb2_bchrg_bias_pad_0          = 0x38,
4002         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
4003         .iophy_pll_p0_ctl1_0            = 0x40,
4004         .iophy_pll_p0_ctl2_0            = 0x44,
4005         .iophy_pll_p0_ctl3_0            = 0x48,
4006         .iophy_pll_p0_ctl4_0            = 0x4c,
4007         .iophy_usb3_pad0_ctl1_0         = 0x50,
4008         .iophy_usb3_pad1_ctl1_0         = 0x54,
4009         .iophy_usb3_pad0_ctl2_0         = 0x58,
4010         .iophy_usb3_pad1_ctl2_0         = 0x5c,
4011         .iophy_usb3_pad0_ctl3_0         = 0x60,
4012         .iophy_usb3_pad1_ctl3_0         = 0x64,
4013         .iophy_usb3_pad0_ctl4_0         = 0x68,
4014         .iophy_usb3_pad1_ctl4_0         = 0x6c,
4015         .iophy_misc_pad_p0_ctl1_0       = 0x70,
4016         .iophy_misc_pad_p1_ctl1_0       = 0x74,
4017         .iophy_misc_pad_p0_ctl2_0       = 0x78,
4018         .iophy_misc_pad_p1_ctl2_0       = 0x7c,
4019         .iophy_misc_pad_p0_ctl3_0       = 0x80,
4020         .iophy_misc_pad_p1_ctl3_0       = 0x84,
4021         .iophy_misc_pad_p0_ctl4_0       = 0x88,
4022         .iophy_misc_pad_p1_ctl4_0       = 0x8c,
4023         .iophy_misc_pad_p0_ctl5_0       = 0x90,
4024         .iophy_misc_pad_p1_ctl5_0       = 0x94,
4025         .iophy_misc_pad_p0_ctl6_0       = 0x98,
4026         .iophy_misc_pad_p1_ctl6_0       = 0x9c,
4027         .usb2_otg_pad0_ctl0_0           = 0xa0,
4028         .usb2_otg_pad1_ctl0_0           = 0xa4,
4029         .usb2_otg_pad2_ctl0_0           = 0xa8,
4030         .usb2_otg_pad0_ctl1_0           = 0xac,
4031         .usb2_otg_pad1_ctl1_0           = 0xb0,
4032         .usb2_otg_pad2_ctl1_0           = 0xb4,
4033         .usb2_bias_pad_ctl0_0           = 0xb8,
4034         .usb2_bias_pad_ctl1_0           = 0xbc,
4035         .usb2_hsic_pad0_ctl0_0          = 0xc0,
4036         .usb2_hsic_pad1_ctl0_0          = 0xc4,
4037         .usb2_hsic_pad0_ctl1_0          = 0xc8,
4038         .usb2_hsic_pad1_ctl1_0          = 0xcc,
4039         .usb2_hsic_pad0_ctl2_0          = 0xd0,
4040         .usb2_hsic_pad1_ctl2_0          = 0xd4,
4041         .ulpi_link_trim_ctl0            = 0xd8,
4042         .ulpi_null_clk_trim_ctl0        = 0xdc,
4043         .hsic_strb_trim_ctl0            = 0xe0,
4044         .wake_ctl0                      = 0xe4,
4045         .pm_spare0                      = 0xe8,
4046         .iophy_misc_pad_p2_ctl1_0       = 0xec,
4047         .iophy_misc_pad_p3_ctl1_0       = 0xf0,
4048         .iophy_misc_pad_p4_ctl1_0       = 0xf4,
4049         .iophy_misc_pad_p2_ctl2_0       = 0xf8,
4050         .iophy_misc_pad_p3_ctl2_0       = 0xfc,
4051         .iophy_misc_pad_p4_ctl2_0       = 0x100,
4052         .iophy_misc_pad_p2_ctl3_0       = 0x104,
4053         .iophy_misc_pad_p3_ctl3_0       = 0x108,
4054         .iophy_misc_pad_p4_ctl3_0       = 0x10c,
4055         .iophy_misc_pad_p2_ctl4_0       = 0x110,
4056         .iophy_misc_pad_p3_ctl4_0       = 0x114,
4057         .iophy_misc_pad_p4_ctl4_0       = 0x118,
4058         .iophy_misc_pad_p2_ctl5_0       = 0x11c,
4059         .iophy_misc_pad_p3_ctl5_0       = 0x120,
4060         .iophy_misc_pad_p4_ctl5_0       = 0x124,
4061         .iophy_misc_pad_p2_ctl6_0       = 0x128,
4062         .iophy_misc_pad_p3_ctl6_0       = 0x12c,
4063         .iophy_misc_pad_p4_ctl6_0       = 0x130,
4064         .usb3_pad_mux_0                 = 0x134,
4065         .iophy_pll_s0_ctl1_0            = 0x138,
4066         .iophy_pll_s0_ctl2_0            = 0x13c,
4067         .iophy_pll_s0_ctl3_0            = 0x140,
4068         .iophy_pll_s0_ctl4_0            = 0x144,
4069         .iophy_misc_pad_s0_ctl1_0       = 0x148,
4070         .iophy_misc_pad_s0_ctl2_0       = 0x14c,
4071         .iophy_misc_pad_s0_ctl3_0       = 0x150,
4072         .iophy_misc_pad_s0_ctl4_0       = 0x154,
4073         .iophy_misc_pad_s0_ctl5_0       = 0x158,
4074         .iophy_misc_pad_s0_ctl6_0       = 0x15c,
4075 };
4076
4077 /* FIXME: using notifier to transfer control to host from suspend
4078  * for otg port when xhci is in elpg. Find  better alternative
4079  */
4080 static int tegra_xhci_otg_notify(struct notifier_block *nb,
4081                                    unsigned long event, void *unused)
4082 {
4083         struct tegra_xhci_hcd *tegra = container_of(nb,
4084                                         struct tegra_xhci_hcd, otgnb);
4085
4086         if ((event == USB_EVENT_ID))
4087                 if (tegra->hc_in_elpg) {
4088                         schedule_work(&tegra->host_elpg_exit_work);
4089                         tegra->host_resume_req = true;
4090         }
4091
4092         return NOTIFY_OK;
4093 }
4094
4095 /* TODO: we have to refine error handling in tegra_xhci_probe() */
4096 static int tegra_xhci_probe(struct platform_device *pdev)
4097 {
4098         const struct hc_driver *driver;
4099         struct xhci_hcd *xhci;
4100         struct tegra_xhci_hcd *tegra;
4101         struct resource *res;
4102         struct usb_hcd  *hcd;
4103         unsigned pad;
4104         unsigned port;
4105         u32 val;
4106         int ret;
4107         int irq;
4108
4109         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
4110
4111         if (usb_disabled())
4112                 return -ENODEV;
4113
4114         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
4115         if (!tegra) {
4116                 dev_err(&pdev->dev, "memory alloc failed\n");
4117                 return -ENOMEM;
4118         }
4119         tegra->pdev = pdev;
4120         tegra->pdata = dev_get_platdata(&pdev->dev);
4121         tegra->bdata = tegra->pdata->bdata;
4122         tegra->ss_pwr_gated = false;
4123         tegra->host_pwr_gated = false;
4124         tegra->hc_in_elpg = false;
4125         tegra->hs_wake_event = false;
4126         tegra->host_resume_req = false;
4127         tegra->lp0_exit = false;
4128
4129         ret = tegra_xhci_request_mem_region(pdev, "padctl",
4130                         &tegra->padctl_base);
4131         if (ret) {
4132                 dev_err(&pdev->dev, "failed to map padctl\n");
4133                 return ret;
4134         }
4135
4136         ret = tegra_xhci_request_mem_region(pdev, "fpci", &tegra->fpci_base);
4137         if (ret) {
4138                 dev_err(&pdev->dev, "failed to map fpci\n");
4139                 return ret;
4140         }
4141
4142         ret = tegra_xhci_request_mem_region(pdev, "ipfs", &tegra->ipfs_base);
4143         if (ret) {
4144                 dev_err(&pdev->dev, "failed to map ipfs\n");
4145                 return ret;
4146         }
4147
4148         ret = tegra_xusb_partitions_clk_init(tegra);
4149         if (ret) {
4150                 dev_err(&pdev->dev,
4151                         "failed to initialize xusb partitions clocks\n");
4152                 return ret;
4153         }
4154
4155         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) {
4156                 tegra->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
4157                 if (IS_ERR_OR_NULL(tegra->transceiver)) {
4158                         dev_err(&pdev->dev, "failed to get usb phy\n");
4159                         tegra->transceiver = NULL;
4160                 } else {
4161                         otg_set_host(tegra->transceiver->otg, &hcd->self);
4162                         tegra->otgnb.notifier_call = tegra_xhci_otg_notify;
4163                         usb_register_notifier(tegra->transceiver,
4164                                 &tegra->otgnb);
4165                 }
4166         }
4167         /* Enable power rails to the PAD,VBUS
4168          * and pull-up voltage.Initialize the regulators
4169          */
4170         ret = tegra_xusb_regulator_init(tegra, pdev);
4171         if (ret) {
4172                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
4173                 goto err_deinit_xusb_partition_clk;
4174         }
4175
4176         /* Enable UTMIP, PLLU and PLLE */
4177         ret = tegra_usb2_clocks_init(tegra);
4178         if (ret) {
4179                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
4180                 goto err_deinit_tegra_xusb_regulator;
4181         }
4182
4183         /* tegra_unpowergate_partition also does partition reset deassert */
4184         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
4185         if (ret)
4186                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
4187
4188         /* tegra_unpowergate_partition also does partition reset deassert */
4189         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
4190         if (ret)
4191                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
4192
4193         ret = tegra_enable_xusb_clk(tegra, pdev);
4194         if (ret)
4195                 dev_err(&pdev->dev, "could not enable partition clock\n");
4196
4197         /* reset the pointer back to NULL. driver uses it */
4198         /* platform_set_drvdata(pdev, NULL); */
4199
4200         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "host");
4201         if (!res) {
4202                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
4203                 ret = -ENODEV;
4204                 goto err_deinit_usb2_clocks;
4205         }
4206         tegra->host_phy_base = res->start;
4207
4208         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
4209                                 res->start, resource_size(res));
4210         if (!tegra->host_phy_virt_base) {
4211                 dev_err(&pdev->dev, "error mapping host phy memory\n");
4212                 ret = -ENOMEM;
4213                 goto err_deinit_usb2_clocks;
4214         }
4215
4216         /* Setup IPFS access and BAR0 space */
4217         tegra_xhci_cfg(tegra);
4218
4219         val = readl(tegra->fpci_base + XUSB_CFG_0);
4220         tegra->device_id = (val >> 16) & 0xffff;
4221
4222         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
4223                 (XUSB_DEVICE_ID_T114 == tegra->device_id) ? "T114" : "T124+");
4224
4225         if (XUSB_DEVICE_ID_T114 == tegra->device_id) {
4226                 tegra->padregs = &t114_padregs_offset;
4227         } else if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
4228                 tegra->padregs = &t124_padregs_offset;
4229         } else {
4230                 dev_info(&pdev->dev, "XUSB device_id neither T114 nor T124!\n");
4231                 dev_info(&pdev->dev, "XUSB using T124 pad register offsets!\n");
4232                 tegra->padregs = &t124_padregs_offset;
4233         }
4234
4235         /* calculate rctrl_val and tctrl_val once at boot time */
4236         /* Issue is only applicable for T114 */
4237         if (XUSB_DEVICE_ID_T114 == tegra->device_id)
4238                 tegra_xhci_war_for_tctrl_rctrl(tegra);
4239
4240         for_each_enabled_hsic_pad(pad, tegra)
4241                 hsic_power_rail_enable(tegra);
4242
4243         /* Program the XUSB pads to take ownership of ports */
4244         tegra_xhci_padctl_portmap_and_caps(tegra);
4245
4246         /* Release XUSB wake logic state latching */
4247         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
4248         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
4249
4250         /* Deassert reset to XUSB host, ss, dev clocks */
4251         tegra_periph_reset_deassert(tegra->host_clk);
4252         tegra_periph_reset_deassert(tegra->ss_clk);
4253
4254         fw_log_init(tegra);
4255         ret = init_firmware(tegra);
4256         if (ret < 0) {
4257                 dev_err(&pdev->dev, "failed to init firmware\n");
4258                 ret = -ENODEV;
4259                 goto err_deinit_firmware_log;
4260         }
4261
4262         ret = load_firmware(tegra, true /* do reset ARU */);
4263         if (ret < 0) {
4264                 dev_err(&pdev->dev, "failed to load firmware\n");
4265                 ret = -ENODEV;
4266                 goto err_deinit_firmware;
4267         }
4268
4269         spin_lock_init(&tegra->lock);
4270         mutex_init(&tegra->sync_lock);
4271         mutex_init(&tegra->mbox_lock);
4272         pmc_init(tegra);
4273
4274         device_init_wakeup(&pdev->dev, 1);
4275         driver = &tegra_plat_xhci_driver;
4276
4277         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
4278         if (!hcd) {
4279                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
4280                 ret = -ENOMEM;
4281                 goto err_deinit_firmware;
4282         }
4283
4284         ret = tegra_xhci_request_mem_region(pdev, "host", &hcd->regs);
4285         if (ret) {
4286                 dev_err(&pdev->dev, "failed to map host\n");
4287                 goto err_put_usb2_hcd;
4288         }
4289         hcd->rsrc_start = res->start;
4290         hcd->rsrc_len = resource_size(res);
4291
4292         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "host");
4293         if (!res) {
4294                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
4295                 ret = -ENODEV;
4296                 goto err_put_usb2_hcd;
4297         }
4298         irq = res->start;
4299         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
4300         if (ret) {
4301                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
4302                 goto err_put_usb2_hcd;
4303         }
4304
4305         /* USB 2.0 roothub is stored in the platform_device now. */
4306         hcd = dev_get_drvdata(&pdev->dev);
4307         xhci = hcd_to_xhci(hcd);
4308         tegra->xhci = xhci;
4309         platform_set_drvdata(pdev, tegra);
4310
4311         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
4312                                                 dev_name(&pdev->dev), hcd);
4313         if (!xhci->shared_hcd) {
4314                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
4315                 ret = -ENOMEM;
4316                 goto err_remove_usb2_hcd;
4317         }
4318
4319         /*
4320          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
4321          * is called by usb_add_hcd().
4322          */
4323         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
4324
4325         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
4326         if (ret) {
4327                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
4328                 goto err_put_usb3_hcd;
4329         }
4330
4331         device_init_wakeup(&hcd->self.root_hub->dev, 1);
4332         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
4333
4334         /* do mailbox related initializations */
4335         tegra->mbox_owner = 0xffff;
4336         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
4337
4338         tegra_xhci_enable_fw_message(tegra);
4339
4340         /* do ss partition elpg exit related initialization */
4341         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
4342
4343         /* do host partition elpg exit related initialization */
4344         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
4345
4346         /* Register interrupt handler for SMI line to handle mailbox
4347          * interrupt from firmware
4348          */
4349         ret = tegra_xhci_request_irq(pdev, "host-smi", tegra_xhci_smi_irq,
4350                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
4351         if (ret != 0)
4352                 goto err_remove_usb3_hcd;
4353
4354         /* Register interrupt handler for PADCTRL line to
4355          * handle wake on connect irqs interrupt from
4356          * firmware
4357          */
4358         ret = tegra_xhci_request_irq(pdev, "padctl", tegra_xhci_padctl_irq,
4359                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
4360                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
4361         if (ret != 0)
4362                 goto err_remove_usb3_hcd;
4363
4364         ret = tegra_xhci_request_irq(pdev, "usb2", pmc_usb_phy_wake_isr,
4365                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4366                 &tegra->usb2_irq);
4367         if (ret != 0)
4368                 goto err_remove_usb3_hcd;
4369
4370         ret = tegra_xhci_request_irq(pdev, "usb3", pmc_usb_phy_wake_isr,
4371                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4372                 &tegra->usb3_irq);
4373         if (ret != 0)
4374                 goto err_remove_usb3_hcd;
4375
4376         for (port = 0; port < XUSB_SS_PORT_COUNT; port++) {
4377                 tegra->ctle_ctx_saved[port] = false;
4378                 tegra->dfe_ctx_saved[port] = false;
4379         }
4380
4381         hsic_pad_pretend_connect(tegra);
4382
4383         tegra_xhci_debug_read_pads(tegra);
4384         utmi_phy_pad_enable();
4385         utmi_phy_iddq_override(false);
4386
4387         tegra_pd_add_device(&pdev->dev);
4388
4389         return 0;
4390
4391 err_remove_usb3_hcd:
4392         usb_remove_hcd(xhci->shared_hcd);
4393 err_put_usb3_hcd:
4394         usb_put_hcd(xhci->shared_hcd);
4395 err_remove_usb2_hcd:
4396         kfree(tegra->xhci);
4397         usb_remove_hcd(hcd);
4398 err_put_usb2_hcd:
4399         usb_put_hcd(hcd);
4400 err_deinit_firmware:
4401         deinit_firmware(tegra);
4402 err_deinit_firmware_log:
4403         fw_log_deinit(tegra);
4404 err_deinit_usb2_clocks:
4405         tegra_usb2_clocks_deinit(tegra);
4406 err_deinit_tegra_xusb_regulator:
4407         tegra_xusb_regulator_deinit(tegra);
4408 err_deinit_xusb_partition_clk:
4409         if (tegra->transceiver)
4410                 usb_unregister_notifier(tegra->transceiver, &tegra->otgnb);
4411
4412         tegra_xusb_partitions_clk_deinit(tegra);
4413
4414         return ret;
4415 }
4416
4417 static int tegra_xhci_remove(struct platform_device *pdev)
4418 {
4419         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4420         struct xhci_hcd *xhci = NULL;
4421         struct usb_hcd *hcd = NULL;
4422         unsigned pad;
4423
4424         if (tegra == NULL)
4425                 return -EINVAL;
4426
4427         xhci = tegra->xhci;
4428         hcd = xhci_to_hcd(xhci);
4429
4430         for_each_enabled_hsic_pad(pad, tegra) {
4431                 hsic_pad_disable(tegra, pad);
4432                 hsic_power_rail_disable(tegra);
4433         }
4434
4435         devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
4436         devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
4437         devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
4438         usb_remove_hcd(xhci->shared_hcd);
4439         usb_put_hcd(xhci->shared_hcd);
4440         usb_remove_hcd(hcd);
4441         usb_put_hcd(hcd);
4442         kfree(xhci);
4443
4444         deinit_firmware(tegra);
4445         fw_log_deinit(tegra);
4446         tegra_xusb_regulator_deinit(tegra);
4447
4448         if (tegra->transceiver)
4449                 usb_unregister_notifier(tegra->transceiver, &tegra->otgnb);
4450
4451         tegra_usb2_clocks_deinit(tegra);
4452         if (!tegra->hc_in_elpg)
4453                 tegra_xusb_partitions_clk_deinit(tegra);
4454         utmi_phy_pad_disable();
4455         utmi_phy_iddq_override(true);
4456
4457         tegra_pd_remove_device(&pdev->dev);
4458         return 0;
4459 }
4460
4461 static void tegra_xhci_shutdown(struct platform_device *pdev)
4462 {
4463         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4464         struct xhci_hcd *xhci = NULL;
4465         struct usb_hcd *hcd = NULL;
4466
4467         if (tegra == NULL)
4468                 return;
4469
4470         if (tegra->hc_in_elpg) {
4471                 pmc_disable_bus_ctrl(tegra);
4472         } else {
4473                 xhci = tegra->xhci;
4474                 hcd = xhci_to_hcd(xhci);
4475                 xhci_shutdown(hcd);
4476         }
4477 }
4478
4479 static struct platform_driver tegra_xhci_driver = {
4480         .probe  = tegra_xhci_probe,
4481         .remove = tegra_xhci_remove,
4482         .shutdown = tegra_xhci_shutdown,
4483 #ifdef CONFIG_PM
4484         .suspend = tegra_xhci_suspend,
4485         .resume  = tegra_xhci_resume,
4486 #endif
4487         .driver = {
4488                 .name = "tegra-xhci",
4489         },
4490 };
4491 MODULE_ALIAS("platform:tegra-xhci");
4492
4493 int tegra_xhci_register_plat(void)
4494 {
4495         return platform_driver_register(&tegra_xhci_driver);
4496 }
4497
4498 void tegra_xhci_unregister_plat(void)
4499 {
4500         platform_driver_unregister(&tegra_xhci_driver);
4501 }