usb: xhci: tegra: enable clock after unpowergate
[linux-3.10.git] / drivers / usb / host / xhci-tegra.c
1 /*
2  * xhci-tegra.c - Nvidia xHCI host controller driver
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/clk.h>
24 #include <linux/ioport.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irq.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/uaccess.h>
30 #include <linux/circ_buf.h>
31 #include <linux/vmalloc.h>
32 #include <linux/debugfs.h>
33 #include <linux/kthread.h>
34 #include <linux/gpio.h>
35
36 #include <mach/powergate.h>
37 #include <mach/clk.h>
38 #include <mach/tegra_usb_pad_ctrl.h>
39 #include <mach/tegra_usb_pmc.h>
40 #include <mach/pm_domains.h>
41 #include <mach/mc.h>
42 #include <mach/xusb.h>
43
44 #include "../../../arch/arm/mach-tegra/iomap.h" /* HACK -- remove */
45 #include "xhci-tegra.h"
46 #include "xhci.h"
47
48 /* macros */
49 #define FW_IOCTL_LOG_DEQUEUE_LOW        (4)
50 #define FW_IOCTL_LOG_DEQUEUE_HIGH       (5)
51 #define FW_IOCTL_DATA_SHIFT             (0)
52 #define FW_IOCTL_DATA_MASK              (0x00ffffff)
53 #define FW_IOCTL_TYPE_SHIFT             (24)
54 #define FW_IOCTL_TYPE_MASK              (0xff000000)
55 #define FW_LOG_SIZE                     (sizeof(struct log_entry))
56 #define FW_LOG_COUNT                    (4096)
57 #define FW_LOG_RING_SIZE                (FW_LOG_SIZE * FW_LOG_COUNT)
58 #define FW_LOG_PAYLOAD_SIZE             (27)
59 #define DRIVER                          (0x01)
60 #define CIRC_BUF_SIZE                   (4 * (1 << 20)) /* 4MB */
61 #define FW_LOG_THREAD_RELAX             (msecs_to_jiffies(100))
62
63 /* tegra_xhci_firmware_log.flags bits */
64 #define FW_LOG_CONTEXT_VALID            (0)
65 #define FW_LOG_FILE_OPENED              (1)
66
67 #define PAGE_SELECT_MASK                        0xFFFFFE00
68 #define PAGE_SELECT_SHIFT                       9
69 #define PAGE_OFFSET_MASK                        0x000001FF
70 #define CSB_PAGE_SELECT(_addr)                                          \
71         ({                                                              \
72                 typecheck(u32, _addr);                                  \
73                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
74         })
75 #define CSB_PAGE_OFFSET(_addr)                                          \
76         ({                                                              \
77                 typecheck(u32, _addr);                                  \
78                 (_addr & PAGE_OFFSET_MASK);                             \
79         })
80
81 /* PMC register definition */
82 #define PMC_PORT_UTMIP_P0               0
83 #define PMC_PORT_UTMIP_P1               1
84 #define PMC_PORT_UTMIP_P2               2
85 #define PMC_PORT_UHSIC_P0               3
86 #define PMC_PORT_NUM                    4
87
88 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
89 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
90 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
91
92 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
93
94 /* private data types */
95 /* command requests from the firmware */
96 enum MBOX_CMD_TYPE {
97         MBOX_CMD_MSG_ENABLED = 1,
98         MBOX_CMD_INC_FALC_CLOCK,
99         MBOX_CMD_DEC_FALC_CLOCK,
100         MBOX_CMD_INC_SSPI_CLOCK,
101         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
102         MBOX_CMD_SET_BW,
103         MBOX_CMD_SET_SS_PWR_GATING,
104         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
105         MBOX_CMD_SAVE_DFE_CTLE_CTX,
106
107         /* needs to be the last cmd */
108         MBOX_CMD_MAX,
109
110         /* resp msg to ack above commands */
111         MBOX_CMD_ACK = 128,
112         MBOX_CMD_NACK
113 };
114
115 struct log_entry {
116         u32 sequence_no;
117         u8 data[FW_LOG_PAYLOAD_SIZE];
118         u8 owner;
119 };
120
121 /* Usb3 Firmware Cfg Table */
122 struct cfgtbl {
123         u32 boot_loadaddr_in_imem;
124         u32 boot_codedfi_offset;
125         u32 boot_codetag;
126         u32 boot_codesize;
127
128         /* Physical memory reserved by Bootloader/BIOS */
129         u32 phys_memaddr;
130         u16 reqphys_memsize;
131         u16 alloc_phys_memsize;
132
133         /* .rodata section */
134         u32 rodata_img_offset;
135         u32 rodata_section_start;
136         u32 rodata_section_end;
137         u32 main_fnaddr;
138
139         u32 fwimg_cksum;
140         u32 fwimg_created_time;
141
142         /* Fields that get filled by linker during linking phase
143          * or initialized in the FW code.
144          */
145         u32 imem_resident_start;
146         u32 imem_resident_end;
147         u32 idirect_start;
148         u32 idirect_end;
149         u32 l2_imem_start;
150         u32 l2_imem_end;
151         u32 version_id;
152         u8 init_ddirect;
153         u8 reserved[3];
154         u32 phys_addr_log_buffer;
155         u32 total_log_entries;
156         u32 dequeue_ptr;
157
158         /*      Below two dummy variables are used to replace
159          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
160          *      retain the size of struct _CFG_TBL used by other AP/Module.
161          */
162         u32 dummy_var1;
163         u32 dummy_var2;
164
165         /* fwimg_len */
166         u32 fwimg_len;
167         u8 magic[8];
168         u32 SS_low_power_entry_timeout;
169         u8 padding[140]; /* padding bytes to makeup 256-bytes cfgtbl */
170 };
171
172 struct xusb_save_regs {
173         u32 msi_bar_sz;
174         u32 msi_axi_barst;
175         u32 msi_fpci_barst;
176         u32 msi_vec0;
177         u32 msi_en_vec0;
178         u32 fpci_error_masks;
179         u32 intr_mask;
180         u32 ipfs_intr_enable;
181         u32 ufpci_config;
182         u32 clkgate_hysteresis;
183         u32 xusb_host_mccif_fifo_cntrl;
184
185         /* PG does not mention below */
186         u32 hs_pls;
187         u32 fs_pls;
188         u32 hs_fs_speed;
189         u32 hs_fs_pp;
190         u32 cfg_aru;
191         u32 cfg_order;
192         u32 cfg_fladj;
193         u32 cfg_sid;
194         /* DFE and CTLE */
195         u32 tap1_val[2];
196         u32 amp_val[2];
197         u32 ctle_z_val[2];
198         u32 ctle_g_val[2];
199 };
200
201 struct tegra_xhci_firmware {
202         void *data; /* kernel virtual address */
203         size_t size; /* firmware size */
204         dma_addr_t dma; /* dma address for controller */
205 };
206
207 struct tegra_xhci_firmware_log {
208         dma_addr_t phys_addr;           /* dma-able address */
209         void *virt_addr;                /* kernel va of the shared log buffer */
210         struct log_entry *dequeue;      /* current dequeue pointer (va) */
211         struct circ_buf circ;           /* big circular buffer */
212         u32 seq;                        /* log sequence number */
213
214         struct task_struct *thread;     /* a thread to consume log */
215         struct mutex mutex;
216         wait_queue_head_t read_wait;
217         wait_queue_head_t write_wait;
218         wait_queue_head_t intr_wait;
219         struct dentry *path;
220         struct dentry *log_file;
221         unsigned long flags;
222 };
223
224 /* structure to hold the offsets of padctl registers */
225 struct tegra_xusb_padctl_regs {
226         u16 boot_media_0;
227         u16 usb2_pad_mux_0;
228         u16 usb2_port_cap_0;
229         u16 snps_oc_map_0;
230         u16 usb2_oc_map_0;
231         u16 ss_port_map_0;
232         u16 oc_det_0;
233         u16 elpg_program_0;
234         u16 usb2_bchrg_otgpad0_ctl0_0;
235         u16 usb2_bchrg_otgpad0_ctl1_0;
236         u16 usb2_bchrg_otgpad1_ctl0_0;
237         u16 usb2_bchrg_otgpad1_ctl1_0;
238         u16 usb2_bchrg_otgpad2_ctl0_0;
239         u16 usb2_bchrg_otgpad2_ctl1_0;
240         u16 usb2_bchrg_bias_pad_0;
241         u16 usb2_bchrg_tdcd_dbnc_timer_0;
242         u16 iophy_pll_p0_ctl1_0;
243         u16 iophy_pll_p0_ctl2_0;
244         u16 iophy_pll_p0_ctl3_0;
245         u16 iophy_pll_p0_ctl4_0;
246         u16 iophy_usb3_pad0_ctl1_0;
247         u16 iophy_usb3_pad1_ctl1_0;
248         u16 iophy_usb3_pad0_ctl2_0;
249         u16 iophy_usb3_pad1_ctl2_0;
250         u16 iophy_usb3_pad0_ctl3_0;
251         u16 iophy_usb3_pad1_ctl3_0;
252         u16 iophy_usb3_pad0_ctl4_0;
253         u16 iophy_usb3_pad1_ctl4_0;
254         u16 iophy_misc_pad_p0_ctl1_0;
255         u16 iophy_misc_pad_p1_ctl1_0;
256         u16 iophy_misc_pad_p0_ctl2_0;
257         u16 iophy_misc_pad_p1_ctl2_0;
258         u16 iophy_misc_pad_p0_ctl3_0;
259         u16 iophy_misc_pad_p1_ctl3_0;
260         u16 iophy_misc_pad_p0_ctl4_0;
261         u16 iophy_misc_pad_p1_ctl4_0;
262         u16 iophy_misc_pad_p0_ctl5_0;
263         u16 iophy_misc_pad_p1_ctl5_0;
264         u16 iophy_misc_pad_p0_ctl6_0;
265         u16 iophy_misc_pad_p1_ctl6_0;
266         u16 usb2_otg_pad0_ctl0_0;
267         u16 usb2_otg_pad1_ctl0_0;
268         u16 usb2_otg_pad2_ctl0_0;
269         u16 usb2_otg_pad0_ctl1_0;
270         u16 usb2_otg_pad1_ctl1_0;
271         u16 usb2_otg_pad2_ctl1_0;
272         u16 usb2_bias_pad_ctl0_0;
273         u16 usb2_bias_pad_ctl1_0;
274         u16 usb2_hsic_pad0_ctl0_0;
275         u16 usb2_hsic_pad1_ctl0_0;
276         u16 usb2_hsic_pad0_ctl1_0;
277         u16 usb2_hsic_pad1_ctl1_0;
278         u16 usb2_hsic_pad0_ctl2_0;
279         u16 usb2_hsic_pad1_ctl2_0;
280         u16 ulpi_link_trim_ctl0;
281         u16 ulpi_null_clk_trim_ctl0;
282         u16 hsic_strb_trim_ctl0;
283         u16 wake_ctl0;
284         u16 pm_spare0;
285         u16 iophy_misc_pad_p2_ctl1_0;
286         u16 iophy_misc_pad_p3_ctl1_0;
287         u16 iophy_misc_pad_p4_ctl1_0;
288         u16 iophy_misc_pad_p2_ctl2_0;
289         u16 iophy_misc_pad_p3_ctl2_0;
290         u16 iophy_misc_pad_p4_ctl2_0;
291         u16 iophy_misc_pad_p2_ctl3_0;
292         u16 iophy_misc_pad_p3_ctl3_0;
293         u16 iophy_misc_pad_p4_ctl3_0;
294         u16 iophy_misc_pad_p2_ctl4_0;
295         u16 iophy_misc_pad_p3_ctl4_0;
296         u16 iophy_misc_pad_p4_ctl4_0;
297         u16 iophy_misc_pad_p2_ctl5_0;
298         u16 iophy_misc_pad_p3_ctl5_0;
299         u16 iophy_misc_pad_p4_ctl5_0;
300         u16 iophy_misc_pad_p2_ctl6_0;
301         u16 iophy_misc_pad_p3_ctl6_0;
302         u16 iophy_misc_pad_p4_ctl6_0;
303         u16 usb3_pad_mux_0;
304         u16 iophy_pll_s0_ctl1_0;
305         u16 iophy_pll_s0_ctl2_0;
306         u16 iophy_pll_s0_ctl3_0;
307         u16 iophy_pll_s0_ctl4_0;
308         u16 iophy_misc_pad_s0_ctl1_0;
309         u16 iophy_misc_pad_s0_ctl2_0;
310         u16 iophy_misc_pad_s0_ctl3_0;
311         u16 iophy_misc_pad_s0_ctl4_0;
312         u16 iophy_misc_pad_s0_ctl5_0;
313         u16 iophy_misc_pad_s0_ctl6_0;
314 };
315
316 struct tegra_xhci_hcd {
317         struct platform_device *pdev;
318         struct xhci_hcd *xhci;
319         u16 device_id;
320
321         spinlock_t lock;
322         struct mutex sync_lock;
323
324         int smi_irq;
325         int padctl_irq;
326         int usb3_irq;
327
328         bool ss_wake_event;
329         bool ss_pwr_gated;
330         bool host_pwr_gated;
331         bool hs_wake_event;
332         bool host_resume_req;
333         bool lp0_exit;
334         bool dfe_ctle_ctx_saved;
335         unsigned long last_jiffies;
336         unsigned long host_phy_base;
337         void __iomem *host_phy_virt_base;
338
339         void __iomem *padctl_base;
340         void __iomem *fpci_base;
341         void __iomem *ipfs_base;
342
343         struct tegra_xusb_platform_data *pdata;
344         struct tegra_xusb_board_data *bdata;
345         struct tegra_xusb_padctl_regs *padregs;
346
347         /* mailbox variables */
348         struct mutex mbox_lock;
349         u32 mbox_owner;
350         u32 cmd_type;
351         u32 cmd_data;
352
353         struct regulator *xusb_s5p0v_reg;
354         struct regulator *xusb_s5p0v1_reg;
355         struct regulator *xusb_s5p0v2_reg;
356         struct regulator *xusb_s1p05v_reg;
357         struct regulator *xusb_s3p3v_reg;
358         struct regulator *xusb_s1p8v_reg;
359
360         struct work_struct mbox_work;
361         struct work_struct ss_elpg_exit_work;
362         struct work_struct host_elpg_exit_work;
363
364         struct clk *host_clk;
365         struct clk *ss_clk;
366
367         /* XUSB Falcon SuperSpeed Clock */
368         struct clk *falc_clk;
369
370         /* EMC Clock */
371         struct clk *emc_clk;
372         /* XUSB SS PI Clock */
373         struct clk *ss_src_clk;
374         /* PLLE Clock */
375         struct clk *plle_clk;
376         struct clk *pll_u_480M;
377         struct clk *clk_m;
378         /* refPLLE clk */
379         struct clk *pll_re_vco_clk;
380         /*
381          * XUSB/IPFS specific registers these need to be saved/restored in
382          * addition to spec defined registers
383          */
384         struct xusb_save_regs sregs;
385         bool usb2_rh_suspend;
386         bool usb3_rh_suspend;
387         bool hc_in_elpg;
388
389         unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
390         /* firmware loading related */
391         struct tegra_xhci_firmware firmware;
392
393         struct tegra_xhci_firmware_log log;
394 };
395
396 static struct tegra_usb_pmc_data pmc_data;
397
398 /* functions */
399 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
400 {
401         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
402 }
403
404 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
405 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
406 {
407         WARN_ON(tegra->sync_lock.owner != current);
408 }
409 #else
410 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
411 #endif
412
413 static void tegra_xhci_setup_gpio_for_ss_lane(struct tegra_xhci_hcd *tegra)
414 {
415         int err = 0;
416
417         if (!tegra->bdata->gpio_controls_muxed_ss_lanes)
418                 return;
419
420         if (tegra->bdata->lane_owner & BIT(0)) {
421                 /* USB3_SS port1 is using SATA lane so set (MUX_SATA)
422                  * GPIO P11 to '0'
423                  */
424                 err = gpio_request((tegra->bdata->gpio_ss1_sata & 0xffff),
425                         "gpio_ss1_sata");
426                 if (err < 0)
427                         pr_err("%s: gpio_ss1_sata gpio_request failed %d\n",
428                                 __func__, err);
429                 err = gpio_direction_output((tegra->bdata->gpio_ss1_sata
430                         & 0xffff), 1);
431                 if (err < 0)
432                         pr_err("%s: gpio_ss1_sata gpio_direction failed %d\n",
433                                 __func__, err);
434                 __gpio_set_value((tegra->bdata->gpio_ss1_sata & 0xffff),
435                                 ((tegra->bdata->gpio_ss1_sata >> 16)));
436         }
437 }
438
439 static void debug_print_portsc(struct xhci_hcd *xhci)
440 {
441         __le32 __iomem *addr;
442         int i;
443         int ports;
444
445         ports = HCS_MAX_PORTS(xhci->hcs_params1);
446         addr = &xhci->op_regs->port_status_base;
447         for (i = 0; i < ports; i++) {
448                 xhci_dbg(xhci, "%p port %d status reg = 0x%x\n",
449                                 addr, i, (unsigned int) xhci_readl(xhci, addr));
450                 addr += NUM_PORT_REGS;
451         }
452 }
453 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra);
454
455 static void update_speed(struct tegra_xhci_hcd *tegra, u8 port, bool setup_wake)
456 {
457         struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
458         u32 portsc;
459
460         /* we don't need speed information to disable PMC */
461         if (!setup_wake)
462                 return;
463
464         portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port));
465         if (DEV_FULLSPEED(portsc))
466                 pmc_data.port_speed = USB_PMC_PORT_SPEED_FULL;
467         else if (DEV_HIGHSPEED(portsc))
468                 pmc_data.port_speed = USB_PMC_PORT_SPEED_HIGH;
469         else if (DEV_LOWSPEED(portsc))
470                 pmc_data.port_speed = USB_PMC_PORT_SPEED_LOW;
471         else if (DEV_SUPERSPEED(portsc))
472                 pmc_data.port_speed = USB_PMC_PORT_SPEED_SUPER;
473         else
474                 pmc_data.port_speed = USB_PMC_PORT_SPEED_UNKNOWN;
475 }
476
477 static void setup_wake_detect(bool setup_wake)
478 {
479         if (setup_wake)
480                 pmc_data.pmc_ops->setup_pmc_wake_detect(&pmc_data);
481         else
482                 pmc_data.pmc_ops->disable_pmc_bus_ctrl(&pmc_data, 0);
483 }
484
485 static void pmc_init(struct tegra_xhci_hcd *tegra, bool setup_wake)
486 {
487         u32 portmap = tegra->bdata->portmap;
488
489         pmc_data.controller_type = TEGRA_USB_3_0;
490         if (portmap & TEGRA_XUSB_USB2_P0) {
491                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 0) & 0xf;
492                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
493                 update_speed(tegra, pmc_data.instance, setup_wake);
494                 tegra_usb_pmc_init(&pmc_data);
495                 setup_wake_detect(setup_wake);
496         }
497         if (portmap & TEGRA_XUSB_USB2_P1) {
498                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 4) & 0xf;
499                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
500                 update_speed(tegra, pmc_data.instance, setup_wake);
501                 tegra_usb_pmc_init(&pmc_data);
502                 setup_wake_detect(setup_wake);
503         }
504         if (portmap & TEGRA_XUSB_USB2_P2) {
505                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 8) & 0xf;
506                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
507                 update_speed(tegra, pmc_data.instance, setup_wake);
508                 tegra_usb_pmc_init(&pmc_data);
509                 setup_wake_detect(setup_wake);
510         }
511         if (portmap & TEGRA_XUSB_HSIC_P0) {
512                 pmc_data.instance = PMC_PORT_UHSIC_P0;
513                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_HSIC;
514                 update_speed(tegra, pmc_data.instance, setup_wake);
515                 tegra_usb_pmc_init(&pmc_data);
516                 setup_wake_detect(setup_wake);
517         }
518 }
519
520 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
521 {
522         void __iomem *fpci_base = tegra->fpci_base;
523         struct platform_device *pdev = tegra->pdev;
524         u32 input_addr;
525         u32 data;
526         u32 csb_page_select;
527
528         /* to select the appropriate CSB page to write to */
529         csb_page_select = CSB_PAGE_SELECT(addr);
530
531         dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
532                         csb_page_select);
533
534         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
535
536         /* selects the appropriate offset in the page to read from */
537         input_addr = CSB_PAGE_OFFSET(addr);
538         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
539
540         dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
541                         input_addr, data);
542         return data;
543 }
544
545 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
546 {
547         void __iomem *fpci_base = tegra->fpci_base;
548         struct platform_device *pdev = tegra->pdev;
549         u32 input_addr;
550         u32 csb_page_select;
551
552         /* to select the appropriate CSB page to write to */
553         csb_page_select = CSB_PAGE_SELECT(addr);
554
555         dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
556                         csb_page_select);
557
558         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
559
560         /* selects the appropriate offset in the page to write to */
561         input_addr = CSB_PAGE_OFFSET(addr);
562         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
563
564         dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
565                         input_addr, data);
566 }
567
568 /**
569  * fw_log_next - find next log entry in a tegra_xhci_firmware_log context.
570  *      This function takes care of wrapping. That means when current log entry
571  *      is the last one, it returns with the first one.
572  *
573  * @param log   The tegra_xhci_firmware_log context.
574  * @param this  The current log entry.
575  * @return      The log entry which is next to the current one.
576  */
577 static inline struct log_entry *fw_log_next(
578                 struct tegra_xhci_firmware_log *log, struct log_entry *this)
579 {
580         struct log_entry *first = (struct log_entry *) log->virt_addr;
581         struct log_entry *last = first + FW_LOG_COUNT - 1;
582
583         WARN((this < first) || (this > last), "%s: invalid input\n", __func__);
584
585         return (this == last) ? first : (this + 1);
586 }
587
588 /**
589  * fw_log_update_dequeue_pointer - update dequeue pointer to both firmware and
590  *      tegra_xhci_firmware_log.dequeue.
591  *
592  * @param log   The tegra_xhci_firmware_log context.
593  * @param n     Counts of log entries to fast-forward.
594  */
595 static inline void fw_log_update_deq_pointer(
596                 struct tegra_xhci_firmware_log *log, int n)
597 {
598         struct tegra_xhci_hcd *tegra =
599                         container_of(log, struct tegra_xhci_hcd, log);
600         struct device *dev = &tegra->pdev->dev;
601         struct log_entry *deq = tegra->log.dequeue;
602         dma_addr_t physical_addr;
603         u32 reg;
604
605         dev_dbg(dev, "curr 0x%p fast-forward %d entries\n", deq, n);
606         while (n-- > 0)
607                 deq = fw_log_next(log, deq);
608
609         tegra->log.dequeue = deq;
610         physical_addr = tegra->log.phys_addr +
611                         ((u8 *)deq - (u8 *)tegra->log.virt_addr);
612
613         /* update dequeue pointer to firmware */
614         reg = (FW_IOCTL_LOG_DEQUEUE_LOW << FW_IOCTL_TYPE_SHIFT);
615         reg |= (physical_addr & 0xffff); /* lower 16-bits */
616         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
617
618         reg = (FW_IOCTL_LOG_DEQUEUE_HIGH << FW_IOCTL_TYPE_SHIFT);
619         reg |= ((physical_addr >> 16) & 0xffff); /* higher 16-bits */
620         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
621
622         dev_dbg(dev, "new 0x%p physical addr 0x%x\n", deq, physical_addr);
623 }
624
625 static inline bool circ_buffer_full(struct circ_buf *circ)
626 {
627         int space = CIRC_SPACE(circ->head, circ->tail, CIRC_BUF_SIZE);
628
629         return (space <= FW_LOG_SIZE);
630 }
631
632 static inline bool fw_log_available(struct tegra_xhci_hcd *tegra)
633 {
634         return (tegra->log.dequeue->owner == DRIVER);
635 }
636
637 /**
638  * fw_log_wait_empty_timeout - wait firmware log thread to clean up shared
639  *      log buffer.
640  * @param tegra:        tegra_xhci_hcd context
641  * @param msec:         timeout value in millisecond
642  * @return true:        shared log buffer is empty,
643  *         false:       shared log buffer isn't empty.
644  */
645 static inline bool fw_log_wait_empty_timeout(struct tegra_xhci_hcd *tegra,
646                 unsigned timeout)
647 {
648         u32 target = jiffies + msecs_to_jiffies(timeout);
649         bool ret;
650
651         mutex_lock(&tegra->log.mutex);
652
653         while (fw_log_available(tegra) && time_is_after_jiffies(target)) {
654                 mutex_unlock(&tegra->log.mutex);
655                 usleep_range(1000, 2000);
656                 mutex_lock(&tegra->log.mutex);
657         }
658
659         ret = fw_log_available(tegra);
660         mutex_unlock(&tegra->log.mutex);
661
662         return ret;
663 }
664
665 /**
666  * fw_log_copy - copy firmware log from device's buffer to driver's circular
667  *      buffer.
668  * @param tegra tegra_xhci_hcd context
669  * @return true,        We still have firmware log in device's buffer to copy.
670  *                      This function returned due the driver's circular buffer
671  *                      is full. Caller should invoke this function again as
672  *                      soon as there is space in driver's circular buffer.
673  *         false,       Device's buffer is empty.
674  */
675 static inline bool fw_log_copy(struct tegra_xhci_hcd *tegra)
676 {
677         struct device *dev = &tegra->pdev->dev;
678         struct circ_buf *circ = &tegra->log.circ;
679         int head, tail;
680         int buffer_len, copy_len;
681         struct log_entry *entry;
682         struct log_entry *first = tegra->log.virt_addr;
683
684         while (fw_log_available(tegra)) {
685
686                 /* calculate maximum contiguous driver buffer length */
687                 head = circ->head;
688                 tail = ACCESS_ONCE(circ->tail);
689                 buffer_len = CIRC_SPACE_TO_END(head, tail, CIRC_BUF_SIZE);
690                 /* round down to FW_LOG_SIZE */
691                 buffer_len -= (buffer_len % FW_LOG_SIZE);
692                 if (!buffer_len)
693                         return true; /* log available but no space left */
694
695                 /* calculate maximum contiguous log copy length */
696                 entry = tegra->log.dequeue;
697                 copy_len = 0;
698                 do {
699                         if (tegra->log.seq != entry->sequence_no) {
700                                 dev_warn(dev,
701                                 "%s: discontinuous seq no, expect %u get %u\n",
702                                 __func__, tegra->log.seq, entry->sequence_no);
703                         }
704                         tegra->log.seq = entry->sequence_no + 1;
705
706                         copy_len += FW_LOG_SIZE;
707                         buffer_len -= FW_LOG_SIZE;
708                         if (!buffer_len)
709                                 break; /* no space left */
710                         entry = fw_log_next(&tegra->log, entry);
711                 } while ((entry->owner == DRIVER) && (entry != first));
712
713                 memcpy(&circ->buf[head], tegra->log.dequeue, copy_len);
714                 memset(tegra->log.dequeue, 0, copy_len);
715                 circ->head = (circ->head + copy_len) & (CIRC_BUF_SIZE - 1);
716
717                 mb();
718
719                 fw_log_update_deq_pointer(&tegra->log, copy_len/FW_LOG_SIZE);
720
721                 dev_dbg(dev, "copied %d entries, new dequeue 0x%p\n",
722                                 copy_len/FW_LOG_SIZE, tegra->log.dequeue);
723                 wake_up_interruptible(&tegra->log.read_wait);
724         }
725
726         return false;
727 }
728
729 static int fw_log_thread(void *data)
730 {
731         struct tegra_xhci_hcd *tegra = data;
732         struct device *dev = &tegra->pdev->dev;
733         struct circ_buf *circ = &tegra->log.circ;
734         bool logs_left;
735
736         dev_dbg(dev, "start firmware log thread\n");
737
738         do {
739                 mutex_lock(&tegra->log.mutex);
740                 if (circ_buffer_full(circ)) {
741                         mutex_unlock(&tegra->log.mutex);
742                         dev_info(dev, "%s: circ buffer full\n", __func__);
743                         wait_event_interruptible(tegra->log.write_wait,
744                             kthread_should_stop() || !circ_buffer_full(circ));
745                         mutex_lock(&tegra->log.mutex);
746                 }
747
748                 logs_left = fw_log_copy(tegra);
749                 mutex_unlock(&tegra->log.mutex);
750
751                 /* relax if no logs left  */
752                 if (!logs_left)
753                         wait_event_interruptible_timeout(tegra->log.intr_wait,
754                                 fw_log_available(tegra), FW_LOG_THREAD_RELAX);
755         } while (!kthread_should_stop());
756
757         dev_dbg(dev, "stop firmware log thread\n");
758         return 0;
759 }
760
761 static inline bool circ_buffer_empty(struct circ_buf *circ)
762 {
763         return (CIRC_CNT(circ->head, circ->tail, CIRC_BUF_SIZE) == 0);
764 }
765
766 static ssize_t fw_log_file_read(struct file *file, char __user *buf,
767                 size_t count, loff_t *offp)
768 {
769         struct tegra_xhci_hcd *tegra = file->private_data;
770         struct platform_device *pdev = tegra->pdev;
771         struct circ_buf *circ = &tegra->log.circ;
772         int head, tail;
773         size_t n = 0;
774         int s;
775
776         mutex_lock(&tegra->log.mutex);
777
778         while (circ_buffer_empty(circ)) {
779                 mutex_unlock(&tegra->log.mutex);
780                 if (file->f_flags & O_NONBLOCK)
781                         return -EAGAIN; /* non-blocking read */
782
783                 dev_dbg(&pdev->dev, "%s: nothing to read\n", __func__);
784
785                 if (wait_event_interruptible(tegra->log.read_wait,
786                                 !circ_buffer_empty(circ)))
787                         return -ERESTARTSYS;
788
789                 if (mutex_lock_interruptible(&tegra->log.mutex))
790                         return -ERESTARTSYS;
791         }
792
793         while (count > 0) {
794                 head = ACCESS_ONCE(circ->head);
795                 tail = circ->tail;
796                 s = min_t(int, count,
797                                 CIRC_CNT_TO_END(head, tail, CIRC_BUF_SIZE));
798
799                 if (s > 0) {
800                         if (copy_to_user(&buf[n], &circ->buf[tail], s)) {
801                                 dev_warn(&pdev->dev, "copy_to_user failed\n");
802                                 mutex_unlock(&tegra->log.mutex);
803                                 return -EFAULT;
804                         }
805                         circ->tail = (circ->tail + s) & (CIRC_BUF_SIZE - 1);
806
807                         count -= s;
808                         n += s;
809                 } else
810                         break;
811         }
812
813         mutex_unlock(&tegra->log.mutex);
814
815         wake_up_interruptible(&tegra->log.write_wait);
816
817         dev_dbg(&pdev->dev, "%s: %d bytes\n", __func__, n);
818
819         return n;
820 }
821
822 static int fw_log_file_open(struct inode *inode, struct file *file)
823 {
824         struct tegra_xhci_hcd *tegra;
825         file->private_data = inode->i_private;
826         tegra = file->private_data;
827
828         if (test_and_set_bit(FW_LOG_FILE_OPENED, &tegra->log.flags)) {
829                 dev_info(&tegra->pdev->dev, "%s: already opened\n", __func__);
830                 return -EBUSY;
831         }
832
833         return 0;
834 }
835
836 static int fw_log_file_close(struct inode *inode, struct file *file)
837 {
838         struct tegra_xhci_hcd *tegra = file->private_data;
839
840         clear_bit(FW_LOG_FILE_OPENED, &tegra->log.flags);
841
842         return 0;
843 }
844
845 static const struct file_operations firmware_log_fops = {
846                 .open           = fw_log_file_open,
847                 .release        = fw_log_file_close,
848                 .read           = fw_log_file_read,
849                 .owner          = THIS_MODULE,
850 };
851
852 static int fw_log_init(struct tegra_xhci_hcd *tegra)
853 {
854         struct platform_device *pdev = tegra->pdev;
855         int rc = 0;
856
857         /* allocate buffer to be shared between driver and firmware */
858         tegra->log.virt_addr = dma_alloc_writecombine(&pdev->dev,
859                         FW_LOG_RING_SIZE, &tegra->log.phys_addr, GFP_KERNEL);
860
861         if (!tegra->log.virt_addr) {
862                 dev_err(&pdev->dev, "dma_alloc_writecombine() size %d failed\n",
863                                 FW_LOG_RING_SIZE);
864                 return -ENOMEM;
865         }
866
867         dev_info(&pdev->dev, "%d bytes log buffer physical 0x%u virtual 0x%p\n",
868                 FW_LOG_RING_SIZE, tegra->log.phys_addr, tegra->log.virt_addr);
869
870         memset(tegra->log.virt_addr, 0, FW_LOG_RING_SIZE);
871         tegra->log.dequeue = tegra->log.virt_addr;
872
873         tegra->log.circ.buf = vmalloc(CIRC_BUF_SIZE);
874         if (!tegra->log.circ.buf) {
875                 dev_err(&pdev->dev, "vmalloc size %d failed\n", CIRC_BUF_SIZE);
876                 rc = -ENOMEM;
877                 goto error_free_dma;
878         }
879
880         tegra->log.circ.head = 0;
881         tegra->log.circ.tail = 0;
882
883         init_waitqueue_head(&tegra->log.read_wait);
884         init_waitqueue_head(&tegra->log.write_wait);
885         init_waitqueue_head(&tegra->log.intr_wait);
886
887         mutex_init(&tegra->log.mutex);
888
889         tegra->log.path = debugfs_create_dir("tegra_xhci", NULL);
890         if (IS_ERR_OR_NULL(tegra->log.path)) {
891                 dev_warn(&pdev->dev, "debugfs_create_dir() failed\n");
892                 rc = -ENOMEM;
893                 goto error_free_mem;
894         }
895
896         tegra->log.log_file = debugfs_create_file("firmware_log",
897                         S_IRUGO, tegra->log.path, tegra, &firmware_log_fops);
898         if ((!tegra->log.log_file) ||
899                         (tegra->log.log_file == ERR_PTR(-ENODEV))) {
900                 dev_warn(&pdev->dev, "debugfs_create_file() failed\n");
901                 rc = -ENOMEM;
902                 goto error_remove_debugfs_path;
903         }
904
905         tegra->log.thread = kthread_run(fw_log_thread, tegra, "xusb-fw-log");
906         if (IS_ERR(tegra->log.thread)) {
907                 dev_warn(&pdev->dev, "kthread_run() failed\n");
908                 rc = -ENOMEM;
909                 goto error_remove_debugfs_file;
910         }
911
912         set_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags);
913         return rc;
914
915 error_remove_debugfs_file:
916         debugfs_remove(tegra->log.log_file);
917 error_remove_debugfs_path:
918         debugfs_remove(tegra->log.path);
919 error_free_mem:
920         vfree(tegra->log.circ.buf);
921 error_free_dma:
922         dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
923                         tegra->log.virt_addr, tegra->log.phys_addr);
924         memset(&tegra->log, sizeof(tegra->log), 0);
925         return rc;
926 }
927
928 static void fw_log_deinit(struct tegra_xhci_hcd *tegra)
929 {
930         struct platform_device *pdev = tegra->pdev;
931
932         if (test_and_clear_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
933
934                 debugfs_remove(tegra->log.log_file);
935                 debugfs_remove(tegra->log.path);
936
937                 wake_up_interruptible(&tegra->log.read_wait);
938                 wake_up_interruptible(&tegra->log.write_wait);
939                 kthread_stop(tegra->log.thread);
940
941                 mutex_lock(&tegra->log.mutex);
942                 dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
943                         tegra->log.virt_addr, tegra->log.phys_addr);
944                 vfree(tegra->log.circ.buf);
945                 tegra->log.circ.head = tegra->log.circ.tail = 0;
946                 mutex_unlock(&tegra->log.mutex);
947
948                 mutex_destroy(&tegra->log.mutex);
949         }
950 }
951
952 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
953 {
954         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
955         struct xhci_hcd *xhci = tegra->xhci;
956         u32 reg;
957
958         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
959         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
960         xhci_info(xhci, " PAD MUX = %x\n", reg);
961         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
962         xhci_info(xhci, " PORT CAP = %x\n", reg);
963         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
964         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
965         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
966         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
967         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
968         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
969         reg = readl(tegra->padctl_base + padregs->oc_det_0);
970         xhci_info(xhci, " OC DET 0= %x\n", reg);
971         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad0_ctl2_0);
972         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
973         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad1_ctl2_0);
974         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
975         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl0_0);
976         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
977         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl0_0);
978         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
979         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl1_0);
980         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
981         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl1_0);
982         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
983         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
984         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
985         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad0_ctl0_0);
986         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
987         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad1_ctl0_0);
988         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
989         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
990 }
991
992 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
993 {
994         u32 reg;
995
996         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
997         reg |= IPFS_EN_FPCI;
998         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
999         udelay(10);
1000
1001         /* Program Bar0 Space */
1002         reg = readl(tegra->fpci_base + XUSB_CFG_4);
1003         reg |= tegra->host_phy_base;
1004         writel(reg, tegra->fpci_base + XUSB_CFG_4);
1005         usleep_range(100, 200);
1006
1007         /* Enable Bus Master */
1008         reg = readl(tegra->fpci_base + XUSB_CFG_1);
1009         reg |= 0x7;
1010         writel(reg, tegra->fpci_base + XUSB_CFG_1);
1011
1012         /* Set intr mask to enable intr assertion */
1013         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1014         reg |= IPFS_IP_INT_MASK;
1015         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1016
1017         /* Set hysteris to 0x80 */
1018         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1019 }
1020
1021 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
1022                 struct platform_device *pdev)
1023 {
1024         struct tegra_xusb_regulator_name *supply = &tegra->bdata->supply;
1025         int err = 0;
1026
1027         tegra->xusb_s3p3v_reg =
1028                         devm_regulator_get(&pdev->dev, supply->s3p3v);
1029         if (IS_ERR(tegra->xusb_s3p3v_reg)) {
1030                 dev_err(&pdev->dev, "3p3v: regulator not found: %ld."
1031                         , PTR_ERR(tegra->xusb_s3p3v_reg));
1032                 err = PTR_ERR(tegra->xusb_s3p3v_reg);
1033                 goto err_null_regulator;
1034         } else {
1035                 err = regulator_enable(tegra->xusb_s3p3v_reg);
1036                 if (err < 0) {
1037                         dev_err(&pdev->dev,
1038                                 "3p3v: regulator enable failed:%d\n", err);
1039                         goto err_null_regulator;
1040                 }
1041         }
1042
1043         tegra->xusb_s5p0v_reg = devm_regulator_get(&pdev->dev, supply->s5p0v);
1044         if (IS_ERR(tegra->xusb_s5p0v_reg)) {
1045                 dev_err(&pdev->dev, "5p0v regulator not found: %ld."
1046                         , PTR_ERR(tegra->xusb_s5p0v_reg));
1047                 err = PTR_ERR(tegra->xusb_s5p0v_reg);
1048                 goto err_put_s3p3v_reg;
1049         } else {
1050                 err = regulator_enable(tegra->xusb_s5p0v_reg);
1051                 if (err < 0) {
1052                         dev_err(&pdev->dev,
1053                                 "5p0v: regulator enable failed:%d\n", err);
1054                         goto err_put_s3p3v_reg;
1055                 }
1056         }
1057
1058         tegra->xusb_s1p8v_reg =
1059                 devm_regulator_get(&pdev->dev, supply->s1p8v);
1060         if (IS_ERR(tegra->xusb_s1p8v_reg)) {
1061                 dev_err(&pdev->dev, "1p8v regulator not found: %ld."
1062                         , PTR_ERR(tegra->xusb_s1p8v_reg));
1063                 err = PTR_ERR(tegra->xusb_s1p8v_reg);
1064                 goto err_put_s5p0v_reg;
1065         } else {
1066                 err = regulator_enable(tegra->xusb_s1p8v_reg);
1067                 if (err < 0) {
1068                         dev_err(&pdev->dev,
1069                         "1p8v: regulator enable failed:%d\n", err);
1070                         goto err_put_s5p0v_reg;
1071                 }
1072         }
1073
1074         tegra->xusb_s1p05v_reg =
1075                         devm_regulator_get(&pdev->dev, supply->s1p05v);
1076         if (IS_ERR(tegra->xusb_s1p05v_reg)) {
1077                 dev_err(&pdev->dev, "1p05v: regulator not found: %ld."
1078                         , PTR_ERR(tegra->xusb_s1p05v_reg));
1079                 err = PTR_ERR(tegra->xusb_s1p05v_reg);
1080                 goto err_put_s1p8v_reg;
1081         } else {
1082                 err = regulator_enable(tegra->xusb_s1p05v_reg);
1083                 if (err < 0) {
1084                         dev_err(&pdev->dev,
1085                         "1p05v: regulator enable failed:%d\n", err);
1086                         goto err_put_s1p8v_reg;
1087                 }
1088         }
1089
1090         if (tegra->bdata->uses_different_vbus_per_port) {
1091                 tegra->xusb_s5p0v1_reg = devm_regulator_get(&pdev->dev,
1092                                                 supply->s5p0v1);
1093                 if (IS_ERR(tegra->xusb_s5p0v1_reg)) {
1094                         dev_err(&pdev->dev, "5p0v1 regulator not found: %ld."
1095                                 , PTR_ERR(tegra->xusb_s5p0v1_reg));
1096                         err = PTR_ERR(tegra->xusb_s5p0v1_reg);
1097                         goto err_put_s1p05v_reg;
1098                 } else {
1099                         err = regulator_enable(tegra->xusb_s5p0v1_reg);
1100                         if (err < 0) {
1101                                 dev_err(&pdev->dev,
1102                                 "5p0v1: regulator enable failed:%d\n", err);
1103                                 goto err_put_s1p05v_reg;
1104                         }
1105                 }
1106
1107                 tegra->xusb_s5p0v2_reg = devm_regulator_get(&pdev->dev,
1108                                                 supply->s5p0v2);
1109                 if (IS_ERR(tegra->xusb_s5p0v2_reg)) {
1110                         dev_err(&pdev->dev, "5p0v2 regulator not found: %ld."
1111                                 , PTR_ERR(tegra->xusb_s5p0v2_reg));
1112                         err = PTR_ERR(tegra->xusb_s5p0v2_reg);
1113                         goto err_put_s1p5v1_reg;
1114                 } else {
1115                         err = regulator_enable(tegra->xusb_s5p0v2_reg);
1116                         if (err < 0) {
1117                                 dev_err(&pdev->dev,
1118                                 "5p0v2: regulator enable failed:%d\n", err);
1119                                 goto err_put_s1p5v1_reg;
1120                         }
1121                 }
1122         }
1123         return err;
1124
1125 err_put_s1p5v1_reg:
1126         if (tegra->bdata->uses_different_vbus_per_port)
1127                 regulator_disable(tegra->xusb_s5p0v1_reg);
1128 err_put_s1p05v_reg:
1129         regulator_disable(tegra->xusb_s1p05v_reg);
1130 err_put_s1p8v_reg:
1131         regulator_disable(tegra->xusb_s1p8v_reg);
1132 err_put_s5p0v_reg:
1133         regulator_disable(tegra->xusb_s5p0v_reg);
1134 err_put_s3p3v_reg:
1135         regulator_disable(tegra->xusb_s3p3v_reg);
1136 err_null_regulator:
1137         tegra->xusb_s5p0v_reg = NULL;
1138         tegra->xusb_s5p0v1_reg = NULL;
1139         tegra->xusb_s5p0v2_reg = NULL;
1140         tegra->xusb_s1p05v_reg = NULL;
1141         tegra->xusb_s3p3v_reg = NULL;
1142         tegra->xusb_s1p8v_reg = NULL;
1143         return err;
1144 }
1145
1146 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
1147 {
1148         regulator_disable(tegra->xusb_s1p05v_reg);
1149         regulator_disable(tegra->xusb_s1p8v_reg);
1150         regulator_disable(tegra->xusb_s5p0v_reg);
1151         regulator_disable(tegra->xusb_s3p3v_reg);
1152         if (tegra->bdata->uses_different_vbus_per_port) {
1153                 regulator_disable(tegra->xusb_s5p0v1_reg);
1154                 regulator_disable(tegra->xusb_s5p0v2_reg);
1155         }
1156
1157         tegra->xusb_s1p05v_reg = NULL;
1158         tegra->xusb_s1p8v_reg = NULL;
1159         tegra->xusb_s5p0v_reg = NULL;
1160         tegra->xusb_s5p0v1_reg = NULL;
1161         tegra->xusb_s5p0v2_reg = NULL;
1162         tegra->xusb_s3p3v_reg = NULL;
1163 }
1164
1165 /*
1166  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
1167  * are under hardware control
1168  */
1169 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
1170 {
1171         struct platform_device *pdev = tegra->pdev;
1172         int err = 0;
1173
1174         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
1175         if (IS_ERR(tegra->plle_clk)) {
1176                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
1177                 err = PTR_ERR(tegra->plle_clk);
1178                 return err;
1179         }
1180         err = clk_enable(tegra->plle_clk);
1181         if (err) {
1182                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
1183                         __func__);
1184                 return err;
1185         }
1186
1187         return err;
1188 }
1189
1190 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
1191 {
1192         clk_disable(tegra->plle_clk);
1193         tegra->plle_clk = NULL;
1194 }
1195
1196 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
1197 {
1198         struct platform_device *pdev = tegra->pdev;
1199         int err = 0;
1200
1201         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
1202         if (IS_ERR(tegra->emc_clk)) {
1203                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
1204                 return PTR_ERR(tegra->emc_clk);
1205         }
1206
1207         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1208                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
1209                 if (IS_ERR(tegra->pll_re_vco_clk)) {
1210                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
1211                         err = PTR_ERR(tegra->pll_re_vco_clk);
1212                         goto get_pll_re_vco_clk_failed;
1213                 }
1214         }
1215
1216         /* get the clock handle of 120MHz clock source */
1217         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
1218         if (IS_ERR(tegra->pll_u_480M)) {
1219                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
1220                 err = PTR_ERR(tegra->pll_u_480M);
1221                 goto get_pll_u_480M_failed;
1222         }
1223
1224         /* get the clock handle of 12MHz clock source */
1225         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1226         if (IS_ERR(tegra->clk_m)) {
1227                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
1228                 err = PTR_ERR(tegra->clk_m);
1229                 goto clk_get_clk_m_failed;
1230         }
1231
1232         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
1233         if (IS_ERR(tegra->ss_src_clk)) {
1234                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
1235                 err = PTR_ERR(tegra->ss_src_clk);
1236                 tegra->ss_src_clk = NULL;
1237                 goto get_ss_src_clk_failed;
1238         }
1239
1240         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
1241         if (IS_ERR(tegra->host_clk)) {
1242                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
1243                 err = PTR_ERR(tegra->host_clk);
1244                 tegra->host_clk = NULL;
1245                 goto get_host_clk_failed;
1246         }
1247
1248         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
1249         if (IS_ERR(tegra->ss_clk)) {
1250                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
1251                 err = PTR_ERR(tegra->ss_clk);
1252                 tegra->ss_clk = NULL;
1253                 goto get_ss_clk_failed;
1254         }
1255
1256         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1257                 err = clk_enable(tegra->pll_re_vco_clk);
1258                 if (err) {
1259                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
1260                         goto enable_pll_re_vco_clk_failed;
1261                 }
1262         }
1263         return 0;
1264
1265 enable_pll_re_vco_clk_failed:
1266         tegra->ss_clk = NULL;
1267
1268 get_ss_clk_failed:
1269         tegra->host_clk = NULL;
1270
1271 get_host_clk_failed:
1272         tegra->ss_src_clk = NULL;
1273
1274 get_ss_src_clk_failed:
1275         tegra->clk_m = NULL;
1276
1277 clk_get_clk_m_failed:
1278         tegra->pll_u_480M = NULL;
1279
1280 get_pll_u_480M_failed:
1281         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1282                 tegra->pll_re_vco_clk = NULL;
1283
1284 get_pll_re_vco_clk_failed:
1285         tegra->emc_clk = NULL;
1286
1287         return err;
1288 }
1289
1290 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
1291 {
1292         clk_disable(tegra->ss_clk);
1293         clk_disable(tegra->host_clk);
1294         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1295                 clk_disable(tegra->pll_re_vco_clk);
1296         tegra->ss_clk = NULL;
1297         tegra->host_clk = NULL;
1298         tegra->ss_src_clk = NULL;
1299         tegra->clk_m = NULL;
1300         tegra->pll_u_480M = NULL;
1301         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1302                 tegra->pll_re_vco_clk = NULL;
1303 }
1304
1305 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
1306         bool enable)
1307 {
1308         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1309         u32 reg;
1310
1311         /* Issue is only applicable for T114 */
1312         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
1313                 return;
1314
1315         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1316                 reg = readl(tegra->padctl_base +
1317                         padregs->iophy_misc_pad_p0_ctl3_0);
1318                 if (enable) {
1319                         reg &= ~RX_IDLE_MODE;
1320                         reg |= RX_IDLE_MODE_OVRD;
1321                 } else {
1322                         reg |= RX_IDLE_MODE;
1323                         reg &= ~RX_IDLE_MODE_OVRD;
1324                 }
1325                 writel(reg, tegra->padctl_base +
1326                         padregs->iophy_misc_pad_p0_ctl3_0);
1327         }
1328
1329         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1330                 reg = readl(tegra->padctl_base +
1331                         padregs->iophy_misc_pad_p1_ctl3_0);
1332                 if (enable) {
1333                         reg &= ~RX_IDLE_MODE;
1334                         reg |= RX_IDLE_MODE_OVRD;
1335                 } else {
1336                         reg |= RX_IDLE_MODE;
1337                         reg &= ~RX_IDLE_MODE_OVRD;
1338                 }
1339                 writel(reg, tegra->padctl_base +
1340                         padregs->iophy_misc_pad_p1_ctl3_0);
1341
1342                 /* SATA lane also if USB3_SS port1 mapped to it */
1343                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
1344                                 tegra->bdata->lane_owner & BIT(0)) {
1345                         reg = readl(tegra->padctl_base +
1346                                 padregs->iophy_misc_pad_s0_ctl3_0);
1347                         if (enable) {
1348                                 reg &= ~RX_IDLE_MODE;
1349                                 reg |= RX_IDLE_MODE_OVRD;
1350                         } else {
1351                                 reg |= RX_IDLE_MODE;
1352                                 reg &= ~RX_IDLE_MODE_OVRD;
1353                         }
1354                         writel(reg, tegra->padctl_base +
1355                                 padregs->iophy_misc_pad_s0_ctl3_0);
1356                 }
1357         }
1358 }
1359
1360 /* Enable ss clk, host clk, falcon clk,
1361  * fs clk, dev clk, plle and refplle
1362  */
1363
1364 static int
1365 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
1366                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
1367 {
1368         int ret = 0;
1369         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
1370         int fw_req_rate = rate, cur_rate;
1371
1372         /* Do not handle clock change as needed for HS disconnect issue */
1373         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1374                 *sw_resp = fw_req_rate | (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
1375                 return ret;
1376         }
1377
1378         /* frequency request from firmware is in KHz.
1379          * Convert it to MHz
1380          */
1381
1382         /* get current rate of clock */
1383         cur_rate = clk_get_rate(clk_handle);
1384         cur_rate /= 1000;
1385
1386         if (fw_req_rate == cur_rate) {
1387                 cmd_ack = MBOX_CMD_ACK;
1388                 *sw_resp = fw_req_rate;
1389         } else {
1390
1391                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
1392                         /* Change SS clock source to CLK_M at 12MHz */
1393                         clk_set_parent(clk_handle, tegra->clk_m);
1394                         clk_set_rate(clk_handle, fw_req_rate * 1000);
1395
1396                         /* save leakage power when SS freq is being decreased */
1397                         tegra_xhci_rx_idle_mode_override(tegra, true);
1398                 } else if (clk_handle == tegra->ss_src_clk &&
1399                                 fw_req_rate == 120000) {
1400                         /* Change SS clock source to HSIC_480 at 120MHz */
1401                         clk_set_rate(clk_handle,  3000 * 1000);
1402                         clk_set_parent(clk_handle, tegra->pll_u_480M);
1403
1404                         /* clear ovrd bits when SS freq is being increased */
1405                         tegra_xhci_rx_idle_mode_override(tegra, false);
1406                 }
1407
1408                 *sw_resp = clk_get_rate(clk_handle);
1409                 *sw_resp /= 1000;
1410
1411                 if (*sw_resp != fw_req_rate) {
1412                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
1413                                 cur_rate, fw_req_rate);
1414                         cmd_ack = MBOX_CMD_NACK;
1415                 }
1416         }
1417         *sw_resp |= (cmd_ack << MBOX_CMD_SHIFT);
1418         return ret;
1419 }
1420
1421 static void tegra_xhci_save_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
1422         u8 port)
1423 {
1424         struct xhci_hcd *xhci = tegra->xhci;
1425         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1426         u32 offset;
1427         u32 reg;
1428
1429         xhci_info(xhci, "saving dfe_cntl and ctle context for port %d\n", port);
1430
1431         /* if port1 is mapped to SATA lane then read from SATA register */
1432         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1433                         tegra->bdata->lane_owner & BIT(0))
1434                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1435         else
1436                 offset = port ? padregs->iophy_misc_pad_p1_ctl6_0 :
1437                                 padregs->iophy_misc_pad_p0_ctl6_0;
1438
1439         /* save tap1_val[] for the port for dfe_cntl */
1440         reg = readl(tegra->padctl_base + offset);
1441         reg &= ~(0xff << 16);
1442         reg |= (0x32 << 16);
1443         writel(reg, tegra->padctl_base + offset);
1444
1445         reg = readl(tegra->padctl_base + offset);
1446         tegra->sregs.tap1_val[port] = ((reg & (0x1f << 24)) >> 24);
1447
1448         /* save amp_val[] for the port for dfe_cntl */
1449         reg = readl(tegra->padctl_base + offset);
1450         reg &= ~(0xff << 16);
1451         reg |= (0x33 << 16);
1452         writel(reg, tegra->padctl_base + offset);
1453
1454         reg = readl(tegra->padctl_base + offset);
1455         tegra->sregs.amp_val[port] = ((reg & (0x7f << 24)) >> 24);
1456
1457         /* save ctle_z_val[] for the port for ctle */
1458         reg = readl(tegra->padctl_base + offset);
1459         reg &= ~(0xff << 16);
1460         reg |= (0x20 << 16);
1461         writel(reg, tegra->padctl_base + offset);
1462
1463         reg = readl(tegra->padctl_base + offset);
1464         tegra->sregs.ctle_z_val[port] = ((reg & (0x3f << 24)) >> 24);
1465
1466         /* save ctle_g_val[] for the port for ctle */
1467         reg = readl(tegra->padctl_base + offset);
1468         reg &= ~(0xff << 16);
1469         reg |= (0x21 << 16);
1470         writel(reg, tegra->padctl_base + offset);
1471
1472         reg = readl(tegra->padctl_base + offset);
1473         tegra->sregs.ctle_g_val[port] = ((reg & (0x3f << 24)) >> 24);
1474         tegra->dfe_ctle_ctx_saved = true;
1475 }
1476
1477 static void tegra_xhci_restore_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
1478         u8 port)
1479 {
1480         struct xhci_hcd *xhci = tegra->xhci;
1481         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1482         u32 ctl4_offset, ctl2_offset;
1483         u32 reg;
1484
1485         /* don't restore if not saved */
1486         if (tegra->dfe_ctle_ctx_saved == false)
1487                 return;
1488
1489         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1490                         padregs->iophy_usb3_pad0_ctl4_0;
1491         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1492                         padregs->iophy_usb3_pad0_ctl2_0;
1493
1494         xhci_info(xhci, "restoring dfe_cntl/ctle context of port %d\n", port);
1495
1496         /* restore dfe_cntl for the port */
1497         reg = readl(tegra->padctl_base + ctl4_offset);
1498         reg &= ~((0x7f << 16) | (0x1f << 24));
1499         reg |= ((tegra->sregs.amp_val[port] << 16) |
1500                 (tegra->sregs.tap1_val[port] << 24));
1501         writel(reg, tegra->padctl_base + ctl4_offset);
1502
1503         /* restore ctle for the port */
1504         reg = readl(tegra->padctl_base + ctl2_offset);
1505         reg &= ~((0x3f << 8) | (0x3f << 16));
1506         reg |= ((tegra->sregs.ctle_g_val[port] << 8) |
1507                 (tegra->sregs.ctle_z_val[port] << 16));
1508         writel(reg, tegra->padctl_base + ctl2_offset);
1509 }
1510
1511 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
1512         u8 port)
1513 {
1514         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1515         u32 reg;
1516
1517         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1518         reg &= ~USB2_ULPI_PAD;
1519         reg |= USB2_ULPI_PAD_OWNER_XUSB;
1520         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1521
1522         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1523         reg &= ~USB2_ULPI_PORT_CAP;
1524         reg |= (tegra->bdata->ulpicap << 24);
1525         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1526         /* FIXME: Program below when more details available
1527          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
1528          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
1529          */
1530 }
1531
1532 static void tegra_xhci_program_hsic_pad(struct tegra_xhci_hcd *tegra,
1533         u8 port)
1534 {
1535         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1536         u32 ctl0_offset;
1537         u32 reg;
1538
1539         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1540         reg &= ~(port ? USB2_HSIC_PAD_PORT1 : USB2_HSIC_PAD_PORT0);
1541         reg |= port ? USB2_HSIC_PAD_P1_OWNER_XUSB :
1542                         USB2_HSIC_PAD_P0_OWNER_XUSB;
1543         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1544
1545         ctl0_offset = port ? padregs->usb2_hsic_pad1_ctl0_0 :
1546                         padregs->usb2_hsic_pad0_ctl0_0;
1547
1548         reg = readl(tegra->padctl_base + ctl0_offset);
1549         reg &= ~(HSIC_TX_SLEWP | HSIC_TX_SLEWN);
1550         writel(reg, tegra->padctl_base + ctl0_offset);
1551
1552         /* FIXME Program below when more details available
1553          * XUSB_PADCTL_HSIC_PAD0_CTL_0_0
1554          * XUSB_PADCTL_HSIC_PAD0_CTL_1_0
1555          * XUSB_PADCTL_HSIC_PAD0_CTL_2_0
1556          * XUSB_PADCTL_HSIC_PAD1_CTL_0_0
1557          * XUSB_PADCTL_HSIC_PAD1_CTL_1_0
1558          * XUSB_PADCTL_HSIC_PAD1_CTL_2_0
1559          * XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0
1560          */
1561 }
1562
1563 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
1564         u8 port)
1565 {
1566         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1567         u32 reg;
1568         u32 ctl0_offset, ctl1_offset;
1569
1570         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1571         reg &= ~USB2_OTG_PAD_PORT_MASK(port);
1572         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
1573         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1574
1575         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1576         reg &= ~USB2_PORT_CAP_MASK(port);
1577         reg |= USB2_PORT_CAP_HOST(port);
1578         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1579
1580         /*
1581          * Modify only the bits which belongs to the port
1582          * and enable respective VBUS_PAD for the port
1583          */
1584         if (tegra->bdata->uses_external_pmic == false) {
1585                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1586                 reg &= ~(port == 2 ? OC_DET_VBUS_ENABLE2_OC_MAP :
1587                         port ? OC_DET_VBUS_ENABLE1_OC_MAP :
1588                                 OC_DET_VBUS_ENABLE0_OC_MAP);
1589
1590                 reg |= (port == 2) ? OC_DET_VBUS_EN2_OC_DETECTED_VBUS_PAD2 :
1591                         port ? OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1 :
1592                                 OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0;
1593                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1594         }
1595         /*
1596          * enable respective VBUS_PAD if port is mapped to any SS port
1597          */
1598         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1599         reg &= ~((port == 2) ? USB2_OC_MAP_PORT2 :
1600                 port ? USB2_OC_MAP_PORT1 : USB2_OC_MAP_PORT0);
1601         reg |= (0x4 | port) << (port * 3);
1602         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1603
1604         ctl0_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl0_0 :
1605                         port ? padregs->usb2_otg_pad1_ctl0_0 :
1606                                 padregs->usb2_otg_pad0_ctl0_0;
1607         ctl1_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl1_0 :
1608                         port ? padregs->usb2_otg_pad1_ctl1_0 :
1609                                 padregs->usb2_otg_pad0_ctl1_0;
1610
1611         reg = readl(tegra->padctl_base + ctl0_offset);
1612         reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
1613                 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
1614                 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
1615
1616         reg |= tegra->pdata->hs_slew;
1617         reg |= (port == 2) ? tegra->pdata->ls_rslew_pad2 :
1618                         port ? tegra->pdata->ls_rslew_pad1 :
1619                         tegra->pdata->ls_rslew_pad0;
1620         reg |= (port == 2) ? tegra->pdata->hs_curr_level_pad2 :
1621                         port ? tegra->pdata->hs_curr_level_pad1 :
1622                         tegra->pdata->hs_curr_level_pad0;
1623         writel(reg, tegra->padctl_base + ctl0_offset);
1624
1625         reg = readl(tegra->padctl_base + ctl1_offset);
1626         reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
1627                 | USB2_OTG_PD_CHRP_FORCE_POWERUP
1628                 | USB2_OTG_PD_DISC_FORCE_POWERUP
1629                 | USB2_OTG_PD_DR);
1630         reg |= (tegra->pdata->hs_iref_cap << 9) |
1631                 (tegra->pdata->hs_term_range_adj << 3);
1632         writel(reg, tegra->padctl_base + ctl1_offset);
1633 }
1634
1635 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
1636         u8 port)
1637 {
1638         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1639         u32 ctl2_offset, ctl4_offset, ctl5_offset;
1640         u32 reg;
1641
1642         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1643                         padregs->iophy_usb3_pad0_ctl2_0;
1644         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1645                         padregs->iophy_usb3_pad0_ctl4_0;
1646         ctl5_offset = port ? padregs->iophy_misc_pad_p1_ctl5_0 :
1647                         padregs->iophy_misc_pad_p0_ctl5_0;
1648
1649         reg = readl(tegra->padctl_base + ctl2_offset);
1650         reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
1651                 IOPHY_USB3_CDRCNTL);
1652         reg |= tegra->pdata->rx_wander | tegra->pdata->rx_eq |
1653                 tegra->pdata->cdr_cntl;
1654         writel(reg, tegra->padctl_base + ctl2_offset);
1655
1656         reg = readl(tegra->padctl_base + ctl4_offset);
1657         reg = tegra->pdata->dfe_cntl;
1658         writel(reg, tegra->padctl_base + ctl4_offset);
1659
1660         reg = readl(tegra->padctl_base + ctl5_offset);
1661         reg |= RX_QEYE_EN;
1662         writel(reg, tegra->padctl_base + ctl5_offset);
1663
1664         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1665         reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
1666         reg |= (tegra->bdata->ss_portmap &
1667                 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
1668         writel(reg, tegra->padctl_base + padregs->ss_port_map_0);
1669
1670         tegra_xhci_restore_dfe_ctle_context(tegra, port);
1671 }
1672
1673 /* This function assigns the USB ports to the controllers,
1674  * then programs the port capabilities and pad parameters
1675  * of ports assigned to XUSB after booted to OS.
1676  */
1677 void
1678 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
1679 {
1680         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1681         u32 reg, oc_bits = 0;
1682
1683         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1684         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
1685         reg |= tegra->pdata->hs_squelch_level | tegra->pdata->hs_disc_lvl;
1686         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1687
1688         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1689         reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3;
1690         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
1691         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1692
1693         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1694         reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
1695         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1696                 reg |= OC_DET_VBUS_ENABLE2_OC_MAP;
1697         writel(reg, tegra->padctl_base + padregs->oc_det_0);
1698
1699         /* check if over current seen. Clear if present */
1700         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1701                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
1702         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1703                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
1704         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1705                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
1706
1707         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1708         if (reg & oc_bits) {
1709                 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
1710                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1711
1712                 usleep_range(100, 200);
1713
1714                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1715                 if (reg & oc_bits)
1716                         xhci_info(tegra->xhci, "Over current still present\n");
1717         }
1718
1719         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1720         reg = USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1;
1721         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1722                 reg |= USB2_OC_MAP_PORT2;
1723         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1724
1725         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1726                 tegra_xhci_program_utmip_pad(tegra, 0);
1727         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1728                 tegra_xhci_program_utmip_pad(tegra, 1);
1729         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1730                 tegra_xhci_program_utmip_pad(tegra, 2);
1731
1732         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
1733                 tegra_xhci_program_ulpi_pad(tegra, 0);
1734
1735         if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P0)
1736                 tegra_xhci_program_hsic_pad(tegra, 0);
1737         if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P1)
1738                 tegra_xhci_program_hsic_pad(tegra, 1);
1739
1740         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1741                 tegra_xhci_program_ss_pad(tegra, 0);
1742         } else {
1743                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1744                 reg = readl(tegra->padctl_base +
1745                         padregs->iophy_misc_pad_p0_ctl3_0);
1746                 reg &= ~RX_IDLE_MODE;
1747                 reg |= RX_IDLE_MODE_OVRD;
1748                 writel(reg, tegra->padctl_base +
1749                         padregs->iophy_misc_pad_p0_ctl3_0);
1750         }
1751
1752         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1753                 tegra_xhci_program_ss_pad(tegra, 1);
1754         } else {
1755                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1756                 reg = readl(tegra->padctl_base +
1757                         padregs->iophy_misc_pad_p1_ctl3_0);
1758                 reg &= ~RX_IDLE_MODE;
1759                 reg |= RX_IDLE_MODE_OVRD;
1760                 writel(reg, tegra->padctl_base +
1761                         padregs->iophy_misc_pad_p1_ctl3_0);
1762
1763                 /* SATA lane also if USB3_SS port1 mapped to it but unused */
1764                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
1765                                 tegra->bdata->lane_owner & BIT(0)) {
1766                         reg = readl(tegra->padctl_base +
1767                                 padregs->iophy_misc_pad_s0_ctl3_0);
1768                         reg &= ~RX_IDLE_MODE;
1769                         reg |= RX_IDLE_MODE_OVRD;
1770                         writel(reg, tegra->padctl_base +
1771                                 padregs->iophy_misc_pad_s0_ctl3_0);
1772                 }
1773         }
1774         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
1775                 tegra_xhci_setup_gpio_for_ss_lane(tegra);
1776                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
1777         }
1778 }
1779
1780 /* This function read XUSB registers and stores in device context */
1781 static void
1782 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
1783 {
1784
1785         /* a. Save the IPFS registers */
1786         tegra->sregs.msi_bar_sz =
1787                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
1788
1789         tegra->sregs.msi_axi_barst =
1790                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
1791
1792         tegra->sregs.msi_fpci_barst =
1793                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
1794
1795         tegra->sregs.msi_vec0 =
1796                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
1797
1798         tegra->sregs.msi_en_vec0 =
1799                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
1800
1801         tegra->sregs.fpci_error_masks =
1802                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
1803
1804         tegra->sregs.intr_mask =
1805                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1806
1807         tegra->sregs.ipfs_intr_enable =
1808                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
1809
1810         tegra->sregs.ufpci_config =
1811                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
1812
1813         tegra->sregs.clkgate_hysteresis =
1814                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1815
1816         tegra->sregs.xusb_host_mccif_fifo_cntrl =
1817                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
1818
1819         /* b. Save the CFG registers */
1820
1821         tegra->sregs.hs_pls =
1822                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
1823
1824         tegra->sregs.fs_pls =
1825                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
1826
1827         tegra->sregs.hs_fs_speed =
1828                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
1829
1830         tegra->sregs.hs_fs_pp =
1831                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
1832
1833         tegra->sregs.cfg_aru =
1834                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
1835
1836         tegra->sregs.cfg_order =
1837                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
1838
1839         tegra->sregs.cfg_fladj =
1840                 readl(tegra->fpci_base + XUSB_CFG_24);
1841
1842         tegra->sregs.cfg_sid =
1843                 readl(tegra->fpci_base + XUSB_CFG_16);
1844 }
1845
1846 /* This function restores XUSB registers from device context */
1847 static void
1848 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
1849 {
1850         /* Restore Cfg registers */
1851         writel(tegra->sregs.hs_pls,
1852                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
1853
1854         writel(tegra->sregs.fs_pls,
1855                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
1856
1857         writel(tegra->sregs.hs_fs_speed,
1858                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
1859
1860         writel(tegra->sregs.hs_fs_pp,
1861                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
1862
1863         writel(tegra->sregs.cfg_aru,
1864                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
1865
1866         writel(tegra->sregs.cfg_order,
1867                 tegra->fpci_base + XUSB_CFG_FPCICFG);
1868
1869         writel(tegra->sregs.cfg_fladj,
1870                 tegra->fpci_base + XUSB_CFG_24);
1871
1872         writel(tegra->sregs.cfg_sid,
1873                 tegra->fpci_base + XUSB_CFG_16);
1874
1875         /* Restore IPFS registers */
1876
1877         writel(tegra->sregs.msi_bar_sz,
1878                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
1879
1880         writel(tegra->sregs.msi_axi_barst,
1881                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
1882
1883         writel(tegra->sregs.msi_fpci_barst,
1884                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
1885
1886         writel(tegra->sregs.msi_vec0,
1887                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
1888
1889         writel(tegra->sregs.msi_en_vec0,
1890                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
1891
1892         writel(tegra->sregs.fpci_error_masks,
1893                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
1894
1895         writel(tegra->sregs.intr_mask,
1896                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1897
1898         writel(tegra->sregs.ipfs_intr_enable,
1899                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
1900
1901         writel(tegra->sregs.ufpci_config,
1902                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
1903
1904         writel(tegra->sregs.clkgate_hysteresis,
1905                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1906
1907         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
1908                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
1909 }
1910
1911 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
1912 {
1913         struct platform_device *pdev = tegra->pdev;
1914         u32 reg, timeout = 0xff, cmd;
1915
1916         mutex_lock(&tegra->mbox_lock);
1917
1918         do {
1919                 writel(MBOX_OWNER_SW,
1920                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
1921                 reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
1922                 usleep_range(10, 20);
1923         } while (reg != MBOX_OWNER_SW && timeout--);
1924
1925         if ((timeout == 0) && (reg != MBOX_OWNER_SW)) {
1926                 dev_err(&pdev->dev, "Failed to set mbox message owner ID\n");
1927                 mutex_unlock(&tegra->mbox_lock);
1928                 return;
1929         }
1930
1931         writel((MBOX_CMD_MSG_ENABLED << MBOX_CMD_SHIFT),
1932                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
1933
1934         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1935         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
1936         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1937
1938         mutex_unlock(&tegra->mbox_lock);
1939 }
1940
1941 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
1942 {
1943         struct platform_device *pdev = tegra->pdev;
1944         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
1945         u32 phys_addr_lo;
1946         u32 HwReg;
1947         u16 nblocks;
1948         time_t fw_time;
1949         struct tm fw_tm;
1950         u8 hc_caplength;
1951         u32 usbsts, count = 0xff;
1952         struct xhci_cap_regs __iomem *cap_regs;
1953         struct xhci_op_regs __iomem *op_regs;
1954
1955         /* enable mbox interrupt */
1956         writel(readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD) | MBOX_INT_EN,
1957                 tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1958
1959         /* First thing, reset the ARU. By the time we get to
1960          * loading boot code below, reset would be complete.
1961          * alternatively we can busy wait on rst pending bit.
1962          */
1963         /* Don't reset during ELPG/LP0 exit path */
1964         if (resetARU) {
1965                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
1966                 usleep_range(1000, 2000);
1967         }
1968
1969         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
1970                 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
1971                                 csb_read(tegra, XUSB_FALC_CPUCTL));
1972                 return 0;
1973         }
1974
1975         /* update the phys_log_buffer and total_entries here */
1976         cfg_tbl->phys_addr_log_buffer = tegra->log.phys_addr;
1977         cfg_tbl->total_log_entries = FW_LOG_COUNT;
1978
1979         phys_addr_lo = tegra->firmware.dma;
1980         phys_addr_lo += sizeof(struct cfgtbl);
1981
1982         /* Program the size of DFI into ILOAD_ATTR */
1983         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
1984
1985         /* Boot code of the firmware reads the ILOAD_BASE_LO register
1986          * to get to the start of the dfi in system memory.
1987          */
1988         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
1989
1990         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
1991         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
1992
1993         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
1994         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
1995
1996         /* Invalidate L2IMEM. */
1997         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
1998
1999         /* Initiate fetch of Bootcode from system memory into L2IMEM.
2000          * Program BootCode location and size in system memory.
2001          */
2002         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
2003                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
2004                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
2005         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
2006                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
2007                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
2008         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
2009
2010         /* Trigger L2IMEM Load operation. */
2011         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
2012
2013         /* Setup Falcon Auto-fill */
2014         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
2015         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
2016                 nblocks += 1;
2017         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
2018
2019         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
2020         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
2021                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
2022         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
2023
2024         csb_write(tegra, XUSB_FALC_DMACTL, 0);
2025         msleep(50);
2026
2027         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
2028
2029         /* Start Falcon CPU */
2030         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
2031         usleep_range(1000, 2000);
2032
2033         fw_time = cfg_tbl->fwimg_created_time;
2034         time_to_tm(fw_time, 0, &fw_tm);
2035         dev_info(&pdev->dev,
2036                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
2037                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
2038                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
2039                 fw_tm.tm_min, fw_tm.tm_sec,
2040                 csb_read(tegra, XUSB_FALC_CPUCTL));
2041
2042         /* return fail if firmware status is not good */
2043         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
2044                 return -EFAULT;
2045
2046         cap_regs = IO_ADDRESS(tegra->host_phy_base);
2047         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
2048         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
2049
2050         /* wait for USBSTS_CNR to get set */
2051         do {
2052                 usbsts = ioread32(&op_regs->status);
2053         } while ((usbsts & STS_CNR) && count--);
2054
2055         if (!count && (usbsts & STS_CNR)) {
2056                 dev_err(&pdev->dev, "Controller not ready\n");
2057                 return -EFAULT;
2058         }
2059         return 0;
2060 }
2061
2062 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
2063         bool release)
2064 {
2065         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2066         u32 reg;
2067
2068         /* Issue is only applicable for T114 */
2069         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
2070                 return;
2071
2072         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2073         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2074                         USB2_OTG_PAD_PORT_MASK(2));
2075
2076         if (!release) {
2077                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2078                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2079                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2080                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2081                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2082                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2083         }
2084
2085         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2086 }
2087 /* SS ELPG Entry initiated by fw */
2088 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
2089 {
2090         struct xhci_hcd *xhci = tegra->xhci;
2091         u32 ret = 0;
2092
2093         must_have_sync_lock(tegra);
2094
2095         /* This is SS partition ELPG entry
2096          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
2097          */
2098
2099         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
2100          * only if it is sw initiated one
2101          */
2102
2103         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
2104          * SuperSpeed partition ELPG entry via mailbox protocol
2105          */
2106
2107         /* STEP 2: xHCI PEP driver and XUSB device mode driver
2108          * enable the XUSB wakeup interrupts for the SuperSpeed
2109          * and USB2.0 ports assigned to host.Section 4.1 Step 3
2110          */
2111         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2112
2113         /* STEP 3: xHCI PEP driver initiates the signal sequence
2114          * to enable the XUSB SSwake detection logic for the
2115          * SuperSpeed ports assigned to host.Section 4.1 Step 4
2116          */
2117         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, true);
2118
2119         /* STEP 4: System Power Management driver asserts reset
2120          * to XUSB SuperSpeed partition then disables its clocks
2121          */
2122         tegra_periph_reset_assert(tegra->ss_clk);
2123         clk_disable(tegra->ss_clk);
2124
2125         usleep_range(100, 200);
2126
2127         /* STEP 5: System Power Management driver disables the
2128          * XUSB SuperSpeed partition power rails.
2129          */
2130         debug_print_portsc(xhci);
2131
2132         /* tegra_powergate_partition also does partition reset assert */
2133         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
2134         if (ret) {
2135                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
2136                                 __func__);
2137                 /* TODO: error recovery? */
2138         }
2139         tegra->ss_pwr_gated = true;
2140
2141         /* STEP 6: xHCI PEP driver initiates the signal sequence
2142          * to enable the XUSB SSwake detection logic for the
2143          * SuperSpeed ports assigned to host.Section 4.1 Step 7
2144          */
2145         tegra_xhci_ss_vcore(tegra->bdata->portmap, true);
2146
2147         return ret;
2148 }
2149
2150 /* Host ELPG Entry */
2151 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
2152 {
2153         struct xhci_hcd *xhci = tegra->xhci;
2154         u32 ret;
2155
2156         must_have_sync_lock(tegra);
2157
2158         /* If ss is already powergated skip ss ctx save stuff */
2159         if (tegra->ss_pwr_gated) {
2160                 xhci_info(xhci, "%s: SS partition is already powergated\n",
2161                         __func__);
2162         } else {
2163                 ret = tegra_xhci_ss_elpg_entry(tegra);
2164                 if (ret) {
2165                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
2166                                 __func__, ret);
2167                         return ret;
2168                 }
2169         }
2170
2171         /* 1. IS INTR PENDING INT_PENDING=1 ? */
2172
2173         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
2174         tegra_xhci_save_xusb_ctx(tegra);
2175
2176         /* calculate rctrl_val and tctrl_val */
2177         tegra_xhci_war_for_tctrl_rctrl(tegra);
2178
2179         pmc_init(tegra, 1);
2180
2181         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2182         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2183                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2184
2185         /* STEP 4: Assert reset to host clk and disable host clk */
2186         tegra_periph_reset_assert(tegra->host_clk);
2187
2188         clk_disable(tegra->host_clk);
2189
2190         /* wait 150us */
2191         usleep_range(150, 200);
2192
2193         /* flush MC client of XUSB_HOST */
2194         tegra_powergate_mc_flush(TEGRA_POWERGATE_XUSBC);
2195
2196         /* STEP 4: Powergate host partition */
2197         /* tegra_powergate_partition also does partition reset assert */
2198         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
2199         if (ret) {
2200                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2201                         __func__, ret);
2202                 /* TODO: error handling? */
2203                 return ret;
2204         }
2205         tegra->host_pwr_gated = true;
2206
2207         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2208                 clk_disable(tegra->pll_re_vco_clk);
2209         clk_disable(tegra->emc_clk);
2210         /* set port ownership to SNPS */
2211         tegra_xhci_release_port_ownership(tegra, true);
2212
2213         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2214                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2215
2216         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
2217         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
2218                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
2219         return ret;
2220 }
2221
2222 /* SS ELPG Exit triggered by PADCTL irq */
2223 /**
2224  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
2225  *
2226  * This function must be called with tegra->sync_lock acquired.
2227  *
2228  * @tegra: xhci controller context
2229  * @return 0 for success, or error numbers
2230  */
2231 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2232 {
2233         struct xhci_hcd *xhci = tegra->xhci;
2234         int ret = 0;
2235
2236         must_have_sync_lock(tegra);
2237
2238         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
2239                         tegra->hs_wake_event || tegra->host_resume_req)) {
2240
2241                 /*
2242                  * PWR_UNGATE SS partition. XUSBA
2243                  * tegra_unpowergate_partition also does partition reset
2244                  * deassert
2245                  */
2246                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
2247                 if (ret) {
2248                         xhci_err(xhci,
2249                         "%s: could not unpowergate xusba partition %d\n",
2250                         __func__, ret);
2251                         goto out;
2252                 }
2253                 if (tegra->ss_wake_event)
2254                         tegra->ss_wake_event = false;
2255
2256         } else {
2257                 xhci_info(xhci, "%s: ss already power gated\n",
2258                         __func__);
2259                 return ret;
2260         }
2261
2262         /* Step 3: Enable clock to ss partition */
2263         clk_enable(tegra->ss_clk);
2264
2265         /* Step 4: Disable ss wake detection logic */
2266         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2267
2268         /* Step 4.1: Disable ss wake detection logic */
2269         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
2270
2271         /* wait 150us */
2272         usleep_range(150, 200);
2273
2274         /* Step 4.2: Disable ss wake detection logic */
2275         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
2276
2277         /* Step 6 Deassert reset for ss clks */
2278         tegra_periph_reset_deassert(tegra->ss_clk);
2279
2280         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
2281         tegra->ss_pwr_gated = false;
2282 out:
2283         return ret;
2284 }
2285
2286 static void ss_partition_elpg_exit_work(struct work_struct *work)
2287 {
2288         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2289                 ss_elpg_exit_work);
2290
2291         mutex_lock(&tegra->sync_lock);
2292         tegra_xhci_ss_partition_elpg_exit(tegra);
2293         mutex_unlock(&tegra->sync_lock);
2294 }
2295
2296 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
2297 static void update_remote_wakeup_ports_pmc(struct tegra_xhci_hcd *tegra)
2298 {
2299         struct xhci_hcd *xhci = tegra->xhci;
2300         u32 wake2_status;
2301
2302 #define PMC_WAKE2_STATUS        0x168
2303 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
2304
2305         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
2306
2307         if (wake2_status & PADCTL_WAKE) {
2308                 /* FIXME: This is customized for Dalmore, find a generic way */
2309                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
2310                 /* clear wake status */
2311                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
2312         }
2313
2314         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
2315                         __func__, tegra->usb3_rh_remote_wakeup_ports);
2316 }
2317
2318 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
2319 {
2320         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2321         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2322         int port, num_ports;
2323         unsigned long *remote_wakeup_ports;
2324         u32 portsc;
2325         __le32 __iomem  **port_array;
2326         unsigned char *rh;
2327         unsigned int retry = 64;
2328
2329
2330         if (hcd == xhci->shared_hcd) {
2331                 port_array = xhci->usb3_ports;
2332                 num_ports = xhci->num_usb3_ports;
2333                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
2334                 rh = "usb3 roothub";
2335         } else
2336                 return;
2337
2338         while (*remote_wakeup_ports && retry--) {
2339                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
2340                         portsc = xhci_readl(xhci, port_array[port]);
2341
2342                         if (!(portsc & PORT_CONNECT)) {
2343                                 /* nothing to do if already disconnected */
2344                                 clear_bit(port, remote_wakeup_ports);
2345                                 continue;
2346                         }
2347
2348                         if ((portsc & PORT_PLS_MASK) == XDEV_U0)
2349                                 clear_bit(port, remote_wakeup_ports);
2350                         else
2351                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
2352                                                 __func__, rh, port, portsc);
2353                 }
2354
2355                 if (*remote_wakeup_ports)
2356                         msleep(20); /* give some time, irq will direct U0 */
2357         }
2358
2359         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
2360                         *remote_wakeup_ports);
2361 }
2362
2363 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
2364 {
2365         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2366         u32 reg, utmip_rctrl_val, utmip_tctrl_val, pad_mux, portmux, portowner;
2367
2368         portmux = USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1);
2369         portowner = USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
2370                         USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2371
2372         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2373                 portmux |= USB2_OTG_PAD_PORT_MASK(2);
2374                 portowner |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2375         }
2376
2377         /* Use xusb padctl space only when xusb owns all UTMIP port */
2378         pad_mux = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2379         if ((pad_mux & portmux) == portowner) {
2380                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
2381                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
2382                  */
2383                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2384                 reg &= ~((1 << 12) | (1 << 13));
2385                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2386
2387                 /* wait 20us */
2388                 usleep_range(20, 30);
2389
2390                 /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
2391                  * :: TCTRL and RCTRL
2392                  */
2393                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl1_0);
2394                 utmip_rctrl_val = RCTRL(reg);
2395                 utmip_tctrl_val = TCTRL(reg);
2396
2397                 /*
2398                  * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
2399                  * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
2400                  */
2401                 pmc_data.utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
2402                 pmc_data.utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
2403
2404                 xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
2405                         pmc_data.utmip_rctrl_val, pmc_data.utmip_tctrl_val);
2406
2407                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
2408                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
2409                  */
2410                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2411                 reg |= (1 << 13);
2412                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2413
2414                 /* Program these values into PMC regiseter and program the
2415                  * PMC override
2416                  */
2417                 reg = PMC_TCTRL_VAL(pmc_data.utmip_tctrl_val) |
2418                         PMC_RCTRL_VAL(pmc_data.utmip_rctrl_val);
2419                 tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG,
2420                         0xffffffff, reg);
2421
2422                 reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
2423                 tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
2424         } else {
2425                 /* TODO use common PMC API to use SNPS register space */
2426         }
2427 }
2428
2429 /* Host ELPG Exit triggered by PADCTL irq */
2430 /**
2431  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
2432  *
2433  * This function must be called with tegra->sync_lock acquired.
2434  *
2435  * @tegra: xhci controller context
2436  * @return 0 for success, or error numbers
2437  */
2438 static int
2439 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2440 {
2441         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2442         struct xhci_hcd *xhci = tegra->xhci;
2443         int ret = 0;
2444
2445         must_have_sync_lock(tegra);
2446
2447         if (!tegra->hc_in_elpg)
2448                 return 0;
2449
2450         clk_enable(tegra->emc_clk);
2451         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2452                 clk_enable(tegra->pll_re_vco_clk);
2453
2454         if (tegra->lp0_exit) {
2455                 u32 reg, oc_bits = 0;
2456
2457                 /* Issue is only applicable for T114 */
2458                 if (XUSB_DEVICE_ID_T114 == tegra->device_id)
2459                         tegra_xhci_war_for_tctrl_rctrl(tegra);
2460                 /* check if over current seen. Clear if present */
2461                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2462                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2463                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2464                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2465                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2466                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2467
2468                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2469                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
2470                 if (reg & oc_bits) {
2471                         xhci_info(xhci, "Over current detected. Clearing...\n");
2472                         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2473
2474                         usleep_range(100, 200);
2475
2476                         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2477                         if (reg & oc_bits)
2478                                 xhci_info(xhci, "Over current still present\n");
2479                 }
2480                 tegra_xhci_padctl_portmap_and_caps(tegra);
2481                 /* release clamps post deassert */
2482                 tegra->lp0_exit = false;
2483         }
2484
2485         /* Clear FLUSH_ENABLE of MC client */
2486         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
2487
2488         /* set port ownership back to xusb */
2489         tegra_xhci_release_port_ownership(tegra, false);
2490
2491         /*
2492          * PWR_UNGATE Host partition. XUSBC
2493          * tegra_unpowergate_partition also does partition reset deassert
2494          */
2495         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
2496         if (ret) {
2497                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2498                         __func__, ret);
2499                 goto out;
2500         }
2501         clk_enable(tegra->host_clk);
2502
2503         /* Step 4: Deassert reset to host partition clk */
2504         tegra_periph_reset_deassert(tegra->host_clk);
2505
2506         /* Step 6.1: IPFS and XUSB BAR initialization */
2507         tegra_xhci_cfg(tegra);
2508
2509         /* Step 6.2: IPFS and XUSB related restore */
2510         tegra_xhci_restore_ctx(tegra);
2511
2512         /* Step 8: xhci spec related ctx restore
2513          * will be done in xhci_resume().Do it here.
2514          */
2515
2516         tegra_xhci_ss_partition_elpg_exit(tegra);
2517
2518         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
2519         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
2520                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
2521                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
2522         }
2523
2524         /* clear ovrd bits */
2525         tegra_xhci_rx_idle_mode_override(tegra, false);
2526
2527         /* Load firmware */
2528         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
2529                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
2530                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
2531                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
2532                         __func__,
2533                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
2534                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
2535                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
2536                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
2537                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
2538                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
2539                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
2540                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
2541                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
2542         debug_print_portsc(xhci);
2543
2544         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
2545         if (ret < 0) {
2546                 xhci_err(xhci, "%s: failed to load firmware %d\n",
2547                         __func__, ret);
2548                 goto out;
2549         }
2550
2551         pmc_init(tegra, 0);
2552
2553         tegra->hc_in_elpg = false;
2554         ret = xhci_resume(tegra->xhci, 0);
2555         if (ret) {
2556                 xhci_err(xhci, "%s: could not resume right %d\n",
2557                                 __func__, ret);
2558                 goto out;
2559         }
2560
2561         update_remote_wakeup_ports_pmc(tegra);
2562
2563         if (tegra->hs_wake_event)
2564                 tegra->hs_wake_event = false;
2565
2566         if (tegra->host_resume_req)
2567                 tegra->host_resume_req = false;
2568
2569         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
2570                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
2571
2572         tegra->host_pwr_gated = false;
2573 out:
2574         return ret;
2575 }
2576
2577 static void host_partition_elpg_exit_work(struct work_struct *work)
2578 {
2579         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2580                 host_elpg_exit_work);
2581
2582         mutex_lock(&tegra->sync_lock);
2583         tegra_xhci_host_partition_elpg_exit(tegra);
2584         mutex_unlock(&tegra->sync_lock);
2585 }
2586
2587 /* Mailbox handling function. This function handles requests
2588  * from firmware and communicates with clock and powergating
2589  * module to alter clock rates and to power gate/ungate xusb
2590  * partitions.
2591  *
2592  * Following is the structure of mailbox messages.
2593  * bit 31:28 - msg type
2594  * bits 27:0 - mbox data
2595  * FIXME:  Check if we can just call clock functions like below
2596  * or should we schedule it for calling later ?
2597  */
2598
2599 static void
2600 tegra_xhci_process_mbox_message(struct work_struct *work)
2601 {
2602         u32 sw_resp = 0, cmd, data_in, fw_msg;
2603         int ret = 0;
2604         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2605                                         mbox_work);
2606         struct xhci_hcd *xhci = tegra->xhci;
2607         unsigned int freq_khz;
2608
2609         mutex_lock(&tegra->mbox_lock);
2610
2611         /* get the owner id */
2612         tegra->mbox_owner = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2613         tegra->mbox_owner &= MBOX_OWNER_ID_MASK;
2614
2615         /* get the mbox message from firmware */
2616         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
2617
2618         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2619         if (data_in) {
2620                 mutex_unlock(&tegra->mbox_lock);
2621                 return;
2622         }
2623
2624         /* get cmd type and cmd data */
2625         tegra->cmd_type = (fw_msg & MBOX_CMD_TYPE_MASK) >> MBOX_CMD_SHIFT;
2626         tegra->cmd_data = (fw_msg & MBOX_CMD_DATA_MASK);
2627
2628         /* decode the message and make appropriate requests to
2629          * clock or powergating module.
2630          */
2631
2632         switch (tegra->cmd_type) {
2633         case MBOX_CMD_INC_FALC_CLOCK:
2634         case MBOX_CMD_DEC_FALC_CLOCK:
2635                 ret = tegra_xusb_request_clk_rate(
2636                                 tegra,
2637                                 tegra->falc_clk,
2638                                 tegra->cmd_data,
2639                                 &sw_resp);
2640                 if (ret)
2641                         xhci_err(xhci, "%s: could not set required falc rate\n",
2642                                 __func__);
2643                 goto send_sw_response;
2644         case MBOX_CMD_INC_SSPI_CLOCK:
2645         case MBOX_CMD_DEC_SSPI_CLOCK:
2646                 ret = tegra_xusb_request_clk_rate(
2647                                 tegra,
2648                                 tegra->ss_src_clk,
2649                                 tegra->cmd_data,
2650                                 &sw_resp);
2651                 if (ret)
2652                         xhci_err(xhci, "%s: could not set required ss rate.\n",
2653                                 __func__);
2654                 goto send_sw_response;
2655         case MBOX_CMD_SET_BW:
2656                 /* fw sends BW request in MByte/sec */
2657                 freq_khz = tegra_emc_bw_to_freq_req(tegra->cmd_data << 10);
2658                 clk_set_rate(tegra->emc_clk, freq_khz * 1000);
2659
2660                 /* clear MBOX_SMI_INT_EN bit */
2661                 cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2662                 cmd &= ~MBOX_SMI_INT_EN;
2663                 writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2664
2665                 /* clear mbox owner as ACK will not be sent for this request */
2666                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2667                 break;
2668         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
2669                 tegra_xhci_save_dfe_ctle_context(tegra, tegra->cmd_data);
2670                 tegra_xhci_restore_dfe_ctle_context(tegra, tegra->cmd_data);
2671                 sw_resp |= tegra->cmd_data | (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
2672                 goto send_sw_response;
2673         case MBOX_CMD_ACK:
2674                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2675                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2676                 break;
2677         case MBOX_CMD_NACK:
2678                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2679                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2680                 break;
2681         default:
2682                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
2683                                 __func__, tegra->cmd_type);
2684         }
2685         mutex_unlock(&tegra->mbox_lock);
2686         return;
2687
2688 send_sw_response:
2689         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2690         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2691         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
2692         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2693
2694         mutex_unlock(&tegra->mbox_lock);
2695 }
2696
2697 static irqreturn_t tegra_xhci_xusb_host_irq(int irq, void *ptrdev)
2698 {
2699         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2700         struct xhci_hcd *xhci = tegra->xhci;
2701
2702         xhci_dbg(xhci, "%s", __func__);
2703         return IRQ_HANDLED;
2704 }
2705
2706 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
2707 {
2708         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2709         struct xhci_hcd *xhci = tegra->xhci;
2710         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2711         u32 elpg_program0 = 0;
2712
2713         spin_lock(&tegra->lock);
2714
2715         tegra->last_jiffies = jiffies;
2716
2717         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
2718         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
2719
2720         /* Clear the interrupt cause. We already read the intr status. */
2721         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2722         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
2723
2724         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
2725         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
2726                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2727         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
2728                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
2729         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
2730                 __func__,
2731                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad0_ctl0_0));
2732         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
2733                 __func__,
2734                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad1_ctl0_0));
2735         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
2736                 __func__,
2737                 readl(tegra->padctl_base + padregs->usb2_bchrg_bias_pad_0));
2738
2739         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
2740                 tegra->ss_wake_event = true;
2741         else if (elpg_program0 &
2742                         (USB2_PORT0_WAKEUP_EVENT | USB2_PORT1_WAKEUP_EVENT |
2743                                 USB2_PORT2_WAKEUP_EVENT))
2744                 tegra->hs_wake_event = true;
2745
2746         if (tegra->ss_wake_event || tegra->hs_wake_event) {
2747                 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
2748                         xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
2749                         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
2750                 } else if (tegra->ss_pwr_gated
2751                                 && tegra->host_pwr_gated) {
2752                         xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
2753                                 __func__);
2754                         schedule_work(&tegra->host_elpg_exit_work);
2755                 }
2756         } else {
2757                 xhci_err(xhci, "error: wake due to no hs/ss event\n");
2758                 tegra_usb_pad_reg_write(padregs->elpg_program_0, 0xffffffff);
2759         }
2760         spin_unlock(&tegra->lock);
2761         return IRQ_HANDLED;
2762 }
2763
2764 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
2765 {
2766         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2767         u32 temp;
2768
2769         spin_lock(&tegra->lock);
2770
2771         /* clear the mbox intr status 1st thing. Other
2772          * bits are W1C bits, so just write to SMI bit.
2773          */
2774
2775         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
2776
2777         /* write 1 to clear SMI INTR en bit ( bit 3 ) */
2778         temp = MBOX_SMI_INTR_EN;
2779         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
2780
2781         schedule_work(&tegra->mbox_work);
2782
2783         spin_unlock(&tegra->lock);
2784         return IRQ_HANDLED;
2785 }
2786
2787 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
2788 {
2789         /*
2790          * As of now platform drivers don't provide MSI support so we ensure
2791          * here that the generic code does not try to make a pci_dev from our
2792          * dev struct in order to setup MSI
2793          */
2794         xhci->quirks |= XHCI_BROKEN_MSI;
2795         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
2796 }
2797
2798 /* called during probe() after chip reset completes */
2799 static int xhci_plat_setup(struct usb_hcd *hcd)
2800 {
2801         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
2802 }
2803
2804 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
2805         const char *name, void __iomem **region)
2806 {
2807         struct resource *res;
2808         void __iomem *mem;
2809
2810         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
2811         if (!res) {
2812                 dev_err(&pdev->dev, "memory resource %s doesn't exist\n", name);
2813                 return -ENODEV;
2814         }
2815
2816         mem = devm_request_and_ioremap(&pdev->dev, res);
2817         if (!mem) {
2818                 dev_err(&pdev->dev, "failed to ioremap for %s\n", name);
2819                 return -EFAULT;
2820         }
2821         *region = mem;
2822
2823         return 0;
2824 }
2825
2826 static int tegra_xhci_request_irq(struct platform_device *pdev,
2827         const char *rscname, irq_handler_t handler, unsigned long irqflags,
2828         const char *devname, int *irq_no)
2829 {
2830         int ret;
2831         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2832         struct resource *res;
2833
2834         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, rscname);
2835         if (!res) {
2836                 dev_err(&pdev->dev, "irq resource %s doesn't exist\n", rscname);
2837                 return -ENODEV;
2838         }
2839
2840         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
2841                         devname, tegra);
2842         if (ret != 0) {
2843                 dev_err(&pdev->dev,
2844                         "failed to request_irq for %s (irq %d), error = %d\n",
2845                         devname, res->start, ret);
2846                 return ret;
2847         }
2848         *irq_no = res->start;
2849
2850         return 0;
2851 }
2852
2853 #ifdef CONFIG_PM
2854
2855 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
2856 {
2857         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2858         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2859         int err = 0;
2860         unsigned long flags;
2861
2862         mutex_lock(&tegra->sync_lock);
2863
2864         if (xhci->shared_hcd == hcd) {
2865                 tegra->usb3_rh_suspend = true;
2866                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
2867         } else if (xhci->main_hcd == hcd) {
2868                 tegra->usb2_rh_suspend = true;
2869                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
2870         }
2871
2872         WARN_ON(tegra->hc_in_elpg);
2873
2874         /* suspend xhci bus. This will also set remote mask */
2875         err = xhci_bus_suspend(hcd);
2876         if (err) {
2877                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
2878                                 __func__, err);
2879                 goto xhci_bus_suspend_failed;
2880         }
2881
2882         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
2883                 goto done; /* one of the root hubs is still working */
2884
2885         spin_lock_irqsave(&tegra->lock, flags);
2886         tegra->hc_in_elpg = true;
2887         spin_unlock_irqrestore(&tegra->lock, flags);
2888
2889         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
2890
2891         /* save xhci spec ctx. Already done by xhci_suspend */
2892         err = xhci_suspend(tegra->xhci);
2893         if (err) {
2894                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
2895                 goto xhci_suspend_failed;
2896         }
2897
2898         /* Powergate host. Include ss power gate if not already done */
2899         err = tegra_xhci_host_elpg_entry(tegra);
2900         if (err) {
2901                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
2902                                 __func__, err);
2903                 goto tegra_xhci_host_elpg_entry_failed;
2904         }
2905
2906         /* At this point,ensure ss/hs intr enables are always on */
2907         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2908         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2909
2910         /* In ELPG, firmware log context is gone. Rewind shared log buffer. */
2911         if (fw_log_wait_empty_timeout(tegra, 100))
2912                 xhci_warn(xhci, "%s still has logs\n", __func__);
2913         tegra->log.dequeue = tegra->log.virt_addr;
2914         tegra->log.seq = 0;
2915
2916 done:
2917         /* pads are disabled only if usb2 root hub in xusb is idle */
2918         /* pads will actually be disabled only when all usb2 ports are idle */
2919         if (xhci->main_hcd == hcd) {
2920                 utmi_phy_pad_disable();
2921                 utmi_phy_iddq_override(true);
2922         }
2923         mutex_unlock(&tegra->sync_lock);
2924         return 0;
2925
2926 tegra_xhci_host_elpg_entry_failed:
2927
2928 xhci_suspend_failed:
2929         tegra->hc_in_elpg = false;
2930 xhci_bus_suspend_failed:
2931         if (xhci->shared_hcd == hcd)
2932                 tegra->usb3_rh_suspend = false;
2933         else if (xhci->main_hcd == hcd)
2934                 tegra->usb2_rh_suspend = false;
2935
2936         mutex_unlock(&tegra->sync_lock);
2937         return err;
2938 }
2939
2940 /* First, USB2HCD and then USB3HCD resume will be called */
2941 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
2942 {
2943         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2944         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2945         int err = 0;
2946
2947         mutex_lock(&tegra->sync_lock);
2948
2949         tegra->host_resume_req = true;
2950
2951         if (xhci->shared_hcd == hcd)
2952                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
2953         else if (xhci->main_hcd == hcd)
2954                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
2955
2956         /* pads are disabled only if usb2 root hub in xusb is idle */
2957         /* pads will actually be disabled only when all usb2 ports are idle */
2958         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
2959                 utmi_phy_pad_enable();
2960                 utmi_phy_iddq_override(false);
2961         }
2962         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
2963                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
2964                         tegra_xhci_host_partition_elpg_exit(tegra);
2965         }
2966
2967          /* handle remote wakeup before resuming bus */
2968         wait_remote_wakeup_ports(hcd);
2969
2970         err = xhci_bus_resume(hcd);
2971         if (err) {
2972                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
2973                                 __func__, err);
2974                 goto xhci_bus_resume_failed;
2975         }
2976
2977         if (xhci->shared_hcd == hcd)
2978                 tegra->usb3_rh_suspend = false;
2979         else if (xhci->main_hcd == hcd)
2980                 tegra->usb2_rh_suspend = false;
2981
2982         mutex_unlock(&tegra->sync_lock);
2983         return 0;
2984
2985 xhci_bus_resume_failed:
2986         /* TODO: reverse elpg? */
2987         mutex_unlock(&tegra->sync_lock);
2988         return err;
2989 }
2990 #endif
2991
2992 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
2993 {
2994         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2995         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2996         irqreturn_t iret = IRQ_HANDLED;
2997         u32 status;
2998
2999         spin_lock(&tegra->lock);
3000         if (tegra->hc_in_elpg) {
3001                 spin_lock(&xhci->lock);
3002                 if (HCD_HW_ACCESSIBLE(hcd)) {
3003                         status = xhci_readl(xhci, &xhci->op_regs->status);
3004                         status |= STS_EINT;
3005                         xhci_writel(xhci, status, &xhci->op_regs->status);
3006                 }
3007                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
3008                                 __func__);
3009                 schedule_work(&tegra->host_elpg_exit_work);
3010                 spin_unlock(&xhci->lock);
3011         } else
3012                 iret = xhci_irq(hcd);
3013         spin_unlock(&tegra->lock);
3014
3015         wake_up_interruptible(&tegra->log.intr_wait);
3016
3017         return iret;
3018 }
3019
3020
3021 static const struct hc_driver tegra_plat_xhci_driver = {
3022         .description =          "tegra-xhci",
3023         .product_desc =         "Nvidia xHCI Host Controller",
3024         .hcd_priv_size =        sizeof(struct xhci_hcd *),
3025
3026         /*
3027          * generic hardware linkage
3028          */
3029         .irq =                  tegra_xhci_irq,
3030         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
3031
3032         /*
3033          * basic lifecycle operations
3034          */
3035         .reset =                xhci_plat_setup,
3036         .start =                xhci_run,
3037         .stop =                 xhci_stop,
3038         .shutdown =             xhci_shutdown,
3039
3040         /*
3041          * managing i/o requests and associated device resources
3042          */
3043         .urb_enqueue =          xhci_urb_enqueue,
3044         .urb_dequeue =          xhci_urb_dequeue,
3045         .alloc_dev =            xhci_alloc_dev,
3046         .free_dev =             xhci_free_dev,
3047         .alloc_streams =        xhci_alloc_streams,
3048         .free_streams =         xhci_free_streams,
3049         .add_endpoint =         xhci_add_endpoint,
3050         .drop_endpoint =        xhci_drop_endpoint,
3051         .endpoint_reset =       xhci_endpoint_reset,
3052         .check_bandwidth =      xhci_check_bandwidth,
3053         .reset_bandwidth =      xhci_reset_bandwidth,
3054         .address_device =       xhci_address_device,
3055         .update_hub_device =    xhci_update_hub_device,
3056         .reset_device =         xhci_discover_or_reset_device,
3057
3058         /*
3059          * scheduling support
3060          */
3061         .get_frame_number =     xhci_get_frame,
3062
3063         /* Root hub support */
3064         .hub_control =          xhci_hub_control,
3065         .hub_status_data =      xhci_hub_status_data,
3066
3067 #ifdef CONFIG_PM
3068         .bus_suspend =          tegra_xhci_bus_suspend,
3069         .bus_resume =           tegra_xhci_bus_resume,
3070 #endif
3071 };
3072
3073 #ifdef CONFIG_PM
3074 static int
3075 tegra_xhci_suspend(struct platform_device *pdev,
3076                                                 pm_message_t state)
3077 {
3078         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3079         struct xhci_hcd *xhci = tegra->xhci;
3080
3081         int ret = 0;
3082
3083         mutex_lock(&tegra->sync_lock);
3084         if (!tegra->hc_in_elpg) {
3085                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
3086                                 __func__);
3087                 mutex_unlock(&tegra->sync_lock);
3088                 return -EBUSY;
3089         }
3090         mutex_unlock(&tegra->sync_lock);
3091
3092         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3093         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3094
3095         /* enable_irq_wake for ss ports */
3096         ret = enable_irq_wake(tegra->padctl_irq);
3097         if (ret < 0) {
3098                 xhci_err(xhci,
3099                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
3100                 __func__, tegra->padctl_irq, ret);
3101         }
3102
3103         /* enable_irq_wake for hs/fs/ls ports */
3104         ret = enable_irq_wake(tegra->usb3_irq);
3105         if (ret < 0) {
3106                 xhci_err(xhci,
3107                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
3108                 __func__, tegra->usb3_irq, ret);
3109         }
3110         regulator_disable(tegra->xusb_s1p8v_reg);
3111         regulator_disable(tegra->xusb_s1p05v_reg);
3112         tegra_usb2_clocks_deinit(tegra);
3113
3114         return ret;
3115 }
3116
3117 static int
3118 tegra_xhci_resume(struct platform_device *pdev)
3119 {
3120         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3121
3122         dev_dbg(&pdev->dev, "%s\n", __func__);
3123
3124         tegra->last_jiffies = jiffies;
3125
3126         disable_irq_wake(tegra->padctl_irq);
3127         disable_irq_wake(tegra->usb3_irq);
3128         tegra->lp0_exit = true;
3129
3130         regulator_enable(tegra->xusb_s1p05v_reg);
3131         regulator_enable(tegra->xusb_s1p8v_reg);
3132         tegra_usb2_clocks_init(tegra);
3133
3134         return 0;
3135 }
3136 #endif
3137
3138
3139 static int init_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3140 {
3141         struct platform_device *pdev = tegra->pdev;
3142         void __iomem *fw_mmio_base;
3143         phys_addr_t fw_mem_phy_addr;
3144         size_t fw_size;
3145         dma_addr_t fw_dma;
3146 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3147         int ret;
3148 #endif
3149
3150         /* bootloader saved firmware memory address in PMC SCRATCH34 register */
3151         fw_mem_phy_addr = tegra_usb_pmc_reg_read(PMC_SCRATCH34);
3152
3153         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3154                         fw_mem_phy_addr, sizeof(struct cfgtbl));
3155
3156         if (!fw_mmio_base) {
3157                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3158                                         fw_mem_phy_addr);
3159                         return -ENOMEM;
3160         }
3161
3162         fw_size = ioread32(fw_mmio_base + FW_SIZE_OFFSET);
3163         devm_iounmap(&pdev->dev, fw_mmio_base);
3164
3165         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3166                         fw_mem_phy_addr, fw_size);
3167         if (!fw_mmio_base) {
3168                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3169                                         fw_mem_phy_addr);
3170                         return -ENOMEM;
3171         }
3172
3173         dev_info(&pdev->dev, "Firmware Memory: phy 0x%x mapped 0x%p (%d Bytes)\n",
3174                         fw_mem_phy_addr, fw_mmio_base, fw_size);
3175
3176 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3177         fw_dma = dma_map_linear(&pdev->dev, fw_mem_phy_addr, fw_size,
3178                         DMA_TO_DEVICE);
3179         if (fw_dma == DMA_ERROR_CODE) {
3180                 dev_err(&pdev->dev, "%s: dma_map_linear failed\n",
3181                                 __func__);
3182                 ret = -ENOMEM;
3183                 goto error_iounmap;
3184         }
3185 #else
3186         fw_dma = fw_mem_phy_addr;
3187 #endif
3188         dev_info(&pdev->dev, "Firmware DMA Memory: dma 0x%p (%d Bytes)\n",
3189                         (void *) fw_dma, fw_size);
3190
3191         /* all set and ready to go */
3192         tegra->firmware.data = fw_mmio_base;
3193         tegra->firmware.dma = fw_dma;
3194         tegra->firmware.size = fw_size;
3195
3196         return 0;
3197
3198 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3199 error_iounmap:
3200         devm_iounmap(&pdev->dev, fw_mmio_base);
3201         return ret;
3202 #endif
3203 }
3204
3205 static void deinit_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3206 {
3207         struct platform_device *pdev = tegra->pdev;
3208         void __iomem *fw_mmio_base = tegra->firmware.data;
3209
3210 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3211         dma_unmap_single(&pdev->dev, tegra->firmware.dma,
3212                         tegra->firmware.size, DMA_TO_DEVICE);
3213 #endif
3214         devm_iounmap(&pdev->dev, fw_mmio_base);
3215
3216         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
3217 }
3218
3219 static int init_firmware(struct tegra_xhci_hcd *tegra)
3220 {
3221         return init_bootloader_firmware(tegra);
3222 }
3223
3224 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
3225 {
3226         deinit_bootloader_firmware(tegra);
3227 }
3228
3229 static int tegra_enable_xusb_clk(struct tegra_xhci_hcd *tegra,
3230                 struct platform_device *pdev)
3231 {
3232         int err = 0;
3233         /* enable ss clock */
3234         err = clk_enable(tegra->host_clk);
3235         if (err) {
3236                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
3237                 goto enable_host_clk_failed;
3238         }
3239
3240         err = clk_enable(tegra->ss_clk);
3241         if (err) {
3242                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
3243                 goto eanble_ss_clk_failed;
3244         }
3245
3246         err = clk_enable(tegra->emc_clk);
3247         if (err) {
3248                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
3249                 goto eanble_emc_clk_failed;
3250         }
3251
3252         return 0;
3253
3254 eanble_emc_clk_failed:
3255         clk_disable(tegra->ss_clk);
3256
3257 eanble_ss_clk_failed:
3258         clk_disable(tegra->host_clk);
3259
3260 enable_host_clk_failed:
3261         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
3262                 clk_disable(tegra->pll_re_vco_clk);
3263         return err;
3264 }
3265
3266 static struct tegra_xusb_padctl_regs t114_padregs_offset = {
3267         .boot_media_0                   = 0x0,
3268         .usb2_pad_mux_0                 = 0x4,
3269         .usb2_port_cap_0                = 0x8,
3270         .snps_oc_map_0                  = 0xc,
3271         .usb2_oc_map_0                  = 0x10,
3272         .ss_port_map_0                  = 0x14,
3273         .oc_det_0                       = 0x18,
3274         .elpg_program_0                 = 0x1c,
3275         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3276         .usb2_bchrg_otgpad0_ctl1_0      = 0xffff,
3277         .usb2_bchrg_otgpad1_ctl0_0      = 0x24,
3278         .usb2_bchrg_otgpad1_ctl1_0      = 0xffff,
3279         .usb2_bchrg_otgpad2_ctl0_0      = 0xffff,
3280         .usb2_bchrg_otgpad2_ctl1_0      = 0xffff,
3281         .usb2_bchrg_bias_pad_0          = 0x28,
3282         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
3283         .iophy_pll_p0_ctl1_0            = 0x30,
3284         .iophy_pll_p0_ctl2_0            = 0x34,
3285         .iophy_pll_p0_ctl3_0            = 0x38,
3286         .iophy_pll_p0_ctl4_0            = 0x3c,
3287         .iophy_usb3_pad0_ctl1_0         = 0x40,
3288         .iophy_usb3_pad1_ctl1_0         = 0x44,
3289         .iophy_usb3_pad0_ctl2_0         = 0x48,
3290         .iophy_usb3_pad1_ctl2_0         = 0x4c,
3291         .iophy_usb3_pad0_ctl3_0         = 0x50,
3292         .iophy_usb3_pad1_ctl3_0         = 0x54,
3293         .iophy_usb3_pad0_ctl4_0         = 0x58,
3294         .iophy_usb3_pad1_ctl4_0         = 0x5c,
3295         .iophy_misc_pad_p0_ctl1_0       = 0x60,
3296         .iophy_misc_pad_p1_ctl1_0       = 0x64,
3297         .iophy_misc_pad_p0_ctl2_0       = 0x68,
3298         .iophy_misc_pad_p1_ctl2_0       = 0x6c,
3299         .iophy_misc_pad_p0_ctl3_0       = 0x70,
3300         .iophy_misc_pad_p1_ctl3_0       = 0x74,
3301         .iophy_misc_pad_p0_ctl4_0       = 0x78,
3302         .iophy_misc_pad_p1_ctl4_0       = 0x7c,
3303         .iophy_misc_pad_p0_ctl5_0       = 0x80,
3304         .iophy_misc_pad_p1_ctl5_0       = 0x84,
3305         .iophy_misc_pad_p0_ctl6_0       = 0x88,
3306         .iophy_misc_pad_p1_ctl6_0       = 0x8c,
3307         .usb2_otg_pad0_ctl0_0           = 0x90,
3308         .usb2_otg_pad1_ctl0_0           = 0x94,
3309         .usb2_otg_pad2_ctl0_0           = 0xffff,
3310         .usb2_otg_pad0_ctl1_0           = 0x98,
3311         .usb2_otg_pad1_ctl1_0           = 0x9c,
3312         .usb2_otg_pad2_ctl1_0           = 0xffff,
3313         .usb2_bias_pad_ctl0_0           = 0xa0,
3314         .usb2_bias_pad_ctl1_0           = 0xa4,
3315         .usb2_hsic_pad0_ctl0_0          = 0xa8,
3316         .usb2_hsic_pad1_ctl0_0          = 0xac,
3317         .usb2_hsic_pad0_ctl1_0          = 0xb0,
3318         .usb2_hsic_pad1_ctl1_0          = 0xb4,
3319         .usb2_hsic_pad0_ctl2_0          = 0xb8,
3320         .usb2_hsic_pad1_ctl2_0          = 0xbc,
3321         .ulpi_link_trim_ctl0            = 0xc0,
3322         .ulpi_null_clk_trim_ctl0        = 0xc4,
3323         .hsic_strb_trim_ctl0            = 0xc8,
3324         .wake_ctl0                      = 0xcc,
3325         .pm_spare0                      = 0xd0,
3326         .iophy_misc_pad_p2_ctl1_0       = 0xffff,
3327         .iophy_misc_pad_p3_ctl1_0       = 0xffff,
3328         .iophy_misc_pad_p4_ctl1_0       = 0xffff,
3329         .iophy_misc_pad_p2_ctl2_0       = 0xffff,
3330         .iophy_misc_pad_p3_ctl2_0       = 0xffff,
3331         .iophy_misc_pad_p4_ctl2_0       = 0xffff,
3332         .iophy_misc_pad_p2_ctl3_0       = 0xffff,
3333         .iophy_misc_pad_p3_ctl3_0       = 0xffff,
3334         .iophy_misc_pad_p4_ctl3_0       = 0xffff,
3335         .iophy_misc_pad_p2_ctl4_0       = 0xffff,
3336         .iophy_misc_pad_p3_ctl4_0       = 0xffff,
3337         .iophy_misc_pad_p4_ctl4_0       = 0xffff,
3338         .iophy_misc_pad_p2_ctl5_0       = 0xffff,
3339         .iophy_misc_pad_p3_ctl5_0       = 0xffff,
3340         .iophy_misc_pad_p4_ctl5_0       = 0xffff,
3341         .iophy_misc_pad_p2_ctl6_0       = 0xffff,
3342         .iophy_misc_pad_p3_ctl6_0       = 0xffff,
3343         .iophy_misc_pad_p4_ctl6_0       = 0xffff,
3344         .usb3_pad_mux_0                 = 0xffff,
3345         .iophy_pll_s0_ctl1_0            = 0xffff,
3346         .iophy_pll_s0_ctl2_0            = 0xffff,
3347         .iophy_pll_s0_ctl3_0            = 0xffff,
3348         .iophy_pll_s0_ctl4_0            = 0xffff,
3349         .iophy_misc_pad_s0_ctl1_0       = 0xffff,
3350         .iophy_misc_pad_s0_ctl2_0       = 0xffff,
3351         .iophy_misc_pad_s0_ctl3_0       = 0xffff,
3352         .iophy_misc_pad_s0_ctl4_0       = 0xffff,
3353         .iophy_misc_pad_s0_ctl5_0       = 0xffff,
3354         .iophy_misc_pad_s0_ctl6_0       = 0xffff,
3355 };
3356
3357 static struct tegra_xusb_padctl_regs t124_padregs_offset = {
3358         .boot_media_0                   = 0x0,
3359         .usb2_pad_mux_0                 = 0x4,
3360         .usb2_port_cap_0                = 0x8,
3361         .snps_oc_map_0                  = 0xc,
3362         .usb2_oc_map_0                  = 0x10,
3363         .ss_port_map_0                  = 0x14,
3364         .oc_det_0                       = 0x18,
3365         .elpg_program_0                 = 0x1c,
3366         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3367         .usb2_bchrg_otgpad0_ctl1_0      = 0x24,
3368         .usb2_bchrg_otgpad1_ctl0_0      = 0x28,
3369         .usb2_bchrg_otgpad1_ctl1_0      = 0x2c,
3370         .usb2_bchrg_otgpad2_ctl0_0      = 0x30,
3371         .usb2_bchrg_otgpad2_ctl1_0      = 0x34,
3372         .usb2_bchrg_bias_pad_0          = 0x38,
3373         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
3374         .iophy_pll_p0_ctl1_0            = 0x40,
3375         .iophy_pll_p0_ctl2_0            = 0x44,
3376         .iophy_pll_p0_ctl3_0            = 0x48,
3377         .iophy_pll_p0_ctl4_0            = 0x4c,
3378         .iophy_usb3_pad0_ctl1_0         = 0x50,
3379         .iophy_usb3_pad1_ctl1_0         = 0x54,
3380         .iophy_usb3_pad0_ctl2_0         = 0x58,
3381         .iophy_usb3_pad1_ctl2_0         = 0x5c,
3382         .iophy_usb3_pad0_ctl3_0         = 0x60,
3383         .iophy_usb3_pad1_ctl3_0         = 0x64,
3384         .iophy_usb3_pad0_ctl4_0         = 0x68,
3385         .iophy_usb3_pad1_ctl4_0         = 0x6c,
3386         .iophy_misc_pad_p0_ctl1_0       = 0x70,
3387         .iophy_misc_pad_p1_ctl1_0       = 0x74,
3388         .iophy_misc_pad_p0_ctl2_0       = 0x78,
3389         .iophy_misc_pad_p1_ctl2_0       = 0x7c,
3390         .iophy_misc_pad_p0_ctl3_0       = 0x80,
3391         .iophy_misc_pad_p1_ctl3_0       = 0x84,
3392         .iophy_misc_pad_p0_ctl4_0       = 0x88,
3393         .iophy_misc_pad_p1_ctl4_0       = 0x8c,
3394         .iophy_misc_pad_p0_ctl5_0       = 0x90,
3395         .iophy_misc_pad_p1_ctl5_0       = 0x94,
3396         .iophy_misc_pad_p0_ctl6_0       = 0x98,
3397         .iophy_misc_pad_p1_ctl6_0       = 0x9c,
3398         .usb2_otg_pad0_ctl0_0           = 0xa0,
3399         .usb2_otg_pad1_ctl0_0           = 0xa4,
3400         .usb2_otg_pad2_ctl0_0           = 0xa8,
3401         .usb2_otg_pad0_ctl1_0           = 0xac,
3402         .usb2_otg_pad1_ctl1_0           = 0xb0,
3403         .usb2_otg_pad2_ctl1_0           = 0xb4,
3404         .usb2_bias_pad_ctl0_0           = 0xb8,
3405         .usb2_bias_pad_ctl1_0           = 0xbc,
3406         .usb2_hsic_pad0_ctl0_0          = 0xc0,
3407         .usb2_hsic_pad1_ctl0_0          = 0xc4,
3408         .usb2_hsic_pad0_ctl1_0          = 0xc8,
3409         .usb2_hsic_pad1_ctl1_0          = 0xcc,
3410         .usb2_hsic_pad0_ctl2_0          = 0xd0,
3411         .usb2_hsic_pad1_ctl2_0          = 0xd4,
3412         .ulpi_link_trim_ctl0            = 0xd8,
3413         .ulpi_null_clk_trim_ctl0        = 0xdc,
3414         .hsic_strb_trim_ctl0            = 0xe0,
3415         .wake_ctl0                      = 0xe4,
3416         .pm_spare0                      = 0xe8,
3417         .iophy_misc_pad_p2_ctl1_0       = 0xec,
3418         .iophy_misc_pad_p3_ctl1_0       = 0xf0,
3419         .iophy_misc_pad_p4_ctl1_0       = 0xf4,
3420         .iophy_misc_pad_p2_ctl2_0       = 0xf8,
3421         .iophy_misc_pad_p3_ctl2_0       = 0xfc,
3422         .iophy_misc_pad_p4_ctl2_0       = 0x100,
3423         .iophy_misc_pad_p2_ctl3_0       = 0x104,
3424         .iophy_misc_pad_p3_ctl3_0       = 0x108,
3425         .iophy_misc_pad_p4_ctl3_0       = 0x10c,
3426         .iophy_misc_pad_p2_ctl4_0       = 0x110,
3427         .iophy_misc_pad_p3_ctl4_0       = 0x114,
3428         .iophy_misc_pad_p4_ctl4_0       = 0x118,
3429         .iophy_misc_pad_p2_ctl5_0       = 0x11c,
3430         .iophy_misc_pad_p3_ctl5_0       = 0x120,
3431         .iophy_misc_pad_p4_ctl5_0       = 0x124,
3432         .iophy_misc_pad_p2_ctl6_0       = 0x128,
3433         .iophy_misc_pad_p3_ctl6_0       = 0x12c,
3434         .iophy_misc_pad_p4_ctl6_0       = 0x130,
3435         .usb3_pad_mux_0                 = 0x134,
3436         .iophy_pll_s0_ctl1_0            = 0x138,
3437         .iophy_pll_s0_ctl2_0            = 0x13c,
3438         .iophy_pll_s0_ctl3_0            = 0x140,
3439         .iophy_pll_s0_ctl4_0            = 0x144,
3440         .iophy_misc_pad_s0_ctl1_0       = 0x148,
3441         .iophy_misc_pad_s0_ctl2_0       = 0x14c,
3442         .iophy_misc_pad_s0_ctl3_0       = 0x150,
3443         .iophy_misc_pad_s0_ctl4_0       = 0x154,
3444         .iophy_misc_pad_s0_ctl5_0       = 0x158,
3445         .iophy_misc_pad_s0_ctl6_0       = 0x15c,
3446 };
3447
3448 /* TODO: we have to refine error handling in tegra_xhci_probe() */
3449 static int tegra_xhci_probe(struct platform_device *pdev)
3450 {
3451         const struct hc_driver *driver;
3452         struct xhci_hcd *xhci;
3453         struct tegra_xhci_hcd *tegra;
3454         struct resource *res;
3455         struct usb_hcd  *hcd;
3456         u32 pmc_reg, val;
3457         int ret;
3458         int irq;
3459
3460         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
3461
3462         if (usb_disabled())
3463                 return -ENODEV;
3464
3465         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
3466         if (!tegra) {
3467                 dev_err(&pdev->dev, "memory alloc failed\n");
3468                 return -ENOMEM;
3469         }
3470         tegra->pdev = pdev;
3471         tegra->pdata = dev_get_platdata(&pdev->dev);
3472         tegra->bdata = tegra->pdata->bdata;
3473
3474         ret = tegra_xhci_request_mem_region(pdev, "padctl",
3475                         &tegra->padctl_base);
3476         if (ret) {
3477                 dev_err(&pdev->dev, "failed to map padctl\n");
3478                 return ret;
3479         }
3480
3481         ret = tegra_xhci_request_mem_region(pdev, "fpci", &tegra->fpci_base);
3482         if (ret) {
3483                 dev_err(&pdev->dev, "failed to map fpci\n");
3484                 return ret;
3485         }
3486
3487         ret = tegra_xhci_request_mem_region(pdev, "ipfs", &tegra->ipfs_base);
3488         if (ret) {
3489                 dev_err(&pdev->dev, "failed to map ipfs\n");
3490                 return ret;
3491         }
3492
3493         ret = tegra_xusb_partitions_clk_init(tegra);
3494         if (ret) {
3495                 dev_err(&pdev->dev,
3496                         "failed to initialize xusb partitions clocks\n");
3497                 return ret;
3498         }
3499
3500         /* Enable power rails to the PAD,VBUS
3501          * and pull-up voltage.Initialize the regulators
3502          */
3503         ret = tegra_xusb_regulator_init(tegra, pdev);
3504         if (ret) {
3505                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
3506                 goto err_deinit_xusb_partition_clk;
3507         }
3508
3509         /* Enable UTMIP, PLLU and PLLE */
3510         ret = tegra_usb2_clocks_init(tegra);
3511         if (ret) {
3512                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
3513                 goto err_deinit_tegra_xusb_regulator;
3514         }
3515
3516         /* tegra_unpowergate_partition also does partition reset deassert */
3517         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
3518         if (ret)
3519                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
3520
3521         /* tegra_unpowergate_partition also does partition reset deassert */
3522         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3523         if (ret)
3524                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
3525
3526         ret = tegra_enable_xusb_clk(tegra, pdev);
3527         if (ret)
3528                 dev_err(&pdev->dev, "could not enable partition clock\n");
3529
3530         /* reset the pointer back to NULL. driver uses it */
3531         /* platform_set_drvdata(pdev, NULL); */
3532
3533         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "host");
3534         if (!res) {
3535                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
3536                 ret = -ENODEV;
3537                 goto err_deinit_usb2_clocks;
3538         }
3539         tegra->host_phy_base = res->start;
3540
3541         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
3542                                 res->start, resource_size(res));
3543         if (!tegra->host_phy_virt_base) {
3544                 dev_err(&pdev->dev, "error mapping host phy memory\n");
3545                 ret = -ENOMEM;
3546                 goto err_deinit_usb2_clocks;
3547         }
3548
3549         /* Setup IPFS access and BAR0 space */
3550         tegra_xhci_cfg(tegra);
3551
3552         val = readl(tegra->fpci_base + XUSB_CFG_0);
3553         tegra->device_id = (val >> 16) & 0xffff;
3554
3555         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
3556                 (XUSB_DEVICE_ID_T114 == tegra->device_id) ? "T114" : "T124+");
3557
3558         if (XUSB_DEVICE_ID_T114 == tegra->device_id) {
3559                 tegra->padregs = &t114_padregs_offset;
3560         } else if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
3561                 tegra->padregs = &t124_padregs_offset;
3562         } else {
3563                 dev_info(&pdev->dev, "XUSB device_id neither T114 nor T124!\n");
3564                 dev_info(&pdev->dev, "XUSB using T124 pad register offsets!\n");
3565                 tegra->padregs = &t124_padregs_offset;
3566         }
3567
3568         /* calculate rctrl_val and tctrl_val once at boot time */
3569         /* Issue is only applicable for T114 */
3570         if (XUSB_DEVICE_ID_T114 == tegra->device_id)
3571                 tegra_xhci_war_for_tctrl_rctrl(tegra);
3572
3573         /* Program the XUSB pads to take ownership of ports */
3574         tegra_xhci_padctl_portmap_and_caps(tegra);
3575
3576         /* Release XUSB wake logic state latching */
3577         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
3578         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
3579
3580         /* Deassert reset to XUSB host, ss, dev clocks */
3581         tegra_periph_reset_deassert(tegra->host_clk);
3582         tegra_periph_reset_deassert(tegra->ss_clk);
3583
3584         fw_log_init(tegra);
3585         ret = init_firmware(tegra);
3586         if (ret < 0) {
3587                 dev_err(&pdev->dev, "failed to init firmware\n");
3588                 ret = -ENODEV;
3589                 goto err_deinit_usb2_clocks;
3590         }
3591
3592         ret = load_firmware(tegra, true /* do reset ARU */);
3593         if (ret < 0) {
3594                 dev_err(&pdev->dev, "failed to load firmware\n");
3595                 ret = -ENODEV;
3596                 goto err_deinit_firmware;
3597         }
3598
3599         device_init_wakeup(&pdev->dev, 1);
3600         driver = &tegra_plat_xhci_driver;
3601
3602         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
3603         if (!hcd) {
3604                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
3605                 ret = -ENOMEM;
3606                 goto err_deinit_firmware;
3607         }
3608
3609         ret = tegra_xhci_request_mem_region(pdev, "host", &hcd->regs);
3610         if (ret) {
3611                 dev_err(&pdev->dev, "failed to map host\n");
3612                 goto err_put_usb2_hcd;
3613         }
3614         hcd->rsrc_start = res->start;
3615         hcd->rsrc_len = resource_size(res);
3616
3617         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "host");
3618         if (!res) {
3619                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
3620                 ret = -ENODEV;
3621                 goto err_put_usb2_hcd;
3622         }
3623         irq = res->start;
3624         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
3625         if (ret) {
3626                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
3627                 goto err_put_usb2_hcd;
3628         }
3629
3630         /* USB 2.0 roothub is stored in the platform_device now. */
3631         hcd = dev_get_drvdata(&pdev->dev);
3632         xhci = hcd_to_xhci(hcd);
3633         tegra->xhci = xhci;
3634         platform_set_drvdata(pdev, tegra);
3635
3636         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
3637                                                 dev_name(&pdev->dev), hcd);
3638         if (!xhci->shared_hcd) {
3639                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
3640                 ret = -ENOMEM;
3641                 goto err_remove_usb2_hcd;
3642         }
3643
3644         /*
3645          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
3646          * is called by usb_add_hcd().
3647          */
3648         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
3649
3650         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
3651         if (ret) {
3652                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
3653                 goto err_put_usb3_hcd;
3654         }
3655
3656         device_init_wakeup(&hcd->self.root_hub->dev, 1);
3657         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
3658         spin_lock_init(&tegra->lock);
3659         mutex_init(&tegra->sync_lock);
3660         mutex_init(&tegra->mbox_lock);
3661
3662         /* do mailbox related initializations */
3663         tegra->mbox_owner = 0xffff;
3664         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
3665
3666         tegra_xhci_enable_fw_message(tegra);
3667
3668         /* do ss partition elpg exit related initialization */
3669         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
3670
3671         /* do host partition elpg exit related initialization */
3672         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
3673
3674         /* Register interrupt handler for SMI line to handle mailbox
3675          * interrupt from firmware
3676          */
3677         ret = tegra_xhci_request_irq(pdev, "host-smi", tegra_xhci_smi_irq,
3678                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
3679         if (ret != 0)
3680                 goto err_remove_usb3_hcd;
3681
3682         /* Register interrupt handler for PADCTRL line to
3683          * handle wake on connect irqs interrupt from
3684          * firmware
3685          */
3686         ret = tegra_xhci_request_irq(pdev, "padctl", tegra_xhci_padctl_irq,
3687                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
3688                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
3689         if (ret != 0)
3690                 goto err_remove_usb3_hcd;
3691
3692         ret = tegra_xhci_request_irq(pdev, "usb3", tegra_xhci_xusb_host_irq,
3693                         IRQF_SHARED | IRQF_TRIGGER_HIGH, "xusb_host_irq",
3694                         &tegra->usb3_irq);
3695         if (ret != 0)
3696                 goto err_remove_usb3_hcd;
3697
3698         tegra->ss_pwr_gated = false;
3699         tegra->host_pwr_gated = false;
3700         tegra->hc_in_elpg = false;
3701         tegra->hs_wake_event = false;
3702         tegra->host_resume_req = false;
3703         tegra->lp0_exit = false;
3704         tegra->dfe_ctle_ctx_saved = false;
3705
3706         /* reset wake event to NONE */
3707         pmc_reg = tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0);
3708         pmc_reg |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE);
3709         pmc_reg |= UTMIP_WAKE_VAL(1, WAKE_VAL_NONE);
3710         pmc_reg |= UTMIP_WAKE_VAL(2, WAKE_VAL_NONE);
3711         pmc_reg |= UTMIP_WAKE_VAL(3, WAKE_VAL_NONE);
3712         tegra_usb_pmc_reg_write(PMC_UTMIP_UHSIC_SLEEP_CFG_0, pmc_reg);
3713
3714         tegra_xhci_debug_read_pads(tegra);
3715         utmi_phy_pad_enable();
3716         utmi_phy_iddq_override(false);
3717
3718         tegra_pd_add_device(&pdev->dev);
3719
3720         return 0;
3721
3722 err_remove_usb3_hcd:
3723         usb_remove_hcd(xhci->shared_hcd);
3724 err_put_usb3_hcd:
3725         usb_put_hcd(xhci->shared_hcd);
3726 err_remove_usb2_hcd:
3727         kfree(tegra->xhci);
3728         usb_remove_hcd(hcd);
3729 err_put_usb2_hcd:
3730         usb_put_hcd(hcd);
3731 err_deinit_firmware:
3732         deinit_firmware(tegra);
3733 err_deinit_usb2_clocks:
3734         tegra_usb2_clocks_deinit(tegra);
3735 err_deinit_tegra_xusb_regulator:
3736         tegra_xusb_regulator_deinit(tegra);
3737 err_deinit_xusb_partition_clk:
3738         tegra_xusb_partitions_clk_deinit(tegra);
3739
3740         return ret;
3741 }
3742
3743 static int tegra_xhci_remove(struct platform_device *pdev)
3744 {
3745         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3746         struct xhci_hcd *xhci = NULL;
3747         struct usb_hcd *hcd = NULL;
3748
3749         if (tegra == NULL)
3750                 return -EINVAL;
3751
3752         xhci = tegra->xhci;
3753         hcd = xhci_to_hcd(xhci);
3754
3755         devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
3756         devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
3757         devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
3758         usb_remove_hcd(xhci->shared_hcd);
3759         usb_put_hcd(xhci->shared_hcd);
3760         usb_remove_hcd(hcd);
3761         usb_put_hcd(hcd);
3762         kfree(xhci);
3763
3764         deinit_firmware(tegra);
3765         fw_log_deinit(tegra);
3766         tegra_xusb_regulator_deinit(tegra);
3767         tegra_usb2_clocks_deinit(tegra);
3768         if (!tegra->hc_in_elpg)
3769                 tegra_xusb_partitions_clk_deinit(tegra);
3770         utmi_phy_pad_disable();
3771         utmi_phy_iddq_override(true);
3772
3773         tegra_pd_remove_device(&pdev->dev);
3774         return 0;
3775 }
3776
3777 static void tegra_xhci_shutdown(struct platform_device *pdev)
3778 {
3779         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3780         struct xhci_hcd *xhci = NULL;
3781         struct usb_hcd *hcd = NULL;
3782
3783         if (tegra == NULL)
3784                 return;
3785
3786         if (tegra->hc_in_elpg) {
3787                 mutex_lock(&tegra->sync_lock);
3788                 pmc_init(tegra, 0);
3789                 mutex_unlock(&tegra->sync_lock);
3790         } else {
3791                 xhci = tegra->xhci;
3792                 hcd = xhci_to_hcd(xhci);
3793                 xhci_shutdown(hcd);
3794         }
3795 }
3796
3797 static struct platform_driver tegra_xhci_driver = {
3798         .probe  = tegra_xhci_probe,
3799         .remove = tegra_xhci_remove,
3800         .shutdown = tegra_xhci_shutdown,
3801 #ifdef CONFIG_PM
3802         .suspend = tegra_xhci_suspend,
3803         .resume  = tegra_xhci_resume,
3804 #endif
3805         .driver = {
3806                 .name = "tegra-xhci",
3807         },
3808 };
3809 MODULE_ALIAS("platform:tegra-xhci");
3810
3811 int tegra_xhci_register_plat(void)
3812 {
3813         return platform_driver_register(&tegra_xhci_driver);
3814 }
3815
3816 void tegra_xhci_unregister_plat(void)
3817 {
3818         platform_driver_unregister(&tegra_xhci_driver);
3819 }