xhci: tegra: fix a race during usb2 remote wakeup
[linux-3.10.git] / drivers / usb / host / xhci-tegra.c
1 /*
2  * xhci-tegra.c - Nvidia xHCI host controller driver
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/clk.h>
24 #include <linux/ioport.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irq.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/uaccess.h>
30 #include <linux/circ_buf.h>
31 #include <linux/vmalloc.h>
32 #include <linux/debugfs.h>
33 #include <linux/kthread.h>
34 #include <linux/gpio.h>
35
36 #include <mach/powergate.h>
37 #include <mach/clk.h>
38 #include <mach/tegra_usb_pad_ctrl.h>
39 #include <mach/tegra_usb_pmc.h>
40 #include <mach/pm_domains.h>
41 #include <mach/mc.h>
42 #include <mach/xusb.h>
43
44 #include "../../../arch/arm/mach-tegra/iomap.h" /* HACK -- remove */
45 #include "xhci-tegra.h"
46 #include "xhci.h"
47
48 /* macros */
49 #define FW_IOCTL_LOG_DEQUEUE_LOW        (4)
50 #define FW_IOCTL_LOG_DEQUEUE_HIGH       (5)
51 #define FW_IOCTL_DATA_SHIFT             (0)
52 #define FW_IOCTL_DATA_MASK              (0x00ffffff)
53 #define FW_IOCTL_TYPE_SHIFT             (24)
54 #define FW_IOCTL_TYPE_MASK              (0xff000000)
55 #define FW_LOG_SIZE                     (sizeof(struct log_entry))
56 #define FW_LOG_COUNT                    (4096)
57 #define FW_LOG_RING_SIZE                (FW_LOG_SIZE * FW_LOG_COUNT)
58 #define FW_LOG_PAYLOAD_SIZE             (27)
59 #define DRIVER                          (0x01)
60 #define CIRC_BUF_SIZE                   (4 * (1 << 20)) /* 4MB */
61 #define FW_LOG_THREAD_RELAX             (msecs_to_jiffies(100))
62
63 /* tegra_xhci_firmware_log.flags bits */
64 #define FW_LOG_CONTEXT_VALID            (0)
65 #define FW_LOG_FILE_OPENED              (1)
66
67 #define PAGE_SELECT_MASK                        0xFFFFFE00
68 #define PAGE_SELECT_SHIFT                       9
69 #define PAGE_OFFSET_MASK                        0x000001FF
70 #define CSB_PAGE_SELECT(_addr)                                          \
71         ({                                                              \
72                 typecheck(u32, _addr);                                  \
73                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
74         })
75 #define CSB_PAGE_OFFSET(_addr)                                          \
76         ({                                                              \
77                 typecheck(u32, _addr);                                  \
78                 (_addr & PAGE_OFFSET_MASK);                             \
79         })
80
81 #define reg_dump(_dev, _base, _reg)                                     \
82         dev_dbg(_dev, "%s: %s @%x = 0x%x\n", __func__, #_reg,           \
83                 _reg, readl(_base + _reg))
84
85 /* PMC register definition */
86 #define PMC_PORT_UTMIP_P0               0
87 #define PMC_PORT_UTMIP_P1               1
88 #define PMC_PORT_UTMIP_P2               2
89 #define PMC_PORT_UHSIC_P0               3
90 #define PMC_PORT_NUM                    4
91
92 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
93 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
94 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
95
96 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
97
98 /* private data types */
99 /* command requests from the firmware */
100 enum MBOX_CMD_TYPE {
101         MBOX_CMD_MSG_ENABLED = 1,
102         MBOX_CMD_INC_FALC_CLOCK,
103         MBOX_CMD_DEC_FALC_CLOCK,
104         MBOX_CMD_INC_SSPI_CLOCK,
105         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
106         MBOX_CMD_SET_BW,
107         MBOX_CMD_SET_SS_PWR_GATING,
108         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
109         MBOX_CMD_SAVE_DFE_CTLE_CTX,
110         MBOX_CMD_AIRPLANE_MODE_ENABLED,
111         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* 11 */
112         MBOX_CMD_STAR_HSIC_IDLE,
113         MBOX_CMD_STOP_HSIC_IDLE,
114
115         /* needs to be the last cmd */
116         MBOX_CMD_MAX,
117
118         /* resp msg to ack above commands */
119         MBOX_CMD_ACK = 128,
120         MBOX_CMD_NACK
121 };
122
123 struct log_entry {
124         u32 sequence_no;
125         u8 data[FW_LOG_PAYLOAD_SIZE];
126         u8 owner;
127 };
128
129 /* Usb3 Firmware Cfg Table */
130 struct cfgtbl {
131         u32 boot_loadaddr_in_imem;
132         u32 boot_codedfi_offset;
133         u32 boot_codetag;
134         u32 boot_codesize;
135
136         /* Physical memory reserved by Bootloader/BIOS */
137         u32 phys_memaddr;
138         u16 reqphys_memsize;
139         u16 alloc_phys_memsize;
140
141         /* .rodata section */
142         u32 rodata_img_offset;
143         u32 rodata_section_start;
144         u32 rodata_section_end;
145         u32 main_fnaddr;
146
147         u32 fwimg_cksum;
148         u32 fwimg_created_time;
149
150         /* Fields that get filled by linker during linking phase
151          * or initialized in the FW code.
152          */
153         u32 imem_resident_start;
154         u32 imem_resident_end;
155         u32 idirect_start;
156         u32 idirect_end;
157         u32 l2_imem_start;
158         u32 l2_imem_end;
159         u32 version_id;
160         u8 init_ddirect;
161         u8 reserved[3];
162         u32 phys_addr_log_buffer;
163         u32 total_log_entries;
164         u32 dequeue_ptr;
165
166         /*      Below two dummy variables are used to replace
167          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
168          *      retain the size of struct _CFG_TBL used by other AP/Module.
169          */
170         u32 dummy_var1;
171         u32 dummy_var2;
172
173         /* fwimg_len */
174         u32 fwimg_len;
175         u8 magic[8];
176         u32 SS_low_power_entry_timeout;
177         u8 num_hsic_port;
178         u8 padding[139]; /* padding bytes to makeup 256-bytes cfgtbl */
179 };
180
181 struct xusb_save_regs {
182         u32 msi_bar_sz;
183         u32 msi_axi_barst;
184         u32 msi_fpci_barst;
185         u32 msi_vec0;
186         u32 msi_en_vec0;
187         u32 fpci_error_masks;
188         u32 intr_mask;
189         u32 ipfs_intr_enable;
190         u32 ufpci_config;
191         u32 clkgate_hysteresis;
192         u32 xusb_host_mccif_fifo_cntrl;
193
194         /* PG does not mention below */
195         u32 hs_pls;
196         u32 fs_pls;
197         u32 hs_fs_speed;
198         u32 hs_fs_pp;
199         u32 cfg_aru;
200         u32 cfg_order;
201         u32 cfg_fladj;
202         u32 cfg_sid;
203         /* DFE and CTLE */
204         u32 tap1_val[2];
205         u32 amp_val[2];
206         u32 ctle_z_val[2];
207         u32 ctle_g_val[2];
208 };
209
210 struct tegra_xhci_firmware {
211         void *data; /* kernel virtual address */
212         size_t size; /* firmware size */
213         dma_addr_t dma; /* dma address for controller */
214 };
215
216 struct tegra_xhci_firmware_log {
217         dma_addr_t phys_addr;           /* dma-able address */
218         void *virt_addr;                /* kernel va of the shared log buffer */
219         struct log_entry *dequeue;      /* current dequeue pointer (va) */
220         struct circ_buf circ;           /* big circular buffer */
221         u32 seq;                        /* log sequence number */
222
223         struct task_struct *thread;     /* a thread to consume log */
224         struct mutex mutex;
225         wait_queue_head_t read_wait;
226         wait_queue_head_t write_wait;
227         wait_queue_head_t intr_wait;
228         struct dentry *path;
229         struct dentry *log_file;
230         unsigned long flags;
231 };
232
233 /* structure to hold the offsets of padctl registers */
234 struct tegra_xusb_padctl_regs {
235         u16 boot_media_0;
236         u16 usb2_pad_mux_0;
237         u16 usb2_port_cap_0;
238         u16 snps_oc_map_0;
239         u16 usb2_oc_map_0;
240         u16 ss_port_map_0;
241         u16 oc_det_0;
242         u16 elpg_program_0;
243         u16 usb2_bchrg_otgpad0_ctl0_0;
244         u16 usb2_bchrg_otgpad0_ctl1_0;
245         u16 usb2_bchrg_otgpad1_ctl0_0;
246         u16 usb2_bchrg_otgpad1_ctl1_0;
247         u16 usb2_bchrg_otgpad2_ctl0_0;
248         u16 usb2_bchrg_otgpad2_ctl1_0;
249         u16 usb2_bchrg_bias_pad_0;
250         u16 usb2_bchrg_tdcd_dbnc_timer_0;
251         u16 iophy_pll_p0_ctl1_0;
252         u16 iophy_pll_p0_ctl2_0;
253         u16 iophy_pll_p0_ctl3_0;
254         u16 iophy_pll_p0_ctl4_0;
255         u16 iophy_usb3_pad0_ctl1_0;
256         u16 iophy_usb3_pad1_ctl1_0;
257         u16 iophy_usb3_pad0_ctl2_0;
258         u16 iophy_usb3_pad1_ctl2_0;
259         u16 iophy_usb3_pad0_ctl3_0;
260         u16 iophy_usb3_pad1_ctl3_0;
261         u16 iophy_usb3_pad0_ctl4_0;
262         u16 iophy_usb3_pad1_ctl4_0;
263         u16 iophy_misc_pad_p0_ctl1_0;
264         u16 iophy_misc_pad_p1_ctl1_0;
265         u16 iophy_misc_pad_p0_ctl2_0;
266         u16 iophy_misc_pad_p1_ctl2_0;
267         u16 iophy_misc_pad_p0_ctl3_0;
268         u16 iophy_misc_pad_p1_ctl3_0;
269         u16 iophy_misc_pad_p0_ctl4_0;
270         u16 iophy_misc_pad_p1_ctl4_0;
271         u16 iophy_misc_pad_p0_ctl5_0;
272         u16 iophy_misc_pad_p1_ctl5_0;
273         u16 iophy_misc_pad_p0_ctl6_0;
274         u16 iophy_misc_pad_p1_ctl6_0;
275         u16 usb2_otg_pad0_ctl0_0;
276         u16 usb2_otg_pad1_ctl0_0;
277         u16 usb2_otg_pad2_ctl0_0;
278         u16 usb2_otg_pad0_ctl1_0;
279         u16 usb2_otg_pad1_ctl1_0;
280         u16 usb2_otg_pad2_ctl1_0;
281         u16 usb2_bias_pad_ctl0_0;
282         u16 usb2_bias_pad_ctl1_0;
283         u16 usb2_hsic_pad0_ctl0_0;
284         u16 usb2_hsic_pad1_ctl0_0;
285         u16 usb2_hsic_pad0_ctl1_0;
286         u16 usb2_hsic_pad1_ctl1_0;
287         u16 usb2_hsic_pad0_ctl2_0;
288         u16 usb2_hsic_pad1_ctl2_0;
289         u16 ulpi_link_trim_ctl0;
290         u16 ulpi_null_clk_trim_ctl0;
291         u16 hsic_strb_trim_ctl0;
292         u16 wake_ctl0;
293         u16 pm_spare0;
294         u16 iophy_misc_pad_p2_ctl1_0;
295         u16 iophy_misc_pad_p3_ctl1_0;
296         u16 iophy_misc_pad_p4_ctl1_0;
297         u16 iophy_misc_pad_p2_ctl2_0;
298         u16 iophy_misc_pad_p3_ctl2_0;
299         u16 iophy_misc_pad_p4_ctl2_0;
300         u16 iophy_misc_pad_p2_ctl3_0;
301         u16 iophy_misc_pad_p3_ctl3_0;
302         u16 iophy_misc_pad_p4_ctl3_0;
303         u16 iophy_misc_pad_p2_ctl4_0;
304         u16 iophy_misc_pad_p3_ctl4_0;
305         u16 iophy_misc_pad_p4_ctl4_0;
306         u16 iophy_misc_pad_p2_ctl5_0;
307         u16 iophy_misc_pad_p3_ctl5_0;
308         u16 iophy_misc_pad_p4_ctl5_0;
309         u16 iophy_misc_pad_p2_ctl6_0;
310         u16 iophy_misc_pad_p3_ctl6_0;
311         u16 iophy_misc_pad_p4_ctl6_0;
312         u16 usb3_pad_mux_0;
313         u16 iophy_pll_s0_ctl1_0;
314         u16 iophy_pll_s0_ctl2_0;
315         u16 iophy_pll_s0_ctl3_0;
316         u16 iophy_pll_s0_ctl4_0;
317         u16 iophy_misc_pad_s0_ctl1_0;
318         u16 iophy_misc_pad_s0_ctl2_0;
319         u16 iophy_misc_pad_s0_ctl3_0;
320         u16 iophy_misc_pad_s0_ctl4_0;
321         u16 iophy_misc_pad_s0_ctl5_0;
322         u16 iophy_misc_pad_s0_ctl6_0;
323 };
324
325 struct tegra_xhci_hcd {
326         struct platform_device *pdev;
327         struct xhci_hcd *xhci;
328         u16 device_id;
329
330         spinlock_t lock;
331         struct mutex sync_lock;
332
333         int smi_irq;
334         int padctl_irq;
335         int usb3_irq;
336         int usb2_irq;
337
338         bool ss_wake_event;
339         bool ss_pwr_gated;
340         bool host_pwr_gated;
341         bool hs_wake_event;
342         bool host_resume_req;
343         bool lp0_exit;
344         bool dfe_ctle_ctx_saved;
345         unsigned long last_jiffies;
346         unsigned long host_phy_base;
347         void __iomem *host_phy_virt_base;
348
349         void __iomem *padctl_base;
350         void __iomem *fpci_base;
351         void __iomem *ipfs_base;
352
353         struct tegra_xusb_platform_data *pdata;
354         struct tegra_xusb_board_data *bdata;
355         struct tegra_xusb_padctl_regs *padregs;
356
357         /* mailbox variables */
358         struct mutex mbox_lock;
359         u32 mbox_owner;
360         u32 cmd_type;
361         u32 cmd_data;
362
363         struct regulator *xusb_s5p0v_reg;
364         struct regulator *xusb_s5p0v1_reg;
365         struct regulator *xusb_s5p0v2_reg;
366         struct regulator *xusb_s1p05v_reg;
367         struct regulator *xusb_s3p3v_reg;
368         struct regulator *xusb_s1p8v_reg;
369         struct regulator *vddio_hsic_reg;
370         int vddio_hsic_refcnt;
371
372         struct work_struct mbox_work;
373         struct work_struct ss_elpg_exit_work;
374         struct work_struct host_elpg_exit_work;
375
376         struct clk *host_clk;
377         struct clk *ss_clk;
378
379         /* XUSB Falcon SuperSpeed Clock */
380         struct clk *falc_clk;
381
382         /* EMC Clock */
383         struct clk *emc_clk;
384         /* XUSB SS PI Clock */
385         struct clk *ss_src_clk;
386         /* PLLE Clock */
387         struct clk *plle_clk;
388         struct clk *pll_u_480M;
389         struct clk *clk_m;
390         /* refPLLE clk */
391         struct clk *pll_re_vco_clk;
392         /*
393          * XUSB/IPFS specific registers these need to be saved/restored in
394          * addition to spec defined registers
395          */
396         struct xusb_save_regs sregs;
397         bool usb2_rh_suspend;
398         bool usb3_rh_suspend;
399         bool hc_in_elpg;
400
401         unsigned long usb2_rh_remote_wakeup_ports; /* one bit per port */
402         unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
403         /* firmware loading related */
404         struct tegra_xhci_firmware firmware;
405
406         struct tegra_xhci_firmware_log log;
407 };
408
409 static struct tegra_usb_pmc_data pmc_data;
410 static struct tegra_usb_pmc_data pmc_hsic_data[XUSB_HSIC_COUNT];
411
412 /* functions */
413 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
414 {
415         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
416 }
417
418 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
419 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
420 {
421         WARN_ON(tegra->sync_lock.owner != current);
422 }
423 #else
424 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
425 #endif
426
427 static void tegra_xhci_setup_gpio_for_ss_lane(struct tegra_xhci_hcd *tegra)
428 {
429         int err = 0;
430
431         if (!tegra->bdata->gpio_controls_muxed_ss_lanes)
432                 return;
433
434         if (tegra->bdata->lane_owner & BIT(0)) {
435                 /* USB3_SS port1 is using SATA lane so set (MUX_SATA)
436                  * GPIO P11 to '0'
437                  */
438                 err = gpio_request((tegra->bdata->gpio_ss1_sata & 0xffff),
439                         "gpio_ss1_sata");
440                 if (err < 0)
441                         pr_err("%s: gpio_ss1_sata gpio_request failed %d\n",
442                                 __func__, err);
443                 err = gpio_direction_output((tegra->bdata->gpio_ss1_sata
444                         & 0xffff), 1);
445                 if (err < 0)
446                         pr_err("%s: gpio_ss1_sata gpio_direction failed %d\n",
447                                 __func__, err);
448                 __gpio_set_value((tegra->bdata->gpio_ss1_sata & 0xffff),
449                                 ((tegra->bdata->gpio_ss1_sata >> 16)));
450         }
451 }
452
453 static u32 xhci_read_portsc(struct xhci_hcd *xhci, unsigned int port)
454 {
455         int num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
456         __le32 __iomem *addr;
457
458         if (port >= num_ports) {
459                 xhci_err(xhci, "%s invalid port %u\n", __func__, port);
460                 return -1;
461         }
462
463         addr = &xhci->op_regs->port_status_base + (NUM_PORT_REGS * port);
464         return xhci_readl(xhci, addr);
465 }
466
467 static void debug_print_portsc(struct xhci_hcd *xhci)
468 {
469         __le32 __iomem *addr = &xhci->op_regs->port_status_base;
470         u32 reg;
471         int i;
472         int ports;
473
474         ports = HCS_MAX_PORTS(xhci->hcs_params1);
475         for (i = 0; i < ports; i++) {
476                 reg = xhci_read_portsc(xhci, i);
477                 xhci_dbg(xhci, "@%p port %d status reg = 0x%x\n",
478                                 addr, i, (unsigned int) reg);
479                 addr += NUM_PORT_REGS;
480         }
481 }
482 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra);
483
484 static void update_speed(struct tegra_xhci_hcd *tegra, u8 port, bool setup_wake)
485 {
486         struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
487         u32 portsc;
488
489         /* we don't need speed information to disable PMC */
490         if (!setup_wake)
491                 return;
492
493         portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port));
494         if (DEV_FULLSPEED(portsc))
495                 pmc_data.port_speed = USB_PMC_PORT_SPEED_FULL;
496         else if (DEV_HIGHSPEED(portsc))
497                 pmc_data.port_speed = USB_PMC_PORT_SPEED_HIGH;
498         else if (DEV_LOWSPEED(portsc))
499                 pmc_data.port_speed = USB_PMC_PORT_SPEED_LOW;
500         else if (DEV_SUPERSPEED(portsc))
501                 pmc_data.port_speed = USB_PMC_PORT_SPEED_SUPER;
502         else
503                 pmc_data.port_speed = USB_PMC_PORT_SPEED_UNKNOWN;
504 }
505
506 static void setup_wake_detect(bool setup_wake)
507 {
508         if (setup_wake)
509                 pmc_data.pmc_ops->setup_pmc_wake_detect(&pmc_data);
510         else
511                 pmc_data.pmc_ops->disable_pmc_bus_ctrl(&pmc_data, 0);
512 }
513
514 static void pmc_setup(struct tegra_xhci_hcd *tegra, bool setup_wake)
515 {
516         u32 portmap = tegra->bdata->portmap;
517
518         pmc_data.controller_type = TEGRA_USB_3_0;
519         if (portmap & TEGRA_XUSB_USB2_P0) {
520                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 0) & 0xf;
521                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
522                 update_speed(tegra, pmc_data.instance, setup_wake);
523                 tegra_usb_pmc_init(&pmc_data);
524                 setup_wake_detect(setup_wake);
525         }
526         if (portmap & TEGRA_XUSB_USB2_P1) {
527                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 4) & 0xf;
528                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
529                 update_speed(tegra, pmc_data.instance, setup_wake);
530                 tegra_usb_pmc_init(&pmc_data);
531                 setup_wake_detect(setup_wake);
532         }
533         if (portmap & TEGRA_XUSB_USB2_P2) {
534                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 8) & 0xf;
535                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
536                 update_speed(tegra, pmc_data.instance, setup_wake);
537                 tegra_usb_pmc_init(&pmc_data);
538                 setup_wake_detect(setup_wake);
539         }
540 }
541
542 static void pmc_init(struct tegra_xhci_hcd *tegra)
543 {
544         struct tegra_usb_pmc_data *pmc;
545         struct device *dev = &tegra->pdev->dev;
546         int pad;
547
548         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
549                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap) {
550                         dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
551
552                         pmc = &pmc_hsic_data[pad];
553                         pmc->instance = pad + 1;
554                         pmc->phy_type = TEGRA_USB_PHY_INTF_HSIC;
555                         pmc->port_speed = USB_PMC_PORT_SPEED_HIGH;
556                         pmc->controller_type = TEGRA_USB_3_0;
557                         tegra_usb_pmc_init(pmc);
558                 }
559         }
560
561 }
562
563 static void pmc_setup_wake_detect(struct tegra_xhci_hcd *tegra)
564 {
565         struct tegra_usb_pmc_data *pmc;
566         struct device *dev = &tegra->pdev->dev;
567         u32 portsc;
568         int port;
569         int pad;
570
571         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
572                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap) {
573                         dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
574
575                         pmc = &pmc_hsic_data[pad];
576                         port = hsic_pad_to_port(pad);
577                         portsc = xhci_read_portsc(tegra->xhci, port);
578                         dev_dbg(dev, "%s hsic pad %d portsc 0x%x\n",
579                                         __func__, pad, portsc);
580
581                         if (((int) portsc != -1) && (portsc & PORT_CONNECT))
582                                 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
583                 }
584         }
585 }
586
587 static void pmc_disable_bus_ctrl(struct tegra_xhci_hcd *tegra)
588 {
589         struct tegra_usb_pmc_data *pmc;
590         struct device *dev = &tegra->pdev->dev;
591         int pad;
592
593         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
594                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap) {
595                         dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
596
597                         pmc = &pmc_hsic_data[pad];
598                         pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
599                 }
600         }
601 }
602
603 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
604 {
605         void __iomem *fpci_base = tegra->fpci_base;
606         struct platform_device *pdev = tegra->pdev;
607         u32 input_addr;
608         u32 data;
609         u32 csb_page_select;
610
611         /* to select the appropriate CSB page to write to */
612         csb_page_select = CSB_PAGE_SELECT(addr);
613
614         dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
615                         csb_page_select);
616
617         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
618
619         /* selects the appropriate offset in the page to read from */
620         input_addr = CSB_PAGE_OFFSET(addr);
621         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
622
623         dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
624                         input_addr, data);
625         return data;
626 }
627
628 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
629 {
630         void __iomem *fpci_base = tegra->fpci_base;
631         struct platform_device *pdev = tegra->pdev;
632         u32 input_addr;
633         u32 csb_page_select;
634
635         /* to select the appropriate CSB page to write to */
636         csb_page_select = CSB_PAGE_SELECT(addr);
637
638         dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
639                         csb_page_select);
640
641         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
642
643         /* selects the appropriate offset in the page to write to */
644         input_addr = CSB_PAGE_OFFSET(addr);
645         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
646
647         dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
648                         input_addr, data);
649 }
650
651 /**
652  * fw_log_next - find next log entry in a tegra_xhci_firmware_log context.
653  *      This function takes care of wrapping. That means when current log entry
654  *      is the last one, it returns with the first one.
655  *
656  * @param log   The tegra_xhci_firmware_log context.
657  * @param this  The current log entry.
658  * @return      The log entry which is next to the current one.
659  */
660 static inline struct log_entry *fw_log_next(
661                 struct tegra_xhci_firmware_log *log, struct log_entry *this)
662 {
663         struct log_entry *first = (struct log_entry *) log->virt_addr;
664         struct log_entry *last = first + FW_LOG_COUNT - 1;
665
666         WARN((this < first) || (this > last), "%s: invalid input\n", __func__);
667
668         return (this == last) ? first : (this + 1);
669 }
670
671 /**
672  * fw_log_update_dequeue_pointer - update dequeue pointer to both firmware and
673  *      tegra_xhci_firmware_log.dequeue.
674  *
675  * @param log   The tegra_xhci_firmware_log context.
676  * @param n     Counts of log entries to fast-forward.
677  */
678 static inline void fw_log_update_deq_pointer(
679                 struct tegra_xhci_firmware_log *log, int n)
680 {
681         struct tegra_xhci_hcd *tegra =
682                         container_of(log, struct tegra_xhci_hcd, log);
683         struct device *dev = &tegra->pdev->dev;
684         struct log_entry *deq = tegra->log.dequeue;
685         dma_addr_t physical_addr;
686         u32 reg;
687
688         dev_dbg(dev, "curr 0x%p fast-forward %d entries\n", deq, n);
689         while (n-- > 0)
690                 deq = fw_log_next(log, deq);
691
692         tegra->log.dequeue = deq;
693         physical_addr = tegra->log.phys_addr +
694                         ((u8 *)deq - (u8 *)tegra->log.virt_addr);
695
696         /* update dequeue pointer to firmware */
697         reg = (FW_IOCTL_LOG_DEQUEUE_LOW << FW_IOCTL_TYPE_SHIFT);
698         reg |= (physical_addr & 0xffff); /* lower 16-bits */
699         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
700
701         reg = (FW_IOCTL_LOG_DEQUEUE_HIGH << FW_IOCTL_TYPE_SHIFT);
702         reg |= ((physical_addr >> 16) & 0xffff); /* higher 16-bits */
703         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
704
705         dev_dbg(dev, "new 0x%p physical addr 0x%x\n", deq, physical_addr);
706 }
707
708 static inline bool circ_buffer_full(struct circ_buf *circ)
709 {
710         int space = CIRC_SPACE(circ->head, circ->tail, CIRC_BUF_SIZE);
711
712         return (space <= FW_LOG_SIZE);
713 }
714
715 static inline bool fw_log_available(struct tegra_xhci_hcd *tegra)
716 {
717         return (tegra->log.dequeue->owner == DRIVER);
718 }
719
720 /**
721  * fw_log_wait_empty_timeout - wait firmware log thread to clean up shared
722  *      log buffer.
723  * @param tegra:        tegra_xhci_hcd context
724  * @param msec:         timeout value in millisecond
725  * @return true:        shared log buffer is empty,
726  *         false:       shared log buffer isn't empty.
727  */
728 static inline bool fw_log_wait_empty_timeout(struct tegra_xhci_hcd *tegra,
729                 unsigned timeout)
730 {
731         u32 target = jiffies + msecs_to_jiffies(timeout);
732         bool ret;
733
734         mutex_lock(&tegra->log.mutex);
735
736         while (fw_log_available(tegra) && time_is_after_jiffies(target)) {
737                 mutex_unlock(&tegra->log.mutex);
738                 usleep_range(1000, 2000);
739                 mutex_lock(&tegra->log.mutex);
740         }
741
742         ret = fw_log_available(tegra);
743         mutex_unlock(&tegra->log.mutex);
744
745         return ret;
746 }
747
748 /**
749  * fw_log_copy - copy firmware log from device's buffer to driver's circular
750  *      buffer.
751  * @param tegra tegra_xhci_hcd context
752  * @return true,        We still have firmware log in device's buffer to copy.
753  *                      This function returned due the driver's circular buffer
754  *                      is full. Caller should invoke this function again as
755  *                      soon as there is space in driver's circular buffer.
756  *         false,       Device's buffer is empty.
757  */
758 static inline bool fw_log_copy(struct tegra_xhci_hcd *tegra)
759 {
760         struct device *dev = &tegra->pdev->dev;
761         struct circ_buf *circ = &tegra->log.circ;
762         int head, tail;
763         int buffer_len, copy_len;
764         struct log_entry *entry;
765         struct log_entry *first = tegra->log.virt_addr;
766
767         while (fw_log_available(tegra)) {
768
769                 /* calculate maximum contiguous driver buffer length */
770                 head = circ->head;
771                 tail = ACCESS_ONCE(circ->tail);
772                 buffer_len = CIRC_SPACE_TO_END(head, tail, CIRC_BUF_SIZE);
773                 /* round down to FW_LOG_SIZE */
774                 buffer_len -= (buffer_len % FW_LOG_SIZE);
775                 if (!buffer_len)
776                         return true; /* log available but no space left */
777
778                 /* calculate maximum contiguous log copy length */
779                 entry = tegra->log.dequeue;
780                 copy_len = 0;
781                 do {
782                         if (tegra->log.seq != entry->sequence_no) {
783                                 dev_warn(dev,
784                                 "%s: discontinuous seq no, expect %u get %u\n",
785                                 __func__, tegra->log.seq, entry->sequence_no);
786                         }
787                         tegra->log.seq = entry->sequence_no + 1;
788
789                         copy_len += FW_LOG_SIZE;
790                         buffer_len -= FW_LOG_SIZE;
791                         if (!buffer_len)
792                                 break; /* no space left */
793                         entry = fw_log_next(&tegra->log, entry);
794                 } while ((entry->owner == DRIVER) && (entry != first));
795
796                 memcpy(&circ->buf[head], tegra->log.dequeue, copy_len);
797                 memset(tegra->log.dequeue, 0, copy_len);
798                 circ->head = (circ->head + copy_len) & (CIRC_BUF_SIZE - 1);
799
800                 mb();
801
802                 fw_log_update_deq_pointer(&tegra->log, copy_len/FW_LOG_SIZE);
803
804                 dev_dbg(dev, "copied %d entries, new dequeue 0x%p\n",
805                                 copy_len/FW_LOG_SIZE, tegra->log.dequeue);
806                 wake_up_interruptible(&tegra->log.read_wait);
807         }
808
809         return false;
810 }
811
812 static int fw_log_thread(void *data)
813 {
814         struct tegra_xhci_hcd *tegra = data;
815         struct device *dev = &tegra->pdev->dev;
816         struct circ_buf *circ = &tegra->log.circ;
817         bool logs_left;
818
819         dev_dbg(dev, "start firmware log thread\n");
820
821         do {
822                 mutex_lock(&tegra->log.mutex);
823                 if (circ_buffer_full(circ)) {
824                         mutex_unlock(&tegra->log.mutex);
825                         dev_info(dev, "%s: circ buffer full\n", __func__);
826                         wait_event_interruptible(tegra->log.write_wait,
827                             kthread_should_stop() || !circ_buffer_full(circ));
828                         mutex_lock(&tegra->log.mutex);
829                 }
830
831                 logs_left = fw_log_copy(tegra);
832                 mutex_unlock(&tegra->log.mutex);
833
834                 /* relax if no logs left  */
835                 if (!logs_left)
836                         wait_event_interruptible_timeout(tegra->log.intr_wait,
837                                 fw_log_available(tegra), FW_LOG_THREAD_RELAX);
838         } while (!kthread_should_stop());
839
840         dev_dbg(dev, "stop firmware log thread\n");
841         return 0;
842 }
843
844 static inline bool circ_buffer_empty(struct circ_buf *circ)
845 {
846         return (CIRC_CNT(circ->head, circ->tail, CIRC_BUF_SIZE) == 0);
847 }
848
849 static ssize_t fw_log_file_read(struct file *file, char __user *buf,
850                 size_t count, loff_t *offp)
851 {
852         struct tegra_xhci_hcd *tegra = file->private_data;
853         struct platform_device *pdev = tegra->pdev;
854         struct circ_buf *circ = &tegra->log.circ;
855         int head, tail;
856         size_t n = 0;
857         int s;
858
859         mutex_lock(&tegra->log.mutex);
860
861         while (circ_buffer_empty(circ)) {
862                 mutex_unlock(&tegra->log.mutex);
863                 if (file->f_flags & O_NONBLOCK)
864                         return -EAGAIN; /* non-blocking read */
865
866                 dev_dbg(&pdev->dev, "%s: nothing to read\n", __func__);
867
868                 if (wait_event_interruptible(tegra->log.read_wait,
869                                 !circ_buffer_empty(circ)))
870                         return -ERESTARTSYS;
871
872                 if (mutex_lock_interruptible(&tegra->log.mutex))
873                         return -ERESTARTSYS;
874         }
875
876         while (count > 0) {
877                 head = ACCESS_ONCE(circ->head);
878                 tail = circ->tail;
879                 s = min_t(int, count,
880                                 CIRC_CNT_TO_END(head, tail, CIRC_BUF_SIZE));
881
882                 if (s > 0) {
883                         if (copy_to_user(&buf[n], &circ->buf[tail], s)) {
884                                 dev_warn(&pdev->dev, "copy_to_user failed\n");
885                                 mutex_unlock(&tegra->log.mutex);
886                                 return -EFAULT;
887                         }
888                         circ->tail = (circ->tail + s) & (CIRC_BUF_SIZE - 1);
889
890                         count -= s;
891                         n += s;
892                 } else
893                         break;
894         }
895
896         mutex_unlock(&tegra->log.mutex);
897
898         wake_up_interruptible(&tegra->log.write_wait);
899
900         dev_dbg(&pdev->dev, "%s: %d bytes\n", __func__, n);
901
902         return n;
903 }
904
905 static int fw_log_file_open(struct inode *inode, struct file *file)
906 {
907         struct tegra_xhci_hcd *tegra;
908         file->private_data = inode->i_private;
909         tegra = file->private_data;
910
911         if (test_and_set_bit(FW_LOG_FILE_OPENED, &tegra->log.flags)) {
912                 dev_info(&tegra->pdev->dev, "%s: already opened\n", __func__);
913                 return -EBUSY;
914         }
915
916         return 0;
917 }
918
919 static int fw_log_file_close(struct inode *inode, struct file *file)
920 {
921         struct tegra_xhci_hcd *tegra = file->private_data;
922
923         clear_bit(FW_LOG_FILE_OPENED, &tegra->log.flags);
924
925         return 0;
926 }
927
928 static const struct file_operations firmware_log_fops = {
929                 .open           = fw_log_file_open,
930                 .release        = fw_log_file_close,
931                 .read           = fw_log_file_read,
932                 .owner          = THIS_MODULE,
933 };
934
935 static int fw_log_init(struct tegra_xhci_hcd *tegra)
936 {
937         struct platform_device *pdev = tegra->pdev;
938         int rc = 0;
939
940         /* allocate buffer to be shared between driver and firmware */
941         tegra->log.virt_addr = dma_alloc_writecombine(&pdev->dev,
942                         FW_LOG_RING_SIZE, &tegra->log.phys_addr, GFP_KERNEL);
943
944         if (!tegra->log.virt_addr) {
945                 dev_err(&pdev->dev, "dma_alloc_writecombine() size %d failed\n",
946                                 FW_LOG_RING_SIZE);
947                 return -ENOMEM;
948         }
949
950         dev_info(&pdev->dev, "%d bytes log buffer physical 0x%u virtual 0x%p\n",
951                 FW_LOG_RING_SIZE, tegra->log.phys_addr, tegra->log.virt_addr);
952
953         memset(tegra->log.virt_addr, 0, FW_LOG_RING_SIZE);
954         tegra->log.dequeue = tegra->log.virt_addr;
955
956         tegra->log.circ.buf = vmalloc(CIRC_BUF_SIZE);
957         if (!tegra->log.circ.buf) {
958                 dev_err(&pdev->dev, "vmalloc size %d failed\n", CIRC_BUF_SIZE);
959                 rc = -ENOMEM;
960                 goto error_free_dma;
961         }
962
963         tegra->log.circ.head = 0;
964         tegra->log.circ.tail = 0;
965
966         init_waitqueue_head(&tegra->log.read_wait);
967         init_waitqueue_head(&tegra->log.write_wait);
968         init_waitqueue_head(&tegra->log.intr_wait);
969
970         mutex_init(&tegra->log.mutex);
971
972         tegra->log.path = debugfs_create_dir("tegra_xhci", NULL);
973         if (IS_ERR_OR_NULL(tegra->log.path)) {
974                 dev_warn(&pdev->dev, "debugfs_create_dir() failed\n");
975                 rc = -ENOMEM;
976                 goto error_free_mem;
977         }
978
979         tegra->log.log_file = debugfs_create_file("firmware_log",
980                         S_IRUGO, tegra->log.path, tegra, &firmware_log_fops);
981         if ((!tegra->log.log_file) ||
982                         (tegra->log.log_file == ERR_PTR(-ENODEV))) {
983                 dev_warn(&pdev->dev, "debugfs_create_file() failed\n");
984                 rc = -ENOMEM;
985                 goto error_remove_debugfs_path;
986         }
987
988         tegra->log.thread = kthread_run(fw_log_thread, tegra, "xusb-fw-log");
989         if (IS_ERR(tegra->log.thread)) {
990                 dev_warn(&pdev->dev, "kthread_run() failed\n");
991                 rc = -ENOMEM;
992                 goto error_remove_debugfs_file;
993         }
994
995         set_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags);
996         return rc;
997
998 error_remove_debugfs_file:
999         debugfs_remove(tegra->log.log_file);
1000 error_remove_debugfs_path:
1001         debugfs_remove(tegra->log.path);
1002 error_free_mem:
1003         vfree(tegra->log.circ.buf);
1004 error_free_dma:
1005         dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1006                         tegra->log.virt_addr, tegra->log.phys_addr);
1007         memset(&tegra->log, sizeof(tegra->log), 0);
1008         return rc;
1009 }
1010
1011 static void fw_log_deinit(struct tegra_xhci_hcd *tegra)
1012 {
1013         struct platform_device *pdev = tegra->pdev;
1014
1015         if (test_and_clear_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
1016
1017                 debugfs_remove(tegra->log.log_file);
1018                 debugfs_remove(tegra->log.path);
1019
1020                 wake_up_interruptible(&tegra->log.read_wait);
1021                 wake_up_interruptible(&tegra->log.write_wait);
1022                 kthread_stop(tegra->log.thread);
1023
1024                 mutex_lock(&tegra->log.mutex);
1025                 dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1026                         tegra->log.virt_addr, tegra->log.phys_addr);
1027                 vfree(tegra->log.circ.buf);
1028                 tegra->log.circ.head = tegra->log.circ.tail = 0;
1029                 mutex_unlock(&tegra->log.mutex);
1030
1031                 mutex_destroy(&tegra->log.mutex);
1032         }
1033 }
1034
1035 /* hsic pad operations */
1036 /*
1037  * HSIC pads need VDDIO_HSIC power rail turned on to be functional. There is
1038  * only one VDDIO_HSIC power rail shared by all HSIC pads.
1039  */
1040 static int hsic_power_rail_enable(struct tegra_xhci_hcd *tegra)
1041 {
1042         struct device *dev = &tegra->pdev->dev;
1043         struct tegra_xusb_regulator_name *supply = &tegra->pdata->bdata->supply;
1044         int ret;
1045
1046         if (tegra->vddio_hsic_reg)
1047                 goto done;
1048
1049         tegra->vddio_hsic_reg = devm_regulator_get(dev, supply->vddio_hsic);
1050         if (IS_ERR_OR_NULL(tegra->vddio_hsic_reg)) {
1051                 dev_err(dev, "%s get vddio_hsic failed\n", __func__);
1052                 ret = PTR_ERR(tegra->vddio_hsic_reg);
1053                 goto get_failed;
1054         }
1055
1056         dev_dbg(dev, "%s regulator_enable vddio_hsic\n", __func__);
1057         ret = regulator_enable(tegra->vddio_hsic_reg);
1058         if (ret < 0) {
1059                 dev_err(dev, "%s enable vddio_hsic failed\n", __func__);
1060                 goto enable_failed;
1061         }
1062
1063 done:
1064         tegra->vddio_hsic_refcnt++;
1065         WARN(tegra->vddio_hsic_refcnt > XUSB_HSIC_COUNT,
1066                         "vddio_hsic_refcnt exceeds\n");
1067         return 0;
1068
1069 enable_failed:
1070         devm_regulator_put(tegra->vddio_hsic_reg);
1071 get_failed:
1072         tegra->vddio_hsic_reg = NULL;
1073         return ret;
1074 }
1075
1076 static int hsic_power_rail_disable(struct tegra_xhci_hcd *tegra)
1077 {
1078         struct device *dev = &tegra->pdev->dev;
1079         int ret;
1080
1081         WARN_ON(!tegra->vddio_hsic_reg || !tegra->vddio_hsic_refcnt);
1082
1083         tegra->vddio_hsic_refcnt--;
1084         if (tegra->vddio_hsic_refcnt)
1085                 return 0;
1086
1087         dev_dbg(dev, "%s regulator_disable vddio_hsic\n", __func__);
1088         ret = regulator_disable(tegra->vddio_hsic_reg);
1089         if (ret < 0) {
1090                 dev_err(dev, "%s disable vddio_hsic failed\n", __func__);
1091                 tegra->vddio_hsic_refcnt++;
1092                 return ret;
1093         }
1094
1095         devm_regulator_put(tegra->vddio_hsic_reg);
1096         tegra->vddio_hsic_reg = NULL;
1097
1098         return 0;
1099 }
1100
1101 static int hsic_pad_enable(struct tegra_xhci_hcd *tegra, unsigned pad)
1102 {
1103         struct device *dev = &tegra->pdev->dev;
1104         void __iomem *base = tegra->padctl_base;
1105         struct tegra_xusb_hsic_config *hsic = &tegra->bdata->hsic;
1106         u32 reg;
1107
1108         if (pad >= XUSB_HSIC_COUNT) {
1109                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1110                 return -EINVAL;
1111         }
1112
1113         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1114
1115         reg = readl(base + HSIC_PAD_CTL_2(pad));
1116         reg &= ~(RX_STROBE_TRIM(~0) | RX_DATA_TRIM(~0));
1117         reg |= RX_STROBE_TRIM(hsic->rx_strobe_trim);
1118         reg |= RX_DATA_TRIM(hsic->rx_data_trim);
1119         writel(reg, base + HSIC_PAD_CTL_2(pad));
1120
1121         reg = readl(base + HSIC_PAD_CTL_0(pad));
1122         reg &= ~(TX_RTUNEP(~0) | TX_RTUNEN(~0) | TX_SLEWP(~0) | TX_SLEWN(~0));
1123         reg |= TX_RTUNEP(hsic->tx_rtune_p);
1124         reg |= TX_RTUNEN(hsic->tx_rtune_n);
1125         reg |= TX_SLEWP(hsic->tx_slew_p);
1126         reg |= TX_SLEWN(hsic->tx_slew_n);
1127         writel(reg, base + HSIC_PAD_CTL_0(pad));
1128
1129         reg = readl(base + HSIC_PAD_CTL_1(pad));
1130         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1131         reg |= (RPD_DATA | RPU_STROBE); /* keep HSIC in IDLE */
1132         if (hsic->auto_term_en)
1133                 reg |= AUTO_TERM_EN;
1134         else
1135                 reg &= ~AUTO_TERM_EN;
1136         reg &= ~(PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1137         writel(reg, base + HSIC_PAD_CTL_1(pad));
1138
1139         reg = readl(base + HSIC_STRB_TRIM_CONTROL);
1140         reg &= ~(STRB_TRIM_VAL(~0));
1141         reg |= STRB_TRIM_VAL(hsic->strb_trim_val);
1142         writel(reg, base + HSIC_STRB_TRIM_CONTROL);
1143
1144         reg = readl(base + USB2_PAD_MUX);
1145         reg |= USB2_HSIC_PAD_PORT(pad);
1146         writel(reg, base + USB2_PAD_MUX);
1147
1148         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1149         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1150         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1151         reg_dump(dev, base, HSIC_STRB_TRIM_CONTROL);
1152         reg_dump(dev, base, USB2_PAD_MUX);
1153         return 0;
1154 }
1155
1156 static int hsic_pad_disable(struct tegra_xhci_hcd *tegra, unsigned pad)
1157 {
1158         struct device *dev = &tegra->pdev->dev;
1159         void __iomem *base = tegra->padctl_base;
1160         u32 reg;
1161
1162         if (pad >= XUSB_HSIC_COUNT) {
1163                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1164                 return -EINVAL;
1165         }
1166
1167         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1168
1169         reg = readl(base + USB2_PAD_MUX);
1170         reg &= ~USB2_HSIC_PAD_PORT(pad);
1171         writel(reg, base + USB2_PAD_MUX);
1172
1173         reg = readl(base + HSIC_PAD_CTL_1(pad));
1174         reg |= (PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1175         writel(reg, base + HSIC_PAD_CTL_1(pad));
1176
1177         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1178         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1179         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1180         reg_dump(dev, base, USB2_PAD_MUX);
1181         return 0;
1182 }
1183
1184 enum hsic_pad_pupd {
1185         PUPD_DISABLE = 0,
1186         PUPD_IDLE,
1187         PUPD_RESET
1188 };
1189
1190 static int hsic_pad_pupd_set(struct tegra_xhci_hcd *tegra, unsigned pad,
1191         enum hsic_pad_pupd pupd)
1192 {
1193         struct device *dev = &tegra->pdev->dev;
1194         void __iomem *base = tegra->padctl_base;
1195         u32 reg;
1196
1197         if (pad >= XUSB_HSIC_COUNT) {
1198                 dev_err(dev, "%s invalid HSIC pad number %u\n", __func__, pad);
1199                 return -EINVAL;
1200         }
1201
1202         dev_dbg(dev, "%s pad %u pupd %d\n", __func__, pad, pupd);
1203
1204         reg = readl(base + HSIC_PAD_CTL_1(pad));
1205         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1206
1207         if (pupd == PUPD_IDLE)
1208                 reg |= (RPD_DATA | RPU_STROBE);
1209         else if (pupd == PUPD_RESET)
1210                 reg |= (RPD_DATA | RPD_STROBE);
1211         else if (pupd != PUPD_DISABLE) {
1212                 dev_err(dev, "%s invalid pupd %d\n", __func__, pupd);
1213                 return -EINVAL;
1214         }
1215
1216         writel(reg, base + HSIC_PAD_CTL_1(pad));
1217
1218         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1219
1220         return 0;
1221 }
1222
1223
1224 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
1225 {
1226         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1227         struct xhci_hcd *xhci = tegra->xhci;
1228         u32 reg;
1229
1230         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
1231         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1232         xhci_info(xhci, " PAD MUX = %x\n", reg);
1233         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1234         xhci_info(xhci, " PORT CAP = %x\n", reg);
1235         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1236         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
1237         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1238         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
1239         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1240         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
1241         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1242         xhci_info(xhci, " OC DET 0= %x\n", reg);
1243         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad0_ctl2_0);
1244         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
1245         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad1_ctl2_0);
1246         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
1247         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl0_0);
1248         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
1249         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl0_0);
1250         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
1251         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl1_0);
1252         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
1253         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl1_0);
1254         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
1255         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1256         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
1257         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad0_ctl0_0);
1258         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
1259         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad1_ctl0_0);
1260         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
1261         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
1262 }
1263
1264 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
1265 {
1266         u32 reg;
1267
1268         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1269         reg |= IPFS_EN_FPCI;
1270         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1271         udelay(10);
1272
1273         /* Program Bar0 Space */
1274         reg = readl(tegra->fpci_base + XUSB_CFG_4);
1275         reg |= tegra->host_phy_base;
1276         writel(reg, tegra->fpci_base + XUSB_CFG_4);
1277         usleep_range(100, 200);
1278
1279         /* Enable Bus Master */
1280         reg = readl(tegra->fpci_base + XUSB_CFG_1);
1281         reg |= 0x7;
1282         writel(reg, tegra->fpci_base + XUSB_CFG_1);
1283
1284         /* Set intr mask to enable intr assertion */
1285         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1286         reg |= IPFS_IP_INT_MASK;
1287         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1288
1289         /* Set hysteris to 0x80 */
1290         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1291 }
1292
1293 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
1294                 struct platform_device *pdev)
1295 {
1296         struct tegra_xusb_regulator_name *supply = &tegra->bdata->supply;
1297         int err = 0;
1298
1299         tegra->xusb_s3p3v_reg =
1300                         devm_regulator_get(&pdev->dev, supply->s3p3v);
1301         if (IS_ERR(tegra->xusb_s3p3v_reg)) {
1302                 dev_err(&pdev->dev, "3p3v: regulator not found: %ld."
1303                         , PTR_ERR(tegra->xusb_s3p3v_reg));
1304                 err = PTR_ERR(tegra->xusb_s3p3v_reg);
1305                 goto err_null_regulator;
1306         } else {
1307                 err = regulator_enable(tegra->xusb_s3p3v_reg);
1308                 if (err < 0) {
1309                         dev_err(&pdev->dev,
1310                                 "3p3v: regulator enable failed:%d\n", err);
1311                         goto err_null_regulator;
1312                 }
1313         }
1314
1315         tegra->xusb_s5p0v_reg = devm_regulator_get(&pdev->dev, supply->s5p0v);
1316         if (IS_ERR(tegra->xusb_s5p0v_reg)) {
1317                 dev_err(&pdev->dev, "5p0v regulator not found: %ld."
1318                         , PTR_ERR(tegra->xusb_s5p0v_reg));
1319                 err = PTR_ERR(tegra->xusb_s5p0v_reg);
1320                 goto err_put_s3p3v_reg;
1321         } else {
1322                 err = regulator_enable(tegra->xusb_s5p0v_reg);
1323                 if (err < 0) {
1324                         dev_err(&pdev->dev,
1325                                 "5p0v: regulator enable failed:%d\n", err);
1326                         goto err_put_s3p3v_reg;
1327                 }
1328         }
1329
1330         tegra->xusb_s1p8v_reg =
1331                 devm_regulator_get(&pdev->dev, supply->s1p8v);
1332         if (IS_ERR(tegra->xusb_s1p8v_reg)) {
1333                 dev_err(&pdev->dev, "1p8v regulator not found: %ld."
1334                         , PTR_ERR(tegra->xusb_s1p8v_reg));
1335                 err = PTR_ERR(tegra->xusb_s1p8v_reg);
1336                 goto err_put_s5p0v_reg;
1337         } else {
1338                 err = regulator_enable(tegra->xusb_s1p8v_reg);
1339                 if (err < 0) {
1340                         dev_err(&pdev->dev,
1341                         "1p8v: regulator enable failed:%d\n", err);
1342                         goto err_put_s5p0v_reg;
1343                 }
1344         }
1345
1346         tegra->xusb_s1p05v_reg =
1347                         devm_regulator_get(&pdev->dev, supply->s1p05v);
1348         if (IS_ERR(tegra->xusb_s1p05v_reg)) {
1349                 dev_err(&pdev->dev, "1p05v: regulator not found: %ld."
1350                         , PTR_ERR(tegra->xusb_s1p05v_reg));
1351                 err = PTR_ERR(tegra->xusb_s1p05v_reg);
1352                 goto err_put_s1p8v_reg;
1353         } else {
1354                 err = regulator_enable(tegra->xusb_s1p05v_reg);
1355                 if (err < 0) {
1356                         dev_err(&pdev->dev,
1357                         "1p05v: regulator enable failed:%d\n", err);
1358                         goto err_put_s1p8v_reg;
1359                 }
1360         }
1361
1362         if (tegra->bdata->uses_different_vbus_per_port) {
1363                 tegra->xusb_s5p0v1_reg = devm_regulator_get(&pdev->dev,
1364                                                 supply->s5p0v1);
1365                 if (IS_ERR(tegra->xusb_s5p0v1_reg)) {
1366                         dev_err(&pdev->dev, "5p0v1 regulator not found: %ld."
1367                                 , PTR_ERR(tegra->xusb_s5p0v1_reg));
1368                         err = PTR_ERR(tegra->xusb_s5p0v1_reg);
1369                         goto err_put_s1p05v_reg;
1370                 } else {
1371                         err = regulator_enable(tegra->xusb_s5p0v1_reg);
1372                         if (err < 0) {
1373                                 dev_err(&pdev->dev,
1374                                 "5p0v1: regulator enable failed:%d\n", err);
1375                                 goto err_put_s1p05v_reg;
1376                         }
1377                 }
1378
1379                 tegra->xusb_s5p0v2_reg = devm_regulator_get(&pdev->dev,
1380                                                 supply->s5p0v2);
1381                 if (IS_ERR(tegra->xusb_s5p0v2_reg)) {
1382                         dev_err(&pdev->dev, "5p0v2 regulator not found: %ld."
1383                                 , PTR_ERR(tegra->xusb_s5p0v2_reg));
1384                         err = PTR_ERR(tegra->xusb_s5p0v2_reg);
1385                         goto err_put_s1p5v1_reg;
1386                 } else {
1387                         err = regulator_enable(tegra->xusb_s5p0v2_reg);
1388                         if (err < 0) {
1389                                 dev_err(&pdev->dev,
1390                                 "5p0v2: regulator enable failed:%d\n", err);
1391                                 goto err_put_s1p5v1_reg;
1392                         }
1393                 }
1394         }
1395         return err;
1396
1397 err_put_s1p5v1_reg:
1398         if (tegra->bdata->uses_different_vbus_per_port)
1399                 regulator_disable(tegra->xusb_s5p0v1_reg);
1400 err_put_s1p05v_reg:
1401         regulator_disable(tegra->xusb_s1p05v_reg);
1402 err_put_s1p8v_reg:
1403         regulator_disable(tegra->xusb_s1p8v_reg);
1404 err_put_s5p0v_reg:
1405         regulator_disable(tegra->xusb_s5p0v_reg);
1406 err_put_s3p3v_reg:
1407         regulator_disable(tegra->xusb_s3p3v_reg);
1408 err_null_regulator:
1409         tegra->xusb_s5p0v_reg = NULL;
1410         tegra->xusb_s5p0v1_reg = NULL;
1411         tegra->xusb_s5p0v2_reg = NULL;
1412         tegra->xusb_s1p05v_reg = NULL;
1413         tegra->xusb_s3p3v_reg = NULL;
1414         tegra->xusb_s1p8v_reg = NULL;
1415         return err;
1416 }
1417
1418 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
1419 {
1420         regulator_disable(tegra->xusb_s1p05v_reg);
1421         regulator_disable(tegra->xusb_s1p8v_reg);
1422         regulator_disable(tegra->xusb_s5p0v_reg);
1423         regulator_disable(tegra->xusb_s3p3v_reg);
1424         if (tegra->bdata->uses_different_vbus_per_port) {
1425                 regulator_disable(tegra->xusb_s5p0v1_reg);
1426                 regulator_disable(tegra->xusb_s5p0v2_reg);
1427         }
1428
1429         tegra->xusb_s1p05v_reg = NULL;
1430         tegra->xusb_s1p8v_reg = NULL;
1431         tegra->xusb_s5p0v_reg = NULL;
1432         tegra->xusb_s5p0v1_reg = NULL;
1433         tegra->xusb_s5p0v2_reg = NULL;
1434         tegra->xusb_s3p3v_reg = NULL;
1435 }
1436
1437 /*
1438  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
1439  * are under hardware control
1440  */
1441 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
1442 {
1443         struct platform_device *pdev = tegra->pdev;
1444         int err = 0;
1445
1446         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
1447         if (IS_ERR(tegra->plle_clk)) {
1448                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
1449                 err = PTR_ERR(tegra->plle_clk);
1450                 return err;
1451         }
1452         err = clk_enable(tegra->plle_clk);
1453         if (err) {
1454                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
1455                         __func__);
1456                 return err;
1457         }
1458
1459         return err;
1460 }
1461
1462 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
1463 {
1464         clk_disable(tegra->plle_clk);
1465         tegra->plle_clk = NULL;
1466 }
1467
1468 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
1469 {
1470         struct platform_device *pdev = tegra->pdev;
1471         int err = 0;
1472
1473         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
1474         if (IS_ERR(tegra->emc_clk)) {
1475                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
1476                 return PTR_ERR(tegra->emc_clk);
1477         }
1478
1479         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1480                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
1481                 if (IS_ERR(tegra->pll_re_vco_clk)) {
1482                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
1483                         err = PTR_ERR(tegra->pll_re_vco_clk);
1484                         goto get_pll_re_vco_clk_failed;
1485                 }
1486         }
1487
1488         /* get the clock handle of 120MHz clock source */
1489         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
1490         if (IS_ERR(tegra->pll_u_480M)) {
1491                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
1492                 err = PTR_ERR(tegra->pll_u_480M);
1493                 goto get_pll_u_480M_failed;
1494         }
1495
1496         /* get the clock handle of 12MHz clock source */
1497         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1498         if (IS_ERR(tegra->clk_m)) {
1499                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
1500                 err = PTR_ERR(tegra->clk_m);
1501                 goto clk_get_clk_m_failed;
1502         }
1503
1504         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
1505         if (IS_ERR(tegra->ss_src_clk)) {
1506                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
1507                 err = PTR_ERR(tegra->ss_src_clk);
1508                 tegra->ss_src_clk = NULL;
1509                 goto get_ss_src_clk_failed;
1510         }
1511
1512         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
1513         if (IS_ERR(tegra->host_clk)) {
1514                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
1515                 err = PTR_ERR(tegra->host_clk);
1516                 tegra->host_clk = NULL;
1517                 goto get_host_clk_failed;
1518         }
1519
1520         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
1521         if (IS_ERR(tegra->ss_clk)) {
1522                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
1523                 err = PTR_ERR(tegra->ss_clk);
1524                 tegra->ss_clk = NULL;
1525                 goto get_ss_clk_failed;
1526         }
1527
1528         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1529                 err = clk_enable(tegra->pll_re_vco_clk);
1530                 if (err) {
1531                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
1532                         goto enable_pll_re_vco_clk_failed;
1533                 }
1534         }
1535         return 0;
1536
1537 enable_pll_re_vco_clk_failed:
1538         tegra->ss_clk = NULL;
1539
1540 get_ss_clk_failed:
1541         tegra->host_clk = NULL;
1542
1543 get_host_clk_failed:
1544         tegra->ss_src_clk = NULL;
1545
1546 get_ss_src_clk_failed:
1547         tegra->clk_m = NULL;
1548
1549 clk_get_clk_m_failed:
1550         tegra->pll_u_480M = NULL;
1551
1552 get_pll_u_480M_failed:
1553         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1554                 tegra->pll_re_vco_clk = NULL;
1555
1556 get_pll_re_vco_clk_failed:
1557         tegra->emc_clk = NULL;
1558
1559         return err;
1560 }
1561
1562 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
1563 {
1564         clk_disable(tegra->ss_clk);
1565         clk_disable(tegra->host_clk);
1566         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1567                 clk_disable(tegra->pll_re_vco_clk);
1568         tegra->ss_clk = NULL;
1569         tegra->host_clk = NULL;
1570         tegra->ss_src_clk = NULL;
1571         tegra->clk_m = NULL;
1572         tegra->pll_u_480M = NULL;
1573         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1574                 tegra->pll_re_vco_clk = NULL;
1575 }
1576
1577 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
1578         bool enable)
1579 {
1580         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1581         u32 reg;
1582
1583         /* Issue is only applicable for T114 */
1584         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
1585                 return;
1586
1587         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1588                 reg = readl(tegra->padctl_base +
1589                         padregs->iophy_misc_pad_p0_ctl3_0);
1590                 if (enable) {
1591                         reg &= ~RX_IDLE_MODE;
1592                         reg |= RX_IDLE_MODE_OVRD;
1593                 } else {
1594                         reg |= RX_IDLE_MODE;
1595                         reg &= ~RX_IDLE_MODE_OVRD;
1596                 }
1597                 writel(reg, tegra->padctl_base +
1598                         padregs->iophy_misc_pad_p0_ctl3_0);
1599         }
1600
1601         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1602                 reg = readl(tegra->padctl_base +
1603                         padregs->iophy_misc_pad_p1_ctl3_0);
1604                 if (enable) {
1605                         reg &= ~RX_IDLE_MODE;
1606                         reg |= RX_IDLE_MODE_OVRD;
1607                 } else {
1608                         reg |= RX_IDLE_MODE;
1609                         reg &= ~RX_IDLE_MODE_OVRD;
1610                 }
1611                 writel(reg, tegra->padctl_base +
1612                         padregs->iophy_misc_pad_p1_ctl3_0);
1613
1614                 /* SATA lane also if USB3_SS port1 mapped to it */
1615                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
1616                                 tegra->bdata->lane_owner & BIT(0)) {
1617                         reg = readl(tegra->padctl_base +
1618                                 padregs->iophy_misc_pad_s0_ctl3_0);
1619                         if (enable) {
1620                                 reg &= ~RX_IDLE_MODE;
1621                                 reg |= RX_IDLE_MODE_OVRD;
1622                         } else {
1623                                 reg |= RX_IDLE_MODE;
1624                                 reg &= ~RX_IDLE_MODE_OVRD;
1625                         }
1626                         writel(reg, tegra->padctl_base +
1627                                 padregs->iophy_misc_pad_s0_ctl3_0);
1628                 }
1629         }
1630 }
1631
1632 /* Enable ss clk, host clk, falcon clk,
1633  * fs clk, dev clk, plle and refplle
1634  */
1635
1636 static int
1637 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
1638                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
1639 {
1640         int ret = 0;
1641         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
1642         int fw_req_rate = rate, cur_rate;
1643
1644         /* Do not handle clock change as needed for HS disconnect issue */
1645         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1646                 *sw_resp = fw_req_rate | (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
1647                 return ret;
1648         }
1649
1650         /* frequency request from firmware is in KHz.
1651          * Convert it to MHz
1652          */
1653
1654         /* get current rate of clock */
1655         cur_rate = clk_get_rate(clk_handle);
1656         cur_rate /= 1000;
1657
1658         if (fw_req_rate == cur_rate) {
1659                 cmd_ack = MBOX_CMD_ACK;
1660                 *sw_resp = fw_req_rate;
1661         } else {
1662
1663                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
1664                         /* Change SS clock source to CLK_M at 12MHz */
1665                         clk_set_parent(clk_handle, tegra->clk_m);
1666                         clk_set_rate(clk_handle, fw_req_rate * 1000);
1667
1668                         /* save leakage power when SS freq is being decreased */
1669                         tegra_xhci_rx_idle_mode_override(tegra, true);
1670                 } else if (clk_handle == tegra->ss_src_clk &&
1671                                 fw_req_rate == 120000) {
1672                         /* Change SS clock source to HSIC_480 at 120MHz */
1673                         clk_set_rate(clk_handle,  3000 * 1000);
1674                         clk_set_parent(clk_handle, tegra->pll_u_480M);
1675
1676                         /* clear ovrd bits when SS freq is being increased */
1677                         tegra_xhci_rx_idle_mode_override(tegra, false);
1678                 }
1679
1680                 *sw_resp = clk_get_rate(clk_handle);
1681                 *sw_resp /= 1000;
1682
1683                 if (*sw_resp != fw_req_rate) {
1684                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
1685                                 cur_rate, fw_req_rate);
1686                         cmd_ack = MBOX_CMD_NACK;
1687                 }
1688         }
1689         *sw_resp |= (cmd_ack << MBOX_CMD_SHIFT);
1690         return ret;
1691 }
1692
1693 static void tegra_xhci_save_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
1694         u8 port)
1695 {
1696         struct xhci_hcd *xhci = tegra->xhci;
1697         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1698         u32 offset;
1699         u32 reg;
1700
1701         xhci_info(xhci, "saving dfe_cntl and ctle context for port %d\n", port);
1702
1703         /* if port1 is mapped to SATA lane then read from SATA register */
1704         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1705                         tegra->bdata->lane_owner & BIT(0))
1706                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1707         else
1708                 offset = port ? padregs->iophy_misc_pad_p1_ctl6_0 :
1709                                 padregs->iophy_misc_pad_p0_ctl6_0;
1710
1711         /* save tap1_val[] for the port for dfe_cntl */
1712         reg = readl(tegra->padctl_base + offset);
1713         reg &= ~(0xff << 16);
1714         reg |= (0x32 << 16);
1715         writel(reg, tegra->padctl_base + offset);
1716
1717         reg = readl(tegra->padctl_base + offset);
1718         tegra->sregs.tap1_val[port] = ((reg & (0x1f << 24)) >> 24);
1719
1720         /* save amp_val[] for the port for dfe_cntl */
1721         reg = readl(tegra->padctl_base + offset);
1722         reg &= ~(0xff << 16);
1723         reg |= (0x33 << 16);
1724         writel(reg, tegra->padctl_base + offset);
1725
1726         reg = readl(tegra->padctl_base + offset);
1727         tegra->sregs.amp_val[port] = ((reg & (0x7f << 24)) >> 24);
1728
1729         /* save ctle_z_val[] for the port for ctle */
1730         reg = readl(tegra->padctl_base + offset);
1731         reg &= ~(0xff << 16);
1732         reg |= (0x20 << 16);
1733         writel(reg, tegra->padctl_base + offset);
1734
1735         reg = readl(tegra->padctl_base + offset);
1736         tegra->sregs.ctle_z_val[port] = ((reg & (0x3f << 24)) >> 24);
1737
1738         /* save ctle_g_val[] for the port for ctle */
1739         reg = readl(tegra->padctl_base + offset);
1740         reg &= ~(0xff << 16);
1741         reg |= (0x21 << 16);
1742         writel(reg, tegra->padctl_base + offset);
1743
1744         reg = readl(tegra->padctl_base + offset);
1745         tegra->sregs.ctle_g_val[port] = ((reg & (0x3f << 24)) >> 24);
1746         tegra->dfe_ctle_ctx_saved = true;
1747 }
1748
1749 static void tegra_xhci_restore_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
1750         u8 port)
1751 {
1752         struct xhci_hcd *xhci = tegra->xhci;
1753         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1754         u32 ctl4_offset, ctl2_offset;
1755         u32 reg;
1756
1757         /* don't restore if not saved */
1758         if (tegra->dfe_ctle_ctx_saved == false)
1759                 return;
1760
1761         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1762                         padregs->iophy_usb3_pad0_ctl4_0;
1763         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1764                         padregs->iophy_usb3_pad0_ctl2_0;
1765
1766         xhci_info(xhci, "restoring dfe_cntl/ctle context of port %d\n", port);
1767
1768         /* restore dfe_cntl for the port */
1769         reg = readl(tegra->padctl_base + ctl4_offset);
1770         reg &= ~((0x7f << 16) | (0x1f << 24));
1771         reg |= ((tegra->sregs.amp_val[port] << 16) |
1772                 (tegra->sregs.tap1_val[port] << 24));
1773         writel(reg, tegra->padctl_base + ctl4_offset);
1774
1775         /* restore ctle for the port */
1776         reg = readl(tegra->padctl_base + ctl2_offset);
1777         reg &= ~((0x3f << 8) | (0x3f << 16));
1778         reg |= ((tegra->sregs.ctle_g_val[port] << 8) |
1779                 (tegra->sregs.ctle_z_val[port] << 16));
1780         writel(reg, tegra->padctl_base + ctl2_offset);
1781 }
1782
1783 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
1784         u8 port)
1785 {
1786         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1787         u32 reg;
1788
1789         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1790         reg &= ~USB2_ULPI_PAD;
1791         reg |= USB2_ULPI_PAD_OWNER_XUSB;
1792         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1793
1794         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1795         reg &= ~USB2_ULPI_PORT_CAP;
1796         reg |= (tegra->bdata->ulpicap << 24);
1797         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1798         /* FIXME: Program below when more details available
1799          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
1800          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
1801          */
1802 }
1803
1804 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
1805         u8 port)
1806 {
1807         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1808         u32 reg;
1809         u32 ctl0_offset, ctl1_offset;
1810
1811         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1812         reg &= ~USB2_OTG_PAD_PORT_MASK(port);
1813         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
1814         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1815
1816         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1817         reg &= ~USB2_PORT_CAP_MASK(port);
1818         reg |= USB2_PORT_CAP_HOST(port);
1819         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1820
1821         /*
1822          * Modify only the bits which belongs to the port
1823          * and enable respective VBUS_PAD for the port
1824          */
1825         if (tegra->bdata->uses_external_pmic == false) {
1826                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1827                 reg &= ~(port == 2 ? OC_DET_VBUS_ENABLE2_OC_MAP :
1828                         port ? OC_DET_VBUS_ENABLE1_OC_MAP :
1829                                 OC_DET_VBUS_ENABLE0_OC_MAP);
1830
1831                 reg |= (port == 2) ? OC_DET_VBUS_EN2_OC_DETECTED_VBUS_PAD2 :
1832                         port ? OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1 :
1833                                 OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0;
1834                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1835         }
1836         /*
1837          * enable respective VBUS_PAD if port is mapped to any SS port
1838          */
1839         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1840         reg &= ~((port == 2) ? USB2_OC_MAP_PORT2 :
1841                 port ? USB2_OC_MAP_PORT1 : USB2_OC_MAP_PORT0);
1842         reg |= (0x4 | port) << (port * 3);
1843         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1844
1845         ctl0_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl0_0 :
1846                         port ? padregs->usb2_otg_pad1_ctl0_0 :
1847                                 padregs->usb2_otg_pad0_ctl0_0;
1848         ctl1_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl1_0 :
1849                         port ? padregs->usb2_otg_pad1_ctl1_0 :
1850                                 padregs->usb2_otg_pad0_ctl1_0;
1851
1852         reg = readl(tegra->padctl_base + ctl0_offset);
1853         reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
1854                 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
1855                 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
1856
1857         reg |= tegra->pdata->hs_slew;
1858         reg |= (port == 2) ? tegra->pdata->ls_rslew_pad2 :
1859                         port ? tegra->pdata->ls_rslew_pad1 :
1860                         tegra->pdata->ls_rslew_pad0;
1861         reg |= (port == 2) ? tegra->pdata->hs_curr_level_pad2 :
1862                         port ? tegra->pdata->hs_curr_level_pad1 :
1863                         tegra->pdata->hs_curr_level_pad0;
1864         writel(reg, tegra->padctl_base + ctl0_offset);
1865
1866         reg = readl(tegra->padctl_base + ctl1_offset);
1867         reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
1868                 | USB2_OTG_PD_CHRP_FORCE_POWERUP
1869                 | USB2_OTG_PD_DISC_FORCE_POWERUP
1870                 | USB2_OTG_PD_DR);
1871         reg |= (tegra->pdata->hs_iref_cap << 9) |
1872                 (tegra->pdata->hs_term_range_adj << 3);
1873         writel(reg, tegra->padctl_base + ctl1_offset);
1874 }
1875
1876 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
1877         u8 port)
1878 {
1879         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1880         u32 ctl2_offset, ctl4_offset, ctl5_offset;
1881         u32 reg;
1882
1883         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1884                         padregs->iophy_usb3_pad0_ctl2_0;
1885         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1886                         padregs->iophy_usb3_pad0_ctl4_0;
1887         ctl5_offset = port ? padregs->iophy_misc_pad_p1_ctl5_0 :
1888                         padregs->iophy_misc_pad_p0_ctl5_0;
1889
1890         reg = readl(tegra->padctl_base + ctl2_offset);
1891         reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
1892                 IOPHY_USB3_CDRCNTL);
1893         reg |= tegra->pdata->rx_wander | tegra->pdata->rx_eq |
1894                 tegra->pdata->cdr_cntl;
1895         writel(reg, tegra->padctl_base + ctl2_offset);
1896
1897         reg = readl(tegra->padctl_base + ctl4_offset);
1898         reg = tegra->pdata->dfe_cntl;
1899         writel(reg, tegra->padctl_base + ctl4_offset);
1900
1901         reg = readl(tegra->padctl_base + ctl5_offset);
1902         reg |= RX_QEYE_EN;
1903         writel(reg, tegra->padctl_base + ctl5_offset);
1904
1905         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1906         reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
1907         reg |= (tegra->bdata->ss_portmap &
1908                 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
1909         writel(reg, tegra->padctl_base + padregs->ss_port_map_0);
1910
1911         tegra_xhci_restore_dfe_ctle_context(tegra, port);
1912 }
1913
1914 /* This function assigns the USB ports to the controllers,
1915  * then programs the port capabilities and pad parameters
1916  * of ports assigned to XUSB after booted to OS.
1917  */
1918 void
1919 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
1920 {
1921         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1922         u32 reg, oc_bits = 0;
1923         unsigned pad;
1924
1925         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1926         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
1927         reg |= tegra->pdata->hs_squelch_level | tegra->pdata->hs_disc_lvl;
1928         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1929
1930         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1931         reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3;
1932         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
1933         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1934
1935         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1936         reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
1937         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1938                 reg |= OC_DET_VBUS_ENABLE2_OC_MAP;
1939         writel(reg, tegra->padctl_base + padregs->oc_det_0);
1940
1941         /* check if over current seen. Clear if present */
1942         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1943                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
1944         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1945                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
1946         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1947                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
1948
1949         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1950         if (reg & oc_bits) {
1951                 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
1952                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1953
1954                 usleep_range(100, 200);
1955
1956                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1957                 if (reg & oc_bits)
1958                         xhci_info(tegra->xhci, "Over current still present\n");
1959         }
1960
1961         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1962         reg = USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1;
1963         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1964                 reg |= USB2_OC_MAP_PORT2;
1965         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1966
1967         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1968                 tegra_xhci_program_utmip_pad(tegra, 0);
1969         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1970                 tegra_xhci_program_utmip_pad(tegra, 1);
1971         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1972                 tegra_xhci_program_utmip_pad(tegra, 2);
1973
1974         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
1975                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap)
1976                         hsic_pad_enable(tegra, pad);
1977         }
1978
1979         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
1980                 tegra_xhci_program_ulpi_pad(tegra, 0);
1981
1982         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1983                 tegra_xhci_program_ss_pad(tegra, 0);
1984         } else {
1985                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1986                 reg = readl(tegra->padctl_base +
1987                         padregs->iophy_misc_pad_p0_ctl3_0);
1988                 reg &= ~RX_IDLE_MODE;
1989                 reg |= RX_IDLE_MODE_OVRD;
1990                 writel(reg, tegra->padctl_base +
1991                         padregs->iophy_misc_pad_p0_ctl3_0);
1992         }
1993
1994         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1995                 tegra_xhci_program_ss_pad(tegra, 1);
1996         } else {
1997                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1998                 reg = readl(tegra->padctl_base +
1999                         padregs->iophy_misc_pad_p1_ctl3_0);
2000                 reg &= ~RX_IDLE_MODE;
2001                 reg |= RX_IDLE_MODE_OVRD;
2002                 writel(reg, tegra->padctl_base +
2003                         padregs->iophy_misc_pad_p1_ctl3_0);
2004
2005                 /* SATA lane also if USB3_SS port1 mapped to it but unused */
2006                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
2007                                 tegra->bdata->lane_owner & BIT(0)) {
2008                         reg = readl(tegra->padctl_base +
2009                                 padregs->iophy_misc_pad_s0_ctl3_0);
2010                         reg &= ~RX_IDLE_MODE;
2011                         reg |= RX_IDLE_MODE_OVRD;
2012                         writel(reg, tegra->padctl_base +
2013                                 padregs->iophy_misc_pad_s0_ctl3_0);
2014                 }
2015         }
2016         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2017                 tegra_xhci_setup_gpio_for_ss_lane(tegra);
2018                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
2019         }
2020 }
2021
2022 /* This function read XUSB registers and stores in device context */
2023 static void
2024 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
2025 {
2026
2027         /* a. Save the IPFS registers */
2028         tegra->sregs.msi_bar_sz =
2029                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2030
2031         tegra->sregs.msi_axi_barst =
2032                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2033
2034         tegra->sregs.msi_fpci_barst =
2035                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2036
2037         tegra->sregs.msi_vec0 =
2038                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2039
2040         tegra->sregs.msi_en_vec0 =
2041                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2042
2043         tegra->sregs.fpci_error_masks =
2044                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2045
2046         tegra->sregs.intr_mask =
2047                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2048
2049         tegra->sregs.ipfs_intr_enable =
2050                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2051
2052         tegra->sregs.ufpci_config =
2053                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2054
2055         tegra->sregs.clkgate_hysteresis =
2056                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2057
2058         tegra->sregs.xusb_host_mccif_fifo_cntrl =
2059                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2060
2061         /* b. Save the CFG registers */
2062
2063         tegra->sregs.hs_pls =
2064                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2065
2066         tegra->sregs.fs_pls =
2067                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2068
2069         tegra->sregs.hs_fs_speed =
2070                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2071
2072         tegra->sregs.hs_fs_pp =
2073                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2074
2075         tegra->sregs.cfg_aru =
2076                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2077
2078         tegra->sregs.cfg_order =
2079                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
2080
2081         tegra->sregs.cfg_fladj =
2082                 readl(tegra->fpci_base + XUSB_CFG_24);
2083
2084         tegra->sregs.cfg_sid =
2085                 readl(tegra->fpci_base + XUSB_CFG_16);
2086 }
2087
2088 /* This function restores XUSB registers from device context */
2089 static void
2090 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
2091 {
2092         /* Restore Cfg registers */
2093         writel(tegra->sregs.hs_pls,
2094                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2095
2096         writel(tegra->sregs.fs_pls,
2097                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2098
2099         writel(tegra->sregs.hs_fs_speed,
2100                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2101
2102         writel(tegra->sregs.hs_fs_pp,
2103                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2104
2105         writel(tegra->sregs.cfg_aru,
2106                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2107
2108         writel(tegra->sregs.cfg_order,
2109                 tegra->fpci_base + XUSB_CFG_FPCICFG);
2110
2111         writel(tegra->sregs.cfg_fladj,
2112                 tegra->fpci_base + XUSB_CFG_24);
2113
2114         writel(tegra->sregs.cfg_sid,
2115                 tegra->fpci_base + XUSB_CFG_16);
2116
2117         /* Restore IPFS registers */
2118
2119         writel(tegra->sregs.msi_bar_sz,
2120                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2121
2122         writel(tegra->sregs.msi_axi_barst,
2123                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2124
2125         writel(tegra->sregs.msi_fpci_barst,
2126                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2127
2128         writel(tegra->sregs.msi_vec0,
2129                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2130
2131         writel(tegra->sregs.msi_en_vec0,
2132                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2133
2134         writel(tegra->sregs.fpci_error_masks,
2135                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2136
2137         writel(tegra->sregs.intr_mask,
2138                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2139
2140         writel(tegra->sregs.ipfs_intr_enable,
2141                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2142
2143         writel(tegra->sregs.ufpci_config,
2144                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2145
2146         writel(tegra->sregs.clkgate_hysteresis,
2147                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2148
2149         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
2150                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2151 }
2152
2153 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
2154 {
2155         struct platform_device *pdev = tegra->pdev;
2156         u32 reg, timeout = 0xff, cmd;
2157
2158         mutex_lock(&tegra->mbox_lock);
2159
2160         do {
2161                 writel(MBOX_OWNER_SW,
2162                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2163                 reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2164                 usleep_range(10, 20);
2165         } while (reg != MBOX_OWNER_SW && timeout--);
2166
2167         if ((timeout == 0) && (reg != MBOX_OWNER_SW)) {
2168                 dev_err(&pdev->dev, "Failed to set mbox message owner ID\n");
2169                 mutex_unlock(&tegra->mbox_lock);
2170                 return;
2171         }
2172
2173         writel((MBOX_CMD_MSG_ENABLED << MBOX_CMD_SHIFT),
2174                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2175
2176         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2177         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
2178         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2179
2180         mutex_unlock(&tegra->mbox_lock);
2181 }
2182
2183 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
2184 {
2185         struct platform_device *pdev = tegra->pdev;
2186         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
2187         u32 phys_addr_lo;
2188         u32 HwReg;
2189         u16 nblocks;
2190         time_t fw_time;
2191         struct tm fw_tm;
2192         u8 hc_caplength;
2193         u32 usbsts, count = 0xff;
2194         struct xhci_cap_regs __iomem *cap_regs;
2195         struct xhci_op_regs __iomem *op_regs;
2196
2197         /* enable mbox interrupt */
2198         writel(readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD) | MBOX_INT_EN,
2199                 tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2200
2201         /* First thing, reset the ARU. By the time we get to
2202          * loading boot code below, reset would be complete.
2203          * alternatively we can busy wait on rst pending bit.
2204          */
2205         /* Don't reset during ELPG/LP0 exit path */
2206         if (resetARU) {
2207                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
2208                 usleep_range(1000, 2000);
2209         }
2210
2211         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
2212                 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
2213                                 csb_read(tegra, XUSB_FALC_CPUCTL));
2214                 return 0;
2215         }
2216
2217         /* update the phys_log_buffer and total_entries here */
2218         cfg_tbl->phys_addr_log_buffer = tegra->log.phys_addr;
2219         cfg_tbl->total_log_entries = FW_LOG_COUNT;
2220
2221         phys_addr_lo = tegra->firmware.dma;
2222         phys_addr_lo += sizeof(struct cfgtbl);
2223
2224         /* Program the size of DFI into ILOAD_ATTR */
2225         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
2226
2227         /* Boot code of the firmware reads the ILOAD_BASE_LO register
2228          * to get to the start of the dfi in system memory.
2229          */
2230         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
2231
2232         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
2233         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
2234
2235         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
2236         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
2237
2238         /* Invalidate L2IMEM. */
2239         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
2240
2241         /* Initiate fetch of Bootcode from system memory into L2IMEM.
2242          * Program BootCode location and size in system memory.
2243          */
2244         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
2245                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
2246                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
2247         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
2248                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
2249                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
2250         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
2251
2252         /* Trigger L2IMEM Load operation. */
2253         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
2254
2255         /* Setup Falcon Auto-fill */
2256         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
2257         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
2258                 nblocks += 1;
2259         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
2260
2261         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
2262         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
2263                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
2264         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
2265
2266         csb_write(tegra, XUSB_FALC_DMACTL, 0);
2267         msleep(50);
2268
2269         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
2270
2271         /* Start Falcon CPU */
2272         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
2273         usleep_range(1000, 2000);
2274
2275         fw_time = cfg_tbl->fwimg_created_time;
2276         time_to_tm(fw_time, 0, &fw_tm);
2277         dev_info(&pdev->dev,
2278                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
2279                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
2280                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
2281                 fw_tm.tm_min, fw_tm.tm_sec,
2282                 csb_read(tegra, XUSB_FALC_CPUCTL));
2283
2284         dev_dbg(&pdev->dev, "num_hsic_port %d\n", cfg_tbl->num_hsic_port);
2285
2286         /* return fail if firmware status is not good */
2287         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
2288                 return -EFAULT;
2289
2290         cap_regs = IO_ADDRESS(tegra->host_phy_base);
2291         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
2292         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
2293
2294         /* wait for USBSTS_CNR to get set */
2295         do {
2296                 usbsts = ioread32(&op_regs->status);
2297         } while ((usbsts & STS_CNR) && count--);
2298
2299         if (!count && (usbsts & STS_CNR)) {
2300                 dev_err(&pdev->dev, "Controller not ready\n");
2301                 return -EFAULT;
2302         }
2303
2304         /* TODO move this into firmware to avoid race */
2305         writel(0x0, tegra->fpci_base + XUSB_CFG_ARU_C11PAGESEL0);
2306         writel(0x1000, tegra->fpci_base + XUSB_CFG_ARU_C11PAGESEL1);
2307         writel(0x10, tegra->fpci_base + XUSB_CFG_HSPX_CORE_HSICWRAP);
2308         reg_dump(&pdev->dev, tegra->fpci_base, XUSB_CFG_ARU_C11PAGESEL0);
2309         reg_dump(&pdev->dev, tegra->fpci_base, XUSB_CFG_ARU_C11PAGESEL1);
2310         reg_dump(&pdev->dev, tegra->fpci_base, XUSB_CFG_HSPX_CORE_HSICWRAP);
2311
2312         return 0;
2313 }
2314
2315 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
2316         bool release)
2317 {
2318         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2319         u32 reg;
2320
2321         /* Issue is only applicable for T114 */
2322         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
2323                 return;
2324
2325         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2326         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2327                         USB2_OTG_PAD_PORT_MASK(2));
2328
2329         if (!release) {
2330                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2331                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2332                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2333                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2334                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2335                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2336         }
2337
2338         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2339 }
2340 /* SS ELPG Entry initiated by fw */
2341 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
2342 {
2343         struct xhci_hcd *xhci = tegra->xhci;
2344         u32 ret = 0;
2345
2346         must_have_sync_lock(tegra);
2347
2348         /* This is SS partition ELPG entry
2349          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
2350          */
2351
2352         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
2353          * only if it is sw initiated one
2354          */
2355
2356         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
2357          * SuperSpeed partition ELPG entry via mailbox protocol
2358          */
2359
2360         /* STEP 2: xHCI PEP driver and XUSB device mode driver
2361          * enable the XUSB wakeup interrupts for the SuperSpeed
2362          * and USB2.0 ports assigned to host.Section 4.1 Step 3
2363          */
2364         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2365
2366         /* STEP 3: xHCI PEP driver initiates the signal sequence
2367          * to enable the XUSB SSwake detection logic for the
2368          * SuperSpeed ports assigned to host.Section 4.1 Step 4
2369          */
2370         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, true);
2371
2372         /* STEP 4: System Power Management driver asserts reset
2373          * to XUSB SuperSpeed partition then disables its clocks
2374          */
2375         tegra_periph_reset_assert(tegra->ss_clk);
2376         clk_disable(tegra->ss_clk);
2377
2378         usleep_range(100, 200);
2379
2380         /* STEP 5: System Power Management driver disables the
2381          * XUSB SuperSpeed partition power rails.
2382          */
2383         debug_print_portsc(xhci);
2384
2385         /* tegra_powergate_partition also does partition reset assert */
2386         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
2387         if (ret) {
2388                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
2389                                 __func__);
2390                 /* TODO: error recovery? */
2391         }
2392         tegra->ss_pwr_gated = true;
2393
2394         /* STEP 6: xHCI PEP driver initiates the signal sequence
2395          * to enable the XUSB SSwake detection logic for the
2396          * SuperSpeed ports assigned to host.Section 4.1 Step 7
2397          */
2398         tegra_xhci_ss_vcore(tegra->bdata->portmap, true);
2399
2400         return ret;
2401 }
2402
2403 /* Host ELPG Entry */
2404 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
2405 {
2406         struct xhci_hcd *xhci = tegra->xhci;
2407         u32 ret;
2408
2409         must_have_sync_lock(tegra);
2410
2411         /* If ss is already powergated skip ss ctx save stuff */
2412         if (tegra->ss_pwr_gated) {
2413                 xhci_info(xhci, "%s: SS partition is already powergated\n",
2414                         __func__);
2415         } else {
2416                 ret = tegra_xhci_ss_elpg_entry(tegra);
2417                 if (ret) {
2418                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
2419                                 __func__, ret);
2420                         return ret;
2421                 }
2422         }
2423
2424         /* 1. IS INTR PENDING INT_PENDING=1 ? */
2425
2426         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
2427         tegra_xhci_save_xusb_ctx(tegra);
2428
2429         /* calculate rctrl_val and tctrl_val */
2430         tegra_xhci_war_for_tctrl_rctrl(tegra);
2431
2432         pmc_setup(tegra, 1);
2433         pmc_setup_wake_detect(tegra);
2434
2435         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2436         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2437                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2438
2439         /* STEP 4: Assert reset to host clk and disable host clk */
2440         tegra_periph_reset_assert(tegra->host_clk);
2441
2442         clk_disable(tegra->host_clk);
2443
2444         /* wait 150us */
2445         usleep_range(150, 200);
2446
2447         /* flush MC client of XUSB_HOST */
2448         tegra_powergate_mc_flush(TEGRA_POWERGATE_XUSBC);
2449
2450         /* STEP 4: Powergate host partition */
2451         /* tegra_powergate_partition also does partition reset assert */
2452         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
2453         if (ret) {
2454                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2455                         __func__, ret);
2456                 /* TODO: error handling? */
2457                 return ret;
2458         }
2459         tegra->host_pwr_gated = true;
2460
2461         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2462                 clk_disable(tegra->pll_re_vco_clk);
2463         clk_disable(tegra->emc_clk);
2464         /* set port ownership to SNPS */
2465         tegra_xhci_release_port_ownership(tegra, true);
2466
2467         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2468                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2469
2470         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
2471         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
2472                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
2473         return ret;
2474 }
2475
2476 /* SS ELPG Exit triggered by PADCTL irq */
2477 /**
2478  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
2479  *
2480  * This function must be called with tegra->sync_lock acquired.
2481  *
2482  * @tegra: xhci controller context
2483  * @return 0 for success, or error numbers
2484  */
2485 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2486 {
2487         struct xhci_hcd *xhci = tegra->xhci;
2488         int ret = 0;
2489
2490         must_have_sync_lock(tegra);
2491
2492         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
2493                         tegra->hs_wake_event || tegra->host_resume_req)) {
2494
2495                 /*
2496                  * PWR_UNGATE SS partition. XUSBA
2497                  * tegra_unpowergate_partition also does partition reset
2498                  * deassert
2499                  */
2500                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
2501                 if (ret) {
2502                         xhci_err(xhci,
2503                         "%s: could not unpowergate xusba partition %d\n",
2504                         __func__, ret);
2505                         goto out;
2506                 }
2507                 if (tegra->ss_wake_event)
2508                         tegra->ss_wake_event = false;
2509
2510         } else {
2511                 xhci_info(xhci, "%s: ss already power gated\n",
2512                         __func__);
2513                 return ret;
2514         }
2515
2516         /* Step 3: Enable clock to ss partition */
2517         clk_enable(tegra->ss_clk);
2518
2519         /* Step 4: Disable ss wake detection logic */
2520         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2521
2522         /* Step 4.1: Disable ss wake detection logic */
2523         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
2524
2525         /* wait 150us */
2526         usleep_range(150, 200);
2527
2528         /* Step 4.2: Disable ss wake detection logic */
2529         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
2530
2531         /* Step 6 Deassert reset for ss clks */
2532         tegra_periph_reset_deassert(tegra->ss_clk);
2533
2534         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
2535         tegra->ss_pwr_gated = false;
2536 out:
2537         return ret;
2538 }
2539
2540 static void ss_partition_elpg_exit_work(struct work_struct *work)
2541 {
2542         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2543                 ss_elpg_exit_work);
2544
2545         mutex_lock(&tegra->sync_lock);
2546         tegra_xhci_ss_partition_elpg_exit(tegra);
2547         mutex_unlock(&tegra->sync_lock);
2548 }
2549
2550 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
2551 static void update_remote_wakeup_ports(struct tegra_xhci_hcd *tegra)
2552 {
2553         struct xhci_hcd *xhci = tegra->xhci;
2554         u32 wake2_status;
2555         int port;
2556
2557 #define PMC_WAKE2_STATUS        0x168
2558 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
2559
2560         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
2561
2562         if (wake2_status & PADCTL_WAKE) {
2563                 /* FIXME: This is customized for Dalmore, find a generic way */
2564                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
2565                 /* clear wake status */
2566                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
2567         }
2568
2569         /* set all usb2 ports with RESUME link state as wakup ports  */
2570         for (port = 0; port < xhci->num_usb2_ports; port++) {
2571                 u32 portsc = xhci_readl(xhci, xhci->usb2_ports[port]);
2572                 if ((portsc & PORT_PLS_MASK) == XDEV_RESUME)
2573                         set_bit(port, &tegra->usb2_rh_remote_wakeup_ports);
2574         }
2575
2576         xhci_dbg(xhci, "%s: usb2 roothub remote_wakeup_ports 0x%lx\n",
2577                         __func__, tegra->usb2_rh_remote_wakeup_ports);
2578         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
2579                         __func__, tegra->usb3_rh_remote_wakeup_ports);
2580 }
2581
2582 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
2583 {
2584         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2585         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2586         int port, num_ports;
2587         unsigned long *remote_wakeup_ports;
2588         u32 portsc;
2589         __le32 __iomem  **port_array;
2590         unsigned char *rh;
2591         unsigned int retry = 64;
2592         struct xhci_bus_state *bus_state;
2593
2594         bus_state = &xhci->bus_state[hcd_index(hcd)];
2595
2596         if (hcd == xhci->shared_hcd) {
2597                 port_array = xhci->usb3_ports;
2598                 num_ports = xhci->num_usb3_ports;
2599                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
2600                 rh = "usb3 roothub";
2601         } else {
2602                 port_array = xhci->usb2_ports;
2603                 num_ports = xhci->num_usb2_ports;
2604                 remote_wakeup_ports = &tegra->usb2_rh_remote_wakeup_ports;
2605                 rh = "usb2 roothub";
2606         }
2607
2608         while (*remote_wakeup_ports && retry--) {
2609                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
2610                         bool can_continue;
2611
2612                         portsc = xhci_readl(xhci, port_array[port]);
2613
2614                         if (!(portsc & PORT_CONNECT)) {
2615                                 /* nothing to do if already disconnected */
2616                                 clear_bit(port, remote_wakeup_ports);
2617                                 continue;
2618                         }
2619
2620                         if (hcd == xhci->shared_hcd) {
2621                                 can_continue =
2622                                         (portsc & PORT_PLS_MASK) == XDEV_U0;
2623                         } else {
2624                                 unsigned long flags;
2625
2626                                 spin_lock_irqsave(&xhci->lock, flags);
2627                                 can_continue =
2628                                 test_bit(port, &bus_state->resuming_ports);
2629                                 spin_unlock_irqrestore(&xhci->lock, flags);
2630                         }
2631
2632                         if (can_continue)
2633                                 clear_bit(port, remote_wakeup_ports);
2634                         else
2635                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
2636                                         __func__, rh, port, portsc);
2637                 }
2638
2639                 if (*remote_wakeup_ports)
2640                         msleep(20); /* give some time, irq will direct U0 */
2641         }
2642
2643         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
2644                         *remote_wakeup_ports);
2645 }
2646
2647 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
2648 {
2649         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2650         u32 reg, utmip_rctrl_val, utmip_tctrl_val, pad_mux, portmux, portowner;
2651
2652         portmux = USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1);
2653         portowner = USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
2654                         USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2655
2656         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2657                 portmux |= USB2_OTG_PAD_PORT_MASK(2);
2658                 portowner |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2659         }
2660
2661         /* Use xusb padctl space only when xusb owns all UTMIP port */
2662         pad_mux = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2663         if ((pad_mux & portmux) == portowner) {
2664                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
2665                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
2666                  */
2667                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2668                 reg &= ~((1 << 12) | (1 << 13));
2669                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2670
2671                 /* wait 20us */
2672                 usleep_range(20, 30);
2673
2674                 /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
2675                  * :: TCTRL and RCTRL
2676                  */
2677                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl1_0);
2678                 utmip_rctrl_val = RCTRL(reg);
2679                 utmip_tctrl_val = TCTRL(reg);
2680
2681                 /*
2682                  * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
2683                  * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
2684                  */
2685                 pmc_data.utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
2686                 pmc_data.utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
2687
2688                 xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
2689                         pmc_data.utmip_rctrl_val, pmc_data.utmip_tctrl_val);
2690
2691                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
2692                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
2693                  */
2694                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2695                 reg |= (1 << 13);
2696                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2697
2698                 /* Program these values into PMC regiseter and program the
2699                  * PMC override
2700                  */
2701                 reg = PMC_TCTRL_VAL(pmc_data.utmip_tctrl_val) |
2702                         PMC_RCTRL_VAL(pmc_data.utmip_rctrl_val);
2703                 tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG,
2704                         0xffffffff, reg);
2705
2706                 reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
2707                 tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
2708         } else {
2709                 /* TODO use common PMC API to use SNPS register space */
2710         }
2711 }
2712
2713 /* Host ELPG Exit triggered by PADCTL irq */
2714 /**
2715  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
2716  *
2717  * This function must be called with tegra->sync_lock acquired.
2718  *
2719  * @tegra: xhci controller context
2720  * @return 0 for success, or error numbers
2721  */
2722 static int
2723 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2724 {
2725         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2726         struct xhci_hcd *xhci = tegra->xhci;
2727         int ret = 0;
2728
2729         must_have_sync_lock(tegra);
2730
2731         if (!tegra->hc_in_elpg)
2732                 return 0;
2733
2734         clk_enable(tegra->emc_clk);
2735         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2736                 clk_enable(tegra->pll_re_vco_clk);
2737
2738         if (tegra->lp0_exit) {
2739                 u32 reg, oc_bits = 0;
2740
2741                 /* Issue is only applicable for T114 */
2742                 if (XUSB_DEVICE_ID_T114 == tegra->device_id)
2743                         tegra_xhci_war_for_tctrl_rctrl(tegra);
2744                 /* check if over current seen. Clear if present */
2745                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2746                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2747                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2748                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2749                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2750                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2751
2752                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2753                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
2754                 if (reg & oc_bits) {
2755                         xhci_info(xhci, "Over current detected. Clearing...\n");
2756                         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2757
2758                         usleep_range(100, 200);
2759
2760                         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2761                         if (reg & oc_bits)
2762                                 xhci_info(xhci, "Over current still present\n");
2763                 }
2764                 tegra_xhci_padctl_portmap_and_caps(tegra);
2765                 /* release clamps post deassert */
2766                 tegra->lp0_exit = false;
2767         }
2768
2769         /* Clear FLUSH_ENABLE of MC client */
2770         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
2771
2772         /* set port ownership back to xusb */
2773         tegra_xhci_release_port_ownership(tegra, false);
2774
2775         /*
2776          * PWR_UNGATE Host partition. XUSBC
2777          * tegra_unpowergate_partition also does partition reset deassert
2778          */
2779         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
2780         if (ret) {
2781                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2782                         __func__, ret);
2783                 goto out;
2784         }
2785         clk_enable(tegra->host_clk);
2786
2787         /* Step 4: Deassert reset to host partition clk */
2788         tegra_periph_reset_deassert(tegra->host_clk);
2789
2790         /* Step 6.1: IPFS and XUSB BAR initialization */
2791         tegra_xhci_cfg(tegra);
2792
2793         /* Step 6.2: IPFS and XUSB related restore */
2794         tegra_xhci_restore_ctx(tegra);
2795
2796         /* Step 8: xhci spec related ctx restore
2797          * will be done in xhci_resume().Do it here.
2798          */
2799
2800         tegra_xhci_ss_partition_elpg_exit(tegra);
2801
2802         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
2803         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
2804                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
2805                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
2806         }
2807
2808         /* clear ovrd bits */
2809         tegra_xhci_rx_idle_mode_override(tegra, false);
2810
2811         /* Load firmware */
2812         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
2813                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
2814                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
2815                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
2816                         __func__,
2817                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
2818                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
2819                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
2820                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
2821                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
2822                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
2823                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
2824                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
2825                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
2826         debug_print_portsc(xhci);
2827
2828         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
2829         if (ret < 0) {
2830                 xhci_err(xhci, "%s: failed to load firmware %d\n",
2831                         __func__, ret);
2832                 goto out;
2833         }
2834
2835         pmc_setup(tegra, 0);
2836         pmc_disable_bus_ctrl(tegra);
2837
2838         tegra->hc_in_elpg = false;
2839         ret = xhci_resume(tegra->xhci, 0);
2840         if (ret) {
2841                 xhci_err(xhci, "%s: could not resume right %d\n",
2842                                 __func__, ret);
2843                 goto out;
2844         }
2845
2846         update_remote_wakeup_ports(tegra);
2847
2848         if (tegra->hs_wake_event)
2849                 tegra->hs_wake_event = false;
2850
2851         if (tegra->host_resume_req)
2852                 tegra->host_resume_req = false;
2853
2854         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
2855                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
2856
2857         tegra->host_pwr_gated = false;
2858 out:
2859         return ret;
2860 }
2861
2862 static void host_partition_elpg_exit_work(struct work_struct *work)
2863 {
2864         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2865                 host_elpg_exit_work);
2866
2867         mutex_lock(&tegra->sync_lock);
2868         tegra_xhci_host_partition_elpg_exit(tegra);
2869         mutex_unlock(&tegra->sync_lock);
2870 }
2871
2872 /* Mailbox handling function. This function handles requests
2873  * from firmware and communicates with clock and powergating
2874  * module to alter clock rates and to power gate/ungate xusb
2875  * partitions.
2876  *
2877  * Following is the structure of mailbox messages.
2878  * bit 31:28 - msg type
2879  * bits 27:0 - mbox data
2880  * FIXME:  Check if we can just call clock functions like below
2881  * or should we schedule it for calling later ?
2882  */
2883
2884 static void
2885 tegra_xhci_process_mbox_message(struct work_struct *work)
2886 {
2887         u32 sw_resp = 0, cmd, data_in, fw_msg;
2888         int ret = 0;
2889         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2890                                         mbox_work);
2891         struct xhci_hcd *xhci = tegra->xhci;
2892         unsigned int freq_khz;
2893         int pad, port;
2894         unsigned long ports;
2895
2896         mutex_lock(&tegra->mbox_lock);
2897
2898         /* get the owner id */
2899         tegra->mbox_owner = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2900         tegra->mbox_owner &= MBOX_OWNER_ID_MASK;
2901
2902         /* get the mbox message from firmware */
2903         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
2904
2905         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2906         if (data_in) {
2907                 mutex_unlock(&tegra->mbox_lock);
2908                 return;
2909         }
2910
2911         /* get cmd type and cmd data */
2912         tegra->cmd_type = (fw_msg & MBOX_CMD_TYPE_MASK) >> MBOX_CMD_SHIFT;
2913         tegra->cmd_data = (fw_msg & MBOX_CMD_DATA_MASK);
2914
2915         /* decode the message and make appropriate requests to
2916          * clock or powergating module.
2917          */
2918
2919         switch (tegra->cmd_type) {
2920         case MBOX_CMD_INC_FALC_CLOCK:
2921         case MBOX_CMD_DEC_FALC_CLOCK:
2922                 ret = tegra_xusb_request_clk_rate(
2923                                 tegra,
2924                                 tegra->falc_clk,
2925                                 tegra->cmd_data,
2926                                 &sw_resp);
2927                 if (ret)
2928                         xhci_err(xhci, "%s: could not set required falc rate\n",
2929                                 __func__);
2930                 goto send_sw_response;
2931         case MBOX_CMD_INC_SSPI_CLOCK:
2932         case MBOX_CMD_DEC_SSPI_CLOCK:
2933                 ret = tegra_xusb_request_clk_rate(
2934                                 tegra,
2935                                 tegra->ss_src_clk,
2936                                 tegra->cmd_data,
2937                                 &sw_resp);
2938                 if (ret)
2939                         xhci_err(xhci, "%s: could not set required ss rate.\n",
2940                                 __func__);
2941                 goto send_sw_response;
2942         case MBOX_CMD_SET_BW:
2943                 /* fw sends BW request in MByte/sec */
2944                 freq_khz = tegra_emc_bw_to_freq_req(tegra->cmd_data << 10);
2945                 clk_set_rate(tegra->emc_clk, freq_khz * 1000);
2946
2947                 /* clear MBOX_SMI_INT_EN bit */
2948                 cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2949                 cmd &= ~MBOX_SMI_INT_EN;
2950                 writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2951
2952                 /* clear mbox owner as ACK will not be sent for this request */
2953                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2954                 break;
2955         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
2956                 tegra_xhci_save_dfe_ctle_context(tegra, tegra->cmd_data);
2957                 tegra_xhci_restore_dfe_ctle_context(tegra, tegra->cmd_data);
2958                 sw_resp |= tegra->cmd_data | (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
2959                 goto send_sw_response;
2960
2961         case MBOX_CMD_STAR_HSIC_IDLE:
2962                 ports = sw_resp = tegra->cmd_data;
2963                 for_each_set_bit(port, &ports, MBOX_CMD_SHIFT) {
2964                         pad = port_to_hsic_pad(port - 1);
2965                         mutex_lock(&tegra->sync_lock);
2966                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
2967                         mutex_unlock(&tegra->sync_lock);
2968                         if (ret)
2969                                 break;
2970                 }
2971
2972                 if (!ret)
2973                         sw_resp |= (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
2974                 else
2975                         sw_resp |= (MBOX_CMD_NACK << MBOX_CMD_SHIFT);
2976
2977                 goto send_sw_response;
2978
2979         case MBOX_CMD_STOP_HSIC_IDLE:
2980                 ports = sw_resp = tegra->cmd_data;
2981                 for_each_set_bit(port, &ports, MBOX_CMD_SHIFT) {
2982                         pad = port_to_hsic_pad(port - 1);
2983                         mutex_lock(&tegra->sync_lock);
2984                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_DISABLE);
2985                         mutex_unlock(&tegra->sync_lock);
2986                         if (ret)
2987                                 break;
2988                 }
2989
2990                 if (!ret)
2991                         sw_resp |= (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
2992                 else
2993                         sw_resp |= (MBOX_CMD_NACK << MBOX_CMD_SHIFT);
2994
2995                 goto send_sw_response;
2996
2997         case MBOX_CMD_ACK:
2998                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2999                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
3000                 break;
3001         case MBOX_CMD_NACK:
3002                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3003                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
3004                 break;
3005         default:
3006                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
3007                                 __func__, tegra->cmd_type);
3008         }
3009         mutex_unlock(&tegra->mbox_lock);
3010         return;
3011
3012 send_sw_response:
3013         if (((sw_resp & MBOX_CMD_TYPE_MASK) >> MBOX_CMD_SHIFT) == MBOX_CMD_NACK)
3014                 xhci_err(xhci, "%s respond fw message 0x%x with NAK\n",
3015                                 __func__, fw_msg);
3016
3017         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3018         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3019         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
3020         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3021
3022         mutex_unlock(&tegra->mbox_lock);
3023 }
3024
3025 static irqreturn_t pmc_usb_phy_wake_isr(int irq, void *data)
3026 {
3027         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) data;
3028         struct xhci_hcd *xhci = tegra->xhci;
3029
3030         xhci_dbg(xhci, "%s irq %d", __func__, irq);
3031         return IRQ_HANDLED;
3032 }
3033
3034 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
3035 {
3036         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3037         struct xhci_hcd *xhci = tegra->xhci;
3038         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3039         u32 elpg_program0 = 0;
3040
3041         spin_lock(&tegra->lock);
3042
3043         tegra->last_jiffies = jiffies;
3044
3045         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
3046         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
3047
3048         /* Clear the interrupt cause. We already read the intr status. */
3049         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3050         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3051
3052         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
3053         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
3054                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
3055         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
3056                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
3057         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
3058                 __func__,
3059                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad0_ctl0_0));
3060         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
3061                 __func__,
3062                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad1_ctl0_0));
3063         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
3064                 __func__,
3065                 readl(tegra->padctl_base + padregs->usb2_bchrg_bias_pad_0));
3066
3067         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
3068                 tegra->ss_wake_event = true;
3069         else if (elpg_program0 & (USB2_PORT0_WAKEUP_EVENT |
3070                         USB2_PORT1_WAKEUP_EVENT |
3071                         USB2_PORT2_WAKEUP_EVENT |
3072                         USB2_HSIC_PORT0_WAKEUP_EVENT |
3073                         USB2_HSIC_PORT1_WAKEUP_EVENT))
3074                 tegra->hs_wake_event = true;
3075
3076         if (tegra->ss_wake_event || tegra->hs_wake_event) {
3077                 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
3078                         xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
3079                         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3080                 } else if (tegra->ss_pwr_gated
3081                                 && tegra->host_pwr_gated) {
3082                         xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
3083                                 __func__);
3084                         schedule_work(&tegra->host_elpg_exit_work);
3085                 }
3086         } else {
3087                 xhci_err(xhci, "error: wake due to no hs/ss event\n");
3088                 tegra_usb_pad_reg_write(padregs->elpg_program_0, 0xffffffff);
3089         }
3090         spin_unlock(&tegra->lock);
3091         return IRQ_HANDLED;
3092 }
3093
3094 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
3095 {
3096         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3097         u32 temp;
3098
3099         spin_lock(&tegra->lock);
3100
3101         /* clear the mbox intr status 1st thing. Other
3102          * bits are W1C bits, so just write to SMI bit.
3103          */
3104
3105         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3106
3107         /* write 1 to clear SMI INTR en bit ( bit 3 ) */
3108         temp = MBOX_SMI_INTR_EN;
3109         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3110
3111         schedule_work(&tegra->mbox_work);
3112
3113         spin_unlock(&tegra->lock);
3114         return IRQ_HANDLED;
3115 }
3116
3117 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
3118 {
3119         /*
3120          * As of now platform drivers don't provide MSI support so we ensure
3121          * here that the generic code does not try to make a pci_dev from our
3122          * dev struct in order to setup MSI
3123          */
3124         xhci->quirks |= XHCI_BROKEN_MSI;
3125         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
3126 }
3127
3128 /* called during probe() after chip reset completes */
3129 static int xhci_plat_setup(struct usb_hcd *hcd)
3130 {
3131         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
3132 }
3133
3134 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
3135         const char *name, void __iomem **region)
3136 {
3137         struct resource *res;
3138         void __iomem *mem;
3139
3140         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
3141         if (!res) {
3142                 dev_err(&pdev->dev, "memory resource %s doesn't exist\n", name);
3143                 return -ENODEV;
3144         }
3145
3146         mem = devm_request_and_ioremap(&pdev->dev, res);
3147         if (!mem) {
3148                 dev_err(&pdev->dev, "failed to ioremap for %s\n", name);
3149                 return -EFAULT;
3150         }
3151         *region = mem;
3152
3153         return 0;
3154 }
3155
3156 static int tegra_xhci_request_irq(struct platform_device *pdev,
3157         const char *rscname, irq_handler_t handler, unsigned long irqflags,
3158         const char *devname, int *irq_no)
3159 {
3160         int ret;
3161         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3162         struct resource *res;
3163
3164         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, rscname);
3165         if (!res) {
3166                 dev_err(&pdev->dev, "irq resource %s doesn't exist\n", rscname);
3167                 return -ENODEV;
3168         }
3169
3170         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
3171                         devname, tegra);
3172         if (ret != 0) {
3173                 dev_err(&pdev->dev,
3174                         "failed to request_irq for %s (irq %d), error = %d\n",
3175                         devname, res->start, ret);
3176                 return ret;
3177         }
3178         *irq_no = res->start;
3179
3180         return 0;
3181 }
3182
3183 #ifdef CONFIG_PM
3184
3185 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
3186 {
3187         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3188         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3189         int err = 0;
3190         unsigned long flags;
3191
3192         mutex_lock(&tegra->sync_lock);
3193
3194         if (xhci->shared_hcd == hcd) {
3195                 tegra->usb3_rh_suspend = true;
3196                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3197         } else if (xhci->main_hcd == hcd) {
3198                 tegra->usb2_rh_suspend = true;
3199                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3200         }
3201
3202         WARN_ON(tegra->hc_in_elpg);
3203
3204         /* suspend xhci bus. This will also set remote mask */
3205         err = xhci_bus_suspend(hcd);
3206         if (err) {
3207                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
3208                                 __func__, err);
3209                 goto xhci_bus_suspend_failed;
3210         }
3211
3212         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
3213                 goto done; /* one of the root hubs is still working */
3214
3215         spin_lock_irqsave(&tegra->lock, flags);
3216         tegra->hc_in_elpg = true;
3217         spin_unlock_irqrestore(&tegra->lock, flags);
3218
3219         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3220
3221         /* save xhci spec ctx. Already done by xhci_suspend */
3222         err = xhci_suspend(tegra->xhci);
3223         if (err) {
3224                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
3225                 goto xhci_suspend_failed;
3226         }
3227
3228         /* Powergate host. Include ss power gate if not already done */
3229         err = tegra_xhci_host_elpg_entry(tegra);
3230         if (err) {
3231                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
3232                                 __func__, err);
3233                 goto tegra_xhci_host_elpg_entry_failed;
3234         }
3235
3236         /* At this point,ensure ss/hs intr enables are always on */
3237         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
3238         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
3239
3240         /* In ELPG, firmware log context is gone. Rewind shared log buffer. */
3241         if (fw_log_wait_empty_timeout(tegra, 100))
3242                 xhci_warn(xhci, "%s still has logs\n", __func__);
3243         tegra->log.dequeue = tegra->log.virt_addr;
3244         tegra->log.seq = 0;
3245
3246 done:
3247         /* pads are disabled only if usb2 root hub in xusb is idle */
3248         /* pads will actually be disabled only when all usb2 ports are idle */
3249         if (xhci->main_hcd == hcd) {
3250                 utmi_phy_pad_disable();
3251                 utmi_phy_iddq_override(true);
3252         }
3253         mutex_unlock(&tegra->sync_lock);
3254         return 0;
3255
3256 tegra_xhci_host_elpg_entry_failed:
3257
3258 xhci_suspend_failed:
3259         tegra->hc_in_elpg = false;
3260 xhci_bus_suspend_failed:
3261         if (xhci->shared_hcd == hcd)
3262                 tegra->usb3_rh_suspend = false;
3263         else if (xhci->main_hcd == hcd)
3264                 tegra->usb2_rh_suspend = false;
3265
3266         mutex_unlock(&tegra->sync_lock);
3267         return err;
3268 }
3269
3270 /* First, USB2HCD and then USB3HCD resume will be called */
3271 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
3272 {
3273         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3274         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3275         int err = 0;
3276
3277         mutex_lock(&tegra->sync_lock);
3278
3279         tegra->host_resume_req = true;
3280
3281         if (xhci->shared_hcd == hcd)
3282                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3283         else if (xhci->main_hcd == hcd)
3284                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3285
3286         /* pads are disabled only if usb2 root hub in xusb is idle */
3287         /* pads will actually be disabled only when all usb2 ports are idle */
3288         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
3289                 utmi_phy_pad_enable();
3290                 utmi_phy_iddq_override(false);
3291         }
3292         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
3293                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
3294                         tegra_xhci_host_partition_elpg_exit(tegra);
3295         }
3296
3297          /* handle remote wakeup before resuming bus */
3298         wait_remote_wakeup_ports(hcd);
3299
3300         err = xhci_bus_resume(hcd);
3301         if (err) {
3302                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
3303                                 __func__, err);
3304                 goto xhci_bus_resume_failed;
3305         }
3306
3307         if (xhci->shared_hcd == hcd)
3308                 tegra->usb3_rh_suspend = false;
3309         else if (xhci->main_hcd == hcd)
3310                 tegra->usb2_rh_suspend = false;
3311
3312         mutex_unlock(&tegra->sync_lock);
3313         return 0;
3314
3315 xhci_bus_resume_failed:
3316         /* TODO: reverse elpg? */
3317         mutex_unlock(&tegra->sync_lock);
3318         return err;
3319 }
3320 #endif
3321
3322 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
3323 {
3324         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3325         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3326         irqreturn_t iret = IRQ_HANDLED;
3327         u32 status;
3328
3329         spin_lock(&tegra->lock);
3330         if (tegra->hc_in_elpg) {
3331                 spin_lock(&xhci->lock);
3332                 if (HCD_HW_ACCESSIBLE(hcd)) {
3333                         status = xhci_readl(xhci, &xhci->op_regs->status);
3334                         status |= STS_EINT;
3335                         xhci_writel(xhci, status, &xhci->op_regs->status);
3336                 }
3337                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
3338                                 __func__);
3339                 schedule_work(&tegra->host_elpg_exit_work);
3340                 spin_unlock(&xhci->lock);
3341         } else
3342                 iret = xhci_irq(hcd);
3343         spin_unlock(&tegra->lock);
3344
3345         wake_up_interruptible(&tegra->log.intr_wait);
3346
3347         return iret;
3348 }
3349
3350
3351 static const struct hc_driver tegra_plat_xhci_driver = {
3352         .description =          "tegra-xhci",
3353         .product_desc =         "Nvidia xHCI Host Controller",
3354         .hcd_priv_size =        sizeof(struct xhci_hcd *),
3355
3356         /*
3357          * generic hardware linkage
3358          */
3359         .irq =                  tegra_xhci_irq,
3360         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
3361
3362         /*
3363          * basic lifecycle operations
3364          */
3365         .reset =                xhci_plat_setup,
3366         .start =                xhci_run,
3367         .stop =                 xhci_stop,
3368         .shutdown =             xhci_shutdown,
3369
3370         /*
3371          * managing i/o requests and associated device resources
3372          */
3373         .urb_enqueue =          xhci_urb_enqueue,
3374         .urb_dequeue =          xhci_urb_dequeue,
3375         .alloc_dev =            xhci_alloc_dev,
3376         .free_dev =             xhci_free_dev,
3377         .alloc_streams =        xhci_alloc_streams,
3378         .free_streams =         xhci_free_streams,
3379         .add_endpoint =         xhci_add_endpoint,
3380         .drop_endpoint =        xhci_drop_endpoint,
3381         .endpoint_reset =       xhci_endpoint_reset,
3382         .check_bandwidth =      xhci_check_bandwidth,
3383         .reset_bandwidth =      xhci_reset_bandwidth,
3384         .address_device =       xhci_address_device,
3385         .update_hub_device =    xhci_update_hub_device,
3386         .reset_device =         xhci_discover_or_reset_device,
3387
3388         /*
3389          * scheduling support
3390          */
3391         .get_frame_number =     xhci_get_frame,
3392
3393         /* Root hub support */
3394         .hub_control =          xhci_hub_control,
3395         .hub_status_data =      xhci_hub_status_data,
3396
3397 #ifdef CONFIG_PM
3398         .bus_suspend =          tegra_xhci_bus_suspend,
3399         .bus_resume =           tegra_xhci_bus_resume,
3400 #endif
3401 };
3402
3403 #ifdef CONFIG_PM
3404 static int
3405 tegra_xhci_suspend(struct platform_device *pdev,
3406                                                 pm_message_t state)
3407 {
3408         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3409         struct xhci_hcd *xhci = tegra->xhci;
3410
3411         int ret = 0;
3412
3413         mutex_lock(&tegra->sync_lock);
3414         if (!tegra->hc_in_elpg) {
3415                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
3416                                 __func__);
3417                 mutex_unlock(&tegra->sync_lock);
3418                 return -EBUSY;
3419         }
3420         mutex_unlock(&tegra->sync_lock);
3421
3422         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3423         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3424
3425         /* enable_irq_wake for ss ports */
3426         ret = enable_irq_wake(tegra->padctl_irq);
3427         if (ret < 0) {
3428                 xhci_err(xhci,
3429                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
3430                 __func__, tegra->padctl_irq, ret);
3431         }
3432
3433         /* enable_irq_wake for utmip/uhisc wakes */
3434         ret = enable_irq_wake(tegra->usb3_irq);
3435         if (ret < 0) {
3436                 xhci_err(xhci,
3437                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3438                 __func__, tegra->usb3_irq, ret);
3439         }
3440
3441         /* enable_irq_wake for utmip/uhisc wakes */
3442         ret = enable_irq_wake(tegra->usb2_irq);
3443         if (ret < 0) {
3444                 xhci_err(xhci,
3445                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3446                 __func__, tegra->usb2_irq, ret);
3447         }
3448
3449         regulator_disable(tegra->xusb_s1p8v_reg);
3450         regulator_disable(tegra->xusb_s1p05v_reg);
3451         tegra_usb2_clocks_deinit(tegra);
3452
3453         return ret;
3454 }
3455
3456 static int
3457 tegra_xhci_resume(struct platform_device *pdev)
3458 {
3459         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3460
3461         dev_dbg(&pdev->dev, "%s\n", __func__);
3462
3463         tegra->last_jiffies = jiffies;
3464
3465         disable_irq_wake(tegra->padctl_irq);
3466         disable_irq_wake(tegra->usb3_irq);
3467         disable_irq_wake(tegra->usb2_irq);
3468         tegra->lp0_exit = true;
3469
3470         regulator_enable(tegra->xusb_s1p05v_reg);
3471         regulator_enable(tegra->xusb_s1p8v_reg);
3472         tegra_usb2_clocks_init(tegra);
3473
3474         return 0;
3475 }
3476 #endif
3477
3478
3479 static int init_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3480 {
3481         struct platform_device *pdev = tegra->pdev;
3482         void __iomem *fw_mmio_base;
3483         phys_addr_t fw_mem_phy_addr;
3484         size_t fw_size;
3485         dma_addr_t fw_dma;
3486 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3487         int ret;
3488         DEFINE_DMA_ATTRS(attrs);
3489 #endif
3490
3491         /* bootloader saved firmware memory address in PMC SCRATCH34 register */
3492         fw_mem_phy_addr = tegra_usb_pmc_reg_read(PMC_SCRATCH34);
3493
3494         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3495                         fw_mem_phy_addr, sizeof(struct cfgtbl));
3496
3497         if (!fw_mmio_base) {
3498                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3499                                         fw_mem_phy_addr);
3500                         return -ENOMEM;
3501         }
3502
3503         fw_size = ioread32(fw_mmio_base + FW_SIZE_OFFSET);
3504         devm_iounmap(&pdev->dev, fw_mmio_base);
3505
3506         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3507                         fw_mem_phy_addr, fw_size);
3508         if (!fw_mmio_base) {
3509                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3510                                         fw_mem_phy_addr);
3511                         return -ENOMEM;
3512         }
3513
3514         dev_info(&pdev->dev, "Firmware Memory: phy 0x%x mapped 0x%p (%d Bytes)\n",
3515                         fw_mem_phy_addr, fw_mmio_base, fw_size);
3516
3517 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3518         dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
3519         fw_dma = dma_map_linear_attrs(&pdev->dev, fw_mem_phy_addr, fw_size,
3520                         DMA_TO_DEVICE, &attrs);
3521
3522         if (fw_dma == DMA_ERROR_CODE) {
3523                 dev_err(&pdev->dev, "%s: dma_map_linear failed\n",
3524                                 __func__);
3525                 ret = -ENOMEM;
3526                 goto error_iounmap;
3527         }
3528 #else
3529         fw_dma = fw_mem_phy_addr;
3530 #endif
3531         dev_info(&pdev->dev, "Firmware DMA Memory: dma 0x%p (%d Bytes)\n",
3532                         (void *) fw_dma, fw_size);
3533
3534         /* all set and ready to go */
3535         tegra->firmware.data = fw_mmio_base;
3536         tegra->firmware.dma = fw_dma;
3537         tegra->firmware.size = fw_size;
3538
3539         return 0;
3540
3541 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3542 error_iounmap:
3543         devm_iounmap(&pdev->dev, fw_mmio_base);
3544         return ret;
3545 #endif
3546 }
3547
3548 static void deinit_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3549 {
3550         struct platform_device *pdev = tegra->pdev;
3551         void __iomem *fw_mmio_base = tegra->firmware.data;
3552
3553 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3554         dma_unmap_single(&pdev->dev, tegra->firmware.dma,
3555                         tegra->firmware.size, DMA_TO_DEVICE);
3556 #endif
3557         devm_iounmap(&pdev->dev, fw_mmio_base);
3558
3559         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
3560 }
3561
3562 static int init_firmware(struct tegra_xhci_hcd *tegra)
3563 {
3564         return init_bootloader_firmware(tegra);
3565 }
3566
3567 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
3568 {
3569         deinit_bootloader_firmware(tegra);
3570 }
3571
3572 static int tegra_enable_xusb_clk(struct tegra_xhci_hcd *tegra,
3573                 struct platform_device *pdev)
3574 {
3575         int err = 0;
3576         /* enable ss clock */
3577         err = clk_enable(tegra->host_clk);
3578         if (err) {
3579                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
3580                 goto enable_host_clk_failed;
3581         }
3582
3583         err = clk_enable(tegra->ss_clk);
3584         if (err) {
3585                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
3586                 goto eanble_ss_clk_failed;
3587         }
3588
3589         err = clk_enable(tegra->emc_clk);
3590         if (err) {
3591                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
3592                 goto eanble_emc_clk_failed;
3593         }
3594
3595         return 0;
3596
3597 eanble_emc_clk_failed:
3598         clk_disable(tegra->ss_clk);
3599
3600 eanble_ss_clk_failed:
3601         clk_disable(tegra->host_clk);
3602
3603 enable_host_clk_failed:
3604         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
3605                 clk_disable(tegra->pll_re_vco_clk);
3606         return err;
3607 }
3608
3609 static struct tegra_xusb_padctl_regs t114_padregs_offset = {
3610         .boot_media_0                   = 0x0,
3611         .usb2_pad_mux_0                 = 0x4,
3612         .usb2_port_cap_0                = 0x8,
3613         .snps_oc_map_0                  = 0xc,
3614         .usb2_oc_map_0                  = 0x10,
3615         .ss_port_map_0                  = 0x14,
3616         .oc_det_0                       = 0x18,
3617         .elpg_program_0                 = 0x1c,
3618         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3619         .usb2_bchrg_otgpad0_ctl1_0      = 0xffff,
3620         .usb2_bchrg_otgpad1_ctl0_0      = 0x24,
3621         .usb2_bchrg_otgpad1_ctl1_0      = 0xffff,
3622         .usb2_bchrg_otgpad2_ctl0_0      = 0xffff,
3623         .usb2_bchrg_otgpad2_ctl1_0      = 0xffff,
3624         .usb2_bchrg_bias_pad_0          = 0x28,
3625         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
3626         .iophy_pll_p0_ctl1_0            = 0x30,
3627         .iophy_pll_p0_ctl2_0            = 0x34,
3628         .iophy_pll_p0_ctl3_0            = 0x38,
3629         .iophy_pll_p0_ctl4_0            = 0x3c,
3630         .iophy_usb3_pad0_ctl1_0         = 0x40,
3631         .iophy_usb3_pad1_ctl1_0         = 0x44,
3632         .iophy_usb3_pad0_ctl2_0         = 0x48,
3633         .iophy_usb3_pad1_ctl2_0         = 0x4c,
3634         .iophy_usb3_pad0_ctl3_0         = 0x50,
3635         .iophy_usb3_pad1_ctl3_0         = 0x54,
3636         .iophy_usb3_pad0_ctl4_0         = 0x58,
3637         .iophy_usb3_pad1_ctl4_0         = 0x5c,
3638         .iophy_misc_pad_p0_ctl1_0       = 0x60,
3639         .iophy_misc_pad_p1_ctl1_0       = 0x64,
3640         .iophy_misc_pad_p0_ctl2_0       = 0x68,
3641         .iophy_misc_pad_p1_ctl2_0       = 0x6c,
3642         .iophy_misc_pad_p0_ctl3_0       = 0x70,
3643         .iophy_misc_pad_p1_ctl3_0       = 0x74,
3644         .iophy_misc_pad_p0_ctl4_0       = 0x78,
3645         .iophy_misc_pad_p1_ctl4_0       = 0x7c,
3646         .iophy_misc_pad_p0_ctl5_0       = 0x80,
3647         .iophy_misc_pad_p1_ctl5_0       = 0x84,
3648         .iophy_misc_pad_p0_ctl6_0       = 0x88,
3649         .iophy_misc_pad_p1_ctl6_0       = 0x8c,
3650         .usb2_otg_pad0_ctl0_0           = 0x90,
3651         .usb2_otg_pad1_ctl0_0           = 0x94,
3652         .usb2_otg_pad2_ctl0_0           = 0xffff,
3653         .usb2_otg_pad0_ctl1_0           = 0x98,
3654         .usb2_otg_pad1_ctl1_0           = 0x9c,
3655         .usb2_otg_pad2_ctl1_0           = 0xffff,
3656         .usb2_bias_pad_ctl0_0           = 0xa0,
3657         .usb2_bias_pad_ctl1_0           = 0xa4,
3658         .usb2_hsic_pad0_ctl0_0          = 0xa8,
3659         .usb2_hsic_pad1_ctl0_0          = 0xac,
3660         .usb2_hsic_pad0_ctl1_0          = 0xb0,
3661         .usb2_hsic_pad1_ctl1_0          = 0xb4,
3662         .usb2_hsic_pad0_ctl2_0          = 0xb8,
3663         .usb2_hsic_pad1_ctl2_0          = 0xbc,
3664         .ulpi_link_trim_ctl0            = 0xc0,
3665         .ulpi_null_clk_trim_ctl0        = 0xc4,
3666         .hsic_strb_trim_ctl0            = 0xc8,
3667         .wake_ctl0                      = 0xcc,
3668         .pm_spare0                      = 0xd0,
3669         .iophy_misc_pad_p2_ctl1_0       = 0xffff,
3670         .iophy_misc_pad_p3_ctl1_0       = 0xffff,
3671         .iophy_misc_pad_p4_ctl1_0       = 0xffff,
3672         .iophy_misc_pad_p2_ctl2_0       = 0xffff,
3673         .iophy_misc_pad_p3_ctl2_0       = 0xffff,
3674         .iophy_misc_pad_p4_ctl2_0       = 0xffff,
3675         .iophy_misc_pad_p2_ctl3_0       = 0xffff,
3676         .iophy_misc_pad_p3_ctl3_0       = 0xffff,
3677         .iophy_misc_pad_p4_ctl3_0       = 0xffff,
3678         .iophy_misc_pad_p2_ctl4_0       = 0xffff,
3679         .iophy_misc_pad_p3_ctl4_0       = 0xffff,
3680         .iophy_misc_pad_p4_ctl4_0       = 0xffff,
3681         .iophy_misc_pad_p2_ctl5_0       = 0xffff,
3682         .iophy_misc_pad_p3_ctl5_0       = 0xffff,
3683         .iophy_misc_pad_p4_ctl5_0       = 0xffff,
3684         .iophy_misc_pad_p2_ctl6_0       = 0xffff,
3685         .iophy_misc_pad_p3_ctl6_0       = 0xffff,
3686         .iophy_misc_pad_p4_ctl6_0       = 0xffff,
3687         .usb3_pad_mux_0                 = 0xffff,
3688         .iophy_pll_s0_ctl1_0            = 0xffff,
3689         .iophy_pll_s0_ctl2_0            = 0xffff,
3690         .iophy_pll_s0_ctl3_0            = 0xffff,
3691         .iophy_pll_s0_ctl4_0            = 0xffff,
3692         .iophy_misc_pad_s0_ctl1_0       = 0xffff,
3693         .iophy_misc_pad_s0_ctl2_0       = 0xffff,
3694         .iophy_misc_pad_s0_ctl3_0       = 0xffff,
3695         .iophy_misc_pad_s0_ctl4_0       = 0xffff,
3696         .iophy_misc_pad_s0_ctl5_0       = 0xffff,
3697         .iophy_misc_pad_s0_ctl6_0       = 0xffff,
3698 };
3699
3700 static struct tegra_xusb_padctl_regs t124_padregs_offset = {
3701         .boot_media_0                   = 0x0,
3702         .usb2_pad_mux_0                 = 0x4,
3703         .usb2_port_cap_0                = 0x8,
3704         .snps_oc_map_0                  = 0xc,
3705         .usb2_oc_map_0                  = 0x10,
3706         .ss_port_map_0                  = 0x14,
3707         .oc_det_0                       = 0x18,
3708         .elpg_program_0                 = 0x1c,
3709         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3710         .usb2_bchrg_otgpad0_ctl1_0      = 0x24,
3711         .usb2_bchrg_otgpad1_ctl0_0      = 0x28,
3712         .usb2_bchrg_otgpad1_ctl1_0      = 0x2c,
3713         .usb2_bchrg_otgpad2_ctl0_0      = 0x30,
3714         .usb2_bchrg_otgpad2_ctl1_0      = 0x34,
3715         .usb2_bchrg_bias_pad_0          = 0x38,
3716         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
3717         .iophy_pll_p0_ctl1_0            = 0x40,
3718         .iophy_pll_p0_ctl2_0            = 0x44,
3719         .iophy_pll_p0_ctl3_0            = 0x48,
3720         .iophy_pll_p0_ctl4_0            = 0x4c,
3721         .iophy_usb3_pad0_ctl1_0         = 0x50,
3722         .iophy_usb3_pad1_ctl1_0         = 0x54,
3723         .iophy_usb3_pad0_ctl2_0         = 0x58,
3724         .iophy_usb3_pad1_ctl2_0         = 0x5c,
3725         .iophy_usb3_pad0_ctl3_0         = 0x60,
3726         .iophy_usb3_pad1_ctl3_0         = 0x64,
3727         .iophy_usb3_pad0_ctl4_0         = 0x68,
3728         .iophy_usb3_pad1_ctl4_0         = 0x6c,
3729         .iophy_misc_pad_p0_ctl1_0       = 0x70,
3730         .iophy_misc_pad_p1_ctl1_0       = 0x74,
3731         .iophy_misc_pad_p0_ctl2_0       = 0x78,
3732         .iophy_misc_pad_p1_ctl2_0       = 0x7c,
3733         .iophy_misc_pad_p0_ctl3_0       = 0x80,
3734         .iophy_misc_pad_p1_ctl3_0       = 0x84,
3735         .iophy_misc_pad_p0_ctl4_0       = 0x88,
3736         .iophy_misc_pad_p1_ctl4_0       = 0x8c,
3737         .iophy_misc_pad_p0_ctl5_0       = 0x90,
3738         .iophy_misc_pad_p1_ctl5_0       = 0x94,
3739         .iophy_misc_pad_p0_ctl6_0       = 0x98,
3740         .iophy_misc_pad_p1_ctl6_0       = 0x9c,
3741         .usb2_otg_pad0_ctl0_0           = 0xa0,
3742         .usb2_otg_pad1_ctl0_0           = 0xa4,
3743         .usb2_otg_pad2_ctl0_0           = 0xa8,
3744         .usb2_otg_pad0_ctl1_0           = 0xac,
3745         .usb2_otg_pad1_ctl1_0           = 0xb0,
3746         .usb2_otg_pad2_ctl1_0           = 0xb4,
3747         .usb2_bias_pad_ctl0_0           = 0xb8,
3748         .usb2_bias_pad_ctl1_0           = 0xbc,
3749         .usb2_hsic_pad0_ctl0_0          = 0xc0,
3750         .usb2_hsic_pad1_ctl0_0          = 0xc4,
3751         .usb2_hsic_pad0_ctl1_0          = 0xc8,
3752         .usb2_hsic_pad1_ctl1_0          = 0xcc,
3753         .usb2_hsic_pad0_ctl2_0          = 0xd0,
3754         .usb2_hsic_pad1_ctl2_0          = 0xd4,
3755         .ulpi_link_trim_ctl0            = 0xd8,
3756         .ulpi_null_clk_trim_ctl0        = 0xdc,
3757         .hsic_strb_trim_ctl0            = 0xe0,
3758         .wake_ctl0                      = 0xe4,
3759         .pm_spare0                      = 0xe8,
3760         .iophy_misc_pad_p2_ctl1_0       = 0xec,
3761         .iophy_misc_pad_p3_ctl1_0       = 0xf0,
3762         .iophy_misc_pad_p4_ctl1_0       = 0xf4,
3763         .iophy_misc_pad_p2_ctl2_0       = 0xf8,
3764         .iophy_misc_pad_p3_ctl2_0       = 0xfc,
3765         .iophy_misc_pad_p4_ctl2_0       = 0x100,
3766         .iophy_misc_pad_p2_ctl3_0       = 0x104,
3767         .iophy_misc_pad_p3_ctl3_0       = 0x108,
3768         .iophy_misc_pad_p4_ctl3_0       = 0x10c,
3769         .iophy_misc_pad_p2_ctl4_0       = 0x110,
3770         .iophy_misc_pad_p3_ctl4_0       = 0x114,
3771         .iophy_misc_pad_p4_ctl4_0       = 0x118,
3772         .iophy_misc_pad_p2_ctl5_0       = 0x11c,
3773         .iophy_misc_pad_p3_ctl5_0       = 0x120,
3774         .iophy_misc_pad_p4_ctl5_0       = 0x124,
3775         .iophy_misc_pad_p2_ctl6_0       = 0x128,
3776         .iophy_misc_pad_p3_ctl6_0       = 0x12c,
3777         .iophy_misc_pad_p4_ctl6_0       = 0x130,
3778         .usb3_pad_mux_0                 = 0x134,
3779         .iophy_pll_s0_ctl1_0            = 0x138,
3780         .iophy_pll_s0_ctl2_0            = 0x13c,
3781         .iophy_pll_s0_ctl3_0            = 0x140,
3782         .iophy_pll_s0_ctl4_0            = 0x144,
3783         .iophy_misc_pad_s0_ctl1_0       = 0x148,
3784         .iophy_misc_pad_s0_ctl2_0       = 0x14c,
3785         .iophy_misc_pad_s0_ctl3_0       = 0x150,
3786         .iophy_misc_pad_s0_ctl4_0       = 0x154,
3787         .iophy_misc_pad_s0_ctl5_0       = 0x158,
3788         .iophy_misc_pad_s0_ctl6_0       = 0x15c,
3789 };
3790
3791 /* TODO: we have to refine error handling in tegra_xhci_probe() */
3792 static int tegra_xhci_probe(struct platform_device *pdev)
3793 {
3794         const struct hc_driver *driver;
3795         struct xhci_hcd *xhci;
3796         struct tegra_xhci_hcd *tegra;
3797         struct resource *res;
3798         struct usb_hcd  *hcd;
3799         unsigned pad;
3800         u32 val;
3801         int ret;
3802         int irq;
3803
3804         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
3805
3806         if (usb_disabled())
3807                 return -ENODEV;
3808
3809         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
3810         if (!tegra) {
3811                 dev_err(&pdev->dev, "memory alloc failed\n");
3812                 return -ENOMEM;
3813         }
3814         tegra->pdev = pdev;
3815         tegra->pdata = dev_get_platdata(&pdev->dev);
3816         tegra->bdata = tegra->pdata->bdata;
3817
3818         ret = tegra_xhci_request_mem_region(pdev, "padctl",
3819                         &tegra->padctl_base);
3820         if (ret) {
3821                 dev_err(&pdev->dev, "failed to map padctl\n");
3822                 return ret;
3823         }
3824
3825         ret = tegra_xhci_request_mem_region(pdev, "fpci", &tegra->fpci_base);
3826         if (ret) {
3827                 dev_err(&pdev->dev, "failed to map fpci\n");
3828                 return ret;
3829         }
3830
3831         ret = tegra_xhci_request_mem_region(pdev, "ipfs", &tegra->ipfs_base);
3832         if (ret) {
3833                 dev_err(&pdev->dev, "failed to map ipfs\n");
3834                 return ret;
3835         }
3836
3837         ret = tegra_xusb_partitions_clk_init(tegra);
3838         if (ret) {
3839                 dev_err(&pdev->dev,
3840                         "failed to initialize xusb partitions clocks\n");
3841                 return ret;
3842         }
3843
3844         /* Enable power rails to the PAD,VBUS
3845          * and pull-up voltage.Initialize the regulators
3846          */
3847         ret = tegra_xusb_regulator_init(tegra, pdev);
3848         if (ret) {
3849                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
3850                 goto err_deinit_xusb_partition_clk;
3851         }
3852
3853         /* Enable UTMIP, PLLU and PLLE */
3854         ret = tegra_usb2_clocks_init(tegra);
3855         if (ret) {
3856                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
3857                 goto err_deinit_tegra_xusb_regulator;
3858         }
3859
3860         /* tegra_unpowergate_partition also does partition reset deassert */
3861         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
3862         if (ret)
3863                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
3864
3865         /* tegra_unpowergate_partition also does partition reset deassert */
3866         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3867         if (ret)
3868                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
3869
3870         ret = tegra_enable_xusb_clk(tegra, pdev);
3871         if (ret)
3872                 dev_err(&pdev->dev, "could not enable partition clock\n");
3873
3874         /* reset the pointer back to NULL. driver uses it */
3875         /* platform_set_drvdata(pdev, NULL); */
3876
3877         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "host");
3878         if (!res) {
3879                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
3880                 ret = -ENODEV;
3881                 goto err_deinit_usb2_clocks;
3882         }
3883         tegra->host_phy_base = res->start;
3884
3885         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
3886                                 res->start, resource_size(res));
3887         if (!tegra->host_phy_virt_base) {
3888                 dev_err(&pdev->dev, "error mapping host phy memory\n");
3889                 ret = -ENOMEM;
3890                 goto err_deinit_usb2_clocks;
3891         }
3892
3893         /* Setup IPFS access and BAR0 space */
3894         tegra_xhci_cfg(tegra);
3895
3896         val = readl(tegra->fpci_base + XUSB_CFG_0);
3897         tegra->device_id = (val >> 16) & 0xffff;
3898
3899         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
3900                 (XUSB_DEVICE_ID_T114 == tegra->device_id) ? "T114" : "T124+");
3901
3902         if (XUSB_DEVICE_ID_T114 == tegra->device_id) {
3903                 tegra->padregs = &t114_padregs_offset;
3904         } else if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
3905                 tegra->padregs = &t124_padregs_offset;
3906         } else {
3907                 dev_info(&pdev->dev, "XUSB device_id neither T114 nor T124!\n");
3908                 dev_info(&pdev->dev, "XUSB using T124 pad register offsets!\n");
3909                 tegra->padregs = &t124_padregs_offset;
3910         }
3911
3912         /* calculate rctrl_val and tctrl_val once at boot time */
3913         /* Issue is only applicable for T114 */
3914         if (XUSB_DEVICE_ID_T114 == tegra->device_id)
3915                 tegra_xhci_war_for_tctrl_rctrl(tegra);
3916
3917         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
3918                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap)
3919                         hsic_power_rail_enable(tegra);
3920         }
3921
3922         /* Program the XUSB pads to take ownership of ports */
3923         tegra_xhci_padctl_portmap_and_caps(tegra);
3924
3925         /* Release XUSB wake logic state latching */
3926         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
3927         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
3928
3929         /* Deassert reset to XUSB host, ss, dev clocks */
3930         tegra_periph_reset_deassert(tegra->host_clk);
3931         tegra_periph_reset_deassert(tegra->ss_clk);
3932
3933         fw_log_init(tegra);
3934         ret = init_firmware(tegra);
3935         if (ret < 0) {
3936                 dev_err(&pdev->dev, "failed to init firmware\n");
3937                 ret = -ENODEV;
3938                 goto err_deinit_usb2_clocks;
3939         }
3940
3941         ret = load_firmware(tegra, true /* do reset ARU */);
3942         if (ret < 0) {
3943                 dev_err(&pdev->dev, "failed to load firmware\n");
3944                 ret = -ENODEV;
3945                 goto err_deinit_firmware;
3946         }
3947
3948         spin_lock_init(&tegra->lock);
3949         mutex_init(&tegra->sync_lock);
3950         mutex_init(&tegra->mbox_lock);
3951         pmc_init(tegra);
3952
3953         device_init_wakeup(&pdev->dev, 1);
3954         driver = &tegra_plat_xhci_driver;
3955
3956         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
3957         if (!hcd) {
3958                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
3959                 ret = -ENOMEM;
3960                 goto err_deinit_firmware;
3961         }
3962
3963         ret = tegra_xhci_request_mem_region(pdev, "host", &hcd->regs);
3964         if (ret) {
3965                 dev_err(&pdev->dev, "failed to map host\n");
3966                 goto err_put_usb2_hcd;
3967         }
3968         hcd->rsrc_start = res->start;
3969         hcd->rsrc_len = resource_size(res);
3970
3971         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "host");
3972         if (!res) {
3973                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
3974                 ret = -ENODEV;
3975                 goto err_put_usb2_hcd;
3976         }
3977         irq = res->start;
3978         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
3979         if (ret) {
3980                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
3981                 goto err_put_usb2_hcd;
3982         }
3983
3984         /* USB 2.0 roothub is stored in the platform_device now. */
3985         hcd = dev_get_drvdata(&pdev->dev);
3986         xhci = hcd_to_xhci(hcd);
3987         tegra->xhci = xhci;
3988         platform_set_drvdata(pdev, tegra);
3989
3990         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
3991                                                 dev_name(&pdev->dev), hcd);
3992         if (!xhci->shared_hcd) {
3993                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
3994                 ret = -ENOMEM;
3995                 goto err_remove_usb2_hcd;
3996         }
3997
3998         /*
3999          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
4000          * is called by usb_add_hcd().
4001          */
4002         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
4003
4004         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
4005         if (ret) {
4006                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
4007                 goto err_put_usb3_hcd;
4008         }
4009
4010         device_init_wakeup(&hcd->self.root_hub->dev, 1);
4011         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
4012
4013         /* do mailbox related initializations */
4014         tegra->mbox_owner = 0xffff;
4015         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
4016
4017         tegra_xhci_enable_fw_message(tegra);
4018
4019         /* do ss partition elpg exit related initialization */
4020         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
4021
4022         /* do host partition elpg exit related initialization */
4023         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
4024
4025         /* Register interrupt handler for SMI line to handle mailbox
4026          * interrupt from firmware
4027          */
4028         ret = tegra_xhci_request_irq(pdev, "host-smi", tegra_xhci_smi_irq,
4029                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
4030         if (ret != 0)
4031                 goto err_remove_usb3_hcd;
4032
4033         /* Register interrupt handler for PADCTRL line to
4034          * handle wake on connect irqs interrupt from
4035          * firmware
4036          */
4037         ret = tegra_xhci_request_irq(pdev, "padctl", tegra_xhci_padctl_irq,
4038                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
4039                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
4040         if (ret != 0)
4041                 goto err_remove_usb3_hcd;
4042
4043         ret = tegra_xhci_request_irq(pdev, "usb2", pmc_usb_phy_wake_isr,
4044                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4045                 &tegra->usb2_irq);
4046         if (ret != 0)
4047                 goto err_remove_usb3_hcd;
4048
4049         ret = tegra_xhci_request_irq(pdev, "usb3", pmc_usb_phy_wake_isr,
4050                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4051                 &tegra->usb3_irq);
4052         if (ret != 0)
4053                 goto err_remove_usb3_hcd;
4054
4055         tegra->ss_pwr_gated = false;
4056         tegra->host_pwr_gated = false;
4057         tegra->hc_in_elpg = false;
4058         tegra->hs_wake_event = false;
4059         tegra->host_resume_req = false;
4060         tegra->lp0_exit = false;
4061         tegra->dfe_ctle_ctx_saved = false;
4062
4063         tegra_xhci_debug_read_pads(tegra);
4064         utmi_phy_pad_enable();
4065         utmi_phy_iddq_override(false);
4066
4067         tegra_pd_add_device(&pdev->dev);
4068
4069         return 0;
4070
4071 err_remove_usb3_hcd:
4072         usb_remove_hcd(xhci->shared_hcd);
4073 err_put_usb3_hcd:
4074         usb_put_hcd(xhci->shared_hcd);
4075 err_remove_usb2_hcd:
4076         kfree(tegra->xhci);
4077         usb_remove_hcd(hcd);
4078 err_put_usb2_hcd:
4079         usb_put_hcd(hcd);
4080 err_deinit_firmware:
4081         deinit_firmware(tegra);
4082 err_deinit_usb2_clocks:
4083         tegra_usb2_clocks_deinit(tegra);
4084 err_deinit_tegra_xusb_regulator:
4085         tegra_xusb_regulator_deinit(tegra);
4086 err_deinit_xusb_partition_clk:
4087         tegra_xusb_partitions_clk_deinit(tegra);
4088
4089         return ret;
4090 }
4091
4092 static int tegra_xhci_remove(struct platform_device *pdev)
4093 {
4094         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4095         struct xhci_hcd *xhci = NULL;
4096         struct usb_hcd *hcd = NULL;
4097         unsigned pad;
4098
4099         if (tegra == NULL)
4100                 return -EINVAL;
4101
4102         xhci = tegra->xhci;
4103         hcd = xhci_to_hcd(xhci);
4104
4105         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
4106                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap)
4107                         hsic_pad_disable(tegra, pad);
4108         }
4109
4110         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
4111                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap)
4112                         hsic_power_rail_disable(tegra);
4113         }
4114
4115         devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
4116         devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
4117         devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
4118         usb_remove_hcd(xhci->shared_hcd);
4119         usb_put_hcd(xhci->shared_hcd);
4120         usb_remove_hcd(hcd);
4121         usb_put_hcd(hcd);
4122         kfree(xhci);
4123
4124         deinit_firmware(tegra);
4125         fw_log_deinit(tegra);
4126         tegra_xusb_regulator_deinit(tegra);
4127         tegra_usb2_clocks_deinit(tegra);
4128         if (!tegra->hc_in_elpg)
4129                 tegra_xusb_partitions_clk_deinit(tegra);
4130         utmi_phy_pad_disable();
4131         utmi_phy_iddq_override(true);
4132
4133         tegra_pd_remove_device(&pdev->dev);
4134         return 0;
4135 }
4136
4137 static void tegra_xhci_shutdown(struct platform_device *pdev)
4138 {
4139         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4140         struct xhci_hcd *xhci = NULL;
4141         struct usb_hcd *hcd = NULL;
4142
4143         if (tegra == NULL)
4144                 return;
4145
4146         if (tegra->hc_in_elpg) {
4147                 mutex_lock(&tegra->sync_lock);
4148                 pmc_setup(tegra, 0);
4149                 mutex_unlock(&tegra->sync_lock);
4150         } else {
4151                 xhci = tegra->xhci;
4152                 hcd = xhci_to_hcd(xhci);
4153                 xhci_shutdown(hcd);
4154         }
4155 }
4156
4157 static struct platform_driver tegra_xhci_driver = {
4158         .probe  = tegra_xhci_probe,
4159         .remove = tegra_xhci_remove,
4160         .shutdown = tegra_xhci_shutdown,
4161 #ifdef CONFIG_PM
4162         .suspend = tegra_xhci_suspend,
4163         .resume  = tegra_xhci_resume,
4164 #endif
4165         .driver = {
4166                 .name = "tegra-xhci",
4167         },
4168 };
4169 MODULE_ALIAS("platform:tegra-xhci");
4170
4171 int tegra_xhci_register_plat(void)
4172 {
4173         return platform_driver_register(&tegra_xhci_driver);
4174 }
4175
4176 void tegra_xhci_unregister_plat(void)
4177 {
4178         platform_driver_unregister(&tegra_xhci_driver);
4179 }