2 * xhci-tegra.c - Nvidia xHCI host controller driver
4 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/clk.h>
24 #include <linux/ioport.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irq.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/uaccess.h>
31 #include <mach/powergate.h>
33 #include <mach/tegra_usb_pad_ctrl.h>
34 #include <mach/tegra_usb_pmc.h>
35 #include <mach/pm_domains.h>
37 #include <mach/xusb.h>
39 #include "../../../arch/arm/mach-tegra/iomap.h" /* HACK -- remove */
40 #include "xhci-tegra.h"
44 #define PAGE_SELECT_MASK 0xFFFFFE00
45 #define PAGE_SELECT_SHIFT 9
46 #define PAGE_OFFSET_MASK 0x000001FF
47 #define CSB_PAGE_SELECT(_addr) \
49 typecheck(u32, _addr); \
50 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT); \
52 #define CSB_PAGE_OFFSET(_addr) \
54 typecheck(u32, _addr); \
55 (_addr & PAGE_OFFSET_MASK); \
58 /* PMC register definition */
59 #define PMC_PORT_UTMIP_P0 0
60 #define PMC_PORT_UTMIP_P1 1
61 #define PMC_PORT_UTMIP_P2 2
62 #define PMC_PORT_UHSIC_P0 3
63 #define PMC_PORT_NUM 4
65 #define PMC_USB_DEBOUNCE_DEL_0 0xec
66 #define UTMIP_LINE_DEB_CNT(x) (((x) & 0xf) << 16)
67 #define UTMIP_LINE_DEB_CNT_MASK (0xf << 16)
69 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0 0x1fc
71 /* private data types */
72 /* command requests from the firmware */
74 MBOX_CMD_MSG_ENABLED = 1,
75 MBOX_CMD_INC_FALC_CLOCK,
76 MBOX_CMD_DEC_FALC_CLOCK,
77 MBOX_CMD_INC_SSPI_CLOCK,
78 MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
80 MBOX_CMD_SET_SS_PWR_GATING,
81 MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
82 MBOX_CMD_SAVE_DFE_CTLE_CTX,
84 /* needs to be the last cmd */
87 /* resp msg to ack above commands */
92 /* Usb3 Firmware Cfg Table */
94 u32 boot_loadaddr_in_imem;
95 u32 boot_codedfi_offset;
99 /* Physical memory reserved by Bootloader/BIOS */
102 u16 alloc_phys_memsize;
104 /* .rodata section */
105 u32 rodata_img_offset;
106 u32 rodata_section_start;
107 u32 rodata_section_end;
111 u32 fwimg_created_time;
113 /* Fields that get filled by linker during linking phase
114 * or initialized in the FW code.
116 u32 imem_resident_start;
117 u32 imem_resident_end;
125 u32 phys_addr_log_buffer;
126 u32 total_log_entries;
129 /* Below two dummy variables are used to replace
130 * L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
131 * retain the size of struct _CFG_TBL used by other AP/Module.
139 u32 SS_low_power_entry_timeout;
140 u8 padding[140]; /* padding bytes to makeup 256-bytes cfgtbl */
143 struct xusb_save_regs {
149 u32 fpci_error_masks;
151 u32 ipfs_intr_enable;
153 u32 clkgate_hysteresis;
154 u32 xusb_host_mccif_fifo_cntrl;
156 /* PG does not mention below */
172 struct tegra_xhci_firmware {
173 void *data; /* kernel virtual address */
174 size_t size; /* firmware size */
175 dma_addr_t dma; /* dma address for controller */
178 struct tegra_xhci_hcd {
179 struct platform_device *pdev;
180 struct xhci_hcd *xhci;
183 struct mutex sync_lock;
193 bool host_resume_req;
195 bool dfe_ctle_ctx_saved;
196 unsigned long last_jiffies;
197 unsigned long host_phy_base;
198 void __iomem *host_phy_virt_base;
200 void __iomem *padctl_base;
201 void __iomem *fpci_base;
202 void __iomem *ipfs_base;
204 struct tegra_xusb_platform_data *pdata;
205 struct tegra_xusb_board_data *bdata;
207 /* mailbox variables */
208 struct mutex mbox_lock;
213 struct regulator *xusb_vbus_reg;
214 struct regulator *xusb_avddio_usb3_reg;
215 struct regulator *xusb_hvdd_usb3_reg;
216 struct regulator *xusb_avdd_usb3_pll_reg;
218 struct work_struct mbox_work;
219 struct work_struct ss_elpg_exit_work;
220 struct work_struct host_elpg_exit_work;
222 struct clk *host_clk;
225 /* XUSB Falcon SuperSpeed Clock */
226 struct clk *falc_clk;
230 /* XUSB SS PI Clock */
231 struct clk *ss_src_clk;
233 struct clk *plle_clk;
234 struct clk *pll_u_480M;
237 struct clk *pll_re_vco_clk;
239 * XUSB/IPFS specific registers these need to be saved/restored in
240 * addition to spec defined registers
242 struct xusb_save_regs sregs;
243 bool usb2_rh_suspend;
244 bool usb3_rh_suspend;
247 unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
248 /* firmware loading related */
249 struct tegra_xhci_firmware firmware;
252 static struct tegra_usb_pmc_data pmc_data;
255 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
257 return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
260 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
261 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
263 WARN_ON(tegra->sync_lock.owner != current);
266 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
269 static bool is_any_hs_connected(struct xhci_hcd *xhci)
271 __le32 __iomem *addr;
276 ports = HCS_MAX_PORTS(xhci->hcs_params1);
277 addr = &xhci->op_regs->port_status_base;
278 for (i = 0; i < ports; i++) {
279 portsc = xhci_readl(xhci, addr);
280 if ((portsc & PORT_CONNECT) && DEV_HIGHSPEED(portsc))
282 addr += NUM_PORT_REGS;
287 static void debug_print_portsc(struct xhci_hcd *xhci)
289 __le32 __iomem *addr;
293 ports = HCS_MAX_PORTS(xhci->hcs_params1);
294 addr = &xhci->op_regs->port_status_base;
295 for (i = 0; i < ports; i++) {
296 xhci_dbg(xhci, "%p port %d status reg = 0x%x\n",
297 addr, i, (unsigned int) xhci_readl(xhci, addr));
298 addr += NUM_PORT_REGS;
302 static void update_speed(struct tegra_xhci_hcd *tegra, u8 port)
304 struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
307 portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port +
308 BAR0_XHCI_OP_PORTSC_UTMIP_0));
309 if (DEV_FULLSPEED(portsc))
310 pmc_data.port_speed = USB_PMC_PORT_SPEED_FULL;
311 else if (DEV_HIGHSPEED(portsc))
312 pmc_data.port_speed = USB_PMC_PORT_SPEED_HIGH;
313 else if (DEV_LOWSPEED(portsc))
314 pmc_data.port_speed = USB_PMC_PORT_SPEED_LOW;
315 else if (DEV_SUPERSPEED(portsc))
316 pmc_data.port_speed = USB_PMC_PORT_SPEED_SUPER;
318 pmc_data.port_speed = USB_PMC_PORT_SPEED_UNKNOWN;
321 static void setup_wake_detect(bool setup_wake)
324 pmc_data.pmc_ops->setup_pmc_wake_detect(&pmc_data);
326 pmc_data.pmc_ops->disable_pmc_bus_ctrl(&pmc_data, 0);
329 static void pmc_init(struct tegra_xhci_hcd *tegra, bool setup_wake)
331 u32 portmap = tegra->bdata->portmap;
333 pmc_data.controller_type = TEGRA_USB_3_0;
334 if (portmap & TEGRA_XUSB_USB2_P0) {
335 pmc_data.instance = PMC_PORT_UTMIP_P0;
336 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
337 update_speed(tegra, PMC_PORT_UTMIP_P0);
338 tegra_usb_pmc_init(&pmc_data);
339 setup_wake_detect(setup_wake);
341 if (portmap & TEGRA_XUSB_USB2_P1) {
342 /* XUSB_USB2_P1 is PMC UTMI_P2 */
343 pmc_data.instance = PMC_PORT_UTMIP_P2;
344 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
345 update_speed(tegra, PMC_PORT_UTMIP_P2);
346 tegra_usb_pmc_init(&pmc_data);
347 setup_wake_detect(setup_wake);
349 if (portmap & TEGRA_XUSB_HSIC_P0) {
350 pmc_data.instance = PMC_PORT_UHSIC_P0;
351 pmc_data.phy_type = TEGRA_USB_PHY_INTF_HSIC;
352 update_speed(tegra, PMC_PORT_UHSIC_P0);
353 tegra_usb_pmc_init(&pmc_data);
354 setup_wake_detect(setup_wake);
358 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
360 void __iomem *fpci_base = tegra->fpci_base;
361 struct platform_device *pdev = tegra->pdev;
366 /* to select the appropriate CSB page to write to */
367 csb_page_select = CSB_PAGE_SELECT(addr);
369 dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
372 iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
374 /* selects the appropriate offset in the page to read from */
375 input_addr = CSB_PAGE_OFFSET(addr);
376 data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
378 dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
383 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
385 void __iomem *fpci_base = tegra->fpci_base;
386 struct platform_device *pdev = tegra->pdev;
390 /* to select the appropriate CSB page to write to */
391 csb_page_select = CSB_PAGE_SELECT(addr);
393 dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
396 iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
398 /* selects the appropriate offset in the page to write to */
399 input_addr = CSB_PAGE_OFFSET(addr);
400 iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
402 dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
406 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
408 struct xhci_hcd *xhci = tegra->xhci;
411 xhci_info(xhci, "============ PADCTL VALUES START =================\n");
412 reg = readl(tegra->padctl_base + USB2_PAD_MUX_0);
413 xhci_info(xhci, " PAD MUX = %x\n", reg);
414 reg = readl(tegra->padctl_base + USB2_PORT_CAP_0);
415 xhci_info(xhci, " PORT CAP = %x\n", reg);
416 reg = readl(tegra->padctl_base + SNPS_OC_MAP_0);
417 xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
418 reg = readl(tegra->padctl_base + USB2_OC_MAP_0);
419 xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
420 reg = readl(tegra->padctl_base + SS_PORT_MAP_0);
421 xhci_info(xhci, " SS PORT MAP = %x\n", reg);
422 reg = readl(tegra->padctl_base + OC_DET_0);
423 xhci_info(xhci, " OC DET 0= %x\n", reg);
424 reg = readl(tegra->padctl_base + IOPHY_USB3_PAD0_CTL_2_0);
425 xhci_info(xhci, " IOPHY_USB3_PAD0_CTL_2_0= %x\n", reg);
426 reg = readl(tegra->padctl_base + IOPHY_USB3_PAD1_CTL_2_0);
427 xhci_info(xhci, " IOPHY_USB3_PAD1_CTL_2_0= %x\n", reg);
428 reg = readl(tegra->padctl_base + USB2_OTG_PAD0_CTL_0_0);
429 xhci_info(xhci, " USB2_OTG_PAD0_CTL_0_0= %x\n", reg);
430 reg = readl(tegra->padctl_base + USB2_OTG_PAD1_CTL_0_0);
431 xhci_info(xhci, " USB2_OTG_PAD1_CTL_0_0= %x\n", reg);
432 reg = readl(tegra->padctl_base + USB2_OTG_PAD0_CTL_1_0);
433 xhci_info(xhci, " USB2_OTG_PAD0_CTL_1_0= %x\n", reg);
434 reg = readl(tegra->padctl_base + USB2_OTG_PAD1_CTL_1_0);
435 xhci_info(xhci, " USB2_OTG_PAD1_CTL_1_0= %x\n", reg);
436 reg = readl(tegra->padctl_base + USB2_BIAS_PAD_CTL_0_0);
437 xhci_info(xhci, " USB2_BIAS_PAD_CTL_0_0= %x\n", reg);
438 reg = readl(tegra->padctl_base + HSIC_PAD0_CTL_0_0);
439 xhci_info(xhci, " HSIC_PAD0_CTL_0_0= %x\n", reg);
440 reg = readl(tegra->padctl_base + HSIC_PAD1_CTL_0_0);
441 xhci_info(xhci, " HSIC_PAD1_CTL_0_0= %x\n", reg);
442 xhci_info(xhci, "============ PADCTL VALUES END=================\n");
445 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
449 reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
451 writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
454 /* Program Bar0 Space */
455 reg = readl(tegra->fpci_base + XUSB_CFG_4);
456 reg |= tegra->host_phy_base;
457 writel(reg, tegra->fpci_base + XUSB_CFG_4);
458 usleep_range(100, 200);
460 /* Enable Bus Master */
461 reg = readl(tegra->fpci_base + XUSB_CFG_1);
463 writel(reg, tegra->fpci_base + XUSB_CFG_1);
465 /* Set intr mask to enable intr assertion */
466 reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
467 reg |= IPFS_IP_INT_MASK;
468 writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
470 /* Set hysteris to 0x80 */
471 writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
474 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
475 struct platform_device *pdev)
479 tegra->xusb_hvdd_usb3_reg =
480 devm_regulator_get(&pdev->dev, "hvdd_usb");
481 if (IS_ERR(tegra->xusb_hvdd_usb3_reg)) {
482 dev_dbg(&pdev->dev, "hvdd_usb: regulator not found: %ld."
483 , PTR_ERR(tegra->xusb_hvdd_usb3_reg));
484 err = PTR_ERR(tegra->xusb_hvdd_usb3_reg);
485 goto err_null_regulator;
487 err = regulator_enable(tegra->xusb_hvdd_usb3_reg);
490 "hvdd_usb3: regulator enable failed:%d\n", err);
491 goto err_null_regulator;
494 tegra->xusb_vbus_reg = devm_regulator_get(&pdev->dev, "usb_vbus");
495 if (IS_ERR(tegra->xusb_vbus_reg)) {
496 dev_err(&pdev->dev, "vbus regulator not found: %ld."
497 , PTR_ERR(tegra->xusb_vbus_reg));
498 err = PTR_ERR(tegra->xusb_vbus_reg);
499 goto err_put_hvdd_usb3;
501 err = regulator_enable(tegra->xusb_vbus_reg);
503 dev_err(&pdev->dev, "vbus: regulator enable failed:%d\n", err);
504 goto err_put_hvdd_usb3;
507 tegra->xusb_avdd_usb3_pll_reg =
508 devm_regulator_get(&pdev->dev, "avdd_usb_pll");
509 if (IS_ERR(tegra->xusb_avdd_usb3_pll_reg)) {
510 dev_dbg(&pdev->dev, "regulator not found: %ld."
511 , PTR_ERR(tegra->xusb_avdd_usb3_pll_reg));
512 err = PTR_ERR(tegra->xusb_avdd_usb3_pll_reg);
515 err = regulator_enable(tegra->xusb_avdd_usb3_pll_reg);
518 "avdd_usb3_pll: regulator enable failed:%d\n", err);
522 tegra->xusb_avddio_usb3_reg =
523 devm_regulator_get(&pdev->dev, "avddio_usb");
524 if (IS_ERR(tegra->xusb_avddio_usb3_reg)) {
525 dev_err(&pdev->dev, "avddio_usb3: regulator not found: %ld."
526 , PTR_ERR(tegra->xusb_avddio_usb3_reg));
527 err = PTR_ERR(tegra->xusb_avddio_usb3_reg);
528 goto err_put_usb3_pll;
530 err = regulator_enable(tegra->xusb_avddio_usb3_reg);
533 "avddio_usb3: regulator enable failed:%d\n", err);
534 goto err_put_usb3_pll;
540 regulator_disable(tegra->xusb_avdd_usb3_pll_reg);
542 regulator_disable(tegra->xusb_vbus_reg);
544 regulator_disable(tegra->xusb_hvdd_usb3_reg);
546 tegra->xusb_vbus_reg = NULL;
547 tegra->xusb_avddio_usb3_reg = NULL;
548 tegra->xusb_hvdd_usb3_reg = NULL;
549 tegra->xusb_avdd_usb3_pll_reg = NULL;
553 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
555 regulator_disable(tegra->xusb_avddio_usb3_reg);
556 regulator_disable(tegra->xusb_avdd_usb3_pll_reg);
557 regulator_disable(tegra->xusb_vbus_reg);
558 regulator_disable(tegra->xusb_hvdd_usb3_reg);
560 tegra->xusb_avddio_usb3_reg = NULL;
561 tegra->xusb_avdd_usb3_pll_reg = NULL;
562 tegra->xusb_vbus_reg = NULL;
563 tegra->xusb_hvdd_usb3_reg = NULL;
567 * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
568 * are under hardware control
570 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
572 struct platform_device *pdev = tegra->pdev;
575 tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
576 if (IS_ERR(tegra->plle_clk)) {
577 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
578 err = PTR_ERR(tegra->plle_clk);
581 err = clk_enable(tegra->plle_clk);
583 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
591 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
593 clk_disable(tegra->plle_clk);
594 tegra->plle_clk = NULL;
597 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
599 struct platform_device *pdev = tegra->pdev;
602 tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
603 if (IS_ERR(tegra->emc_clk)) {
604 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
605 return PTR_ERR(tegra->emc_clk);
608 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
609 if (IS_ERR(tegra->pll_re_vco_clk)) {
610 dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
611 err = PTR_ERR(tegra->pll_re_vco_clk);
612 goto get_emc_clk_failed;
615 /* get the clock handle of 120MHz clock source */
616 tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
617 if (IS_ERR(tegra->pll_u_480M)) {
618 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
619 err = PTR_ERR(tegra->pll_u_480M);
620 goto get_pll_u_480M_failed;
623 /* get the clock handle of 12MHz clock source */
624 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
625 if (IS_ERR(tegra->clk_m)) {
626 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
627 err = PTR_ERR(tegra->clk_m);
628 goto clk_get_clk_m_failed;
631 tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
632 if (IS_ERR(tegra->ss_src_clk)) {
633 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
634 err = PTR_ERR(tegra->ss_src_clk);
635 tegra->ss_src_clk = NULL;
636 goto get_ss_src_clk_failed;
639 tegra->host_clk = devm_clk_get(&pdev->dev, "host");
640 if (IS_ERR(tegra->host_clk)) {
641 dev_err(&pdev->dev, "Failed to get host partition clk\n");
642 err = PTR_ERR(tegra->host_clk);
643 tegra->host_clk = NULL;
644 goto get_host_clk_failed;
647 tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
648 if (IS_ERR(tegra->ss_clk)) {
649 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
650 err = PTR_ERR(tegra->ss_clk);
651 tegra->ss_clk = NULL;
652 goto get_ss_clk_failed;
655 err = clk_enable(tegra->pll_re_vco_clk);
657 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
658 goto enable_pll_re_vco_clk_failed;
660 /* enable ss clock */
661 err = clk_enable(tegra->host_clk);
663 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
664 goto enable_host_clk_failed;
667 err = clk_enable(tegra->ss_clk);
669 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
670 goto eanble_ss_clk_failed;
673 err = clk_enable(tegra->emc_clk);
675 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
676 goto eanble_emc_clk_failed;
681 eanble_emc_clk_failed:
682 clk_disable(tegra->ss_clk);
684 eanble_ss_clk_failed:
685 clk_disable(tegra->host_clk);
687 enable_host_clk_failed:
688 clk_disable(tegra->pll_re_vco_clk);
690 enable_pll_re_vco_clk_failed:
691 tegra->ss_clk = NULL;
694 tegra->host_clk = NULL;
697 tegra->ss_src_clk = NULL;
699 get_ss_src_clk_failed:
702 clk_get_clk_m_failed:
703 tegra->pll_u_480M = NULL;
705 get_pll_u_480M_failed:
706 tegra->pll_re_vco_clk = NULL;
709 tegra->emc_clk = NULL;
714 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
716 clk_disable(tegra->ss_clk);
717 clk_disable(tegra->host_clk);
718 clk_disable(tegra->pll_re_vco_clk);
719 tegra->ss_clk = NULL;
720 tegra->host_clk = NULL;
721 tegra->ss_src_clk = NULL;
723 tegra->pll_u_480M = NULL;
724 tegra->pll_re_vco_clk = NULL;
727 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
732 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
733 reg = readl(tegra->padctl_base + IOPHY_MISC_PAD0_CTL_3_0);
735 reg &= ~RX_IDLE_MODE;
736 reg |= RX_IDLE_MODE_OVRD;
739 reg &= ~RX_IDLE_MODE_OVRD;
741 writel(reg, tegra->padctl_base + IOPHY_MISC_PAD0_CTL_3_0);
744 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
745 reg = readl(tegra->padctl_base + IOPHY_MISC_PAD1_CTL_3_0);
747 reg &= ~RX_IDLE_MODE;
748 reg |= RX_IDLE_MODE_OVRD;
751 reg &= ~RX_IDLE_MODE_OVRD;
753 writel(reg, tegra->padctl_base + IOPHY_MISC_PAD1_CTL_3_0);
757 /* Enable ss clk, host clk, falcon clk,
758 * fs clk, dev clk, plle and refplle
762 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
763 struct clk *clk_handle, u32 rate, u32 *sw_resp)
766 enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
767 int fw_req_rate = rate, cur_rate;
769 /* Do not handle clock change as needed for HS disconnect issue */
770 if (tegra->pdata->quirks & TEGRA_XUSB_NEED_HS_DISCONNECT_SW_WAR) {
771 *sw_resp = fw_req_rate | (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
775 /* frequency request from firmware is in KHz.
779 /* get current rate of clock */
780 cur_rate = clk_get_rate(clk_handle);
783 if (fw_req_rate == cur_rate) {
784 cmd_ack = MBOX_CMD_ACK;
785 *sw_resp = fw_req_rate;
788 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
789 /* Change SS clock source to CLK_M at 12MHz */
790 clk_set_parent(clk_handle, tegra->clk_m);
791 clk_set_rate(clk_handle, fw_req_rate * 1000);
793 /* save leakage power when SS freq is being decreased */
794 tegra_xhci_rx_idle_mode_override(tegra, true);
795 } else if (clk_handle == tegra->ss_src_clk &&
796 fw_req_rate == 120000) {
797 /* Change SS clock source to HSIC_480 at 120MHz */
798 clk_set_rate(clk_handle, 3000 * 1000);
799 clk_set_parent(clk_handle, tegra->pll_u_480M);
801 /* clear ovrd bits when SS freq is being increased */
802 tegra_xhci_rx_idle_mode_override(tegra, false);
805 *sw_resp = clk_get_rate(clk_handle);
808 if (*sw_resp != fw_req_rate) {
809 xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
810 cur_rate, fw_req_rate);
811 cmd_ack = MBOX_CMD_NACK;
814 *sw_resp |= (cmd_ack << MBOX_CMD_SHIFT);
819 tegra_xhci_ss_wake_on_interrupts(struct tegra_xhci_hcd *tegra, bool enable)
823 /* clear any event */
824 elpg_program0 = readl(tegra->padctl_base + ELPG_PROGRAM_0);
825 elpg_program0 |= (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT);
826 writel(elpg_program0, tegra->padctl_base + ELPG_PROGRAM_0);
828 /* enable ss wake interrupts */
829 elpg_program0 = readl(tegra->padctl_base + ELPG_PROGRAM_0);
832 /* enable interrupts */
833 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0)
834 elpg_program0 |= SS_PORT0_WAKE_INTERRUPT_ENABLE;
835 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
836 elpg_program0 |= SS_PORT1_WAKE_INTERRUPT_ENABLE;
838 /* disable interrupts */
839 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0)
840 elpg_program0 &= ~SS_PORT0_WAKE_INTERRUPT_ENABLE;
841 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
842 elpg_program0 &= ~SS_PORT1_WAKE_INTERRUPT_ENABLE;
844 writel(elpg_program0, tegra->padctl_base + ELPG_PROGRAM_0);
848 tegra_xhci_hs_wake_on_interrupts(struct tegra_xhci_hcd *tegra, bool enable)
852 elpg_program0 = readl(tegra->padctl_base + ELPG_PROGRAM_0);
853 elpg_program0 |= (USB2_PORT0_WAKEUP_EVENT | USB2_PORT1_WAKEUP_EVENT
854 | USB2_HSIC_PORT0_WAKEUP_EVENT
855 | USB2_HSIC_PORT1_WAKEUP_EVENT);
856 writel(elpg_program0, tegra->padctl_base + ELPG_PROGRAM_0);
858 /* Enable the wake interrupts */
859 elpg_program0 = readl(tegra->padctl_base + ELPG_PROGRAM_0);
861 /* enable interrupts */
862 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
863 elpg_program0 |= USB2_PORT0_WAKE_INTERRUPT_ENABLE;
864 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
865 elpg_program0 |= USB2_PORT1_WAKE_INTERRUPT_ENABLE;
866 if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P0)
867 elpg_program0 |= USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE;
868 if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P1)
869 elpg_program0 |= USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE;
871 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
872 elpg_program0 &= ~USB2_PORT0_WAKE_INTERRUPT_ENABLE;
873 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
874 elpg_program0 &= ~USB2_PORT1_WAKE_INTERRUPT_ENABLE;
875 if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P0)
876 elpg_program0 &= ~USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE;
877 if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P1)
878 elpg_program0 &= ~USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE;
880 writel(elpg_program0, tegra->padctl_base + ELPG_PROGRAM_0);
884 tegra_xhci_ss_wake_signal(struct tegra_xhci_hcd *tegra, bool enable)
888 /* DO NOT COMBINE BELOW 2 WRITES */
890 /* Assert/Deassert clamp_en_early signals to SSP0/1 */
891 elpg_program0 = readl(tegra->padctl_base + ELPG_PROGRAM_0);
893 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0)
894 elpg_program0 |= SSP0_ELPG_CLAMP_EN_EARLY;
895 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
896 elpg_program0 |= SSP1_ELPG_CLAMP_EN_EARLY;
898 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0)
899 elpg_program0 &= ~SSP0_ELPG_CLAMP_EN_EARLY;
900 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
901 elpg_program0 &= ~SSP1_ELPG_CLAMP_EN_EARLY;
903 writel(elpg_program0, tegra->padctl_base + ELPG_PROGRAM_0);
906 * Check the LP0 figure and leave gap bw writes to
907 * clamp_en_early and clamp_en
909 usleep_range(100, 200);
911 /* Assert/Deassert clam_en signal */
912 elpg_program0 = readl(tegra->padctl_base + ELPG_PROGRAM_0);
915 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0)
916 elpg_program0 |= SSP0_ELPG_CLAMP_EN;
917 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
918 elpg_program0 |= SSP1_ELPG_CLAMP_EN;
920 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0)
921 elpg_program0 &= ~SSP0_ELPG_CLAMP_EN;
922 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
923 elpg_program0 &= ~SSP1_ELPG_CLAMP_EN;
926 writel(elpg_program0, tegra->padctl_base + ELPG_PROGRAM_0);
928 /* wait for 250us for the writes to propogate */
930 usleep_range(250, 300);
934 tegra_xhci_ss_vcore(struct tegra_xhci_hcd *tegra, bool enable)
938 /* Assert vcore_off signal */
939 elpg_program0 = readl(tegra->padctl_base + ELPG_PROGRAM_0);
942 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0)
943 elpg_program0 |= SSP0_ELPG_VCORE_DOWN;
944 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
945 elpg_program0 |= SSP1_ELPG_VCORE_DOWN;
947 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0)
948 elpg_program0 &= ~SSP0_ELPG_VCORE_DOWN;
949 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
950 elpg_program0 &= ~SSP1_ELPG_VCORE_DOWN;
952 writel(elpg_program0, tegra->padctl_base + ELPG_PROGRAM_0);
955 static void tegra_xhci_save_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
958 struct xhci_hcd *xhci = tegra->xhci;
962 xhci_info(xhci, "saving dfe_cntl and ctle context for port %d\n", port);
964 offset = port ? IOPHY_MISC_PAD1_CTL_6_0 : IOPHY_MISC_PAD0_CTL_6_0;
966 /* save tap1_val[] for the port for dfe_cntl */
967 reg = readl(tegra->padctl_base + offset);
968 reg &= ~(0xff << 16);
970 writel(reg, tegra->padctl_base + offset);
972 reg = readl(tegra->padctl_base + offset);
973 tegra->sregs.tap1_val[port] = ((reg & (0x1f << 24)) >> 24);
975 /* save amp_val[] for the port for dfe_cntl */
976 reg = readl(tegra->padctl_base + offset);
977 reg &= ~(0xff << 16);
979 writel(reg, tegra->padctl_base + offset);
981 reg = readl(tegra->padctl_base + offset);
982 tegra->sregs.amp_val[port] = ((reg & (0x7f << 24)) >> 24);
984 /* save ctle_z_val[] for the port for ctle */
985 reg = readl(tegra->padctl_base + offset);
986 reg &= ~(0xff << 16);
988 writel(reg, tegra->padctl_base + offset);
990 reg = readl(tegra->padctl_base + offset);
991 tegra->sregs.ctle_z_val[port] = ((reg & (0x3f << 24)) >> 24);
993 /* save ctle_g_val[] for the port for ctle */
994 reg = readl(tegra->padctl_base + offset);
995 reg &= ~(0xff << 16);
997 writel(reg, tegra->padctl_base + offset);
999 reg = readl(tegra->padctl_base + offset);
1000 tegra->sregs.ctle_g_val[port] = ((reg & (0x3f << 24)) >> 24);
1001 tegra->dfe_ctle_ctx_saved = true;
1004 static void tegra_xhci_restore_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
1007 struct xhci_hcd *xhci = tegra->xhci;
1008 u32 ctl4_offset, ctl2_offset;
1011 /* don't restore if not saved */
1012 if (tegra->dfe_ctle_ctx_saved == false)
1015 ctl4_offset = port ? IOPHY_USB3_PAD1_CTL_4_0 : IOPHY_USB3_PAD0_CTL_4_0;
1016 ctl2_offset = port ? IOPHY_USB3_PAD1_CTL_2_0 : IOPHY_USB3_PAD0_CTL_2_0;
1018 xhci_info(xhci, "restoring dfe_cntl/ctle context of port %d\n", port);
1020 /* restore dfe_cntl for the port */
1021 reg = readl(tegra->padctl_base + ctl4_offset);
1022 reg &= ~((0x7f << 16) | (0x1f << 24));
1023 reg |= ((tegra->sregs.amp_val[port] << 16) |
1024 (tegra->sregs.tap1_val[port] << 24));
1025 writel(reg, tegra->padctl_base + ctl4_offset);
1027 /* restore ctle for the port */
1028 reg = readl(tegra->padctl_base + ctl2_offset);
1029 reg &= ~((0x3f << 8) | (0x3f << 16));
1030 reg |= ((tegra->sregs.ctle_g_val[port] << 8) |
1031 (tegra->sregs.ctle_z_val[port] << 16));
1032 writel(reg, tegra->padctl_base + ctl2_offset);
1035 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
1040 reg = readl(tegra->padctl_base + USB2_PAD_MUX_0);
1041 reg &= ~USB2_ULPI_PAD;
1042 reg |= USB2_ULPI_PAD_OWNER_XUSB;
1043 writel(reg, tegra->padctl_base + USB2_PAD_MUX_0);
1045 reg = readl(tegra->padctl_base + USB2_PORT_CAP_0);
1046 reg &= ~USB2_ULPI_PORT_CAP;
1047 reg |= (tegra->bdata->ulpicap << 24);
1048 writel(reg, tegra->padctl_base + USB2_PORT_CAP_0);
1049 /* FIXME: Program below when more details available
1050 * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
1051 * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
1055 static void tegra_xhci_program_hsic_pad(struct tegra_xhci_hcd *tegra,
1061 reg = readl(tegra->padctl_base + USB2_PAD_MUX_0);
1062 reg &= ~(port ? USB2_HSIC_PAD_PORT1 : USB2_HSIC_PAD_PORT0);
1063 reg |= port ? USB2_HSIC_PAD_P1_OWNER_XUSB :
1064 USB2_HSIC_PAD_P0_OWNER_XUSB;
1065 writel(reg, tegra->padctl_base + USB2_PAD_MUX_0);
1067 ctl0_offset = port ? HSIC_PAD1_CTL_0_0 : HSIC_PAD0_CTL_0_0;
1069 reg = readl(tegra->padctl_base + ctl0_offset);
1070 reg &= ~(HSIC_TX_SLEWP | HSIC_TX_SLEWN);
1071 writel(reg, tegra->padctl_base + ctl0_offset);
1073 /* FIXME Program below when more details available
1074 * XUSB_PADCTL_HSIC_PAD0_CTL_0_0
1075 * XUSB_PADCTL_HSIC_PAD0_CTL_1_0
1076 * XUSB_PADCTL_HSIC_PAD0_CTL_2_0
1077 * XUSB_PADCTL_HSIC_PAD1_CTL_0_0
1078 * XUSB_PADCTL_HSIC_PAD1_CTL_1_0
1079 * XUSB_PADCTL_HSIC_PAD1_CTL_2_0
1080 * XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0
1084 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
1088 u32 ctl0_offset, ctl1_offset;
1090 reg = readl(tegra->padctl_base + USB2_PAD_MUX_0);
1091 reg &= ~USB2_OTG_PAD_PORT_MASK(port);
1092 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
1093 writel(reg, tegra->padctl_base + USB2_PAD_MUX_0);
1095 reg = readl(tegra->padctl_base + USB2_PORT_CAP_0);
1096 reg &= ~USB2_PORT_CAP_MASK(port);
1097 reg |= USB2_PORT_CAP_HOST(port);
1098 writel(reg, tegra->padctl_base + USB2_PORT_CAP_0);
1100 reg = readl(tegra->padctl_base + SNPS_OC_MAP_0);
1102 reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 |
1105 reg |= SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3 |
1106 SNPS_CTRL1_OC_DETECTED_VBUS_PAD0;
1107 writel(reg, tegra->padctl_base + SNPS_OC_MAP_0);
1108 reg = readl(tegra->padctl_base + SNPS_OC_MAP_0);
1110 reg = readl(tegra->padctl_base + OC_DET_0);
1112 reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
1114 reg |= OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0
1115 | OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1;
1116 writel(reg, tegra->padctl_base + OC_DET_0);
1118 reg = readl(tegra->padctl_base + USB2_OC_MAP_0);
1120 reg |= USB2_OC_MAP_PORT1
1121 | USB2_OC_MAP_PORT0_OC_DETECTED_VBUS_PAD0;
1123 reg |= USB2_OC_MAP_PORT0
1124 | USB2_OC_MAP_PORT1_OC_DETECTED_VBUS_PAD1;
1125 writel(reg, tegra->padctl_base + USB2_OC_MAP_0);
1127 ctl0_offset = port ? USB2_OTG_PAD1_CTL_0_0 : USB2_OTG_PAD0_CTL_0_0;
1128 ctl1_offset = port ? USB2_OTG_PAD1_CTL_1_0 : USB2_OTG_PAD0_CTL_1_0;
1130 reg = readl(tegra->padctl_base + ctl0_offset);
1131 reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
1132 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
1133 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
1134 reg |= tegra->pdata->hs_slew;
1135 reg |= port ? 0 : tegra->pdata->ls_rslew;
1136 reg |= port ? tegra->pdata->hs_curr_level_pad1 :
1137 tegra->pdata->hs_curr_level_pad0;
1138 writel(reg, tegra->padctl_base + ctl0_offset);
1140 reg = readl(tegra->padctl_base + ctl1_offset);
1141 reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
1142 | USB2_OTG_PD_CHRP_FORCE_POWERUP
1143 | USB2_OTG_PD_DISC_FORCE_POWERUP
1145 reg |= (tegra->pdata->hs_iref_cap << 9) |
1146 (tegra->pdata->hs_term_range_adj << 3);
1147 writel(reg, tegra->padctl_base + ctl1_offset);
1150 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
1153 u32 ctl2_offset, ctl4_offset;
1156 ctl2_offset = port ? IOPHY_USB3_PAD1_CTL_2_0 : IOPHY_USB3_PAD0_CTL_2_0;
1157 ctl4_offset = port ? IOPHY_USB3_PAD1_CTL_4_0 : IOPHY_USB3_PAD0_CTL_4_0;
1159 reg = readl(tegra->padctl_base + ctl2_offset);
1160 reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
1161 IOPHY_USB3_CDRCNTL);
1162 reg |= tegra->pdata->rx_wander | tegra->pdata->rx_eq |
1163 tegra->pdata->cdr_cntl;
1164 writel(reg, tegra->padctl_base + ctl2_offset);
1166 reg = readl(tegra->padctl_base + ctl4_offset);
1167 reg = tegra->pdata->dfe_cntl;
1168 writel(reg, tegra->padctl_base + ctl4_offset);
1170 reg = readl(tegra->padctl_base + SS_PORT_MAP_0);
1171 reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
1172 reg |= (tegra->bdata->ss_portmap &
1173 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
1174 writel(reg, tegra->padctl_base + SS_PORT_MAP_0);
1176 tegra_xhci_restore_dfe_ctle_context(tegra, port);
1179 /* This function assigns the USB ports to the controllers,
1180 * then programs the port capabilities and pad parameters
1181 * of ports assigned to XUSB after booted to OS.
1184 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
1188 reg = readl(tegra->padctl_base + USB2_BIAS_PAD_CTL_0_0);
1189 reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
1190 reg |= tegra->pdata->hs_squelch_level | tegra->pdata->hs_disc_lvl;
1191 writel(reg, tegra->padctl_base + USB2_BIAS_PAD_CTL_0_0);
1193 reg = readl(tegra->padctl_base + SNPS_OC_MAP_0);
1194 reg &= ~(SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3);
1195 writel(reg, tegra->padctl_base + SNPS_OC_MAP_0);
1196 reg = readl(tegra->padctl_base + SNPS_OC_MAP_0);
1198 reg = readl(tegra->padctl_base + OC_DET_0);
1199 reg &= ~(OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP);
1200 writel(reg, tegra->padctl_base + OC_DET_0);
1202 /* check if over current seen. Clear if present */
1203 reg = readl(tegra->padctl_base + OC_DET_0);
1204 if (reg & (0x3 << 20)) {
1205 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
1206 writel(reg, tegra->padctl_base + OC_DET_0);
1208 usleep_range(100, 200);
1210 reg = readl(tegra->padctl_base + OC_DET_0);
1211 if (reg & (0x3 << 20))
1212 xhci_info(tegra->xhci, "Over current still present\n");
1215 reg = readl(tegra->padctl_base + USB2_OC_MAP_0);
1216 reg &= ~(USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1);
1217 writel(reg, tegra->padctl_base + USB2_OC_MAP_0);
1219 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1220 tegra_xhci_program_utmip_pad(tegra, 0);
1221 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1222 tegra_xhci_program_utmip_pad(tegra, 1);
1224 if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
1225 tegra_xhci_program_ulpi_pad(tegra, 0);
1227 if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P0)
1228 tegra_xhci_program_hsic_pad(tegra, 0);
1229 if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P1)
1230 tegra_xhci_program_hsic_pad(tegra, 1);
1232 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1233 tegra_xhci_program_ss_pad(tegra, 0);
1235 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1236 reg = readl(tegra->padctl_base + IOPHY_MISC_PAD0_CTL_3_0);
1237 reg &= ~RX_IDLE_MODE;
1238 reg |= RX_IDLE_MODE_OVRD;
1239 writel(reg, tegra->padctl_base + IOPHY_MISC_PAD0_CTL_3_0);
1242 if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1243 tegra_xhci_program_ss_pad(tegra, 1);
1245 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1246 reg = readl(tegra->padctl_base + IOPHY_MISC_PAD1_CTL_3_0);
1247 reg &= ~RX_IDLE_MODE;
1248 reg |= RX_IDLE_MODE_OVRD;
1249 writel(reg, tegra->padctl_base + IOPHY_MISC_PAD1_CTL_3_0);
1253 /* This function read XUSB registers and stores in device context */
1255 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
1258 /* a. Save the IPFS registers */
1259 tegra->sregs.msi_bar_sz =
1260 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
1262 tegra->sregs.msi_axi_barst =
1263 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
1265 tegra->sregs.msi_fpci_barst =
1266 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
1268 tegra->sregs.msi_vec0 =
1269 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
1271 tegra->sregs.msi_en_vec0 =
1272 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
1274 tegra->sregs.fpci_error_masks =
1275 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
1277 tegra->sregs.intr_mask =
1278 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1280 tegra->sregs.ipfs_intr_enable =
1281 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
1283 tegra->sregs.ufpci_config =
1284 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
1286 tegra->sregs.clkgate_hysteresis =
1287 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1289 tegra->sregs.xusb_host_mccif_fifo_cntrl =
1290 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
1292 /* b. Save the CFG registers */
1294 tegra->sregs.hs_pls =
1295 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
1297 tegra->sregs.fs_pls =
1298 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
1300 tegra->sregs.hs_fs_speed =
1301 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
1303 tegra->sregs.hs_fs_pp =
1304 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
1306 tegra->sregs.cfg_aru =
1307 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
1309 tegra->sregs.cfg_order =
1310 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
1312 tegra->sregs.cfg_fladj =
1313 readl(tegra->fpci_base + XUSB_CFG_24);
1315 tegra->sregs.cfg_sid =
1316 readl(tegra->fpci_base + XUSB_CFG_16);
1319 /* This function restores XUSB registers from device context */
1321 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
1323 /* Restore Cfg registers */
1324 writel(tegra->sregs.hs_pls,
1325 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
1327 writel(tegra->sregs.fs_pls,
1328 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
1330 writel(tegra->sregs.hs_fs_speed,
1331 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
1333 writel(tegra->sregs.hs_fs_pp,
1334 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
1336 writel(tegra->sregs.cfg_aru,
1337 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
1339 writel(tegra->sregs.cfg_order,
1340 tegra->fpci_base + XUSB_CFG_FPCICFG);
1342 writel(tegra->sregs.cfg_fladj,
1343 tegra->fpci_base + XUSB_CFG_24);
1345 writel(tegra->sregs.cfg_sid,
1346 tegra->fpci_base + XUSB_CFG_16);
1348 /* Restore IPFS registers */
1350 writel(tegra->sregs.msi_bar_sz,
1351 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
1353 writel(tegra->sregs.msi_axi_barst,
1354 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
1356 writel(tegra->sregs.msi_fpci_barst,
1357 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
1359 writel(tegra->sregs.msi_vec0,
1360 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
1362 writel(tegra->sregs.msi_en_vec0,
1363 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
1365 writel(tegra->sregs.fpci_error_masks,
1366 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
1368 writel(tegra->sregs.intr_mask,
1369 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1371 writel(tegra->sregs.ipfs_intr_enable,
1372 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
1374 writel(tegra->sregs.ufpci_config,
1375 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
1377 writel(tegra->sregs.clkgate_hysteresis,
1378 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1380 writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
1381 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
1384 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
1386 struct platform_device *pdev = tegra->pdev;
1387 u32 reg, timeout = 0xff, cmd;
1389 mutex_lock(&tegra->mbox_lock);
1392 writel(MBOX_OWNER_SW,
1393 tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
1394 reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
1395 usleep_range(10, 20);
1396 } while (reg != MBOX_OWNER_SW && timeout--);
1398 if ((timeout == 0) && (reg != MBOX_OWNER_SW)) {
1399 dev_err(&pdev->dev, "Failed to set mbox message owner ID\n");
1400 mutex_unlock(&tegra->mbox_lock);
1404 writel((MBOX_CMD_MSG_ENABLED << MBOX_CMD_SHIFT),
1405 tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
1407 cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1408 cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
1409 writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1411 mutex_unlock(&tegra->mbox_lock);
1414 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
1416 struct platform_device *pdev = tegra->pdev;
1417 struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
1424 u32 usbsts, count = 0xff;
1425 struct xhci_cap_regs __iomem *cap_regs;
1426 struct xhci_op_regs __iomem *op_regs;
1428 /* enable mbox interrupt */
1429 writel(readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD) | MBOX_INT_EN,
1430 tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1432 /* First thing, reset the ARU. By the time we get to
1433 * loading boot code below, reset would be complete.
1434 * alternatively we can busy wait on rst pending bit.
1436 /* Don't reset during ELPG/LP0 exit path */
1438 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
1439 usleep_range(1000, 2000);
1442 if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
1443 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
1444 csb_read(tegra, XUSB_FALC_CPUCTL));
1448 phys_addr_lo = tegra->firmware.dma;
1449 phys_addr_lo += sizeof(struct cfgtbl);
1451 /* Program the size of DFI into ILOAD_ATTR */
1452 csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
1454 /* Boot code of the firmware reads the ILOAD_BASE_LO register
1455 * to get to the start of the dfi in system memory.
1457 csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
1459 /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
1460 csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
1462 /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
1463 csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
1465 /* Invalidate L2IMEM. */
1466 csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
1468 /* Initiate fetch of Bootcode from system memory into L2IMEM.
1469 * Program BootCode location and size in system memory.
1471 HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
1472 L2IMEMOP_SIZE_SRC_OFFSET_MASK)
1473 << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
1474 HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
1475 L2IMEMOP_SIZE_SRC_COUNT_MASK)
1476 << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
1477 csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
1479 /* Trigger L2IMEM Load operation. */
1480 csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
1482 /* Setup Falcon Auto-fill */
1483 nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
1484 if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
1486 csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
1488 HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
1489 HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
1490 /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
1491 csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
1493 csb_write(tegra, XUSB_FALC_DMACTL, 0);
1496 csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
1498 /* Start Falcon CPU */
1499 csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
1500 usleep_range(1000, 2000);
1502 fw_time = cfg_tbl->fwimg_created_time;
1503 time_to_tm(fw_time, 0, &fw_tm);
1504 dev_info(&pdev->dev,
1505 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
1506 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
1507 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
1508 fw_tm.tm_min, fw_tm.tm_sec,
1509 csb_read(tegra, XUSB_FALC_CPUCTL));
1511 /* return fail if firmware status is not good */
1512 if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
1515 cap_regs = IO_ADDRESS(tegra->host_phy_base);
1516 hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
1517 op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
1519 /* wait for USBSTS_CNR to get set */
1521 usbsts = ioread32(&op_regs->status);
1522 } while ((usbsts & STS_CNR) && count--);
1524 if (!count && (usbsts & STS_CNR)) {
1525 dev_err(&pdev->dev, "Controller not ready\n");
1531 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
1536 reg = readl(tegra->padctl_base + USB2_PAD_MUX_0);
1537 reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1));
1540 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1541 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
1542 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1543 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
1546 writel(reg, tegra->padctl_base + USB2_PAD_MUX_0);
1548 /* SS ELPG Entry initiated by fw */
1549 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
1551 struct xhci_hcd *xhci = tegra->xhci;
1554 must_have_sync_lock(tegra);
1556 /* This is SS partition ELPG entry
1557 * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
1560 /* Step 0: Acquire mbox and send PWRGATE msg to firmware
1561 * only if it is sw initiated one
1564 /* STEP 1: xHCI firmware and xHCIPEP driver communicates
1565 * SuperSpeed partition ELPG entry via mailbox protocol
1568 /* STEP 2: xHCI PEP driver and XUSB device mode driver
1569 * enable the XUSB wakeup interrupts for the SuperSpeed
1570 * and USB2.0 ports assigned to host.Section 4.1 Step 3
1572 tegra_xhci_ss_wake_on_interrupts(tegra, true);
1574 /* STEP 3: xHCI PEP driver initiates the signal sequence
1575 * to enable the XUSB SSwake detection logic for the
1576 * SuperSpeed ports assigned to host.Section 4.1 Step 4
1578 tegra_xhci_ss_wake_signal(tegra, true);
1580 /* STEP 4: System Power Management driver asserts reset
1581 * to XUSB SuperSpeed partition then disables its clocks
1583 tegra_periph_reset_assert(tegra->ss_clk);
1584 clk_disable(tegra->ss_clk);
1586 usleep_range(100, 200);
1588 /* STEP 5: System Power Management driver disables the
1589 * XUSB SuperSpeed partition power rails.
1591 debug_print_portsc(xhci);
1593 /* tegra_powergate_partition also does partition reset assert */
1594 ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
1596 xhci_err(xhci, "%s: could not powergate xusba partition\n",
1598 /* TODO: error recovery? */
1600 tegra->ss_pwr_gated = true;
1602 /* STEP 6: xHCI PEP driver initiates the signal sequence
1603 * to enable the XUSB SSwake detection logic for the
1604 * SuperSpeed ports assigned to host.Section 4.1 Step 7
1606 tegra_xhci_ss_vcore(tegra, true);
1611 /* Host ELPG Entry */
1612 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
1614 struct xhci_hcd *xhci = tegra->xhci;
1617 must_have_sync_lock(tegra);
1619 /* If ss is already powergated skip ss ctx save stuff */
1620 if (tegra->ss_pwr_gated) {
1621 xhci_info(xhci, "%s: SS partition is already powergated\n",
1624 ret = tegra_xhci_ss_elpg_entry(tegra);
1626 xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
1632 /* 1. IS INTR PENDING INT_PENDING=1 ? */
1634 /* STEP 1.1: Do a context save of XUSB and IPFS registers */
1635 tegra_xhci_save_xusb_ctx(tegra);
1639 tegra_xhci_hs_wake_on_interrupts(tegra, true);
1640 xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
1641 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
1643 /* STEP 4: Assert reset to host clk and disable host clk */
1644 tegra_periph_reset_assert(tegra->host_clk);
1646 clk_disable(tegra->host_clk);
1649 usleep_range(150, 200);
1651 /* flush MC client of XUSB_HOST */
1652 tegra_powergate_mc_flush(TEGRA_POWERGATE_XUSBC);
1654 /* STEP 4: Powergate host partition */
1655 /* tegra_powergate_partition also does partition reset assert */
1656 ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
1658 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
1660 /* TODO: error handling? */
1663 tegra->host_pwr_gated = true;
1665 clk_disable(tegra->pll_re_vco_clk);
1666 clk_disable(tegra->emc_clk);
1667 /* set port ownership to SNPS */
1668 tegra_xhci_release_port_ownership(tegra, true);
1670 xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
1671 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
1673 xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
1674 xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
1675 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
1679 /* SS ELPG Exit triggered by PADCTL irq */
1681 * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
1683 * This function must be called with tegra->sync_lock acquired.
1685 * @tegra: xhci controller context
1686 * @return 0 for success, or error numbers
1688 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
1690 struct xhci_hcd *xhci = tegra->xhci;
1693 must_have_sync_lock(tegra);
1695 if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
1696 tegra->hs_wake_event || tegra->host_resume_req)) {
1699 * PWR_UNGATE SS partition. XUSBA
1700 * tegra_unpowergate_partition also does partition reset
1703 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
1706 "%s: could not unpowergate xusba partition %d\n",
1710 if (tegra->ss_wake_event)
1711 tegra->ss_wake_event = false;
1714 xhci_info(xhci, "%s: ss already power gated\n",
1719 /* Step 3: Enable clock to ss partition */
1720 clk_enable(tegra->ss_clk);
1722 /* Step 4: Disable ss wake detection logic */
1723 tegra_xhci_ss_wake_on_interrupts(tegra, false);
1725 /* Step 4.1: Disable ss wake detection logic */
1726 tegra_xhci_ss_vcore(tegra, false);
1729 usleep_range(150, 200);
1731 /* Step 4.2: Disable ss wake detection logic */
1732 tegra_xhci_ss_wake_signal(tegra, false);
1734 /* Step 6 Deassert reset for ss clks */
1735 tegra_periph_reset_deassert(tegra->ss_clk);
1737 xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
1738 tegra->ss_pwr_gated = false;
1743 static void ss_partition_elpg_exit_work(struct work_struct *work)
1745 struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
1748 mutex_lock(&tegra->sync_lock);
1749 tegra_xhci_ss_partition_elpg_exit(tegra);
1750 mutex_unlock(&tegra->sync_lock);
1753 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
1754 static void update_remote_wakeup_ports_pmc(struct tegra_xhci_hcd *tegra)
1756 struct xhci_hcd *xhci = tegra->xhci;
1759 #define PMC_WAKE2_STATUS 0x168
1760 #define PADCTL_WAKE (1 << (58 - 32)) /* PADCTL is WAKE#58 */
1762 wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
1764 if (wake2_status & PADCTL_WAKE) {
1765 /* FIXME: This is customized for Dalmore, find a generic way */
1766 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
1767 /* clear wake status */
1768 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
1771 xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
1772 __func__, tegra->usb3_rh_remote_wakeup_ports);
1775 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
1777 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1778 struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
1779 int port, num_ports;
1780 unsigned long *remote_wakeup_ports;
1782 __le32 __iomem **port_array;
1784 unsigned int retry = 64;
1787 if (hcd == xhci->shared_hcd) {
1788 port_array = xhci->usb3_ports;
1789 num_ports = xhci->num_usb3_ports;
1790 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
1791 rh = "usb3 roothub";
1795 while (*remote_wakeup_ports && retry--) {
1796 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
1797 portsc = xhci_readl(xhci, port_array[port]);
1799 if (!(portsc & PORT_CONNECT)) {
1800 /* nothing to do if already disconnected */
1801 clear_bit(port, remote_wakeup_ports);
1805 if ((portsc & PORT_PLS_MASK) == XDEV_U0)
1806 clear_bit(port, remote_wakeup_ports);
1808 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
1809 __func__, rh, port, portsc);
1812 if (*remote_wakeup_ports)
1813 msleep(20); /* give some time, irq will direct U0 */
1816 xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
1817 *remote_wakeup_ports);
1820 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
1822 u32 reg, utmip_rctrl_val, utmip_tctrl_val;
1824 /* Program XUSB as port owner for both Port 0 and port 1 */
1825 reg = readl(tegra->padctl_base + USB2_PAD_MUX_0);
1826 reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1));
1827 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
1828 USB2_OTG_PAD_PORT_OWNER_XUSB(1);
1829 writel(reg, tegra->padctl_base + USB2_PAD_MUX_0);
1831 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
1832 * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
1834 reg = readl(tegra->padctl_base + USB2_BIAS_PAD_CTL_0_0);
1835 reg &= ~((1 << 12) | (1 << 13));
1836 writel(reg, tegra->padctl_base + USB2_BIAS_PAD_CTL_0_0);
1839 usleep_range(20, 30);
1841 /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
1842 * :: TCTRL and RCTRL
1844 reg = readl(tegra->padctl_base + USB2_BIAS_PAD_CTL_1_0);
1845 utmip_rctrl_val = RCTRL(reg);
1846 utmip_tctrl_val = TCTRL(reg);
1849 * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
1850 * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
1852 pmc_data.utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
1853 pmc_data.utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
1855 xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
1856 pmc_data.utmip_rctrl_val, pmc_data.utmip_tctrl_val);
1858 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
1859 * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
1861 reg = readl(tegra->padctl_base + USB2_BIAS_PAD_CTL_0_0);
1862 reg |= (1 << 12) | (1 << 13);
1863 writel(reg, tegra->padctl_base + USB2_BIAS_PAD_CTL_0_0);
1865 /* Program these values into PMC regiseter and program the
1868 reg = PMC_TCTRL_VAL(pmc_data.utmip_tctrl_val) |
1869 PMC_RCTRL_VAL(pmc_data.utmip_rctrl_val);
1870 tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG, 0xffffffff, reg);
1872 reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
1873 tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
1875 /* Restore correct port ownership in padctl */
1876 reg = readl(tegra->padctl_base + USB2_PAD_MUX_0);
1877 reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1));
1878 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1879 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
1880 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1881 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
1882 writel(reg, tegra->padctl_base + USB2_PAD_MUX_0);
1885 /* Host ELPG Exit triggered by PADCTL irq */
1887 * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
1889 * This function must be called with tegra->sync_lock acquired.
1891 * @tegra: xhci controller context
1892 * @return 0 for success, or error numbers
1895 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
1897 struct xhci_hcd *xhci = tegra->xhci;
1900 must_have_sync_lock(tegra);
1902 if (!tegra->hc_in_elpg)
1905 clk_enable(tegra->emc_clk);
1906 clk_enable(tegra->pll_re_vco_clk);
1907 /* Step 2: Enable clock to host partition */
1908 clk_enable(tegra->host_clk);
1910 if (tegra->lp0_exit) {
1913 tegra_xhci_war_for_tctrl_rctrl(tegra);
1914 /* check if over current seen. Clear if present */
1915 reg = readl(tegra->padctl_base + OC_DET_0);
1916 xhci_dbg(xhci, "%s: OC_DET_0=0x%x\n", __func__, reg);
1917 if (reg & (0x3 << 20)) {
1918 xhci_info(xhci, "Over current detected. Clearing...\n");
1919 writel(reg, tegra->padctl_base + OC_DET_0);
1921 usleep_range(100, 200);
1923 reg = readl(tegra->padctl_base + OC_DET_0);
1924 if (reg & (0x3 << 20))
1925 xhci_info(xhci, "Over current still present\n");
1927 tegra_xhci_padctl_portmap_and_caps(tegra);
1928 /* release clamps post deassert */
1929 tegra->lp0_exit = false;
1932 /* Clear FLUSH_ENABLE of MC client */
1933 tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
1935 /* set port ownership back to xusb */
1936 tegra_xhci_release_port_ownership(tegra, false);
1939 * PWR_UNGATE Host partition. XUSBC
1940 * tegra_unpowergate_partition also does partition reset deassert
1942 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
1944 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
1949 /* Step 4: Deassert reset to host partition clk */
1950 tegra_periph_reset_deassert(tegra->host_clk);
1952 /* Step 6.1: IPFS and XUSB BAR initialization */
1953 tegra_xhci_cfg(tegra);
1955 /* Step 6.2: IPFS and XUSB related restore */
1956 tegra_xhci_restore_ctx(tegra);
1958 /* Step 8: xhci spec related ctx restore
1959 * will be done in xhci_resume().Do it here.
1962 tegra_xhci_ss_partition_elpg_exit(tegra);
1964 /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
1965 if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
1966 clk_set_rate(tegra->ss_src_clk, 3000 * 1000);
1967 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
1970 /* clear ovrd bits */
1971 tegra_xhci_rx_idle_mode_override(tegra, false);
1974 xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
1975 "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
1976 "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
1977 "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
1979 csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
1980 csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
1981 csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
1982 csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
1983 csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
1984 csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
1985 csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
1986 csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
1987 csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
1988 debug_print_portsc(xhci);
1990 ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
1992 xhci_err(xhci, "%s: failed to load firmware %d\n",
1999 tegra->hc_in_elpg = false;
2000 ret = xhci_resume(tegra->xhci, 0);
2002 xhci_err(xhci, "%s: could not resume right %d\n",
2007 update_remote_wakeup_ports_pmc(tegra);
2009 if (tegra->hs_wake_event)
2010 tegra->hs_wake_event = false;
2012 if (tegra->host_resume_req)
2013 tegra->host_resume_req = false;
2015 xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
2016 jiffies_to_msecs(jiffies - tegra->last_jiffies));
2018 tegra->host_pwr_gated = false;
2023 static void host_partition_elpg_exit_work(struct work_struct *work)
2025 struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2026 host_elpg_exit_work);
2028 mutex_lock(&tegra->sync_lock);
2029 tegra_xhci_host_partition_elpg_exit(tegra);
2030 mutex_unlock(&tegra->sync_lock);
2033 /* Mailbox handling function. This function handles requests
2034 * from firmware and communicates with clock and powergating
2035 * module to alter clock rates and to power gate/ungate xusb
2038 * Following is the structure of mailbox messages.
2039 * bit 31:28 - msg type
2040 * bits 27:0 - mbox data
2041 * FIXME: Check if we can just call clock functions like below
2042 * or should we schedule it for calling later ?
2046 tegra_xhci_process_mbox_message(struct work_struct *work)
2048 u32 sw_resp = 0, cmd, data_in, fw_msg;
2050 struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2052 struct xhci_hcd *xhci = tegra->xhci;
2053 unsigned int freq_khz;
2055 mutex_lock(&tegra->mbox_lock);
2057 /* get the owner id */
2058 tegra->mbox_owner = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2059 tegra->mbox_owner &= MBOX_OWNER_ID_MASK;
2061 /* get the mbox message from firmware */
2062 fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
2064 data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2066 mutex_unlock(&tegra->mbox_lock);
2070 /* get cmd type and cmd data */
2071 tegra->cmd_type = (fw_msg & MBOX_CMD_TYPE_MASK) >> MBOX_CMD_SHIFT;
2072 tegra->cmd_data = (fw_msg & MBOX_CMD_DATA_MASK);
2074 /* decode the message and make appropriate requests to
2075 * clock or powergating module.
2078 switch (tegra->cmd_type) {
2079 case MBOX_CMD_INC_FALC_CLOCK:
2080 case MBOX_CMD_DEC_FALC_CLOCK:
2081 ret = tegra_xusb_request_clk_rate(
2087 xhci_err(xhci, "%s: could not set required falc rate\n",
2089 goto send_sw_response;
2090 case MBOX_CMD_INC_SSPI_CLOCK:
2091 case MBOX_CMD_DEC_SSPI_CLOCK:
2092 ret = tegra_xusb_request_clk_rate(
2098 xhci_err(xhci, "%s: could not set required ss rate.\n",
2100 goto send_sw_response;
2101 case MBOX_CMD_SET_BW:
2102 /* fw sends BW request in MByte/sec */
2103 freq_khz = tegra_emc_bw_to_freq_req(tegra->cmd_data << 10);
2104 clk_set_rate(tegra->emc_clk, freq_khz * 1000);
2106 /* clear MBOX_SMI_INT_EN bit */
2107 cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2108 cmd &= ~MBOX_SMI_INT_EN;
2109 writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2111 /* clear mbox owner as ACK will not be sent for this request */
2112 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2114 case MBOX_CMD_SAVE_DFE_CTLE_CTX:
2115 tegra_xhci_save_dfe_ctle_context(tegra, tegra->cmd_data);
2116 tegra_xhci_restore_dfe_ctle_context(tegra, tegra->cmd_data);
2117 sw_resp |= (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
2118 goto send_sw_response;
2120 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2121 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2124 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2125 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2128 xhci_err(xhci, "%s: invalid cmdtype %d\n",
2129 __func__, tegra->cmd_type);
2131 mutex_unlock(&tegra->mbox_lock);
2135 writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2136 cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2137 cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
2138 writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2140 mutex_unlock(&tegra->mbox_lock);
2143 static irqreturn_t tegra_xhci_xusb_host_irq(int irq, void *ptrdev)
2145 struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2146 struct xhci_hcd *xhci = tegra->xhci;
2148 xhci_dbg(xhci, "%s", __func__);
2152 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
2154 struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2155 struct xhci_hcd *xhci = tegra->xhci;
2156 u32 elpg_program0 = 0;
2158 spin_lock(&tegra->lock);
2160 tegra->last_jiffies = jiffies;
2162 /* Check the intr cause. Could be USB2 or HSIC or SS wake events */
2163 elpg_program0 = readl(tegra->padctl_base + ELPG_PROGRAM_0);
2165 /* Clear the interrupt cause. We already read the intr status. */
2166 tegra_xhci_ss_wake_on_interrupts(tegra, false);
2167 tegra_xhci_hs_wake_on_interrupts(tegra, false);
2169 xhci_dbg(xhci, "%s: elpg_program0 = %x\n",
2170 __func__, elpg_program0);
2171 xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
2172 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2173 xhci_dbg(xhci, "%s: PAD ELPG_PROGRAM_0 INTERRUPT REGISTER = %x\n",
2174 __func__, readl(tegra->padctl_base + ELPG_PROGRAM_0));
2175 xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
2176 __func__, readl(tegra->padctl_base + OC_DET_0));
2177 xhci_dbg(xhci, "%s: USB2_BATTERY_CHRG_OTGPAD0_0 Register = %x\n",
2179 readl(tegra->padctl_base + USB2_BATTERY_CHRG_OTGPAD0_0));
2180 xhci_dbg(xhci, "%s: USB2_BATTERY_CHRG_OTGPAD1_0 Register = %x\n",
2182 readl(tegra->padctl_base + USB2_BATTERY_CHRG_OTGPAD1_0));
2183 xhci_dbg(xhci, "%s: USB2_BATTERY_CHRG_BIASPAD_0 Register = %x\n",
2185 readl(tegra->padctl_base + USB2_BATTERY_CHRG_BIASPAD_0));
2187 if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
2188 tegra->ss_wake_event = true;
2189 else if (elpg_program0 &
2190 (USB2_PORT0_WAKEUP_EVENT | USB2_PORT1_WAKEUP_EVENT))
2191 tegra->hs_wake_event = true;
2193 if (tegra->ss_wake_event || tegra->hs_wake_event) {
2194 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
2195 xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
2196 WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
2197 } else if (tegra->ss_pwr_gated
2198 && tegra->host_pwr_gated) {
2199 xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
2201 schedule_work(&tegra->host_elpg_exit_work);
2204 xhci_err(xhci, "error: wake due to no hs/ss event\n");
2205 writel(0xffffffff, tegra->padctl_base + ELPG_PROGRAM_0);
2207 spin_unlock(&tegra->lock);
2211 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
2213 struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2216 spin_lock(&tegra->lock);
2218 /* clear the mbox intr status 1st thing. Other
2219 * bits are W1C bits, so just write to SMI bit.
2222 temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
2224 /* write 1 to clear SMI INTR en bit ( bit 3 ) */
2225 temp = MBOX_SMI_INTR_EN;
2226 writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
2228 schedule_work(&tegra->mbox_work);
2230 spin_unlock(&tegra->lock);
2234 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
2237 * As of now platform drivers don't provide MSI support so we ensure
2238 * here that the generic code does not try to make a pci_dev from our
2239 * dev struct in order to setup MSI
2241 xhci->quirks |= XHCI_BROKEN_MSI;
2242 xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
2245 /* called during probe() after chip reset completes */
2246 static int xhci_plat_setup(struct usb_hcd *hcd)
2248 return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
2251 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
2252 const char *name, void __iomem **region)
2254 struct resource *res;
2257 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
2259 dev_err(&pdev->dev, "memory resource %s doesn't exist\n", name);
2263 mem = devm_request_and_ioremap(&pdev->dev, res);
2265 dev_err(&pdev->dev, "failed to ioremap for %s\n", name);
2273 static int tegra_xhci_request_irq(struct platform_device *pdev,
2274 const char *rscname, irq_handler_t handler, unsigned long irqflags,
2275 const char *devname, int *irq_no)
2278 struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2279 struct resource *res;
2281 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, rscname);
2283 dev_err(&pdev->dev, "irq resource %s doesn't exist\n", rscname);
2287 ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
2291 "failed to request_irq for %s (irq %d), error = %d\n",
2292 devname, res->start, ret);
2295 *irq_no = res->start;
2302 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
2304 struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2305 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2307 unsigned long flags;
2309 mutex_lock(&tegra->sync_lock);
2311 if (xhci->shared_hcd == hcd) {
2312 tegra->usb3_rh_suspend = true;
2313 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
2314 } else if (xhci->main_hcd == hcd) {
2315 tegra->usb2_rh_suspend = true;
2316 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
2319 WARN_ON(tegra->hc_in_elpg);
2321 /* suspend xhci bus. This will also set remote mask */
2322 err = xhci_bus_suspend(hcd);
2324 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
2326 goto xhci_bus_suspend_failed;
2329 if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
2330 goto done; /* one of the root hubs is still working */
2332 spin_lock_irqsave(&tegra->lock, flags);
2333 tegra->hc_in_elpg = true;
2334 spin_unlock_irqrestore(&tegra->lock, flags);
2336 WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
2338 /* save xhci spec ctx. Already done by xhci_suspend */
2339 err = xhci_suspend(tegra->xhci);
2341 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
2342 goto xhci_suspend_failed;
2345 /* Powergate host. Include ss power gate if not already done */
2346 err = tegra_xhci_host_elpg_entry(tegra);
2348 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
2350 goto tegra_xhci_host_elpg_entry_failed;
2353 /* At this point,ensure ss/hs intr enables are always on */
2354 tegra_xhci_ss_wake_on_interrupts(tegra, true);
2355 tegra_xhci_hs_wake_on_interrupts(tegra, true);
2358 /* pads are disabled only if usb2 root hub in xusb is idle */
2359 /* pads will actually be disabled only when all usb2 ports are idle */
2360 if (xhci->main_hcd == hcd) {
2361 utmi_phy_pad_disable();
2362 utmi_phy_iddq_override(true);
2363 /* port ownership to SNPS when no HS connected to save power */
2364 if (!is_any_hs_connected(xhci))
2365 tegra_xhci_release_port_ownership(tegra, true);
2366 } else if (xhci->shared_hcd == hcd) {
2367 /* save leakage power when SS not in use.
2368 * This is also done when fw mbox message is received for freq
2369 * decrease but on T114 we don't change freq due to sw WAR
2370 * used for hs disconnect issue.
2372 tegra_xhci_rx_idle_mode_override(tegra, true);
2374 mutex_unlock(&tegra->sync_lock);
2377 tegra_xhci_host_elpg_entry_failed:
2379 xhci_suspend_failed:
2380 tegra->hc_in_elpg = false;
2381 xhci_bus_suspend_failed:
2382 if (xhci->shared_hcd == hcd)
2383 tegra->usb3_rh_suspend = false;
2384 else if (xhci->main_hcd == hcd)
2385 tegra->usb2_rh_suspend = false;
2387 mutex_unlock(&tegra->sync_lock);
2391 /* First, USB2HCD and then USB3HCD resume will be called */
2392 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
2394 struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2395 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2398 mutex_lock(&tegra->sync_lock);
2400 tegra->host_resume_req = true;
2402 if (xhci->shared_hcd == hcd)
2403 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
2404 else if (xhci->main_hcd == hcd)
2405 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
2407 /* pads are disabled only if usb2 root hub in xusb is idle */
2408 /* pads will actually be disabled only when all usb2 ports are idle */
2409 if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
2410 utmi_phy_pad_enable();
2411 utmi_phy_iddq_override(false);
2412 tegra_xhci_release_port_ownership(tegra, false);
2413 } else if (xhci->shared_hcd == hcd && tegra->usb3_rh_suspend) {
2414 /* clear ovrd bits */
2415 tegra_xhci_rx_idle_mode_override(tegra, false);
2417 if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
2418 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
2419 tegra_xhci_host_partition_elpg_exit(tegra);
2422 /* handle remote wakeup before resuming bus */
2423 wait_remote_wakeup_ports(hcd);
2425 err = xhci_bus_resume(hcd);
2427 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
2429 goto xhci_bus_resume_failed;
2432 if (xhci->shared_hcd == hcd)
2433 tegra->usb3_rh_suspend = false;
2434 else if (xhci->main_hcd == hcd)
2435 tegra->usb2_rh_suspend = false;
2437 mutex_unlock(&tegra->sync_lock);
2440 xhci_bus_resume_failed:
2441 /* TODO: reverse elpg? */
2442 mutex_unlock(&tegra->sync_lock);
2447 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
2449 struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2450 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2451 irqreturn_t iret = IRQ_HANDLED;
2454 spin_lock(&tegra->lock);
2455 if (tegra->hc_in_elpg) {
2456 spin_lock(&xhci->lock);
2457 if (HCD_HW_ACCESSIBLE(hcd)) {
2458 status = xhci_readl(xhci, &xhci->op_regs->status);
2460 xhci_writel(xhci, status, &xhci->op_regs->status);
2462 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
2464 schedule_work(&tegra->host_elpg_exit_work);
2465 spin_unlock(&xhci->lock);
2467 iret = xhci_irq(hcd);
2468 spin_unlock(&tegra->lock);
2474 static const struct hc_driver tegra_plat_xhci_driver = {
2475 .description = "tegra-xhci",
2476 .product_desc = "Nvidia xHCI Host Controller",
2477 .hcd_priv_size = sizeof(struct xhci_hcd *),
2480 * generic hardware linkage
2482 .irq = tegra_xhci_irq,
2483 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
2486 * basic lifecycle operations
2488 .reset = xhci_plat_setup,
2491 .shutdown = xhci_shutdown,
2494 * managing i/o requests and associated device resources
2496 .urb_enqueue = xhci_urb_enqueue,
2497 .urb_dequeue = xhci_urb_dequeue,
2498 .alloc_dev = xhci_alloc_dev,
2499 .free_dev = xhci_free_dev,
2500 .alloc_streams = xhci_alloc_streams,
2501 .free_streams = xhci_free_streams,
2502 .add_endpoint = xhci_add_endpoint,
2503 .drop_endpoint = xhci_drop_endpoint,
2504 .endpoint_reset = xhci_endpoint_reset,
2505 .check_bandwidth = xhci_check_bandwidth,
2506 .reset_bandwidth = xhci_reset_bandwidth,
2507 .address_device = xhci_address_device,
2508 .update_hub_device = xhci_update_hub_device,
2509 .reset_device = xhci_discover_or_reset_device,
2512 * scheduling support
2514 .get_frame_number = xhci_get_frame,
2516 /* Root hub support */
2517 .hub_control = xhci_hub_control,
2518 .hub_status_data = xhci_hub_status_data,
2521 .bus_suspend = tegra_xhci_bus_suspend,
2522 .bus_resume = tegra_xhci_bus_resume,
2528 tegra_xhci_suspend(struct platform_device *pdev,
2531 struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2532 struct xhci_hcd *xhci = tegra->xhci;
2536 mutex_lock(&tegra->sync_lock);
2537 if (!tegra->hc_in_elpg) {
2538 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
2540 mutex_unlock(&tegra->sync_lock);
2543 mutex_unlock(&tegra->sync_lock);
2545 tegra_xhci_ss_wake_on_interrupts(tegra, false);
2546 tegra_xhci_hs_wake_on_interrupts(tegra, false);
2548 /* enable_irq_wake for ss ports */
2549 ret = enable_irq_wake(tegra->padctl_irq);
2552 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
2553 __func__, tegra->padctl_irq, ret);
2556 /* enable_irq_wake for hs/fs/ls ports */
2557 ret = enable_irq_wake(tegra->usb3_irq);
2560 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
2561 __func__, tegra->usb3_irq, ret);
2563 regulator_disable(tegra->xusb_avdd_usb3_pll_reg);
2564 regulator_disable(tegra->xusb_avddio_usb3_reg);
2565 tegra_usb2_clocks_deinit(tegra);
2571 tegra_xhci_resume(struct platform_device *pdev)
2573 struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2575 dev_dbg(&pdev->dev, "%s\n", __func__);
2577 tegra->last_jiffies = jiffies;
2579 disable_irq_wake(tegra->padctl_irq);
2580 disable_irq_wake(tegra->usb3_irq);
2581 tegra->lp0_exit = true;
2583 regulator_enable(tegra->xusb_avddio_usb3_reg);
2584 regulator_enable(tegra->xusb_avdd_usb3_pll_reg);
2585 tegra_usb2_clocks_init(tegra);
2592 static int init_bootloader_firmware(struct tegra_xhci_hcd *tegra)
2594 struct platform_device *pdev = tegra->pdev;
2595 void __iomem *fw_mmio_base;
2596 phys_addr_t fw_mem_phy_addr;
2599 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2603 /* bootloader saved firmware memory address in PMC SCRATCH34 register */
2604 fw_mem_phy_addr = tegra_usb_pmc_reg_read(PMC_SCRATCH34);
2606 fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
2607 fw_mem_phy_addr, sizeof(struct cfgtbl));
2609 if (!fw_mmio_base) {
2610 dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
2615 fw_size = ioread32(fw_mmio_base + FW_SIZE_OFFSET);
2616 devm_iounmap(&pdev->dev, fw_mmio_base);
2618 fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
2619 fw_mem_phy_addr, fw_size);
2620 if (!fw_mmio_base) {
2621 dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
2626 dev_info(&pdev->dev, "Firmware Memory: phy 0x%x mapped 0x%p (%d Bytes)\n",
2627 fw_mem_phy_addr, fw_mmio_base, fw_size);
2629 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2630 fw_dma = dma_map_linear(&pdev->dev, fw_mem_phy_addr, fw_size,
2632 if (fw_dma == DMA_ERROR_CODE) {
2633 dev_err(&pdev->dev, "%s: dma_map_linear failed\n",
2639 fw_dma = fw_mem_phy_addr;
2641 dev_info(&pdev->dev, "Firmware DMA Memory: dma 0x%p (%d Bytes)\n",
2642 (void *) fw_dma, fw_size);
2644 /* all set and ready to go */
2645 tegra->firmware.data = fw_mmio_base;
2646 tegra->firmware.dma = fw_dma;
2647 tegra->firmware.size = fw_size;
2651 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2653 devm_iounmap(&pdev->dev, fw_mmio_base);
2658 static void deinit_bootloader_firmware(struct tegra_xhci_hcd *tegra)
2660 struct platform_device *pdev = tegra->pdev;
2661 void __iomem *fw_mmio_base = tegra->firmware.data;
2663 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2664 dma_unmap_single(&pdev->dev, tegra->firmware.dma,
2665 tegra->firmware.size, DMA_TO_DEVICE);
2667 devm_iounmap(&pdev->dev, fw_mmio_base);
2669 memset(&tegra->firmware, 0, sizeof(tegra->firmware));
2672 static int init_firmware(struct tegra_xhci_hcd *tegra)
2674 return init_bootloader_firmware(tegra);
2677 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
2679 deinit_bootloader_firmware(tegra);
2682 /* TODO: we have to refine error handling in tegra_xhci_probe() */
2683 static int tegra_xhci_probe(struct platform_device *pdev)
2685 const struct hc_driver *driver;
2686 struct xhci_hcd *xhci;
2687 struct tegra_xhci_hcd *tegra;
2688 struct resource *res;
2689 struct usb_hcd *hcd;
2694 BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
2699 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
2701 dev_err(&pdev->dev, "memory alloc failed\n");
2706 ret = tegra_xhci_request_mem_region(pdev, "padctl",
2707 &tegra->padctl_base);
2709 dev_err(&pdev->dev, "failed to map padctl\n");
2713 ret = tegra_xhci_request_mem_region(pdev, "fpci", &tegra->fpci_base);
2715 dev_err(&pdev->dev, "failed to map fpci\n");
2719 ret = tegra_xhci_request_mem_region(pdev, "ipfs", &tegra->ipfs_base);
2721 dev_err(&pdev->dev, "failed to map ipfs\n");
2725 ret = tegra_xusb_partitions_clk_init(tegra);
2728 "failed to initialize xusb partitions clocks\n");
2732 /* Enable power rails to the PAD,VBUS
2733 * and pull-up voltage.Initialize the regulators
2735 ret = tegra_xusb_regulator_init(tegra, pdev);
2737 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
2738 goto err_deinit_xusb_partition_clk;
2741 /* Enable UTMIP, PLLU and PLLE */
2742 ret = tegra_usb2_clocks_init(tegra);
2744 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
2745 goto err_deinit_tegra_xusb_regulator;
2748 /* tegra_unpowergate_partition also does partition reset deassert */
2749 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
2751 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
2753 /* tegra_unpowergate_partition also does partition reset deassert */
2754 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
2756 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
2758 tegra->pdata = dev_get_platdata(&pdev->dev);
2759 tegra->bdata = tegra->pdata->bdata;
2761 /* reset the pointer back to NULL. driver uses it */
2762 /* platform_set_drvdata(pdev, NULL); */
2764 /* calculate rctrl_val and tctrl_val once at boot time */
2765 tegra_xhci_war_for_tctrl_rctrl(tegra);
2767 /* Program the XUSB pads to take ownership of ports */
2768 tegra_xhci_padctl_portmap_and_caps(tegra);
2770 /* Release XUSB wake logic state latching */
2771 tegra_xhci_ss_wake_signal(tegra, false);
2772 tegra_xhci_ss_vcore(tegra, false);
2774 /* Deassert reset to XUSB host, ss, dev clocks */
2775 tegra_periph_reset_deassert(tegra->host_clk);
2776 tegra_periph_reset_deassert(tegra->ss_clk);
2778 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "host");
2780 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
2782 goto err_deinit_usb2_clocks;
2784 tegra->host_phy_base = res->start;
2786 tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
2787 res->start, resource_size(res));
2788 if (!tegra->host_phy_virt_base) {
2789 dev_err(&pdev->dev, "error mapping host phy memory\n");
2791 goto err_deinit_usb2_clocks;
2794 /* Setup IPFS access and BAR0 space */
2795 tegra_xhci_cfg(tegra);
2797 ret = init_firmware(tegra);
2799 dev_err(&pdev->dev, "failed to init firmware\n");
2801 goto err_deinit_usb2_clocks;
2804 ret = load_firmware(tegra, true /* do reset ARU */);
2806 dev_err(&pdev->dev, "failed to load firmware\n");
2808 goto err_deinit_firmware;
2811 device_init_wakeup(&pdev->dev, 1);
2812 driver = &tegra_plat_xhci_driver;
2814 hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
2816 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
2818 goto err_deinit_firmware;
2821 ret = tegra_xhci_request_mem_region(pdev, "host", &hcd->regs);
2823 dev_err(&pdev->dev, "failed to map host\n");
2824 goto err_put_usb2_hcd;
2826 hcd->rsrc_start = res->start;
2827 hcd->rsrc_len = resource_size(res);
2829 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "host");
2831 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
2833 goto err_put_usb2_hcd;
2836 ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
2838 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
2839 goto err_put_usb2_hcd;
2842 /* USB 2.0 roothub is stored in the platform_device now. */
2843 hcd = dev_get_drvdata(&pdev->dev);
2844 xhci = hcd_to_xhci(hcd);
2846 platform_set_drvdata(pdev, tegra);
2848 xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
2849 dev_name(&pdev->dev), hcd);
2850 if (!xhci->shared_hcd) {
2851 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
2853 goto err_remove_usb2_hcd;
2857 * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
2858 * is called by usb_add_hcd().
2860 *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
2862 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
2864 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
2865 goto err_put_usb3_hcd;
2868 device_init_wakeup(&hcd->self.root_hub->dev, 1);
2869 device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
2870 spin_lock_init(&tegra->lock);
2871 mutex_init(&tegra->sync_lock);
2872 mutex_init(&tegra->mbox_lock);
2874 /* do mailbox related initializations */
2875 tegra->mbox_owner = 0xffff;
2876 INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
2878 tegra_xhci_enable_fw_message(tegra);
2880 /* do ss partition elpg exit related initialization */
2881 INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
2883 /* do host partition elpg exit related initialization */
2884 INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
2886 /* Register interrupt handler for SMI line to handle mailbox
2887 * interrupt from firmware
2889 ret = tegra_xhci_request_irq(pdev, "host-smi", tegra_xhci_smi_irq,
2890 IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
2892 goto err_remove_usb3_hcd;
2894 /* Register interrupt handler for PADCTRL line to
2895 * handle wake on connect irqs interrupt from
2898 ret = tegra_xhci_request_irq(pdev, "padctl", tegra_xhci_padctl_irq,
2899 IRQF_SHARED | IRQF_TRIGGER_HIGH,
2900 "tegra_xhci_padctl_irq", &tegra->padctl_irq);
2902 goto err_remove_usb3_hcd;
2904 ret = tegra_xhci_request_irq(pdev, "usb3", tegra_xhci_xusb_host_irq,
2905 IRQF_SHARED | IRQF_TRIGGER_HIGH, "xusb_host_irq",
2908 goto err_remove_usb3_hcd;
2910 tegra->ss_pwr_gated = false;
2911 tegra->host_pwr_gated = false;
2912 tegra->hc_in_elpg = false;
2913 tegra->hs_wake_event = false;
2914 tegra->host_resume_req = false;
2915 tegra->lp0_exit = false;
2916 tegra->dfe_ctle_ctx_saved = false;
2918 /* reset wake event to NONE */
2919 pmc_reg = tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0);
2920 pmc_reg |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE);
2921 pmc_reg |= UTMIP_WAKE_VAL(1, WAKE_VAL_NONE);
2922 pmc_reg |= UTMIP_WAKE_VAL(2, WAKE_VAL_NONE);
2923 pmc_reg |= UTMIP_WAKE_VAL(3, WAKE_VAL_NONE);
2924 tegra_usb_pmc_reg_write(PMC_UTMIP_UHSIC_SLEEP_CFG_0, pmc_reg);
2926 tegra_xhci_debug_read_pads(tegra);
2927 utmi_phy_pad_enable();
2928 utmi_phy_iddq_override(false);
2930 tegra_pd_add_device(&pdev->dev);
2934 err_remove_usb3_hcd:
2935 usb_remove_hcd(xhci->shared_hcd);
2937 usb_put_hcd(xhci->shared_hcd);
2938 err_remove_usb2_hcd:
2940 usb_remove_hcd(hcd);
2943 err_deinit_firmware:
2944 deinit_firmware(tegra);
2945 err_deinit_usb2_clocks:
2946 tegra_usb2_clocks_deinit(tegra);
2947 err_deinit_tegra_xusb_regulator:
2948 tegra_xusb_regulator_deinit(tegra);
2949 err_deinit_xusb_partition_clk:
2950 tegra_xusb_partitions_clk_deinit(tegra);
2955 static int tegra_xhci_remove(struct platform_device *pdev)
2957 struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2958 struct xhci_hcd *xhci = NULL;
2959 struct usb_hcd *hcd = NULL;
2965 hcd = xhci_to_hcd(xhci);
2967 devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
2968 devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
2969 devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
2970 usb_remove_hcd(xhci->shared_hcd);
2971 usb_put_hcd(xhci->shared_hcd);
2972 usb_remove_hcd(hcd);
2976 deinit_firmware(tegra);
2977 tegra_xusb_regulator_deinit(tegra);
2978 tegra_usb2_clocks_deinit(tegra);
2979 if (!tegra->hc_in_elpg)
2980 tegra_xusb_partitions_clk_deinit(tegra);
2981 utmi_phy_pad_disable();
2982 utmi_phy_iddq_override(true);
2987 static void tegra_xhci_shutdown(struct platform_device *pdev)
2989 struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2990 struct xhci_hcd *xhci = NULL;
2991 struct usb_hcd *hcd = NULL;
2996 if (tegra->hc_in_elpg) {
2997 mutex_lock(&tegra->sync_lock);
2998 tegra_xhci_host_partition_elpg_exit(tegra);
2999 mutex_unlock(&tegra->sync_lock);
3002 hcd = xhci_to_hcd(xhci);
3006 static struct platform_driver tegra_xhci_driver = {
3007 .probe = tegra_xhci_probe,
3008 .remove = tegra_xhci_remove,
3009 .shutdown = tegra_xhci_shutdown,
3011 .suspend = tegra_xhci_suspend,
3012 .resume = tegra_xhci_resume,
3015 .name = "tegra-xhci",
3018 MODULE_ALIAS("platform:tegra-xhci");
3020 int tegra_xhci_register_plat(void)
3022 return platform_driver_register(&tegra_xhci_driver);
3025 void tegra_xhci_unregister_plat(void)
3027 platform_driver_unregister(&tegra_xhci_driver);