c0a2ace5644a6aa50680c90c473e526244b35a76
[linux-3.10.git] / drivers / usb / host / xhci-tegra.c
1 /*
2  * xhci-tegra.c - Nvidia xHCI host controller driver
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/clk.h>
24 #include <linux/ioport.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irq.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/uaccess.h>
30 #include <linux/circ_buf.h>
31 #include <linux/vmalloc.h>
32 #include <linux/debugfs.h>
33 #include <linux/kthread.h>
34 #include <linux/gpio.h>
35 #include <linux/usb/otg.h>
36 #include <linux/clk/tegra.h>
37 #include <linux/tegra-powergate.h>
38
39 #include <mach/tegra_usb_pad_ctrl.h>
40 #include <mach/tegra_usb_pmc.h>
41 #include <mach/pm_domains.h>
42 #include <mach/mc.h>
43 #include <mach/xusb.h>
44
45 #include "../../../arch/arm/mach-tegra/iomap.h" /* HACK -- remove */
46 #include "xhci-tegra.h"
47 #include "xhci.h"
48
49 /* macros */
50 #define FW_IOCTL_LOG_DEQUEUE_LOW        (4)
51 #define FW_IOCTL_LOG_DEQUEUE_HIGH       (5)
52 #define FW_IOCTL_DATA_SHIFT             (0)
53 #define FW_IOCTL_DATA_MASK              (0x00ffffff)
54 #define FW_IOCTL_TYPE_SHIFT             (24)
55 #define FW_IOCTL_TYPE_MASK              (0xff000000)
56 #define FW_LOG_SIZE                     (sizeof(struct log_entry))
57 #define FW_LOG_COUNT                    (4096)
58 #define FW_LOG_RING_SIZE                (FW_LOG_SIZE * FW_LOG_COUNT)
59 #define FW_LOG_PAYLOAD_SIZE             (27)
60 #define DRIVER                          (0x01)
61 #define CIRC_BUF_SIZE                   (4 * (1 << 20)) /* 4MB */
62 #define FW_LOG_THREAD_RELAX             (msecs_to_jiffies(100))
63
64 /* tegra_xhci_firmware_log.flags bits */
65 #define FW_LOG_CONTEXT_VALID            (0)
66 #define FW_LOG_FILE_OPENED              (1)
67
68 #define PAGE_SELECT_MASK                        0xFFFFFE00
69 #define PAGE_SELECT_SHIFT                       9
70 #define PAGE_OFFSET_MASK                        0x000001FF
71 #define CSB_PAGE_SELECT(_addr)                                          \
72         ({                                                              \
73                 typecheck(u32, _addr);                                  \
74                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
75         })
76 #define CSB_PAGE_OFFSET(_addr)                                          \
77         ({                                                              \
78                 typecheck(u32, _addr);                                  \
79                 (_addr & PAGE_OFFSET_MASK);                             \
80         })
81
82 #define reg_dump(_dev, _base, _reg)                                     \
83         dev_dbg(_dev, "%s: %s @%x = 0x%x\n", __func__, #_reg,           \
84                 _reg, readl(_base + _reg))
85
86 /* PMC register definition */
87 #define PMC_PORT_UTMIP_P0               0
88 #define PMC_PORT_UTMIP_P1               1
89 #define PMC_PORT_UTMIP_P2               2
90 #define PMC_PORT_UHSIC_P0               3
91 #define PMC_PORT_NUM                    4
92
93 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
94 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
95 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
96
97 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
98
99 /* private data types */
100 /* command requests from the firmware */
101 enum MBOX_CMD_TYPE {
102         MBOX_CMD_MSG_ENABLED = 1,
103         MBOX_CMD_INC_FALC_CLOCK,
104         MBOX_CMD_DEC_FALC_CLOCK,
105         MBOX_CMD_INC_SSPI_CLOCK,
106         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
107         MBOX_CMD_SET_BW,
108         MBOX_CMD_SET_SS_PWR_GATING,
109         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
110         MBOX_CMD_SAVE_DFE_CTLE_CTX,
111         MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
112         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* 11, unused */
113         MBOX_CMD_STAR_HSIC_IDLE,
114         MBOX_CMD_STOP_HSIC_IDLE,
115         MBOX_CMD_DBC_WAKE_STACK, /* unused */
116         MBOX_CMD_HSIC_PRETEND_CONNECT,
117
118         /* needs to be the last cmd */
119         MBOX_CMD_MAX,
120
121         /* resp msg to ack above commands */
122         MBOX_CMD_ACK = 128,
123         MBOX_CMD_NACK
124 };
125
126 struct log_entry {
127         u32 sequence_no;
128         u8 data[FW_LOG_PAYLOAD_SIZE];
129         u8 owner;
130 };
131
132 /* Usb3 Firmware Cfg Table */
133 struct cfgtbl {
134         u32 boot_loadaddr_in_imem;
135         u32 boot_codedfi_offset;
136         u32 boot_codetag;
137         u32 boot_codesize;
138
139         /* Physical memory reserved by Bootloader/BIOS */
140         u32 phys_memaddr;
141         u16 reqphys_memsize;
142         u16 alloc_phys_memsize;
143
144         /* .rodata section */
145         u32 rodata_img_offset;
146         u32 rodata_section_start;
147         u32 rodata_section_end;
148         u32 main_fnaddr;
149
150         u32 fwimg_cksum;
151         u32 fwimg_created_time;
152
153         /* Fields that get filled by linker during linking phase
154          * or initialized in the FW code.
155          */
156         u32 imem_resident_start;
157         u32 imem_resident_end;
158         u32 idirect_start;
159         u32 idirect_end;
160         u32 l2_imem_start;
161         u32 l2_imem_end;
162         u32 version_id;
163         u8 init_ddirect;
164         u8 reserved[3];
165         u32 phys_addr_log_buffer;
166         u32 total_log_entries;
167         u32 dequeue_ptr;
168
169         /*      Below two dummy variables are used to replace
170          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
171          *      retain the size of struct _CFG_TBL used by other AP/Module.
172          */
173         u32 dummy_var1;
174         u32 dummy_var2;
175
176         /* fwimg_len */
177         u32 fwimg_len;
178         u8 magic[8];
179         u32 SS_low_power_entry_timeout;
180         u8 num_hsic_port;
181         u8 padding[139]; /* padding bytes to makeup 256-bytes cfgtbl */
182 };
183
184 struct xusb_save_regs {
185         u32 msi_bar_sz;
186         u32 msi_axi_barst;
187         u32 msi_fpci_barst;
188         u32 msi_vec0;
189         u32 msi_en_vec0;
190         u32 fpci_error_masks;
191         u32 intr_mask;
192         u32 ipfs_intr_enable;
193         u32 ufpci_config;
194         u32 clkgate_hysteresis;
195         u32 xusb_host_mccif_fifo_cntrl;
196
197         /* PG does not mention below */
198         u32 hs_pls;
199         u32 fs_pls;
200         u32 hs_fs_speed;
201         u32 hs_fs_pp;
202         u32 cfg_aru;
203         u32 cfg_order;
204         u32 cfg_fladj;
205         u32 cfg_sid;
206         /* DFE and CTLE */
207         u32 tap1_val[XUSB_SS_PORT_COUNT];
208         u32 amp_val[XUSB_SS_PORT_COUNT];
209         u32 ctle_z_val[XUSB_SS_PORT_COUNT];
210         u32 ctle_g_val[XUSB_SS_PORT_COUNT];
211 };
212
213 struct tegra_xhci_firmware {
214         void *data; /* kernel virtual address */
215         size_t size; /* firmware size */
216         dma_addr_t dma; /* dma address for controller */
217 };
218
219 struct tegra_xhci_firmware_log {
220         dma_addr_t phys_addr;           /* dma-able address */
221         void *virt_addr;                /* kernel va of the shared log buffer */
222         struct log_entry *dequeue;      /* current dequeue pointer (va) */
223         struct circ_buf circ;           /* big circular buffer */
224         u32 seq;                        /* log sequence number */
225
226         struct task_struct *thread;     /* a thread to consume log */
227         struct mutex mutex;
228         wait_queue_head_t read_wait;
229         wait_queue_head_t write_wait;
230         wait_queue_head_t intr_wait;
231         struct dentry *path;
232         struct dentry *log_file;
233         unsigned long flags;
234 };
235
236 /* structure to hold the offsets of padctl registers */
237 struct tegra_xusb_padctl_regs {
238         u16 boot_media_0;
239         u16 usb2_pad_mux_0;
240         u16 usb2_port_cap_0;
241         u16 snps_oc_map_0;
242         u16 usb2_oc_map_0;
243         u16 ss_port_map_0;
244         u16 oc_det_0;
245         u16 elpg_program_0;
246         u16 usb2_bchrg_otgpad0_ctl0_0;
247         u16 usb2_bchrg_otgpad0_ctl1_0;
248         u16 usb2_bchrg_otgpad1_ctl0_0;
249         u16 usb2_bchrg_otgpad1_ctl1_0;
250         u16 usb2_bchrg_otgpad2_ctl0_0;
251         u16 usb2_bchrg_otgpad2_ctl1_0;
252         u16 usb2_bchrg_bias_pad_0;
253         u16 usb2_bchrg_tdcd_dbnc_timer_0;
254         u16 iophy_pll_p0_ctl1_0;
255         u16 iophy_pll_p0_ctl2_0;
256         u16 iophy_pll_p0_ctl3_0;
257         u16 iophy_pll_p0_ctl4_0;
258         u16 iophy_usb3_pad0_ctl1_0;
259         u16 iophy_usb3_pad1_ctl1_0;
260         u16 iophy_usb3_pad0_ctl2_0;
261         u16 iophy_usb3_pad1_ctl2_0;
262         u16 iophy_usb3_pad0_ctl3_0;
263         u16 iophy_usb3_pad1_ctl3_0;
264         u16 iophy_usb3_pad0_ctl4_0;
265         u16 iophy_usb3_pad1_ctl4_0;
266         u16 iophy_misc_pad_p0_ctl1_0;
267         u16 iophy_misc_pad_p1_ctl1_0;
268         u16 iophy_misc_pad_p0_ctl2_0;
269         u16 iophy_misc_pad_p1_ctl2_0;
270         u16 iophy_misc_pad_p0_ctl3_0;
271         u16 iophy_misc_pad_p1_ctl3_0;
272         u16 iophy_misc_pad_p0_ctl4_0;
273         u16 iophy_misc_pad_p1_ctl4_0;
274         u16 iophy_misc_pad_p0_ctl5_0;
275         u16 iophy_misc_pad_p1_ctl5_0;
276         u16 iophy_misc_pad_p0_ctl6_0;
277         u16 iophy_misc_pad_p1_ctl6_0;
278         u16 usb2_otg_pad0_ctl0_0;
279         u16 usb2_otg_pad1_ctl0_0;
280         u16 usb2_otg_pad2_ctl0_0;
281         u16 usb2_otg_pad0_ctl1_0;
282         u16 usb2_otg_pad1_ctl1_0;
283         u16 usb2_otg_pad2_ctl1_0;
284         u16 usb2_bias_pad_ctl0_0;
285         u16 usb2_bias_pad_ctl1_0;
286         u16 usb2_hsic_pad0_ctl0_0;
287         u16 usb2_hsic_pad1_ctl0_0;
288         u16 usb2_hsic_pad0_ctl1_0;
289         u16 usb2_hsic_pad1_ctl1_0;
290         u16 usb2_hsic_pad0_ctl2_0;
291         u16 usb2_hsic_pad1_ctl2_0;
292         u16 ulpi_link_trim_ctl0;
293         u16 ulpi_null_clk_trim_ctl0;
294         u16 hsic_strb_trim_ctl0;
295         u16 wake_ctl0;
296         u16 pm_spare0;
297         u16 iophy_misc_pad_p2_ctl1_0;
298         u16 iophy_misc_pad_p3_ctl1_0;
299         u16 iophy_misc_pad_p4_ctl1_0;
300         u16 iophy_misc_pad_p2_ctl2_0;
301         u16 iophy_misc_pad_p3_ctl2_0;
302         u16 iophy_misc_pad_p4_ctl2_0;
303         u16 iophy_misc_pad_p2_ctl3_0;
304         u16 iophy_misc_pad_p3_ctl3_0;
305         u16 iophy_misc_pad_p4_ctl3_0;
306         u16 iophy_misc_pad_p2_ctl4_0;
307         u16 iophy_misc_pad_p3_ctl4_0;
308         u16 iophy_misc_pad_p4_ctl4_0;
309         u16 iophy_misc_pad_p2_ctl5_0;
310         u16 iophy_misc_pad_p3_ctl5_0;
311         u16 iophy_misc_pad_p4_ctl5_0;
312         u16 iophy_misc_pad_p2_ctl6_0;
313         u16 iophy_misc_pad_p3_ctl6_0;
314         u16 iophy_misc_pad_p4_ctl6_0;
315         u16 usb3_pad_mux_0;
316         u16 iophy_pll_s0_ctl1_0;
317         u16 iophy_pll_s0_ctl2_0;
318         u16 iophy_pll_s0_ctl3_0;
319         u16 iophy_pll_s0_ctl4_0;
320         u16 iophy_misc_pad_s0_ctl1_0;
321         u16 iophy_misc_pad_s0_ctl2_0;
322         u16 iophy_misc_pad_s0_ctl3_0;
323         u16 iophy_misc_pad_s0_ctl4_0;
324         u16 iophy_misc_pad_s0_ctl5_0;
325         u16 iophy_misc_pad_s0_ctl6_0;
326 };
327
328 struct tegra_xhci_hcd {
329         struct platform_device *pdev;
330         struct xhci_hcd *xhci;
331         u16 device_id;
332
333         spinlock_t lock;
334         struct mutex sync_lock;
335
336         int smi_irq;
337         int padctl_irq;
338         int usb3_irq;
339         int usb2_irq;
340
341         bool ss_wake_event;
342         bool ss_pwr_gated;
343         bool host_pwr_gated;
344         bool hs_wake_event;
345         bool host_resume_req;
346         bool lp0_exit;
347         bool dfe_ctx_saved[XUSB_SS_PORT_COUNT];
348         bool ctle_ctx_saved[XUSB_SS_PORT_COUNT];
349         unsigned long last_jiffies;
350         unsigned long host_phy_base;
351         void __iomem *host_phy_virt_base;
352
353         void __iomem *padctl_base;
354         void __iomem *fpci_base;
355         void __iomem *ipfs_base;
356
357         struct tegra_xusb_platform_data *pdata;
358         struct tegra_xusb_board_data *bdata;
359         struct tegra_xusb_padctl_regs *padregs;
360
361         /* mailbox variables */
362         struct mutex mbox_lock;
363         u32 mbox_owner;
364         u32 cmd_type;
365         u32 cmd_data;
366
367         struct regulator *xusb_s5p0v_reg;
368         struct regulator *xusb_s5p0v1_reg;
369         struct regulator *xusb_s5p0v2_reg;
370         struct regulator *xusb_s1p05v_reg;
371         struct regulator *xusb_s3p3v_reg;
372         struct regulator *xusb_s1p8v_reg;
373         struct regulator *vddio_hsic_reg;
374         int vddio_hsic_refcnt;
375
376         struct work_struct mbox_work;
377         struct work_struct ss_elpg_exit_work;
378         struct work_struct host_elpg_exit_work;
379
380         struct clk *host_clk;
381         struct clk *ss_clk;
382
383         /* XUSB Falcon SuperSpeed Clock */
384         struct clk *falc_clk;
385
386         /* EMC Clock */
387         struct clk *emc_clk;
388         /* XUSB SS PI Clock */
389         struct clk *ss_src_clk;
390         /* PLLE Clock */
391         struct clk *plle_clk;
392         struct clk *pll_u_480M;
393         struct clk *clk_m;
394         /* refPLLE clk */
395         struct clk *pll_re_vco_clk;
396         /*
397          * XUSB/IPFS specific registers these need to be saved/restored in
398          * addition to spec defined registers
399          */
400         struct xusb_save_regs sregs;
401         bool usb2_rh_suspend;
402         bool usb3_rh_suspend;
403         bool hc_in_elpg;
404
405         /* otg transceiver */
406         struct usb_phy *transceiver;
407         struct notifier_block otgnb;
408
409         unsigned long usb2_rh_remote_wakeup_ports; /* one bit per port */
410         unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
411         /* firmware loading related */
412         struct tegra_xhci_firmware firmware;
413
414         struct tegra_xhci_firmware_log log;
415 };
416
417 static struct tegra_usb_pmc_data pmc_data[XUSB_UTMI_COUNT];
418 static struct tegra_usb_pmc_data pmc_hsic_data[XUSB_HSIC_COUNT];
419 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
420         u8 port)  __attribute__ ((unused));
421
422 /* functions */
423 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
424 {
425         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
426 }
427
428 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
429 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
430 {
431         WARN_ON(tegra->sync_lock.owner != current);
432 }
433 #else
434 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
435 #endif
436
437 #define for_each_enabled_hsic_pad(_pad, _tegra_xhci_hcd)                \
438         for (_pad = find_next_enabled_hsic_pad(_tegra_xhci_hcd, 0);     \
439             (_pad < XUSB_HSIC_COUNT) && (_pad >= 0);                    \
440             _pad = find_next_enabled_hsic_pad(_tegra_xhci_hcd, _pad + 1))
441
442 static inline int find_next_enabled_pad(struct tegra_xhci_hcd *tegra,
443                                                 int start, int last)
444 {
445         unsigned long portmap = tegra->bdata->portmap;
446         return find_next_bit(&portmap, last , start);
447 }
448
449 static inline int find_next_enabled_hsic_pad(struct tegra_xhci_hcd *tegra,
450                                                 int curr_pad)
451 {
452         int start = XUSB_HSIC_INDEX + curr_pad;
453         int last = XUSB_HSIC_INDEX + XUSB_HSIC_COUNT;
454
455         if ((curr_pad < 0) || (curr_pad >= XUSB_HSIC_COUNT))
456                 return -1;
457
458         return find_next_enabled_pad(tegra, start, last) - XUSB_HSIC_INDEX;
459 }
460
461 static void tegra_xhci_setup_gpio_for_ss_lane(struct tegra_xhci_hcd *tegra)
462 {
463         int err = 0;
464
465         if (!tegra->bdata->gpio_controls_muxed_ss_lanes)
466                 return;
467
468         if (tegra->bdata->lane_owner & BIT(0)) {
469                 /* USB3_SS port1 is using SATA lane so set (MUX_SATA)
470                  * GPIO P11 to '0'
471                  */
472                 err = gpio_request((tegra->bdata->gpio_ss1_sata & 0xffff),
473                         "gpio_ss1_sata");
474                 if (err < 0)
475                         pr_err("%s: gpio_ss1_sata gpio_request failed %d\n",
476                                 __func__, err);
477                 err = gpio_direction_output((tegra->bdata->gpio_ss1_sata
478                         & 0xffff), 1);
479                 if (err < 0)
480                         pr_err("%s: gpio_ss1_sata gpio_direction failed %d\n",
481                                 __func__, err);
482                 __gpio_set_value((tegra->bdata->gpio_ss1_sata & 0xffff),
483                                 ((tegra->bdata->gpio_ss1_sata >> 16)));
484         }
485 }
486
487 static u32 xhci_read_portsc(struct xhci_hcd *xhci, unsigned int port)
488 {
489         int num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
490         __le32 __iomem *addr;
491
492         if (port >= num_ports) {
493                 xhci_err(xhci, "%s invalid port %u\n", __func__, port);
494                 return -1;
495         }
496
497         addr = &xhci->op_regs->port_status_base + (NUM_PORT_REGS * port);
498         return xhci_readl(xhci, addr);
499 }
500
501 static void debug_print_portsc(struct xhci_hcd *xhci)
502 {
503         __le32 __iomem *addr = &xhci->op_regs->port_status_base;
504         u32 reg;
505         int i;
506         int ports;
507
508         ports = HCS_MAX_PORTS(xhci->hcs_params1);
509         for (i = 0; i < ports; i++) {
510                 reg = xhci_read_portsc(xhci, i);
511                 xhci_dbg(xhci, "@%p port %d status reg = 0x%x\n",
512                                 addr, i, (unsigned int) reg);
513                 addr += NUM_PORT_REGS;
514         }
515 }
516 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra);
517
518 static bool is_otg_host(struct tegra_xhci_hcd *tegra)
519 {
520         if (!tegra->transceiver)
521                 return true;
522         else if (tegra->transceiver->state == OTG_STATE_A_HOST)
523                 return true;
524         else
525                 return false;
526 }
527
528 static int update_speed(struct tegra_xhci_hcd *tegra, u8 port)
529 {
530         struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
531         u32 portsc;
532
533         portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port));
534         if (DEV_FULLSPEED(portsc))
535                 return USB_PMC_PORT_SPEED_FULL;
536         else if (DEV_HIGHSPEED(portsc))
537                 return USB_PMC_PORT_SPEED_HIGH;
538         else if (DEV_LOWSPEED(portsc))
539                 return USB_PMC_PORT_SPEED_LOW;
540         else if (DEV_SUPERSPEED(portsc))
541                 return USB_PMC_PORT_SPEED_SUPER;
542         else
543                 return USB_PMC_PORT_SPEED_UNKNOWN;
544 }
545
546 static void pmc_init(struct tegra_xhci_hcd *tegra)
547 {
548         struct tegra_usb_pmc_data *pmc;
549         struct device *dev = &tegra->pdev->dev;
550         int pad;
551
552         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
553                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
554                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
555                         pmc = &pmc_data[pad];
556                         pmc->instance = pad;
557                         pmc->phy_type = TEGRA_USB_PHY_INTF_UTMI;
558                         pmc->port_speed = USB_PMC_PORT_SPEED_HIGH;
559                         pmc->controller_type = TEGRA_USB_3_0;
560                         tegra_usb_pmc_init(pmc);
561                 }
562         }
563
564         for_each_enabled_hsic_pad(pad, tegra) {
565                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
566                 pmc = &pmc_hsic_data[pad];
567                 pmc->instance = pad + 1;
568                 pmc->phy_type = TEGRA_USB_PHY_INTF_HSIC;
569                 pmc->port_speed = USB_PMC_PORT_SPEED_HIGH;
570                 pmc->controller_type = TEGRA_USB_3_0;
571                 tegra_usb_pmc_init(pmc);
572         }
573 }
574
575 static void pmc_setup_wake_detect(struct tegra_xhci_hcd *tegra)
576 {
577         struct tegra_usb_pmc_data *pmc;
578         struct device *dev = &tegra->pdev->dev;
579         u32 portsc;
580         int port;
581         int pad;
582
583         for_each_enabled_hsic_pad(pad, tegra) {
584                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
585
586                 pmc = &pmc_hsic_data[pad];
587                 port = hsic_pad_to_port(pad);
588                 portsc = xhci_read_portsc(tegra->xhci, port);
589                 dev_dbg(dev, "%s hsic pad %d portsc 0x%x\n",
590                         __func__, pad, portsc);
591
592                 if (((int) portsc != -1) && (portsc & PORT_CONNECT))
593                         pmc->pmc_ops->setup_pmc_wake_detect(pmc);
594         }
595
596         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
597                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
598                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
599                         pmc = &pmc_data[pad];
600                         pmc->port_speed = update_speed(tegra, pad);
601                         if (pad == 0) {
602                                 if (is_otg_host(tegra))
603                                         pmc->pmc_ops->setup_pmc_wake_detect(
604                                                                         pmc);
605                         } else
606                                 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
607                 }
608         }
609 }
610
611 static void pmc_disable_bus_ctrl(struct tegra_xhci_hcd *tegra)
612 {
613         struct tegra_usb_pmc_data *pmc;
614         struct device *dev = &tegra->pdev->dev;
615         int pad;
616
617         for_each_enabled_hsic_pad(pad, tegra) {
618                 dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
619
620                 pmc = &pmc_hsic_data[pad];
621                 pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
622         }
623
624         for (pad = 0; pad < XUSB_UTMI_COUNT; pad++) {
625                 if (BIT(XUSB_UTMI_INDEX + pad) & tegra->bdata->portmap) {
626                         dev_dbg(dev, "%s utmi pad %d\n", __func__, pad);
627                         pmc = &pmc_data[pad];
628                         pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
629                 }
630         }
631 }
632
633 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
634 {
635         void __iomem *fpci_base = tegra->fpci_base;
636         struct platform_device *pdev = tegra->pdev;
637         u32 input_addr;
638         u32 data;
639         u32 csb_page_select;
640
641         /* to select the appropriate CSB page to write to */
642         csb_page_select = CSB_PAGE_SELECT(addr);
643
644         dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
645                         csb_page_select);
646
647         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
648
649         /* selects the appropriate offset in the page to read from */
650         input_addr = CSB_PAGE_OFFSET(addr);
651         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
652
653         dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
654                         input_addr, data);
655         return data;
656 }
657
658 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
659 {
660         void __iomem *fpci_base = tegra->fpci_base;
661         struct platform_device *pdev = tegra->pdev;
662         u32 input_addr;
663         u32 csb_page_select;
664
665         /* to select the appropriate CSB page to write to */
666         csb_page_select = CSB_PAGE_SELECT(addr);
667
668         dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
669                         csb_page_select);
670
671         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
672
673         /* selects the appropriate offset in the page to write to */
674         input_addr = CSB_PAGE_OFFSET(addr);
675         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
676
677         dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
678                         input_addr, data);
679 }
680
681 static int fw_message_send(struct tegra_xhci_hcd *tegra,
682         enum MBOX_CMD_TYPE type, u32 data)
683 {
684         struct device *dev = &tegra->pdev->dev;
685         void __iomem *base = tegra->fpci_base;
686         unsigned long target;
687         u32 reg;
688
689         dev_dbg(dev, "%s type %d data 0x%x\n", __func__, type, data);
690
691         mutex_lock(&tegra->mbox_lock);
692
693         target = jiffies + msecs_to_jiffies(20);
694         /* wait mailbox to become idle, timeout in 20ms */
695         while (((reg = readl(base + XUSB_CFG_ARU_MBOX_OWNER)) != 0) &&
696                 time_is_after_jiffies(target)) {
697                 mutex_unlock(&tegra->mbox_lock);
698                 usleep_range(100, 200);
699                 mutex_lock(&tegra->mbox_lock);
700         }
701
702         if (reg != 0) {
703                 dev_err(dev, "%s mailbox is still busy\n", __func__);
704                 goto timeout;
705         }
706
707         target = jiffies + msecs_to_jiffies(10);
708         /* acquire mailbox , timeout in 10ms */
709         writel(MBOX_OWNER_SW, base + XUSB_CFG_ARU_MBOX_OWNER);
710         while (((reg = readl(base + XUSB_CFG_ARU_MBOX_OWNER)) != MBOX_OWNER_SW)
711                 && time_is_after_jiffies(target)) {
712                 mutex_unlock(&tegra->mbox_lock);
713                 usleep_range(100, 200);
714                 mutex_lock(&tegra->mbox_lock);
715                 writel(MBOX_OWNER_SW, base + XUSB_CFG_ARU_MBOX_OWNER);
716         }
717
718         if (reg != MBOX_OWNER_SW) {
719                 dev_err(dev, "%s acquire mailbox timeout\n", __func__);
720                 goto timeout;
721         }
722
723         reg = CMD_TYPE(type) | CMD_DATA(data);
724         writel(reg, base + XUSB_CFG_ARU_MBOX_DATA_IN);
725
726         reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
727         reg |= MBOX_INT_EN | MBOX_FALC_INT_EN;
728         writel(reg, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
729
730         mutex_unlock(&tegra->mbox_lock);
731         return 0;
732
733 timeout:
734         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_CMD);
735         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_DATA_IN);
736         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_DATA_OUT);
737         reg_dump(dev, base, XUSB_CFG_ARU_MBOX_OWNER);
738         mutex_unlock(&tegra->mbox_lock);
739         return -ETIMEDOUT;
740 }
741
742 /**
743  * fw_log_next - find next log entry in a tegra_xhci_firmware_log context.
744  *      This function takes care of wrapping. That means when current log entry
745  *      is the last one, it returns with the first one.
746  *
747  * @param log   The tegra_xhci_firmware_log context.
748  * @param this  The current log entry.
749  * @return      The log entry which is next to the current one.
750  */
751 static inline struct log_entry *fw_log_next(
752                 struct tegra_xhci_firmware_log *log, struct log_entry *this)
753 {
754         struct log_entry *first = (struct log_entry *) log->virt_addr;
755         struct log_entry *last = first + FW_LOG_COUNT - 1;
756
757         WARN((this < first) || (this > last), "%s: invalid input\n", __func__);
758
759         return (this == last) ? first : (this + 1);
760 }
761
762 /**
763  * fw_log_update_dequeue_pointer - update dequeue pointer to both firmware and
764  *      tegra_xhci_firmware_log.dequeue.
765  *
766  * @param log   The tegra_xhci_firmware_log context.
767  * @param n     Counts of log entries to fast-forward.
768  */
769 static inline void fw_log_update_deq_pointer(
770                 struct tegra_xhci_firmware_log *log, int n)
771 {
772         struct tegra_xhci_hcd *tegra =
773                         container_of(log, struct tegra_xhci_hcd, log);
774         struct device *dev = &tegra->pdev->dev;
775         struct log_entry *deq = tegra->log.dequeue;
776         dma_addr_t physical_addr;
777         u32 reg;
778
779         dev_dbg(dev, "curr 0x%p fast-forward %d entries\n", deq, n);
780         while (n-- > 0)
781                 deq = fw_log_next(log, deq);
782
783         tegra->log.dequeue = deq;
784         physical_addr = tegra->log.phys_addr +
785                         ((u8 *)deq - (u8 *)tegra->log.virt_addr);
786
787         /* update dequeue pointer to firmware */
788         reg = (FW_IOCTL_LOG_DEQUEUE_LOW << FW_IOCTL_TYPE_SHIFT);
789         reg |= (physical_addr & 0xffff); /* lower 16-bits */
790         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
791
792         reg = (FW_IOCTL_LOG_DEQUEUE_HIGH << FW_IOCTL_TYPE_SHIFT);
793         reg |= ((physical_addr >> 16) & 0xffff); /* higher 16-bits */
794         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
795
796         dev_dbg(dev, "new 0x%p physical addr 0x%x\n", deq, physical_addr);
797 }
798
799 static inline bool circ_buffer_full(struct circ_buf *circ)
800 {
801         int space = CIRC_SPACE(circ->head, circ->tail, CIRC_BUF_SIZE);
802
803         return (space <= FW_LOG_SIZE);
804 }
805
806 static inline bool fw_log_available(struct tegra_xhci_hcd *tegra)
807 {
808         return (tegra->log.dequeue->owner == DRIVER);
809 }
810
811 /**
812  * fw_log_wait_empty_timeout - wait firmware log thread to clean up shared
813  *      log buffer.
814  * @param tegra:        tegra_xhci_hcd context
815  * @param msec:         timeout value in millisecond
816  * @return true:        shared log buffer is empty,
817  *         false:       shared log buffer isn't empty.
818  */
819 static inline bool fw_log_wait_empty_timeout(struct tegra_xhci_hcd *tegra,
820                 unsigned timeout)
821 {
822         unsigned long target = jiffies + msecs_to_jiffies(timeout);
823         bool ret;
824
825         mutex_lock(&tegra->log.mutex);
826
827         while (fw_log_available(tegra) && time_is_after_jiffies(target)) {
828                 mutex_unlock(&tegra->log.mutex);
829                 usleep_range(1000, 2000);
830                 mutex_lock(&tegra->log.mutex);
831         }
832
833         ret = fw_log_available(tegra);
834         mutex_unlock(&tegra->log.mutex);
835
836         return ret;
837 }
838
839 /**
840  * fw_log_copy - copy firmware log from device's buffer to driver's circular
841  *      buffer.
842  * @param tegra tegra_xhci_hcd context
843  * @return true,        We still have firmware log in device's buffer to copy.
844  *                      This function returned due the driver's circular buffer
845  *                      is full. Caller should invoke this function again as
846  *                      soon as there is space in driver's circular buffer.
847  *         false,       Device's buffer is empty.
848  */
849 static inline bool fw_log_copy(struct tegra_xhci_hcd *tegra)
850 {
851         struct device *dev = &tegra->pdev->dev;
852         struct circ_buf *circ = &tegra->log.circ;
853         int head, tail;
854         int buffer_len, copy_len;
855         struct log_entry *entry;
856         struct log_entry *first = tegra->log.virt_addr;
857
858         while (fw_log_available(tegra)) {
859
860                 /* calculate maximum contiguous driver buffer length */
861                 head = circ->head;
862                 tail = ACCESS_ONCE(circ->tail);
863                 buffer_len = CIRC_SPACE_TO_END(head, tail, CIRC_BUF_SIZE);
864                 /* round down to FW_LOG_SIZE */
865                 buffer_len -= (buffer_len % FW_LOG_SIZE);
866                 if (!buffer_len)
867                         return true; /* log available but no space left */
868
869                 /* calculate maximum contiguous log copy length */
870                 entry = tegra->log.dequeue;
871                 copy_len = 0;
872                 do {
873                         if (tegra->log.seq != entry->sequence_no) {
874                                 dev_warn(dev,
875                                 "%s: discontinuous seq no, expect %u get %u\n",
876                                 __func__, tegra->log.seq, entry->sequence_no);
877                         }
878                         tegra->log.seq = entry->sequence_no + 1;
879
880                         copy_len += FW_LOG_SIZE;
881                         buffer_len -= FW_LOG_SIZE;
882                         if (!buffer_len)
883                                 break; /* no space left */
884                         entry = fw_log_next(&tegra->log, entry);
885                 } while ((entry->owner == DRIVER) && (entry != first));
886
887                 memcpy(&circ->buf[head], tegra->log.dequeue, copy_len);
888                 memset(tegra->log.dequeue, 0, copy_len);
889                 circ->head = (circ->head + copy_len) & (CIRC_BUF_SIZE - 1);
890
891                 mb();
892
893                 fw_log_update_deq_pointer(&tegra->log, copy_len/FW_LOG_SIZE);
894
895                 dev_dbg(dev, "copied %d entries, new dequeue 0x%p\n",
896                                 copy_len/FW_LOG_SIZE, tegra->log.dequeue);
897                 wake_up_interruptible(&tegra->log.read_wait);
898         }
899
900         return false;
901 }
902
903 static int fw_log_thread(void *data)
904 {
905         struct tegra_xhci_hcd *tegra = data;
906         struct device *dev = &tegra->pdev->dev;
907         struct circ_buf *circ = &tegra->log.circ;
908         bool logs_left;
909
910         dev_dbg(dev, "start firmware log thread\n");
911
912         do {
913                 mutex_lock(&tegra->log.mutex);
914                 if (circ_buffer_full(circ)) {
915                         mutex_unlock(&tegra->log.mutex);
916                         dev_info(dev, "%s: circ buffer full\n", __func__);
917                         wait_event_interruptible(tegra->log.write_wait,
918                             kthread_should_stop() || !circ_buffer_full(circ));
919                         mutex_lock(&tegra->log.mutex);
920                 }
921
922                 logs_left = fw_log_copy(tegra);
923                 mutex_unlock(&tegra->log.mutex);
924
925                 /* relax if no logs left  */
926                 if (!logs_left)
927                         wait_event_interruptible_timeout(tegra->log.intr_wait,
928                                 fw_log_available(tegra), FW_LOG_THREAD_RELAX);
929         } while (!kthread_should_stop());
930
931         dev_dbg(dev, "stop firmware log thread\n");
932         return 0;
933 }
934
935 static inline bool circ_buffer_empty(struct circ_buf *circ)
936 {
937         return (CIRC_CNT(circ->head, circ->tail, CIRC_BUF_SIZE) == 0);
938 }
939
940 static ssize_t fw_log_file_read(struct file *file, char __user *buf,
941                 size_t count, loff_t *offp)
942 {
943         struct tegra_xhci_hcd *tegra = file->private_data;
944         struct platform_device *pdev = tegra->pdev;
945         struct circ_buf *circ = &tegra->log.circ;
946         int head, tail;
947         size_t n = 0;
948         int s;
949
950         mutex_lock(&tegra->log.mutex);
951
952         while (circ_buffer_empty(circ)) {
953                 mutex_unlock(&tegra->log.mutex);
954                 if (file->f_flags & O_NONBLOCK)
955                         return -EAGAIN; /* non-blocking read */
956
957                 dev_dbg(&pdev->dev, "%s: nothing to read\n", __func__);
958
959                 if (wait_event_interruptible(tegra->log.read_wait,
960                                 !circ_buffer_empty(circ)))
961                         return -ERESTARTSYS;
962
963                 if (mutex_lock_interruptible(&tegra->log.mutex))
964                         return -ERESTARTSYS;
965         }
966
967         while (count > 0) {
968                 head = ACCESS_ONCE(circ->head);
969                 tail = circ->tail;
970                 s = min_t(int, count,
971                                 CIRC_CNT_TO_END(head, tail, CIRC_BUF_SIZE));
972
973                 if (s > 0) {
974                         if (copy_to_user(&buf[n], &circ->buf[tail], s)) {
975                                 dev_warn(&pdev->dev, "copy_to_user failed\n");
976                                 mutex_unlock(&tegra->log.mutex);
977                                 return -EFAULT;
978                         }
979                         circ->tail = (circ->tail + s) & (CIRC_BUF_SIZE - 1);
980
981                         count -= s;
982                         n += s;
983                 } else
984                         break;
985         }
986
987         mutex_unlock(&tegra->log.mutex);
988
989         wake_up_interruptible(&tegra->log.write_wait);
990
991         dev_dbg(&pdev->dev, "%s: %d bytes\n", __func__, n);
992
993         return n;
994 }
995
996 static int fw_log_file_open(struct inode *inode, struct file *file)
997 {
998         struct tegra_xhci_hcd *tegra;
999         file->private_data = inode->i_private;
1000         tegra = file->private_data;
1001
1002         if (test_and_set_bit(FW_LOG_FILE_OPENED, &tegra->log.flags)) {
1003                 dev_info(&tegra->pdev->dev, "%s: already opened\n", __func__);
1004                 return -EBUSY;
1005         }
1006
1007         return 0;
1008 }
1009
1010 static int fw_log_file_close(struct inode *inode, struct file *file)
1011 {
1012         struct tegra_xhci_hcd *tegra = file->private_data;
1013
1014         clear_bit(FW_LOG_FILE_OPENED, &tegra->log.flags);
1015
1016         return 0;
1017 }
1018
1019 static const struct file_operations firmware_log_fops = {
1020                 .open           = fw_log_file_open,
1021                 .release        = fw_log_file_close,
1022                 .read           = fw_log_file_read,
1023                 .owner          = THIS_MODULE,
1024 };
1025
1026 static int fw_log_init(struct tegra_xhci_hcd *tegra)
1027 {
1028         struct platform_device *pdev = tegra->pdev;
1029         int rc = 0;
1030
1031         /* allocate buffer to be shared between driver and firmware */
1032         tegra->log.virt_addr = dma_alloc_writecombine(&pdev->dev,
1033                         FW_LOG_RING_SIZE, &tegra->log.phys_addr, GFP_KERNEL);
1034
1035         if (!tegra->log.virt_addr) {
1036                 dev_err(&pdev->dev, "dma_alloc_writecombine() size %d failed\n",
1037                                 FW_LOG_RING_SIZE);
1038                 return -ENOMEM;
1039         }
1040
1041         dev_info(&pdev->dev, "%d bytes log buffer physical 0x%u virtual 0x%p\n",
1042                 FW_LOG_RING_SIZE, tegra->log.phys_addr, tegra->log.virt_addr);
1043
1044         memset(tegra->log.virt_addr, 0, FW_LOG_RING_SIZE);
1045         tegra->log.dequeue = tegra->log.virt_addr;
1046
1047         tegra->log.circ.buf = vmalloc(CIRC_BUF_SIZE);
1048         if (!tegra->log.circ.buf) {
1049                 dev_err(&pdev->dev, "vmalloc size %d failed\n", CIRC_BUF_SIZE);
1050                 rc = -ENOMEM;
1051                 goto error_free_dma;
1052         }
1053
1054         tegra->log.circ.head = 0;
1055         tegra->log.circ.tail = 0;
1056
1057         init_waitqueue_head(&tegra->log.read_wait);
1058         init_waitqueue_head(&tegra->log.write_wait);
1059         init_waitqueue_head(&tegra->log.intr_wait);
1060
1061         mutex_init(&tegra->log.mutex);
1062
1063         tegra->log.path = debugfs_create_dir("tegra_xhci", NULL);
1064         if (IS_ERR_OR_NULL(tegra->log.path)) {
1065                 dev_warn(&pdev->dev, "debugfs_create_dir() failed\n");
1066                 rc = -ENOMEM;
1067                 goto error_free_mem;
1068         }
1069
1070         tegra->log.log_file = debugfs_create_file("firmware_log",
1071                         S_IRUGO, tegra->log.path, tegra, &firmware_log_fops);
1072         if ((!tegra->log.log_file) ||
1073                         (tegra->log.log_file == ERR_PTR(-ENODEV))) {
1074                 dev_warn(&pdev->dev, "debugfs_create_file() failed\n");
1075                 rc = -ENOMEM;
1076                 goto error_remove_debugfs_path;
1077         }
1078
1079         tegra->log.thread = kthread_run(fw_log_thread, tegra, "xusb-fw-log");
1080         if (IS_ERR(tegra->log.thread)) {
1081                 dev_warn(&pdev->dev, "kthread_run() failed\n");
1082                 rc = -ENOMEM;
1083                 goto error_remove_debugfs_file;
1084         }
1085
1086         set_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags);
1087         return rc;
1088
1089 error_remove_debugfs_file:
1090         debugfs_remove(tegra->log.log_file);
1091 error_remove_debugfs_path:
1092         debugfs_remove(tegra->log.path);
1093 error_free_mem:
1094         vfree(tegra->log.circ.buf);
1095 error_free_dma:
1096         dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1097                         tegra->log.virt_addr, tegra->log.phys_addr);
1098         memset(&tegra->log, sizeof(tegra->log), 0);
1099         return rc;
1100 }
1101
1102 static void fw_log_deinit(struct tegra_xhci_hcd *tegra)
1103 {
1104         struct platform_device *pdev = tegra->pdev;
1105
1106         if (test_and_clear_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
1107
1108                 debugfs_remove(tegra->log.log_file);
1109                 debugfs_remove(tegra->log.path);
1110
1111                 wake_up_interruptible(&tegra->log.read_wait);
1112                 wake_up_interruptible(&tegra->log.write_wait);
1113                 kthread_stop(tegra->log.thread);
1114
1115                 mutex_lock(&tegra->log.mutex);
1116                 dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1117                         tegra->log.virt_addr, tegra->log.phys_addr);
1118                 vfree(tegra->log.circ.buf);
1119                 tegra->log.circ.head = tegra->log.circ.tail = 0;
1120                 mutex_unlock(&tegra->log.mutex);
1121
1122                 mutex_destroy(&tegra->log.mutex);
1123         }
1124 }
1125
1126 /* hsic pad operations */
1127 /*
1128  * HSIC pads need VDDIO_HSIC power rail turned on to be functional. There is
1129  * only one VDDIO_HSIC power rail shared by all HSIC pads.
1130  */
1131 static int hsic_power_rail_enable(struct tegra_xhci_hcd *tegra)
1132 {
1133         struct device *dev = &tegra->pdev->dev;
1134         struct tegra_xusb_regulator_name *supply = &tegra->pdata->bdata->supply;
1135         int ret;
1136
1137         if (tegra->vddio_hsic_reg)
1138                 goto done;
1139
1140         tegra->vddio_hsic_reg = devm_regulator_get(dev, supply->vddio_hsic);
1141         if (IS_ERR_OR_NULL(tegra->vddio_hsic_reg)) {
1142                 dev_err(dev, "%s get vddio_hsic failed\n", __func__);
1143                 ret = PTR_ERR(tegra->vddio_hsic_reg);
1144                 goto get_failed;
1145         }
1146
1147         dev_dbg(dev, "%s regulator_enable vddio_hsic\n", __func__);
1148         ret = regulator_enable(tegra->vddio_hsic_reg);
1149         if (ret < 0) {
1150                 dev_err(dev, "%s enable vddio_hsic failed\n", __func__);
1151                 goto enable_failed;
1152         }
1153
1154 done:
1155         tegra->vddio_hsic_refcnt++;
1156         WARN(tegra->vddio_hsic_refcnt > XUSB_HSIC_COUNT,
1157                         "vddio_hsic_refcnt exceeds\n");
1158         return 0;
1159
1160 enable_failed:
1161         devm_regulator_put(tegra->vddio_hsic_reg);
1162 get_failed:
1163         tegra->vddio_hsic_reg = NULL;
1164         return ret;
1165 }
1166
1167 static int hsic_power_rail_disable(struct tegra_xhci_hcd *tegra)
1168 {
1169         struct device *dev = &tegra->pdev->dev;
1170         int ret;
1171
1172         WARN_ON(!tegra->vddio_hsic_reg || !tegra->vddio_hsic_refcnt);
1173
1174         tegra->vddio_hsic_refcnt--;
1175         if (tegra->vddio_hsic_refcnt)
1176                 return 0;
1177
1178         dev_dbg(dev, "%s regulator_disable vddio_hsic\n", __func__);
1179         ret = regulator_disable(tegra->vddio_hsic_reg);
1180         if (ret < 0) {
1181                 dev_err(dev, "%s disable vddio_hsic failed\n", __func__);
1182                 tegra->vddio_hsic_refcnt++;
1183                 return ret;
1184         }
1185
1186         devm_regulator_put(tegra->vddio_hsic_reg);
1187         tegra->vddio_hsic_reg = NULL;
1188
1189         return 0;
1190 }
1191
1192 static int hsic_pad_enable(struct tegra_xhci_hcd *tegra, unsigned pad)
1193 {
1194         struct device *dev = &tegra->pdev->dev;
1195         void __iomem *base = tegra->padctl_base;
1196         struct tegra_xusb_hsic_config *hsic = &tegra->bdata->hsic[pad];
1197         u32 reg;
1198
1199         if (pad >= XUSB_HSIC_COUNT) {
1200                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1201                 return -EINVAL;
1202         }
1203
1204         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1205
1206         reg = readl(base + HSIC_PAD_CTL_2(pad));
1207         reg &= ~(RX_STROBE_TRIM(~0) | RX_DATA_TRIM(~0));
1208         reg |= RX_STROBE_TRIM(hsic->rx_strobe_trim);
1209         reg |= RX_DATA_TRIM(hsic->rx_data_trim);
1210         writel(reg, base + HSIC_PAD_CTL_2(pad));
1211
1212         reg = readl(base + HSIC_PAD_CTL_0(pad));
1213         reg &= ~(TX_RTUNEP(~0) | TX_RTUNEN(~0) | TX_SLEWP(~0) | TX_SLEWN(~0));
1214         reg |= TX_RTUNEP(hsic->tx_rtune_p);
1215         reg |= TX_RTUNEN(hsic->tx_rtune_n);
1216         reg |= TX_SLEWP(hsic->tx_slew_p);
1217         reg |= TX_SLEWN(hsic->tx_slew_n);
1218         writel(reg, base + HSIC_PAD_CTL_0(pad));
1219
1220         reg = readl(base + HSIC_PAD_CTL_1(pad));
1221         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1222         reg |= (RPD_DATA | RPU_STROBE); /* keep HSIC in IDLE */
1223         if (hsic->auto_term_en)
1224                 reg |= AUTO_TERM_EN;
1225         else
1226                 reg &= ~AUTO_TERM_EN;
1227         reg &= ~(PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1228         writel(reg, base + HSIC_PAD_CTL_1(pad));
1229
1230         reg = readl(base + HSIC_STRB_TRIM_CONTROL);
1231         reg &= ~(STRB_TRIM_VAL(~0));
1232         reg |= STRB_TRIM_VAL(hsic->strb_trim_val);
1233         writel(reg, base + HSIC_STRB_TRIM_CONTROL);
1234
1235         reg = readl(base + USB2_PAD_MUX);
1236         reg |= USB2_HSIC_PAD_PORT(pad);
1237         writel(reg, base + USB2_PAD_MUX);
1238
1239         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1240         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1241         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1242         reg_dump(dev, base, HSIC_STRB_TRIM_CONTROL);
1243         reg_dump(dev, base, USB2_PAD_MUX);
1244         return 0;
1245 }
1246
1247 static void hsic_pad_pretend_connect(struct tegra_xhci_hcd *tegra)
1248 {
1249         struct device *dev = &tegra->pdev->dev;
1250         struct tegra_xusb_hsic_config *hsic;
1251         struct usb_device *hs_root_hub = tegra->xhci->main_hcd->self.root_hub;
1252         int pad;
1253         u32 portsc;
1254         int port;
1255         int enabled_pads = 0;
1256         unsigned long wait_ports = 0;
1257         unsigned long target;
1258
1259         for_each_enabled_hsic_pad(pad, tegra) {
1260                 hsic = &tegra->bdata->hsic[pad];
1261                 if (hsic->pretend_connect)
1262                         enabled_pads++;
1263         }
1264
1265         if (enabled_pads == 0) {
1266                 dev_dbg(dev, "%s no hsic pretend_connect enabled\n", __func__);
1267                 return;
1268         }
1269
1270         usb_disable_autosuspend(hs_root_hub);
1271
1272         for_each_enabled_hsic_pad(pad, tegra) {
1273                 hsic = &tegra->bdata->hsic[pad];
1274                 if (!hsic->pretend_connect)
1275                         continue;
1276
1277                 port = hsic_pad_to_port(pad);
1278                 portsc = xhci_read_portsc(tegra->xhci, port);
1279                 dev_dbg(dev, "%s pad %u portsc 0x%x\n", __func__, pad, portsc);
1280
1281                 if (!(portsc & PORT_CONNECT)) {
1282                         /* firmware wants 1-based port index */
1283                         fw_message_send(tegra,
1284                                 MBOX_CMD_HSIC_PRETEND_CONNECT, BIT(port + 1));
1285                 }
1286
1287                 set_bit(port, &wait_ports);
1288         }
1289
1290         /* wait till port reaches U0 */
1291         target = jiffies + msecs_to_jiffies(500);
1292         do {
1293                 for_each_set_bit(port, &wait_ports, BITS_PER_LONG) {
1294                         portsc = xhci_read_portsc(tegra->xhci, port);
1295                         pad = port_to_hsic_pad(port);
1296                         dev_dbg(dev, "%s pad %u portsc 0x%x\n", __func__,
1297                                 pad, portsc);
1298                         if ((PORT_PLS_MASK & portsc) == XDEV_U0)
1299                                 clear_bit(port, &wait_ports);
1300                 }
1301
1302                 if (wait_ports)
1303                         usleep_range(1000, 5000);
1304         } while (wait_ports && time_is_after_jiffies(target));
1305
1306         if (wait_ports)
1307                 dev_warn(dev, "%s HSIC pad(s) didn't reach U0.\n", __func__);
1308
1309         usb_enable_autosuspend(hs_root_hub);
1310
1311         return;
1312 }
1313
1314 static int hsic_pad_disable(struct tegra_xhci_hcd *tegra, unsigned pad)
1315 {
1316         struct device *dev = &tegra->pdev->dev;
1317         void __iomem *base = tegra->padctl_base;
1318         u32 reg;
1319
1320         if (pad >= XUSB_HSIC_COUNT) {
1321                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1322                 return -EINVAL;
1323         }
1324
1325         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1326
1327         reg = readl(base + USB2_PAD_MUX);
1328         reg &= ~USB2_HSIC_PAD_PORT(pad);
1329         writel(reg, base + USB2_PAD_MUX);
1330
1331         reg = readl(base + HSIC_PAD_CTL_1(pad));
1332         reg |= (PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1333         writel(reg, base + HSIC_PAD_CTL_1(pad));
1334
1335         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1336         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1337         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1338         reg_dump(dev, base, USB2_PAD_MUX);
1339         return 0;
1340 }
1341
1342 enum hsic_pad_pupd {
1343         PUPD_DISABLE = 0,
1344         PUPD_IDLE,
1345         PUPD_RESET
1346 };
1347
1348 static int hsic_pad_pupd_set(struct tegra_xhci_hcd *tegra, unsigned pad,
1349         enum hsic_pad_pupd pupd)
1350 {
1351         struct device *dev = &tegra->pdev->dev;
1352         void __iomem *base = tegra->padctl_base;
1353         u32 reg;
1354
1355         if (pad >= XUSB_HSIC_COUNT) {
1356                 dev_err(dev, "%s invalid HSIC pad number %u\n", __func__, pad);
1357                 return -EINVAL;
1358         }
1359
1360         dev_dbg(dev, "%s pad %u pupd %d\n", __func__, pad, pupd);
1361
1362         reg = readl(base + HSIC_PAD_CTL_1(pad));
1363         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1364
1365         if (pupd == PUPD_IDLE)
1366                 reg |= (RPD_DATA | RPU_STROBE);
1367         else if (pupd == PUPD_RESET)
1368                 reg |= (RPD_DATA | RPD_STROBE);
1369         else if (pupd != PUPD_DISABLE) {
1370                 dev_err(dev, "%s invalid pupd %d\n", __func__, pupd);
1371                 return -EINVAL;
1372         }
1373
1374         writel(reg, base + HSIC_PAD_CTL_1(pad));
1375
1376         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1377
1378         return 0;
1379 }
1380
1381
1382 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
1383 {
1384         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1385         struct xhci_hcd *xhci = tegra->xhci;
1386         u32 reg;
1387
1388         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
1389         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1390         xhci_info(xhci, " PAD MUX = %x\n", reg);
1391         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1392         xhci_info(xhci, " PORT CAP = %x\n", reg);
1393         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1394         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
1395         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1396         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
1397         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1398         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
1399         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1400         xhci_info(xhci, " OC DET 0= %x\n", reg);
1401         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad0_ctl2_0);
1402         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
1403         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad1_ctl2_0);
1404         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
1405         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl0_0);
1406         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
1407         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl0_0);
1408         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
1409         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl1_0);
1410         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
1411         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl1_0);
1412         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
1413         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1414         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
1415         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad0_ctl0_0);
1416         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
1417         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad1_ctl0_0);
1418         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
1419         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
1420 }
1421
1422 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
1423 {
1424         u32 reg;
1425
1426         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1427         reg |= IPFS_EN_FPCI;
1428         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1429         udelay(10);
1430
1431         /* Program Bar0 Space */
1432         reg = readl(tegra->fpci_base + XUSB_CFG_4);
1433         reg |= tegra->host_phy_base;
1434         writel(reg, tegra->fpci_base + XUSB_CFG_4);
1435         usleep_range(100, 200);
1436
1437         /* Enable Bus Master */
1438         reg = readl(tegra->fpci_base + XUSB_CFG_1);
1439         reg |= 0x7;
1440         writel(reg, tegra->fpci_base + XUSB_CFG_1);
1441
1442         /* Set intr mask to enable intr assertion */
1443         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1444         reg |= IPFS_IP_INT_MASK;
1445         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1446
1447         /* Set hysteris to 0x80 */
1448         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1449 }
1450
1451 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
1452                 struct platform_device *pdev)
1453 {
1454         struct tegra_xusb_regulator_name *supply = &tegra->bdata->supply;
1455         int err = 0;
1456
1457         tegra->xusb_s3p3v_reg =
1458                         devm_regulator_get(&pdev->dev, supply->s3p3v);
1459         if (IS_ERR(tegra->xusb_s3p3v_reg)) {
1460                 dev_err(&pdev->dev, "3p3v: regulator not found: %ld."
1461                         , PTR_ERR(tegra->xusb_s3p3v_reg));
1462                 err = PTR_ERR(tegra->xusb_s3p3v_reg);
1463                 goto err_null_regulator;
1464         } else {
1465                 err = regulator_enable(tegra->xusb_s3p3v_reg);
1466                 if (err < 0) {
1467                         dev_err(&pdev->dev,
1468                                 "3p3v: regulator enable failed:%d\n", err);
1469                         goto err_null_regulator;
1470                 }
1471         }
1472
1473         if ((tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) &&
1474                                          !tegra->transceiver) {
1475                 tegra->xusb_s5p0v_reg = devm_regulator_get(&pdev->dev,
1476                                                 supply->s5p0v);
1477                 if (IS_ERR(tegra->xusb_s5p0v_reg)) {
1478                         dev_err(&pdev->dev, "5p0v regulator not found: %ld."
1479                                 , PTR_ERR(tegra->xusb_s5p0v_reg));
1480                         err = PTR_ERR(tegra->xusb_s5p0v_reg);
1481                         goto err_put_s3p3v_reg;
1482                 } else {
1483                         err = regulator_enable(tegra->xusb_s5p0v_reg);
1484                         if (err < 0) {
1485                                 dev_err(&pdev->dev,
1486                                         "5p0v: regulator enable failed:%d\n",
1487                                         err);
1488                                 goto err_put_s3p3v_reg;
1489                         }
1490                 }
1491         }
1492
1493         tegra->xusb_s1p8v_reg =
1494                 devm_regulator_get(&pdev->dev, supply->s1p8v);
1495         if (IS_ERR(tegra->xusb_s1p8v_reg)) {
1496                 dev_err(&pdev->dev, "1p8v regulator not found: %ld."
1497                         , PTR_ERR(tegra->xusb_s1p8v_reg));
1498                 err = PTR_ERR(tegra->xusb_s1p8v_reg);
1499                 goto err_put_s5p0v_reg;
1500         } else {
1501                 err = regulator_enable(tegra->xusb_s1p8v_reg);
1502                 if (err < 0) {
1503                         dev_err(&pdev->dev,
1504                         "1p8v: regulator enable failed:%d\n", err);
1505                         goto err_put_s5p0v_reg;
1506                 }
1507         }
1508
1509         tegra->xusb_s1p05v_reg =
1510                         devm_regulator_get(&pdev->dev, supply->s1p05v);
1511         if (IS_ERR(tegra->xusb_s1p05v_reg)) {
1512                 dev_err(&pdev->dev, "1p05v: regulator not found: %ld."
1513                         , PTR_ERR(tegra->xusb_s1p05v_reg));
1514                 err = PTR_ERR(tegra->xusb_s1p05v_reg);
1515                 goto err_put_s1p8v_reg;
1516         } else {
1517                 err = regulator_enable(tegra->xusb_s1p05v_reg);
1518                 if (err < 0) {
1519                         dev_err(&pdev->dev,
1520                         "1p05v: regulator enable failed:%d\n", err);
1521                         goto err_put_s1p8v_reg;
1522                 }
1523         }
1524
1525         if (tegra->bdata->uses_different_vbus_per_port) {
1526                 tegra->xusb_s5p0v1_reg = devm_regulator_get(&pdev->dev,
1527                                                 supply->s5p0v1);
1528                 if (IS_ERR(tegra->xusb_s5p0v1_reg)) {
1529                         dev_err(&pdev->dev, "5p0v1 regulator not found: %ld."
1530                                 , PTR_ERR(tegra->xusb_s5p0v1_reg));
1531                         err = PTR_ERR(tegra->xusb_s5p0v1_reg);
1532                         goto err_put_s1p05v_reg;
1533                 } else {
1534                         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1535                                 err = regulator_enable(tegra->xusb_s5p0v1_reg);
1536                         if (err < 0) {
1537                                 dev_err(&pdev->dev,
1538                                 "5p0v1: regulator enable failed:%d\n", err);
1539                                 goto err_put_s1p05v_reg;
1540                         }
1541                 }
1542
1543                 tegra->xusb_s5p0v2_reg = devm_regulator_get(&pdev->dev,
1544                                                 supply->s5p0v2);
1545                 if (IS_ERR(tegra->xusb_s5p0v2_reg)) {
1546                         dev_err(&pdev->dev, "5p0v2 regulator not found: %ld."
1547                                 , PTR_ERR(tegra->xusb_s5p0v2_reg));
1548                         err = PTR_ERR(tegra->xusb_s5p0v2_reg);
1549                         goto err_put_s1p5v1_reg;
1550                 } else {
1551                         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1552                                 err = regulator_enable(tegra->xusb_s5p0v2_reg);
1553                         if (err < 0) {
1554                                 dev_err(&pdev->dev,
1555                                 "5p0v2: regulator enable failed:%d\n", err);
1556                                 goto err_put_s1p5v1_reg;
1557                         }
1558                 }
1559         }
1560         return err;
1561
1562 err_put_s1p5v1_reg:
1563         if (tegra->bdata->uses_different_vbus_per_port &&
1564                 tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1565                 regulator_disable(tegra->xusb_s5p0v1_reg);
1566 err_put_s1p05v_reg:
1567         regulator_disable(tegra->xusb_s1p05v_reg);
1568 err_put_s1p8v_reg:
1569         regulator_disable(tegra->xusb_s1p8v_reg);
1570 err_put_s5p0v_reg:
1571         if ((tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) && !tegra->transceiver)
1572                 regulator_disable(tegra->xusb_s5p0v_reg);
1573 err_put_s3p3v_reg:
1574         regulator_disable(tegra->xusb_s3p3v_reg);
1575 err_null_regulator:
1576         tegra->xusb_s5p0v_reg = NULL;
1577         tegra->xusb_s5p0v1_reg = NULL;
1578         tegra->xusb_s5p0v2_reg = NULL;
1579         tegra->xusb_s1p05v_reg = NULL;
1580         tegra->xusb_s3p3v_reg = NULL;
1581         tegra->xusb_s1p8v_reg = NULL;
1582         return err;
1583 }
1584
1585 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
1586 {
1587         regulator_disable(tegra->xusb_s1p05v_reg);
1588         regulator_disable(tegra->xusb_s1p8v_reg);
1589         if ((tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) && !tegra->transceiver)
1590                 regulator_disable(tegra->xusb_s5p0v_reg);
1591         regulator_disable(tegra->xusb_s3p3v_reg);
1592         if (tegra->bdata->uses_different_vbus_per_port) {
1593                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1594                         regulator_disable(tegra->xusb_s5p0v1_reg);
1595                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1596                         regulator_disable(tegra->xusb_s5p0v2_reg);
1597         }
1598
1599         tegra->xusb_s1p05v_reg = NULL;
1600         tegra->xusb_s1p8v_reg = NULL;
1601         tegra->xusb_s5p0v_reg = NULL;
1602         tegra->xusb_s5p0v1_reg = NULL;
1603         tegra->xusb_s5p0v2_reg = NULL;
1604         tegra->xusb_s3p3v_reg = NULL;
1605 }
1606
1607 /*
1608  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
1609  * are under hardware control
1610  */
1611 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
1612 {
1613         struct platform_device *pdev = tegra->pdev;
1614         int err = 0;
1615
1616         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
1617         if (IS_ERR(tegra->plle_clk)) {
1618                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
1619                 err = PTR_ERR(tegra->plle_clk);
1620                 return err;
1621         }
1622         err = clk_enable(tegra->plle_clk);
1623         if (err) {
1624                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
1625                         __func__);
1626                 return err;
1627         }
1628
1629         return err;
1630 }
1631
1632 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
1633 {
1634         clk_disable(tegra->plle_clk);
1635         tegra->plle_clk = NULL;
1636 }
1637
1638 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
1639 {
1640         struct platform_device *pdev = tegra->pdev;
1641         int err = 0;
1642
1643         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
1644         if (IS_ERR(tegra->emc_clk)) {
1645                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
1646                 return PTR_ERR(tegra->emc_clk);
1647         }
1648
1649         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1650                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
1651                 if (IS_ERR(tegra->pll_re_vco_clk)) {
1652                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
1653                         err = PTR_ERR(tegra->pll_re_vco_clk);
1654                         goto get_pll_re_vco_clk_failed;
1655                 }
1656         }
1657
1658         /* get the clock handle of 120MHz clock source */
1659         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
1660         if (IS_ERR(tegra->pll_u_480M)) {
1661                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
1662                 err = PTR_ERR(tegra->pll_u_480M);
1663                 goto get_pll_u_480M_failed;
1664         }
1665
1666         /* get the clock handle of 12MHz clock source */
1667         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1668         if (IS_ERR(tegra->clk_m)) {
1669                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
1670                 err = PTR_ERR(tegra->clk_m);
1671                 goto clk_get_clk_m_failed;
1672         }
1673
1674         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
1675         if (IS_ERR(tegra->ss_src_clk)) {
1676                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
1677                 err = PTR_ERR(tegra->ss_src_clk);
1678                 tegra->ss_src_clk = NULL;
1679                 goto get_ss_src_clk_failed;
1680         }
1681
1682         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
1683         if (IS_ERR(tegra->host_clk)) {
1684                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
1685                 err = PTR_ERR(tegra->host_clk);
1686                 tegra->host_clk = NULL;
1687                 goto get_host_clk_failed;
1688         }
1689
1690         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
1691         if (IS_ERR(tegra->ss_clk)) {
1692                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
1693                 err = PTR_ERR(tegra->ss_clk);
1694                 tegra->ss_clk = NULL;
1695                 goto get_ss_clk_failed;
1696         }
1697
1698         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1699                 err = clk_enable(tegra->pll_re_vco_clk);
1700                 if (err) {
1701                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
1702                         goto enable_pll_re_vco_clk_failed;
1703                 }
1704         }
1705         return 0;
1706
1707 enable_pll_re_vco_clk_failed:
1708         tegra->ss_clk = NULL;
1709
1710 get_ss_clk_failed:
1711         tegra->host_clk = NULL;
1712
1713 get_host_clk_failed:
1714         tegra->ss_src_clk = NULL;
1715
1716 get_ss_src_clk_failed:
1717         tegra->clk_m = NULL;
1718
1719 clk_get_clk_m_failed:
1720         tegra->pll_u_480M = NULL;
1721
1722 get_pll_u_480M_failed:
1723         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1724                 tegra->pll_re_vco_clk = NULL;
1725
1726 get_pll_re_vco_clk_failed:
1727         tegra->emc_clk = NULL;
1728
1729         return err;
1730 }
1731
1732 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
1733 {
1734         clk_disable(tegra->ss_clk);
1735         clk_disable(tegra->host_clk);
1736         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1737                 clk_disable(tegra->pll_re_vco_clk);
1738         tegra->ss_clk = NULL;
1739         tegra->host_clk = NULL;
1740         tegra->ss_src_clk = NULL;
1741         tegra->clk_m = NULL;
1742         tegra->pll_u_480M = NULL;
1743         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1744                 tegra->pll_re_vco_clk = NULL;
1745 }
1746
1747 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
1748         bool enable)
1749 {
1750         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1751         u32 reg;
1752
1753         /* Issue is only applicable for T114 */
1754         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
1755                 return;
1756
1757         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1758                 reg = readl(tegra->padctl_base +
1759                         padregs->iophy_misc_pad_p0_ctl3_0);
1760                 if (enable) {
1761                         reg &= ~RX_IDLE_MODE;
1762                         reg |= RX_IDLE_MODE_OVRD;
1763                 } else {
1764                         reg |= RX_IDLE_MODE;
1765                         reg &= ~RX_IDLE_MODE_OVRD;
1766                 }
1767                 writel(reg, tegra->padctl_base +
1768                         padregs->iophy_misc_pad_p0_ctl3_0);
1769         }
1770
1771         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1772                 reg = readl(tegra->padctl_base +
1773                         padregs->iophy_misc_pad_p1_ctl3_0);
1774                 if (enable) {
1775                         reg &= ~RX_IDLE_MODE;
1776                         reg |= RX_IDLE_MODE_OVRD;
1777                 } else {
1778                         reg |= RX_IDLE_MODE;
1779                         reg &= ~RX_IDLE_MODE_OVRD;
1780                 }
1781                 writel(reg, tegra->padctl_base +
1782                         padregs->iophy_misc_pad_p1_ctl3_0);
1783
1784                 /* SATA lane also if USB3_SS port1 mapped to it */
1785                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
1786                                 tegra->bdata->lane_owner & BIT(0)) {
1787                         reg = readl(tegra->padctl_base +
1788                                 padregs->iophy_misc_pad_s0_ctl3_0);
1789                         if (enable) {
1790                                 reg &= ~RX_IDLE_MODE;
1791                                 reg |= RX_IDLE_MODE_OVRD;
1792                         } else {
1793                                 reg |= RX_IDLE_MODE;
1794                                 reg &= ~RX_IDLE_MODE_OVRD;
1795                         }
1796                         writel(reg, tegra->padctl_base +
1797                                 padregs->iophy_misc_pad_s0_ctl3_0);
1798                 }
1799         }
1800 }
1801
1802 /* Enable ss clk, host clk, falcon clk,
1803  * fs clk, dev clk, plle and refplle
1804  */
1805
1806 static int
1807 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
1808                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
1809 {
1810         int ret = 0;
1811         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
1812         int fw_req_rate = rate, cur_rate;
1813
1814         /* Do not handle clock change as needed for HS disconnect issue */
1815         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1816                 *sw_resp = CMD_DATA(fw_req_rate) | CMD_TYPE(MBOX_CMD_ACK);
1817                 return ret;
1818         }
1819
1820         /* frequency request from firmware is in KHz.
1821          * Convert it to MHz
1822          */
1823
1824         /* get current rate of clock */
1825         cur_rate = clk_get_rate(clk_handle);
1826         cur_rate /= 1000;
1827
1828         if (fw_req_rate == cur_rate) {
1829                 cmd_ack = MBOX_CMD_ACK;
1830
1831         } else {
1832
1833                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
1834                         /* Change SS clock source to CLK_M at 12MHz */
1835                         clk_set_parent(clk_handle, tegra->clk_m);
1836                         clk_set_rate(clk_handle, fw_req_rate * 1000);
1837
1838                         /* save leakage power when SS freq is being decreased */
1839                         tegra_xhci_rx_idle_mode_override(tegra, true);
1840                 } else if (clk_handle == tegra->ss_src_clk &&
1841                                 fw_req_rate == 120000) {
1842                         /* Change SS clock source to HSIC_480 at 120MHz */
1843                         clk_set_rate(clk_handle,  3000 * 1000);
1844                         clk_set_parent(clk_handle, tegra->pll_u_480M);
1845
1846                         /* clear ovrd bits when SS freq is being increased */
1847                         tegra_xhci_rx_idle_mode_override(tegra, false);
1848                 }
1849
1850                 cur_rate = (clk_get_rate(clk_handle) / 1000);
1851
1852                 if (cur_rate != fw_req_rate) {
1853                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
1854                                 cur_rate, fw_req_rate);
1855                         cmd_ack = MBOX_CMD_NACK;
1856                 }
1857         }
1858         *sw_resp = CMD_DATA(cur_rate) | CMD_TYPE(cmd_ack);
1859         return ret;
1860 }
1861
1862 static void tegra_xhci_save_dfe_context(struct tegra_xhci_hcd *tegra,
1863         u8 port)
1864 {
1865         struct xhci_hcd *xhci = tegra->xhci;
1866         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1867         u32 offset;
1868         u32 reg;
1869
1870         if (port > (XUSB_SS_PORT_COUNT - 1)) {
1871                 pr_err("%s invalid SS port number %u\n", __func__, port);
1872                 return;
1873         }
1874
1875         xhci_info(xhci, "saving restore DFE context for port %d\n", port);
1876
1877         /* if port1 is mapped to SATA lane then read from SATA register */
1878         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1879                         tegra->bdata->lane_owner & BIT(0))
1880                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1881         else
1882                 offset = MISC_PAD_CTL_6_0(port);
1883
1884         /*
1885          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
1886          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
1887          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
1888          */
1889         reg = readl(tegra->padctl_base + offset);
1890         reg &= ~MISC_OUT_SEL(~0);
1891         reg |= MISC_OUT_SEL(0x32);
1892         writel(reg, tegra->padctl_base + offset);
1893
1894         reg = readl(tegra->padctl_base + offset);
1895         tegra->sregs.tap1_val[port] = MISC_OUT_TAP_VAL(reg);
1896
1897         reg = readl(tegra->padctl_base + offset);
1898         reg &= ~MISC_OUT_SEL(~0);
1899         reg |= MISC_OUT_SEL(0x33);
1900         writel(reg, tegra->padctl_base + offset);
1901
1902         reg = readl(tegra->padctl_base + offset);
1903         tegra->sregs.amp_val[port] = MISC_OUT_AMP_VAL(reg);
1904
1905         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1906         reg &= ~DFE_CNTL_TAP_VAL(~0);
1907         reg |= DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
1908         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1909
1910         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1911         reg &= ~DFE_CNTL_AMP_VAL(~0);
1912         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]);
1913         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1914
1915         tegra->dfe_ctx_saved[port] = true;
1916 }
1917
1918 static void save_ctle_context(struct tegra_xhci_hcd *tegra,
1919         u8 port)
1920 {
1921         struct xhci_hcd *xhci = tegra->xhci;
1922         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1923         u32 offset;
1924         u32 reg;
1925
1926         if (port > (XUSB_SS_PORT_COUNT - 1)) {
1927                 pr_err("%s invalid SS port number %u\n", __func__, port);
1928                 return;
1929         }
1930
1931         xhci_info(xhci, "saving restore CTLE context for port %d\n", port);
1932
1933         /* if port1 is mapped to SATA lane then read from SATA register */
1934         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1935                         tegra->bdata->lane_owner & BIT(0))
1936                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1937         else
1938                 offset = MISC_PAD_CTL_6_0(port);
1939
1940         /*
1941          * Value set to IOPHY_MISC_PAD_x_CTL_6 where x P0/P1/S0/ is from,
1942          * T114 refer PG USB3_FW_Programming_Guide_Host.doc section 14.3.10
1943          * T124 refer PG T124_USB3_FW_Programming_Guide_Host.doc section 14.3.10
1944          */
1945         reg = readl(tegra->padctl_base + offset);
1946         reg &= ~MISC_OUT_SEL(~0);
1947         reg |= MISC_OUT_SEL(0xa1);
1948         writel(reg, tegra->padctl_base + offset);
1949
1950         reg = readl(tegra->padctl_base + offset);
1951         reg &= ~MISC_OUT_SEL(~0);
1952         reg |= MISC_OUT_SEL(0x21);
1953         writel(reg, tegra->padctl_base + offset);
1954
1955         reg = readl(tegra->padctl_base + offset);
1956         tegra->sregs.ctle_g_val[port] = MISC_OUT_G_Z_VAL(reg);
1957
1958         reg = readl(tegra->padctl_base + offset);
1959         reg &= ~MISC_OUT_SEL(~0);
1960         reg |= MISC_OUT_SEL(0x48);
1961         writel(reg, tegra->padctl_base + offset);
1962
1963         reg = readl(tegra->padctl_base + offset);
1964         tegra->sregs.ctle_z_val[port] = MISC_OUT_G_Z_VAL(reg);
1965
1966         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1967         reg &= ~RX_EQ_Z_VAL(~0);
1968         reg |= RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]);
1969         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1970
1971         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1972         reg &= ~RX_EQ_G_VAL(~0);
1973         reg |= RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]);
1974         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
1975
1976         tegra->ctle_ctx_saved[port] = true;
1977 }
1978
1979 static void tegra_xhci_restore_dfe_context(struct tegra_xhci_hcd *tegra,
1980         u8 port)
1981 {
1982         struct xhci_hcd *xhci = tegra->xhci;
1983         u32 reg;
1984
1985         /* don't restore if not saved */
1986         if (tegra->dfe_ctx_saved[port] == false)
1987                 return;
1988
1989         xhci_info(xhci, "restoring dfe context of port %d\n", port);
1990
1991         /* restore dfe_cntl for the port */
1992         reg = readl(tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1993         reg &= ~(DFE_CNTL_AMP_VAL(~0) |
1994                         DFE_CNTL_TAP_VAL(~0));
1995         reg |= DFE_CNTL_AMP_VAL(tegra->sregs.amp_val[port]) |
1996                 DFE_CNTL_TAP_VAL(tegra->sregs.tap1_val[port]);
1997         writel(reg, tegra->padctl_base + USB3_PAD_CTL_4_0(port));
1998 }
1999
2000 void restore_ctle_context(struct tegra_xhci_hcd *tegra,
2001         u8 port)
2002 {
2003         struct xhci_hcd *xhci = tegra->xhci;
2004         u32 reg;
2005
2006         /* don't restore if not saved */
2007         if (tegra->ctle_ctx_saved[port] == false)
2008                 return;
2009
2010         xhci_info(xhci, "restoring CTLE context of port %d\n", port);
2011
2012         /* restore ctle for the port */
2013         reg = readl(tegra->padctl_base + USB3_PAD_CTL_2_0(port));
2014         reg &= ~(RX_EQ_Z_VAL(~0) |
2015                         RX_EQ_G_VAL(~0));
2016         reg |= (RX_EQ_Z_VAL(tegra->sregs.ctle_z_val[port]) |
2017                 RX_EQ_G_VAL(tegra->sregs.ctle_g_val[port]));
2018         writel(reg, tegra->padctl_base + USB3_PAD_CTL_2_0(port));
2019 }
2020
2021 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
2022         u8 port)
2023 {
2024         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2025         u32 reg;
2026
2027         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2028         reg &= ~USB2_ULPI_PAD;
2029         reg |= USB2_ULPI_PAD_OWNER_XUSB;
2030         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2031
2032         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
2033         reg &= ~USB2_ULPI_PORT_CAP;
2034         reg |= (tegra->bdata->ulpicap << 24);
2035         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
2036         /* FIXME: Program below when more details available
2037          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
2038          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
2039          */
2040 }
2041
2042 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
2043         u8 port)
2044 {
2045         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2046         u32 reg;
2047         u32 ctl0_offset, ctl1_offset;
2048
2049         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2050         reg &= ~USB2_OTG_PAD_PORT_MASK(port);
2051         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
2052         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2053
2054         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
2055         reg &= ~USB2_PORT_CAP_MASK(port);
2056         reg |= USB2_PORT_CAP_HOST(port);
2057         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
2058
2059         /*
2060          * Modify only the bits which belongs to the port
2061          * and enable respective VBUS_PAD for the port
2062          */
2063         if (tegra->bdata->uses_external_pmic == false) {
2064                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2065                 reg &= ~(port == 2 ? OC_DET_VBUS_ENABLE2_OC_MAP :
2066                         port ? OC_DET_VBUS_ENABLE1_OC_MAP :
2067                                 OC_DET_VBUS_ENABLE0_OC_MAP);
2068
2069                 reg |= (port == 2) ? OC_DET_VBUS_EN2_OC_DETECTED_VBUS_PAD2 :
2070                         port ? OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1 :
2071                                 OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0;
2072                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
2073         }
2074         /*
2075          * enable respective VBUS_PAD if port is mapped to any SS port
2076          */
2077         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
2078         reg &= ~((port == 2) ? USB2_OC_MAP_PORT2 :
2079                 port ? USB2_OC_MAP_PORT1 : USB2_OC_MAP_PORT0);
2080         reg |= (0x4 | port) << (port * 3);
2081         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
2082
2083         ctl0_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl0_0 :
2084                         port ? padregs->usb2_otg_pad1_ctl0_0 :
2085                                 padregs->usb2_otg_pad0_ctl0_0;
2086         ctl1_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl1_0 :
2087                         port ? padregs->usb2_otg_pad1_ctl1_0 :
2088                                 padregs->usb2_otg_pad0_ctl1_0;
2089
2090         reg = readl(tegra->padctl_base + ctl0_offset);
2091         reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
2092                 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
2093                 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
2094
2095         reg |= tegra->pdata->hs_slew;
2096         reg |= (port == 2) ? tegra->pdata->ls_rslew_pad2 :
2097                         port ? tegra->pdata->ls_rslew_pad1 :
2098                         tegra->pdata->ls_rslew_pad0;
2099         reg |= (port == 2) ? tegra->pdata->hs_curr_level_pad2 :
2100                         port ? tegra->pdata->hs_curr_level_pad1 :
2101                         tegra->pdata->hs_curr_level_pad0;
2102         writel(reg, tegra->padctl_base + ctl0_offset);
2103
2104         reg = readl(tegra->padctl_base + ctl1_offset);
2105         reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
2106                 | USB2_OTG_PD_CHRP_FORCE_POWERUP
2107                 | USB2_OTG_PD_DISC_FORCE_POWERUP
2108                 | USB2_OTG_PD_DR);
2109         reg |= (tegra->pdata->hs_iref_cap << 9) |
2110                 (tegra->pdata->hs_term_range_adj << 3);
2111         writel(reg, tegra->padctl_base + ctl1_offset);
2112
2113         /*Release OTG port if not in host mode*/
2114
2115         if ((port == 0) && !is_otg_host(tegra))
2116                 tegra_xhci_release_otg_port(true);
2117 }
2118
2119 static inline bool xusb_use_sata_lane(struct tegra_xhci_hcd *tegra)
2120 {
2121         return ((XUSB_DEVICE_ID_T114 == tegra->device_id) ? false
2122         : ((tegra->bdata->portmap & TEGRA_XUSB_SS_P1)
2123                 && (tegra->bdata->lane_owner & BIT(0))));
2124 }
2125
2126 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
2127         u8 port)
2128 {
2129         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2130         u32 ctl2_offset, ctl4_offset, ctl5_offset;
2131         u32 reg;
2132
2133         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
2134                         padregs->iophy_usb3_pad0_ctl2_0;
2135         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
2136                         padregs->iophy_usb3_pad0_ctl4_0;
2137         ctl5_offset = port ? padregs->iophy_misc_pad_p1_ctl5_0 :
2138                         padregs->iophy_misc_pad_p0_ctl5_0;
2139
2140         reg = readl(tegra->padctl_base + ctl2_offset);
2141         reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
2142                 IOPHY_USB3_CDRCNTL);
2143         reg |= tegra->pdata->rx_wander | tegra->pdata->rx_eq |
2144                 tegra->pdata->cdr_cntl;
2145         writel(reg, tegra->padctl_base + ctl2_offset);
2146
2147         reg = readl(tegra->padctl_base + ctl4_offset);
2148         reg = tegra->pdata->dfe_cntl;
2149         writel(reg, tegra->padctl_base + ctl4_offset);
2150
2151         reg = readl(tegra->padctl_base + ctl5_offset);
2152         reg |= RX_QEYE_EN;
2153         writel(reg, tegra->padctl_base + ctl5_offset);
2154
2155         reg = readl(tegra->padctl_base + MISC_PAD_CTL_2_0(port));
2156         reg &= ~SPARE_IN(~0);
2157         reg |= SPARE_IN(tegra->pdata->spare_in);
2158         writel(reg, tegra->padctl_base + MISC_PAD_CTL_2_0(port));
2159
2160         if (xusb_use_sata_lane(tegra)) {
2161                 reg = readl(tegra->padctl_base + MISC_PAD_S0_CTL_5_0);
2162                 reg |= RX_QEYE_EN;
2163                 writel(reg, tegra->padctl_base + MISC_PAD_S0_CTL_5_0);
2164
2165                 reg = readl(tegra->padctl_base + MISC_PAD_S0_CTL_2_0);
2166                 reg &= ~SPARE_IN(~0);
2167                 reg |= SPARE_IN(tegra->pdata->spare_in);
2168                 writel(reg, tegra->padctl_base + MISC_PAD_S0_CTL_2_0);
2169         }
2170
2171         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
2172         reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
2173         reg |= (tegra->bdata->ss_portmap &
2174                 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
2175         writel(reg, tegra->padctl_base + padregs->ss_port_map_0);
2176
2177         tegra_xhci_restore_dfe_context(tegra, port);
2178         tegra_xhci_restore_ctle_context(tegra, port);
2179 }
2180
2181 /* This function assigns the USB ports to the controllers,
2182  * then programs the port capabilities and pad parameters
2183  * of ports assigned to XUSB after booted to OS.
2184  */
2185 void
2186 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
2187 {
2188         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2189         u32 reg, oc_bits = 0;
2190         unsigned pad;
2191
2192         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2193         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
2194         reg |= tegra->pdata->hs_squelch_level | tegra->pdata->hs_disc_lvl;
2195         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2196
2197         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
2198         reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3;
2199         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
2200         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
2201
2202         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2203         reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
2204         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2205                 reg |= OC_DET_VBUS_ENABLE2_OC_MAP;
2206         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2207
2208         /* check if over current seen. Clear if present */
2209         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2210                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2211         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2212                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2213         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2214                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2215
2216         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2217         if (reg & oc_bits) {
2218                 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
2219                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
2220
2221                 usleep_range(100, 200);
2222
2223                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2224                 if (reg & oc_bits)
2225                         xhci_info(tegra->xhci, "Over current still present\n");
2226         }
2227
2228         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
2229         reg = USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1;
2230         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2231                 reg |= USB2_OC_MAP_PORT2;
2232         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
2233
2234         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2235                 tegra_xhci_program_utmip_pad(tegra, 0);
2236         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2237                 tegra_xhci_program_utmip_pad(tegra, 1);
2238         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2239                 tegra_xhci_program_utmip_pad(tegra, 2);
2240
2241         for_each_enabled_hsic_pad(pad, tegra)
2242                 hsic_pad_enable(tegra, pad);
2243
2244         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
2245                 tegra_xhci_program_ulpi_pad(tegra, 0);
2246
2247         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
2248                 tegra_xhci_program_ss_pad(tegra, 0);
2249         } else {
2250                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
2251                 reg = readl(tegra->padctl_base +
2252                         padregs->iophy_misc_pad_p0_ctl3_0);
2253                 reg &= ~RX_IDLE_MODE;
2254                 reg |= RX_IDLE_MODE_OVRD;
2255                 writel(reg, tegra->padctl_base +
2256                         padregs->iophy_misc_pad_p0_ctl3_0);
2257         }
2258
2259         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
2260                 tegra_xhci_program_ss_pad(tegra, 1);
2261         } else {
2262                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
2263                 reg = readl(tegra->padctl_base +
2264                         padregs->iophy_misc_pad_p1_ctl3_0);
2265                 reg &= ~RX_IDLE_MODE;
2266                 reg |= RX_IDLE_MODE_OVRD;
2267                 writel(reg, tegra->padctl_base +
2268                         padregs->iophy_misc_pad_p1_ctl3_0);
2269
2270                 /* SATA lane also if USB3_SS port1 mapped to it but unused */
2271                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
2272                                 tegra->bdata->lane_owner & BIT(0)) {
2273                         reg = readl(tegra->padctl_base +
2274                                 padregs->iophy_misc_pad_s0_ctl3_0);
2275                         reg &= ~RX_IDLE_MODE;
2276                         reg |= RX_IDLE_MODE_OVRD;
2277                         writel(reg, tegra->padctl_base +
2278                                 padregs->iophy_misc_pad_s0_ctl3_0);
2279                 }
2280         }
2281         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2282                 tegra_xhci_setup_gpio_for_ss_lane(tegra);
2283                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
2284         }
2285 }
2286
2287 /* This function read XUSB registers and stores in device context */
2288 static void
2289 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
2290 {
2291
2292         /* a. Save the IPFS registers */
2293         tegra->sregs.msi_bar_sz =
2294                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2295
2296         tegra->sregs.msi_axi_barst =
2297                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2298
2299         tegra->sregs.msi_fpci_barst =
2300                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2301
2302         tegra->sregs.msi_vec0 =
2303                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2304
2305         tegra->sregs.msi_en_vec0 =
2306                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2307
2308         tegra->sregs.fpci_error_masks =
2309                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2310
2311         tegra->sregs.intr_mask =
2312                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2313
2314         tegra->sregs.ipfs_intr_enable =
2315                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2316
2317         tegra->sregs.ufpci_config =
2318                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2319
2320         tegra->sregs.clkgate_hysteresis =
2321                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2322
2323         tegra->sregs.xusb_host_mccif_fifo_cntrl =
2324                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2325
2326         /* b. Save the CFG registers */
2327
2328         tegra->sregs.hs_pls =
2329                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2330
2331         tegra->sregs.fs_pls =
2332                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2333
2334         tegra->sregs.hs_fs_speed =
2335                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2336
2337         tegra->sregs.hs_fs_pp =
2338                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2339
2340         tegra->sregs.cfg_aru =
2341                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2342
2343         tegra->sregs.cfg_order =
2344                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
2345
2346         tegra->sregs.cfg_fladj =
2347                 readl(tegra->fpci_base + XUSB_CFG_24);
2348
2349         tegra->sregs.cfg_sid =
2350                 readl(tegra->fpci_base + XUSB_CFG_16);
2351 }
2352
2353 /* This function restores XUSB registers from device context */
2354 static void
2355 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
2356 {
2357         /* Restore Cfg registers */
2358         writel(tegra->sregs.hs_pls,
2359                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2360
2361         writel(tegra->sregs.fs_pls,
2362                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2363
2364         writel(tegra->sregs.hs_fs_speed,
2365                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2366
2367         writel(tegra->sregs.hs_fs_pp,
2368                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2369
2370         writel(tegra->sregs.cfg_aru,
2371                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2372
2373         writel(tegra->sregs.cfg_order,
2374                 tegra->fpci_base + XUSB_CFG_FPCICFG);
2375
2376         writel(tegra->sregs.cfg_fladj,
2377                 tegra->fpci_base + XUSB_CFG_24);
2378
2379         writel(tegra->sregs.cfg_sid,
2380                 tegra->fpci_base + XUSB_CFG_16);
2381
2382         /* Restore IPFS registers */
2383
2384         writel(tegra->sregs.msi_bar_sz,
2385                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2386
2387         writel(tegra->sregs.msi_axi_barst,
2388                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2389
2390         writel(tegra->sregs.msi_fpci_barst,
2391                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2392
2393         writel(tegra->sregs.msi_vec0,
2394                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2395
2396         writel(tegra->sregs.msi_en_vec0,
2397                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2398
2399         writel(tegra->sregs.fpci_error_masks,
2400                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2401
2402         writel(tegra->sregs.intr_mask,
2403                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2404
2405         writel(tegra->sregs.ipfs_intr_enable,
2406                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2407
2408         writel(tegra->sregs.ufpci_config,
2409                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2410
2411         writel(tegra->sregs.clkgate_hysteresis,
2412                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2413
2414         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
2415                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2416 }
2417
2418 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
2419 {
2420         fw_message_send(tegra, MBOX_CMD_MSG_ENABLED, 0 /* no data needed */);
2421 }
2422
2423 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
2424 {
2425         struct platform_device *pdev = tegra->pdev;
2426         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
2427         u32 phys_addr_lo;
2428         u32 HwReg;
2429         u16 nblocks;
2430         time_t fw_time;
2431         struct tm fw_tm;
2432         u8 hc_caplength;
2433         u32 usbsts, count = 0xff;
2434         struct xhci_cap_regs __iomem *cap_regs;
2435         struct xhci_op_regs __iomem *op_regs;
2436
2437         /* enable mbox interrupt */
2438         writel(readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD) | MBOX_INT_EN,
2439                 tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2440
2441         /* First thing, reset the ARU. By the time we get to
2442          * loading boot code below, reset would be complete.
2443          * alternatively we can busy wait on rst pending bit.
2444          */
2445         /* Don't reset during ELPG/LP0 exit path */
2446         if (resetARU) {
2447                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
2448                 usleep_range(1000, 2000);
2449         }
2450
2451         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
2452                 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
2453                                 csb_read(tegra, XUSB_FALC_CPUCTL));
2454                 return 0;
2455         }
2456
2457         /* update the phys_log_buffer and total_entries here */
2458         cfg_tbl->phys_addr_log_buffer = tegra->log.phys_addr;
2459         cfg_tbl->total_log_entries = FW_LOG_COUNT;
2460
2461         phys_addr_lo = tegra->firmware.dma;
2462         phys_addr_lo += sizeof(struct cfgtbl);
2463
2464         /* Program the size of DFI into ILOAD_ATTR */
2465         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
2466
2467         /* Boot code of the firmware reads the ILOAD_BASE_LO register
2468          * to get to the start of the dfi in system memory.
2469          */
2470         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
2471
2472         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
2473         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
2474
2475         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
2476         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
2477
2478         /* Invalidate L2IMEM. */
2479         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
2480
2481         /* Initiate fetch of Bootcode from system memory into L2IMEM.
2482          * Program BootCode location and size in system memory.
2483          */
2484         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
2485                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
2486                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
2487         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
2488                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
2489                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
2490         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
2491
2492         /* Trigger L2IMEM Load operation. */
2493         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
2494
2495         /* Setup Falcon Auto-fill */
2496         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
2497         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
2498                 nblocks += 1;
2499         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
2500
2501         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
2502         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
2503                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
2504         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
2505
2506         csb_write(tegra, XUSB_FALC_DMACTL, 0);
2507         msleep(50);
2508
2509         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
2510
2511         /* Start Falcon CPU */
2512         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
2513         usleep_range(1000, 2000);
2514
2515         fw_time = cfg_tbl->fwimg_created_time;
2516         time_to_tm(fw_time, 0, &fw_tm);
2517         dev_info(&pdev->dev,
2518                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
2519                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
2520                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
2521                 fw_tm.tm_min, fw_tm.tm_sec,
2522                 csb_read(tegra, XUSB_FALC_CPUCTL));
2523
2524         dev_dbg(&pdev->dev, "num_hsic_port %d\n", cfg_tbl->num_hsic_port);
2525
2526         /* return fail if firmware status is not good */
2527         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
2528                 return -EFAULT;
2529
2530         cap_regs = IO_ADDRESS(tegra->host_phy_base);
2531         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
2532         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
2533
2534         /* wait for USBSTS_CNR to get set */
2535         do {
2536                 usbsts = ioread32(&op_regs->status);
2537         } while ((usbsts & STS_CNR) && count--);
2538
2539         if (!count && (usbsts & STS_CNR)) {
2540                 dev_err(&pdev->dev, "Controller not ready\n");
2541                 return -EFAULT;
2542         }
2543
2544         /* TODO move this into firmware to avoid race */
2545         writel(0x0, tegra->fpci_base + XUSB_CFG_ARU_C11PAGESEL0);
2546         writel(0x1000, tegra->fpci_base + XUSB_CFG_ARU_C11PAGESEL1);
2547         writel(0x10, tegra->fpci_base + XUSB_CFG_HSPX_CORE_HSICWRAP);
2548         reg_dump(&pdev->dev, tegra->fpci_base, XUSB_CFG_ARU_C11PAGESEL0);
2549         reg_dump(&pdev->dev, tegra->fpci_base, XUSB_CFG_ARU_C11PAGESEL1);
2550         reg_dump(&pdev->dev, tegra->fpci_base, XUSB_CFG_HSPX_CORE_HSICWRAP);
2551
2552         return 0;
2553 }
2554
2555 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
2556         bool release)
2557 {
2558         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2559         u32 reg;
2560
2561         /* Issue is only applicable for T114 */
2562         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
2563                 return;
2564
2565         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2566         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2567                         USB2_OTG_PAD_PORT_MASK(2));
2568
2569         if (!release) {
2570                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2571                         if (is_otg_host(tegra))
2572                                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2573                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2574                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2575                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2576                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2577         }
2578
2579         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2580 }
2581 /* SS ELPG Entry initiated by fw */
2582 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
2583 {
2584         struct xhci_hcd *xhci = tegra->xhci;
2585         u32 ret = 0;
2586
2587         must_have_sync_lock(tegra);
2588
2589         /* This is SS partition ELPG entry
2590          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
2591          */
2592
2593         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
2594          * only if it is sw initiated one
2595          */
2596
2597         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
2598          * SuperSpeed partition ELPG entry via mailbox protocol
2599          */
2600
2601         /* STEP 2: xHCI PEP driver and XUSB device mode driver
2602          * enable the XUSB wakeup interrupts for the SuperSpeed
2603          * and USB2.0 ports assigned to host.Section 4.1 Step 3
2604          */
2605         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2606
2607         /* STEP 3: xHCI PEP driver initiates the signal sequence
2608          * to enable the XUSB SSwake detection logic for the
2609          * SuperSpeed ports assigned to host.Section 4.1 Step 4
2610          */
2611         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, true);
2612
2613         /* STEP 4: System Power Management driver asserts reset
2614          * to XUSB SuperSpeed partition then disables its clocks
2615          */
2616         tegra_periph_reset_assert(tegra->ss_clk);
2617         clk_disable(tegra->ss_clk);
2618
2619         usleep_range(100, 200);
2620
2621         /* STEP 5: System Power Management driver disables the
2622          * XUSB SuperSpeed partition power rails.
2623          */
2624         debug_print_portsc(xhci);
2625
2626         /* tegra_powergate_partition also does partition reset assert */
2627         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
2628         if (ret) {
2629                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
2630                                 __func__);
2631                 /* TODO: error recovery? */
2632         }
2633         tegra->ss_pwr_gated = true;
2634
2635         /* STEP 6: xHCI PEP driver initiates the signal sequence
2636          * to enable the XUSB SSwake detection logic for the
2637          * SuperSpeed ports assigned to host.Section 4.1 Step 7
2638          */
2639         tegra_xhci_ss_vcore(tegra->bdata->portmap, true);
2640
2641         return ret;
2642 }
2643
2644 /* Host ELPG Entry */
2645 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
2646 {
2647         struct xhci_hcd *xhci = tegra->xhci;
2648         u32 ret;
2649
2650         must_have_sync_lock(tegra);
2651
2652         /* If ss is already powergated skip ss ctx save stuff */
2653         if (tegra->ss_pwr_gated) {
2654                 xhci_info(xhci, "%s: SS partition is already powergated\n",
2655                         __func__);
2656         } else {
2657                 ret = tegra_xhci_ss_elpg_entry(tegra);
2658                 if (ret) {
2659                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
2660                                 __func__, ret);
2661                         return ret;
2662                 }
2663         }
2664
2665         /* 1. IS INTR PENDING INT_PENDING=1 ? */
2666
2667         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
2668         tegra_xhci_save_xusb_ctx(tegra);
2669
2670         /* calculate rctrl_val and tctrl_val */
2671         tegra_xhci_war_for_tctrl_rctrl(tegra);
2672
2673         pmc_setup_wake_detect(tegra);
2674
2675         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2676         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2677                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2678
2679         /* tegra_powergate_partition also does partition reset assert */
2680         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
2681         if (ret) {
2682                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2683                         __func__, ret);
2684                 /* TODO: error handling? */
2685                 return ret;
2686         }
2687         tegra->host_pwr_gated = true;
2688         clk_disable(tegra->host_clk);
2689
2690         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2691                 clk_disable(tegra->pll_re_vco_clk);
2692         clk_disable(tegra->emc_clk);
2693         /* set port ownership to SNPS */
2694         tegra_xhci_release_port_ownership(tegra, true);
2695
2696         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2697                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2698
2699         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
2700         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
2701                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
2702         return ret;
2703 }
2704
2705 /* SS ELPG Exit triggered by PADCTL irq */
2706 /**
2707  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
2708  *
2709  * This function must be called with tegra->sync_lock acquired.
2710  *
2711  * @tegra: xhci controller context
2712  * @return 0 for success, or error numbers
2713  */
2714 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2715 {
2716         struct xhci_hcd *xhci = tegra->xhci;
2717         int ret = 0;
2718
2719         must_have_sync_lock(tegra);
2720
2721         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
2722                         tegra->hs_wake_event || tegra->host_resume_req)) {
2723
2724                 /*
2725                  * PWR_UNGATE SS partition. XUSBA
2726                  * tegra_unpowergate_partition also does partition reset
2727                  * deassert
2728                  */
2729                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
2730                 if (ret) {
2731                         xhci_err(xhci,
2732                         "%s: could not unpowergate xusba partition %d\n",
2733                         __func__, ret);
2734                         goto out;
2735                 }
2736                 if (tegra->ss_wake_event)
2737                         tegra->ss_wake_event = false;
2738
2739         } else {
2740                 xhci_info(xhci, "%s: ss already power gated\n",
2741                         __func__);
2742                 return ret;
2743         }
2744
2745         /* Step 3: Enable clock to ss partition */
2746         clk_enable(tegra->ss_clk);
2747
2748         /* Step 4: Disable ss wake detection logic */
2749         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2750
2751         /* Step 4.1: Disable ss wake detection logic */
2752         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
2753
2754         /* wait 150us */
2755         usleep_range(150, 200);
2756
2757         /* Step 4.2: Disable ss wake detection logic */
2758         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
2759
2760         /* Step 6 Deassert reset for ss clks */
2761         tegra_periph_reset_deassert(tegra->ss_clk);
2762
2763         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
2764         tegra->ss_pwr_gated = false;
2765 out:
2766         return ret;
2767 }
2768
2769 static void ss_partition_elpg_exit_work(struct work_struct *work)
2770 {
2771         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2772                 ss_elpg_exit_work);
2773
2774         mutex_lock(&tegra->sync_lock);
2775         tegra_xhci_ss_partition_elpg_exit(tegra);
2776         mutex_unlock(&tegra->sync_lock);
2777 }
2778
2779 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
2780 static void update_remote_wakeup_ports(struct tegra_xhci_hcd *tegra)
2781 {
2782         struct xhci_hcd *xhci = tegra->xhci;
2783         u32 wake2_status;
2784         int port;
2785
2786 #define PMC_WAKE2_STATUS        0x168
2787 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
2788
2789         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
2790
2791         if (wake2_status & PADCTL_WAKE) {
2792                 /* FIXME: This is customized for Dalmore, find a generic way */
2793                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
2794                 /* clear wake status */
2795                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
2796         }
2797
2798         /* set all usb2 ports with RESUME link state as wakup ports  */
2799         for (port = 0; port < xhci->num_usb2_ports; port++) {
2800                 u32 portsc = xhci_readl(xhci, xhci->usb2_ports[port]);
2801                 if ((portsc & PORT_PLS_MASK) == XDEV_RESUME)
2802                         set_bit(port, &tegra->usb2_rh_remote_wakeup_ports);
2803         }
2804
2805         xhci_dbg(xhci, "%s: usb2 roothub remote_wakeup_ports 0x%lx\n",
2806                         __func__, tegra->usb2_rh_remote_wakeup_ports);
2807         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
2808                         __func__, tegra->usb3_rh_remote_wakeup_ports);
2809 }
2810
2811 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
2812 {
2813         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2814         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2815         int port, num_ports;
2816         unsigned long *remote_wakeup_ports;
2817         u32 portsc;
2818         __le32 __iomem  **port_array;
2819         unsigned char *rh;
2820         unsigned int retry = 64;
2821         struct xhci_bus_state *bus_state;
2822
2823         bus_state = &xhci->bus_state[hcd_index(hcd)];
2824
2825         if (hcd == xhci->shared_hcd) {
2826                 port_array = xhci->usb3_ports;
2827                 num_ports = xhci->num_usb3_ports;
2828                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
2829                 rh = "usb3 roothub";
2830         } else {
2831                 port_array = xhci->usb2_ports;
2832                 num_ports = xhci->num_usb2_ports;
2833                 remote_wakeup_ports = &tegra->usb2_rh_remote_wakeup_ports;
2834                 rh = "usb2 roothub";
2835         }
2836
2837         while (*remote_wakeup_ports && retry--) {
2838                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
2839                         bool can_continue;
2840
2841                         portsc = xhci_readl(xhci, port_array[port]);
2842
2843                         if (!(portsc & PORT_CONNECT)) {
2844                                 /* nothing to do if already disconnected */
2845                                 clear_bit(port, remote_wakeup_ports);
2846                                 continue;
2847                         }
2848
2849                         if (hcd == xhci->shared_hcd) {
2850                                 can_continue =
2851                                         (portsc & PORT_PLS_MASK) == XDEV_U0;
2852                         } else {
2853                                 unsigned long flags;
2854
2855                                 spin_lock_irqsave(&xhci->lock, flags);
2856                                 can_continue =
2857                                 test_bit(port, &bus_state->resuming_ports);
2858                                 spin_unlock_irqrestore(&xhci->lock, flags);
2859                         }
2860
2861                         if (can_continue)
2862                                 clear_bit(port, remote_wakeup_ports);
2863                         else
2864                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
2865                                         __func__, rh, port, portsc);
2866                 }
2867
2868                 if (*remote_wakeup_ports)
2869                         msleep(20); /* give some time, irq will direct U0 */
2870         }
2871
2872         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
2873                         *remote_wakeup_ports);
2874 }
2875
2876 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
2877 {
2878         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2879         u32 reg, utmip_rctrl_val, utmip_tctrl_val, pad_mux, portmux, portowner;
2880         int port;
2881
2882         portmux = USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1);
2883         portowner = USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
2884                         USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2885
2886         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2887                 portmux |= USB2_OTG_PAD_PORT_MASK(2);
2888                 portowner |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2889         }
2890
2891         /* Use xusb padctl space only when xusb owns all UTMIP port */
2892         pad_mux = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2893         if ((pad_mux & portmux) == portowner) {
2894                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
2895                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
2896                  */
2897                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2898                 reg &= ~((1 << 12) | (1 << 13));
2899                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2900
2901                 /* wait 20us */
2902                 usleep_range(20, 30);
2903
2904                 /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
2905                  * :: TCTRL and RCTRL
2906                  */
2907                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl1_0);
2908                 utmip_rctrl_val = RCTRL(reg);
2909                 utmip_tctrl_val = TCTRL(reg);
2910
2911                 /*
2912                  * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
2913                  * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
2914                  */
2915                 utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
2916                 utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
2917                 utmi_phy_update_trking_data(utmip_tctrl_val, utmip_rctrl_val);
2918                 xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
2919                                         utmip_rctrl_val, utmip_tctrl_val);
2920
2921                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
2922                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
2923                  */
2924                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2925                 reg |= (1 << 13);
2926                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2927
2928                 /* Program these values into PMC regiseter and program the
2929                  * PMC override.
2930                  */
2931                 reg = PMC_TCTRL_VAL(utmip_tctrl_val) |
2932                                 PMC_RCTRL_VAL(utmip_rctrl_val);
2933                 tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG,
2934                                         0xffffffff, reg);
2935                 reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
2936                 tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
2937         } else {
2938                 /* Use common PMC API to use SNPS register space */
2939                 utmi_phy_set_snps_trking_data();
2940         }
2941 }
2942
2943 /* Host ELPG Exit triggered by PADCTL irq */
2944 /**
2945  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
2946  *
2947  * This function must be called with tegra->sync_lock acquired.
2948  *
2949  * @tegra: xhci controller context
2950  * @return 0 for success, or error numbers
2951  */
2952 static int
2953 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2954 {
2955         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2956         struct xhci_hcd *xhci = tegra->xhci;
2957         int ret = 0;
2958
2959         must_have_sync_lock(tegra);
2960
2961         if (!tegra->hc_in_elpg)
2962                 return 0;
2963
2964         clk_enable(tegra->emc_clk);
2965         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2966                 clk_enable(tegra->pll_re_vco_clk);
2967
2968         if (tegra->lp0_exit) {
2969                 u32 reg, oc_bits = 0;
2970
2971                 /* Issue is only applicable for T114 */
2972                 if (XUSB_DEVICE_ID_T114 == tegra->device_id)
2973                         tegra_xhci_war_for_tctrl_rctrl(tegra);
2974                 /* check if over current seen. Clear if present */
2975                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2976                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2977                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2978                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2979                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2980                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2981
2982                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2983                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
2984                 if (reg & oc_bits) {
2985                         xhci_info(xhci, "Over current detected. Clearing...\n");
2986                         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2987
2988                         usleep_range(100, 200);
2989
2990                         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2991                         if (reg & oc_bits)
2992                                 xhci_info(xhci, "Over current still present\n");
2993                 }
2994                 tegra_xhci_padctl_portmap_and_caps(tegra);
2995                 /* release clamps post deassert */
2996                 tegra->lp0_exit = false;
2997         }
2998
2999         /* Clear FLUSH_ENABLE of MC client */
3000         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
3001
3002         /* set port ownership back to xusb */
3003         tegra_xhci_release_port_ownership(tegra, false);
3004
3005         /*
3006          * PWR_UNGATE Host partition. XUSBC
3007          * tegra_unpowergate_partition also does partition reset deassert
3008          */
3009         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3010         if (ret) {
3011                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
3012                         __func__, ret);
3013                 goto out;
3014         }
3015         clk_enable(tegra->host_clk);
3016
3017         /* Step 4: Deassert reset to host partition clk */
3018         tegra_periph_reset_deassert(tegra->host_clk);
3019
3020         /* Step 6.1: IPFS and XUSB BAR initialization */
3021         tegra_xhci_cfg(tegra);
3022
3023         /* Step 6.2: IPFS and XUSB related restore */
3024         tegra_xhci_restore_ctx(tegra);
3025
3026         /* Step 8: xhci spec related ctx restore
3027          * will be done in xhci_resume().Do it here.
3028          */
3029
3030         tegra_xhci_ss_partition_elpg_exit(tegra);
3031
3032         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
3033         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
3034                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
3035                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
3036         }
3037
3038         /* clear ovrd bits */
3039         tegra_xhci_rx_idle_mode_override(tegra, false);
3040
3041         /* Load firmware */
3042         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
3043                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
3044                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
3045                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
3046                         __func__,
3047                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
3048                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
3049                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
3050                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
3051                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
3052                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
3053                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
3054                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
3055                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
3056         debug_print_portsc(xhci);
3057
3058         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
3059         if (ret < 0) {
3060                 xhci_err(xhci, "%s: failed to load firmware %d\n",
3061                         __func__, ret);
3062                 goto out;
3063         }
3064
3065         pmc_disable_bus_ctrl(tegra);
3066
3067         tegra->hc_in_elpg = false;
3068         ret = xhci_resume(tegra->xhci, 0);
3069         if (ret) {
3070                 xhci_err(xhci, "%s: could not resume right %d\n",
3071                                 __func__, ret);
3072                 goto out;
3073         }
3074
3075         update_remote_wakeup_ports(tegra);
3076
3077         if (tegra->hs_wake_event)
3078                 tegra->hs_wake_event = false;
3079
3080         if (tegra->host_resume_req)
3081                 tegra->host_resume_req = false;
3082
3083         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
3084                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
3085
3086         tegra->host_pwr_gated = false;
3087 out:
3088         return ret;
3089 }
3090
3091 static void host_partition_elpg_exit_work(struct work_struct *work)
3092 {
3093         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3094                 host_elpg_exit_work);
3095
3096         mutex_lock(&tegra->sync_lock);
3097         tegra_xhci_host_partition_elpg_exit(tegra);
3098         mutex_unlock(&tegra->sync_lock);
3099 }
3100
3101 /* Mailbox handling function. This function handles requests
3102  * from firmware and communicates with clock and powergating
3103  * module to alter clock rates and to power gate/ungate xusb
3104  * partitions.
3105  *
3106  * Following is the structure of mailbox messages.
3107  * bit 31:28 - msg type
3108  * bits 27:0 - mbox data
3109  * FIXME:  Check if we can just call clock functions like below
3110  * or should we schedule it for calling later ?
3111  */
3112
3113 static void
3114 tegra_xhci_process_mbox_message(struct work_struct *work)
3115 {
3116         u32 sw_resp = 0, cmd, data_in, fw_msg;
3117         int ret = 0;
3118         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
3119                                         mbox_work);
3120         struct xhci_hcd *xhci = tegra->xhci;
3121         unsigned int freq_khz;
3122         int pad, port;
3123         unsigned long ports;
3124
3125         mutex_lock(&tegra->mbox_lock);
3126
3127         /* get the mbox message from firmware */
3128         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
3129
3130         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3131         if (data_in) {
3132                 dev_warn(&tegra->pdev->dev, "%s data_in 0x%x\n",
3133                         __func__, data_in);
3134                 mutex_unlock(&tegra->mbox_lock);
3135                 return;
3136         }
3137
3138         /* get cmd type and cmd data */
3139         tegra->cmd_type = (fw_msg >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
3140         tegra->cmd_data = (fw_msg >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
3141
3142         /* decode the message and make appropriate requests to
3143          * clock or powergating module.
3144          */
3145
3146         switch (tegra->cmd_type) {
3147         case MBOX_CMD_INC_FALC_CLOCK:
3148         case MBOX_CMD_DEC_FALC_CLOCK:
3149                 ret = tegra_xusb_request_clk_rate(
3150                                 tegra,
3151                                 tegra->falc_clk,
3152                                 tegra->cmd_data,
3153                                 &sw_resp);
3154                 if (ret)
3155                         xhci_err(xhci, "%s: could not set required falc rate\n",
3156                                 __func__);
3157                 goto send_sw_response;
3158         case MBOX_CMD_INC_SSPI_CLOCK:
3159         case MBOX_CMD_DEC_SSPI_CLOCK:
3160                 ret = tegra_xusb_request_clk_rate(
3161                                 tegra,
3162                                 tegra->ss_src_clk,
3163                                 tegra->cmd_data,
3164                                 &sw_resp);
3165                 if (ret)
3166                         xhci_err(xhci, "%s: could not set required ss rate.\n",
3167                                 __func__);
3168                 goto send_sw_response;
3169         case MBOX_CMD_SET_BW:
3170                 /* fw sends BW request in MByte/sec */
3171                 freq_khz = tegra_emc_bw_to_freq_req(tegra->cmd_data << 10);
3172                 clk_set_rate(tegra->emc_clk, freq_khz * 1000);
3173
3174                 /* clear MBOX_SMI_INT_EN bit */
3175                 cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3176                 cmd &= ~MBOX_SMI_INT_EN;
3177                 writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3178
3179                 /* clear mbox owner as ACK will not be sent for this request */
3180                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
3181                 break;
3182         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
3183                 tegra_xhci_save_dfe_context(tegra, tegra->cmd_data);
3184                 tegra_xhci_save_ctle_context(tegra, tegra->cmd_data);
3185                 sw_resp = CMD_DATA(tegra->cmd_data) | CMD_TYPE(MBOX_CMD_ACK);
3186                 goto send_sw_response;
3187
3188         case MBOX_CMD_STAR_HSIC_IDLE:
3189                 ports = tegra->cmd_data;
3190                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3191                         pad = port_to_hsic_pad(port - 1);
3192                         mutex_lock(&tegra->sync_lock);
3193                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
3194                         mutex_unlock(&tegra->sync_lock);
3195                         if (ret)
3196                                 break;
3197                 }
3198
3199                 sw_resp = CMD_DATA(tegra->cmd_data);
3200                 if (!ret)
3201                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3202                 else
3203                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3204
3205                 goto send_sw_response;
3206
3207         case MBOX_CMD_STOP_HSIC_IDLE:
3208                 ports = tegra->cmd_data;
3209                 for_each_set_bit(port, &ports, BITS_PER_LONG) {
3210                         pad = port_to_hsic_pad(port - 1);
3211                         mutex_lock(&tegra->sync_lock);
3212                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_DISABLE);
3213                         mutex_unlock(&tegra->sync_lock);
3214                         if (ret)
3215                                 break;
3216                 }
3217
3218                 sw_resp = CMD_DATA(tegra->cmd_data);
3219                 if (!ret)
3220                         sw_resp |= CMD_TYPE(MBOX_CMD_ACK);
3221                 else
3222                         sw_resp |= CMD_TYPE(MBOX_CMD_NACK);
3223                 goto send_sw_response;
3224
3225         case MBOX_CMD_ACK:
3226                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3227                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
3228                 break;
3229         case MBOX_CMD_NACK:
3230                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3231                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
3232                 break;
3233         default:
3234                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
3235                                 __func__, tegra->cmd_type);
3236         }
3237         mutex_unlock(&tegra->mbox_lock);
3238         return;
3239
3240 send_sw_response:
3241         if (((sw_resp >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK) == MBOX_CMD_NACK)
3242                 xhci_err(xhci, "%s respond fw message 0x%x with NAK\n",
3243                                 __func__, fw_msg);
3244
3245         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
3246         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3247         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
3248         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
3249
3250         mutex_unlock(&tegra->mbox_lock);
3251 }
3252
3253 static irqreturn_t pmc_usb_phy_wake_isr(int irq, void *data)
3254 {
3255         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) data;
3256         struct xhci_hcd *xhci = tegra->xhci;
3257
3258         xhci_dbg(xhci, "%s irq %d", __func__, irq);
3259         return IRQ_HANDLED;
3260 }
3261
3262 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
3263 {
3264         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3265         struct xhci_hcd *xhci = tegra->xhci;
3266         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3267         u32 elpg_program0 = 0;
3268
3269         spin_lock(&tegra->lock);
3270
3271         tegra->last_jiffies = jiffies;
3272
3273         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
3274         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
3275
3276         /* Clear the interrupt cause. We already read the intr status. */
3277         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3278         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3279
3280         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
3281         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
3282                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
3283         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
3284                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
3285         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
3286                 __func__,
3287                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad0_ctl0_0));
3288         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
3289                 __func__,
3290                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad1_ctl0_0));
3291         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
3292                 __func__,
3293                 readl(tegra->padctl_base + padregs->usb2_bchrg_bias_pad_0));
3294
3295         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
3296                 tegra->ss_wake_event = true;
3297         else if (elpg_program0 & (USB2_PORT0_WAKEUP_EVENT |
3298                         USB2_PORT1_WAKEUP_EVENT |
3299                         USB2_PORT2_WAKEUP_EVENT |
3300                         USB2_HSIC_PORT0_WAKEUP_EVENT |
3301                         USB2_HSIC_PORT1_WAKEUP_EVENT))
3302                 tegra->hs_wake_event = true;
3303
3304         if (tegra->ss_wake_event || tegra->hs_wake_event) {
3305                 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
3306                         xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
3307                         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3308                 } else if (tegra->ss_pwr_gated
3309                                 && tegra->host_pwr_gated) {
3310                         xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
3311                                 __func__);
3312                         schedule_work(&tegra->host_elpg_exit_work);
3313                 }
3314         } else {
3315                 xhci_err(xhci, "error: wake due to no hs/ss event\n");
3316                 tegra_usb_pad_reg_write(padregs->elpg_program_0, 0xffffffff);
3317         }
3318         spin_unlock(&tegra->lock);
3319         return IRQ_HANDLED;
3320 }
3321
3322 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
3323 {
3324         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3325         u32 temp;
3326
3327         spin_lock(&tegra->lock);
3328
3329         /* clear the mbox intr status 1st thing. Other
3330          * bits are W1C bits, so just write to SMI bit.
3331          */
3332
3333         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3334
3335         /* write 1 to clear SMI INTR en bit ( bit 3 ) */
3336         temp = MBOX_SMI_INTR_EN;
3337         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3338
3339         schedule_work(&tegra->mbox_work);
3340
3341         spin_unlock(&tegra->lock);
3342         return IRQ_HANDLED;
3343 }
3344
3345 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
3346 {
3347         /*
3348          * As of now platform drivers don't provide MSI support so we ensure
3349          * here that the generic code does not try to make a pci_dev from our
3350          * dev struct in order to setup MSI
3351          */
3352         xhci->quirks |= XHCI_BROKEN_MSI;
3353         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
3354 }
3355
3356 /* called during probe() after chip reset completes */
3357 static int xhci_plat_setup(struct usb_hcd *hcd)
3358 {
3359         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
3360 }
3361
3362 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
3363         const char *name, void __iomem **region)
3364 {
3365         struct resource *res;
3366         void __iomem *mem;
3367
3368         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
3369         if (!res) {
3370                 dev_err(&pdev->dev, "memory resource %s doesn't exist\n", name);
3371                 return -ENODEV;
3372         }
3373
3374         mem = devm_request_and_ioremap(&pdev->dev, res);
3375         if (!mem) {
3376                 dev_err(&pdev->dev, "failed to ioremap for %s\n", name);
3377                 return -EFAULT;
3378         }
3379         *region = mem;
3380
3381         return 0;
3382 }
3383
3384 static int tegra_xhci_request_irq(struct platform_device *pdev,
3385         const char *rscname, irq_handler_t handler, unsigned long irqflags,
3386         const char *devname, int *irq_no)
3387 {
3388         int ret;
3389         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3390         struct resource *res;
3391
3392         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, rscname);
3393         if (!res) {
3394                 dev_err(&pdev->dev, "irq resource %s doesn't exist\n", rscname);
3395                 return -ENODEV;
3396         }
3397
3398         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
3399                         devname, tegra);
3400         if (ret != 0) {
3401                 dev_err(&pdev->dev,
3402                         "failed to request_irq for %s (irq %d), error = %d\n",
3403                         devname, res->start, ret);
3404                 return ret;
3405         }
3406         *irq_no = res->start;
3407
3408         return 0;
3409 }
3410
3411 #ifdef CONFIG_PM
3412
3413 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
3414 {
3415         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3416         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3417         int err = 0;
3418         unsigned long flags;
3419
3420         mutex_lock(&tegra->sync_lock);
3421
3422         if (xhci->shared_hcd == hcd) {
3423                 tegra->usb3_rh_suspend = true;
3424                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3425         } else if (xhci->main_hcd == hcd) {
3426                 tegra->usb2_rh_suspend = true;
3427                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3428         }
3429
3430         WARN_ON(tegra->hc_in_elpg);
3431
3432         /* suspend xhci bus. This will also set remote mask */
3433         err = xhci_bus_suspend(hcd);
3434         if (err) {
3435                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
3436                                 __func__, err);
3437                 goto xhci_bus_suspend_failed;
3438         }
3439
3440         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
3441                 goto done; /* one of the root hubs is still working */
3442
3443         spin_lock_irqsave(&tegra->lock, flags);
3444         tegra->hc_in_elpg = true;
3445         spin_unlock_irqrestore(&tegra->lock, flags);
3446
3447         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3448
3449         /* save xhci spec ctx. Already done by xhci_suspend */
3450         err = xhci_suspend(tegra->xhci);
3451         if (err) {
3452                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
3453                 goto xhci_suspend_failed;
3454         }
3455
3456         /* Powergate host. Include ss power gate if not already done */
3457         err = tegra_xhci_host_elpg_entry(tegra);
3458         if (err) {
3459                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
3460                                 __func__, err);
3461                 goto tegra_xhci_host_elpg_entry_failed;
3462         }
3463
3464         /* At this point,ensure ss/hs intr enables are always on */
3465         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
3466         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
3467
3468         /* In ELPG, firmware log context is gone. Rewind shared log buffer. */
3469         if (fw_log_wait_empty_timeout(tegra, 100))
3470                 xhci_warn(xhci, "%s still has logs\n", __func__);
3471         tegra->log.dequeue = tegra->log.virt_addr;
3472         tegra->log.seq = 0;
3473
3474 done:
3475         /* pads are disabled only if usb2 root hub in xusb is idle */
3476         /* pads will actually be disabled only when all usb2 ports are idle */
3477         if (xhci->main_hcd == hcd) {
3478                 utmi_phy_pad_disable();
3479                 utmi_phy_iddq_override(true);
3480         }
3481         mutex_unlock(&tegra->sync_lock);
3482         return 0;
3483
3484 tegra_xhci_host_elpg_entry_failed:
3485
3486 xhci_suspend_failed:
3487         tegra->hc_in_elpg = false;
3488 xhci_bus_suspend_failed:
3489         if (xhci->shared_hcd == hcd)
3490                 tegra->usb3_rh_suspend = false;
3491         else if (xhci->main_hcd == hcd)
3492                 tegra->usb2_rh_suspend = false;
3493
3494         mutex_unlock(&tegra->sync_lock);
3495         return err;
3496 }
3497
3498 /* First, USB2HCD and then USB3HCD resume will be called */
3499 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
3500 {
3501         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3502         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3503         int err = 0;
3504
3505         mutex_lock(&tegra->sync_lock);
3506
3507         tegra->host_resume_req = true;
3508
3509         if (xhci->shared_hcd == hcd)
3510                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3511         else if (xhci->main_hcd == hcd)
3512                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3513
3514         /* pads are disabled only if usb2 root hub in xusb is idle */
3515         /* pads will actually be disabled only when all usb2 ports are idle */
3516         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
3517                 utmi_phy_pad_enable();
3518                 utmi_phy_iddq_override(false);
3519         }
3520         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
3521                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
3522                         tegra_xhci_host_partition_elpg_exit(tegra);
3523         }
3524
3525          /* handle remote wakeup before resuming bus */
3526         wait_remote_wakeup_ports(hcd);
3527
3528         err = xhci_bus_resume(hcd);
3529         if (err) {
3530                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
3531                                 __func__, err);
3532                 goto xhci_bus_resume_failed;
3533         }
3534
3535         if (xhci->shared_hcd == hcd)
3536                 tegra->usb3_rh_suspend = false;
3537         else if (xhci->main_hcd == hcd)
3538                 tegra->usb2_rh_suspend = false;
3539
3540         mutex_unlock(&tegra->sync_lock);
3541         return 0;
3542
3543 xhci_bus_resume_failed:
3544         /* TODO: reverse elpg? */
3545         mutex_unlock(&tegra->sync_lock);
3546         return err;
3547 }
3548 #endif
3549
3550 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
3551 {
3552         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3553         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3554         irqreturn_t iret = IRQ_HANDLED;
3555         u32 status;
3556
3557         spin_lock(&tegra->lock);
3558         if (tegra->hc_in_elpg) {
3559                 spin_lock(&xhci->lock);
3560                 if (HCD_HW_ACCESSIBLE(hcd)) {
3561                         status = xhci_readl(xhci, &xhci->op_regs->status);
3562                         status |= STS_EINT;
3563                         xhci_writel(xhci, status, &xhci->op_regs->status);
3564                 }
3565                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
3566                                 __func__);
3567                 schedule_work(&tegra->host_elpg_exit_work);
3568                 spin_unlock(&xhci->lock);
3569         } else
3570                 iret = xhci_irq(hcd);
3571         spin_unlock(&tegra->lock);
3572
3573         wake_up_interruptible(&tegra->log.intr_wait);
3574
3575         return iret;
3576 }
3577
3578
3579 static const struct hc_driver tegra_plat_xhci_driver = {
3580         .description =          "tegra-xhci",
3581         .product_desc =         "Nvidia xHCI Host Controller",
3582         .hcd_priv_size =        sizeof(struct xhci_hcd *),
3583
3584         /*
3585          * generic hardware linkage
3586          */
3587         .irq =                  tegra_xhci_irq,
3588         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
3589
3590         /*
3591          * basic lifecycle operations
3592          */
3593         .reset =                xhci_plat_setup,
3594         .start =                xhci_run,
3595         .stop =                 xhci_stop,
3596         .shutdown =             xhci_shutdown,
3597
3598         /*
3599          * managing i/o requests and associated device resources
3600          */
3601         .urb_enqueue =          xhci_urb_enqueue,
3602         .urb_dequeue =          xhci_urb_dequeue,
3603         .alloc_dev =            xhci_alloc_dev,
3604         .free_dev =             xhci_free_dev,
3605         .alloc_streams =        xhci_alloc_streams,
3606         .free_streams =         xhci_free_streams,
3607         .add_endpoint =         xhci_add_endpoint,
3608         .drop_endpoint =        xhci_drop_endpoint,
3609         .endpoint_reset =       xhci_endpoint_reset,
3610         .check_bandwidth =      xhci_check_bandwidth,
3611         .reset_bandwidth =      xhci_reset_bandwidth,
3612         .address_device =       xhci_address_device,
3613         .update_hub_device =    xhci_update_hub_device,
3614         .reset_device =         xhci_discover_or_reset_device,
3615
3616         /*
3617          * scheduling support
3618          */
3619         .get_frame_number =     xhci_get_frame,
3620
3621         /* Root hub support */
3622         .hub_control =          xhci_hub_control,
3623         .hub_status_data =      xhci_hub_status_data,
3624
3625 #ifdef CONFIG_PM
3626         .bus_suspend =          tegra_xhci_bus_suspend,
3627         .bus_resume =           tegra_xhci_bus_resume,
3628 #endif
3629 };
3630
3631 #ifdef CONFIG_PM
3632 static int
3633 tegra_xhci_suspend(struct platform_device *pdev,
3634                                                 pm_message_t state)
3635 {
3636         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3637         struct xhci_hcd *xhci = tegra->xhci;
3638
3639         int ret = 0;
3640
3641         mutex_lock(&tegra->sync_lock);
3642         if (!tegra->hc_in_elpg) {
3643                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
3644                                 __func__);
3645                 mutex_unlock(&tegra->sync_lock);
3646                 return -EBUSY;
3647         }
3648         mutex_unlock(&tegra->sync_lock);
3649
3650         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3651         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3652
3653         /* enable_irq_wake for ss ports */
3654         ret = enable_irq_wake(tegra->padctl_irq);
3655         if (ret < 0) {
3656                 xhci_err(xhci,
3657                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
3658                 __func__, tegra->padctl_irq, ret);
3659         }
3660
3661         /* enable_irq_wake for utmip/uhisc wakes */
3662         ret = enable_irq_wake(tegra->usb3_irq);
3663         if (ret < 0) {
3664                 xhci_err(xhci,
3665                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3666                 __func__, tegra->usb3_irq, ret);
3667         }
3668
3669         /* enable_irq_wake for utmip/uhisc wakes */
3670         ret = enable_irq_wake(tegra->usb2_irq);
3671         if (ret < 0) {
3672                 xhci_err(xhci,
3673                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3674                 __func__, tegra->usb2_irq, ret);
3675         }
3676
3677         regulator_disable(tegra->xusb_s1p8v_reg);
3678         regulator_disable(tegra->xusb_s1p05v_reg);
3679         tegra_usb2_clocks_deinit(tegra);
3680
3681         return ret;
3682 }
3683
3684 static int
3685 tegra_xhci_resume(struct platform_device *pdev)
3686 {
3687         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3688
3689         dev_dbg(&pdev->dev, "%s\n", __func__);
3690
3691         tegra->last_jiffies = jiffies;
3692
3693         disable_irq_wake(tegra->padctl_irq);
3694         disable_irq_wake(tegra->usb3_irq);
3695         disable_irq_wake(tegra->usb2_irq);
3696         tegra->lp0_exit = true;
3697
3698         regulator_enable(tegra->xusb_s1p05v_reg);
3699         regulator_enable(tegra->xusb_s1p8v_reg);
3700         tegra_usb2_clocks_init(tegra);
3701
3702         return 0;
3703 }
3704 #endif
3705
3706
3707 static int init_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3708 {
3709         struct platform_device *pdev = tegra->pdev;
3710         void __iomem *fw_mmio_base;
3711         phys_addr_t fw_mem_phy_addr;
3712         size_t fw_size;
3713         dma_addr_t fw_dma;
3714 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3715         int ret;
3716         DEFINE_DMA_ATTRS(attrs);
3717 #endif
3718
3719         /* bootloader saved firmware memory address in PMC SCRATCH34 register */
3720         fw_mem_phy_addr = tegra_usb_pmc_reg_read(PMC_SCRATCH34);
3721
3722         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3723                         fw_mem_phy_addr, sizeof(struct cfgtbl));
3724
3725         if (!fw_mmio_base) {
3726                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3727                                         fw_mem_phy_addr);
3728                         return -ENOMEM;
3729         }
3730
3731         fw_size = ioread32(fw_mmio_base + FW_SIZE_OFFSET);
3732         devm_iounmap(&pdev->dev, fw_mmio_base);
3733
3734         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3735                         fw_mem_phy_addr, fw_size);
3736         if (!fw_mmio_base) {
3737                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3738                                         fw_mem_phy_addr);
3739                         return -ENOMEM;
3740         }
3741
3742         dev_info(&pdev->dev, "Firmware Memory: phy 0x%x mapped 0x%p (%d Bytes)\n",
3743                         fw_mem_phy_addr, fw_mmio_base, fw_size);
3744
3745 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3746         dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
3747         fw_dma = dma_map_linear_attrs(&pdev->dev, fw_mem_phy_addr, fw_size,
3748                         DMA_TO_DEVICE, &attrs);
3749
3750         if (fw_dma == DMA_ERROR_CODE) {
3751                 dev_err(&pdev->dev, "%s: dma_map_linear failed\n",
3752                                 __func__);
3753                 ret = -ENOMEM;
3754                 goto error_iounmap;
3755         }
3756 #else
3757         fw_dma = fw_mem_phy_addr;
3758 #endif
3759         dev_info(&pdev->dev, "Firmware DMA Memory: dma 0x%p (%d Bytes)\n",
3760                         (void *) fw_dma, fw_size);
3761
3762         /* all set and ready to go */
3763         tegra->firmware.data = fw_mmio_base;
3764         tegra->firmware.dma = fw_dma;
3765         tegra->firmware.size = fw_size;
3766
3767         return 0;
3768
3769 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3770 error_iounmap:
3771         devm_iounmap(&pdev->dev, fw_mmio_base);
3772         return ret;
3773 #endif
3774 }
3775
3776 static void deinit_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3777 {
3778         struct platform_device *pdev = tegra->pdev;
3779         void __iomem *fw_mmio_base = tegra->firmware.data;
3780
3781 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3782         dma_unmap_single(&pdev->dev, tegra->firmware.dma,
3783                         tegra->firmware.size, DMA_TO_DEVICE);
3784 #endif
3785         devm_iounmap(&pdev->dev, fw_mmio_base);
3786
3787         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
3788 }
3789
3790 static int init_firmware(struct tegra_xhci_hcd *tegra)
3791 {
3792         return init_bootloader_firmware(tegra);
3793 }
3794
3795 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
3796 {
3797         deinit_bootloader_firmware(tegra);
3798 }
3799
3800 static int tegra_enable_xusb_clk(struct tegra_xhci_hcd *tegra,
3801                 struct platform_device *pdev)
3802 {
3803         int err = 0;
3804         /* enable ss clock */
3805         err = clk_enable(tegra->host_clk);
3806         if (err) {
3807                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
3808                 goto enable_host_clk_failed;
3809         }
3810
3811         err = clk_enable(tegra->ss_clk);
3812         if (err) {
3813                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
3814                 goto eanble_ss_clk_failed;
3815         }
3816
3817         err = clk_enable(tegra->emc_clk);
3818         if (err) {
3819                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
3820                 goto eanble_emc_clk_failed;
3821         }
3822
3823         return 0;
3824
3825 eanble_emc_clk_failed:
3826         clk_disable(tegra->ss_clk);
3827
3828 eanble_ss_clk_failed:
3829         clk_disable(tegra->host_clk);
3830
3831 enable_host_clk_failed:
3832         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
3833                 clk_disable(tegra->pll_re_vco_clk);
3834         return err;
3835 }
3836
3837 static struct tegra_xusb_padctl_regs t114_padregs_offset = {
3838         .boot_media_0                   = 0x0,
3839         .usb2_pad_mux_0                 = 0x4,
3840         .usb2_port_cap_0                = 0x8,
3841         .snps_oc_map_0                  = 0xc,
3842         .usb2_oc_map_0                  = 0x10,
3843         .ss_port_map_0                  = 0x14,
3844         .oc_det_0                       = 0x18,
3845         .elpg_program_0                 = 0x1c,
3846         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3847         .usb2_bchrg_otgpad0_ctl1_0      = 0xffff,
3848         .usb2_bchrg_otgpad1_ctl0_0      = 0x24,
3849         .usb2_bchrg_otgpad1_ctl1_0      = 0xffff,
3850         .usb2_bchrg_otgpad2_ctl0_0      = 0xffff,
3851         .usb2_bchrg_otgpad2_ctl1_0      = 0xffff,
3852         .usb2_bchrg_bias_pad_0          = 0x28,
3853         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
3854         .iophy_pll_p0_ctl1_0            = 0x30,
3855         .iophy_pll_p0_ctl2_0            = 0x34,
3856         .iophy_pll_p0_ctl3_0            = 0x38,
3857         .iophy_pll_p0_ctl4_0            = 0x3c,
3858         .iophy_usb3_pad0_ctl1_0         = 0x40,
3859         .iophy_usb3_pad1_ctl1_0         = 0x44,
3860         .iophy_usb3_pad0_ctl2_0         = 0x48,
3861         .iophy_usb3_pad1_ctl2_0         = 0x4c,
3862         .iophy_usb3_pad0_ctl3_0         = 0x50,
3863         .iophy_usb3_pad1_ctl3_0         = 0x54,
3864         .iophy_usb3_pad0_ctl4_0         = 0x58,
3865         .iophy_usb3_pad1_ctl4_0         = 0x5c,
3866         .iophy_misc_pad_p0_ctl1_0       = 0x60,
3867         .iophy_misc_pad_p1_ctl1_0       = 0x64,
3868         .iophy_misc_pad_p0_ctl2_0       = 0x68,
3869         .iophy_misc_pad_p1_ctl2_0       = 0x6c,
3870         .iophy_misc_pad_p0_ctl3_0       = 0x70,
3871         .iophy_misc_pad_p1_ctl3_0       = 0x74,
3872         .iophy_misc_pad_p0_ctl4_0       = 0x78,
3873         .iophy_misc_pad_p1_ctl4_0       = 0x7c,
3874         .iophy_misc_pad_p0_ctl5_0       = 0x80,
3875         .iophy_misc_pad_p1_ctl5_0       = 0x84,
3876         .iophy_misc_pad_p0_ctl6_0       = 0x88,
3877         .iophy_misc_pad_p1_ctl6_0       = 0x8c,
3878         .usb2_otg_pad0_ctl0_0           = 0x90,
3879         .usb2_otg_pad1_ctl0_0           = 0x94,
3880         .usb2_otg_pad2_ctl0_0           = 0xffff,
3881         .usb2_otg_pad0_ctl1_0           = 0x98,
3882         .usb2_otg_pad1_ctl1_0           = 0x9c,
3883         .usb2_otg_pad2_ctl1_0           = 0xffff,
3884         .usb2_bias_pad_ctl0_0           = 0xa0,
3885         .usb2_bias_pad_ctl1_0           = 0xa4,
3886         .usb2_hsic_pad0_ctl0_0          = 0xa8,
3887         .usb2_hsic_pad1_ctl0_0          = 0xac,
3888         .usb2_hsic_pad0_ctl1_0          = 0xb0,
3889         .usb2_hsic_pad1_ctl1_0          = 0xb4,
3890         .usb2_hsic_pad0_ctl2_0          = 0xb8,
3891         .usb2_hsic_pad1_ctl2_0          = 0xbc,
3892         .ulpi_link_trim_ctl0            = 0xc0,
3893         .ulpi_null_clk_trim_ctl0        = 0xc4,
3894         .hsic_strb_trim_ctl0            = 0xc8,
3895         .wake_ctl0                      = 0xcc,
3896         .pm_spare0                      = 0xd0,
3897         .iophy_misc_pad_p2_ctl1_0       = 0xffff,
3898         .iophy_misc_pad_p3_ctl1_0       = 0xffff,
3899         .iophy_misc_pad_p4_ctl1_0       = 0xffff,
3900         .iophy_misc_pad_p2_ctl2_0       = 0xffff,
3901         .iophy_misc_pad_p3_ctl2_0       = 0xffff,
3902         .iophy_misc_pad_p4_ctl2_0       = 0xffff,
3903         .iophy_misc_pad_p2_ctl3_0       = 0xffff,
3904         .iophy_misc_pad_p3_ctl3_0       = 0xffff,
3905         .iophy_misc_pad_p4_ctl3_0       = 0xffff,
3906         .iophy_misc_pad_p2_ctl4_0       = 0xffff,
3907         .iophy_misc_pad_p3_ctl4_0       = 0xffff,
3908         .iophy_misc_pad_p4_ctl4_0       = 0xffff,
3909         .iophy_misc_pad_p2_ctl5_0       = 0xffff,
3910         .iophy_misc_pad_p3_ctl5_0       = 0xffff,
3911         .iophy_misc_pad_p4_ctl5_0       = 0xffff,
3912         .iophy_misc_pad_p2_ctl6_0       = 0xffff,
3913         .iophy_misc_pad_p3_ctl6_0       = 0xffff,
3914         .iophy_misc_pad_p4_ctl6_0       = 0xffff,
3915         .usb3_pad_mux_0                 = 0xffff,
3916         .iophy_pll_s0_ctl1_0            = 0xffff,
3917         .iophy_pll_s0_ctl2_0            = 0xffff,
3918         .iophy_pll_s0_ctl3_0            = 0xffff,
3919         .iophy_pll_s0_ctl4_0            = 0xffff,
3920         .iophy_misc_pad_s0_ctl1_0       = 0xffff,
3921         .iophy_misc_pad_s0_ctl2_0       = 0xffff,
3922         .iophy_misc_pad_s0_ctl3_0       = 0xffff,
3923         .iophy_misc_pad_s0_ctl4_0       = 0xffff,
3924         .iophy_misc_pad_s0_ctl5_0       = 0xffff,
3925         .iophy_misc_pad_s0_ctl6_0       = 0xffff,
3926 };
3927
3928 static struct tegra_xusb_padctl_regs t124_padregs_offset = {
3929         .boot_media_0                   = 0x0,
3930         .usb2_pad_mux_0                 = 0x4,
3931         .usb2_port_cap_0                = 0x8,
3932         .snps_oc_map_0                  = 0xc,
3933         .usb2_oc_map_0                  = 0x10,
3934         .ss_port_map_0                  = 0x14,
3935         .oc_det_0                       = 0x18,
3936         .elpg_program_0                 = 0x1c,
3937         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3938         .usb2_bchrg_otgpad0_ctl1_0      = 0x24,
3939         .usb2_bchrg_otgpad1_ctl0_0      = 0x28,
3940         .usb2_bchrg_otgpad1_ctl1_0      = 0x2c,
3941         .usb2_bchrg_otgpad2_ctl0_0      = 0x30,
3942         .usb2_bchrg_otgpad2_ctl1_0      = 0x34,
3943         .usb2_bchrg_bias_pad_0          = 0x38,
3944         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
3945         .iophy_pll_p0_ctl1_0            = 0x40,
3946         .iophy_pll_p0_ctl2_0            = 0x44,
3947         .iophy_pll_p0_ctl3_0            = 0x48,
3948         .iophy_pll_p0_ctl4_0            = 0x4c,
3949         .iophy_usb3_pad0_ctl1_0         = 0x50,
3950         .iophy_usb3_pad1_ctl1_0         = 0x54,
3951         .iophy_usb3_pad0_ctl2_0         = 0x58,
3952         .iophy_usb3_pad1_ctl2_0         = 0x5c,
3953         .iophy_usb3_pad0_ctl3_0         = 0x60,
3954         .iophy_usb3_pad1_ctl3_0         = 0x64,
3955         .iophy_usb3_pad0_ctl4_0         = 0x68,
3956         .iophy_usb3_pad1_ctl4_0         = 0x6c,
3957         .iophy_misc_pad_p0_ctl1_0       = 0x70,
3958         .iophy_misc_pad_p1_ctl1_0       = 0x74,
3959         .iophy_misc_pad_p0_ctl2_0       = 0x78,
3960         .iophy_misc_pad_p1_ctl2_0       = 0x7c,
3961         .iophy_misc_pad_p0_ctl3_0       = 0x80,
3962         .iophy_misc_pad_p1_ctl3_0       = 0x84,
3963         .iophy_misc_pad_p0_ctl4_0       = 0x88,
3964         .iophy_misc_pad_p1_ctl4_0       = 0x8c,
3965         .iophy_misc_pad_p0_ctl5_0       = 0x90,
3966         .iophy_misc_pad_p1_ctl5_0       = 0x94,
3967         .iophy_misc_pad_p0_ctl6_0       = 0x98,
3968         .iophy_misc_pad_p1_ctl6_0       = 0x9c,
3969         .usb2_otg_pad0_ctl0_0           = 0xa0,
3970         .usb2_otg_pad1_ctl0_0           = 0xa4,
3971         .usb2_otg_pad2_ctl0_0           = 0xa8,
3972         .usb2_otg_pad0_ctl1_0           = 0xac,
3973         .usb2_otg_pad1_ctl1_0           = 0xb0,
3974         .usb2_otg_pad2_ctl1_0           = 0xb4,
3975         .usb2_bias_pad_ctl0_0           = 0xb8,
3976         .usb2_bias_pad_ctl1_0           = 0xbc,
3977         .usb2_hsic_pad0_ctl0_0          = 0xc0,
3978         .usb2_hsic_pad1_ctl0_0          = 0xc4,
3979         .usb2_hsic_pad0_ctl1_0          = 0xc8,
3980         .usb2_hsic_pad1_ctl1_0          = 0xcc,
3981         .usb2_hsic_pad0_ctl2_0          = 0xd0,
3982         .usb2_hsic_pad1_ctl2_0          = 0xd4,
3983         .ulpi_link_trim_ctl0            = 0xd8,
3984         .ulpi_null_clk_trim_ctl0        = 0xdc,
3985         .hsic_strb_trim_ctl0            = 0xe0,
3986         .wake_ctl0                      = 0xe4,
3987         .pm_spare0                      = 0xe8,
3988         .iophy_misc_pad_p2_ctl1_0       = 0xec,
3989         .iophy_misc_pad_p3_ctl1_0       = 0xf0,
3990         .iophy_misc_pad_p4_ctl1_0       = 0xf4,
3991         .iophy_misc_pad_p2_ctl2_0       = 0xf8,
3992         .iophy_misc_pad_p3_ctl2_0       = 0xfc,
3993         .iophy_misc_pad_p4_ctl2_0       = 0x100,
3994         .iophy_misc_pad_p2_ctl3_0       = 0x104,
3995         .iophy_misc_pad_p3_ctl3_0       = 0x108,
3996         .iophy_misc_pad_p4_ctl3_0       = 0x10c,
3997         .iophy_misc_pad_p2_ctl4_0       = 0x110,
3998         .iophy_misc_pad_p3_ctl4_0       = 0x114,
3999         .iophy_misc_pad_p4_ctl4_0       = 0x118,
4000         .iophy_misc_pad_p2_ctl5_0       = 0x11c,
4001         .iophy_misc_pad_p3_ctl5_0       = 0x120,
4002         .iophy_misc_pad_p4_ctl5_0       = 0x124,
4003         .iophy_misc_pad_p2_ctl6_0       = 0x128,
4004         .iophy_misc_pad_p3_ctl6_0       = 0x12c,
4005         .iophy_misc_pad_p4_ctl6_0       = 0x130,
4006         .usb3_pad_mux_0                 = 0x134,
4007         .iophy_pll_s0_ctl1_0            = 0x138,
4008         .iophy_pll_s0_ctl2_0            = 0x13c,
4009         .iophy_pll_s0_ctl3_0            = 0x140,
4010         .iophy_pll_s0_ctl4_0            = 0x144,
4011         .iophy_misc_pad_s0_ctl1_0       = 0x148,
4012         .iophy_misc_pad_s0_ctl2_0       = 0x14c,
4013         .iophy_misc_pad_s0_ctl3_0       = 0x150,
4014         .iophy_misc_pad_s0_ctl4_0       = 0x154,
4015         .iophy_misc_pad_s0_ctl5_0       = 0x158,
4016         .iophy_misc_pad_s0_ctl6_0       = 0x15c,
4017 };
4018
4019 /* FIXME: using notifier to transfer control to host from suspend
4020  * for otg port when xhci is in elpg. Find  better alternative
4021  */
4022 static int tegra_xhci_otg_notify(struct notifier_block *nb,
4023                                    unsigned long event, void *unused)
4024 {
4025         struct tegra_xhci_hcd *tegra = container_of(nb,
4026                                         struct tegra_xhci_hcd, otgnb);
4027
4028         if ((event == USB_EVENT_ID))
4029                 if (tegra->hc_in_elpg) {
4030                         schedule_work(&tegra->host_elpg_exit_work);
4031                         tegra->host_resume_req = true;
4032         }
4033
4034         return NOTIFY_OK;
4035 }
4036
4037 /* TODO: we have to refine error handling in tegra_xhci_probe() */
4038 static int tegra_xhci_probe(struct platform_device *pdev)
4039 {
4040         const struct hc_driver *driver;
4041         struct xhci_hcd *xhci;
4042         struct tegra_xhci_hcd *tegra;
4043         struct resource *res;
4044         struct usb_hcd  *hcd;
4045         unsigned pad;
4046         unsigned port;
4047         u32 val;
4048         int ret;
4049         int irq;
4050
4051         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
4052
4053         if (usb_disabled())
4054                 return -ENODEV;
4055
4056         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
4057         if (!tegra) {
4058                 dev_err(&pdev->dev, "memory alloc failed\n");
4059                 return -ENOMEM;
4060         }
4061         tegra->pdev = pdev;
4062         tegra->pdata = dev_get_platdata(&pdev->dev);
4063         tegra->bdata = tegra->pdata->bdata;
4064         tegra->ss_pwr_gated = false;
4065         tegra->host_pwr_gated = false;
4066         tegra->hc_in_elpg = false;
4067         tegra->hs_wake_event = false;
4068         tegra->host_resume_req = false;
4069         tegra->lp0_exit = false;
4070
4071         ret = tegra_xhci_request_mem_region(pdev, "padctl",
4072                         &tegra->padctl_base);
4073         if (ret) {
4074                 dev_err(&pdev->dev, "failed to map padctl\n");
4075                 return ret;
4076         }
4077
4078         ret = tegra_xhci_request_mem_region(pdev, "fpci", &tegra->fpci_base);
4079         if (ret) {
4080                 dev_err(&pdev->dev, "failed to map fpci\n");
4081                 return ret;
4082         }
4083
4084         ret = tegra_xhci_request_mem_region(pdev, "ipfs", &tegra->ipfs_base);
4085         if (ret) {
4086                 dev_err(&pdev->dev, "failed to map ipfs\n");
4087                 return ret;
4088         }
4089
4090         ret = tegra_xusb_partitions_clk_init(tegra);
4091         if (ret) {
4092                 dev_err(&pdev->dev,
4093                         "failed to initialize xusb partitions clocks\n");
4094                 return ret;
4095         }
4096
4097         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0) {
4098                 tegra->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
4099                 if (IS_ERR_OR_NULL(tegra->transceiver)) {
4100                         dev_err(&pdev->dev, "failed to get usb phy\n");
4101                         tegra->transceiver = NULL;
4102                 } else {
4103                         otg_set_host(tegra->transceiver->otg, &hcd->self);
4104                         tegra->otgnb.notifier_call = tegra_xhci_otg_notify;
4105                         usb_register_notifier(tegra->transceiver,
4106                                 &tegra->otgnb);
4107                 }
4108         }
4109         /* Enable power rails to the PAD,VBUS
4110          * and pull-up voltage.Initialize the regulators
4111          */
4112         ret = tegra_xusb_regulator_init(tegra, pdev);
4113         if (ret) {
4114                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
4115                 goto err_deinit_xusb_partition_clk;
4116         }
4117
4118         /* Enable UTMIP, PLLU and PLLE */
4119         ret = tegra_usb2_clocks_init(tegra);
4120         if (ret) {
4121                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
4122                 goto err_deinit_tegra_xusb_regulator;
4123         }
4124
4125         /* tegra_unpowergate_partition also does partition reset deassert */
4126         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
4127         if (ret)
4128                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
4129
4130         /* tegra_unpowergate_partition also does partition reset deassert */
4131         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
4132         if (ret)
4133                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
4134
4135         ret = tegra_enable_xusb_clk(tegra, pdev);
4136         if (ret)
4137                 dev_err(&pdev->dev, "could not enable partition clock\n");
4138
4139         /* reset the pointer back to NULL. driver uses it */
4140         /* platform_set_drvdata(pdev, NULL); */
4141
4142         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "host");
4143         if (!res) {
4144                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
4145                 ret = -ENODEV;
4146                 goto err_deinit_usb2_clocks;
4147         }
4148         tegra->host_phy_base = res->start;
4149
4150         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
4151                                 res->start, resource_size(res));
4152         if (!tegra->host_phy_virt_base) {
4153                 dev_err(&pdev->dev, "error mapping host phy memory\n");
4154                 ret = -ENOMEM;
4155                 goto err_deinit_usb2_clocks;
4156         }
4157
4158         /* Setup IPFS access and BAR0 space */
4159         tegra_xhci_cfg(tegra);
4160
4161         val = readl(tegra->fpci_base + XUSB_CFG_0);
4162         tegra->device_id = (val >> 16) & 0xffff;
4163
4164         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
4165                 (XUSB_DEVICE_ID_T114 == tegra->device_id) ? "T114" : "T124+");
4166
4167         if (XUSB_DEVICE_ID_T114 == tegra->device_id) {
4168                 tegra->padregs = &t114_padregs_offset;
4169         } else if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
4170                 tegra->padregs = &t124_padregs_offset;
4171         } else {
4172                 dev_info(&pdev->dev, "XUSB device_id neither T114 nor T124!\n");
4173                 dev_info(&pdev->dev, "XUSB using T124 pad register offsets!\n");
4174                 tegra->padregs = &t124_padregs_offset;
4175         }
4176
4177         /* calculate rctrl_val and tctrl_val once at boot time */
4178         /* Issue is only applicable for T114 */
4179         if (XUSB_DEVICE_ID_T114 == tegra->device_id)
4180                 tegra_xhci_war_for_tctrl_rctrl(tegra);
4181
4182         for_each_enabled_hsic_pad(pad, tegra)
4183                 hsic_power_rail_enable(tegra);
4184
4185         /* Program the XUSB pads to take ownership of ports */
4186         tegra_xhci_padctl_portmap_and_caps(tegra);
4187
4188         /* Release XUSB wake logic state latching */
4189         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
4190         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
4191
4192         /* Deassert reset to XUSB host, ss, dev clocks */
4193         tegra_periph_reset_deassert(tegra->host_clk);
4194         tegra_periph_reset_deassert(tegra->ss_clk);
4195
4196         fw_log_init(tegra);
4197         ret = init_firmware(tegra);
4198         if (ret < 0) {
4199                 dev_err(&pdev->dev, "failed to init firmware\n");
4200                 ret = -ENODEV;
4201                 goto err_deinit_usb2_clocks;
4202         }
4203
4204         ret = load_firmware(tegra, true /* do reset ARU */);
4205         if (ret < 0) {
4206                 dev_err(&pdev->dev, "failed to load firmware\n");
4207                 ret = -ENODEV;
4208                 goto err_deinit_firmware;
4209         }
4210
4211         spin_lock_init(&tegra->lock);
4212         mutex_init(&tegra->sync_lock);
4213         mutex_init(&tegra->mbox_lock);
4214         pmc_init(tegra);
4215
4216         device_init_wakeup(&pdev->dev, 1);
4217         driver = &tegra_plat_xhci_driver;
4218
4219         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
4220         if (!hcd) {
4221                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
4222                 ret = -ENOMEM;
4223                 goto err_deinit_firmware;
4224         }
4225
4226         ret = tegra_xhci_request_mem_region(pdev, "host", &hcd->regs);
4227         if (ret) {
4228                 dev_err(&pdev->dev, "failed to map host\n");
4229                 goto err_put_usb2_hcd;
4230         }
4231         hcd->rsrc_start = res->start;
4232         hcd->rsrc_len = resource_size(res);
4233
4234         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "host");
4235         if (!res) {
4236                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
4237                 ret = -ENODEV;
4238                 goto err_put_usb2_hcd;
4239         }
4240         irq = res->start;
4241         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
4242         if (ret) {
4243                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
4244                 goto err_put_usb2_hcd;
4245         }
4246
4247         /* USB 2.0 roothub is stored in the platform_device now. */
4248         hcd = dev_get_drvdata(&pdev->dev);
4249         xhci = hcd_to_xhci(hcd);
4250         tegra->xhci = xhci;
4251         platform_set_drvdata(pdev, tegra);
4252
4253         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
4254                                                 dev_name(&pdev->dev), hcd);
4255         if (!xhci->shared_hcd) {
4256                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
4257                 ret = -ENOMEM;
4258                 goto err_remove_usb2_hcd;
4259         }
4260
4261         /*
4262          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
4263          * is called by usb_add_hcd().
4264          */
4265         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
4266
4267         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
4268         if (ret) {
4269                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
4270                 goto err_put_usb3_hcd;
4271         }
4272
4273         device_init_wakeup(&hcd->self.root_hub->dev, 1);
4274         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
4275
4276         /* do mailbox related initializations */
4277         tegra->mbox_owner = 0xffff;
4278         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
4279
4280         tegra_xhci_enable_fw_message(tegra);
4281
4282         /* do ss partition elpg exit related initialization */
4283         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
4284
4285         /* do host partition elpg exit related initialization */
4286         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
4287
4288         /* Register interrupt handler for SMI line to handle mailbox
4289          * interrupt from firmware
4290          */
4291         ret = tegra_xhci_request_irq(pdev, "host-smi", tegra_xhci_smi_irq,
4292                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
4293         if (ret != 0)
4294                 goto err_remove_usb3_hcd;
4295
4296         /* Register interrupt handler for PADCTRL line to
4297          * handle wake on connect irqs interrupt from
4298          * firmware
4299          */
4300         ret = tegra_xhci_request_irq(pdev, "padctl", tegra_xhci_padctl_irq,
4301                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
4302                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
4303         if (ret != 0)
4304                 goto err_remove_usb3_hcd;
4305
4306         ret = tegra_xhci_request_irq(pdev, "usb2", pmc_usb_phy_wake_isr,
4307                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4308                 &tegra->usb2_irq);
4309         if (ret != 0)
4310                 goto err_remove_usb3_hcd;
4311
4312         ret = tegra_xhci_request_irq(pdev, "usb3", pmc_usb_phy_wake_isr,
4313                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4314                 &tegra->usb3_irq);
4315         if (ret != 0)
4316                 goto err_remove_usb3_hcd;
4317
4318         for (port = 0; port < XUSB_SS_PORT_COUNT; port++) {
4319                 tegra->ctle_ctx_saved[port] = false;
4320                 tegra->dfe_ctx_saved[port] = false;
4321         }
4322
4323         hsic_pad_pretend_connect(tegra);
4324
4325         tegra_xhci_debug_read_pads(tegra);
4326         utmi_phy_pad_enable();
4327         utmi_phy_iddq_override(false);
4328
4329         tegra_pd_add_device(&pdev->dev);
4330
4331         return 0;
4332
4333 err_remove_usb3_hcd:
4334         usb_remove_hcd(xhci->shared_hcd);
4335 err_put_usb3_hcd:
4336         usb_put_hcd(xhci->shared_hcd);
4337 err_remove_usb2_hcd:
4338         kfree(tegra->xhci);
4339         usb_remove_hcd(hcd);
4340 err_put_usb2_hcd:
4341         usb_put_hcd(hcd);
4342 err_deinit_firmware:
4343         deinit_firmware(tegra);
4344 err_deinit_usb2_clocks:
4345         tegra_usb2_clocks_deinit(tegra);
4346 err_deinit_tegra_xusb_regulator:
4347         tegra_xusb_regulator_deinit(tegra);
4348 err_deinit_xusb_partition_clk:
4349         usb_unregister_notifier(tegra->transceiver,
4350                 &tegra->otgnb);
4351         tegra_xusb_partitions_clk_deinit(tegra);
4352
4353         return ret;
4354 }
4355
4356 static int tegra_xhci_remove(struct platform_device *pdev)
4357 {
4358         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4359         struct xhci_hcd *xhci = NULL;
4360         struct usb_hcd *hcd = NULL;
4361         unsigned pad;
4362
4363         if (tegra == NULL)
4364                 return -EINVAL;
4365
4366         xhci = tegra->xhci;
4367         hcd = xhci_to_hcd(xhci);
4368
4369         for_each_enabled_hsic_pad(pad, tegra) {
4370                 hsic_pad_disable(tegra, pad);
4371                 hsic_power_rail_disable(tegra);
4372         }
4373
4374         devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
4375         devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
4376         devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
4377         usb_remove_hcd(xhci->shared_hcd);
4378         usb_put_hcd(xhci->shared_hcd);
4379         usb_remove_hcd(hcd);
4380         usb_put_hcd(hcd);
4381         kfree(xhci);
4382
4383         deinit_firmware(tegra);
4384         fw_log_deinit(tegra);
4385         tegra_xusb_regulator_deinit(tegra);
4386         usb_unregister_notifier(tegra->transceiver,
4387                 &tegra->otgnb);
4388         tegra_usb2_clocks_deinit(tegra);
4389         if (!tegra->hc_in_elpg)
4390                 tegra_xusb_partitions_clk_deinit(tegra);
4391         utmi_phy_pad_disable();
4392         utmi_phy_iddq_override(true);
4393
4394         tegra_pd_remove_device(&pdev->dev);
4395         return 0;
4396 }
4397
4398 static void tegra_xhci_shutdown(struct platform_device *pdev)
4399 {
4400         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4401         struct xhci_hcd *xhci = NULL;
4402         struct usb_hcd *hcd = NULL;
4403
4404         if (tegra == NULL)
4405                 return;
4406
4407         if (tegra->hc_in_elpg) {
4408                 pmc_disable_bus_ctrl(tegra);
4409         } else {
4410                 xhci = tegra->xhci;
4411                 hcd = xhci_to_hcd(xhci);
4412                 xhci_shutdown(hcd);
4413         }
4414 }
4415
4416 static struct platform_driver tegra_xhci_driver = {
4417         .probe  = tegra_xhci_probe,
4418         .remove = tegra_xhci_remove,
4419         .shutdown = tegra_xhci_shutdown,
4420 #ifdef CONFIG_PM
4421         .suspend = tegra_xhci_suspend,
4422         .resume  = tegra_xhci_resume,
4423 #endif
4424         .driver = {
4425                 .name = "tegra-xhci",
4426         },
4427 };
4428 MODULE_ALIAS("platform:tegra-xhci");
4429
4430 int tegra_xhci_register_plat(void)
4431 {
4432         return platform_driver_register(&tegra_xhci_driver);
4433 }
4434
4435 void tegra_xhci_unregister_plat(void)
4436 {
4437         platform_driver_unregister(&tegra_xhci_driver);
4438 }