xhci: tegra: rewind firmware log buffer across ELPG
[linux-3.10.git] / drivers / usb / host / xhci-tegra.c
1 /*
2  * xhci-tegra.c - Nvidia xHCI host controller driver
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/clk.h>
24 #include <linux/ioport.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irq.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/uaccess.h>
30 #include <linux/circ_buf.h>
31 #include <linux/vmalloc.h>
32 #include <linux/debugfs.h>
33 #include <linux/kthread.h>
34 #include <linux/gpio.h>
35
36 #include <mach/powergate.h>
37 #include <mach/clk.h>
38 #include <mach/tegra_usb_pad_ctrl.h>
39 #include <mach/tegra_usb_pmc.h>
40 #include <mach/pm_domains.h>
41 #include <mach/mc.h>
42 #include <mach/xusb.h>
43
44 #include "../../../arch/arm/mach-tegra/iomap.h" /* HACK -- remove */
45 #include "xhci-tegra.h"
46 #include "xhci.h"
47
48 /* macros */
49 #define FW_IOCTL_LOG_DEQUEUE_LOW        (4)
50 #define FW_IOCTL_LOG_DEQUEUE_HIGH       (5)
51 #define FW_IOCTL_DATA_SHIFT             (0)
52 #define FW_IOCTL_DATA_MASK              (0x00ffffff)
53 #define FW_IOCTL_TYPE_SHIFT             (24)
54 #define FW_IOCTL_TYPE_MASK              (0xff000000)
55 #define FW_LOG_SIZE                     (sizeof(struct log_entry))
56 #define FW_LOG_COUNT                    (4096)
57 #define FW_LOG_RING_SIZE                (FW_LOG_SIZE * FW_LOG_COUNT)
58 #define FW_LOG_PAYLOAD_SIZE             (27)
59 #define DRIVER                          (0x01)
60 #define CIRC_BUF_SIZE                   (4 * (1 << 20)) /* 4MB */
61 #define FW_LOG_THREAD_RELAX             (msecs_to_jiffies(100))
62
63 /* tegra_xhci_firmware_log.flags bits */
64 #define FW_LOG_CONTEXT_VALID            (0)
65 #define FW_LOG_FILE_OPENED              (1)
66
67 #define PAGE_SELECT_MASK                        0xFFFFFE00
68 #define PAGE_SELECT_SHIFT                       9
69 #define PAGE_OFFSET_MASK                        0x000001FF
70 #define CSB_PAGE_SELECT(_addr)                                          \
71         ({                                                              \
72                 typecheck(u32, _addr);                                  \
73                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
74         })
75 #define CSB_PAGE_OFFSET(_addr)                                          \
76         ({                                                              \
77                 typecheck(u32, _addr);                                  \
78                 (_addr & PAGE_OFFSET_MASK);                             \
79         })
80
81 /* PMC register definition */
82 #define PMC_PORT_UTMIP_P0               0
83 #define PMC_PORT_UTMIP_P1               1
84 #define PMC_PORT_UTMIP_P2               2
85 #define PMC_PORT_UHSIC_P0               3
86 #define PMC_PORT_NUM                    4
87
88 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
89 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
90 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
91
92 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
93
94 /* private data types */
95 /* command requests from the firmware */
96 enum MBOX_CMD_TYPE {
97         MBOX_CMD_MSG_ENABLED = 1,
98         MBOX_CMD_INC_FALC_CLOCK,
99         MBOX_CMD_DEC_FALC_CLOCK,
100         MBOX_CMD_INC_SSPI_CLOCK,
101         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
102         MBOX_CMD_SET_BW,
103         MBOX_CMD_SET_SS_PWR_GATING,
104         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
105         MBOX_CMD_SAVE_DFE_CTLE_CTX,
106
107         /* needs to be the last cmd */
108         MBOX_CMD_MAX,
109
110         /* resp msg to ack above commands */
111         MBOX_CMD_ACK = 128,
112         MBOX_CMD_NACK
113 };
114
115 struct log_entry {
116         u32 sequence_no;
117         u8 data[FW_LOG_PAYLOAD_SIZE];
118         u8 owner;
119 };
120
121 /* Usb3 Firmware Cfg Table */
122 struct cfgtbl {
123         u32 boot_loadaddr_in_imem;
124         u32 boot_codedfi_offset;
125         u32 boot_codetag;
126         u32 boot_codesize;
127
128         /* Physical memory reserved by Bootloader/BIOS */
129         u32 phys_memaddr;
130         u16 reqphys_memsize;
131         u16 alloc_phys_memsize;
132
133         /* .rodata section */
134         u32 rodata_img_offset;
135         u32 rodata_section_start;
136         u32 rodata_section_end;
137         u32 main_fnaddr;
138
139         u32 fwimg_cksum;
140         u32 fwimg_created_time;
141
142         /* Fields that get filled by linker during linking phase
143          * or initialized in the FW code.
144          */
145         u32 imem_resident_start;
146         u32 imem_resident_end;
147         u32 idirect_start;
148         u32 idirect_end;
149         u32 l2_imem_start;
150         u32 l2_imem_end;
151         u32 version_id;
152         u8 init_ddirect;
153         u8 reserved[3];
154         u32 phys_addr_log_buffer;
155         u32 total_log_entries;
156         u32 dequeue_ptr;
157
158         /*      Below two dummy variables are used to replace
159          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
160          *      retain the size of struct _CFG_TBL used by other AP/Module.
161          */
162         u32 dummy_var1;
163         u32 dummy_var2;
164
165         /* fwimg_len */
166         u32 fwimg_len;
167         u8 magic[8];
168         u32 SS_low_power_entry_timeout;
169         u8 padding[140]; /* padding bytes to makeup 256-bytes cfgtbl */
170 };
171
172 struct xusb_save_regs {
173         u32 msi_bar_sz;
174         u32 msi_axi_barst;
175         u32 msi_fpci_barst;
176         u32 msi_vec0;
177         u32 msi_en_vec0;
178         u32 fpci_error_masks;
179         u32 intr_mask;
180         u32 ipfs_intr_enable;
181         u32 ufpci_config;
182         u32 clkgate_hysteresis;
183         u32 xusb_host_mccif_fifo_cntrl;
184
185         /* PG does not mention below */
186         u32 hs_pls;
187         u32 fs_pls;
188         u32 hs_fs_speed;
189         u32 hs_fs_pp;
190         u32 cfg_aru;
191         u32 cfg_order;
192         u32 cfg_fladj;
193         u32 cfg_sid;
194         /* DFE and CTLE */
195         u32 tap1_val[2];
196         u32 amp_val[2];
197         u32 ctle_z_val[2];
198         u32 ctle_g_val[2];
199 };
200
201 struct tegra_xhci_firmware {
202         void *data; /* kernel virtual address */
203         size_t size; /* firmware size */
204         dma_addr_t dma; /* dma address for controller */
205 };
206
207 struct tegra_xhci_firmware_log {
208         dma_addr_t phys_addr;           /* dma-able address */
209         void *virt_addr;                /* kernel va of the shared log buffer */
210         struct log_entry *dequeue;      /* current dequeue pointer (va) */
211         struct circ_buf circ;           /* big circular buffer */
212         u32 seq;                        /* log sequence number */
213
214         struct task_struct *thread;     /* a thread to consume log */
215         struct mutex mutex;
216         wait_queue_head_t read_wait;
217         wait_queue_head_t write_wait;
218         wait_queue_head_t intr_wait;
219         struct dentry *path;
220         struct dentry *log_file;
221         unsigned long flags;
222 };
223
224 /* structure to hold the offsets of padctl registers */
225 struct tegra_xusb_padctl_regs {
226         u16 boot_media_0;
227         u16 usb2_pad_mux_0;
228         u16 usb2_port_cap_0;
229         u16 snps_oc_map_0;
230         u16 usb2_oc_map_0;
231         u16 ss_port_map_0;
232         u16 oc_det_0;
233         u16 elpg_program_0;
234         u16 usb2_bchrg_otgpad0_ctl0_0;
235         u16 usb2_bchrg_otgpad0_ctl1_0;
236         u16 usb2_bchrg_otgpad1_ctl0_0;
237         u16 usb2_bchrg_otgpad1_ctl1_0;
238         u16 usb2_bchrg_otgpad2_ctl0_0;
239         u16 usb2_bchrg_otgpad2_ctl1_0;
240         u16 usb2_bchrg_bias_pad_0;
241         u16 usb2_bchrg_tdcd_dbnc_timer_0;
242         u16 iophy_pll_p0_ctl1_0;
243         u16 iophy_pll_p0_ctl2_0;
244         u16 iophy_pll_p0_ctl3_0;
245         u16 iophy_pll_p0_ctl4_0;
246         u16 iophy_usb3_pad0_ctl1_0;
247         u16 iophy_usb3_pad1_ctl1_0;
248         u16 iophy_usb3_pad0_ctl2_0;
249         u16 iophy_usb3_pad1_ctl2_0;
250         u16 iophy_usb3_pad0_ctl3_0;
251         u16 iophy_usb3_pad1_ctl3_0;
252         u16 iophy_usb3_pad0_ctl4_0;
253         u16 iophy_usb3_pad1_ctl4_0;
254         u16 iophy_misc_pad_p0_ctl1_0;
255         u16 iophy_misc_pad_p1_ctl1_0;
256         u16 iophy_misc_pad_p0_ctl2_0;
257         u16 iophy_misc_pad_p1_ctl2_0;
258         u16 iophy_misc_pad_p0_ctl3_0;
259         u16 iophy_misc_pad_p1_ctl3_0;
260         u16 iophy_misc_pad_p0_ctl4_0;
261         u16 iophy_misc_pad_p1_ctl4_0;
262         u16 iophy_misc_pad_p0_ctl5_0;
263         u16 iophy_misc_pad_p1_ctl5_0;
264         u16 iophy_misc_pad_p0_ctl6_0;
265         u16 iophy_misc_pad_p1_ctl6_0;
266         u16 usb2_otg_pad0_ctl0_0;
267         u16 usb2_otg_pad1_ctl0_0;
268         u16 usb2_otg_pad2_ctl0_0;
269         u16 usb2_otg_pad0_ctl1_0;
270         u16 usb2_otg_pad1_ctl1_0;
271         u16 usb2_otg_pad2_ctl1_0;
272         u16 usb2_bias_pad_ctl0_0;
273         u16 usb2_bias_pad_ctl1_0;
274         u16 usb2_hsic_pad0_ctl0_0;
275         u16 usb2_hsic_pad1_ctl0_0;
276         u16 usb2_hsic_pad0_ctl1_0;
277         u16 usb2_hsic_pad1_ctl1_0;
278         u16 usb2_hsic_pad0_ctl2_0;
279         u16 usb2_hsic_pad1_ctl2_0;
280         u16 ulpi_link_trim_ctl0;
281         u16 ulpi_null_clk_trim_ctl0;
282         u16 hsic_strb_trim_ctl0;
283         u16 wake_ctl0;
284         u16 pm_spare0;
285         u16 iophy_misc_pad_p2_ctl1_0;
286         u16 iophy_misc_pad_p3_ctl1_0;
287         u16 iophy_misc_pad_p4_ctl1_0;
288         u16 iophy_misc_pad_p2_ctl2_0;
289         u16 iophy_misc_pad_p3_ctl2_0;
290         u16 iophy_misc_pad_p4_ctl2_0;
291         u16 iophy_misc_pad_p2_ctl3_0;
292         u16 iophy_misc_pad_p3_ctl3_0;
293         u16 iophy_misc_pad_p4_ctl3_0;
294         u16 iophy_misc_pad_p2_ctl4_0;
295         u16 iophy_misc_pad_p3_ctl4_0;
296         u16 iophy_misc_pad_p4_ctl4_0;
297         u16 iophy_misc_pad_p2_ctl5_0;
298         u16 iophy_misc_pad_p3_ctl5_0;
299         u16 iophy_misc_pad_p4_ctl5_0;
300         u16 iophy_misc_pad_p2_ctl6_0;
301         u16 iophy_misc_pad_p3_ctl6_0;
302         u16 iophy_misc_pad_p4_ctl6_0;
303         u16 usb3_pad_mux_0;
304         u16 iophy_pll_s0_ctl1_0;
305         u16 iophy_pll_s0_ctl2_0;
306         u16 iophy_pll_s0_ctl3_0;
307         u16 iophy_pll_s0_ctl4_0;
308         u16 iophy_misc_pad_s0_ctl1_0;
309         u16 iophy_misc_pad_s0_ctl2_0;
310         u16 iophy_misc_pad_s0_ctl3_0;
311         u16 iophy_misc_pad_s0_ctl4_0;
312         u16 iophy_misc_pad_s0_ctl5_0;
313         u16 iophy_misc_pad_s0_ctl6_0;
314 };
315
316 struct tegra_xhci_hcd {
317         struct platform_device *pdev;
318         struct xhci_hcd *xhci;
319         u16 device_id;
320
321         spinlock_t lock;
322         struct mutex sync_lock;
323
324         int smi_irq;
325         int padctl_irq;
326         int usb3_irq;
327
328         bool ss_wake_event;
329         bool ss_pwr_gated;
330         bool host_pwr_gated;
331         bool hs_wake_event;
332         bool host_resume_req;
333         bool lp0_exit;
334         bool dfe_ctle_ctx_saved;
335         unsigned long last_jiffies;
336         unsigned long host_phy_base;
337         void __iomem *host_phy_virt_base;
338
339         void __iomem *padctl_base;
340         void __iomem *fpci_base;
341         void __iomem *ipfs_base;
342
343         struct tegra_xusb_platform_data *pdata;
344         struct tegra_xusb_board_data *bdata;
345         struct tegra_xusb_padctl_regs *padregs;
346
347         /* mailbox variables */
348         struct mutex mbox_lock;
349         u32 mbox_owner;
350         u32 cmd_type;
351         u32 cmd_data;
352
353         struct regulator *xusb_s5p0v_reg;
354         struct regulator *xusb_s5p0v1_reg;
355         struct regulator *xusb_s5p0v2_reg;
356         struct regulator *xusb_s1p05v_reg;
357         struct regulator *xusb_s3p3v_reg;
358         struct regulator *xusb_s1p8v_reg;
359
360         struct work_struct mbox_work;
361         struct work_struct ss_elpg_exit_work;
362         struct work_struct host_elpg_exit_work;
363
364         struct clk *host_clk;
365         struct clk *ss_clk;
366
367         /* XUSB Falcon SuperSpeed Clock */
368         struct clk *falc_clk;
369
370         /* EMC Clock */
371         struct clk *emc_clk;
372         /* XUSB SS PI Clock */
373         struct clk *ss_src_clk;
374         /* PLLE Clock */
375         struct clk *plle_clk;
376         struct clk *pll_u_480M;
377         struct clk *clk_m;
378         /* refPLLE clk */
379         struct clk *pll_re_vco_clk;
380         /*
381          * XUSB/IPFS specific registers these need to be saved/restored in
382          * addition to spec defined registers
383          */
384         struct xusb_save_regs sregs;
385         bool usb2_rh_suspend;
386         bool usb3_rh_suspend;
387         bool hc_in_elpg;
388
389         unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
390         /* firmware loading related */
391         struct tegra_xhci_firmware firmware;
392
393         struct tegra_xhci_firmware_log log;
394 };
395
396 static struct tegra_usb_pmc_data pmc_data;
397
398 /* functions */
399 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
400 {
401         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
402 }
403
404 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
405 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
406 {
407         WARN_ON(tegra->sync_lock.owner != current);
408 }
409 #else
410 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
411 #endif
412
413 static void tegra_xhci_setup_gpio_for_ss_lane(struct tegra_xhci_hcd *tegra)
414 {
415         int err = 0;
416
417         if (!tegra->bdata->gpio_controls_muxed_ss_lanes)
418                 return;
419
420         if (tegra->bdata->lane_owner & BIT(0)) {
421                 /* USB3_SS port1 is using SATA lane so set (MUX_SATA)
422                  * GPIO P11 to '0'
423                  */
424                 err = gpio_request((tegra->bdata->gpio_ss1_sata & 0xffff),
425                         "gpio_ss1_sata");
426                 if (err < 0)
427                         pr_err("%s: gpio_ss1_sata gpio_request failed %d\n",
428                                 __func__, err);
429                 err = gpio_direction_output((tegra->bdata->gpio_ss1_sata
430                         & 0xffff), 1);
431                 if (err < 0)
432                         pr_err("%s: gpio_ss1_sata gpio_direction failed %d\n",
433                                 __func__, err);
434                 __gpio_set_value((tegra->bdata->gpio_ss1_sata & 0xffff),
435                                 ((tegra->bdata->gpio_ss1_sata >> 16)));
436         }
437 }
438
439 static void debug_print_portsc(struct xhci_hcd *xhci)
440 {
441         __le32 __iomem *addr;
442         int i;
443         int ports;
444
445         ports = HCS_MAX_PORTS(xhci->hcs_params1);
446         addr = &xhci->op_regs->port_status_base;
447         for (i = 0; i < ports; i++) {
448                 xhci_dbg(xhci, "%p port %d status reg = 0x%x\n",
449                                 addr, i, (unsigned int) xhci_readl(xhci, addr));
450                 addr += NUM_PORT_REGS;
451         }
452 }
453
454 static void update_speed(struct tegra_xhci_hcd *tegra, u8 port, bool setup_wake)
455 {
456         struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
457         u32 portsc;
458
459         /* we don't need speed information to disable PMC */
460         if (!setup_wake)
461                 return;
462
463         portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port));
464         if (DEV_FULLSPEED(portsc))
465                 pmc_data.port_speed = USB_PMC_PORT_SPEED_FULL;
466         else if (DEV_HIGHSPEED(portsc))
467                 pmc_data.port_speed = USB_PMC_PORT_SPEED_HIGH;
468         else if (DEV_LOWSPEED(portsc))
469                 pmc_data.port_speed = USB_PMC_PORT_SPEED_LOW;
470         else if (DEV_SUPERSPEED(portsc))
471                 pmc_data.port_speed = USB_PMC_PORT_SPEED_SUPER;
472         else
473                 pmc_data.port_speed = USB_PMC_PORT_SPEED_UNKNOWN;
474 }
475
476 static void setup_wake_detect(bool setup_wake)
477 {
478         if (setup_wake)
479                 pmc_data.pmc_ops->setup_pmc_wake_detect(&pmc_data);
480         else
481                 pmc_data.pmc_ops->disable_pmc_bus_ctrl(&pmc_data, 0);
482 }
483
484 static void pmc_init(struct tegra_xhci_hcd *tegra, bool setup_wake)
485 {
486         u32 portmap = tegra->bdata->portmap;
487
488         pmc_data.controller_type = TEGRA_USB_3_0;
489         if (portmap & TEGRA_XUSB_USB2_P0) {
490                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 0) & 0xf;
491                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
492                 update_speed(tegra, pmc_data.instance, setup_wake);
493                 tegra_usb_pmc_init(&pmc_data);
494                 setup_wake_detect(setup_wake);
495         }
496         if (portmap & TEGRA_XUSB_USB2_P1) {
497                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 4) & 0xf;
498                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
499                 update_speed(tegra, pmc_data.instance, setup_wake);
500                 tegra_usb_pmc_init(&pmc_data);
501                 setup_wake_detect(setup_wake);
502         }
503         if (portmap & TEGRA_XUSB_USB2_P2) {
504                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 8) & 0xf;
505                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
506                 update_speed(tegra, pmc_data.instance, setup_wake);
507                 tegra_usb_pmc_init(&pmc_data);
508                 setup_wake_detect(setup_wake);
509         }
510         if (portmap & TEGRA_XUSB_HSIC_P0) {
511                 pmc_data.instance = PMC_PORT_UHSIC_P0;
512                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_HSIC;
513                 update_speed(tegra, pmc_data.instance, setup_wake);
514                 tegra_usb_pmc_init(&pmc_data);
515                 setup_wake_detect(setup_wake);
516         }
517 }
518
519 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
520 {
521         void __iomem *fpci_base = tegra->fpci_base;
522         struct platform_device *pdev = tegra->pdev;
523         u32 input_addr;
524         u32 data;
525         u32 csb_page_select;
526
527         /* to select the appropriate CSB page to write to */
528         csb_page_select = CSB_PAGE_SELECT(addr);
529
530         dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
531                         csb_page_select);
532
533         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
534
535         /* selects the appropriate offset in the page to read from */
536         input_addr = CSB_PAGE_OFFSET(addr);
537         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
538
539         dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
540                         input_addr, data);
541         return data;
542 }
543
544 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
545 {
546         void __iomem *fpci_base = tegra->fpci_base;
547         struct platform_device *pdev = tegra->pdev;
548         u32 input_addr;
549         u32 csb_page_select;
550
551         /* to select the appropriate CSB page to write to */
552         csb_page_select = CSB_PAGE_SELECT(addr);
553
554         dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
555                         csb_page_select);
556
557         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
558
559         /* selects the appropriate offset in the page to write to */
560         input_addr = CSB_PAGE_OFFSET(addr);
561         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
562
563         dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
564                         input_addr, data);
565 }
566
567 /**
568  * fw_log_next - find next log entry in a tegra_xhci_firmware_log context.
569  *      This function takes care of wrapping. That means when current log entry
570  *      is the last one, it returns with the first one.
571  *
572  * @param log   The tegra_xhci_firmware_log context.
573  * @param this  The current log entry.
574  * @return      The log entry which is next to the current one.
575  */
576 static inline struct log_entry *fw_log_next(
577                 struct tegra_xhci_firmware_log *log, struct log_entry *this)
578 {
579         struct log_entry *first = (struct log_entry *) log->virt_addr;
580         struct log_entry *last = first + FW_LOG_COUNT - 1;
581
582         WARN((this < first) || (this > last), "%s: invalid input\n", __func__);
583
584         return (this == last) ? first : (this + 1);
585 }
586
587 /**
588  * fw_log_update_dequeue_pointer - update dequeue pointer to both firmware and
589  *      tegra_xhci_firmware_log.dequeue.
590  *
591  * @param log   The tegra_xhci_firmware_log context.
592  * @param n     Counts of log entries to fast-forward.
593  */
594 static inline void fw_log_update_deq_pointer(
595                 struct tegra_xhci_firmware_log *log, int n)
596 {
597         struct tegra_xhci_hcd *tegra =
598                         container_of(log, struct tegra_xhci_hcd, log);
599         struct device *dev = &tegra->pdev->dev;
600         struct log_entry *deq = tegra->log.dequeue;
601         dma_addr_t physical_addr;
602         u32 reg;
603
604         dev_dbg(dev, "curr 0x%p fast-forward %d entries\n", deq, n);
605         while (n-- > 0)
606                 deq = fw_log_next(log, deq);
607
608         tegra->log.dequeue = deq;
609         physical_addr = tegra->log.phys_addr +
610                         ((u8 *)deq - (u8 *)tegra->log.virt_addr);
611
612         /* update dequeue pointer to firmware */
613         reg = (FW_IOCTL_LOG_DEQUEUE_LOW << FW_IOCTL_TYPE_SHIFT);
614         reg |= (physical_addr & 0xffff); /* lower 16-bits */
615         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
616
617         reg = (FW_IOCTL_LOG_DEQUEUE_HIGH << FW_IOCTL_TYPE_SHIFT);
618         reg |= ((physical_addr >> 16) & 0xffff); /* higher 16-bits */
619         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
620
621         dev_dbg(dev, "new 0x%p physical addr 0x%x\n", deq, physical_addr);
622 }
623
624 static inline bool circ_buffer_full(struct circ_buf *circ)
625 {
626         int space = CIRC_SPACE(circ->head, circ->tail, CIRC_BUF_SIZE);
627
628         return (space <= FW_LOG_SIZE);
629 }
630
631 static inline bool fw_log_available(struct tegra_xhci_hcd *tegra)
632 {
633         return (tegra->log.dequeue->owner == DRIVER);
634 }
635
636 /**
637  * fw_log_wait_empty_timeout - wait firmware log thread to clean up shared
638  *      log buffer.
639  * @param tegra:        tegra_xhci_hcd context
640  * @param msec:         timeout value in millisecond
641  * @return true:        shared log buffer is empty,
642  *         false:       shared log buffer isn't empty.
643  */
644 static inline bool fw_log_wait_empty_timeout(struct tegra_xhci_hcd *tegra,
645                 unsigned timeout)
646 {
647         u32 target = jiffies + msecs_to_jiffies(timeout);
648         bool ret;
649
650         mutex_lock(&tegra->log.mutex);
651
652         while (fw_log_available(tegra) && time_is_after_jiffies(target)) {
653                 mutex_unlock(&tegra->log.mutex);
654                 usleep_range(1000, 2000);
655                 mutex_lock(&tegra->log.mutex);
656         }
657
658         ret = fw_log_available(tegra);
659         mutex_unlock(&tegra->log.mutex);
660
661         return ret;
662 }
663
664 /**
665  * fw_log_copy - copy firmware log from device's buffer to driver's circular
666  *      buffer.
667  * @param tegra tegra_xhci_hcd context
668  * @return true,        We still have firmware log in device's buffer to copy.
669  *                      This function returned due the driver's circular buffer
670  *                      is full. Caller should invoke this function again as
671  *                      soon as there is space in driver's circular buffer.
672  *         false,       Device's buffer is empty.
673  */
674 static inline bool fw_log_copy(struct tegra_xhci_hcd *tegra)
675 {
676         struct device *dev = &tegra->pdev->dev;
677         struct circ_buf *circ = &tegra->log.circ;
678         int head, tail;
679         int buffer_len, copy_len;
680         struct log_entry *entry;
681         struct log_entry *first = tegra->log.virt_addr;
682
683         while (fw_log_available(tegra)) {
684
685                 /* calculate maximum contiguous driver buffer length */
686                 head = circ->head;
687                 tail = ACCESS_ONCE(circ->tail);
688                 buffer_len = CIRC_SPACE_TO_END(head, tail, CIRC_BUF_SIZE);
689                 /* round down to FW_LOG_SIZE */
690                 buffer_len -= (buffer_len % FW_LOG_SIZE);
691                 if (!buffer_len)
692                         return true; /* log available but no space left */
693
694                 /* calculate maximum contiguous log copy length */
695                 entry = tegra->log.dequeue;
696                 copy_len = 0;
697                 do {
698                         if (tegra->log.seq != entry->sequence_no) {
699                                 dev_warn(dev,
700                                 "%s: discontinuous seq no, expect %u get %u\n",
701                                 __func__, tegra->log.seq, entry->sequence_no);
702                         }
703                         tegra->log.seq = entry->sequence_no + 1;
704
705                         copy_len += FW_LOG_SIZE;
706                         buffer_len -= FW_LOG_SIZE;
707                         if (!buffer_len)
708                                 break; /* no space left */
709                         entry = fw_log_next(&tegra->log, entry);
710                 } while ((entry->owner == DRIVER) && (entry != first));
711
712                 memcpy(&circ->buf[head], tegra->log.dequeue, copy_len);
713                 memset(tegra->log.dequeue, 0, copy_len);
714                 circ->head = (circ->head + copy_len) & (CIRC_BUF_SIZE - 1);
715
716                 mb();
717
718                 fw_log_update_deq_pointer(&tegra->log, copy_len/FW_LOG_SIZE);
719
720                 dev_dbg(dev, "copied %d entries, new dequeue 0x%p\n",
721                                 copy_len/FW_LOG_SIZE, tegra->log.dequeue);
722                 wake_up_interruptible(&tegra->log.read_wait);
723         }
724
725         return false;
726 }
727
728 static int fw_log_thread(void *data)
729 {
730         struct tegra_xhci_hcd *tegra = data;
731         struct device *dev = &tegra->pdev->dev;
732         struct circ_buf *circ = &tegra->log.circ;
733         bool logs_left;
734
735         dev_dbg(dev, "start firmware log thread\n");
736
737         do {
738                 mutex_lock(&tegra->log.mutex);
739                 if (circ_buffer_full(circ)) {
740                         mutex_unlock(&tegra->log.mutex);
741                         dev_info(dev, "%s: circ buffer full\n", __func__);
742                         wait_event_interruptible(tegra->log.write_wait,
743                             kthread_should_stop() || !circ_buffer_full(circ));
744                         mutex_lock(&tegra->log.mutex);
745                 }
746
747                 logs_left = fw_log_copy(tegra);
748                 mutex_unlock(&tegra->log.mutex);
749
750                 /* relax if no logs left  */
751                 if (!logs_left)
752                         wait_event_interruptible_timeout(tegra->log.intr_wait,
753                                 fw_log_available(tegra), FW_LOG_THREAD_RELAX);
754         } while (!kthread_should_stop());
755
756         dev_dbg(dev, "stop firmware log thread\n");
757         return 0;
758 }
759
760 static inline bool circ_buffer_empty(struct circ_buf *circ)
761 {
762         return (CIRC_CNT(circ->head, circ->tail, CIRC_BUF_SIZE) == 0);
763 }
764
765 static ssize_t fw_log_file_read(struct file *file, char __user *buf,
766                 size_t count, loff_t *offp)
767 {
768         struct tegra_xhci_hcd *tegra = file->private_data;
769         struct platform_device *pdev = tegra->pdev;
770         struct circ_buf *circ = &tegra->log.circ;
771         int head, tail;
772         size_t n = 0;
773         int s;
774
775         mutex_lock(&tegra->log.mutex);
776
777         while (circ_buffer_empty(circ)) {
778                 mutex_unlock(&tegra->log.mutex);
779                 if (file->f_flags & O_NONBLOCK)
780                         return -EAGAIN; /* non-blocking read */
781
782                 dev_dbg(&pdev->dev, "%s: nothing to read\n", __func__);
783
784                 if (wait_event_interruptible(tegra->log.read_wait,
785                                 !circ_buffer_empty(circ)))
786                         return -ERESTARTSYS;
787
788                 if (mutex_lock_interruptible(&tegra->log.mutex))
789                         return -ERESTARTSYS;
790         }
791
792         while (count > 0) {
793                 head = ACCESS_ONCE(circ->head);
794                 tail = circ->tail;
795                 s = min_t(int, count,
796                                 CIRC_CNT_TO_END(head, tail, CIRC_BUF_SIZE));
797
798                 if (s > 0) {
799                         if (copy_to_user(&buf[n], &circ->buf[tail], s)) {
800                                 dev_warn(&pdev->dev, "copy_to_user failed\n");
801                                 mutex_unlock(&tegra->log.mutex);
802                                 return -EFAULT;
803                         }
804                         circ->tail = (circ->tail + s) & (CIRC_BUF_SIZE - 1);
805
806                         count -= s;
807                         n += s;
808                 } else
809                         break;
810         }
811
812         mutex_unlock(&tegra->log.mutex);
813
814         wake_up_interruptible(&tegra->log.write_wait);
815
816         dev_dbg(&pdev->dev, "%s: %d bytes\n", __func__, n);
817
818         return n;
819 }
820
821 static int fw_log_file_open(struct inode *inode, struct file *file)
822 {
823         struct tegra_xhci_hcd *tegra;
824         file->private_data = inode->i_private;
825         tegra = file->private_data;
826
827         if (test_and_set_bit(FW_LOG_FILE_OPENED, &tegra->log.flags)) {
828                 dev_info(&tegra->pdev->dev, "%s: already opened\n", __func__);
829                 return -EBUSY;
830         }
831
832         return 0;
833 }
834
835 static int fw_log_file_close(struct inode *inode, struct file *file)
836 {
837         struct tegra_xhci_hcd *tegra = file->private_data;
838
839         clear_bit(FW_LOG_FILE_OPENED, &tegra->log.flags);
840
841         return 0;
842 }
843
844 static const struct file_operations firmware_log_fops = {
845                 .open           = fw_log_file_open,
846                 .release        = fw_log_file_close,
847                 .read           = fw_log_file_read,
848                 .owner          = THIS_MODULE,
849 };
850
851 static int fw_log_init(struct tegra_xhci_hcd *tegra)
852 {
853         struct platform_device *pdev = tegra->pdev;
854         int rc = 0;
855
856         /* allocate buffer to be shared between driver and firmware */
857         tegra->log.virt_addr = dma_alloc_writecombine(&pdev->dev,
858                         FW_LOG_RING_SIZE, &tegra->log.phys_addr, GFP_KERNEL);
859
860         if (!tegra->log.virt_addr) {
861                 dev_err(&pdev->dev, "dma_alloc_writecombine() size %d failed\n",
862                                 FW_LOG_RING_SIZE);
863                 return -ENOMEM;
864         }
865
866         dev_info(&pdev->dev, "%d bytes log buffer physical 0x%u virtual 0x%p\n",
867                 FW_LOG_RING_SIZE, tegra->log.phys_addr, tegra->log.virt_addr);
868
869         memset(tegra->log.virt_addr, 0, FW_LOG_RING_SIZE);
870         tegra->log.dequeue = tegra->log.virt_addr;
871
872         tegra->log.circ.buf = vmalloc(CIRC_BUF_SIZE);
873         if (!tegra->log.circ.buf) {
874                 dev_err(&pdev->dev, "vmalloc size %d failed\n", CIRC_BUF_SIZE);
875                 rc = -ENOMEM;
876                 goto error_free_dma;
877         }
878
879         tegra->log.circ.head = 0;
880         tegra->log.circ.tail = 0;
881
882         init_waitqueue_head(&tegra->log.read_wait);
883         init_waitqueue_head(&tegra->log.write_wait);
884         init_waitqueue_head(&tegra->log.intr_wait);
885
886         mutex_init(&tegra->log.mutex);
887
888         tegra->log.path = debugfs_create_dir("tegra_xhci", NULL);
889         if (IS_ERR_OR_NULL(tegra->log.path)) {
890                 dev_warn(&pdev->dev, "debugfs_create_dir() failed\n");
891                 rc = -ENOMEM;
892                 goto error_free_mem;
893         }
894
895         tegra->log.log_file = debugfs_create_file("firmware_log",
896                         S_IRUGO, tegra->log.path, tegra, &firmware_log_fops);
897         if ((!tegra->log.log_file) ||
898                         (tegra->log.log_file == ERR_PTR(-ENODEV))) {
899                 dev_warn(&pdev->dev, "debugfs_create_file() failed\n");
900                 rc = -ENOMEM;
901                 goto error_remove_debugfs_path;
902         }
903
904         tegra->log.thread = kthread_run(fw_log_thread, tegra, "xusb-fw-log");
905         if (IS_ERR(tegra->log.thread)) {
906                 dev_warn(&pdev->dev, "kthread_run() failed\n");
907                 rc = -ENOMEM;
908                 goto error_remove_debugfs_file;
909         }
910
911         set_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags);
912         return rc;
913
914 error_remove_debugfs_file:
915         debugfs_remove(tegra->log.log_file);
916 error_remove_debugfs_path:
917         debugfs_remove(tegra->log.path);
918 error_free_mem:
919         vfree(tegra->log.circ.buf);
920 error_free_dma:
921         dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
922                         tegra->log.virt_addr, tegra->log.phys_addr);
923         memset(&tegra->log, sizeof(tegra->log), 0);
924         return rc;
925 }
926
927 static void fw_log_deinit(struct tegra_xhci_hcd *tegra)
928 {
929         struct platform_device *pdev = tegra->pdev;
930
931         if (test_and_clear_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
932
933                 debugfs_remove(tegra->log.log_file);
934                 debugfs_remove(tegra->log.path);
935
936                 wake_up_interruptible(&tegra->log.read_wait);
937                 wake_up_interruptible(&tegra->log.write_wait);
938                 kthread_stop(tegra->log.thread);
939
940                 mutex_lock(&tegra->log.mutex);
941                 dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
942                         tegra->log.virt_addr, tegra->log.phys_addr);
943                 vfree(tegra->log.circ.buf);
944                 tegra->log.circ.head = tegra->log.circ.tail = 0;
945                 mutex_unlock(&tegra->log.mutex);
946
947                 mutex_destroy(&tegra->log.mutex);
948         }
949 }
950
951 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
952 {
953         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
954         struct xhci_hcd *xhci = tegra->xhci;
955         u32 reg;
956
957         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
958         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
959         xhci_info(xhci, " PAD MUX = %x\n", reg);
960         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
961         xhci_info(xhci, " PORT CAP = %x\n", reg);
962         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
963         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
964         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
965         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
966         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
967         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
968         reg = readl(tegra->padctl_base + padregs->oc_det_0);
969         xhci_info(xhci, " OC DET 0= %x\n", reg);
970         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad0_ctl2_0);
971         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
972         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad1_ctl2_0);
973         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
974         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl0_0);
975         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
976         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl0_0);
977         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
978         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl1_0);
979         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
980         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl1_0);
981         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
982         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
983         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
984         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad0_ctl0_0);
985         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
986         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad1_ctl0_0);
987         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
988         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
989 }
990
991 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
992 {
993         u32 reg;
994
995         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
996         reg |= IPFS_EN_FPCI;
997         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
998         udelay(10);
999
1000         /* Program Bar0 Space */
1001         reg = readl(tegra->fpci_base + XUSB_CFG_4);
1002         reg |= tegra->host_phy_base;
1003         writel(reg, tegra->fpci_base + XUSB_CFG_4);
1004         usleep_range(100, 200);
1005
1006         /* Enable Bus Master */
1007         reg = readl(tegra->fpci_base + XUSB_CFG_1);
1008         reg |= 0x7;
1009         writel(reg, tegra->fpci_base + XUSB_CFG_1);
1010
1011         /* Set intr mask to enable intr assertion */
1012         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1013         reg |= IPFS_IP_INT_MASK;
1014         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1015
1016         /* Set hysteris to 0x80 */
1017         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1018 }
1019
1020 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
1021                 struct platform_device *pdev)
1022 {
1023         struct tegra_xusb_regulator_name *supply = &tegra->bdata->supply;
1024         int err = 0;
1025
1026         tegra->xusb_s3p3v_reg =
1027                         devm_regulator_get(&pdev->dev, supply->s3p3v);
1028         if (IS_ERR(tegra->xusb_s3p3v_reg)) {
1029                 dev_err(&pdev->dev, "3p3v: regulator not found: %ld."
1030                         , PTR_ERR(tegra->xusb_s3p3v_reg));
1031                 err = PTR_ERR(tegra->xusb_s3p3v_reg);
1032                 goto err_null_regulator;
1033         } else {
1034                 err = regulator_enable(tegra->xusb_s3p3v_reg);
1035                 if (err < 0) {
1036                         dev_err(&pdev->dev,
1037                                 "3p3v: regulator enable failed:%d\n", err);
1038                         goto err_null_regulator;
1039                 }
1040         }
1041
1042         tegra->xusb_s5p0v_reg = devm_regulator_get(&pdev->dev, supply->s5p0v);
1043         if (IS_ERR(tegra->xusb_s5p0v_reg)) {
1044                 dev_err(&pdev->dev, "5p0v regulator not found: %ld."
1045                         , PTR_ERR(tegra->xusb_s5p0v_reg));
1046                 err = PTR_ERR(tegra->xusb_s5p0v_reg);
1047                 goto err_put_s3p3v_reg;
1048         } else {
1049                 err = regulator_enable(tegra->xusb_s5p0v_reg);
1050                 if (err < 0) {
1051                         dev_err(&pdev->dev,
1052                                 "5p0v: regulator enable failed:%d\n", err);
1053                         goto err_put_s3p3v_reg;
1054                 }
1055         }
1056
1057         tegra->xusb_s1p8v_reg =
1058                 devm_regulator_get(&pdev->dev, supply->s1p8v);
1059         if (IS_ERR(tegra->xusb_s1p8v_reg)) {
1060                 dev_err(&pdev->dev, "1p8v regulator not found: %ld."
1061                         , PTR_ERR(tegra->xusb_s1p8v_reg));
1062                 err = PTR_ERR(tegra->xusb_s1p8v_reg);
1063                 goto err_put_s5p0v_reg;
1064         } else {
1065                 err = regulator_enable(tegra->xusb_s1p8v_reg);
1066                 if (err < 0) {
1067                         dev_err(&pdev->dev,
1068                         "1p8v: regulator enable failed:%d\n", err);
1069                         goto err_put_s5p0v_reg;
1070                 }
1071         }
1072
1073         tegra->xusb_s1p05v_reg =
1074                         devm_regulator_get(&pdev->dev, supply->s1p05v);
1075         if (IS_ERR(tegra->xusb_s1p05v_reg)) {
1076                 dev_err(&pdev->dev, "1p05v: regulator not found: %ld."
1077                         , PTR_ERR(tegra->xusb_s1p05v_reg));
1078                 err = PTR_ERR(tegra->xusb_s1p05v_reg);
1079                 goto err_put_s1p8v_reg;
1080         } else {
1081                 err = regulator_enable(tegra->xusb_s1p05v_reg);
1082                 if (err < 0) {
1083                         dev_err(&pdev->dev,
1084                         "1p05v: regulator enable failed:%d\n", err);
1085                         goto err_put_s1p8v_reg;
1086                 }
1087         }
1088
1089         if (tegra->bdata->uses_different_vbus_per_port) {
1090                 tegra->xusb_s5p0v1_reg = devm_regulator_get(&pdev->dev,
1091                                                 supply->s5p0v1);
1092                 if (IS_ERR(tegra->xusb_s5p0v1_reg)) {
1093                         dev_err(&pdev->dev, "5p0v1 regulator not found: %ld."
1094                                 , PTR_ERR(tegra->xusb_s5p0v1_reg));
1095                         err = PTR_ERR(tegra->xusb_s5p0v1_reg);
1096                         goto err_put_s1p05v_reg;
1097                 } else {
1098                         err = regulator_enable(tegra->xusb_s5p0v1_reg);
1099                         if (err < 0) {
1100                                 dev_err(&pdev->dev,
1101                                 "5p0v1: regulator enable failed:%d\n", err);
1102                                 goto err_put_s1p05v_reg;
1103                         }
1104                 }
1105
1106                 tegra->xusb_s5p0v2_reg = devm_regulator_get(&pdev->dev,
1107                                                 supply->s5p0v2);
1108                 if (IS_ERR(tegra->xusb_s5p0v2_reg)) {
1109                         dev_err(&pdev->dev, "5p0v2 regulator not found: %ld."
1110                                 , PTR_ERR(tegra->xusb_s5p0v2_reg));
1111                         err = PTR_ERR(tegra->xusb_s5p0v2_reg);
1112                         goto err_put_s1p5v1_reg;
1113                 } else {
1114                         err = regulator_enable(tegra->xusb_s5p0v2_reg);
1115                         if (err < 0) {
1116                                 dev_err(&pdev->dev,
1117                                 "5p0v2: regulator enable failed:%d\n", err);
1118                                 goto err_put_s1p5v1_reg;
1119                         }
1120                 }
1121         }
1122         return err;
1123
1124 err_put_s1p5v1_reg:
1125         if (tegra->bdata->uses_different_vbus_per_port)
1126                 regulator_disable(tegra->xusb_s5p0v1_reg);
1127 err_put_s1p05v_reg:
1128         regulator_disable(tegra->xusb_s1p05v_reg);
1129 err_put_s1p8v_reg:
1130         regulator_disable(tegra->xusb_s1p8v_reg);
1131 err_put_s5p0v_reg:
1132         regulator_disable(tegra->xusb_s5p0v_reg);
1133 err_put_s3p3v_reg:
1134         regulator_disable(tegra->xusb_s3p3v_reg);
1135 err_null_regulator:
1136         tegra->xusb_s5p0v_reg = NULL;
1137         tegra->xusb_s5p0v1_reg = NULL;
1138         tegra->xusb_s5p0v2_reg = NULL;
1139         tegra->xusb_s1p05v_reg = NULL;
1140         tegra->xusb_s3p3v_reg = NULL;
1141         tegra->xusb_s1p8v_reg = NULL;
1142         return err;
1143 }
1144
1145 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
1146 {
1147         regulator_disable(tegra->xusb_s1p05v_reg);
1148         regulator_disable(tegra->xusb_s1p8v_reg);
1149         regulator_disable(tegra->xusb_s5p0v_reg);
1150         regulator_disable(tegra->xusb_s3p3v_reg);
1151         if (tegra->bdata->uses_different_vbus_per_port) {
1152                 regulator_disable(tegra->xusb_s5p0v1_reg);
1153                 regulator_disable(tegra->xusb_s5p0v2_reg);
1154         }
1155
1156         tegra->xusb_s1p05v_reg = NULL;
1157         tegra->xusb_s1p8v_reg = NULL;
1158         tegra->xusb_s5p0v_reg = NULL;
1159         tegra->xusb_s5p0v1_reg = NULL;
1160         tegra->xusb_s5p0v2_reg = NULL;
1161         tegra->xusb_s3p3v_reg = NULL;
1162 }
1163
1164 /*
1165  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
1166  * are under hardware control
1167  */
1168 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
1169 {
1170         struct platform_device *pdev = tegra->pdev;
1171         int err = 0;
1172
1173         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
1174         if (IS_ERR(tegra->plle_clk)) {
1175                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
1176                 err = PTR_ERR(tegra->plle_clk);
1177                 return err;
1178         }
1179         err = clk_enable(tegra->plle_clk);
1180         if (err) {
1181                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
1182                         __func__);
1183                 return err;
1184         }
1185
1186         return err;
1187 }
1188
1189 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
1190 {
1191         clk_disable(tegra->plle_clk);
1192         tegra->plle_clk = NULL;
1193 }
1194
1195 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
1196 {
1197         struct platform_device *pdev = tegra->pdev;
1198         int err = 0;
1199
1200         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
1201         if (IS_ERR(tegra->emc_clk)) {
1202                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
1203                 return PTR_ERR(tegra->emc_clk);
1204         }
1205
1206         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1207                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
1208                 if (IS_ERR(tegra->pll_re_vco_clk)) {
1209                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
1210                         err = PTR_ERR(tegra->pll_re_vco_clk);
1211                         goto get_pll_re_vco_clk_failed;
1212                 }
1213         }
1214
1215         /* get the clock handle of 120MHz clock source */
1216         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
1217         if (IS_ERR(tegra->pll_u_480M)) {
1218                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
1219                 err = PTR_ERR(tegra->pll_u_480M);
1220                 goto get_pll_u_480M_failed;
1221         }
1222
1223         /* get the clock handle of 12MHz clock source */
1224         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1225         if (IS_ERR(tegra->clk_m)) {
1226                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
1227                 err = PTR_ERR(tegra->clk_m);
1228                 goto clk_get_clk_m_failed;
1229         }
1230
1231         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
1232         if (IS_ERR(tegra->ss_src_clk)) {
1233                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
1234                 err = PTR_ERR(tegra->ss_src_clk);
1235                 tegra->ss_src_clk = NULL;
1236                 goto get_ss_src_clk_failed;
1237         }
1238
1239         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
1240         if (IS_ERR(tegra->host_clk)) {
1241                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
1242                 err = PTR_ERR(tegra->host_clk);
1243                 tegra->host_clk = NULL;
1244                 goto get_host_clk_failed;
1245         }
1246
1247         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
1248         if (IS_ERR(tegra->ss_clk)) {
1249                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
1250                 err = PTR_ERR(tegra->ss_clk);
1251                 tegra->ss_clk = NULL;
1252                 goto get_ss_clk_failed;
1253         }
1254
1255         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1256                 err = clk_enable(tegra->pll_re_vco_clk);
1257                 if (err) {
1258                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
1259                         goto enable_pll_re_vco_clk_failed;
1260                 }
1261         }
1262         /* enable ss clock */
1263         err = clk_enable(tegra->host_clk);
1264         if (err) {
1265                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
1266                 goto enable_host_clk_failed;
1267         }
1268
1269         err = clk_enable(tegra->ss_clk);
1270         if (err) {
1271                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
1272                 goto eanble_ss_clk_failed;
1273         }
1274
1275         err = clk_enable(tegra->emc_clk);
1276         if (err) {
1277                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
1278                 goto eanble_emc_clk_failed;
1279         }
1280
1281         return 0;
1282
1283 eanble_emc_clk_failed:
1284         clk_disable(tegra->ss_clk);
1285
1286 eanble_ss_clk_failed:
1287         clk_disable(tegra->host_clk);
1288
1289 enable_host_clk_failed:
1290         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1291                 clk_disable(tegra->pll_re_vco_clk);
1292
1293 enable_pll_re_vco_clk_failed:
1294         tegra->ss_clk = NULL;
1295
1296 get_ss_clk_failed:
1297         tegra->host_clk = NULL;
1298
1299 get_host_clk_failed:
1300         tegra->ss_src_clk = NULL;
1301
1302 get_ss_src_clk_failed:
1303         tegra->clk_m = NULL;
1304
1305 clk_get_clk_m_failed:
1306         tegra->pll_u_480M = NULL;
1307
1308 get_pll_u_480M_failed:
1309         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1310                 tegra->pll_re_vco_clk = NULL;
1311
1312 get_pll_re_vco_clk_failed:
1313         tegra->emc_clk = NULL;
1314
1315         return err;
1316 }
1317
1318 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
1319 {
1320         clk_disable(tegra->ss_clk);
1321         clk_disable(tegra->host_clk);
1322         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1323                 clk_disable(tegra->pll_re_vco_clk);
1324         tegra->ss_clk = NULL;
1325         tegra->host_clk = NULL;
1326         tegra->ss_src_clk = NULL;
1327         tegra->clk_m = NULL;
1328         tegra->pll_u_480M = NULL;
1329         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1330                 tegra->pll_re_vco_clk = NULL;
1331 }
1332
1333 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
1334         bool enable)
1335 {
1336         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1337         u32 reg;
1338
1339         /* Issue is only applicable for T114 */
1340         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
1341                 return;
1342
1343         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1344                 reg = readl(tegra->padctl_base +
1345                         padregs->iophy_misc_pad_p0_ctl3_0);
1346                 if (enable) {
1347                         reg &= ~RX_IDLE_MODE;
1348                         reg |= RX_IDLE_MODE_OVRD;
1349                 } else {
1350                         reg |= RX_IDLE_MODE;
1351                         reg &= ~RX_IDLE_MODE_OVRD;
1352                 }
1353                 writel(reg, tegra->padctl_base +
1354                         padregs->iophy_misc_pad_p0_ctl3_0);
1355         }
1356
1357         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1358                 reg = readl(tegra->padctl_base +
1359                         padregs->iophy_misc_pad_p1_ctl3_0);
1360                 if (enable) {
1361                         reg &= ~RX_IDLE_MODE;
1362                         reg |= RX_IDLE_MODE_OVRD;
1363                 } else {
1364                         reg |= RX_IDLE_MODE;
1365                         reg &= ~RX_IDLE_MODE_OVRD;
1366                 }
1367                 writel(reg, tegra->padctl_base +
1368                         padregs->iophy_misc_pad_p1_ctl3_0);
1369
1370                 /* SATA lane also if USB3_SS port1 mapped to it */
1371                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
1372                                 tegra->bdata->lane_owner & BIT(0)) {
1373                         reg = readl(tegra->padctl_base +
1374                                 padregs->iophy_misc_pad_s0_ctl3_0);
1375                         if (enable) {
1376                                 reg &= ~RX_IDLE_MODE;
1377                                 reg |= RX_IDLE_MODE_OVRD;
1378                         } else {
1379                                 reg |= RX_IDLE_MODE;
1380                                 reg &= ~RX_IDLE_MODE_OVRD;
1381                         }
1382                         writel(reg, tegra->padctl_base +
1383                                 padregs->iophy_misc_pad_s0_ctl3_0);
1384                 }
1385         }
1386 }
1387
1388 /* Enable ss clk, host clk, falcon clk,
1389  * fs clk, dev clk, plle and refplle
1390  */
1391
1392 static int
1393 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
1394                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
1395 {
1396         int ret = 0;
1397         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
1398         int fw_req_rate = rate, cur_rate;
1399
1400         /* Do not handle clock change as needed for HS disconnect issue */
1401         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1402                 *sw_resp = fw_req_rate | (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
1403                 return ret;
1404         }
1405
1406         /* frequency request from firmware is in KHz.
1407          * Convert it to MHz
1408          */
1409
1410         /* get current rate of clock */
1411         cur_rate = clk_get_rate(clk_handle);
1412         cur_rate /= 1000;
1413
1414         if (fw_req_rate == cur_rate) {
1415                 cmd_ack = MBOX_CMD_ACK;
1416                 *sw_resp = fw_req_rate;
1417         } else {
1418
1419                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
1420                         /* Change SS clock source to CLK_M at 12MHz */
1421                         clk_set_parent(clk_handle, tegra->clk_m);
1422                         clk_set_rate(clk_handle, fw_req_rate * 1000);
1423
1424                         /* save leakage power when SS freq is being decreased */
1425                         tegra_xhci_rx_idle_mode_override(tegra, true);
1426                 } else if (clk_handle == tegra->ss_src_clk &&
1427                                 fw_req_rate == 120000) {
1428                         /* Change SS clock source to HSIC_480 at 120MHz */
1429                         clk_set_rate(clk_handle,  3000 * 1000);
1430                         clk_set_parent(clk_handle, tegra->pll_u_480M);
1431
1432                         /* clear ovrd bits when SS freq is being increased */
1433                         tegra_xhci_rx_idle_mode_override(tegra, false);
1434                 }
1435
1436                 *sw_resp = clk_get_rate(clk_handle);
1437                 *sw_resp /= 1000;
1438
1439                 if (*sw_resp != fw_req_rate) {
1440                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
1441                                 cur_rate, fw_req_rate);
1442                         cmd_ack = MBOX_CMD_NACK;
1443                 }
1444         }
1445         *sw_resp |= (cmd_ack << MBOX_CMD_SHIFT);
1446         return ret;
1447 }
1448
1449 static void tegra_xhci_save_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
1450         u8 port)
1451 {
1452         struct xhci_hcd *xhci = tegra->xhci;
1453         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1454         u32 offset;
1455         u32 reg;
1456
1457         xhci_info(xhci, "saving dfe_cntl and ctle context for port %d\n", port);
1458
1459         if (port == 3 /* SATA pad */)
1460                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1461         else
1462                 offset = port ? padregs->iophy_misc_pad_p1_ctl6_0 :
1463                                 padregs->iophy_misc_pad_p0_ctl6_0;
1464
1465         /* save tap1_val[] for the port for dfe_cntl */
1466         reg = readl(tegra->padctl_base + offset);
1467         reg &= ~(0xff << 16);
1468         reg |= (0x32 << 16);
1469         writel(reg, tegra->padctl_base + offset);
1470
1471         reg = readl(tegra->padctl_base + offset);
1472         tegra->sregs.tap1_val[port] = ((reg & (0x1f << 24)) >> 24);
1473
1474         /* save amp_val[] for the port for dfe_cntl */
1475         reg = readl(tegra->padctl_base + offset);
1476         reg &= ~(0xff << 16);
1477         reg |= (0x33 << 16);
1478         writel(reg, tegra->padctl_base + offset);
1479
1480         reg = readl(tegra->padctl_base + offset);
1481         tegra->sregs.amp_val[port] = ((reg & (0x7f << 24)) >> 24);
1482
1483         /* save ctle_z_val[] for the port for ctle */
1484         reg = readl(tegra->padctl_base + offset);
1485         reg &= ~(0xff << 16);
1486         reg |= (0x20 << 16);
1487         writel(reg, tegra->padctl_base + offset);
1488
1489         reg = readl(tegra->padctl_base + offset);
1490         tegra->sregs.ctle_z_val[port] = ((reg & (0x3f << 24)) >> 24);
1491
1492         /* save ctle_g_val[] for the port for ctle */
1493         reg = readl(tegra->padctl_base + offset);
1494         reg &= ~(0xff << 16);
1495         reg |= (0x21 << 16);
1496         writel(reg, tegra->padctl_base + offset);
1497
1498         reg = readl(tegra->padctl_base + offset);
1499         tegra->sregs.ctle_g_val[port] = ((reg & (0x3f << 24)) >> 24);
1500         tegra->dfe_ctle_ctx_saved = true;
1501 }
1502
1503 static void tegra_xhci_restore_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
1504         u8 port)
1505 {
1506         struct xhci_hcd *xhci = tegra->xhci;
1507         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1508         u32 ctl4_offset, ctl2_offset;
1509         u32 reg;
1510
1511         /* don't restore if not saved */
1512         if (tegra->dfe_ctle_ctx_saved == false)
1513                 return;
1514
1515         if (port == 3 /* SATA pad */) {
1516                 ctl4_offset = padregs->iophy_misc_pad_s0_ctl4_0;
1517                 ctl2_offset = padregs->iophy_misc_pad_s0_ctl2_0;
1518         } else {
1519                 ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1520                                 padregs->iophy_usb3_pad0_ctl4_0;
1521                 ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1522                                 padregs->iophy_usb3_pad0_ctl2_0;
1523         }
1524
1525         xhci_info(xhci, "restoring dfe_cntl/ctle context of port %d\n", port);
1526
1527         /* restore dfe_cntl for the port */
1528         reg = readl(tegra->padctl_base + ctl4_offset);
1529         reg &= ~((0x7f << 16) | (0x1f << 24));
1530         reg |= ((tegra->sregs.amp_val[port] << 16) |
1531                 (tegra->sregs.tap1_val[port] << 24));
1532         writel(reg, tegra->padctl_base + ctl4_offset);
1533
1534         /* restore ctle for the port */
1535         reg = readl(tegra->padctl_base + ctl2_offset);
1536         reg &= ~((0x3f << 8) | (0x3f << 16));
1537         reg |= ((tegra->sregs.ctle_g_val[port] << 8) |
1538                 (tegra->sregs.ctle_z_val[port] << 16));
1539         writel(reg, tegra->padctl_base + ctl2_offset);
1540 }
1541
1542 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
1543         u8 port)
1544 {
1545         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1546         u32 reg;
1547
1548         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1549         reg &= ~USB2_ULPI_PAD;
1550         reg |= USB2_ULPI_PAD_OWNER_XUSB;
1551         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1552
1553         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1554         reg &= ~USB2_ULPI_PORT_CAP;
1555         reg |= (tegra->bdata->ulpicap << 24);
1556         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1557         /* FIXME: Program below when more details available
1558          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
1559          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
1560          */
1561 }
1562
1563 static void tegra_xhci_program_hsic_pad(struct tegra_xhci_hcd *tegra,
1564         u8 port)
1565 {
1566         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1567         u32 ctl0_offset;
1568         u32 reg;
1569
1570         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1571         reg &= ~(port ? USB2_HSIC_PAD_PORT1 : USB2_HSIC_PAD_PORT0);
1572         reg |= port ? USB2_HSIC_PAD_P1_OWNER_XUSB :
1573                         USB2_HSIC_PAD_P0_OWNER_XUSB;
1574         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1575
1576         ctl0_offset = port ? padregs->usb2_hsic_pad1_ctl0_0 :
1577                         padregs->usb2_hsic_pad0_ctl0_0;
1578
1579         reg = readl(tegra->padctl_base + ctl0_offset);
1580         reg &= ~(HSIC_TX_SLEWP | HSIC_TX_SLEWN);
1581         writel(reg, tegra->padctl_base + ctl0_offset);
1582
1583         /* FIXME Program below when more details available
1584          * XUSB_PADCTL_HSIC_PAD0_CTL_0_0
1585          * XUSB_PADCTL_HSIC_PAD0_CTL_1_0
1586          * XUSB_PADCTL_HSIC_PAD0_CTL_2_0
1587          * XUSB_PADCTL_HSIC_PAD1_CTL_0_0
1588          * XUSB_PADCTL_HSIC_PAD1_CTL_1_0
1589          * XUSB_PADCTL_HSIC_PAD1_CTL_2_0
1590          * XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL_0
1591          */
1592 }
1593
1594 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
1595         u8 port)
1596 {
1597         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1598         u32 reg;
1599         u32 ctl0_offset, ctl1_offset;
1600
1601         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1602         reg &= ~USB2_OTG_PAD_PORT_MASK(port);
1603         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
1604         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1605
1606         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1607         reg &= ~USB2_PORT_CAP_MASK(port);
1608         reg |= USB2_PORT_CAP_HOST(port);
1609         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1610
1611         /*
1612          * Modify only the bits which belongs to the port
1613          * and enable respective VBUS_PAD for the port
1614          */
1615         if (tegra->bdata->uses_external_pmic == false) {
1616                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1617                 reg &= ~(port == 2 ? OC_DET_VBUS_ENABLE2_OC_MAP :
1618                         port ? OC_DET_VBUS_ENABLE1_OC_MAP :
1619                                 OC_DET_VBUS_ENABLE0_OC_MAP);
1620
1621                 reg |= (port == 2) ? OC_DET_VBUS_EN2_OC_DETECTED_VBUS_PAD2 :
1622                         port ? OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1 :
1623                                 OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0;
1624                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1625         }
1626         /*
1627          * enable respective VBUS_PAD if port is mapped to any SS port
1628          */
1629         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1630         reg &= ~((port == 2) ? USB2_OC_MAP_PORT2 :
1631                 port ? USB2_OC_MAP_PORT1 : USB2_OC_MAP_PORT0);
1632         reg |= (0x4 | port) << (port * 3);
1633         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1634
1635         ctl0_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl0_0 :
1636                         port ? padregs->usb2_otg_pad1_ctl0_0 :
1637                                 padregs->usb2_otg_pad0_ctl0_0;
1638         ctl1_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl1_0 :
1639                         port ? padregs->usb2_otg_pad1_ctl1_0 :
1640                                 padregs->usb2_otg_pad0_ctl1_0;
1641
1642         reg = readl(tegra->padctl_base + ctl0_offset);
1643         reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
1644                 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
1645                 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
1646
1647         reg |= tegra->pdata->hs_slew;
1648         reg |= (port == 2) ? tegra->pdata->ls_rslew_pad2 :
1649                         port ? tegra->pdata->ls_rslew_pad1 :
1650                         tegra->pdata->ls_rslew_pad0;
1651         reg |= (port == 2) ? tegra->pdata->hs_curr_level_pad2 :
1652                         port ? tegra->pdata->hs_curr_level_pad1 :
1653                         tegra->pdata->hs_curr_level_pad0;
1654         writel(reg, tegra->padctl_base + ctl0_offset);
1655
1656         reg = readl(tegra->padctl_base + ctl1_offset);
1657         reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
1658                 | USB2_OTG_PD_CHRP_FORCE_POWERUP
1659                 | USB2_OTG_PD_DISC_FORCE_POWERUP
1660                 | USB2_OTG_PD_DR);
1661         reg |= (tegra->pdata->hs_iref_cap << 9) |
1662                 (tegra->pdata->hs_term_range_adj << 3);
1663         writel(reg, tegra->padctl_base + ctl1_offset);
1664 }
1665
1666 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
1667         u8 port)
1668 {
1669         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1670         u32 ctl2_offset, ctl4_offset, ctl5_offset;
1671         u32 reg;
1672
1673         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1674                         padregs->iophy_usb3_pad0_ctl2_0;
1675         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1676                         padregs->iophy_usb3_pad0_ctl4_0;
1677         ctl5_offset = port ? padregs->iophy_misc_pad_p1_ctl5_0 :
1678                         padregs->iophy_misc_pad_p0_ctl5_0;
1679
1680         reg = readl(tegra->padctl_base + ctl2_offset);
1681         reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
1682                 IOPHY_USB3_CDRCNTL);
1683         reg |= tegra->pdata->rx_wander | tegra->pdata->rx_eq |
1684                 tegra->pdata->cdr_cntl;
1685         writel(reg, tegra->padctl_base + ctl2_offset);
1686
1687         reg = readl(tegra->padctl_base + ctl4_offset);
1688         reg = tegra->pdata->dfe_cntl;
1689         writel(reg, tegra->padctl_base + ctl4_offset);
1690
1691         reg = readl(tegra->padctl_base + ctl5_offset);
1692         reg |= RX_QEYE_EN;
1693         writel(reg, tegra->padctl_base + ctl5_offset);
1694
1695         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1696         reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
1697         reg |= (tegra->bdata->ss_portmap &
1698                 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
1699         writel(reg, tegra->padctl_base + padregs->ss_port_map_0);
1700
1701         tegra_xhci_restore_dfe_ctle_context(tegra, port);
1702         /* SATA also if USB3_SS port1 mapped to it */
1703         if ((port == 1) && (XUSB_DEVICE_ID_T114 != tegra->device_id) &&
1704                         (tegra->bdata->lane_owner & BIT(0)))
1705                 tegra_xhci_restore_dfe_ctle_context(tegra, 3);
1706 }
1707
1708 /* This function assigns the USB ports to the controllers,
1709  * then programs the port capabilities and pad parameters
1710  * of ports assigned to XUSB after booted to OS.
1711  */
1712 void
1713 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
1714 {
1715         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1716         u32 reg, oc_bits = 0;
1717
1718         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1719         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
1720         reg |= tegra->pdata->hs_squelch_level | tegra->pdata->hs_disc_lvl;
1721         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1722
1723         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1724         reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3;
1725         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
1726         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1727
1728         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1729         reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
1730         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1731                 reg |= OC_DET_VBUS_ENABLE2_OC_MAP;
1732         writel(reg, tegra->padctl_base + padregs->oc_det_0);
1733
1734         /* check if over current seen. Clear if present */
1735         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1736                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
1737         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1738                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
1739         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1740                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
1741
1742         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1743         if (reg & oc_bits) {
1744                 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
1745                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1746
1747                 usleep_range(100, 200);
1748
1749                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1750                 if (reg & oc_bits)
1751                         xhci_info(tegra->xhci, "Over current still present\n");
1752         }
1753
1754         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1755         reg = USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1;
1756         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1757                 reg |= USB2_OC_MAP_PORT2;
1758         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1759
1760         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1761                 tegra_xhci_program_utmip_pad(tegra, 0);
1762         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1763                 tegra_xhci_program_utmip_pad(tegra, 1);
1764         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1765                 tegra_xhci_program_utmip_pad(tegra, 2);
1766
1767         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
1768                 tegra_xhci_program_ulpi_pad(tegra, 0);
1769
1770         if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P0)
1771                 tegra_xhci_program_hsic_pad(tegra, 0);
1772         if (tegra->bdata->portmap & TEGRA_XUSB_HSIC_P1)
1773                 tegra_xhci_program_hsic_pad(tegra, 1);
1774
1775         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1776                 tegra_xhci_program_ss_pad(tegra, 0);
1777         } else {
1778                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1779                 reg = readl(tegra->padctl_base +
1780                         padregs->iophy_misc_pad_p0_ctl3_0);
1781                 reg &= ~RX_IDLE_MODE;
1782                 reg |= RX_IDLE_MODE_OVRD;
1783                 writel(reg, tegra->padctl_base +
1784                         padregs->iophy_misc_pad_p0_ctl3_0);
1785         }
1786
1787         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1788                 tegra_xhci_program_ss_pad(tegra, 1);
1789         } else {
1790                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1791                 reg = readl(tegra->padctl_base +
1792                         padregs->iophy_misc_pad_p1_ctl3_0);
1793                 reg &= ~RX_IDLE_MODE;
1794                 reg |= RX_IDLE_MODE_OVRD;
1795                 writel(reg, tegra->padctl_base +
1796                         padregs->iophy_misc_pad_p1_ctl3_0);
1797
1798                 /* SATA lane also if USB3_SS port1 mapped to it but unused */
1799                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
1800                                 tegra->bdata->lane_owner & BIT(0)) {
1801                         reg = readl(tegra->padctl_base +
1802                                 padregs->iophy_misc_pad_s0_ctl3_0);
1803                         reg &= ~RX_IDLE_MODE;
1804                         reg |= RX_IDLE_MODE_OVRD;
1805                         writel(reg, tegra->padctl_base +
1806                                 padregs->iophy_misc_pad_s0_ctl3_0);
1807                 }
1808         }
1809         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
1810                 tegra_xhci_setup_gpio_for_ss_lane(tegra);
1811                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
1812         }
1813 }
1814
1815 /* This function read XUSB registers and stores in device context */
1816 static void
1817 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
1818 {
1819
1820         /* a. Save the IPFS registers */
1821         tegra->sregs.msi_bar_sz =
1822                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
1823
1824         tegra->sregs.msi_axi_barst =
1825                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
1826
1827         tegra->sregs.msi_fpci_barst =
1828                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
1829
1830         tegra->sregs.msi_vec0 =
1831                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
1832
1833         tegra->sregs.msi_en_vec0 =
1834                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
1835
1836         tegra->sregs.fpci_error_masks =
1837                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
1838
1839         tegra->sregs.intr_mask =
1840                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1841
1842         tegra->sregs.ipfs_intr_enable =
1843                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
1844
1845         tegra->sregs.ufpci_config =
1846                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
1847
1848         tegra->sregs.clkgate_hysteresis =
1849                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1850
1851         tegra->sregs.xusb_host_mccif_fifo_cntrl =
1852                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
1853
1854         /* b. Save the CFG registers */
1855
1856         tegra->sregs.hs_pls =
1857                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
1858
1859         tegra->sregs.fs_pls =
1860                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
1861
1862         tegra->sregs.hs_fs_speed =
1863                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
1864
1865         tegra->sregs.hs_fs_pp =
1866                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
1867
1868         tegra->sregs.cfg_aru =
1869                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
1870
1871         tegra->sregs.cfg_order =
1872                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
1873
1874         tegra->sregs.cfg_fladj =
1875                 readl(tegra->fpci_base + XUSB_CFG_24);
1876
1877         tegra->sregs.cfg_sid =
1878                 readl(tegra->fpci_base + XUSB_CFG_16);
1879 }
1880
1881 /* This function restores XUSB registers from device context */
1882 static void
1883 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
1884 {
1885         /* Restore Cfg registers */
1886         writel(tegra->sregs.hs_pls,
1887                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
1888
1889         writel(tegra->sregs.fs_pls,
1890                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
1891
1892         writel(tegra->sregs.hs_fs_speed,
1893                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
1894
1895         writel(tegra->sregs.hs_fs_pp,
1896                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
1897
1898         writel(tegra->sregs.cfg_aru,
1899                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
1900
1901         writel(tegra->sregs.cfg_order,
1902                 tegra->fpci_base + XUSB_CFG_FPCICFG);
1903
1904         writel(tegra->sregs.cfg_fladj,
1905                 tegra->fpci_base + XUSB_CFG_24);
1906
1907         writel(tegra->sregs.cfg_sid,
1908                 tegra->fpci_base + XUSB_CFG_16);
1909
1910         /* Restore IPFS registers */
1911
1912         writel(tegra->sregs.msi_bar_sz,
1913                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
1914
1915         writel(tegra->sregs.msi_axi_barst,
1916                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
1917
1918         writel(tegra->sregs.msi_fpci_barst,
1919                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
1920
1921         writel(tegra->sregs.msi_vec0,
1922                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
1923
1924         writel(tegra->sregs.msi_en_vec0,
1925                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
1926
1927         writel(tegra->sregs.fpci_error_masks,
1928                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
1929
1930         writel(tegra->sregs.intr_mask,
1931                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1932
1933         writel(tegra->sregs.ipfs_intr_enable,
1934                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
1935
1936         writel(tegra->sregs.ufpci_config,
1937                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
1938
1939         writel(tegra->sregs.clkgate_hysteresis,
1940                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1941
1942         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
1943                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
1944 }
1945
1946 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
1947 {
1948         struct platform_device *pdev = tegra->pdev;
1949         u32 reg, timeout = 0xff, cmd;
1950
1951         mutex_lock(&tegra->mbox_lock);
1952
1953         do {
1954                 writel(MBOX_OWNER_SW,
1955                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
1956                 reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
1957                 usleep_range(10, 20);
1958         } while (reg != MBOX_OWNER_SW && timeout--);
1959
1960         if ((timeout == 0) && (reg != MBOX_OWNER_SW)) {
1961                 dev_err(&pdev->dev, "Failed to set mbox message owner ID\n");
1962                 mutex_unlock(&tegra->mbox_lock);
1963                 return;
1964         }
1965
1966         writel((MBOX_CMD_MSG_ENABLED << MBOX_CMD_SHIFT),
1967                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
1968
1969         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1970         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
1971         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1972
1973         mutex_unlock(&tegra->mbox_lock);
1974 }
1975
1976 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
1977 {
1978         struct platform_device *pdev = tegra->pdev;
1979         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
1980         u32 phys_addr_lo;
1981         u32 HwReg;
1982         u16 nblocks;
1983         time_t fw_time;
1984         struct tm fw_tm;
1985         u8 hc_caplength;
1986         u32 usbsts, count = 0xff;
1987         struct xhci_cap_regs __iomem *cap_regs;
1988         struct xhci_op_regs __iomem *op_regs;
1989
1990         /* enable mbox interrupt */
1991         writel(readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD) | MBOX_INT_EN,
1992                 tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
1993
1994         /* First thing, reset the ARU. By the time we get to
1995          * loading boot code below, reset would be complete.
1996          * alternatively we can busy wait on rst pending bit.
1997          */
1998         /* Don't reset during ELPG/LP0 exit path */
1999         if (resetARU) {
2000                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
2001                 usleep_range(1000, 2000);
2002         }
2003
2004         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
2005                 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
2006                                 csb_read(tegra, XUSB_FALC_CPUCTL));
2007                 return 0;
2008         }
2009
2010         /* update the phys_log_buffer and total_entries here */
2011         cfg_tbl->phys_addr_log_buffer = tegra->log.phys_addr;
2012         cfg_tbl->total_log_entries = FW_LOG_COUNT;
2013
2014         phys_addr_lo = tegra->firmware.dma;
2015         phys_addr_lo += sizeof(struct cfgtbl);
2016
2017         /* Program the size of DFI into ILOAD_ATTR */
2018         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
2019
2020         /* Boot code of the firmware reads the ILOAD_BASE_LO register
2021          * to get to the start of the dfi in system memory.
2022          */
2023         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
2024
2025         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
2026         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
2027
2028         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
2029         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
2030
2031         /* Invalidate L2IMEM. */
2032         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
2033
2034         /* Initiate fetch of Bootcode from system memory into L2IMEM.
2035          * Program BootCode location and size in system memory.
2036          */
2037         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
2038                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
2039                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
2040         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
2041                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
2042                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
2043         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
2044
2045         /* Trigger L2IMEM Load operation. */
2046         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
2047
2048         /* Setup Falcon Auto-fill */
2049         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
2050         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
2051                 nblocks += 1;
2052         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
2053
2054         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
2055         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
2056                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
2057         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
2058
2059         csb_write(tegra, XUSB_FALC_DMACTL, 0);
2060         msleep(50);
2061
2062         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
2063
2064         /* Start Falcon CPU */
2065         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
2066         usleep_range(1000, 2000);
2067
2068         fw_time = cfg_tbl->fwimg_created_time;
2069         time_to_tm(fw_time, 0, &fw_tm);
2070         dev_info(&pdev->dev,
2071                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
2072                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
2073                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
2074                 fw_tm.tm_min, fw_tm.tm_sec,
2075                 csb_read(tegra, XUSB_FALC_CPUCTL));
2076
2077         /* return fail if firmware status is not good */
2078         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
2079                 return -EFAULT;
2080
2081         cap_regs = IO_ADDRESS(tegra->host_phy_base);
2082         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
2083         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
2084
2085         /* wait for USBSTS_CNR to get set */
2086         do {
2087                 usbsts = ioread32(&op_regs->status);
2088         } while ((usbsts & STS_CNR) && count--);
2089
2090         if (!count && (usbsts & STS_CNR)) {
2091                 dev_err(&pdev->dev, "Controller not ready\n");
2092                 return -EFAULT;
2093         }
2094         return 0;
2095 }
2096
2097 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
2098         bool release)
2099 {
2100         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2101         u32 reg;
2102
2103         /* Issue is only applicable for T114 */
2104         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
2105                 return;
2106
2107         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2108         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2109                         USB2_OTG_PAD_PORT_MASK(2));
2110
2111         if (!release) {
2112                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2113                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2114                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2115                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2116                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2117                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2118         }
2119
2120         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2121 }
2122 /* SS ELPG Entry initiated by fw */
2123 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
2124 {
2125         struct xhci_hcd *xhci = tegra->xhci;
2126         u32 ret = 0;
2127
2128         must_have_sync_lock(tegra);
2129
2130         /* This is SS partition ELPG entry
2131          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
2132          */
2133
2134         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
2135          * only if it is sw initiated one
2136          */
2137
2138         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
2139          * SuperSpeed partition ELPG entry via mailbox protocol
2140          */
2141
2142         /* STEP 2: xHCI PEP driver and XUSB device mode driver
2143          * enable the XUSB wakeup interrupts for the SuperSpeed
2144          * and USB2.0 ports assigned to host.Section 4.1 Step 3
2145          */
2146         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2147
2148         /* STEP 3: xHCI PEP driver initiates the signal sequence
2149          * to enable the XUSB SSwake detection logic for the
2150          * SuperSpeed ports assigned to host.Section 4.1 Step 4
2151          */
2152         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, true);
2153
2154         /* STEP 4: System Power Management driver asserts reset
2155          * to XUSB SuperSpeed partition then disables its clocks
2156          */
2157         tegra_periph_reset_assert(tegra->ss_clk);
2158         clk_disable(tegra->ss_clk);
2159
2160         usleep_range(100, 200);
2161
2162         /* STEP 5: System Power Management driver disables the
2163          * XUSB SuperSpeed partition power rails.
2164          */
2165         debug_print_portsc(xhci);
2166
2167         /* tegra_powergate_partition also does partition reset assert */
2168         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
2169         if (ret) {
2170                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
2171                                 __func__);
2172                 /* TODO: error recovery? */
2173         }
2174         tegra->ss_pwr_gated = true;
2175
2176         /* STEP 6: xHCI PEP driver initiates the signal sequence
2177          * to enable the XUSB SSwake detection logic for the
2178          * SuperSpeed ports assigned to host.Section 4.1 Step 7
2179          */
2180         tegra_xhci_ss_vcore(tegra->bdata->portmap, true);
2181
2182         return ret;
2183 }
2184
2185 /* Host ELPG Entry */
2186 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
2187 {
2188         struct xhci_hcd *xhci = tegra->xhci;
2189         u32 ret;
2190
2191         must_have_sync_lock(tegra);
2192
2193         /* If ss is already powergated skip ss ctx save stuff */
2194         if (tegra->ss_pwr_gated) {
2195                 xhci_info(xhci, "%s: SS partition is already powergated\n",
2196                         __func__);
2197         } else {
2198                 ret = tegra_xhci_ss_elpg_entry(tegra);
2199                 if (ret) {
2200                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
2201                                 __func__, ret);
2202                         return ret;
2203                 }
2204         }
2205
2206         /* 1. IS INTR PENDING INT_PENDING=1 ? */
2207
2208         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
2209         tegra_xhci_save_xusb_ctx(tegra);
2210
2211         pmc_init(tegra, 1);
2212
2213         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2214         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2215                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2216
2217         /* STEP 4: Assert reset to host clk and disable host clk */
2218         tegra_periph_reset_assert(tegra->host_clk);
2219
2220         clk_disable(tegra->host_clk);
2221
2222         /* wait 150us */
2223         usleep_range(150, 200);
2224
2225         /* flush MC client of XUSB_HOST */
2226         tegra_powergate_mc_flush(TEGRA_POWERGATE_XUSBC);
2227
2228         /* STEP 4: Powergate host partition */
2229         /* tegra_powergate_partition also does partition reset assert */
2230         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
2231         if (ret) {
2232                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2233                         __func__, ret);
2234                 /* TODO: error handling? */
2235                 return ret;
2236         }
2237         tegra->host_pwr_gated = true;
2238
2239         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2240                 clk_disable(tegra->pll_re_vco_clk);
2241         clk_disable(tegra->emc_clk);
2242         /* set port ownership to SNPS */
2243         tegra_xhci_release_port_ownership(tegra, true);
2244
2245         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2246                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2247
2248         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
2249         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
2250                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
2251         return ret;
2252 }
2253
2254 /* SS ELPG Exit triggered by PADCTL irq */
2255 /**
2256  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
2257  *
2258  * This function must be called with tegra->sync_lock acquired.
2259  *
2260  * @tegra: xhci controller context
2261  * @return 0 for success, or error numbers
2262  */
2263 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2264 {
2265         struct xhci_hcd *xhci = tegra->xhci;
2266         int ret = 0;
2267
2268         must_have_sync_lock(tegra);
2269
2270         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
2271                         tegra->hs_wake_event || tegra->host_resume_req)) {
2272
2273                 /*
2274                  * PWR_UNGATE SS partition. XUSBA
2275                  * tegra_unpowergate_partition also does partition reset
2276                  * deassert
2277                  */
2278                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
2279                 if (ret) {
2280                         xhci_err(xhci,
2281                         "%s: could not unpowergate xusba partition %d\n",
2282                         __func__, ret);
2283                         goto out;
2284                 }
2285                 if (tegra->ss_wake_event)
2286                         tegra->ss_wake_event = false;
2287
2288         } else {
2289                 xhci_info(xhci, "%s: ss already power gated\n",
2290                         __func__);
2291                 return ret;
2292         }
2293
2294         /* Step 3: Enable clock to ss partition */
2295         clk_enable(tegra->ss_clk);
2296
2297         /* Step 4: Disable ss wake detection logic */
2298         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2299
2300         /* Step 4.1: Disable ss wake detection logic */
2301         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
2302
2303         /* wait 150us */
2304         usleep_range(150, 200);
2305
2306         /* Step 4.2: Disable ss wake detection logic */
2307         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
2308
2309         /* Step 6 Deassert reset for ss clks */
2310         tegra_periph_reset_deassert(tegra->ss_clk);
2311
2312         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
2313         tegra->ss_pwr_gated = false;
2314 out:
2315         return ret;
2316 }
2317
2318 static void ss_partition_elpg_exit_work(struct work_struct *work)
2319 {
2320         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2321                 ss_elpg_exit_work);
2322
2323         mutex_lock(&tegra->sync_lock);
2324         tegra_xhci_ss_partition_elpg_exit(tegra);
2325         mutex_unlock(&tegra->sync_lock);
2326 }
2327
2328 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
2329 static void update_remote_wakeup_ports_pmc(struct tegra_xhci_hcd *tegra)
2330 {
2331         struct xhci_hcd *xhci = tegra->xhci;
2332         u32 wake2_status;
2333
2334 #define PMC_WAKE2_STATUS        0x168
2335 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
2336
2337         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
2338
2339         if (wake2_status & PADCTL_WAKE) {
2340                 /* FIXME: This is customized for Dalmore, find a generic way */
2341                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
2342                 /* clear wake status */
2343                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
2344         }
2345
2346         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
2347                         __func__, tegra->usb3_rh_remote_wakeup_ports);
2348 }
2349
2350 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
2351 {
2352         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2353         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2354         int port, num_ports;
2355         unsigned long *remote_wakeup_ports;
2356         u32 portsc;
2357         __le32 __iomem  **port_array;
2358         unsigned char *rh;
2359         unsigned int retry = 64;
2360
2361
2362         if (hcd == xhci->shared_hcd) {
2363                 port_array = xhci->usb3_ports;
2364                 num_ports = xhci->num_usb3_ports;
2365                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
2366                 rh = "usb3 roothub";
2367         } else
2368                 return;
2369
2370         while (*remote_wakeup_ports && retry--) {
2371                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
2372                         portsc = xhci_readl(xhci, port_array[port]);
2373
2374                         if (!(portsc & PORT_CONNECT)) {
2375                                 /* nothing to do if already disconnected */
2376                                 clear_bit(port, remote_wakeup_ports);
2377                                 continue;
2378                         }
2379
2380                         if ((portsc & PORT_PLS_MASK) == XDEV_U0)
2381                                 clear_bit(port, remote_wakeup_ports);
2382                         else
2383                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
2384                                                 __func__, rh, port, portsc);
2385                 }
2386
2387                 if (*remote_wakeup_ports)
2388                         msleep(20); /* give some time, irq will direct U0 */
2389         }
2390
2391         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
2392                         *remote_wakeup_ports);
2393 }
2394
2395 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
2396 {
2397         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2398         u32 reg, utmip_rctrl_val, utmip_tctrl_val;
2399
2400         /* Program XUSB as port owner for all usb2 ports */
2401         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2402         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2403                         USB2_OTG_PAD_PORT_MASK(2));
2404         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
2405                 USB2_OTG_PAD_PORT_OWNER_XUSB(1) | USB2_OTG_PAD_PORT_MASK(2);
2406         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2407
2408         /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
2409          * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
2410          */
2411         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2412         reg &= ~((1 << 12) | (1 << 13));
2413         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2414
2415         /* wait 20us */
2416         usleep_range(20, 30);
2417
2418         /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
2419          * :: TCTRL and RCTRL
2420          */
2421         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl1_0);
2422         utmip_rctrl_val = RCTRL(reg);
2423         utmip_tctrl_val = TCTRL(reg);
2424
2425         /*
2426          * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
2427          * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
2428          */
2429         pmc_data.utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
2430         pmc_data.utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
2431
2432         xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
2433                 pmc_data.utmip_rctrl_val, pmc_data.utmip_tctrl_val);
2434
2435         /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
2436          * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
2437          */
2438         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2439         reg |= (1 << 13);
2440         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2441
2442         /* Program these values into PMC regiseter and program the
2443          * PMC override
2444          */
2445         reg = PMC_TCTRL_VAL(pmc_data.utmip_tctrl_val) |
2446                 PMC_RCTRL_VAL(pmc_data.utmip_rctrl_val);
2447         tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG, 0xffffffff, reg);
2448
2449         reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
2450         tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
2451
2452         /* Restore correct port ownership in padctl */
2453         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2454         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2455                         USB2_OTG_PAD_PORT_MASK(2));
2456         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2457                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2458         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2459                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2460         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2461                 reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2462         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2463 }
2464
2465 /* Host ELPG Exit triggered by PADCTL irq */
2466 /**
2467  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
2468  *
2469  * This function must be called with tegra->sync_lock acquired.
2470  *
2471  * @tegra: xhci controller context
2472  * @return 0 for success, or error numbers
2473  */
2474 static int
2475 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2476 {
2477         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2478         struct xhci_hcd *xhci = tegra->xhci;
2479         int ret = 0;
2480
2481         must_have_sync_lock(tegra);
2482
2483         if (!tegra->hc_in_elpg)
2484                 return 0;
2485
2486         clk_enable(tegra->emc_clk);
2487         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2488                 clk_enable(tegra->pll_re_vco_clk);
2489         /* Step 2: Enable clock to host partition */
2490         clk_enable(tegra->host_clk);
2491
2492         if (tegra->lp0_exit) {
2493                 u32 reg, oc_bits = 0;
2494
2495                 /* Issue is only applicable for T114 */
2496                 if (XUSB_DEVICE_ID_T114 == tegra->device_id)
2497                         tegra_xhci_war_for_tctrl_rctrl(tegra);
2498                 /* check if over current seen. Clear if present */
2499                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2500                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2501                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2502                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2503                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2504                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2505
2506                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2507                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
2508                 if (reg & oc_bits) {
2509                         xhci_info(xhci, "Over current detected. Clearing...\n");
2510                         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2511
2512                         usleep_range(100, 200);
2513
2514                         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2515                         if (reg & oc_bits)
2516                                 xhci_info(xhci, "Over current still present\n");
2517                 }
2518                 tegra_xhci_padctl_portmap_and_caps(tegra);
2519                 /* release clamps post deassert */
2520                 tegra->lp0_exit = false;
2521         }
2522
2523         /* Clear FLUSH_ENABLE of MC client */
2524         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
2525
2526         /* set port ownership back to xusb */
2527         tegra_xhci_release_port_ownership(tegra, false);
2528
2529         /*
2530          * PWR_UNGATE Host partition. XUSBC
2531          * tegra_unpowergate_partition also does partition reset deassert
2532          */
2533         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
2534         if (ret) {
2535                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2536                         __func__, ret);
2537                 goto out;
2538         }
2539
2540         /* Step 4: Deassert reset to host partition clk */
2541         tegra_periph_reset_deassert(tegra->host_clk);
2542
2543         /* Step 6.1: IPFS and XUSB BAR initialization */
2544         tegra_xhci_cfg(tegra);
2545
2546         /* Step 6.2: IPFS and XUSB related restore */
2547         tegra_xhci_restore_ctx(tegra);
2548
2549         /* Step 8: xhci spec related ctx restore
2550          * will be done in xhci_resume().Do it here.
2551          */
2552
2553         tegra_xhci_ss_partition_elpg_exit(tegra);
2554
2555         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
2556         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
2557                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
2558                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
2559         }
2560
2561         /* clear ovrd bits */
2562         tegra_xhci_rx_idle_mode_override(tegra, false);
2563
2564         /* Load firmware */
2565         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
2566                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
2567                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
2568                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
2569                         __func__,
2570                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
2571                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
2572                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
2573                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
2574                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
2575                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
2576                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
2577                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
2578                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
2579         debug_print_portsc(xhci);
2580
2581         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
2582         if (ret < 0) {
2583                 xhci_err(xhci, "%s: failed to load firmware %d\n",
2584                         __func__, ret);
2585                 goto out;
2586         }
2587
2588         pmc_init(tegra, 0);
2589
2590         tegra->hc_in_elpg = false;
2591         ret = xhci_resume(tegra->xhci, 0);
2592         if (ret) {
2593                 xhci_err(xhci, "%s: could not resume right %d\n",
2594                                 __func__, ret);
2595                 goto out;
2596         }
2597
2598         update_remote_wakeup_ports_pmc(tegra);
2599
2600         if (tegra->hs_wake_event)
2601                 tegra->hs_wake_event = false;
2602
2603         if (tegra->host_resume_req)
2604                 tegra->host_resume_req = false;
2605
2606         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
2607                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
2608
2609         tegra->host_pwr_gated = false;
2610 out:
2611         return ret;
2612 }
2613
2614 static void host_partition_elpg_exit_work(struct work_struct *work)
2615 {
2616         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2617                 host_elpg_exit_work);
2618
2619         mutex_lock(&tegra->sync_lock);
2620         tegra_xhci_host_partition_elpg_exit(tegra);
2621         mutex_unlock(&tegra->sync_lock);
2622 }
2623
2624 /* Mailbox handling function. This function handles requests
2625  * from firmware and communicates with clock and powergating
2626  * module to alter clock rates and to power gate/ungate xusb
2627  * partitions.
2628  *
2629  * Following is the structure of mailbox messages.
2630  * bit 31:28 - msg type
2631  * bits 27:0 - mbox data
2632  * FIXME:  Check if we can just call clock functions like below
2633  * or should we schedule it for calling later ?
2634  */
2635
2636 static void
2637 tegra_xhci_process_mbox_message(struct work_struct *work)
2638 {
2639         u32 sw_resp = 0, cmd, data_in, fw_msg;
2640         int ret = 0;
2641         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2642                                         mbox_work);
2643         struct xhci_hcd *xhci = tegra->xhci;
2644         unsigned int freq_khz;
2645
2646         mutex_lock(&tegra->mbox_lock);
2647
2648         /* get the owner id */
2649         tegra->mbox_owner = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2650         tegra->mbox_owner &= MBOX_OWNER_ID_MASK;
2651
2652         /* get the mbox message from firmware */
2653         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
2654
2655         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2656         if (data_in) {
2657                 mutex_unlock(&tegra->mbox_lock);
2658                 return;
2659         }
2660
2661         /* get cmd type and cmd data */
2662         tegra->cmd_type = (fw_msg & MBOX_CMD_TYPE_MASK) >> MBOX_CMD_SHIFT;
2663         tegra->cmd_data = (fw_msg & MBOX_CMD_DATA_MASK);
2664
2665         /* decode the message and make appropriate requests to
2666          * clock or powergating module.
2667          */
2668
2669         switch (tegra->cmd_type) {
2670         case MBOX_CMD_INC_FALC_CLOCK:
2671         case MBOX_CMD_DEC_FALC_CLOCK:
2672                 ret = tegra_xusb_request_clk_rate(
2673                                 tegra,
2674                                 tegra->falc_clk,
2675                                 tegra->cmd_data,
2676                                 &sw_resp);
2677                 if (ret)
2678                         xhci_err(xhci, "%s: could not set required falc rate\n",
2679                                 __func__);
2680                 goto send_sw_response;
2681         case MBOX_CMD_INC_SSPI_CLOCK:
2682         case MBOX_CMD_DEC_SSPI_CLOCK:
2683                 ret = tegra_xusb_request_clk_rate(
2684                                 tegra,
2685                                 tegra->ss_src_clk,
2686                                 tegra->cmd_data,
2687                                 &sw_resp);
2688                 if (ret)
2689                         xhci_err(xhci, "%s: could not set required ss rate.\n",
2690                                 __func__);
2691                 goto send_sw_response;
2692         case MBOX_CMD_SET_BW:
2693                 /* fw sends BW request in MByte/sec */
2694                 freq_khz = tegra_emc_bw_to_freq_req(tegra->cmd_data << 10);
2695                 clk_set_rate(tegra->emc_clk, freq_khz * 1000);
2696
2697                 /* clear MBOX_SMI_INT_EN bit */
2698                 cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2699                 cmd &= ~MBOX_SMI_INT_EN;
2700                 writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2701
2702                 /* clear mbox owner as ACK will not be sent for this request */
2703                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2704                 break;
2705         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
2706                 tegra_xhci_save_dfe_ctle_context(tegra, tegra->cmd_data);
2707                 tegra_xhci_restore_dfe_ctle_context(tegra, tegra->cmd_data);
2708                 /* SATA lane also if USB3_SS port1 mapped to it */
2709                 if (tegra->cmd_data == 0x1 &&
2710                         XUSB_DEVICE_ID_T114 != tegra->device_id &&
2711                                 tegra->bdata->lane_owner & BIT(0)) {
2712                         tegra_xhci_save_dfe_ctle_context(tegra, 3);
2713                         tegra_xhci_restore_dfe_ctle_context(tegra, 3);
2714                 }
2715
2716                 sw_resp |= (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
2717                 goto send_sw_response;
2718         case MBOX_CMD_ACK:
2719                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2720                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2721                 break;
2722         case MBOX_CMD_NACK:
2723                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2724                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2725                 break;
2726         default:
2727                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
2728                                 __func__, tegra->cmd_type);
2729         }
2730         mutex_unlock(&tegra->mbox_lock);
2731         return;
2732
2733 send_sw_response:
2734         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2735         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2736         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
2737         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2738
2739         mutex_unlock(&tegra->mbox_lock);
2740 }
2741
2742 static irqreturn_t tegra_xhci_xusb_host_irq(int irq, void *ptrdev)
2743 {
2744         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2745         struct xhci_hcd *xhci = tegra->xhci;
2746
2747         xhci_dbg(xhci, "%s", __func__);
2748         return IRQ_HANDLED;
2749 }
2750
2751 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
2752 {
2753         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2754         struct xhci_hcd *xhci = tegra->xhci;
2755         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2756         u32 elpg_program0 = 0;
2757
2758         spin_lock(&tegra->lock);
2759
2760         tegra->last_jiffies = jiffies;
2761
2762         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
2763         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
2764
2765         /* Clear the interrupt cause. We already read the intr status. */
2766         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2767         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
2768
2769         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
2770         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
2771                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2772         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
2773                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
2774         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
2775                 __func__,
2776                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad0_ctl0_0));
2777         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
2778                 __func__,
2779                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad1_ctl0_0));
2780         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
2781                 __func__,
2782                 readl(tegra->padctl_base + padregs->usb2_bchrg_bias_pad_0));
2783
2784         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
2785                 tegra->ss_wake_event = true;
2786         else if (elpg_program0 &
2787                         (USB2_PORT0_WAKEUP_EVENT | USB2_PORT1_WAKEUP_EVENT |
2788                                 USB2_PORT2_WAKEUP_EVENT))
2789                 tegra->hs_wake_event = true;
2790
2791         if (tegra->ss_wake_event || tegra->hs_wake_event) {
2792                 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
2793                         xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
2794                         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
2795                 } else if (tegra->ss_pwr_gated
2796                                 && tegra->host_pwr_gated) {
2797                         xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
2798                                 __func__);
2799                         schedule_work(&tegra->host_elpg_exit_work);
2800                 }
2801         } else {
2802                 xhci_err(xhci, "error: wake due to no hs/ss event\n");
2803                 tegra_usb_pad_reg_write(padregs->elpg_program_0, 0xffffffff);
2804         }
2805         spin_unlock(&tegra->lock);
2806         return IRQ_HANDLED;
2807 }
2808
2809 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
2810 {
2811         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
2812         u32 temp;
2813
2814         spin_lock(&tegra->lock);
2815
2816         /* clear the mbox intr status 1st thing. Other
2817          * bits are W1C bits, so just write to SMI bit.
2818          */
2819
2820         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
2821
2822         /* write 1 to clear SMI INTR en bit ( bit 3 ) */
2823         temp = MBOX_SMI_INTR_EN;
2824         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
2825
2826         schedule_work(&tegra->mbox_work);
2827
2828         spin_unlock(&tegra->lock);
2829         return IRQ_HANDLED;
2830 }
2831
2832 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
2833 {
2834         /*
2835          * As of now platform drivers don't provide MSI support so we ensure
2836          * here that the generic code does not try to make a pci_dev from our
2837          * dev struct in order to setup MSI
2838          */
2839         xhci->quirks |= XHCI_BROKEN_MSI;
2840         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
2841 }
2842
2843 /* called during probe() after chip reset completes */
2844 static int xhci_plat_setup(struct usb_hcd *hcd)
2845 {
2846         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
2847 }
2848
2849 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
2850         const char *name, void __iomem **region)
2851 {
2852         struct resource *res;
2853         void __iomem *mem;
2854
2855         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
2856         if (!res) {
2857                 dev_err(&pdev->dev, "memory resource %s doesn't exist\n", name);
2858                 return -ENODEV;
2859         }
2860
2861         mem = devm_request_and_ioremap(&pdev->dev, res);
2862         if (!mem) {
2863                 dev_err(&pdev->dev, "failed to ioremap for %s\n", name);
2864                 return -EFAULT;
2865         }
2866         *region = mem;
2867
2868         return 0;
2869 }
2870
2871 static int tegra_xhci_request_irq(struct platform_device *pdev,
2872         const char *rscname, irq_handler_t handler, unsigned long irqflags,
2873         const char *devname, int *irq_no)
2874 {
2875         int ret;
2876         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
2877         struct resource *res;
2878
2879         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, rscname);
2880         if (!res) {
2881                 dev_err(&pdev->dev, "irq resource %s doesn't exist\n", rscname);
2882                 return -ENODEV;
2883         }
2884
2885         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
2886                         devname, tegra);
2887         if (ret != 0) {
2888                 dev_err(&pdev->dev,
2889                         "failed to request_irq for %s (irq %d), error = %d\n",
2890                         devname, res->start, ret);
2891                 return ret;
2892         }
2893         *irq_no = res->start;
2894
2895         return 0;
2896 }
2897
2898 #ifdef CONFIG_PM
2899
2900 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
2901 {
2902         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2903         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2904         int err = 0;
2905         unsigned long flags;
2906
2907         mutex_lock(&tegra->sync_lock);
2908
2909         if (xhci->shared_hcd == hcd) {
2910                 tegra->usb3_rh_suspend = true;
2911                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
2912         } else if (xhci->main_hcd == hcd) {
2913                 tegra->usb2_rh_suspend = true;
2914                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
2915         }
2916
2917         WARN_ON(tegra->hc_in_elpg);
2918
2919         /* suspend xhci bus. This will also set remote mask */
2920         err = xhci_bus_suspend(hcd);
2921         if (err) {
2922                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
2923                                 __func__, err);
2924                 goto xhci_bus_suspend_failed;
2925         }
2926
2927         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
2928                 goto done; /* one of the root hubs is still working */
2929
2930         spin_lock_irqsave(&tegra->lock, flags);
2931         tegra->hc_in_elpg = true;
2932         spin_unlock_irqrestore(&tegra->lock, flags);
2933
2934         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
2935
2936         /* save xhci spec ctx. Already done by xhci_suspend */
2937         err = xhci_suspend(tegra->xhci);
2938         if (err) {
2939                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
2940                 goto xhci_suspend_failed;
2941         }
2942
2943         /* Powergate host. Include ss power gate if not already done */
2944         err = tegra_xhci_host_elpg_entry(tegra);
2945         if (err) {
2946                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
2947                                 __func__, err);
2948                 goto tegra_xhci_host_elpg_entry_failed;
2949         }
2950
2951         /* At this point,ensure ss/hs intr enables are always on */
2952         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2953         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2954
2955         /* In ELPG, firmware log context is gone. Rewind shared log buffer. */
2956         if (fw_log_wait_empty_timeout(tegra, 100))
2957                 xhci_warn(xhci, "%s still has logs\n", __func__);
2958         tegra->log.dequeue = tegra->log.virt_addr;
2959         tegra->log.seq = 0;
2960
2961 done:
2962         /* pads are disabled only if usb2 root hub in xusb is idle */
2963         /* pads will actually be disabled only when all usb2 ports are idle */
2964         if (xhci->main_hcd == hcd) {
2965                 utmi_phy_pad_disable();
2966                 utmi_phy_iddq_override(true);
2967         }
2968         mutex_unlock(&tegra->sync_lock);
2969         return 0;
2970
2971 tegra_xhci_host_elpg_entry_failed:
2972
2973 xhci_suspend_failed:
2974         tegra->hc_in_elpg = false;
2975 xhci_bus_suspend_failed:
2976         if (xhci->shared_hcd == hcd)
2977                 tegra->usb3_rh_suspend = false;
2978         else if (xhci->main_hcd == hcd)
2979                 tegra->usb2_rh_suspend = false;
2980
2981         mutex_unlock(&tegra->sync_lock);
2982         return err;
2983 }
2984
2985 /* First, USB2HCD and then USB3HCD resume will be called */
2986 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
2987 {
2988         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2989         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2990         int err = 0;
2991
2992         mutex_lock(&tegra->sync_lock);
2993
2994         tegra->host_resume_req = true;
2995
2996         if (xhci->shared_hcd == hcd)
2997                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
2998         else if (xhci->main_hcd == hcd)
2999                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3000
3001         /* pads are disabled only if usb2 root hub in xusb is idle */
3002         /* pads will actually be disabled only when all usb2 ports are idle */
3003         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
3004                 utmi_phy_pad_enable();
3005                 utmi_phy_iddq_override(false);
3006         }
3007         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
3008                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
3009                         tegra_xhci_host_partition_elpg_exit(tegra);
3010         }
3011
3012          /* handle remote wakeup before resuming bus */
3013         wait_remote_wakeup_ports(hcd);
3014
3015         err = xhci_bus_resume(hcd);
3016         if (err) {
3017                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
3018                                 __func__, err);
3019                 goto xhci_bus_resume_failed;
3020         }
3021
3022         if (xhci->shared_hcd == hcd)
3023                 tegra->usb3_rh_suspend = false;
3024         else if (xhci->main_hcd == hcd)
3025                 tegra->usb2_rh_suspend = false;
3026
3027         mutex_unlock(&tegra->sync_lock);
3028         return 0;
3029
3030 xhci_bus_resume_failed:
3031         /* TODO: reverse elpg? */
3032         mutex_unlock(&tegra->sync_lock);
3033         return err;
3034 }
3035 #endif
3036
3037 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
3038 {
3039         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3040         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3041         irqreturn_t iret = IRQ_HANDLED;
3042         u32 status;
3043
3044         spin_lock(&tegra->lock);
3045         if (tegra->hc_in_elpg) {
3046                 spin_lock(&xhci->lock);
3047                 if (HCD_HW_ACCESSIBLE(hcd)) {
3048                         status = xhci_readl(xhci, &xhci->op_regs->status);
3049                         status |= STS_EINT;
3050                         xhci_writel(xhci, status, &xhci->op_regs->status);
3051                 }
3052                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
3053                                 __func__);
3054                 schedule_work(&tegra->host_elpg_exit_work);
3055                 spin_unlock(&xhci->lock);
3056         } else
3057                 iret = xhci_irq(hcd);
3058         spin_unlock(&tegra->lock);
3059
3060         wake_up_interruptible(&tegra->log.intr_wait);
3061
3062         return iret;
3063 }
3064
3065
3066 static const struct hc_driver tegra_plat_xhci_driver = {
3067         .description =          "tegra-xhci",
3068         .product_desc =         "Nvidia xHCI Host Controller",
3069         .hcd_priv_size =        sizeof(struct xhci_hcd *),
3070
3071         /*
3072          * generic hardware linkage
3073          */
3074         .irq =                  tegra_xhci_irq,
3075         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
3076
3077         /*
3078          * basic lifecycle operations
3079          */
3080         .reset =                xhci_plat_setup,
3081         .start =                xhci_run,
3082         .stop =                 xhci_stop,
3083         .shutdown =             xhci_shutdown,
3084
3085         /*
3086          * managing i/o requests and associated device resources
3087          */
3088         .urb_enqueue =          xhci_urb_enqueue,
3089         .urb_dequeue =          xhci_urb_dequeue,
3090         .alloc_dev =            xhci_alloc_dev,
3091         .free_dev =             xhci_free_dev,
3092         .alloc_streams =        xhci_alloc_streams,
3093         .free_streams =         xhci_free_streams,
3094         .add_endpoint =         xhci_add_endpoint,
3095         .drop_endpoint =        xhci_drop_endpoint,
3096         .endpoint_reset =       xhci_endpoint_reset,
3097         .check_bandwidth =      xhci_check_bandwidth,
3098         .reset_bandwidth =      xhci_reset_bandwidth,
3099         .address_device =       xhci_address_device,
3100         .update_hub_device =    xhci_update_hub_device,
3101         .reset_device =         xhci_discover_or_reset_device,
3102
3103         /*
3104          * scheduling support
3105          */
3106         .get_frame_number =     xhci_get_frame,
3107
3108         /* Root hub support */
3109         .hub_control =          xhci_hub_control,
3110         .hub_status_data =      xhci_hub_status_data,
3111
3112 #ifdef CONFIG_PM
3113         .bus_suspend =          tegra_xhci_bus_suspend,
3114         .bus_resume =           tegra_xhci_bus_resume,
3115 #endif
3116 };
3117
3118 #ifdef CONFIG_PM
3119 static int
3120 tegra_xhci_suspend(struct platform_device *pdev,
3121                                                 pm_message_t state)
3122 {
3123         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3124         struct xhci_hcd *xhci = tegra->xhci;
3125
3126         int ret = 0;
3127
3128         mutex_lock(&tegra->sync_lock);
3129         if (!tegra->hc_in_elpg) {
3130                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
3131                                 __func__);
3132                 mutex_unlock(&tegra->sync_lock);
3133                 return -EBUSY;
3134         }
3135         mutex_unlock(&tegra->sync_lock);
3136
3137         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3138         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3139
3140         /* enable_irq_wake for ss ports */
3141         ret = enable_irq_wake(tegra->padctl_irq);
3142         if (ret < 0) {
3143                 xhci_err(xhci,
3144                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
3145                 __func__, tegra->padctl_irq, ret);
3146         }
3147
3148         /* enable_irq_wake for hs/fs/ls ports */
3149         ret = enable_irq_wake(tegra->usb3_irq);
3150         if (ret < 0) {
3151                 xhci_err(xhci,
3152                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
3153                 __func__, tegra->usb3_irq, ret);
3154         }
3155         regulator_disable(tegra->xusb_s1p8v_reg);
3156         regulator_disable(tegra->xusb_s1p05v_reg);
3157         tegra_usb2_clocks_deinit(tegra);
3158
3159         return ret;
3160 }
3161
3162 static int
3163 tegra_xhci_resume(struct platform_device *pdev)
3164 {
3165         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3166
3167         dev_dbg(&pdev->dev, "%s\n", __func__);
3168
3169         tegra->last_jiffies = jiffies;
3170
3171         disable_irq_wake(tegra->padctl_irq);
3172         disable_irq_wake(tegra->usb3_irq);
3173         tegra->lp0_exit = true;
3174
3175         regulator_enable(tegra->xusb_s1p05v_reg);
3176         regulator_enable(tegra->xusb_s1p8v_reg);
3177         tegra_usb2_clocks_init(tegra);
3178
3179         return 0;
3180 }
3181 #endif
3182
3183
3184 static int init_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3185 {
3186         struct platform_device *pdev = tegra->pdev;
3187         void __iomem *fw_mmio_base;
3188         phys_addr_t fw_mem_phy_addr;
3189         size_t fw_size;
3190         dma_addr_t fw_dma;
3191 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3192         int ret;
3193 #endif
3194
3195         /* bootloader saved firmware memory address in PMC SCRATCH34 register */
3196         fw_mem_phy_addr = tegra_usb_pmc_reg_read(PMC_SCRATCH34);
3197
3198         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3199                         fw_mem_phy_addr, sizeof(struct cfgtbl));
3200
3201         if (!fw_mmio_base) {
3202                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3203                                         fw_mem_phy_addr);
3204                         return -ENOMEM;
3205         }
3206
3207         fw_size = ioread32(fw_mmio_base + FW_SIZE_OFFSET);
3208         devm_iounmap(&pdev->dev, fw_mmio_base);
3209
3210         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3211                         fw_mem_phy_addr, fw_size);
3212         if (!fw_mmio_base) {
3213                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3214                                         fw_mem_phy_addr);
3215                         return -ENOMEM;
3216         }
3217
3218         dev_info(&pdev->dev, "Firmware Memory: phy 0x%x mapped 0x%p (%d Bytes)\n",
3219                         fw_mem_phy_addr, fw_mmio_base, fw_size);
3220
3221 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3222         fw_dma = dma_map_linear(&pdev->dev, fw_mem_phy_addr, fw_size,
3223                         DMA_TO_DEVICE);
3224         if (fw_dma == DMA_ERROR_CODE) {
3225                 dev_err(&pdev->dev, "%s: dma_map_linear failed\n",
3226                                 __func__);
3227                 ret = -ENOMEM;
3228                 goto error_iounmap;
3229         }
3230 #else
3231         fw_dma = fw_mem_phy_addr;
3232 #endif
3233         dev_info(&pdev->dev, "Firmware DMA Memory: dma 0x%p (%d Bytes)\n",
3234                         (void *) fw_dma, fw_size);
3235
3236         /* all set and ready to go */
3237         tegra->firmware.data = fw_mmio_base;
3238         tegra->firmware.dma = fw_dma;
3239         tegra->firmware.size = fw_size;
3240
3241         return 0;
3242
3243 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3244 error_iounmap:
3245         devm_iounmap(&pdev->dev, fw_mmio_base);
3246         return ret;
3247 #endif
3248 }
3249
3250 static void deinit_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3251 {
3252         struct platform_device *pdev = tegra->pdev;
3253         void __iomem *fw_mmio_base = tegra->firmware.data;
3254
3255 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3256         dma_unmap_single(&pdev->dev, tegra->firmware.dma,
3257                         tegra->firmware.size, DMA_TO_DEVICE);
3258 #endif
3259         devm_iounmap(&pdev->dev, fw_mmio_base);
3260
3261         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
3262 }
3263
3264 static int init_firmware(struct tegra_xhci_hcd *tegra)
3265 {
3266         return init_bootloader_firmware(tegra);
3267 }
3268
3269 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
3270 {
3271         deinit_bootloader_firmware(tegra);
3272 }
3273
3274 static struct tegra_xusb_padctl_regs t114_padregs_offset = {
3275         .boot_media_0                   = 0x0,
3276         .usb2_pad_mux_0                 = 0x4,
3277         .usb2_port_cap_0                = 0x8,
3278         .snps_oc_map_0                  = 0xc,
3279         .usb2_oc_map_0                  = 0x10,
3280         .ss_port_map_0                  = 0x14,
3281         .oc_det_0                       = 0x18,
3282         .elpg_program_0                 = 0x1c,
3283         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3284         .usb2_bchrg_otgpad0_ctl1_0      = 0xffff,
3285         .usb2_bchrg_otgpad1_ctl0_0      = 0x24,
3286         .usb2_bchrg_otgpad1_ctl1_0      = 0xffff,
3287         .usb2_bchrg_otgpad2_ctl0_0      = 0xffff,
3288         .usb2_bchrg_otgpad2_ctl1_0      = 0xffff,
3289         .usb2_bchrg_bias_pad_0          = 0x28,
3290         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
3291         .iophy_pll_p0_ctl1_0            = 0x30,
3292         .iophy_pll_p0_ctl2_0            = 0x34,
3293         .iophy_pll_p0_ctl3_0            = 0x38,
3294         .iophy_pll_p0_ctl4_0            = 0x3c,
3295         .iophy_usb3_pad0_ctl1_0         = 0x40,
3296         .iophy_usb3_pad1_ctl1_0         = 0x44,
3297         .iophy_usb3_pad0_ctl2_0         = 0x48,
3298         .iophy_usb3_pad1_ctl2_0         = 0x4c,
3299         .iophy_usb3_pad0_ctl3_0         = 0x50,
3300         .iophy_usb3_pad1_ctl3_0         = 0x54,
3301         .iophy_usb3_pad0_ctl4_0         = 0x58,
3302         .iophy_usb3_pad1_ctl4_0         = 0x5c,
3303         .iophy_misc_pad_p0_ctl1_0       = 0x60,
3304         .iophy_misc_pad_p1_ctl1_0       = 0x64,
3305         .iophy_misc_pad_p0_ctl2_0       = 0x68,
3306         .iophy_misc_pad_p1_ctl2_0       = 0x6c,
3307         .iophy_misc_pad_p0_ctl3_0       = 0x70,
3308         .iophy_misc_pad_p1_ctl3_0       = 0x74,
3309         .iophy_misc_pad_p0_ctl4_0       = 0x78,
3310         .iophy_misc_pad_p1_ctl4_0       = 0x7c,
3311         .iophy_misc_pad_p0_ctl5_0       = 0x80,
3312         .iophy_misc_pad_p1_ctl5_0       = 0x84,
3313         .iophy_misc_pad_p0_ctl6_0       = 0x88,
3314         .iophy_misc_pad_p1_ctl6_0       = 0x8c,
3315         .usb2_otg_pad0_ctl0_0           = 0x90,
3316         .usb2_otg_pad1_ctl0_0           = 0x94,
3317         .usb2_otg_pad2_ctl0_0           = 0xffff,
3318         .usb2_otg_pad0_ctl1_0           = 0x98,
3319         .usb2_otg_pad1_ctl1_0           = 0x9c,
3320         .usb2_otg_pad2_ctl1_0           = 0xffff,
3321         .usb2_bias_pad_ctl0_0           = 0xa0,
3322         .usb2_bias_pad_ctl1_0           = 0xa4,
3323         .usb2_hsic_pad0_ctl0_0          = 0xa8,
3324         .usb2_hsic_pad1_ctl0_0          = 0xac,
3325         .usb2_hsic_pad0_ctl1_0          = 0xb0,
3326         .usb2_hsic_pad1_ctl1_0          = 0xb4,
3327         .usb2_hsic_pad0_ctl2_0          = 0xb8,
3328         .usb2_hsic_pad1_ctl2_0          = 0xbc,
3329         .ulpi_link_trim_ctl0            = 0xc0,
3330         .ulpi_null_clk_trim_ctl0        = 0xc4,
3331         .hsic_strb_trim_ctl0            = 0xc8,
3332         .wake_ctl0                      = 0xcc,
3333         .pm_spare0                      = 0xd0,
3334         .iophy_misc_pad_p2_ctl1_0       = 0xffff,
3335         .iophy_misc_pad_p3_ctl1_0       = 0xffff,
3336         .iophy_misc_pad_p4_ctl1_0       = 0xffff,
3337         .iophy_misc_pad_p2_ctl2_0       = 0xffff,
3338         .iophy_misc_pad_p3_ctl2_0       = 0xffff,
3339         .iophy_misc_pad_p4_ctl2_0       = 0xffff,
3340         .iophy_misc_pad_p2_ctl3_0       = 0xffff,
3341         .iophy_misc_pad_p3_ctl3_0       = 0xffff,
3342         .iophy_misc_pad_p4_ctl3_0       = 0xffff,
3343         .iophy_misc_pad_p2_ctl4_0       = 0xffff,
3344         .iophy_misc_pad_p3_ctl4_0       = 0xffff,
3345         .iophy_misc_pad_p4_ctl4_0       = 0xffff,
3346         .iophy_misc_pad_p2_ctl5_0       = 0xffff,
3347         .iophy_misc_pad_p3_ctl5_0       = 0xffff,
3348         .iophy_misc_pad_p4_ctl5_0       = 0xffff,
3349         .iophy_misc_pad_p2_ctl6_0       = 0xffff,
3350         .iophy_misc_pad_p3_ctl6_0       = 0xffff,
3351         .iophy_misc_pad_p4_ctl6_0       = 0xffff,
3352         .usb3_pad_mux_0                 = 0xffff,
3353         .iophy_pll_s0_ctl1_0            = 0xffff,
3354         .iophy_pll_s0_ctl2_0            = 0xffff,
3355         .iophy_pll_s0_ctl3_0            = 0xffff,
3356         .iophy_pll_s0_ctl4_0            = 0xffff,
3357         .iophy_misc_pad_s0_ctl1_0       = 0xffff,
3358         .iophy_misc_pad_s0_ctl2_0       = 0xffff,
3359         .iophy_misc_pad_s0_ctl3_0       = 0xffff,
3360         .iophy_misc_pad_s0_ctl4_0       = 0xffff,
3361         .iophy_misc_pad_s0_ctl5_0       = 0xffff,
3362         .iophy_misc_pad_s0_ctl6_0       = 0xffff,
3363 };
3364
3365 static struct tegra_xusb_padctl_regs t124_padregs_offset = {
3366         .boot_media_0                   = 0x0,
3367         .usb2_pad_mux_0                 = 0x4,
3368         .usb2_port_cap_0                = 0x8,
3369         .snps_oc_map_0                  = 0xc,
3370         .usb2_oc_map_0                  = 0x10,
3371         .ss_port_map_0                  = 0x14,
3372         .oc_det_0                       = 0x18,
3373         .elpg_program_0                 = 0x1c,
3374         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3375         .usb2_bchrg_otgpad0_ctl1_0      = 0x24,
3376         .usb2_bchrg_otgpad1_ctl0_0      = 0x28,
3377         .usb2_bchrg_otgpad1_ctl1_0      = 0x2c,
3378         .usb2_bchrg_otgpad2_ctl0_0      = 0x30,
3379         .usb2_bchrg_otgpad2_ctl1_0      = 0x34,
3380         .usb2_bchrg_bias_pad_0          = 0x38,
3381         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
3382         .iophy_pll_p0_ctl1_0            = 0x40,
3383         .iophy_pll_p0_ctl2_0            = 0x44,
3384         .iophy_pll_p0_ctl3_0            = 0x48,
3385         .iophy_pll_p0_ctl4_0            = 0x4c,
3386         .iophy_usb3_pad0_ctl1_0         = 0x50,
3387         .iophy_usb3_pad1_ctl1_0         = 0x54,
3388         .iophy_usb3_pad0_ctl2_0         = 0x58,
3389         .iophy_usb3_pad1_ctl2_0         = 0x5c,
3390         .iophy_usb3_pad0_ctl3_0         = 0x60,
3391         .iophy_usb3_pad1_ctl3_0         = 0x64,
3392         .iophy_usb3_pad0_ctl4_0         = 0x68,
3393         .iophy_usb3_pad1_ctl4_0         = 0x6c,
3394         .iophy_misc_pad_p0_ctl1_0       = 0x70,
3395         .iophy_misc_pad_p1_ctl1_0       = 0x74,
3396         .iophy_misc_pad_p0_ctl2_0       = 0x78,
3397         .iophy_misc_pad_p1_ctl2_0       = 0x7c,
3398         .iophy_misc_pad_p0_ctl3_0       = 0x80,
3399         .iophy_misc_pad_p1_ctl3_0       = 0x84,
3400         .iophy_misc_pad_p0_ctl4_0       = 0x88,
3401         .iophy_misc_pad_p1_ctl4_0       = 0x8c,
3402         .iophy_misc_pad_p0_ctl5_0       = 0x90,
3403         .iophy_misc_pad_p1_ctl5_0       = 0x94,
3404         .iophy_misc_pad_p0_ctl6_0       = 0x98,
3405         .iophy_misc_pad_p1_ctl6_0       = 0x9c,
3406         .usb2_otg_pad0_ctl0_0           = 0xa0,
3407         .usb2_otg_pad1_ctl0_0           = 0xa4,
3408         .usb2_otg_pad2_ctl0_0           = 0xa8,
3409         .usb2_otg_pad0_ctl1_0           = 0xac,
3410         .usb2_otg_pad1_ctl1_0           = 0xb0,
3411         .usb2_otg_pad2_ctl1_0           = 0xb4,
3412         .usb2_bias_pad_ctl0_0           = 0xb8,
3413         .usb2_bias_pad_ctl1_0           = 0xbc,
3414         .usb2_hsic_pad0_ctl0_0          = 0xc0,
3415         .usb2_hsic_pad1_ctl0_0          = 0xc4,
3416         .usb2_hsic_pad0_ctl1_0          = 0xc8,
3417         .usb2_hsic_pad1_ctl1_0          = 0xcc,
3418         .usb2_hsic_pad0_ctl2_0          = 0xd0,
3419         .usb2_hsic_pad1_ctl2_0          = 0xd4,
3420         .ulpi_link_trim_ctl0            = 0xd8,
3421         .ulpi_null_clk_trim_ctl0        = 0xdc,
3422         .hsic_strb_trim_ctl0            = 0xe0,
3423         .wake_ctl0                      = 0xe4,
3424         .pm_spare0                      = 0xe8,
3425         .iophy_misc_pad_p2_ctl1_0       = 0xec,
3426         .iophy_misc_pad_p3_ctl1_0       = 0xf0,
3427         .iophy_misc_pad_p4_ctl1_0       = 0xf4,
3428         .iophy_misc_pad_p2_ctl2_0       = 0xf8,
3429         .iophy_misc_pad_p3_ctl2_0       = 0xfc,
3430         .iophy_misc_pad_p4_ctl2_0       = 0x100,
3431         .iophy_misc_pad_p2_ctl3_0       = 0x104,
3432         .iophy_misc_pad_p3_ctl3_0       = 0x108,
3433         .iophy_misc_pad_p4_ctl3_0       = 0x10c,
3434         .iophy_misc_pad_p2_ctl4_0       = 0x110,
3435         .iophy_misc_pad_p3_ctl4_0       = 0x114,
3436         .iophy_misc_pad_p4_ctl4_0       = 0x118,
3437         .iophy_misc_pad_p2_ctl5_0       = 0x11c,
3438         .iophy_misc_pad_p3_ctl5_0       = 0x120,
3439         .iophy_misc_pad_p4_ctl5_0       = 0x124,
3440         .iophy_misc_pad_p2_ctl6_0       = 0x128,
3441         .iophy_misc_pad_p3_ctl6_0       = 0x12c,
3442         .iophy_misc_pad_p4_ctl6_0       = 0x130,
3443         .usb3_pad_mux_0                 = 0x134,
3444         .iophy_pll_s0_ctl1_0            = 0x138,
3445         .iophy_pll_s0_ctl2_0            = 0x13c,
3446         .iophy_pll_s0_ctl3_0            = 0x140,
3447         .iophy_pll_s0_ctl4_0            = 0x144,
3448         .iophy_misc_pad_s0_ctl1_0       = 0x148,
3449         .iophy_misc_pad_s0_ctl2_0       = 0x14c,
3450         .iophy_misc_pad_s0_ctl3_0       = 0x150,
3451         .iophy_misc_pad_s0_ctl4_0       = 0x154,
3452         .iophy_misc_pad_s0_ctl5_0       = 0x158,
3453         .iophy_misc_pad_s0_ctl6_0       = 0x15c,
3454 };
3455
3456 /* TODO: we have to refine error handling in tegra_xhci_probe() */
3457 static int tegra_xhci_probe(struct platform_device *pdev)
3458 {
3459         const struct hc_driver *driver;
3460         struct xhci_hcd *xhci;
3461         struct tegra_xhci_hcd *tegra;
3462         struct resource *res;
3463         struct usb_hcd  *hcd;
3464         u32 pmc_reg, val;
3465         int ret;
3466         int irq;
3467
3468         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
3469
3470         if (usb_disabled())
3471                 return -ENODEV;
3472
3473         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
3474         if (!tegra) {
3475                 dev_err(&pdev->dev, "memory alloc failed\n");
3476                 return -ENOMEM;
3477         }
3478         tegra->pdev = pdev;
3479         tegra->pdata = dev_get_platdata(&pdev->dev);
3480         tegra->bdata = tegra->pdata->bdata;
3481
3482         ret = tegra_xhci_request_mem_region(pdev, "padctl",
3483                         &tegra->padctl_base);
3484         if (ret) {
3485                 dev_err(&pdev->dev, "failed to map padctl\n");
3486                 return ret;
3487         }
3488
3489         ret = tegra_xhci_request_mem_region(pdev, "fpci", &tegra->fpci_base);
3490         if (ret) {
3491                 dev_err(&pdev->dev, "failed to map fpci\n");
3492                 return ret;
3493         }
3494
3495         ret = tegra_xhci_request_mem_region(pdev, "ipfs", &tegra->ipfs_base);
3496         if (ret) {
3497                 dev_err(&pdev->dev, "failed to map ipfs\n");
3498                 return ret;
3499         }
3500
3501         ret = tegra_xusb_partitions_clk_init(tegra);
3502         if (ret) {
3503                 dev_err(&pdev->dev,
3504                         "failed to initialize xusb partitions clocks\n");
3505                 return ret;
3506         }
3507
3508         /* Enable power rails to the PAD,VBUS
3509          * and pull-up voltage.Initialize the regulators
3510          */
3511         ret = tegra_xusb_regulator_init(tegra, pdev);
3512         if (ret) {
3513                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
3514                 goto err_deinit_xusb_partition_clk;
3515         }
3516
3517         /* Enable UTMIP, PLLU and PLLE */
3518         ret = tegra_usb2_clocks_init(tegra);
3519         if (ret) {
3520                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
3521                 goto err_deinit_tegra_xusb_regulator;
3522         }
3523
3524         /* tegra_unpowergate_partition also does partition reset deassert */
3525         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
3526         if (ret)
3527                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
3528
3529         /* tegra_unpowergate_partition also does partition reset deassert */
3530         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3531         if (ret)
3532                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
3533
3534         /* reset the pointer back to NULL. driver uses it */
3535         /* platform_set_drvdata(pdev, NULL); */
3536
3537         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "host");
3538         if (!res) {
3539                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
3540                 ret = -ENODEV;
3541                 goto err_deinit_usb2_clocks;
3542         }
3543         tegra->host_phy_base = res->start;
3544
3545         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
3546                                 res->start, resource_size(res));
3547         if (!tegra->host_phy_virt_base) {
3548                 dev_err(&pdev->dev, "error mapping host phy memory\n");
3549                 ret = -ENOMEM;
3550                 goto err_deinit_usb2_clocks;
3551         }
3552
3553         /* Setup IPFS access and BAR0 space */
3554         tegra_xhci_cfg(tegra);
3555
3556         val = readl(tegra->fpci_base + XUSB_CFG_0);
3557         tegra->device_id = (val >> 16) & 0xffff;
3558
3559         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
3560                 (XUSB_DEVICE_ID_T114 == tegra->device_id) ? "T114" : "T124+");
3561
3562         if (XUSB_DEVICE_ID_T114 == tegra->device_id) {
3563                 tegra->padregs = &t114_padregs_offset;
3564         } else if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
3565                 tegra->padregs = &t124_padregs_offset;
3566         } else {
3567                 dev_info(&pdev->dev, "XUSB device_id neither T114 nor T124!\n");
3568                 dev_info(&pdev->dev, "XUSB using T124 pad register offsets!\n");
3569                 tegra->padregs = &t124_padregs_offset;
3570         }
3571
3572         /* calculate rctrl_val and tctrl_val once at boot time */
3573         tegra_xhci_war_for_tctrl_rctrl(tegra);
3574
3575         /* Program the XUSB pads to take ownership of ports */
3576         tegra_xhci_padctl_portmap_and_caps(tegra);
3577
3578         /* Release XUSB wake logic state latching */
3579         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
3580         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
3581
3582         /* Deassert reset to XUSB host, ss, dev clocks */
3583         tegra_periph_reset_deassert(tegra->host_clk);
3584         tegra_periph_reset_deassert(tegra->ss_clk);
3585
3586         fw_log_init(tegra);
3587         ret = init_firmware(tegra);
3588         if (ret < 0) {
3589                 dev_err(&pdev->dev, "failed to init firmware\n");
3590                 ret = -ENODEV;
3591                 goto err_deinit_usb2_clocks;
3592         }
3593
3594         ret = load_firmware(tegra, true /* do reset ARU */);
3595         if (ret < 0) {
3596                 dev_err(&pdev->dev, "failed to load firmware\n");
3597                 ret = -ENODEV;
3598                 goto err_deinit_firmware;
3599         }
3600
3601         device_init_wakeup(&pdev->dev, 1);
3602         driver = &tegra_plat_xhci_driver;
3603
3604         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
3605         if (!hcd) {
3606                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
3607                 ret = -ENOMEM;
3608                 goto err_deinit_firmware;
3609         }
3610
3611         ret = tegra_xhci_request_mem_region(pdev, "host", &hcd->regs);
3612         if (ret) {
3613                 dev_err(&pdev->dev, "failed to map host\n");
3614                 goto err_put_usb2_hcd;
3615         }
3616         hcd->rsrc_start = res->start;
3617         hcd->rsrc_len = resource_size(res);
3618
3619         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "host");
3620         if (!res) {
3621                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
3622                 ret = -ENODEV;
3623                 goto err_put_usb2_hcd;
3624         }
3625         irq = res->start;
3626         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
3627         if (ret) {
3628                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
3629                 goto err_put_usb2_hcd;
3630         }
3631
3632         /* USB 2.0 roothub is stored in the platform_device now. */
3633         hcd = dev_get_drvdata(&pdev->dev);
3634         xhci = hcd_to_xhci(hcd);
3635         tegra->xhci = xhci;
3636         platform_set_drvdata(pdev, tegra);
3637
3638         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
3639                                                 dev_name(&pdev->dev), hcd);
3640         if (!xhci->shared_hcd) {
3641                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
3642                 ret = -ENOMEM;
3643                 goto err_remove_usb2_hcd;
3644         }
3645
3646         /*
3647          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
3648          * is called by usb_add_hcd().
3649          */
3650         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
3651
3652         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
3653         if (ret) {
3654                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
3655                 goto err_put_usb3_hcd;
3656         }
3657
3658         device_init_wakeup(&hcd->self.root_hub->dev, 1);
3659         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
3660         spin_lock_init(&tegra->lock);
3661         mutex_init(&tegra->sync_lock);
3662         mutex_init(&tegra->mbox_lock);
3663
3664         /* do mailbox related initializations */
3665         tegra->mbox_owner = 0xffff;
3666         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
3667
3668         tegra_xhci_enable_fw_message(tegra);
3669
3670         /* do ss partition elpg exit related initialization */
3671         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
3672
3673         /* do host partition elpg exit related initialization */
3674         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
3675
3676         /* Register interrupt handler for SMI line to handle mailbox
3677          * interrupt from firmware
3678          */
3679         ret = tegra_xhci_request_irq(pdev, "host-smi", tegra_xhci_smi_irq,
3680                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
3681         if (ret != 0)
3682                 goto err_remove_usb3_hcd;
3683
3684         /* Register interrupt handler for PADCTRL line to
3685          * handle wake on connect irqs interrupt from
3686          * firmware
3687          */
3688         ret = tegra_xhci_request_irq(pdev, "padctl", tegra_xhci_padctl_irq,
3689                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
3690                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
3691         if (ret != 0)
3692                 goto err_remove_usb3_hcd;
3693
3694         ret = tegra_xhci_request_irq(pdev, "usb3", tegra_xhci_xusb_host_irq,
3695                         IRQF_SHARED | IRQF_TRIGGER_HIGH, "xusb_host_irq",
3696                         &tegra->usb3_irq);
3697         if (ret != 0)
3698                 goto err_remove_usb3_hcd;
3699
3700         tegra->ss_pwr_gated = false;
3701         tegra->host_pwr_gated = false;
3702         tegra->hc_in_elpg = false;
3703         tegra->hs_wake_event = false;
3704         tegra->host_resume_req = false;
3705         tegra->lp0_exit = false;
3706         tegra->dfe_ctle_ctx_saved = false;
3707
3708         /* reset wake event to NONE */
3709         pmc_reg = tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0);
3710         pmc_reg |= UTMIP_WAKE_VAL(0, WAKE_VAL_NONE);
3711         pmc_reg |= UTMIP_WAKE_VAL(1, WAKE_VAL_NONE);
3712         pmc_reg |= UTMIP_WAKE_VAL(2, WAKE_VAL_NONE);
3713         pmc_reg |= UTMIP_WAKE_VAL(3, WAKE_VAL_NONE);
3714         tegra_usb_pmc_reg_write(PMC_UTMIP_UHSIC_SLEEP_CFG_0, pmc_reg);
3715
3716         tegra_xhci_debug_read_pads(tegra);
3717         utmi_phy_pad_enable();
3718         utmi_phy_iddq_override(false);
3719
3720         tegra_pd_add_device(&pdev->dev);
3721
3722         return 0;
3723
3724 err_remove_usb3_hcd:
3725         usb_remove_hcd(xhci->shared_hcd);
3726 err_put_usb3_hcd:
3727         usb_put_hcd(xhci->shared_hcd);
3728 err_remove_usb2_hcd:
3729         kfree(tegra->xhci);
3730         usb_remove_hcd(hcd);
3731 err_put_usb2_hcd:
3732         usb_put_hcd(hcd);
3733 err_deinit_firmware:
3734         deinit_firmware(tegra);
3735 err_deinit_usb2_clocks:
3736         tegra_usb2_clocks_deinit(tegra);
3737 err_deinit_tegra_xusb_regulator:
3738         tegra_xusb_regulator_deinit(tegra);
3739 err_deinit_xusb_partition_clk:
3740         tegra_xusb_partitions_clk_deinit(tegra);
3741
3742         return ret;
3743 }
3744
3745 static int tegra_xhci_remove(struct platform_device *pdev)
3746 {
3747         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3748         struct xhci_hcd *xhci = NULL;
3749         struct usb_hcd *hcd = NULL;
3750
3751         if (tegra == NULL)
3752                 return -EINVAL;
3753
3754         xhci = tegra->xhci;
3755         hcd = xhci_to_hcd(xhci);
3756
3757         devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
3758         devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
3759         devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
3760         usb_remove_hcd(xhci->shared_hcd);
3761         usb_put_hcd(xhci->shared_hcd);
3762         usb_remove_hcd(hcd);
3763         usb_put_hcd(hcd);
3764         kfree(xhci);
3765
3766         deinit_firmware(tegra);
3767         fw_log_deinit(tegra);
3768         tegra_xusb_regulator_deinit(tegra);
3769         tegra_usb2_clocks_deinit(tegra);
3770         if (!tegra->hc_in_elpg)
3771                 tegra_xusb_partitions_clk_deinit(tegra);
3772         utmi_phy_pad_disable();
3773         utmi_phy_iddq_override(true);
3774
3775         return 0;
3776 }
3777
3778 static void tegra_xhci_shutdown(struct platform_device *pdev)
3779 {
3780         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3781         struct xhci_hcd *xhci = NULL;
3782         struct usb_hcd *hcd = NULL;
3783
3784         if (tegra == NULL)
3785                 return;
3786
3787         if (tegra->hc_in_elpg) {
3788                 mutex_lock(&tegra->sync_lock);
3789                 pmc_init(tegra, 0);
3790                 mutex_unlock(&tegra->sync_lock);
3791         } else {
3792                 xhci = tegra->xhci;
3793                 hcd = xhci_to_hcd(xhci);
3794                 xhci_shutdown(hcd);
3795         }
3796 }
3797
3798 static struct platform_driver tegra_xhci_driver = {
3799         .probe  = tegra_xhci_probe,
3800         .remove = tegra_xhci_remove,
3801         .shutdown = tegra_xhci_shutdown,
3802 #ifdef CONFIG_PM
3803         .suspend = tegra_xhci_suspend,
3804         .resume  = tegra_xhci_resume,
3805 #endif
3806         .driver = {
3807                 .name = "tegra-xhci",
3808         },
3809 };
3810 MODULE_ALIAS("platform:tegra-xhci");
3811
3812 int tegra_xhci_register_plat(void)
3813 {
3814         return platform_driver_register(&tegra_xhci_driver);
3815 }
3816
3817 void tegra_xhci_unregister_plat(void)
3818 {
3819         platform_driver_unregister(&tegra_xhci_driver);
3820 }