xhci: tegra: support HSIC ports
[linux-3.10.git] / drivers / usb / host / xhci-tegra.c
1 /*
2  * xhci-tegra.c - Nvidia xHCI host controller driver
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/clk.h>
24 #include <linux/ioport.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/irq.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/uaccess.h>
30 #include <linux/circ_buf.h>
31 #include <linux/vmalloc.h>
32 #include <linux/debugfs.h>
33 #include <linux/kthread.h>
34 #include <linux/gpio.h>
35
36 #include <mach/powergate.h>
37 #include <mach/clk.h>
38 #include <mach/tegra_usb_pad_ctrl.h>
39 #include <mach/tegra_usb_pmc.h>
40 #include <mach/pm_domains.h>
41 #include <mach/mc.h>
42 #include <mach/xusb.h>
43
44 #include "../../../arch/arm/mach-tegra/iomap.h" /* HACK -- remove */
45 #include "xhci-tegra.h"
46 #include "xhci.h"
47
48 /* macros */
49 #define FW_IOCTL_LOG_DEQUEUE_LOW        (4)
50 #define FW_IOCTL_LOG_DEQUEUE_HIGH       (5)
51 #define FW_IOCTL_DATA_SHIFT             (0)
52 #define FW_IOCTL_DATA_MASK              (0x00ffffff)
53 #define FW_IOCTL_TYPE_SHIFT             (24)
54 #define FW_IOCTL_TYPE_MASK              (0xff000000)
55 #define FW_LOG_SIZE                     (sizeof(struct log_entry))
56 #define FW_LOG_COUNT                    (4096)
57 #define FW_LOG_RING_SIZE                (FW_LOG_SIZE * FW_LOG_COUNT)
58 #define FW_LOG_PAYLOAD_SIZE             (27)
59 #define DRIVER                          (0x01)
60 #define CIRC_BUF_SIZE                   (4 * (1 << 20)) /* 4MB */
61 #define FW_LOG_THREAD_RELAX             (msecs_to_jiffies(100))
62
63 /* tegra_xhci_firmware_log.flags bits */
64 #define FW_LOG_CONTEXT_VALID            (0)
65 #define FW_LOG_FILE_OPENED              (1)
66
67 #define PAGE_SELECT_MASK                        0xFFFFFE00
68 #define PAGE_SELECT_SHIFT                       9
69 #define PAGE_OFFSET_MASK                        0x000001FF
70 #define CSB_PAGE_SELECT(_addr)                                          \
71         ({                                                              \
72                 typecheck(u32, _addr);                                  \
73                 ((_addr & PAGE_SELECT_MASK) >> PAGE_SELECT_SHIFT);      \
74         })
75 #define CSB_PAGE_OFFSET(_addr)                                          \
76         ({                                                              \
77                 typecheck(u32, _addr);                                  \
78                 (_addr & PAGE_OFFSET_MASK);                             \
79         })
80
81 #define reg_dump(_dev, _base, _reg)                                     \
82         dev_dbg(_dev, "%s: %s @%x = 0x%x\n", __func__, #_reg,           \
83                 _reg, readl(_base + _reg))
84
85 /* PMC register definition */
86 #define PMC_PORT_UTMIP_P0               0
87 #define PMC_PORT_UTMIP_P1               1
88 #define PMC_PORT_UTMIP_P2               2
89 #define PMC_PORT_UHSIC_P0               3
90 #define PMC_PORT_NUM                    4
91
92 #define PMC_USB_DEBOUNCE_DEL_0                  0xec
93 #define   UTMIP_LINE_DEB_CNT(x)         (((x) & 0xf) << 16)
94 #define   UTMIP_LINE_DEB_CNT_MASK               (0xf << 16)
95
96 #define PMC_UTMIP_UHSIC_SLEEP_CFG_0             0x1fc
97
98 /* private data types */
99 /* command requests from the firmware */
100 enum MBOX_CMD_TYPE {
101         MBOX_CMD_MSG_ENABLED = 1,
102         MBOX_CMD_INC_FALC_CLOCK,
103         MBOX_CMD_DEC_FALC_CLOCK,
104         MBOX_CMD_INC_SSPI_CLOCK,
105         MBOX_CMD_DEC_SSPI_CLOCK, /* 5 */
106         MBOX_CMD_SET_BW,
107         MBOX_CMD_SET_SS_PWR_GATING,
108         MBOX_CMD_SET_SS_PWR_UNGATING, /* 8 */
109         MBOX_CMD_SAVE_DFE_CTLE_CTX,
110         MBOX_CMD_AIRPLANE_MODE_ENABLED,
111         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* 11 */
112         MBOX_CMD_STAR_HSIC_IDLE,
113         MBOX_CMD_STOP_HSIC_IDLE,
114
115         /* needs to be the last cmd */
116         MBOX_CMD_MAX,
117
118         /* resp msg to ack above commands */
119         MBOX_CMD_ACK = 128,
120         MBOX_CMD_NACK
121 };
122
123 struct log_entry {
124         u32 sequence_no;
125         u8 data[FW_LOG_PAYLOAD_SIZE];
126         u8 owner;
127 };
128
129 /* Usb3 Firmware Cfg Table */
130 struct cfgtbl {
131         u32 boot_loadaddr_in_imem;
132         u32 boot_codedfi_offset;
133         u32 boot_codetag;
134         u32 boot_codesize;
135
136         /* Physical memory reserved by Bootloader/BIOS */
137         u32 phys_memaddr;
138         u16 reqphys_memsize;
139         u16 alloc_phys_memsize;
140
141         /* .rodata section */
142         u32 rodata_img_offset;
143         u32 rodata_section_start;
144         u32 rodata_section_end;
145         u32 main_fnaddr;
146
147         u32 fwimg_cksum;
148         u32 fwimg_created_time;
149
150         /* Fields that get filled by linker during linking phase
151          * or initialized in the FW code.
152          */
153         u32 imem_resident_start;
154         u32 imem_resident_end;
155         u32 idirect_start;
156         u32 idirect_end;
157         u32 l2_imem_start;
158         u32 l2_imem_end;
159         u32 version_id;
160         u8 init_ddirect;
161         u8 reserved[3];
162         u32 phys_addr_log_buffer;
163         u32 total_log_entries;
164         u32 dequeue_ptr;
165
166         /*      Below two dummy variables are used to replace
167          *      L2IMemSymTabOffsetInDFI and L2IMemSymTabSize in order to
168          *      retain the size of struct _CFG_TBL used by other AP/Module.
169          */
170         u32 dummy_var1;
171         u32 dummy_var2;
172
173         /* fwimg_len */
174         u32 fwimg_len;
175         u8 magic[8];
176         u32 SS_low_power_entry_timeout;
177         u8 num_hsic_port;
178         u8 padding[139]; /* padding bytes to makeup 256-bytes cfgtbl */
179 };
180
181 struct xusb_save_regs {
182         u32 msi_bar_sz;
183         u32 msi_axi_barst;
184         u32 msi_fpci_barst;
185         u32 msi_vec0;
186         u32 msi_en_vec0;
187         u32 fpci_error_masks;
188         u32 intr_mask;
189         u32 ipfs_intr_enable;
190         u32 ufpci_config;
191         u32 clkgate_hysteresis;
192         u32 xusb_host_mccif_fifo_cntrl;
193
194         /* PG does not mention below */
195         u32 hs_pls;
196         u32 fs_pls;
197         u32 hs_fs_speed;
198         u32 hs_fs_pp;
199         u32 cfg_aru;
200         u32 cfg_order;
201         u32 cfg_fladj;
202         u32 cfg_sid;
203         /* DFE and CTLE */
204         u32 tap1_val[2];
205         u32 amp_val[2];
206         u32 ctle_z_val[2];
207         u32 ctle_g_val[2];
208 };
209
210 struct tegra_xhci_firmware {
211         void *data; /* kernel virtual address */
212         size_t size; /* firmware size */
213         dma_addr_t dma; /* dma address for controller */
214 };
215
216 struct tegra_xhci_firmware_log {
217         dma_addr_t phys_addr;           /* dma-able address */
218         void *virt_addr;                /* kernel va of the shared log buffer */
219         struct log_entry *dequeue;      /* current dequeue pointer (va) */
220         struct circ_buf circ;           /* big circular buffer */
221         u32 seq;                        /* log sequence number */
222
223         struct task_struct *thread;     /* a thread to consume log */
224         struct mutex mutex;
225         wait_queue_head_t read_wait;
226         wait_queue_head_t write_wait;
227         wait_queue_head_t intr_wait;
228         struct dentry *path;
229         struct dentry *log_file;
230         unsigned long flags;
231 };
232
233 /* structure to hold the offsets of padctl registers */
234 struct tegra_xusb_padctl_regs {
235         u16 boot_media_0;
236         u16 usb2_pad_mux_0;
237         u16 usb2_port_cap_0;
238         u16 snps_oc_map_0;
239         u16 usb2_oc_map_0;
240         u16 ss_port_map_0;
241         u16 oc_det_0;
242         u16 elpg_program_0;
243         u16 usb2_bchrg_otgpad0_ctl0_0;
244         u16 usb2_bchrg_otgpad0_ctl1_0;
245         u16 usb2_bchrg_otgpad1_ctl0_0;
246         u16 usb2_bchrg_otgpad1_ctl1_0;
247         u16 usb2_bchrg_otgpad2_ctl0_0;
248         u16 usb2_bchrg_otgpad2_ctl1_0;
249         u16 usb2_bchrg_bias_pad_0;
250         u16 usb2_bchrg_tdcd_dbnc_timer_0;
251         u16 iophy_pll_p0_ctl1_0;
252         u16 iophy_pll_p0_ctl2_0;
253         u16 iophy_pll_p0_ctl3_0;
254         u16 iophy_pll_p0_ctl4_0;
255         u16 iophy_usb3_pad0_ctl1_0;
256         u16 iophy_usb3_pad1_ctl1_0;
257         u16 iophy_usb3_pad0_ctl2_0;
258         u16 iophy_usb3_pad1_ctl2_0;
259         u16 iophy_usb3_pad0_ctl3_0;
260         u16 iophy_usb3_pad1_ctl3_0;
261         u16 iophy_usb3_pad0_ctl4_0;
262         u16 iophy_usb3_pad1_ctl4_0;
263         u16 iophy_misc_pad_p0_ctl1_0;
264         u16 iophy_misc_pad_p1_ctl1_0;
265         u16 iophy_misc_pad_p0_ctl2_0;
266         u16 iophy_misc_pad_p1_ctl2_0;
267         u16 iophy_misc_pad_p0_ctl3_0;
268         u16 iophy_misc_pad_p1_ctl3_0;
269         u16 iophy_misc_pad_p0_ctl4_0;
270         u16 iophy_misc_pad_p1_ctl4_0;
271         u16 iophy_misc_pad_p0_ctl5_0;
272         u16 iophy_misc_pad_p1_ctl5_0;
273         u16 iophy_misc_pad_p0_ctl6_0;
274         u16 iophy_misc_pad_p1_ctl6_0;
275         u16 usb2_otg_pad0_ctl0_0;
276         u16 usb2_otg_pad1_ctl0_0;
277         u16 usb2_otg_pad2_ctl0_0;
278         u16 usb2_otg_pad0_ctl1_0;
279         u16 usb2_otg_pad1_ctl1_0;
280         u16 usb2_otg_pad2_ctl1_0;
281         u16 usb2_bias_pad_ctl0_0;
282         u16 usb2_bias_pad_ctl1_0;
283         u16 usb2_hsic_pad0_ctl0_0;
284         u16 usb2_hsic_pad1_ctl0_0;
285         u16 usb2_hsic_pad0_ctl1_0;
286         u16 usb2_hsic_pad1_ctl1_0;
287         u16 usb2_hsic_pad0_ctl2_0;
288         u16 usb2_hsic_pad1_ctl2_0;
289         u16 ulpi_link_trim_ctl0;
290         u16 ulpi_null_clk_trim_ctl0;
291         u16 hsic_strb_trim_ctl0;
292         u16 wake_ctl0;
293         u16 pm_spare0;
294         u16 iophy_misc_pad_p2_ctl1_0;
295         u16 iophy_misc_pad_p3_ctl1_0;
296         u16 iophy_misc_pad_p4_ctl1_0;
297         u16 iophy_misc_pad_p2_ctl2_0;
298         u16 iophy_misc_pad_p3_ctl2_0;
299         u16 iophy_misc_pad_p4_ctl2_0;
300         u16 iophy_misc_pad_p2_ctl3_0;
301         u16 iophy_misc_pad_p3_ctl3_0;
302         u16 iophy_misc_pad_p4_ctl3_0;
303         u16 iophy_misc_pad_p2_ctl4_0;
304         u16 iophy_misc_pad_p3_ctl4_0;
305         u16 iophy_misc_pad_p4_ctl4_0;
306         u16 iophy_misc_pad_p2_ctl5_0;
307         u16 iophy_misc_pad_p3_ctl5_0;
308         u16 iophy_misc_pad_p4_ctl5_0;
309         u16 iophy_misc_pad_p2_ctl6_0;
310         u16 iophy_misc_pad_p3_ctl6_0;
311         u16 iophy_misc_pad_p4_ctl6_0;
312         u16 usb3_pad_mux_0;
313         u16 iophy_pll_s0_ctl1_0;
314         u16 iophy_pll_s0_ctl2_0;
315         u16 iophy_pll_s0_ctl3_0;
316         u16 iophy_pll_s0_ctl4_0;
317         u16 iophy_misc_pad_s0_ctl1_0;
318         u16 iophy_misc_pad_s0_ctl2_0;
319         u16 iophy_misc_pad_s0_ctl3_0;
320         u16 iophy_misc_pad_s0_ctl4_0;
321         u16 iophy_misc_pad_s0_ctl5_0;
322         u16 iophy_misc_pad_s0_ctl6_0;
323 };
324
325 struct tegra_xhci_hcd {
326         struct platform_device *pdev;
327         struct xhci_hcd *xhci;
328         u16 device_id;
329
330         spinlock_t lock;
331         struct mutex sync_lock;
332
333         int smi_irq;
334         int padctl_irq;
335         int usb3_irq;
336         int usb2_irq;
337
338         bool ss_wake_event;
339         bool ss_pwr_gated;
340         bool host_pwr_gated;
341         bool hs_wake_event;
342         bool host_resume_req;
343         bool lp0_exit;
344         bool dfe_ctle_ctx_saved;
345         unsigned long last_jiffies;
346         unsigned long host_phy_base;
347         void __iomem *host_phy_virt_base;
348
349         void __iomem *padctl_base;
350         void __iomem *fpci_base;
351         void __iomem *ipfs_base;
352
353         struct tegra_xusb_platform_data *pdata;
354         struct tegra_xusb_board_data *bdata;
355         struct tegra_xusb_padctl_regs *padregs;
356
357         /* mailbox variables */
358         struct mutex mbox_lock;
359         u32 mbox_owner;
360         u32 cmd_type;
361         u32 cmd_data;
362
363         struct regulator *xusb_s5p0v_reg;
364         struct regulator *xusb_s5p0v1_reg;
365         struct regulator *xusb_s5p0v2_reg;
366         struct regulator *xusb_s1p05v_reg;
367         struct regulator *xusb_s3p3v_reg;
368         struct regulator *xusb_s1p8v_reg;
369         struct regulator *vddio_hsic_reg;
370         int vddio_hsic_refcnt;
371
372         struct work_struct mbox_work;
373         struct work_struct ss_elpg_exit_work;
374         struct work_struct host_elpg_exit_work;
375
376         struct clk *host_clk;
377         struct clk *ss_clk;
378
379         /* XUSB Falcon SuperSpeed Clock */
380         struct clk *falc_clk;
381
382         /* EMC Clock */
383         struct clk *emc_clk;
384         /* XUSB SS PI Clock */
385         struct clk *ss_src_clk;
386         /* PLLE Clock */
387         struct clk *plle_clk;
388         struct clk *pll_u_480M;
389         struct clk *clk_m;
390         /* refPLLE clk */
391         struct clk *pll_re_vco_clk;
392         /*
393          * XUSB/IPFS specific registers these need to be saved/restored in
394          * addition to spec defined registers
395          */
396         struct xusb_save_regs sregs;
397         bool usb2_rh_suspend;
398         bool usb3_rh_suspend;
399         bool hc_in_elpg;
400
401         unsigned long usb3_rh_remote_wakeup_ports; /* one bit per port */
402         /* firmware loading related */
403         struct tegra_xhci_firmware firmware;
404
405         struct tegra_xhci_firmware_log log;
406 };
407
408 static struct tegra_usb_pmc_data pmc_data;
409 static struct tegra_usb_pmc_data pmc_hsic_data[XUSB_HSIC_COUNT];
410
411 /* functions */
412 static inline struct tegra_xhci_hcd *hcd_to_tegra_xhci(struct usb_hcd *hcd)
413 {
414         return (struct tegra_xhci_hcd *) dev_get_drvdata(hcd->self.controller);
415 }
416
417 #if defined(CONFIG_DEBUG_MUTEXES) || defined(CONFIG_SMP)
418 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
419 {
420         WARN_ON(tegra->sync_lock.owner != current);
421 }
422 #else
423 static inline void must_have_sync_lock(struct tegra_xhci_hcd *tegra)
424 #endif
425
426 static void tegra_xhci_setup_gpio_for_ss_lane(struct tegra_xhci_hcd *tegra)
427 {
428         int err = 0;
429
430         if (!tegra->bdata->gpio_controls_muxed_ss_lanes)
431                 return;
432
433         if (tegra->bdata->lane_owner & BIT(0)) {
434                 /* USB3_SS port1 is using SATA lane so set (MUX_SATA)
435                  * GPIO P11 to '0'
436                  */
437                 err = gpio_request((tegra->bdata->gpio_ss1_sata & 0xffff),
438                         "gpio_ss1_sata");
439                 if (err < 0)
440                         pr_err("%s: gpio_ss1_sata gpio_request failed %d\n",
441                                 __func__, err);
442                 err = gpio_direction_output((tegra->bdata->gpio_ss1_sata
443                         & 0xffff), 1);
444                 if (err < 0)
445                         pr_err("%s: gpio_ss1_sata gpio_direction failed %d\n",
446                                 __func__, err);
447                 __gpio_set_value((tegra->bdata->gpio_ss1_sata & 0xffff),
448                                 ((tegra->bdata->gpio_ss1_sata >> 16)));
449         }
450 }
451
452 static u32 xhci_read_portsc(struct xhci_hcd *xhci, unsigned int port)
453 {
454         int num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
455         __le32 __iomem *addr;
456
457         if (port >= num_ports) {
458                 xhci_err(xhci, "%s invalid port %u\n", __func__, port);
459                 return -1;
460         }
461
462         addr = &xhci->op_regs->port_status_base + (NUM_PORT_REGS * port);
463         return xhci_readl(xhci, addr);
464 }
465
466 static void debug_print_portsc(struct xhci_hcd *xhci)
467 {
468         __le32 __iomem *addr = &xhci->op_regs->port_status_base;
469         u32 reg;
470         int i;
471         int ports;
472
473         ports = HCS_MAX_PORTS(xhci->hcs_params1);
474         for (i = 0; i < ports; i++) {
475                 reg = xhci_read_portsc(xhci, i);
476                 xhci_dbg(xhci, "@%p port %d status reg = 0x%x\n",
477                                 addr, i, (unsigned int) reg);
478                 addr += NUM_PORT_REGS;
479         }
480 }
481 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra);
482
483 static void update_speed(struct tegra_xhci_hcd *tegra, u8 port, bool setup_wake)
484 {
485         struct usb_hcd *hcd = xhci_to_hcd(tegra->xhci);
486         u32 portsc;
487
488         /* we don't need speed information to disable PMC */
489         if (!setup_wake)
490                 return;
491
492         portsc = readl(hcd->regs + BAR0_XHCI_OP_PORTSC(port));
493         if (DEV_FULLSPEED(portsc))
494                 pmc_data.port_speed = USB_PMC_PORT_SPEED_FULL;
495         else if (DEV_HIGHSPEED(portsc))
496                 pmc_data.port_speed = USB_PMC_PORT_SPEED_HIGH;
497         else if (DEV_LOWSPEED(portsc))
498                 pmc_data.port_speed = USB_PMC_PORT_SPEED_LOW;
499         else if (DEV_SUPERSPEED(portsc))
500                 pmc_data.port_speed = USB_PMC_PORT_SPEED_SUPER;
501         else
502                 pmc_data.port_speed = USB_PMC_PORT_SPEED_UNKNOWN;
503 }
504
505 static void setup_wake_detect(bool setup_wake)
506 {
507         if (setup_wake)
508                 pmc_data.pmc_ops->setup_pmc_wake_detect(&pmc_data);
509         else
510                 pmc_data.pmc_ops->disable_pmc_bus_ctrl(&pmc_data, 0);
511 }
512
513 static void pmc_setup(struct tegra_xhci_hcd *tegra, bool setup_wake)
514 {
515         u32 portmap = tegra->bdata->portmap;
516
517         pmc_data.controller_type = TEGRA_USB_3_0;
518         if (portmap & TEGRA_XUSB_USB2_P0) {
519                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 0) & 0xf;
520                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
521                 update_speed(tegra, pmc_data.instance, setup_wake);
522                 tegra_usb_pmc_init(&pmc_data);
523                 setup_wake_detect(setup_wake);
524         }
525         if (portmap & TEGRA_XUSB_USB2_P1) {
526                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 4) & 0xf;
527                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
528                 update_speed(tegra, pmc_data.instance, setup_wake);
529                 tegra_usb_pmc_init(&pmc_data);
530                 setup_wake_detect(setup_wake);
531         }
532         if (portmap & TEGRA_XUSB_USB2_P2) {
533                 pmc_data.instance = (tegra->pdata->pmc_portmap >> 8) & 0xf;
534                 pmc_data.phy_type = TEGRA_USB_PHY_INTF_UTMI;
535                 update_speed(tegra, pmc_data.instance, setup_wake);
536                 tegra_usb_pmc_init(&pmc_data);
537                 setup_wake_detect(setup_wake);
538         }
539 }
540
541 static void pmc_init(struct tegra_xhci_hcd *tegra)
542 {
543         struct tegra_usb_pmc_data *pmc;
544         struct device *dev = &tegra->pdev->dev;
545         int pad;
546
547         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
548                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap) {
549                         dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
550
551                         pmc = &pmc_hsic_data[pad];
552                         pmc->instance = pad + 1;
553                         pmc->phy_type = TEGRA_USB_PHY_INTF_HSIC;
554                         pmc->port_speed = USB_PMC_PORT_SPEED_HIGH;
555                         pmc->controller_type = TEGRA_USB_3_0;
556                         tegra_usb_pmc_init(pmc);
557                 }
558         }
559
560 }
561
562 static void pmc_setup_wake_detect(struct tegra_xhci_hcd *tegra)
563 {
564         struct tegra_usb_pmc_data *pmc;
565         struct device *dev = &tegra->pdev->dev;
566         u32 portsc;
567         int port;
568         int pad;
569
570         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
571                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap) {
572                         dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
573
574                         pmc = &pmc_hsic_data[pad];
575                         port = hsic_pad_to_port(pad);
576                         portsc = xhci_read_portsc(tegra->xhci, port);
577                         dev_dbg(dev, "%s hsic pad %d portsc 0x%x\n",
578                                         __func__, pad, portsc);
579
580                         if (((int) portsc != -1) && (portsc & PORT_CONNECT))
581                                 pmc->pmc_ops->setup_pmc_wake_detect(pmc);
582                 }
583         }
584 }
585
586 static void pmc_disable_bus_ctrl(struct tegra_xhci_hcd *tegra)
587 {
588         struct tegra_usb_pmc_data *pmc;
589         struct device *dev = &tegra->pdev->dev;
590         int pad;
591
592         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
593                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap) {
594                         dev_dbg(dev, "%s hsic pad %d\n", __func__, pad);
595
596                         pmc = &pmc_hsic_data[pad];
597                         pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 0);
598                 }
599         }
600 }
601
602 u32 csb_read(struct tegra_xhci_hcd *tegra, u32 addr)
603 {
604         void __iomem *fpci_base = tegra->fpci_base;
605         struct platform_device *pdev = tegra->pdev;
606         u32 input_addr;
607         u32 data;
608         u32 csb_page_select;
609
610         /* to select the appropriate CSB page to write to */
611         csb_page_select = CSB_PAGE_SELECT(addr);
612
613         dev_dbg(&pdev->dev, "csb_read: csb_page_select= 0x%08x\n",
614                         csb_page_select);
615
616         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
617
618         /* selects the appropriate offset in the page to read from */
619         input_addr = CSB_PAGE_OFFSET(addr);
620         data = ioread32(fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
621
622         dev_dbg(&pdev->dev, "csb_read: input_addr = 0x%08x data = 0x%08x\n",
623                         input_addr, data);
624         return data;
625 }
626
627 void csb_write(struct tegra_xhci_hcd *tegra, u32 addr, u32 data)
628 {
629         void __iomem *fpci_base = tegra->fpci_base;
630         struct platform_device *pdev = tegra->pdev;
631         u32 input_addr;
632         u32 csb_page_select;
633
634         /* to select the appropriate CSB page to write to */
635         csb_page_select = CSB_PAGE_SELECT(addr);
636
637         dev_dbg(&pdev->dev, "csb_write:csb_page_selectx = 0x%08x\n",
638                         csb_page_select);
639
640         iowrite32(csb_page_select, fpci_base + XUSB_CFG_ARU_C11_CSBRANGE);
641
642         /* selects the appropriate offset in the page to write to */
643         input_addr = CSB_PAGE_OFFSET(addr);
644         iowrite32(data, fpci_base + XUSB_CFG_CSB_BASE_ADDR + input_addr);
645
646         dev_dbg(&pdev->dev, "csb_write: input_addr = 0x%08x data = %0x08x\n",
647                         input_addr, data);
648 }
649
650 /**
651  * fw_log_next - find next log entry in a tegra_xhci_firmware_log context.
652  *      This function takes care of wrapping. That means when current log entry
653  *      is the last one, it returns with the first one.
654  *
655  * @param log   The tegra_xhci_firmware_log context.
656  * @param this  The current log entry.
657  * @return      The log entry which is next to the current one.
658  */
659 static inline struct log_entry *fw_log_next(
660                 struct tegra_xhci_firmware_log *log, struct log_entry *this)
661 {
662         struct log_entry *first = (struct log_entry *) log->virt_addr;
663         struct log_entry *last = first + FW_LOG_COUNT - 1;
664
665         WARN((this < first) || (this > last), "%s: invalid input\n", __func__);
666
667         return (this == last) ? first : (this + 1);
668 }
669
670 /**
671  * fw_log_update_dequeue_pointer - update dequeue pointer to both firmware and
672  *      tegra_xhci_firmware_log.dequeue.
673  *
674  * @param log   The tegra_xhci_firmware_log context.
675  * @param n     Counts of log entries to fast-forward.
676  */
677 static inline void fw_log_update_deq_pointer(
678                 struct tegra_xhci_firmware_log *log, int n)
679 {
680         struct tegra_xhci_hcd *tegra =
681                         container_of(log, struct tegra_xhci_hcd, log);
682         struct device *dev = &tegra->pdev->dev;
683         struct log_entry *deq = tegra->log.dequeue;
684         dma_addr_t physical_addr;
685         u32 reg;
686
687         dev_dbg(dev, "curr 0x%p fast-forward %d entries\n", deq, n);
688         while (n-- > 0)
689                 deq = fw_log_next(log, deq);
690
691         tegra->log.dequeue = deq;
692         physical_addr = tegra->log.phys_addr +
693                         ((u8 *)deq - (u8 *)tegra->log.virt_addr);
694
695         /* update dequeue pointer to firmware */
696         reg = (FW_IOCTL_LOG_DEQUEUE_LOW << FW_IOCTL_TYPE_SHIFT);
697         reg |= (physical_addr & 0xffff); /* lower 16-bits */
698         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
699
700         reg = (FW_IOCTL_LOG_DEQUEUE_HIGH << FW_IOCTL_TYPE_SHIFT);
701         reg |= ((physical_addr >> 16) & 0xffff); /* higher 16-bits */
702         iowrite32(reg, tegra->fpci_base + XUSB_CFG_ARU_FW_SCRATCH);
703
704         dev_dbg(dev, "new 0x%p physical addr 0x%x\n", deq, physical_addr);
705 }
706
707 static inline bool circ_buffer_full(struct circ_buf *circ)
708 {
709         int space = CIRC_SPACE(circ->head, circ->tail, CIRC_BUF_SIZE);
710
711         return (space <= FW_LOG_SIZE);
712 }
713
714 static inline bool fw_log_available(struct tegra_xhci_hcd *tegra)
715 {
716         return (tegra->log.dequeue->owner == DRIVER);
717 }
718
719 /**
720  * fw_log_wait_empty_timeout - wait firmware log thread to clean up shared
721  *      log buffer.
722  * @param tegra:        tegra_xhci_hcd context
723  * @param msec:         timeout value in millisecond
724  * @return true:        shared log buffer is empty,
725  *         false:       shared log buffer isn't empty.
726  */
727 static inline bool fw_log_wait_empty_timeout(struct tegra_xhci_hcd *tegra,
728                 unsigned timeout)
729 {
730         u32 target = jiffies + msecs_to_jiffies(timeout);
731         bool ret;
732
733         mutex_lock(&tegra->log.mutex);
734
735         while (fw_log_available(tegra) && time_is_after_jiffies(target)) {
736                 mutex_unlock(&tegra->log.mutex);
737                 usleep_range(1000, 2000);
738                 mutex_lock(&tegra->log.mutex);
739         }
740
741         ret = fw_log_available(tegra);
742         mutex_unlock(&tegra->log.mutex);
743
744         return ret;
745 }
746
747 /**
748  * fw_log_copy - copy firmware log from device's buffer to driver's circular
749  *      buffer.
750  * @param tegra tegra_xhci_hcd context
751  * @return true,        We still have firmware log in device's buffer to copy.
752  *                      This function returned due the driver's circular buffer
753  *                      is full. Caller should invoke this function again as
754  *                      soon as there is space in driver's circular buffer.
755  *         false,       Device's buffer is empty.
756  */
757 static inline bool fw_log_copy(struct tegra_xhci_hcd *tegra)
758 {
759         struct device *dev = &tegra->pdev->dev;
760         struct circ_buf *circ = &tegra->log.circ;
761         int head, tail;
762         int buffer_len, copy_len;
763         struct log_entry *entry;
764         struct log_entry *first = tegra->log.virt_addr;
765
766         while (fw_log_available(tegra)) {
767
768                 /* calculate maximum contiguous driver buffer length */
769                 head = circ->head;
770                 tail = ACCESS_ONCE(circ->tail);
771                 buffer_len = CIRC_SPACE_TO_END(head, tail, CIRC_BUF_SIZE);
772                 /* round down to FW_LOG_SIZE */
773                 buffer_len -= (buffer_len % FW_LOG_SIZE);
774                 if (!buffer_len)
775                         return true; /* log available but no space left */
776
777                 /* calculate maximum contiguous log copy length */
778                 entry = tegra->log.dequeue;
779                 copy_len = 0;
780                 do {
781                         if (tegra->log.seq != entry->sequence_no) {
782                                 dev_warn(dev,
783                                 "%s: discontinuous seq no, expect %u get %u\n",
784                                 __func__, tegra->log.seq, entry->sequence_no);
785                         }
786                         tegra->log.seq = entry->sequence_no + 1;
787
788                         copy_len += FW_LOG_SIZE;
789                         buffer_len -= FW_LOG_SIZE;
790                         if (!buffer_len)
791                                 break; /* no space left */
792                         entry = fw_log_next(&tegra->log, entry);
793                 } while ((entry->owner == DRIVER) && (entry != first));
794
795                 memcpy(&circ->buf[head], tegra->log.dequeue, copy_len);
796                 memset(tegra->log.dequeue, 0, copy_len);
797                 circ->head = (circ->head + copy_len) & (CIRC_BUF_SIZE - 1);
798
799                 mb();
800
801                 fw_log_update_deq_pointer(&tegra->log, copy_len/FW_LOG_SIZE);
802
803                 dev_dbg(dev, "copied %d entries, new dequeue 0x%p\n",
804                                 copy_len/FW_LOG_SIZE, tegra->log.dequeue);
805                 wake_up_interruptible(&tegra->log.read_wait);
806         }
807
808         return false;
809 }
810
811 static int fw_log_thread(void *data)
812 {
813         struct tegra_xhci_hcd *tegra = data;
814         struct device *dev = &tegra->pdev->dev;
815         struct circ_buf *circ = &tegra->log.circ;
816         bool logs_left;
817
818         dev_dbg(dev, "start firmware log thread\n");
819
820         do {
821                 mutex_lock(&tegra->log.mutex);
822                 if (circ_buffer_full(circ)) {
823                         mutex_unlock(&tegra->log.mutex);
824                         dev_info(dev, "%s: circ buffer full\n", __func__);
825                         wait_event_interruptible(tegra->log.write_wait,
826                             kthread_should_stop() || !circ_buffer_full(circ));
827                         mutex_lock(&tegra->log.mutex);
828                 }
829
830                 logs_left = fw_log_copy(tegra);
831                 mutex_unlock(&tegra->log.mutex);
832
833                 /* relax if no logs left  */
834                 if (!logs_left)
835                         wait_event_interruptible_timeout(tegra->log.intr_wait,
836                                 fw_log_available(tegra), FW_LOG_THREAD_RELAX);
837         } while (!kthread_should_stop());
838
839         dev_dbg(dev, "stop firmware log thread\n");
840         return 0;
841 }
842
843 static inline bool circ_buffer_empty(struct circ_buf *circ)
844 {
845         return (CIRC_CNT(circ->head, circ->tail, CIRC_BUF_SIZE) == 0);
846 }
847
848 static ssize_t fw_log_file_read(struct file *file, char __user *buf,
849                 size_t count, loff_t *offp)
850 {
851         struct tegra_xhci_hcd *tegra = file->private_data;
852         struct platform_device *pdev = tegra->pdev;
853         struct circ_buf *circ = &tegra->log.circ;
854         int head, tail;
855         size_t n = 0;
856         int s;
857
858         mutex_lock(&tegra->log.mutex);
859
860         while (circ_buffer_empty(circ)) {
861                 mutex_unlock(&tegra->log.mutex);
862                 if (file->f_flags & O_NONBLOCK)
863                         return -EAGAIN; /* non-blocking read */
864
865                 dev_dbg(&pdev->dev, "%s: nothing to read\n", __func__);
866
867                 if (wait_event_interruptible(tegra->log.read_wait,
868                                 !circ_buffer_empty(circ)))
869                         return -ERESTARTSYS;
870
871                 if (mutex_lock_interruptible(&tegra->log.mutex))
872                         return -ERESTARTSYS;
873         }
874
875         while (count > 0) {
876                 head = ACCESS_ONCE(circ->head);
877                 tail = circ->tail;
878                 s = min_t(int, count,
879                                 CIRC_CNT_TO_END(head, tail, CIRC_BUF_SIZE));
880
881                 if (s > 0) {
882                         if (copy_to_user(&buf[n], &circ->buf[tail], s)) {
883                                 dev_warn(&pdev->dev, "copy_to_user failed\n");
884                                 mutex_unlock(&tegra->log.mutex);
885                                 return -EFAULT;
886                         }
887                         circ->tail = (circ->tail + s) & (CIRC_BUF_SIZE - 1);
888
889                         count -= s;
890                         n += s;
891                 } else
892                         break;
893         }
894
895         mutex_unlock(&tegra->log.mutex);
896
897         wake_up_interruptible(&tegra->log.write_wait);
898
899         dev_dbg(&pdev->dev, "%s: %d bytes\n", __func__, n);
900
901         return n;
902 }
903
904 static int fw_log_file_open(struct inode *inode, struct file *file)
905 {
906         struct tegra_xhci_hcd *tegra;
907         file->private_data = inode->i_private;
908         tegra = file->private_data;
909
910         if (test_and_set_bit(FW_LOG_FILE_OPENED, &tegra->log.flags)) {
911                 dev_info(&tegra->pdev->dev, "%s: already opened\n", __func__);
912                 return -EBUSY;
913         }
914
915         return 0;
916 }
917
918 static int fw_log_file_close(struct inode *inode, struct file *file)
919 {
920         struct tegra_xhci_hcd *tegra = file->private_data;
921
922         clear_bit(FW_LOG_FILE_OPENED, &tegra->log.flags);
923
924         return 0;
925 }
926
927 static const struct file_operations firmware_log_fops = {
928                 .open           = fw_log_file_open,
929                 .release        = fw_log_file_close,
930                 .read           = fw_log_file_read,
931                 .owner          = THIS_MODULE,
932 };
933
934 static int fw_log_init(struct tegra_xhci_hcd *tegra)
935 {
936         struct platform_device *pdev = tegra->pdev;
937         int rc = 0;
938
939         /* allocate buffer to be shared between driver and firmware */
940         tegra->log.virt_addr = dma_alloc_writecombine(&pdev->dev,
941                         FW_LOG_RING_SIZE, &tegra->log.phys_addr, GFP_KERNEL);
942
943         if (!tegra->log.virt_addr) {
944                 dev_err(&pdev->dev, "dma_alloc_writecombine() size %d failed\n",
945                                 FW_LOG_RING_SIZE);
946                 return -ENOMEM;
947         }
948
949         dev_info(&pdev->dev, "%d bytes log buffer physical 0x%u virtual 0x%p\n",
950                 FW_LOG_RING_SIZE, tegra->log.phys_addr, tegra->log.virt_addr);
951
952         memset(tegra->log.virt_addr, 0, FW_LOG_RING_SIZE);
953         tegra->log.dequeue = tegra->log.virt_addr;
954
955         tegra->log.circ.buf = vmalloc(CIRC_BUF_SIZE);
956         if (!tegra->log.circ.buf) {
957                 dev_err(&pdev->dev, "vmalloc size %d failed\n", CIRC_BUF_SIZE);
958                 rc = -ENOMEM;
959                 goto error_free_dma;
960         }
961
962         tegra->log.circ.head = 0;
963         tegra->log.circ.tail = 0;
964
965         init_waitqueue_head(&tegra->log.read_wait);
966         init_waitqueue_head(&tegra->log.write_wait);
967         init_waitqueue_head(&tegra->log.intr_wait);
968
969         mutex_init(&tegra->log.mutex);
970
971         tegra->log.path = debugfs_create_dir("tegra_xhci", NULL);
972         if (IS_ERR_OR_NULL(tegra->log.path)) {
973                 dev_warn(&pdev->dev, "debugfs_create_dir() failed\n");
974                 rc = -ENOMEM;
975                 goto error_free_mem;
976         }
977
978         tegra->log.log_file = debugfs_create_file("firmware_log",
979                         S_IRUGO, tegra->log.path, tegra, &firmware_log_fops);
980         if ((!tegra->log.log_file) ||
981                         (tegra->log.log_file == ERR_PTR(-ENODEV))) {
982                 dev_warn(&pdev->dev, "debugfs_create_file() failed\n");
983                 rc = -ENOMEM;
984                 goto error_remove_debugfs_path;
985         }
986
987         tegra->log.thread = kthread_run(fw_log_thread, tegra, "xusb-fw-log");
988         if (IS_ERR(tegra->log.thread)) {
989                 dev_warn(&pdev->dev, "kthread_run() failed\n");
990                 rc = -ENOMEM;
991                 goto error_remove_debugfs_file;
992         }
993
994         set_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags);
995         return rc;
996
997 error_remove_debugfs_file:
998         debugfs_remove(tegra->log.log_file);
999 error_remove_debugfs_path:
1000         debugfs_remove(tegra->log.path);
1001 error_free_mem:
1002         vfree(tegra->log.circ.buf);
1003 error_free_dma:
1004         dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1005                         tegra->log.virt_addr, tegra->log.phys_addr);
1006         memset(&tegra->log, sizeof(tegra->log), 0);
1007         return rc;
1008 }
1009
1010 static void fw_log_deinit(struct tegra_xhci_hcd *tegra)
1011 {
1012         struct platform_device *pdev = tegra->pdev;
1013
1014         if (test_and_clear_bit(FW_LOG_CONTEXT_VALID, &tegra->log.flags)) {
1015
1016                 debugfs_remove(tegra->log.log_file);
1017                 debugfs_remove(tegra->log.path);
1018
1019                 wake_up_interruptible(&tegra->log.read_wait);
1020                 wake_up_interruptible(&tegra->log.write_wait);
1021                 kthread_stop(tegra->log.thread);
1022
1023                 mutex_lock(&tegra->log.mutex);
1024                 dma_free_writecombine(&pdev->dev, FW_LOG_RING_SIZE,
1025                         tegra->log.virt_addr, tegra->log.phys_addr);
1026                 vfree(tegra->log.circ.buf);
1027                 tegra->log.circ.head = tegra->log.circ.tail = 0;
1028                 mutex_unlock(&tegra->log.mutex);
1029
1030                 mutex_destroy(&tegra->log.mutex);
1031         }
1032 }
1033
1034 /* hsic pad operations */
1035 /*
1036  * HSIC pads need VDDIO_HSIC power rail turned on to be functional. There is
1037  * only one VDDIO_HSIC power rail shared by all HSIC pads.
1038  */
1039 static int hsic_power_rail_enable(struct tegra_xhci_hcd *tegra)
1040 {
1041         struct device *dev = &tegra->pdev->dev;
1042         struct tegra_xusb_regulator_name *supply = &tegra->pdata->bdata->supply;
1043         int ret;
1044
1045         if (tegra->vddio_hsic_reg)
1046                 goto done;
1047
1048         tegra->vddio_hsic_reg = devm_regulator_get(dev, supply->vddio_hsic);
1049         if (IS_ERR_OR_NULL(tegra->vddio_hsic_reg)) {
1050                 dev_err(dev, "%s get vddio_hsic failed\n", __func__);
1051                 ret = PTR_ERR(tegra->vddio_hsic_reg);
1052                 goto get_failed;
1053         }
1054
1055         dev_dbg(dev, "%s regulator_enable vddio_hsic\n", __func__);
1056         ret = regulator_enable(tegra->vddio_hsic_reg);
1057         if (ret < 0) {
1058                 dev_err(dev, "%s enable vddio_hsic failed\n", __func__);
1059                 goto enable_failed;
1060         }
1061
1062 done:
1063         tegra->vddio_hsic_refcnt++;
1064         WARN(tegra->vddio_hsic_refcnt > XUSB_HSIC_COUNT,
1065                         "vddio_hsic_refcnt exceeds\n");
1066         return 0;
1067
1068 enable_failed:
1069         devm_regulator_put(tegra->vddio_hsic_reg);
1070 get_failed:
1071         tegra->vddio_hsic_reg = NULL;
1072         return ret;
1073 }
1074
1075 static int hsic_power_rail_disable(struct tegra_xhci_hcd *tegra)
1076 {
1077         struct device *dev = &tegra->pdev->dev;
1078         int ret;
1079
1080         WARN_ON(!tegra->vddio_hsic_reg || !tegra->vddio_hsic_refcnt);
1081
1082         tegra->vddio_hsic_refcnt--;
1083         if (tegra->vddio_hsic_refcnt)
1084                 return 0;
1085
1086         dev_dbg(dev, "%s regulator_disable vddio_hsic\n", __func__);
1087         ret = regulator_disable(tegra->vddio_hsic_reg);
1088         if (ret < 0) {
1089                 dev_err(dev, "%s disable vddio_hsic failed\n", __func__);
1090                 tegra->vddio_hsic_refcnt++;
1091                 return ret;
1092         }
1093
1094         devm_regulator_put(tegra->vddio_hsic_reg);
1095         tegra->vddio_hsic_reg = NULL;
1096
1097         return 0;
1098 }
1099
1100 static int hsic_pad_enable(struct tegra_xhci_hcd *tegra, unsigned pad)
1101 {
1102         struct device *dev = &tegra->pdev->dev;
1103         void __iomem *base = tegra->padctl_base;
1104         struct tegra_xusb_hsic_config *hsic = &tegra->bdata->hsic;
1105         u32 reg;
1106
1107         if (pad >= XUSB_HSIC_COUNT) {
1108                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1109                 return -EINVAL;
1110         }
1111
1112         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1113
1114         reg = readl(base + HSIC_PAD_CTL_2(pad));
1115         reg &= ~(RX_STROBE_TRIM(~0) | RX_DATA_TRIM(~0));
1116         reg |= RX_STROBE_TRIM(hsic->rx_strobe_trim);
1117         reg |= RX_DATA_TRIM(hsic->rx_data_trim);
1118         writel(reg, base + HSIC_PAD_CTL_2(pad));
1119
1120         reg = readl(base + HSIC_PAD_CTL_0(pad));
1121         reg &= ~(TX_RTUNEP(~0) | TX_RTUNEN(~0) | TX_SLEWP(~0) | TX_SLEWN(~0));
1122         reg |= TX_RTUNEP(hsic->tx_rtune_p);
1123         reg |= TX_RTUNEN(hsic->tx_rtune_n);
1124         reg |= TX_SLEWP(hsic->tx_slew_p);
1125         reg |= TX_SLEWN(hsic->tx_slew_n);
1126         writel(reg, base + HSIC_PAD_CTL_0(pad));
1127
1128         reg = readl(base + HSIC_PAD_CTL_1(pad));
1129         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1130         reg |= (RPD_DATA | RPU_STROBE); /* keep HSIC in IDLE */
1131         if (hsic->auto_term_en)
1132                 reg |= AUTO_TERM_EN;
1133         else
1134                 reg &= ~AUTO_TERM_EN;
1135         reg &= ~(PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1136         writel(reg, base + HSIC_PAD_CTL_1(pad));
1137
1138         reg = readl(base + HSIC_STRB_TRIM_CONTROL);
1139         reg &= ~(STRB_TRIM_VAL(~0));
1140         reg |= STRB_TRIM_VAL(hsic->strb_trim_val);
1141         writel(reg, base + HSIC_STRB_TRIM_CONTROL);
1142
1143         reg = readl(base + USB2_PAD_MUX);
1144         reg |= USB2_HSIC_PAD_PORT(pad);
1145         writel(reg, base + USB2_PAD_MUX);
1146
1147         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1148         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1149         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1150         reg_dump(dev, base, HSIC_STRB_TRIM_CONTROL);
1151         reg_dump(dev, base, USB2_PAD_MUX);
1152         return 0;
1153 }
1154
1155 static int hsic_pad_disable(struct tegra_xhci_hcd *tegra, unsigned pad)
1156 {
1157         struct device *dev = &tegra->pdev->dev;
1158         void __iomem *base = tegra->padctl_base;
1159         u32 reg;
1160
1161         if (pad >= XUSB_HSIC_COUNT) {
1162                 dev_err(dev, "%s invalid HSIC pad number %d\n", __func__, pad);
1163                 return -EINVAL;
1164         }
1165
1166         dev_dbg(dev, "%s pad %u\n", __func__, pad);
1167
1168         reg = readl(base + USB2_PAD_MUX);
1169         reg &= ~USB2_HSIC_PAD_PORT(pad);
1170         writel(reg, base + USB2_PAD_MUX);
1171
1172         reg = readl(base + HSIC_PAD_CTL_1(pad));
1173         reg |= (PD_RX | HSIC_PD_ZI | PD_TRX | PD_TX);
1174         writel(reg, base + HSIC_PAD_CTL_1(pad));
1175
1176         reg_dump(dev, base, HSIC_PAD_CTL_0(pad));
1177         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1178         reg_dump(dev, base, HSIC_PAD_CTL_2(pad));
1179         reg_dump(dev, base, USB2_PAD_MUX);
1180         return 0;
1181 }
1182
1183 enum hsic_pad_pupd {
1184         PUPD_DISABLE = 0,
1185         PUPD_IDLE,
1186         PUPD_RESET
1187 };
1188
1189 static int hsic_pad_pupd_set(struct tegra_xhci_hcd *tegra, unsigned pad,
1190         enum hsic_pad_pupd pupd)
1191 {
1192         struct device *dev = &tegra->pdev->dev;
1193         void __iomem *base = tegra->padctl_base;
1194         u32 reg;
1195
1196         if (pad >= XUSB_HSIC_COUNT) {
1197                 dev_err(dev, "%s invalid HSIC pad number %u\n", __func__, pad);
1198                 return -EINVAL;
1199         }
1200
1201         dev_dbg(dev, "%s pad %u pupd %d\n", __func__, pad, pupd);
1202
1203         reg = readl(base + HSIC_PAD_CTL_1(pad));
1204         reg &= ~(RPD_DATA | RPD_STROBE | RPU_DATA | RPU_STROBE);
1205
1206         if (pupd == PUPD_IDLE)
1207                 reg |= (RPD_DATA | RPU_STROBE);
1208         else if (pupd == PUPD_RESET)
1209                 reg |= (RPD_DATA | RPD_STROBE);
1210         else if (pupd != PUPD_DISABLE) {
1211                 dev_err(dev, "%s invalid pupd %d\n", __func__, pupd);
1212                 return -EINVAL;
1213         }
1214
1215         writel(reg, base + HSIC_PAD_CTL_1(pad));
1216
1217         reg_dump(dev, base, HSIC_PAD_CTL_1(pad));
1218
1219         return 0;
1220 }
1221
1222
1223 static void tegra_xhci_debug_read_pads(struct tegra_xhci_hcd *tegra)
1224 {
1225         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1226         struct xhci_hcd *xhci = tegra->xhci;
1227         u32 reg;
1228
1229         xhci_info(xhci, "============ PADCTL VALUES START =================\n");
1230         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1231         xhci_info(xhci, " PAD MUX = %x\n", reg);
1232         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1233         xhci_info(xhci, " PORT CAP = %x\n", reg);
1234         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1235         xhci_info(xhci, " SNPS OC MAP = %x\n", reg);
1236         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1237         xhci_info(xhci, " USB2 OC MAP = %x\n", reg);
1238         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1239         xhci_info(xhci, " SS PORT MAP = %x\n", reg);
1240         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1241         xhci_info(xhci, " OC DET 0= %x\n", reg);
1242         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad0_ctl2_0);
1243         xhci_info(xhci, " iophy_usb3_pad0_ctl2_0= %x\n", reg);
1244         reg = readl(tegra->padctl_base + padregs->iophy_usb3_pad1_ctl2_0);
1245         xhci_info(xhci, " iophy_usb3_pad1_ctl2_0= %x\n", reg);
1246         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl0_0);
1247         xhci_info(xhci, " usb2_otg_pad0_ctl0_0= %x\n", reg);
1248         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl0_0);
1249         xhci_info(xhci, " usb2_otg_pad1_ctl0_0= %x\n", reg);
1250         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad0_ctl1_0);
1251         xhci_info(xhci, " usb2_otg_pad0_ctl1_0= %x\n", reg);
1252         reg = readl(tegra->padctl_base + padregs->usb2_otg_pad1_ctl1_0);
1253         xhci_info(xhci, " usb2_otg_pad1_ctl1_0= %x\n", reg);
1254         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1255         xhci_info(xhci, " usb2_bias_pad_ctl0_0= %x\n", reg);
1256         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad0_ctl0_0);
1257         xhci_info(xhci, " usb2_hsic_pad0_ctl0_0= %x\n", reg);
1258         reg = readl(tegra->padctl_base + padregs->usb2_hsic_pad1_ctl0_0);
1259         xhci_info(xhci, " usb2_hsic_pad1_ctl0_0= %x\n", reg);
1260         xhci_info(xhci, "============ PADCTL VALUES END=================\n");
1261 }
1262
1263 static void tegra_xhci_cfg(struct tegra_xhci_hcd *tegra)
1264 {
1265         u32 reg;
1266
1267         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1268         reg |= IPFS_EN_FPCI;
1269         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_CONFIGURATION_0);
1270         udelay(10);
1271
1272         /* Program Bar0 Space */
1273         reg = readl(tegra->fpci_base + XUSB_CFG_4);
1274         reg |= tegra->host_phy_base;
1275         writel(reg, tegra->fpci_base + XUSB_CFG_4);
1276         usleep_range(100, 200);
1277
1278         /* Enable Bus Master */
1279         reg = readl(tegra->fpci_base + XUSB_CFG_1);
1280         reg |= 0x7;
1281         writel(reg, tegra->fpci_base + XUSB_CFG_1);
1282
1283         /* Set intr mask to enable intr assertion */
1284         reg = readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1285         reg |= IPFS_IP_INT_MASK;
1286         writel(reg, tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
1287
1288         /* Set hysteris to 0x80 */
1289         writel(0x80, tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
1290 }
1291
1292 static int tegra_xusb_regulator_init(struct tegra_xhci_hcd *tegra,
1293                 struct platform_device *pdev)
1294 {
1295         struct tegra_xusb_regulator_name *supply = &tegra->bdata->supply;
1296         int err = 0;
1297
1298         tegra->xusb_s3p3v_reg =
1299                         devm_regulator_get(&pdev->dev, supply->s3p3v);
1300         if (IS_ERR(tegra->xusb_s3p3v_reg)) {
1301                 dev_err(&pdev->dev, "3p3v: regulator not found: %ld."
1302                         , PTR_ERR(tegra->xusb_s3p3v_reg));
1303                 err = PTR_ERR(tegra->xusb_s3p3v_reg);
1304                 goto err_null_regulator;
1305         } else {
1306                 err = regulator_enable(tegra->xusb_s3p3v_reg);
1307                 if (err < 0) {
1308                         dev_err(&pdev->dev,
1309                                 "3p3v: regulator enable failed:%d\n", err);
1310                         goto err_null_regulator;
1311                 }
1312         }
1313
1314         tegra->xusb_s5p0v_reg = devm_regulator_get(&pdev->dev, supply->s5p0v);
1315         if (IS_ERR(tegra->xusb_s5p0v_reg)) {
1316                 dev_err(&pdev->dev, "5p0v regulator not found: %ld."
1317                         , PTR_ERR(tegra->xusb_s5p0v_reg));
1318                 err = PTR_ERR(tegra->xusb_s5p0v_reg);
1319                 goto err_put_s3p3v_reg;
1320         } else {
1321                 err = regulator_enable(tegra->xusb_s5p0v_reg);
1322                 if (err < 0) {
1323                         dev_err(&pdev->dev,
1324                                 "5p0v: regulator enable failed:%d\n", err);
1325                         goto err_put_s3p3v_reg;
1326                 }
1327         }
1328
1329         tegra->xusb_s1p8v_reg =
1330                 devm_regulator_get(&pdev->dev, supply->s1p8v);
1331         if (IS_ERR(tegra->xusb_s1p8v_reg)) {
1332                 dev_err(&pdev->dev, "1p8v regulator not found: %ld."
1333                         , PTR_ERR(tegra->xusb_s1p8v_reg));
1334                 err = PTR_ERR(tegra->xusb_s1p8v_reg);
1335                 goto err_put_s5p0v_reg;
1336         } else {
1337                 err = regulator_enable(tegra->xusb_s1p8v_reg);
1338                 if (err < 0) {
1339                         dev_err(&pdev->dev,
1340                         "1p8v: regulator enable failed:%d\n", err);
1341                         goto err_put_s5p0v_reg;
1342                 }
1343         }
1344
1345         tegra->xusb_s1p05v_reg =
1346                         devm_regulator_get(&pdev->dev, supply->s1p05v);
1347         if (IS_ERR(tegra->xusb_s1p05v_reg)) {
1348                 dev_err(&pdev->dev, "1p05v: regulator not found: %ld."
1349                         , PTR_ERR(tegra->xusb_s1p05v_reg));
1350                 err = PTR_ERR(tegra->xusb_s1p05v_reg);
1351                 goto err_put_s1p8v_reg;
1352         } else {
1353                 err = regulator_enable(tegra->xusb_s1p05v_reg);
1354                 if (err < 0) {
1355                         dev_err(&pdev->dev,
1356                         "1p05v: regulator enable failed:%d\n", err);
1357                         goto err_put_s1p8v_reg;
1358                 }
1359         }
1360
1361         if (tegra->bdata->uses_different_vbus_per_port) {
1362                 tegra->xusb_s5p0v1_reg = devm_regulator_get(&pdev->dev,
1363                                                 supply->s5p0v1);
1364                 if (IS_ERR(tegra->xusb_s5p0v1_reg)) {
1365                         dev_err(&pdev->dev, "5p0v1 regulator not found: %ld."
1366                                 , PTR_ERR(tegra->xusb_s5p0v1_reg));
1367                         err = PTR_ERR(tegra->xusb_s5p0v1_reg);
1368                         goto err_put_s1p05v_reg;
1369                 } else {
1370                         err = regulator_enable(tegra->xusb_s5p0v1_reg);
1371                         if (err < 0) {
1372                                 dev_err(&pdev->dev,
1373                                 "5p0v1: regulator enable failed:%d\n", err);
1374                                 goto err_put_s1p05v_reg;
1375                         }
1376                 }
1377
1378                 tegra->xusb_s5p0v2_reg = devm_regulator_get(&pdev->dev,
1379                                                 supply->s5p0v2);
1380                 if (IS_ERR(tegra->xusb_s5p0v2_reg)) {
1381                         dev_err(&pdev->dev, "5p0v2 regulator not found: %ld."
1382                                 , PTR_ERR(tegra->xusb_s5p0v2_reg));
1383                         err = PTR_ERR(tegra->xusb_s5p0v2_reg);
1384                         goto err_put_s1p5v1_reg;
1385                 } else {
1386                         err = regulator_enable(tegra->xusb_s5p0v2_reg);
1387                         if (err < 0) {
1388                                 dev_err(&pdev->dev,
1389                                 "5p0v2: regulator enable failed:%d\n", err);
1390                                 goto err_put_s1p5v1_reg;
1391                         }
1392                 }
1393         }
1394         return err;
1395
1396 err_put_s1p5v1_reg:
1397         if (tegra->bdata->uses_different_vbus_per_port)
1398                 regulator_disable(tegra->xusb_s5p0v1_reg);
1399 err_put_s1p05v_reg:
1400         regulator_disable(tegra->xusb_s1p05v_reg);
1401 err_put_s1p8v_reg:
1402         regulator_disable(tegra->xusb_s1p8v_reg);
1403 err_put_s5p0v_reg:
1404         regulator_disable(tegra->xusb_s5p0v_reg);
1405 err_put_s3p3v_reg:
1406         regulator_disable(tegra->xusb_s3p3v_reg);
1407 err_null_regulator:
1408         tegra->xusb_s5p0v_reg = NULL;
1409         tegra->xusb_s5p0v1_reg = NULL;
1410         tegra->xusb_s5p0v2_reg = NULL;
1411         tegra->xusb_s1p05v_reg = NULL;
1412         tegra->xusb_s3p3v_reg = NULL;
1413         tegra->xusb_s1p8v_reg = NULL;
1414         return err;
1415 }
1416
1417 static void tegra_xusb_regulator_deinit(struct tegra_xhci_hcd *tegra)
1418 {
1419         regulator_disable(tegra->xusb_s1p05v_reg);
1420         regulator_disable(tegra->xusb_s1p8v_reg);
1421         regulator_disable(tegra->xusb_s5p0v_reg);
1422         regulator_disable(tegra->xusb_s3p3v_reg);
1423         if (tegra->bdata->uses_different_vbus_per_port) {
1424                 regulator_disable(tegra->xusb_s5p0v1_reg);
1425                 regulator_disable(tegra->xusb_s5p0v2_reg);
1426         }
1427
1428         tegra->xusb_s1p05v_reg = NULL;
1429         tegra->xusb_s1p8v_reg = NULL;
1430         tegra->xusb_s5p0v_reg = NULL;
1431         tegra->xusb_s5p0v1_reg = NULL;
1432         tegra->xusb_s5p0v2_reg = NULL;
1433         tegra->xusb_s3p3v_reg = NULL;
1434 }
1435
1436 /*
1437  * We need to enable only plle_clk as pllu_clk, utmip_clk and plle_re_vco_clk
1438  * are under hardware control
1439  */
1440 static int tegra_usb2_clocks_init(struct tegra_xhci_hcd *tegra)
1441 {
1442         struct platform_device *pdev = tegra->pdev;
1443         int err = 0;
1444
1445         tegra->plle_clk = devm_clk_get(&pdev->dev, "pll_e");
1446         if (IS_ERR(tegra->plle_clk)) {
1447                 dev_err(&pdev->dev, "%s: Failed to get plle clock\n", __func__);
1448                 err = PTR_ERR(tegra->plle_clk);
1449                 return err;
1450         }
1451         err = clk_enable(tegra->plle_clk);
1452         if (err) {
1453                 dev_err(&pdev->dev, "%s: could not enable plle clock\n",
1454                         __func__);
1455                 return err;
1456         }
1457
1458         return err;
1459 }
1460
1461 static void tegra_usb2_clocks_deinit(struct tegra_xhci_hcd *tegra)
1462 {
1463         clk_disable(tegra->plle_clk);
1464         tegra->plle_clk = NULL;
1465 }
1466
1467 static int tegra_xusb_partitions_clk_init(struct tegra_xhci_hcd *tegra)
1468 {
1469         struct platform_device *pdev = tegra->pdev;
1470         int err = 0;
1471
1472         tegra->emc_clk = devm_clk_get(&pdev->dev, "emc");
1473         if (IS_ERR(tegra->emc_clk)) {
1474                 dev_err(&pdev->dev, "Failed to get xusb.emc clock\n");
1475                 return PTR_ERR(tegra->emc_clk);
1476         }
1477
1478         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1479                 tegra->pll_re_vco_clk = devm_clk_get(&pdev->dev, "pll_re_vco");
1480                 if (IS_ERR(tegra->pll_re_vco_clk)) {
1481                         dev_err(&pdev->dev, "Failed to get refPLLE clock\n");
1482                         err = PTR_ERR(tegra->pll_re_vco_clk);
1483                         goto get_pll_re_vco_clk_failed;
1484                 }
1485         }
1486
1487         /* get the clock handle of 120MHz clock source */
1488         tegra->pll_u_480M = devm_clk_get(&pdev->dev, "pll_u_480M");
1489         if (IS_ERR(tegra->pll_u_480M)) {
1490                 dev_err(&pdev->dev, "Failed to get pll_u_480M clk handle\n");
1491                 err = PTR_ERR(tegra->pll_u_480M);
1492                 goto get_pll_u_480M_failed;
1493         }
1494
1495         /* get the clock handle of 12MHz clock source */
1496         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1497         if (IS_ERR(tegra->clk_m)) {
1498                 dev_err(&pdev->dev, "Failed to get clk_m clk handle\n");
1499                 err = PTR_ERR(tegra->clk_m);
1500                 goto clk_get_clk_m_failed;
1501         }
1502
1503         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "ss_src");
1504         if (IS_ERR(tegra->ss_src_clk)) {
1505                 dev_err(&pdev->dev, "Failed to get SSPI clk\n");
1506                 err = PTR_ERR(tegra->ss_src_clk);
1507                 tegra->ss_src_clk = NULL;
1508                 goto get_ss_src_clk_failed;
1509         }
1510
1511         tegra->host_clk = devm_clk_get(&pdev->dev, "host");
1512         if (IS_ERR(tegra->host_clk)) {
1513                 dev_err(&pdev->dev, "Failed to get host partition clk\n");
1514                 err = PTR_ERR(tegra->host_clk);
1515                 tegra->host_clk = NULL;
1516                 goto get_host_clk_failed;
1517         }
1518
1519         tegra->ss_clk = devm_clk_get(&pdev->dev, "ss");
1520         if (IS_ERR(tegra->ss_clk)) {
1521                 dev_err(&pdev->dev, "Failed to get ss partition clk\n");
1522                 err = PTR_ERR(tegra->ss_clk);
1523                 tegra->ss_clk = NULL;
1524                 goto get_ss_clk_failed;
1525         }
1526
1527         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1528                 err = clk_enable(tegra->pll_re_vco_clk);
1529                 if (err) {
1530                         dev_err(&pdev->dev, "Failed to enable refPLLE clk\n");
1531                         goto enable_pll_re_vco_clk_failed;
1532                 }
1533         }
1534         return 0;
1535
1536 enable_pll_re_vco_clk_failed:
1537         tegra->ss_clk = NULL;
1538
1539 get_ss_clk_failed:
1540         tegra->host_clk = NULL;
1541
1542 get_host_clk_failed:
1543         tegra->ss_src_clk = NULL;
1544
1545 get_ss_src_clk_failed:
1546         tegra->clk_m = NULL;
1547
1548 clk_get_clk_m_failed:
1549         tegra->pll_u_480M = NULL;
1550
1551 get_pll_u_480M_failed:
1552         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1553                 tegra->pll_re_vco_clk = NULL;
1554
1555 get_pll_re_vco_clk_failed:
1556         tegra->emc_clk = NULL;
1557
1558         return err;
1559 }
1560
1561 static void tegra_xusb_partitions_clk_deinit(struct tegra_xhci_hcd *tegra)
1562 {
1563         clk_disable(tegra->ss_clk);
1564         clk_disable(tegra->host_clk);
1565         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1566                 clk_disable(tegra->pll_re_vco_clk);
1567         tegra->ss_clk = NULL;
1568         tegra->host_clk = NULL;
1569         tegra->ss_src_clk = NULL;
1570         tegra->clk_m = NULL;
1571         tegra->pll_u_480M = NULL;
1572         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
1573                 tegra->pll_re_vco_clk = NULL;
1574 }
1575
1576 static void tegra_xhci_rx_idle_mode_override(struct tegra_xhci_hcd *tegra,
1577         bool enable)
1578 {
1579         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1580         u32 reg;
1581
1582         /* Issue is only applicable for T114 */
1583         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
1584                 return;
1585
1586         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1587                 reg = readl(tegra->padctl_base +
1588                         padregs->iophy_misc_pad_p0_ctl3_0);
1589                 if (enable) {
1590                         reg &= ~RX_IDLE_MODE;
1591                         reg |= RX_IDLE_MODE_OVRD;
1592                 } else {
1593                         reg |= RX_IDLE_MODE;
1594                         reg &= ~RX_IDLE_MODE_OVRD;
1595                 }
1596                 writel(reg, tegra->padctl_base +
1597                         padregs->iophy_misc_pad_p0_ctl3_0);
1598         }
1599
1600         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1601                 reg = readl(tegra->padctl_base +
1602                         padregs->iophy_misc_pad_p1_ctl3_0);
1603                 if (enable) {
1604                         reg &= ~RX_IDLE_MODE;
1605                         reg |= RX_IDLE_MODE_OVRD;
1606                 } else {
1607                         reg |= RX_IDLE_MODE;
1608                         reg &= ~RX_IDLE_MODE_OVRD;
1609                 }
1610                 writel(reg, tegra->padctl_base +
1611                         padregs->iophy_misc_pad_p1_ctl3_0);
1612
1613                 /* SATA lane also if USB3_SS port1 mapped to it */
1614                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
1615                                 tegra->bdata->lane_owner & BIT(0)) {
1616                         reg = readl(tegra->padctl_base +
1617                                 padregs->iophy_misc_pad_s0_ctl3_0);
1618                         if (enable) {
1619                                 reg &= ~RX_IDLE_MODE;
1620                                 reg |= RX_IDLE_MODE_OVRD;
1621                         } else {
1622                                 reg |= RX_IDLE_MODE;
1623                                 reg &= ~RX_IDLE_MODE_OVRD;
1624                         }
1625                         writel(reg, tegra->padctl_base +
1626                                 padregs->iophy_misc_pad_s0_ctl3_0);
1627                 }
1628         }
1629 }
1630
1631 /* Enable ss clk, host clk, falcon clk,
1632  * fs clk, dev clk, plle and refplle
1633  */
1634
1635 static int
1636 tegra_xusb_request_clk_rate(struct tegra_xhci_hcd *tegra,
1637                 struct clk *clk_handle, u32 rate, u32 *sw_resp)
1638 {
1639         int ret = 0;
1640         enum MBOX_CMD_TYPE cmd_ack = MBOX_CMD_ACK;
1641         int fw_req_rate = rate, cur_rate;
1642
1643         /* Do not handle clock change as needed for HS disconnect issue */
1644         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2) {
1645                 *sw_resp = fw_req_rate | (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
1646                 return ret;
1647         }
1648
1649         /* frequency request from firmware is in KHz.
1650          * Convert it to MHz
1651          */
1652
1653         /* get current rate of clock */
1654         cur_rate = clk_get_rate(clk_handle);
1655         cur_rate /= 1000;
1656
1657         if (fw_req_rate == cur_rate) {
1658                 cmd_ack = MBOX_CMD_ACK;
1659                 *sw_resp = fw_req_rate;
1660         } else {
1661
1662                 if (clk_handle == tegra->ss_src_clk && fw_req_rate == 12000) {
1663                         /* Change SS clock source to CLK_M at 12MHz */
1664                         clk_set_parent(clk_handle, tegra->clk_m);
1665                         clk_set_rate(clk_handle, fw_req_rate * 1000);
1666
1667                         /* save leakage power when SS freq is being decreased */
1668                         tegra_xhci_rx_idle_mode_override(tegra, true);
1669                 } else if (clk_handle == tegra->ss_src_clk &&
1670                                 fw_req_rate == 120000) {
1671                         /* Change SS clock source to HSIC_480 at 120MHz */
1672                         clk_set_rate(clk_handle,  3000 * 1000);
1673                         clk_set_parent(clk_handle, tegra->pll_u_480M);
1674
1675                         /* clear ovrd bits when SS freq is being increased */
1676                         tegra_xhci_rx_idle_mode_override(tegra, false);
1677                 }
1678
1679                 *sw_resp = clk_get_rate(clk_handle);
1680                 *sw_resp /= 1000;
1681
1682                 if (*sw_resp != fw_req_rate) {
1683                         xhci_err(tegra->xhci, "cur_rate=%d, fw_req_rate=%d\n",
1684                                 cur_rate, fw_req_rate);
1685                         cmd_ack = MBOX_CMD_NACK;
1686                 }
1687         }
1688         *sw_resp |= (cmd_ack << MBOX_CMD_SHIFT);
1689         return ret;
1690 }
1691
1692 static void tegra_xhci_save_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
1693         u8 port)
1694 {
1695         struct xhci_hcd *xhci = tegra->xhci;
1696         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1697         u32 offset;
1698         u32 reg;
1699
1700         xhci_info(xhci, "saving dfe_cntl and ctle context for port %d\n", port);
1701
1702         /* if port1 is mapped to SATA lane then read from SATA register */
1703         if (port == 1 && XUSB_DEVICE_ID_T114 != tegra->device_id &&
1704                         tegra->bdata->lane_owner & BIT(0))
1705                 offset = padregs->iophy_misc_pad_s0_ctl6_0;
1706         else
1707                 offset = port ? padregs->iophy_misc_pad_p1_ctl6_0 :
1708                                 padregs->iophy_misc_pad_p0_ctl6_0;
1709
1710         /* save tap1_val[] for the port for dfe_cntl */
1711         reg = readl(tegra->padctl_base + offset);
1712         reg &= ~(0xff << 16);
1713         reg |= (0x32 << 16);
1714         writel(reg, tegra->padctl_base + offset);
1715
1716         reg = readl(tegra->padctl_base + offset);
1717         tegra->sregs.tap1_val[port] = ((reg & (0x1f << 24)) >> 24);
1718
1719         /* save amp_val[] for the port for dfe_cntl */
1720         reg = readl(tegra->padctl_base + offset);
1721         reg &= ~(0xff << 16);
1722         reg |= (0x33 << 16);
1723         writel(reg, tegra->padctl_base + offset);
1724
1725         reg = readl(tegra->padctl_base + offset);
1726         tegra->sregs.amp_val[port] = ((reg & (0x7f << 24)) >> 24);
1727
1728         /* save ctle_z_val[] for the port for ctle */
1729         reg = readl(tegra->padctl_base + offset);
1730         reg &= ~(0xff << 16);
1731         reg |= (0x20 << 16);
1732         writel(reg, tegra->padctl_base + offset);
1733
1734         reg = readl(tegra->padctl_base + offset);
1735         tegra->sregs.ctle_z_val[port] = ((reg & (0x3f << 24)) >> 24);
1736
1737         /* save ctle_g_val[] for the port for ctle */
1738         reg = readl(tegra->padctl_base + offset);
1739         reg &= ~(0xff << 16);
1740         reg |= (0x21 << 16);
1741         writel(reg, tegra->padctl_base + offset);
1742
1743         reg = readl(tegra->padctl_base + offset);
1744         tegra->sregs.ctle_g_val[port] = ((reg & (0x3f << 24)) >> 24);
1745         tegra->dfe_ctle_ctx_saved = true;
1746 }
1747
1748 static void tegra_xhci_restore_dfe_ctle_context(struct tegra_xhci_hcd *tegra,
1749         u8 port)
1750 {
1751         struct xhci_hcd *xhci = tegra->xhci;
1752         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1753         u32 ctl4_offset, ctl2_offset;
1754         u32 reg;
1755
1756         /* don't restore if not saved */
1757         if (tegra->dfe_ctle_ctx_saved == false)
1758                 return;
1759
1760         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1761                         padregs->iophy_usb3_pad0_ctl4_0;
1762         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1763                         padregs->iophy_usb3_pad0_ctl2_0;
1764
1765         xhci_info(xhci, "restoring dfe_cntl/ctle context of port %d\n", port);
1766
1767         /* restore dfe_cntl for the port */
1768         reg = readl(tegra->padctl_base + ctl4_offset);
1769         reg &= ~((0x7f << 16) | (0x1f << 24));
1770         reg |= ((tegra->sregs.amp_val[port] << 16) |
1771                 (tegra->sregs.tap1_val[port] << 24));
1772         writel(reg, tegra->padctl_base + ctl4_offset);
1773
1774         /* restore ctle for the port */
1775         reg = readl(tegra->padctl_base + ctl2_offset);
1776         reg &= ~((0x3f << 8) | (0x3f << 16));
1777         reg |= ((tegra->sregs.ctle_g_val[port] << 8) |
1778                 (tegra->sregs.ctle_z_val[port] << 16));
1779         writel(reg, tegra->padctl_base + ctl2_offset);
1780 }
1781
1782 static void tegra_xhci_program_ulpi_pad(struct tegra_xhci_hcd *tegra,
1783         u8 port)
1784 {
1785         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1786         u32 reg;
1787
1788         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1789         reg &= ~USB2_ULPI_PAD;
1790         reg |= USB2_ULPI_PAD_OWNER_XUSB;
1791         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1792
1793         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1794         reg &= ~USB2_ULPI_PORT_CAP;
1795         reg |= (tegra->bdata->ulpicap << 24);
1796         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1797         /* FIXME: Program below when more details available
1798          * XUSB_PADCTL_ULPI_LINK_TRIM_CONTROL_0
1799          * XUSB_PADCTL_ULPI_NULL_CLK_TRIM_CONTROL_0
1800          */
1801 }
1802
1803 static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra,
1804         u8 port)
1805 {
1806         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1807         u32 reg;
1808         u32 ctl0_offset, ctl1_offset;
1809
1810         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
1811         reg &= ~USB2_OTG_PAD_PORT_MASK(port);
1812         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(port);
1813         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
1814
1815         reg = readl(tegra->padctl_base + padregs->usb2_port_cap_0);
1816         reg &= ~USB2_PORT_CAP_MASK(port);
1817         reg |= USB2_PORT_CAP_HOST(port);
1818         writel(reg, tegra->padctl_base + padregs->usb2_port_cap_0);
1819
1820         /*
1821          * Modify only the bits which belongs to the port
1822          * and enable respective VBUS_PAD for the port
1823          */
1824         if (tegra->bdata->uses_external_pmic == false) {
1825                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1826                 reg &= ~(port == 2 ? OC_DET_VBUS_ENABLE2_OC_MAP :
1827                         port ? OC_DET_VBUS_ENABLE1_OC_MAP :
1828                                 OC_DET_VBUS_ENABLE0_OC_MAP);
1829
1830                 reg |= (port == 2) ? OC_DET_VBUS_EN2_OC_DETECTED_VBUS_PAD2 :
1831                         port ? OC_DET_VBUS_EN1_OC_DETECTED_VBUS_PAD1 :
1832                                 OC_DET_VBUS_EN0_OC_DETECTED_VBUS_PAD0;
1833                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1834         }
1835         /*
1836          * enable respective VBUS_PAD if port is mapped to any SS port
1837          */
1838         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1839         reg &= ~((port == 2) ? USB2_OC_MAP_PORT2 :
1840                 port ? USB2_OC_MAP_PORT1 : USB2_OC_MAP_PORT0);
1841         reg |= (0x4 | port) << (port * 3);
1842         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1843
1844         ctl0_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl0_0 :
1845                         port ? padregs->usb2_otg_pad1_ctl0_0 :
1846                                 padregs->usb2_otg_pad0_ctl0_0;
1847         ctl1_offset = (port == 2) ? padregs->usb2_otg_pad2_ctl1_0 :
1848                         port ? padregs->usb2_otg_pad1_ctl1_0 :
1849                                 padregs->usb2_otg_pad0_ctl1_0;
1850
1851         reg = readl(tegra->padctl_base + ctl0_offset);
1852         reg &= ~(USB2_OTG_HS_CURR_LVL | USB2_OTG_HS_SLEW |
1853                 USB2_OTG_FS_SLEW | USB2_OTG_LS_RSLEW |
1854                 USB2_OTG_PD | USB2_OTG_PD2 | USB2_OTG_PD_ZI);
1855
1856         reg |= tegra->pdata->hs_slew;
1857         reg |= (port == 2) ? tegra->pdata->ls_rslew_pad2 :
1858                         port ? tegra->pdata->ls_rslew_pad1 :
1859                         tegra->pdata->ls_rslew_pad0;
1860         reg |= (port == 2) ? tegra->pdata->hs_curr_level_pad2 :
1861                         port ? tegra->pdata->hs_curr_level_pad1 :
1862                         tegra->pdata->hs_curr_level_pad0;
1863         writel(reg, tegra->padctl_base + ctl0_offset);
1864
1865         reg = readl(tegra->padctl_base + ctl1_offset);
1866         reg &= ~(USB2_OTG_TERM_RANGE_AD | USB2_OTG_HS_IREF_CAP
1867                 | USB2_OTG_PD_CHRP_FORCE_POWERUP
1868                 | USB2_OTG_PD_DISC_FORCE_POWERUP
1869                 | USB2_OTG_PD_DR);
1870         reg |= (tegra->pdata->hs_iref_cap << 9) |
1871                 (tegra->pdata->hs_term_range_adj << 3);
1872         writel(reg, tegra->padctl_base + ctl1_offset);
1873 }
1874
1875 static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra,
1876         u8 port)
1877 {
1878         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1879         u32 ctl2_offset, ctl4_offset, ctl5_offset;
1880         u32 reg;
1881
1882         ctl2_offset = port ? padregs->iophy_usb3_pad1_ctl2_0 :
1883                         padregs->iophy_usb3_pad0_ctl2_0;
1884         ctl4_offset = port ? padregs->iophy_usb3_pad1_ctl4_0 :
1885                         padregs->iophy_usb3_pad0_ctl4_0;
1886         ctl5_offset = port ? padregs->iophy_misc_pad_p1_ctl5_0 :
1887                         padregs->iophy_misc_pad_p0_ctl5_0;
1888
1889         reg = readl(tegra->padctl_base + ctl2_offset);
1890         reg &= ~(IOPHY_USB3_RXWANDER | IOPHY_USB3_RXEQ |
1891                 IOPHY_USB3_CDRCNTL);
1892         reg |= tegra->pdata->rx_wander | tegra->pdata->rx_eq |
1893                 tegra->pdata->cdr_cntl;
1894         writel(reg, tegra->padctl_base + ctl2_offset);
1895
1896         reg = readl(tegra->padctl_base + ctl4_offset);
1897         reg = tegra->pdata->dfe_cntl;
1898         writel(reg, tegra->padctl_base + ctl4_offset);
1899
1900         reg = readl(tegra->padctl_base + ctl5_offset);
1901         reg |= RX_QEYE_EN;
1902         writel(reg, tegra->padctl_base + ctl5_offset);
1903
1904         reg = readl(tegra->padctl_base + padregs->ss_port_map_0);
1905         reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0);
1906         reg |= (tegra->bdata->ss_portmap &
1907                 (port ? TEGRA_XUSB_SS1_PORT_MAP : TEGRA_XUSB_SS0_PORT_MAP));
1908         writel(reg, tegra->padctl_base + padregs->ss_port_map_0);
1909
1910         tegra_xhci_restore_dfe_ctle_context(tegra, port);
1911 }
1912
1913 /* This function assigns the USB ports to the controllers,
1914  * then programs the port capabilities and pad parameters
1915  * of ports assigned to XUSB after booted to OS.
1916  */
1917 void
1918 tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
1919 {
1920         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
1921         u32 reg, oc_bits = 0;
1922         unsigned pad;
1923
1924         reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1925         reg &= ~(USB2_BIAS_HS_SQUELCH_LEVEL | USB2_BIAS_HS_DISCON_LEVEL);
1926         reg |= tegra->pdata->hs_squelch_level | tegra->pdata->hs_disc_lvl;
1927         writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
1928
1929         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1930         reg |= SNPS_OC_MAP_CTRL1 | SNPS_OC_MAP_CTRL2 | SNPS_OC_MAP_CTRL3;
1931         writel(reg, tegra->padctl_base + padregs->snps_oc_map_0);
1932         reg = readl(tegra->padctl_base + padregs->snps_oc_map_0);
1933
1934         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1935         reg |= OC_DET_VBUS_ENABLE0_OC_MAP | OC_DET_VBUS_ENABLE1_OC_MAP;
1936         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1937                 reg |= OC_DET_VBUS_ENABLE2_OC_MAP;
1938         writel(reg, tegra->padctl_base + padregs->oc_det_0);
1939
1940         /* check if over current seen. Clear if present */
1941         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1942                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
1943         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1944                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
1945         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1946                 oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
1947
1948         reg = readl(tegra->padctl_base + padregs->oc_det_0);
1949         if (reg & oc_bits) {
1950                 xhci_info(tegra->xhci, "Over current detected. Clearing...\n");
1951                 writel(reg, tegra->padctl_base + padregs->oc_det_0);
1952
1953                 usleep_range(100, 200);
1954
1955                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
1956                 if (reg & oc_bits)
1957                         xhci_info(tegra->xhci, "Over current still present\n");
1958         }
1959
1960         reg = readl(tegra->padctl_base + padregs->usb2_oc_map_0);
1961         reg = USB2_OC_MAP_PORT0 | USB2_OC_MAP_PORT1;
1962         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1963                 reg |= USB2_OC_MAP_PORT2;
1964         writel(reg, tegra->padctl_base + padregs->usb2_oc_map_0);
1965
1966         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
1967                 tegra_xhci_program_utmip_pad(tegra, 0);
1968         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
1969                 tegra_xhci_program_utmip_pad(tegra, 1);
1970         if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
1971                 tegra_xhci_program_utmip_pad(tegra, 2);
1972
1973         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
1974                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap)
1975                         hsic_pad_enable(tegra, pad);
1976         }
1977
1978         if (tegra->bdata->portmap & TEGRA_XUSB_ULPI_P0)
1979                 tegra_xhci_program_ulpi_pad(tegra, 0);
1980
1981         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P0) {
1982                 tegra_xhci_program_ss_pad(tegra, 0);
1983         } else {
1984                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1985                 reg = readl(tegra->padctl_base +
1986                         padregs->iophy_misc_pad_p0_ctl3_0);
1987                 reg &= ~RX_IDLE_MODE;
1988                 reg |= RX_IDLE_MODE_OVRD;
1989                 writel(reg, tegra->padctl_base +
1990                         padregs->iophy_misc_pad_p0_ctl3_0);
1991         }
1992
1993         if (tegra->bdata->portmap & TEGRA_XUSB_SS_P1) {
1994                 tegra_xhci_program_ss_pad(tegra, 1);
1995         } else {
1996                 /* set rx_idle_mode_ovrd for unused SS ports to save power */
1997                 reg = readl(tegra->padctl_base +
1998                         padregs->iophy_misc_pad_p1_ctl3_0);
1999                 reg &= ~RX_IDLE_MODE;
2000                 reg |= RX_IDLE_MODE_OVRD;
2001                 writel(reg, tegra->padctl_base +
2002                         padregs->iophy_misc_pad_p1_ctl3_0);
2003
2004                 /* SATA lane also if USB3_SS port1 mapped to it but unused */
2005                 if (XUSB_DEVICE_ID_T114 != tegra->device_id &&
2006                                 tegra->bdata->lane_owner & BIT(0)) {
2007                         reg = readl(tegra->padctl_base +
2008                                 padregs->iophy_misc_pad_s0_ctl3_0);
2009                         reg &= ~RX_IDLE_MODE;
2010                         reg |= RX_IDLE_MODE_OVRD;
2011                         writel(reg, tegra->padctl_base +
2012                                 padregs->iophy_misc_pad_s0_ctl3_0);
2013                 }
2014         }
2015         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2016                 tegra_xhci_setup_gpio_for_ss_lane(tegra);
2017                 usb3_phy_pad_enable(tegra->bdata->lane_owner);
2018         }
2019 }
2020
2021 /* This function read XUSB registers and stores in device context */
2022 static void
2023 tegra_xhci_save_xusb_ctx(struct tegra_xhci_hcd *tegra)
2024 {
2025
2026         /* a. Save the IPFS registers */
2027         tegra->sregs.msi_bar_sz =
2028                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2029
2030         tegra->sregs.msi_axi_barst =
2031                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2032
2033         tegra->sregs.msi_fpci_barst =
2034                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2035
2036         tegra->sregs.msi_vec0 =
2037                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2038
2039         tegra->sregs.msi_en_vec0 =
2040                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2041
2042         tegra->sregs.fpci_error_masks =
2043                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2044
2045         tegra->sregs.intr_mask =
2046                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2047
2048         tegra->sregs.ipfs_intr_enable =
2049                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2050
2051         tegra->sregs.ufpci_config =
2052                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2053
2054         tegra->sregs.clkgate_hysteresis =
2055                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2056
2057         tegra->sregs.xusb_host_mccif_fifo_cntrl =
2058                 readl(tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2059
2060         /* b. Save the CFG registers */
2061
2062         tegra->sregs.hs_pls =
2063                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2064
2065         tegra->sregs.fs_pls =
2066                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2067
2068         tegra->sregs.hs_fs_speed =
2069                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2070
2071         tegra->sregs.hs_fs_pp =
2072                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2073
2074         tegra->sregs.cfg_aru =
2075                 readl(tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2076
2077         tegra->sregs.cfg_order =
2078                 readl(tegra->fpci_base + XUSB_CFG_FPCICFG);
2079
2080         tegra->sregs.cfg_fladj =
2081                 readl(tegra->fpci_base + XUSB_CFG_24);
2082
2083         tegra->sregs.cfg_sid =
2084                 readl(tegra->fpci_base + XUSB_CFG_16);
2085 }
2086
2087 /* This function restores XUSB registers from device context */
2088 static void
2089 tegra_xhci_restore_ctx(struct tegra_xhci_hcd *tegra)
2090 {
2091         /* Restore Cfg registers */
2092         writel(tegra->sregs.hs_pls,
2093                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HS_PLS);
2094
2095         writel(tegra->sregs.fs_pls,
2096                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_FS_PLS);
2097
2098         writel(tegra->sregs.hs_fs_speed,
2099                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_SPEED);
2100
2101         writel(tegra->sregs.hs_fs_pp,
2102                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT_HSFS_PP);
2103
2104         writel(tegra->sregs.cfg_aru,
2105                 tegra->fpci_base + XUSB_CFG_ARU_CONTEXT);
2106
2107         writel(tegra->sregs.cfg_order,
2108                 tegra->fpci_base + XUSB_CFG_FPCICFG);
2109
2110         writel(tegra->sregs.cfg_fladj,
2111                 tegra->fpci_base + XUSB_CFG_24);
2112
2113         writel(tegra->sregs.cfg_sid,
2114                 tegra->fpci_base + XUSB_CFG_16);
2115
2116         /* Restore IPFS registers */
2117
2118         writel(tegra->sregs.msi_bar_sz,
2119                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_BAR_SZ_0);
2120
2121         writel(tegra->sregs.msi_axi_barst,
2122                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0);
2123
2124         writel(tegra->sregs.msi_fpci_barst,
2125                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_BAR_ST_0);
2126
2127         writel(tegra->sregs.msi_vec0,
2128                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_VEC0_0);
2129
2130         writel(tegra->sregs.msi_en_vec0,
2131                 tegra->ipfs_base + IPFS_XUSB_HOST_MSI_EN_VEC0_0);
2132
2133         writel(tegra->sregs.fpci_error_masks,
2134                 tegra->ipfs_base + IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0);
2135
2136         writel(tegra->sregs.intr_mask,
2137                 tegra->ipfs_base + IPFS_XUSB_HOST_INTR_MASK_0);
2138
2139         writel(tegra->sregs.ipfs_intr_enable,
2140                 tegra->ipfs_base + IPFS_XUSB_HOST_IPFS_INTR_ENABLE_0);
2141
2142         writel(tegra->sregs.ufpci_config,
2143                 tegra->fpci_base + IPFS_XUSB_HOST_UFPCI_CONFIG_0);
2144
2145         writel(tegra->sregs.clkgate_hysteresis,
2146                 tegra->ipfs_base + IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
2147
2148         writel(tegra->sregs.xusb_host_mccif_fifo_cntrl,
2149                 tegra->ipfs_base + IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0);
2150 }
2151
2152 static void tegra_xhci_enable_fw_message(struct tegra_xhci_hcd *tegra)
2153 {
2154         struct platform_device *pdev = tegra->pdev;
2155         u32 reg, timeout = 0xff, cmd;
2156
2157         mutex_lock(&tegra->mbox_lock);
2158
2159         do {
2160                 writel(MBOX_OWNER_SW,
2161                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2162                 reg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2163                 usleep_range(10, 20);
2164         } while (reg != MBOX_OWNER_SW && timeout--);
2165
2166         if ((timeout == 0) && (reg != MBOX_OWNER_SW)) {
2167                 dev_err(&pdev->dev, "Failed to set mbox message owner ID\n");
2168                 mutex_unlock(&tegra->mbox_lock);
2169                 return;
2170         }
2171
2172         writel((MBOX_CMD_MSG_ENABLED << MBOX_CMD_SHIFT),
2173                         tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2174
2175         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2176         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
2177         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2178
2179         mutex_unlock(&tegra->mbox_lock);
2180 }
2181
2182 static int load_firmware(struct tegra_xhci_hcd *tegra, bool resetARU)
2183 {
2184         struct platform_device *pdev = tegra->pdev;
2185         struct cfgtbl *cfg_tbl = (struct cfgtbl *) tegra->firmware.data;
2186         u32 phys_addr_lo;
2187         u32 HwReg;
2188         u16 nblocks;
2189         time_t fw_time;
2190         struct tm fw_tm;
2191         u8 hc_caplength;
2192         u32 usbsts, count = 0xff;
2193         struct xhci_cap_regs __iomem *cap_regs;
2194         struct xhci_op_regs __iomem *op_regs;
2195
2196         /* enable mbox interrupt */
2197         writel(readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD) | MBOX_INT_EN,
2198                 tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2199
2200         /* First thing, reset the ARU. By the time we get to
2201          * loading boot code below, reset would be complete.
2202          * alternatively we can busy wait on rst pending bit.
2203          */
2204         /* Don't reset during ELPG/LP0 exit path */
2205         if (resetARU) {
2206                 iowrite32(0x1, tegra->fpci_base + XUSB_CFG_ARU_RST);
2207                 usleep_range(1000, 2000);
2208         }
2209
2210         if (csb_read(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
2211                 dev_info(&pdev->dev, "Firmware already loaded, Falcon state 0x%x\n",
2212                                 csb_read(tegra, XUSB_FALC_CPUCTL));
2213                 return 0;
2214         }
2215
2216         /* update the phys_log_buffer and total_entries here */
2217         cfg_tbl->phys_addr_log_buffer = tegra->log.phys_addr;
2218         cfg_tbl->total_log_entries = FW_LOG_COUNT;
2219
2220         phys_addr_lo = tegra->firmware.dma;
2221         phys_addr_lo += sizeof(struct cfgtbl);
2222
2223         /* Program the size of DFI into ILOAD_ATTR */
2224         csb_write(tegra, XUSB_CSB_MP_ILOAD_ATTR, tegra->firmware.size);
2225
2226         /* Boot code of the firmware reads the ILOAD_BASE_LO register
2227          * to get to the start of the dfi in system memory.
2228          */
2229         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_LO, phys_addr_lo);
2230
2231         /* Program the ILOAD_BASE_HI with a value of MSB 32 bits */
2232         csb_write(tegra, XUSB_CSB_MP_ILOAD_BASE_HI, 0);
2233
2234         /* Set BOOTPATH to 1 in APMAP Register. Bit 31 is APMAP_BOOTMAP */
2235         csb_write(tegra, XUSB_CSB_MP_APMAP, APMAP_BOOTPATH);
2236
2237         /* Invalidate L2IMEM. */
2238         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_INVALIDATE_ALL);
2239
2240         /* Initiate fetch of Bootcode from system memory into L2IMEM.
2241          * Program BootCode location and size in system memory.
2242          */
2243         HwReg = ((cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) &
2244                         L2IMEMOP_SIZE_SRC_OFFSET_MASK)
2245                         << L2IMEMOP_SIZE_SRC_OFFSET_SHIFT;
2246         HwReg |= ((cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE) &
2247                         L2IMEMOP_SIZE_SRC_COUNT_MASK)
2248                         << L2IMEMOP_SIZE_SRC_COUNT_SHIFT;
2249         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_SIZE, HwReg);
2250
2251         /* Trigger L2IMEM Load operation. */
2252         csb_write(tegra, XUSB_CSB_MP_L2IMEMOP_TRIG, L2IMEM_LOAD_LOCKED_RESULT);
2253
2254         /* Setup Falcon Auto-fill */
2255         nblocks = (cfg_tbl->boot_codesize / IMEM_BLOCK_SIZE);
2256         if ((cfg_tbl->boot_codesize % IMEM_BLOCK_SIZE) != 0)
2257                 nblocks += 1;
2258         csb_write(tegra, XUSB_FALC_IMFILLCTL, nblocks);
2259
2260         HwReg = (cfg_tbl->boot_codetag / IMEM_BLOCK_SIZE) & IMFILLRNG_TAG_MASK;
2261         HwReg |= (((cfg_tbl->boot_codetag + cfg_tbl->boot_codesize)
2262                         /IMEM_BLOCK_SIZE) - 1) << IMFILLRNG1_TAG_HI_SHIFT;
2263         csb_write(tegra, XUSB_FALC_IMFILLRNG1, HwReg);
2264
2265         csb_write(tegra, XUSB_FALC_DMACTL, 0);
2266         msleep(50);
2267
2268         csb_write(tegra, XUSB_FALC_BOOTVEC, cfg_tbl->boot_codetag);
2269
2270         /* Start Falcon CPU */
2271         csb_write(tegra, XUSB_FALC_CPUCTL, CPUCTL_STARTCPU);
2272         usleep_range(1000, 2000);
2273
2274         fw_time = cfg_tbl->fwimg_created_time;
2275         time_to_tm(fw_time, 0, &fw_tm);
2276         dev_info(&pdev->dev,
2277                 "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC, "\
2278                 "Falcon state 0x%x\n", fw_tm.tm_year + 1900,
2279                 fw_tm.tm_mon + 1, fw_tm.tm_mday, fw_tm.tm_hour,
2280                 fw_tm.tm_min, fw_tm.tm_sec,
2281                 csb_read(tegra, XUSB_FALC_CPUCTL));
2282
2283         dev_dbg(&pdev->dev, "num_hsic_port %d\n", cfg_tbl->num_hsic_port);
2284
2285         /* return fail if firmware status is not good */
2286         if (csb_read(tegra, XUSB_FALC_CPUCTL) == XUSB_FALC_STATE_HALTED)
2287                 return -EFAULT;
2288
2289         cap_regs = IO_ADDRESS(tegra->host_phy_base);
2290         hc_caplength = HC_LENGTH(ioread32(&cap_regs->hc_capbase));
2291         op_regs = IO_ADDRESS(tegra->host_phy_base + hc_caplength);
2292
2293         /* wait for USBSTS_CNR to get set */
2294         do {
2295                 usbsts = ioread32(&op_regs->status);
2296         } while ((usbsts & STS_CNR) && count--);
2297
2298         if (!count && (usbsts & STS_CNR)) {
2299                 dev_err(&pdev->dev, "Controller not ready\n");
2300                 return -EFAULT;
2301         }
2302
2303         /* TODO move this into firmware to avoid race */
2304         writel(0x0, tegra->fpci_base + XUSB_CFG_ARU_C11PAGESEL0);
2305         writel(0x1000, tegra->fpci_base + XUSB_CFG_ARU_C11PAGESEL1);
2306         writel(0x10, tegra->fpci_base + XUSB_CFG_HSPX_CORE_HSICWRAP);
2307         reg_dump(&pdev->dev, tegra->fpci_base, XUSB_CFG_ARU_C11PAGESEL0);
2308         reg_dump(&pdev->dev, tegra->fpci_base, XUSB_CFG_ARU_C11PAGESEL1);
2309         reg_dump(&pdev->dev, tegra->fpci_base, XUSB_CFG_HSPX_CORE_HSICWRAP);
2310
2311         return 0;
2312 }
2313
2314 static void tegra_xhci_release_port_ownership(struct tegra_xhci_hcd *tegra,
2315         bool release)
2316 {
2317         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2318         u32 reg;
2319
2320         /* Issue is only applicable for T114 */
2321         if (XUSB_DEVICE_ID_T114 != tegra->device_id)
2322                 return;
2323
2324         reg = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2325         reg &= ~(USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1) |
2326                         USB2_OTG_PAD_PORT_MASK(2));
2327
2328         if (!release) {
2329                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2330                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(0);
2331                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2332                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2333                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2334                         reg |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2335         }
2336
2337         writel(reg, tegra->padctl_base + padregs->usb2_pad_mux_0);
2338 }
2339 /* SS ELPG Entry initiated by fw */
2340 static int tegra_xhci_ss_elpg_entry(struct tegra_xhci_hcd *tegra)
2341 {
2342         struct xhci_hcd *xhci = tegra->xhci;
2343         u32 ret = 0;
2344
2345         must_have_sync_lock(tegra);
2346
2347         /* This is SS partition ELPG entry
2348          * STEP 0: firmware will set WOC WOD bits in PVTPORTSC2 regs.
2349          */
2350
2351         /* Step 0: Acquire mbox and send PWRGATE msg to firmware
2352          * only if it is sw initiated one
2353          */
2354
2355         /* STEP 1: xHCI firmware and xHCIPEP driver communicates
2356          * SuperSpeed partition ELPG entry via mailbox protocol
2357          */
2358
2359         /* STEP 2: xHCI PEP driver and XUSB device mode driver
2360          * enable the XUSB wakeup interrupts for the SuperSpeed
2361          * and USB2.0 ports assigned to host.Section 4.1 Step 3
2362          */
2363         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
2364
2365         /* STEP 3: xHCI PEP driver initiates the signal sequence
2366          * to enable the XUSB SSwake detection logic for the
2367          * SuperSpeed ports assigned to host.Section 4.1 Step 4
2368          */
2369         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, true);
2370
2371         /* STEP 4: System Power Management driver asserts reset
2372          * to XUSB SuperSpeed partition then disables its clocks
2373          */
2374         tegra_periph_reset_assert(tegra->ss_clk);
2375         clk_disable(tegra->ss_clk);
2376
2377         usleep_range(100, 200);
2378
2379         /* STEP 5: System Power Management driver disables the
2380          * XUSB SuperSpeed partition power rails.
2381          */
2382         debug_print_portsc(xhci);
2383
2384         /* tegra_powergate_partition also does partition reset assert */
2385         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBA);
2386         if (ret) {
2387                 xhci_err(xhci, "%s: could not powergate xusba partition\n",
2388                                 __func__);
2389                 /* TODO: error recovery? */
2390         }
2391         tegra->ss_pwr_gated = true;
2392
2393         /* STEP 6: xHCI PEP driver initiates the signal sequence
2394          * to enable the XUSB SSwake detection logic for the
2395          * SuperSpeed ports assigned to host.Section 4.1 Step 7
2396          */
2397         tegra_xhci_ss_vcore(tegra->bdata->portmap, true);
2398
2399         return ret;
2400 }
2401
2402 /* Host ELPG Entry */
2403 static int tegra_xhci_host_elpg_entry(struct tegra_xhci_hcd *tegra)
2404 {
2405         struct xhci_hcd *xhci = tegra->xhci;
2406         u32 ret;
2407
2408         must_have_sync_lock(tegra);
2409
2410         /* If ss is already powergated skip ss ctx save stuff */
2411         if (tegra->ss_pwr_gated) {
2412                 xhci_info(xhci, "%s: SS partition is already powergated\n",
2413                         __func__);
2414         } else {
2415                 ret = tegra_xhci_ss_elpg_entry(tegra);
2416                 if (ret) {
2417                         xhci_err(xhci, "%s: ss_elpg_entry failed %d\n",
2418                                 __func__, ret);
2419                         return ret;
2420                 }
2421         }
2422
2423         /* 1. IS INTR PENDING INT_PENDING=1 ? */
2424
2425         /* STEP 1.1: Do a context save of XUSB and IPFS registers */
2426         tegra_xhci_save_xusb_ctx(tegra);
2427
2428         /* calculate rctrl_val and tctrl_val */
2429         tegra_xhci_war_for_tctrl_rctrl(tegra);
2430
2431         pmc_setup(tegra, 1);
2432         pmc_setup_wake_detect(tegra);
2433
2434         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
2435         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2436                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2437
2438         /* STEP 4: Assert reset to host clk and disable host clk */
2439         tegra_periph_reset_assert(tegra->host_clk);
2440
2441         clk_disable(tegra->host_clk);
2442
2443         /* wait 150us */
2444         usleep_range(150, 200);
2445
2446         /* flush MC client of XUSB_HOST */
2447         tegra_powergate_mc_flush(TEGRA_POWERGATE_XUSBC);
2448
2449         /* STEP 4: Powergate host partition */
2450         /* tegra_powergate_partition also does partition reset assert */
2451         ret = tegra_powergate_partition(TEGRA_POWERGATE_XUSBC);
2452         if (ret) {
2453                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2454                         __func__, ret);
2455                 /* TODO: error handling? */
2456                 return ret;
2457         }
2458         tegra->host_pwr_gated = true;
2459
2460         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2461                 clk_disable(tegra->pll_re_vco_clk);
2462         clk_disable(tegra->emc_clk);
2463         /* set port ownership to SNPS */
2464         tegra_xhci_release_port_ownership(tegra, true);
2465
2466         xhci_dbg(xhci, "%s: PMC_UTMIP_UHSIC_SLEEP_CFG_0 = %x\n", __func__,
2467                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
2468
2469         xhci_info(xhci, "%s: elpg_entry: completed\n", __func__);
2470         xhci_dbg(xhci, "%s: HOST POWER STATUS = %d\n",
2471                 __func__, tegra_powergate_is_powered(TEGRA_POWERGATE_XUSBC));
2472         return ret;
2473 }
2474
2475 /* SS ELPG Exit triggered by PADCTL irq */
2476 /**
2477  * tegra_xhci_ss_partition_elpg_exit - bring XUSBA partition out from elpg
2478  *
2479  * This function must be called with tegra->sync_lock acquired.
2480  *
2481  * @tegra: xhci controller context
2482  * @return 0 for success, or error numbers
2483  */
2484 static int tegra_xhci_ss_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2485 {
2486         struct xhci_hcd *xhci = tegra->xhci;
2487         int ret = 0;
2488
2489         must_have_sync_lock(tegra);
2490
2491         if (tegra->ss_pwr_gated && (tegra->ss_wake_event ||
2492                         tegra->hs_wake_event || tegra->host_resume_req)) {
2493
2494                 /*
2495                  * PWR_UNGATE SS partition. XUSBA
2496                  * tegra_unpowergate_partition also does partition reset
2497                  * deassert
2498                  */
2499                 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
2500                 if (ret) {
2501                         xhci_err(xhci,
2502                         "%s: could not unpowergate xusba partition %d\n",
2503                         __func__, ret);
2504                         goto out;
2505                 }
2506                 if (tegra->ss_wake_event)
2507                         tegra->ss_wake_event = false;
2508
2509         } else {
2510                 xhci_info(xhci, "%s: ss already power gated\n",
2511                         __func__);
2512                 return ret;
2513         }
2514
2515         /* Step 3: Enable clock to ss partition */
2516         clk_enable(tegra->ss_clk);
2517
2518         /* Step 4: Disable ss wake detection logic */
2519         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
2520
2521         /* Step 4.1: Disable ss wake detection logic */
2522         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
2523
2524         /* wait 150us */
2525         usleep_range(150, 200);
2526
2527         /* Step 4.2: Disable ss wake detection logic */
2528         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
2529
2530         /* Step 6 Deassert reset for ss clks */
2531         tegra_periph_reset_deassert(tegra->ss_clk);
2532
2533         xhci_dbg(xhci, "%s: SS ELPG EXIT. ALL DONE\n", __func__);
2534         tegra->ss_pwr_gated = false;
2535 out:
2536         return ret;
2537 }
2538
2539 static void ss_partition_elpg_exit_work(struct work_struct *work)
2540 {
2541         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2542                 ss_elpg_exit_work);
2543
2544         mutex_lock(&tegra->sync_lock);
2545         tegra_xhci_ss_partition_elpg_exit(tegra);
2546         mutex_unlock(&tegra->sync_lock);
2547 }
2548
2549 /* read pmc WAKE2_STATUS register to know if SS port caused remote wake */
2550 static void update_remote_wakeup_ports_pmc(struct tegra_xhci_hcd *tegra)
2551 {
2552         struct xhci_hcd *xhci = tegra->xhci;
2553         u32 wake2_status;
2554
2555 #define PMC_WAKE2_STATUS        0x168
2556 #define PADCTL_WAKE             (1 << (58 - 32)) /* PADCTL is WAKE#58 */
2557
2558         wake2_status = tegra_usb_pmc_reg_read(PMC_WAKE2_STATUS);
2559
2560         if (wake2_status & PADCTL_WAKE) {
2561                 /* FIXME: This is customized for Dalmore, find a generic way */
2562                 set_bit(0, &tegra->usb3_rh_remote_wakeup_ports);
2563                 /* clear wake status */
2564                 tegra_usb_pmc_reg_write(PMC_WAKE2_STATUS, PADCTL_WAKE);
2565         }
2566
2567         xhci_dbg(xhci, "%s: usb3 roothub remote_wakeup_ports 0x%lx\n",
2568                         __func__, tegra->usb3_rh_remote_wakeup_ports);
2569 }
2570
2571 static void wait_remote_wakeup_ports(struct usb_hcd *hcd)
2572 {
2573         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2574         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
2575         int port, num_ports;
2576         unsigned long *remote_wakeup_ports;
2577         u32 portsc;
2578         __le32 __iomem  **port_array;
2579         unsigned char *rh;
2580         unsigned int retry = 64;
2581
2582
2583         if (hcd == xhci->shared_hcd) {
2584                 port_array = xhci->usb3_ports;
2585                 num_ports = xhci->num_usb3_ports;
2586                 remote_wakeup_ports = &tegra->usb3_rh_remote_wakeup_ports;
2587                 rh = "usb3 roothub";
2588         } else
2589                 return;
2590
2591         while (*remote_wakeup_ports && retry--) {
2592                 for_each_set_bit(port, remote_wakeup_ports, num_ports) {
2593                         portsc = xhci_readl(xhci, port_array[port]);
2594
2595                         if (!(portsc & PORT_CONNECT)) {
2596                                 /* nothing to do if already disconnected */
2597                                 clear_bit(port, remote_wakeup_ports);
2598                                 continue;
2599                         }
2600
2601                         if ((portsc & PORT_PLS_MASK) == XDEV_U0)
2602                                 clear_bit(port, remote_wakeup_ports);
2603                         else
2604                                 xhci_dbg(xhci, "%s: %s port %d status 0x%x\n",
2605                                                 __func__, rh, port, portsc);
2606                 }
2607
2608                 if (*remote_wakeup_ports)
2609                         msleep(20); /* give some time, irq will direct U0 */
2610         }
2611
2612         xhci_dbg(xhci, "%s: %s remote_wakeup_ports 0x%lx\n", __func__, rh,
2613                         *remote_wakeup_ports);
2614 }
2615
2616 static void tegra_xhci_war_for_tctrl_rctrl(struct tegra_xhci_hcd *tegra)
2617 {
2618         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2619         u32 reg, utmip_rctrl_val, utmip_tctrl_val, pad_mux, portmux, portowner;
2620
2621         portmux = USB2_OTG_PAD_PORT_MASK(0) | USB2_OTG_PAD_PORT_MASK(1);
2622         portowner = USB2_OTG_PAD_PORT_OWNER_XUSB(0) |
2623                         USB2_OTG_PAD_PORT_OWNER_XUSB(1);
2624
2625         if (XUSB_DEVICE_ID_T114 != tegra->device_id) {
2626                 portmux |= USB2_OTG_PAD_PORT_MASK(2);
2627                 portowner |= USB2_OTG_PAD_PORT_OWNER_XUSB(2);
2628         }
2629
2630         /* Use xusb padctl space only when xusb owns all UTMIP port */
2631         pad_mux = readl(tegra->padctl_base + padregs->usb2_pad_mux_0);
2632         if ((pad_mux & portmux) == portowner) {
2633                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 0 and
2634                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 0
2635                  */
2636                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2637                 reg &= ~((1 << 12) | (1 << 13));
2638                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2639
2640                 /* wait 20us */
2641                 usleep_range(20, 30);
2642
2643                 /* Read XUSB_PADCTL:: XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
2644                  * :: TCTRL and RCTRL
2645                  */
2646                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl1_0);
2647                 utmip_rctrl_val = RCTRL(reg);
2648                 utmip_tctrl_val = TCTRL(reg);
2649
2650                 /*
2651                  * tctrl_val = 0x1f - (16 - ffz(utmip_tctrl_val)
2652                  * rctrl_val = 0x1f - (16 - ffz(utmip_rctrl_val)
2653                  */
2654                 pmc_data.utmip_rctrl_val = 0xf + ffz(utmip_rctrl_val);
2655                 pmc_data.utmip_tctrl_val = 0xf + ffz(utmip_tctrl_val);
2656
2657                 xhci_dbg(tegra->xhci, "rctrl_val = 0x%x, tctrl_val = 0x%x\n",
2658                         pmc_data.utmip_rctrl_val, pmc_data.utmip_tctrl_val);
2659
2660                 /* XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD = 1 and
2661                  * XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0::PD_TRK = 1
2662                  */
2663                 reg = readl(tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2664                 reg |= (1 << 13);
2665                 writel(reg, tegra->padctl_base + padregs->usb2_bias_pad_ctl0_0);
2666
2667                 /* Program these values into PMC regiseter and program the
2668                  * PMC override
2669                  */
2670                 reg = PMC_TCTRL_VAL(pmc_data.utmip_tctrl_val) |
2671                         PMC_RCTRL_VAL(pmc_data.utmip_rctrl_val);
2672                 tegra_usb_pmc_reg_update(PMC_UTMIP_TERM_PAD_CFG,
2673                         0xffffffff, reg);
2674
2675                 reg = UTMIP_RCTRL_USE_PMC_P2 | UTMIP_TCTRL_USE_PMC_P2;
2676                 tegra_usb_pmc_reg_update(PMC_SLEEP_CFG, reg, reg);
2677         } else {
2678                 /* TODO use common PMC API to use SNPS register space */
2679         }
2680 }
2681
2682 /* Host ELPG Exit triggered by PADCTL irq */
2683 /**
2684  * tegra_xhci_host_partition_elpg_exit - bring XUSBC partition out from elpg
2685  *
2686  * This function must be called with tegra->sync_lock acquired.
2687  *
2688  * @tegra: xhci controller context
2689  * @return 0 for success, or error numbers
2690  */
2691 static int
2692 tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
2693 {
2694         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
2695         struct xhci_hcd *xhci = tegra->xhci;
2696         int ret = 0;
2697
2698         must_have_sync_lock(tegra);
2699
2700         if (!tegra->hc_in_elpg)
2701                 return 0;
2702
2703         clk_enable(tegra->emc_clk);
2704         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
2705                 clk_enable(tegra->pll_re_vco_clk);
2706
2707         if (tegra->lp0_exit) {
2708                 u32 reg, oc_bits = 0;
2709
2710                 /* Issue is only applicable for T114 */
2711                 if (XUSB_DEVICE_ID_T114 == tegra->device_id)
2712                         tegra_xhci_war_for_tctrl_rctrl(tegra);
2713                 /* check if over current seen. Clear if present */
2714                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P0)
2715                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD0;
2716                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P1)
2717                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD1;
2718                 if (tegra->bdata->portmap & TEGRA_XUSB_USB2_P2)
2719                         oc_bits |= OC_DET_OC_DETECTED_VBUS_PAD2;
2720
2721                 reg = readl(tegra->padctl_base + padregs->oc_det_0);
2722                 xhci_dbg(xhci, "%s: oc_det_0=0x%x\n", __func__, reg);
2723                 if (reg & oc_bits) {
2724                         xhci_info(xhci, "Over current detected. Clearing...\n");
2725                         writel(reg, tegra->padctl_base + padregs->oc_det_0);
2726
2727                         usleep_range(100, 200);
2728
2729                         reg = readl(tegra->padctl_base + padregs->oc_det_0);
2730                         if (reg & oc_bits)
2731                                 xhci_info(xhci, "Over current still present\n");
2732                 }
2733                 tegra_xhci_padctl_portmap_and_caps(tegra);
2734                 /* release clamps post deassert */
2735                 tegra->lp0_exit = false;
2736         }
2737
2738         /* Clear FLUSH_ENABLE of MC client */
2739         tegra_powergate_mc_flush_done(TEGRA_POWERGATE_XUSBC);
2740
2741         /* set port ownership back to xusb */
2742         tegra_xhci_release_port_ownership(tegra, false);
2743
2744         /*
2745          * PWR_UNGATE Host partition. XUSBC
2746          * tegra_unpowergate_partition also does partition reset deassert
2747          */
2748         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
2749         if (ret) {
2750                 xhci_err(xhci, "%s: could not unpowergate xusbc partition %d\n",
2751                         __func__, ret);
2752                 goto out;
2753         }
2754         clk_enable(tegra->host_clk);
2755
2756         /* Step 4: Deassert reset to host partition clk */
2757         tegra_periph_reset_deassert(tegra->host_clk);
2758
2759         /* Step 6.1: IPFS and XUSB BAR initialization */
2760         tegra_xhci_cfg(tegra);
2761
2762         /* Step 6.2: IPFS and XUSB related restore */
2763         tegra_xhci_restore_ctx(tegra);
2764
2765         /* Step 8: xhci spec related ctx restore
2766          * will be done in xhci_resume().Do it here.
2767          */
2768
2769         tegra_xhci_ss_partition_elpg_exit(tegra);
2770
2771         /* Change SS clock source to HSIC_480 and set ss_src_clk at 120MHz */
2772         if (clk_get_rate(tegra->ss_src_clk) == 12000000) {
2773                 clk_set_rate(tegra->ss_src_clk,  3000 * 1000);
2774                 clk_set_parent(tegra->ss_src_clk, tegra->pll_u_480M);
2775         }
2776
2777         /* clear ovrd bits */
2778         tegra_xhci_rx_idle_mode_override(tegra, false);
2779
2780         /* Load firmware */
2781         xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
2782                         "ss (p1=0x%x, p2=0x%x, p3=0x%x), "
2783                         "hs (p1=0x%x, p2=0x%x, p3=0x%x),\n"
2784                         "fs (p1=0x%x, p2=0x%x, p3=0x%x)\n",
2785                         __func__,
2786                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC1),
2787                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC2),
2788                         csb_read(tegra, XUSB_FALC_SS_PVTPORTSC3),
2789                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC1),
2790                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC2),
2791                         csb_read(tegra, XUSB_FALC_HS_PVTPORTSC3),
2792                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC1),
2793                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC2),
2794                         csb_read(tegra, XUSB_FALC_FS_PVTPORTSC3));
2795         debug_print_portsc(xhci);
2796
2797         ret = load_firmware(tegra, false /* EPLG exit, do not reset ARU */);
2798         if (ret < 0) {
2799                 xhci_err(xhci, "%s: failed to load firmware %d\n",
2800                         __func__, ret);
2801                 goto out;
2802         }
2803
2804         pmc_setup(tegra, 0);
2805         pmc_disable_bus_ctrl(tegra);
2806
2807         tegra->hc_in_elpg = false;
2808         ret = xhci_resume(tegra->xhci, 0);
2809         if (ret) {
2810                 xhci_err(xhci, "%s: could not resume right %d\n",
2811                                 __func__, ret);
2812                 goto out;
2813         }
2814
2815         update_remote_wakeup_ports_pmc(tegra);
2816
2817         if (tegra->hs_wake_event)
2818                 tegra->hs_wake_event = false;
2819
2820         if (tegra->host_resume_req)
2821                 tegra->host_resume_req = false;
2822
2823         xhci_info(xhci, "elpg_exit: completed: lp0/elpg time=%d msec\n",
2824                 jiffies_to_msecs(jiffies - tegra->last_jiffies));
2825
2826         tegra->host_pwr_gated = false;
2827 out:
2828         return ret;
2829 }
2830
2831 static void host_partition_elpg_exit_work(struct work_struct *work)
2832 {
2833         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2834                 host_elpg_exit_work);
2835
2836         mutex_lock(&tegra->sync_lock);
2837         tegra_xhci_host_partition_elpg_exit(tegra);
2838         mutex_unlock(&tegra->sync_lock);
2839 }
2840
2841 /* Mailbox handling function. This function handles requests
2842  * from firmware and communicates with clock and powergating
2843  * module to alter clock rates and to power gate/ungate xusb
2844  * partitions.
2845  *
2846  * Following is the structure of mailbox messages.
2847  * bit 31:28 - msg type
2848  * bits 27:0 - mbox data
2849  * FIXME:  Check if we can just call clock functions like below
2850  * or should we schedule it for calling later ?
2851  */
2852
2853 static void
2854 tegra_xhci_process_mbox_message(struct work_struct *work)
2855 {
2856         u32 sw_resp = 0, cmd, data_in, fw_msg;
2857         int ret = 0;
2858         struct tegra_xhci_hcd *tegra = container_of(work, struct tegra_xhci_hcd,
2859                                         mbox_work);
2860         struct xhci_hcd *xhci = tegra->xhci;
2861         unsigned int freq_khz;
2862         int pad, port;
2863         unsigned long ports;
2864
2865         mutex_lock(&tegra->mbox_lock);
2866
2867         /* get the owner id */
2868         tegra->mbox_owner = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2869         tegra->mbox_owner &= MBOX_OWNER_ID_MASK;
2870
2871         /* get the mbox message from firmware */
2872         fw_msg = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_OUT);
2873
2874         data_in = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2875         if (data_in) {
2876                 mutex_unlock(&tegra->mbox_lock);
2877                 return;
2878         }
2879
2880         /* get cmd type and cmd data */
2881         tegra->cmd_type = (fw_msg & MBOX_CMD_TYPE_MASK) >> MBOX_CMD_SHIFT;
2882         tegra->cmd_data = (fw_msg & MBOX_CMD_DATA_MASK);
2883
2884         /* decode the message and make appropriate requests to
2885          * clock or powergating module.
2886          */
2887
2888         switch (tegra->cmd_type) {
2889         case MBOX_CMD_INC_FALC_CLOCK:
2890         case MBOX_CMD_DEC_FALC_CLOCK:
2891                 ret = tegra_xusb_request_clk_rate(
2892                                 tegra,
2893                                 tegra->falc_clk,
2894                                 tegra->cmd_data,
2895                                 &sw_resp);
2896                 if (ret)
2897                         xhci_err(xhci, "%s: could not set required falc rate\n",
2898                                 __func__);
2899                 goto send_sw_response;
2900         case MBOX_CMD_INC_SSPI_CLOCK:
2901         case MBOX_CMD_DEC_SSPI_CLOCK:
2902                 ret = tegra_xusb_request_clk_rate(
2903                                 tegra,
2904                                 tegra->ss_src_clk,
2905                                 tegra->cmd_data,
2906                                 &sw_resp);
2907                 if (ret)
2908                         xhci_err(xhci, "%s: could not set required ss rate.\n",
2909                                 __func__);
2910                 goto send_sw_response;
2911         case MBOX_CMD_SET_BW:
2912                 /* fw sends BW request in MByte/sec */
2913                 freq_khz = tegra_emc_bw_to_freq_req(tegra->cmd_data << 10);
2914                 clk_set_rate(tegra->emc_clk, freq_khz * 1000);
2915
2916                 /* clear MBOX_SMI_INT_EN bit */
2917                 cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2918                 cmd &= ~MBOX_SMI_INT_EN;
2919                 writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2920
2921                 /* clear mbox owner as ACK will not be sent for this request */
2922                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2923                 break;
2924         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
2925                 tegra_xhci_save_dfe_ctle_context(tegra, tegra->cmd_data);
2926                 tegra_xhci_restore_dfe_ctle_context(tegra, tegra->cmd_data);
2927                 sw_resp |= tegra->cmd_data | (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
2928                 goto send_sw_response;
2929
2930         case MBOX_CMD_STAR_HSIC_IDLE:
2931                 ports = sw_resp = tegra->cmd_data;
2932                 for_each_set_bit(port, &ports, MBOX_CMD_SHIFT) {
2933                         pad = port_to_hsic_pad(port - 1);
2934                         mutex_lock(&tegra->sync_lock);
2935                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_IDLE);
2936                         mutex_unlock(&tegra->sync_lock);
2937                         if (ret)
2938                                 break;
2939                 }
2940
2941                 if (!ret)
2942                         sw_resp |= (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
2943                 else
2944                         sw_resp |= (MBOX_CMD_NACK << MBOX_CMD_SHIFT);
2945
2946                 goto send_sw_response;
2947
2948         case MBOX_CMD_STOP_HSIC_IDLE:
2949                 ports = sw_resp = tegra->cmd_data;
2950                 for_each_set_bit(port, &ports, MBOX_CMD_SHIFT) {
2951                         pad = port_to_hsic_pad(port - 1);
2952                         mutex_lock(&tegra->sync_lock);
2953                         ret = hsic_pad_pupd_set(tegra, pad, PUPD_DISABLE);
2954                         mutex_unlock(&tegra->sync_lock);
2955                         if (ret)
2956                                 break;
2957                 }
2958
2959                 if (!ret)
2960                         sw_resp |= (MBOX_CMD_ACK << MBOX_CMD_SHIFT);
2961                 else
2962                         sw_resp |= (MBOX_CMD_NACK << MBOX_CMD_SHIFT);
2963
2964                 goto send_sw_response;
2965
2966         case MBOX_CMD_ACK:
2967                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2968                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2969                 break;
2970         case MBOX_CMD_NACK:
2971                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2972                 writel(0, tegra->fpci_base + XUSB_CFG_ARU_MBOX_OWNER);
2973                 break;
2974         default:
2975                 xhci_err(xhci, "%s: invalid cmdtype %d\n",
2976                                 __func__, tegra->cmd_type);
2977         }
2978         mutex_unlock(&tegra->mbox_lock);
2979         return;
2980
2981 send_sw_response:
2982         if (((sw_resp & MBOX_CMD_TYPE_MASK) >> MBOX_CMD_SHIFT) == MBOX_CMD_NACK)
2983                 xhci_err(xhci, "%s respond fw message 0x%x with NAK\n",
2984                                 __func__, fw_msg);
2985
2986         writel(sw_resp, tegra->fpci_base + XUSB_CFG_ARU_MBOX_DATA_IN);
2987         cmd = readl(tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2988         cmd |= MBOX_INT_EN | MBOX_FALC_INT_EN;
2989         writel(cmd, tegra->fpci_base + XUSB_CFG_ARU_MBOX_CMD);
2990
2991         mutex_unlock(&tegra->mbox_lock);
2992 }
2993
2994 static irqreturn_t pmc_usb_phy_wake_isr(int irq, void *data)
2995 {
2996         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) data;
2997         struct xhci_hcd *xhci = tegra->xhci;
2998
2999         xhci_dbg(xhci, "%s irq %d", __func__, irq);
3000         return IRQ_HANDLED;
3001 }
3002
3003 static irqreturn_t tegra_xhci_padctl_irq(int irq, void *ptrdev)
3004 {
3005         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3006         struct xhci_hcd *xhci = tegra->xhci;
3007         struct tegra_xusb_padctl_regs *padregs = tegra->padregs;
3008         u32 elpg_program0 = 0;
3009
3010         spin_lock(&tegra->lock);
3011
3012         tegra->last_jiffies = jiffies;
3013
3014         /* Check the intr cause. Could be  USB2 or HSIC or SS wake events */
3015         elpg_program0 = tegra_usb_pad_reg_read(padregs->elpg_program_0);
3016
3017         /* Clear the interrupt cause. We already read the intr status. */
3018         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3019         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3020
3021         xhci_dbg(xhci, "%s: elpg_program0 = %x\n", __func__, elpg_program0);
3022         xhci_dbg(xhci, "%s: PMC REGISTER = %x\n", __func__,
3023                 tegra_usb_pmc_reg_read(PMC_UTMIP_UHSIC_SLEEP_CFG_0));
3024         xhci_dbg(xhci, "%s: OC_DET Register = %x\n",
3025                 __func__, readl(tegra->padctl_base + padregs->oc_det_0));
3026         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad0_ctl0_0 Register = %x\n",
3027                 __func__,
3028                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad0_ctl0_0));
3029         xhci_dbg(xhci, "%s: usb2_bchrg_otgpad1_ctl0_0 Register = %x\n",
3030                 __func__,
3031                 readl(tegra->padctl_base + padregs->usb2_bchrg_otgpad1_ctl0_0));
3032         xhci_dbg(xhci, "%s: usb2_bchrg_bias_pad_0 Register = %x\n",
3033                 __func__,
3034                 readl(tegra->padctl_base + padregs->usb2_bchrg_bias_pad_0));
3035
3036         if (elpg_program0 & (SS_PORT0_WAKEUP_EVENT | SS_PORT1_WAKEUP_EVENT))
3037                 tegra->ss_wake_event = true;
3038         else if (elpg_program0 & (USB2_PORT0_WAKEUP_EVENT |
3039                         USB2_PORT1_WAKEUP_EVENT |
3040                         USB2_PORT2_WAKEUP_EVENT |
3041                         USB2_HSIC_PORT0_WAKEUP_EVENT |
3042                         USB2_HSIC_PORT1_WAKEUP_EVENT))
3043                 tegra->hs_wake_event = true;
3044
3045         if (tegra->ss_wake_event || tegra->hs_wake_event) {
3046                 if (tegra->ss_pwr_gated && !tegra->host_pwr_gated) {
3047                         xhci_err(xhci, "SS gated Host ungated. Should not happen\n");
3048                         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3049                 } else if (tegra->ss_pwr_gated
3050                                 && tegra->host_pwr_gated) {
3051                         xhci_dbg(xhci, "[%s] schedule host_elpg_exit_work\n",
3052                                 __func__);
3053                         schedule_work(&tegra->host_elpg_exit_work);
3054                 }
3055         } else {
3056                 xhci_err(xhci, "error: wake due to no hs/ss event\n");
3057                 tegra_usb_pad_reg_write(padregs->elpg_program_0, 0xffffffff);
3058         }
3059         spin_unlock(&tegra->lock);
3060         return IRQ_HANDLED;
3061 }
3062
3063 static irqreturn_t tegra_xhci_smi_irq(int irq, void *ptrdev)
3064 {
3065         struct tegra_xhci_hcd *tegra = (struct tegra_xhci_hcd *) ptrdev;
3066         u32 temp;
3067
3068         spin_lock(&tegra->lock);
3069
3070         /* clear the mbox intr status 1st thing. Other
3071          * bits are W1C bits, so just write to SMI bit.
3072          */
3073
3074         temp = readl(tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3075
3076         /* write 1 to clear SMI INTR en bit ( bit 3 ) */
3077         temp = MBOX_SMI_INTR_EN;
3078         writel(temp, tegra->fpci_base + XUSB_CFG_ARU_SMI_INTR);
3079
3080         schedule_work(&tegra->mbox_work);
3081
3082         spin_unlock(&tegra->lock);
3083         return IRQ_HANDLED;
3084 }
3085
3086 static void tegra_xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
3087 {
3088         /*
3089          * As of now platform drivers don't provide MSI support so we ensure
3090          * here that the generic code does not try to make a pci_dev from our
3091          * dev struct in order to setup MSI
3092          */
3093         xhci->quirks |= XHCI_BROKEN_MSI;
3094         xhci->quirks &= ~XHCI_SPURIOUS_REBOOT;
3095 }
3096
3097 /* called during probe() after chip reset completes */
3098 static int xhci_plat_setup(struct usb_hcd *hcd)
3099 {
3100         return xhci_gen_setup(hcd, tegra_xhci_plat_quirks);
3101 }
3102
3103 static int tegra_xhci_request_mem_region(struct platform_device *pdev,
3104         const char *name, void __iomem **region)
3105 {
3106         struct resource *res;
3107         void __iomem *mem;
3108
3109         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
3110         if (!res) {
3111                 dev_err(&pdev->dev, "memory resource %s doesn't exist\n", name);
3112                 return -ENODEV;
3113         }
3114
3115         mem = devm_request_and_ioremap(&pdev->dev, res);
3116         if (!mem) {
3117                 dev_err(&pdev->dev, "failed to ioremap for %s\n", name);
3118                 return -EFAULT;
3119         }
3120         *region = mem;
3121
3122         return 0;
3123 }
3124
3125 static int tegra_xhci_request_irq(struct platform_device *pdev,
3126         const char *rscname, irq_handler_t handler, unsigned long irqflags,
3127         const char *devname, int *irq_no)
3128 {
3129         int ret;
3130         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3131         struct resource *res;
3132
3133         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, rscname);
3134         if (!res) {
3135                 dev_err(&pdev->dev, "irq resource %s doesn't exist\n", rscname);
3136                 return -ENODEV;
3137         }
3138
3139         ret = devm_request_irq(&pdev->dev, res->start, handler, irqflags,
3140                         devname, tegra);
3141         if (ret != 0) {
3142                 dev_err(&pdev->dev,
3143                         "failed to request_irq for %s (irq %d), error = %d\n",
3144                         devname, res->start, ret);
3145                 return ret;
3146         }
3147         *irq_no = res->start;
3148
3149         return 0;
3150 }
3151
3152 #ifdef CONFIG_PM
3153
3154 static int tegra_xhci_bus_suspend(struct usb_hcd *hcd)
3155 {
3156         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3157         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3158         int err = 0;
3159         unsigned long flags;
3160
3161         mutex_lock(&tegra->sync_lock);
3162
3163         if (xhci->shared_hcd == hcd) {
3164                 tegra->usb3_rh_suspend = true;
3165                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3166         } else if (xhci->main_hcd == hcd) {
3167                 tegra->usb2_rh_suspend = true;
3168                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3169         }
3170
3171         WARN_ON(tegra->hc_in_elpg);
3172
3173         /* suspend xhci bus. This will also set remote mask */
3174         err = xhci_bus_suspend(hcd);
3175         if (err) {
3176                 xhci_err(xhci, "%s: xhci_bus_suspend failed %d\n",
3177                                 __func__, err);
3178                 goto xhci_bus_suspend_failed;
3179         }
3180
3181         if (!(tegra->usb2_rh_suspend && tegra->usb3_rh_suspend))
3182                 goto done; /* one of the root hubs is still working */
3183
3184         spin_lock_irqsave(&tegra->lock, flags);
3185         tegra->hc_in_elpg = true;
3186         spin_unlock_irqrestore(&tegra->lock, flags);
3187
3188         WARN_ON(tegra->ss_pwr_gated && tegra->host_pwr_gated);
3189
3190         /* save xhci spec ctx. Already done by xhci_suspend */
3191         err = xhci_suspend(tegra->xhci);
3192         if (err) {
3193                 xhci_err(xhci, "%s: xhci_suspend failed %d\n", __func__, err);
3194                 goto xhci_suspend_failed;
3195         }
3196
3197         /* Powergate host. Include ss power gate if not already done */
3198         err = tegra_xhci_host_elpg_entry(tegra);
3199         if (err) {
3200                 xhci_err(xhci, "%s: unable to perform elpg entry %d\n",
3201                                 __func__, err);
3202                 goto tegra_xhci_host_elpg_entry_failed;
3203         }
3204
3205         /* At this point,ensure ss/hs intr enables are always on */
3206         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, true);
3207         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, true);
3208
3209         /* In ELPG, firmware log context is gone. Rewind shared log buffer. */
3210         if (fw_log_wait_empty_timeout(tegra, 100))
3211                 xhci_warn(xhci, "%s still has logs\n", __func__);
3212         tegra->log.dequeue = tegra->log.virt_addr;
3213         tegra->log.seq = 0;
3214
3215 done:
3216         /* pads are disabled only if usb2 root hub in xusb is idle */
3217         /* pads will actually be disabled only when all usb2 ports are idle */
3218         if (xhci->main_hcd == hcd) {
3219                 utmi_phy_pad_disable();
3220                 utmi_phy_iddq_override(true);
3221         }
3222         mutex_unlock(&tegra->sync_lock);
3223         return 0;
3224
3225 tegra_xhci_host_elpg_entry_failed:
3226
3227 xhci_suspend_failed:
3228         tegra->hc_in_elpg = false;
3229 xhci_bus_suspend_failed:
3230         if (xhci->shared_hcd == hcd)
3231                 tegra->usb3_rh_suspend = false;
3232         else if (xhci->main_hcd == hcd)
3233                 tegra->usb2_rh_suspend = false;
3234
3235         mutex_unlock(&tegra->sync_lock);
3236         return err;
3237 }
3238
3239 /* First, USB2HCD and then USB3HCD resume will be called */
3240 static int tegra_xhci_bus_resume(struct usb_hcd *hcd)
3241 {
3242         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3243         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3244         int err = 0;
3245
3246         mutex_lock(&tegra->sync_lock);
3247
3248         tegra->host_resume_req = true;
3249
3250         if (xhci->shared_hcd == hcd)
3251                 xhci_dbg(xhci, "%s: usb3 root hub\n", __func__);
3252         else if (xhci->main_hcd == hcd)
3253                 xhci_dbg(xhci, "%s: usb2 root hub\n", __func__);
3254
3255         /* pads are disabled only if usb2 root hub in xusb is idle */
3256         /* pads will actually be disabled only when all usb2 ports are idle */
3257         if (xhci->main_hcd == hcd && tegra->usb2_rh_suspend) {
3258                 utmi_phy_pad_enable();
3259                 utmi_phy_iddq_override(false);
3260         }
3261         if (tegra->usb2_rh_suspend && tegra->usb3_rh_suspend) {
3262                 if (tegra->ss_pwr_gated && tegra->host_pwr_gated)
3263                         tegra_xhci_host_partition_elpg_exit(tegra);
3264         }
3265
3266          /* handle remote wakeup before resuming bus */
3267         wait_remote_wakeup_ports(hcd);
3268
3269         err = xhci_bus_resume(hcd);
3270         if (err) {
3271                 xhci_err(xhci, "%s: xhci_bus_resume failed %d\n",
3272                                 __func__, err);
3273                 goto xhci_bus_resume_failed;
3274         }
3275
3276         if (xhci->shared_hcd == hcd)
3277                 tegra->usb3_rh_suspend = false;
3278         else if (xhci->main_hcd == hcd)
3279                 tegra->usb2_rh_suspend = false;
3280
3281         mutex_unlock(&tegra->sync_lock);
3282         return 0;
3283
3284 xhci_bus_resume_failed:
3285         /* TODO: reverse elpg? */
3286         mutex_unlock(&tegra->sync_lock);
3287         return err;
3288 }
3289 #endif
3290
3291 static irqreturn_t tegra_xhci_irq(struct usb_hcd *hcd)
3292 {
3293         struct tegra_xhci_hcd *tegra = hcd_to_tegra_xhci(hcd);
3294         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3295         irqreturn_t iret = IRQ_HANDLED;
3296         u32 status;
3297
3298         spin_lock(&tegra->lock);
3299         if (tegra->hc_in_elpg) {
3300                 spin_lock(&xhci->lock);
3301                 if (HCD_HW_ACCESSIBLE(hcd)) {
3302                         status = xhci_readl(xhci, &xhci->op_regs->status);
3303                         status |= STS_EINT;
3304                         xhci_writel(xhci, status, &xhci->op_regs->status);
3305                 }
3306                 xhci_dbg(xhci, "%s: schedule host_elpg_exit_work\n",
3307                                 __func__);
3308                 schedule_work(&tegra->host_elpg_exit_work);
3309                 spin_unlock(&xhci->lock);
3310         } else
3311                 iret = xhci_irq(hcd);
3312         spin_unlock(&tegra->lock);
3313
3314         wake_up_interruptible(&tegra->log.intr_wait);
3315
3316         return iret;
3317 }
3318
3319
3320 static const struct hc_driver tegra_plat_xhci_driver = {
3321         .description =          "tegra-xhci",
3322         .product_desc =         "Nvidia xHCI Host Controller",
3323         .hcd_priv_size =        sizeof(struct xhci_hcd *),
3324
3325         /*
3326          * generic hardware linkage
3327          */
3328         .irq =                  tegra_xhci_irq,
3329         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
3330
3331         /*
3332          * basic lifecycle operations
3333          */
3334         .reset =                xhci_plat_setup,
3335         .start =                xhci_run,
3336         .stop =                 xhci_stop,
3337         .shutdown =             xhci_shutdown,
3338
3339         /*
3340          * managing i/o requests and associated device resources
3341          */
3342         .urb_enqueue =          xhci_urb_enqueue,
3343         .urb_dequeue =          xhci_urb_dequeue,
3344         .alloc_dev =            xhci_alloc_dev,
3345         .free_dev =             xhci_free_dev,
3346         .alloc_streams =        xhci_alloc_streams,
3347         .free_streams =         xhci_free_streams,
3348         .add_endpoint =         xhci_add_endpoint,
3349         .drop_endpoint =        xhci_drop_endpoint,
3350         .endpoint_reset =       xhci_endpoint_reset,
3351         .check_bandwidth =      xhci_check_bandwidth,
3352         .reset_bandwidth =      xhci_reset_bandwidth,
3353         .address_device =       xhci_address_device,
3354         .update_hub_device =    xhci_update_hub_device,
3355         .reset_device =         xhci_discover_or_reset_device,
3356
3357         /*
3358          * scheduling support
3359          */
3360         .get_frame_number =     xhci_get_frame,
3361
3362         /* Root hub support */
3363         .hub_control =          xhci_hub_control,
3364         .hub_status_data =      xhci_hub_status_data,
3365
3366 #ifdef CONFIG_PM
3367         .bus_suspend =          tegra_xhci_bus_suspend,
3368         .bus_resume =           tegra_xhci_bus_resume,
3369 #endif
3370 };
3371
3372 #ifdef CONFIG_PM
3373 static int
3374 tegra_xhci_suspend(struct platform_device *pdev,
3375                                                 pm_message_t state)
3376 {
3377         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3378         struct xhci_hcd *xhci = tegra->xhci;
3379
3380         int ret = 0;
3381
3382         mutex_lock(&tegra->sync_lock);
3383         if (!tegra->hc_in_elpg) {
3384                 xhci_warn(xhci, "%s: lp0 suspend entry while elpg not done\n",
3385                                 __func__);
3386                 mutex_unlock(&tegra->sync_lock);
3387                 return -EBUSY;
3388         }
3389         mutex_unlock(&tegra->sync_lock);
3390
3391         tegra_xhci_ss_wake_on_interrupts(tegra->bdata->portmap, false);
3392         tegra_xhci_hs_wake_on_interrupts(tegra->bdata->portmap, false);
3393
3394         /* enable_irq_wake for ss ports */
3395         ret = enable_irq_wake(tegra->padctl_irq);
3396         if (ret < 0) {
3397                 xhci_err(xhci,
3398                 "%s: Couldn't enable USB host mode wakeup, irq=%d, error=%d\n",
3399                 __func__, tegra->padctl_irq, ret);
3400         }
3401
3402         /* enable_irq_wake for utmip/uhisc wakes */
3403         ret = enable_irq_wake(tegra->usb3_irq);
3404         if (ret < 0) {
3405                 xhci_err(xhci,
3406                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3407                 __func__, tegra->usb3_irq, ret);
3408         }
3409
3410         /* enable_irq_wake for utmip/uhisc wakes */
3411         ret = enable_irq_wake(tegra->usb2_irq);
3412         if (ret < 0) {
3413                 xhci_err(xhci,
3414                 "%s: Couldn't enable utmip/uhsic wakeup, irq=%d, error=%d\n",
3415                 __func__, tegra->usb2_irq, ret);
3416         }
3417
3418         regulator_disable(tegra->xusb_s1p8v_reg);
3419         regulator_disable(tegra->xusb_s1p05v_reg);
3420         tegra_usb2_clocks_deinit(tegra);
3421
3422         return ret;
3423 }
3424
3425 static int
3426 tegra_xhci_resume(struct platform_device *pdev)
3427 {
3428         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
3429
3430         dev_dbg(&pdev->dev, "%s\n", __func__);
3431
3432         tegra->last_jiffies = jiffies;
3433
3434         disable_irq_wake(tegra->padctl_irq);
3435         disable_irq_wake(tegra->usb3_irq);
3436         disable_irq_wake(tegra->usb2_irq);
3437         tegra->lp0_exit = true;
3438
3439         regulator_enable(tegra->xusb_s1p05v_reg);
3440         regulator_enable(tegra->xusb_s1p8v_reg);
3441         tegra_usb2_clocks_init(tegra);
3442
3443         return 0;
3444 }
3445 #endif
3446
3447
3448 static int init_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3449 {
3450         struct platform_device *pdev = tegra->pdev;
3451         void __iomem *fw_mmio_base;
3452         phys_addr_t fw_mem_phy_addr;
3453         size_t fw_size;
3454         dma_addr_t fw_dma;
3455 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3456         int ret;
3457 #endif
3458
3459         /* bootloader saved firmware memory address in PMC SCRATCH34 register */
3460         fw_mem_phy_addr = tegra_usb_pmc_reg_read(PMC_SCRATCH34);
3461
3462         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3463                         fw_mem_phy_addr, sizeof(struct cfgtbl));
3464
3465         if (!fw_mmio_base) {
3466                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3467                                         fw_mem_phy_addr);
3468                         return -ENOMEM;
3469         }
3470
3471         fw_size = ioread32(fw_mmio_base + FW_SIZE_OFFSET);
3472         devm_iounmap(&pdev->dev, fw_mmio_base);
3473
3474         fw_mmio_base = devm_ioremap_nocache(&pdev->dev,
3475                         fw_mem_phy_addr, fw_size);
3476         if (!fw_mmio_base) {
3477                         dev_err(&pdev->dev, "error mapping fw memory 0x%x\n",
3478                                         fw_mem_phy_addr);
3479                         return -ENOMEM;
3480         }
3481
3482         dev_info(&pdev->dev, "Firmware Memory: phy 0x%x mapped 0x%p (%d Bytes)\n",
3483                         fw_mem_phy_addr, fw_mmio_base, fw_size);
3484
3485 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3486         fw_dma = dma_map_linear(&pdev->dev, fw_mem_phy_addr, fw_size,
3487                         DMA_TO_DEVICE);
3488         if (fw_dma == DMA_ERROR_CODE) {
3489                 dev_err(&pdev->dev, "%s: dma_map_linear failed\n",
3490                                 __func__);
3491                 ret = -ENOMEM;
3492                 goto error_iounmap;
3493         }
3494 #else
3495         fw_dma = fw_mem_phy_addr;
3496 #endif
3497         dev_info(&pdev->dev, "Firmware DMA Memory: dma 0x%p (%d Bytes)\n",
3498                         (void *) fw_dma, fw_size);
3499
3500         /* all set and ready to go */
3501         tegra->firmware.data = fw_mmio_base;
3502         tegra->firmware.dma = fw_dma;
3503         tegra->firmware.size = fw_size;
3504
3505         return 0;
3506
3507 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3508 error_iounmap:
3509         devm_iounmap(&pdev->dev, fw_mmio_base);
3510         return ret;
3511 #endif
3512 }
3513
3514 static void deinit_bootloader_firmware(struct tegra_xhci_hcd *tegra)
3515 {
3516         struct platform_device *pdev = tegra->pdev;
3517         void __iomem *fw_mmio_base = tegra->firmware.data;
3518
3519 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
3520         dma_unmap_single(&pdev->dev, tegra->firmware.dma,
3521                         tegra->firmware.size, DMA_TO_DEVICE);
3522 #endif
3523         devm_iounmap(&pdev->dev, fw_mmio_base);
3524
3525         memset(&tegra->firmware, 0, sizeof(tegra->firmware));
3526 }
3527
3528 static int init_firmware(struct tegra_xhci_hcd *tegra)
3529 {
3530         return init_bootloader_firmware(tegra);
3531 }
3532
3533 static void deinit_firmware(struct tegra_xhci_hcd *tegra)
3534 {
3535         deinit_bootloader_firmware(tegra);
3536 }
3537
3538 static int tegra_enable_xusb_clk(struct tegra_xhci_hcd *tegra,
3539                 struct platform_device *pdev)
3540 {
3541         int err = 0;
3542         /* enable ss clock */
3543         err = clk_enable(tegra->host_clk);
3544         if (err) {
3545                 dev_err(&pdev->dev, "Failed to enable host partition clk\n");
3546                 goto enable_host_clk_failed;
3547         }
3548
3549         err = clk_enable(tegra->ss_clk);
3550         if (err) {
3551                 dev_err(&pdev->dev, "Failed to enable ss partition clk\n");
3552                 goto eanble_ss_clk_failed;
3553         }
3554
3555         err = clk_enable(tegra->emc_clk);
3556         if (err) {
3557                 dev_err(&pdev->dev, "Failed to enable xusb.emc clk\n");
3558                 goto eanble_emc_clk_failed;
3559         }
3560
3561         return 0;
3562
3563 eanble_emc_clk_failed:
3564         clk_disable(tegra->ss_clk);
3565
3566 eanble_ss_clk_failed:
3567         clk_disable(tegra->host_clk);
3568
3569 enable_host_clk_failed:
3570         if (tegra->pdata->quirks & TEGRA_XUSB_USE_HS_SRC_CLOCK2)
3571                 clk_disable(tegra->pll_re_vco_clk);
3572         return err;
3573 }
3574
3575 static struct tegra_xusb_padctl_regs t114_padregs_offset = {
3576         .boot_media_0                   = 0x0,
3577         .usb2_pad_mux_0                 = 0x4,
3578         .usb2_port_cap_0                = 0x8,
3579         .snps_oc_map_0                  = 0xc,
3580         .usb2_oc_map_0                  = 0x10,
3581         .ss_port_map_0                  = 0x14,
3582         .oc_det_0                       = 0x18,
3583         .elpg_program_0                 = 0x1c,
3584         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3585         .usb2_bchrg_otgpad0_ctl1_0      = 0xffff,
3586         .usb2_bchrg_otgpad1_ctl0_0      = 0x24,
3587         .usb2_bchrg_otgpad1_ctl1_0      = 0xffff,
3588         .usb2_bchrg_otgpad2_ctl0_0      = 0xffff,
3589         .usb2_bchrg_otgpad2_ctl1_0      = 0xffff,
3590         .usb2_bchrg_bias_pad_0          = 0x28,
3591         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x2c,
3592         .iophy_pll_p0_ctl1_0            = 0x30,
3593         .iophy_pll_p0_ctl2_0            = 0x34,
3594         .iophy_pll_p0_ctl3_0            = 0x38,
3595         .iophy_pll_p0_ctl4_0            = 0x3c,
3596         .iophy_usb3_pad0_ctl1_0         = 0x40,
3597         .iophy_usb3_pad1_ctl1_0         = 0x44,
3598         .iophy_usb3_pad0_ctl2_0         = 0x48,
3599         .iophy_usb3_pad1_ctl2_0         = 0x4c,
3600         .iophy_usb3_pad0_ctl3_0         = 0x50,
3601         .iophy_usb3_pad1_ctl3_0         = 0x54,
3602         .iophy_usb3_pad0_ctl4_0         = 0x58,
3603         .iophy_usb3_pad1_ctl4_0         = 0x5c,
3604         .iophy_misc_pad_p0_ctl1_0       = 0x60,
3605         .iophy_misc_pad_p1_ctl1_0       = 0x64,
3606         .iophy_misc_pad_p0_ctl2_0       = 0x68,
3607         .iophy_misc_pad_p1_ctl2_0       = 0x6c,
3608         .iophy_misc_pad_p0_ctl3_0       = 0x70,
3609         .iophy_misc_pad_p1_ctl3_0       = 0x74,
3610         .iophy_misc_pad_p0_ctl4_0       = 0x78,
3611         .iophy_misc_pad_p1_ctl4_0       = 0x7c,
3612         .iophy_misc_pad_p0_ctl5_0       = 0x80,
3613         .iophy_misc_pad_p1_ctl5_0       = 0x84,
3614         .iophy_misc_pad_p0_ctl6_0       = 0x88,
3615         .iophy_misc_pad_p1_ctl6_0       = 0x8c,
3616         .usb2_otg_pad0_ctl0_0           = 0x90,
3617         .usb2_otg_pad1_ctl0_0           = 0x94,
3618         .usb2_otg_pad2_ctl0_0           = 0xffff,
3619         .usb2_otg_pad0_ctl1_0           = 0x98,
3620         .usb2_otg_pad1_ctl1_0           = 0x9c,
3621         .usb2_otg_pad2_ctl1_0           = 0xffff,
3622         .usb2_bias_pad_ctl0_0           = 0xa0,
3623         .usb2_bias_pad_ctl1_0           = 0xa4,
3624         .usb2_hsic_pad0_ctl0_0          = 0xa8,
3625         .usb2_hsic_pad1_ctl0_0          = 0xac,
3626         .usb2_hsic_pad0_ctl1_0          = 0xb0,
3627         .usb2_hsic_pad1_ctl1_0          = 0xb4,
3628         .usb2_hsic_pad0_ctl2_0          = 0xb8,
3629         .usb2_hsic_pad1_ctl2_0          = 0xbc,
3630         .ulpi_link_trim_ctl0            = 0xc0,
3631         .ulpi_null_clk_trim_ctl0        = 0xc4,
3632         .hsic_strb_trim_ctl0            = 0xc8,
3633         .wake_ctl0                      = 0xcc,
3634         .pm_spare0                      = 0xd0,
3635         .iophy_misc_pad_p2_ctl1_0       = 0xffff,
3636         .iophy_misc_pad_p3_ctl1_0       = 0xffff,
3637         .iophy_misc_pad_p4_ctl1_0       = 0xffff,
3638         .iophy_misc_pad_p2_ctl2_0       = 0xffff,
3639         .iophy_misc_pad_p3_ctl2_0       = 0xffff,
3640         .iophy_misc_pad_p4_ctl2_0       = 0xffff,
3641         .iophy_misc_pad_p2_ctl3_0       = 0xffff,
3642         .iophy_misc_pad_p3_ctl3_0       = 0xffff,
3643         .iophy_misc_pad_p4_ctl3_0       = 0xffff,
3644         .iophy_misc_pad_p2_ctl4_0       = 0xffff,
3645         .iophy_misc_pad_p3_ctl4_0       = 0xffff,
3646         .iophy_misc_pad_p4_ctl4_0       = 0xffff,
3647         .iophy_misc_pad_p2_ctl5_0       = 0xffff,
3648         .iophy_misc_pad_p3_ctl5_0       = 0xffff,
3649         .iophy_misc_pad_p4_ctl5_0       = 0xffff,
3650         .iophy_misc_pad_p2_ctl6_0       = 0xffff,
3651         .iophy_misc_pad_p3_ctl6_0       = 0xffff,
3652         .iophy_misc_pad_p4_ctl6_0       = 0xffff,
3653         .usb3_pad_mux_0                 = 0xffff,
3654         .iophy_pll_s0_ctl1_0            = 0xffff,
3655         .iophy_pll_s0_ctl2_0            = 0xffff,
3656         .iophy_pll_s0_ctl3_0            = 0xffff,
3657         .iophy_pll_s0_ctl4_0            = 0xffff,
3658         .iophy_misc_pad_s0_ctl1_0       = 0xffff,
3659         .iophy_misc_pad_s0_ctl2_0       = 0xffff,
3660         .iophy_misc_pad_s0_ctl3_0       = 0xffff,
3661         .iophy_misc_pad_s0_ctl4_0       = 0xffff,
3662         .iophy_misc_pad_s0_ctl5_0       = 0xffff,
3663         .iophy_misc_pad_s0_ctl6_0       = 0xffff,
3664 };
3665
3666 static struct tegra_xusb_padctl_regs t124_padregs_offset = {
3667         .boot_media_0                   = 0x0,
3668         .usb2_pad_mux_0                 = 0x4,
3669         .usb2_port_cap_0                = 0x8,
3670         .snps_oc_map_0                  = 0xc,
3671         .usb2_oc_map_0                  = 0x10,
3672         .ss_port_map_0                  = 0x14,
3673         .oc_det_0                       = 0x18,
3674         .elpg_program_0                 = 0x1c,
3675         .usb2_bchrg_otgpad0_ctl0_0      = 0x20,
3676         .usb2_bchrg_otgpad0_ctl1_0      = 0x24,
3677         .usb2_bchrg_otgpad1_ctl0_0      = 0x28,
3678         .usb2_bchrg_otgpad1_ctl1_0      = 0x2c,
3679         .usb2_bchrg_otgpad2_ctl0_0      = 0x30,
3680         .usb2_bchrg_otgpad2_ctl1_0      = 0x34,
3681         .usb2_bchrg_bias_pad_0          = 0x38,
3682         .usb2_bchrg_tdcd_dbnc_timer_0   = 0x3c,
3683         .iophy_pll_p0_ctl1_0            = 0x40,
3684         .iophy_pll_p0_ctl2_0            = 0x44,
3685         .iophy_pll_p0_ctl3_0            = 0x48,
3686         .iophy_pll_p0_ctl4_0            = 0x4c,
3687         .iophy_usb3_pad0_ctl1_0         = 0x50,
3688         .iophy_usb3_pad1_ctl1_0         = 0x54,
3689         .iophy_usb3_pad0_ctl2_0         = 0x58,
3690         .iophy_usb3_pad1_ctl2_0         = 0x5c,
3691         .iophy_usb3_pad0_ctl3_0         = 0x60,
3692         .iophy_usb3_pad1_ctl3_0         = 0x64,
3693         .iophy_usb3_pad0_ctl4_0         = 0x68,
3694         .iophy_usb3_pad1_ctl4_0         = 0x6c,
3695         .iophy_misc_pad_p0_ctl1_0       = 0x70,
3696         .iophy_misc_pad_p1_ctl1_0       = 0x74,
3697         .iophy_misc_pad_p0_ctl2_0       = 0x78,
3698         .iophy_misc_pad_p1_ctl2_0       = 0x7c,
3699         .iophy_misc_pad_p0_ctl3_0       = 0x80,
3700         .iophy_misc_pad_p1_ctl3_0       = 0x84,
3701         .iophy_misc_pad_p0_ctl4_0       = 0x88,
3702         .iophy_misc_pad_p1_ctl4_0       = 0x8c,
3703         .iophy_misc_pad_p0_ctl5_0       = 0x90,
3704         .iophy_misc_pad_p1_ctl5_0       = 0x94,
3705         .iophy_misc_pad_p0_ctl6_0       = 0x98,
3706         .iophy_misc_pad_p1_ctl6_0       = 0x9c,
3707         .usb2_otg_pad0_ctl0_0           = 0xa0,
3708         .usb2_otg_pad1_ctl0_0           = 0xa4,
3709         .usb2_otg_pad2_ctl0_0           = 0xa8,
3710         .usb2_otg_pad0_ctl1_0           = 0xac,
3711         .usb2_otg_pad1_ctl1_0           = 0xb0,
3712         .usb2_otg_pad2_ctl1_0           = 0xb4,
3713         .usb2_bias_pad_ctl0_0           = 0xb8,
3714         .usb2_bias_pad_ctl1_0           = 0xbc,
3715         .usb2_hsic_pad0_ctl0_0          = 0xc0,
3716         .usb2_hsic_pad1_ctl0_0          = 0xc4,
3717         .usb2_hsic_pad0_ctl1_0          = 0xc8,
3718         .usb2_hsic_pad1_ctl1_0          = 0xcc,
3719         .usb2_hsic_pad0_ctl2_0          = 0xd0,
3720         .usb2_hsic_pad1_ctl2_0          = 0xd4,
3721         .ulpi_link_trim_ctl0            = 0xd8,
3722         .ulpi_null_clk_trim_ctl0        = 0xdc,
3723         .hsic_strb_trim_ctl0            = 0xe0,
3724         .wake_ctl0                      = 0xe4,
3725         .pm_spare0                      = 0xe8,
3726         .iophy_misc_pad_p2_ctl1_0       = 0xec,
3727         .iophy_misc_pad_p3_ctl1_0       = 0xf0,
3728         .iophy_misc_pad_p4_ctl1_0       = 0xf4,
3729         .iophy_misc_pad_p2_ctl2_0       = 0xf8,
3730         .iophy_misc_pad_p3_ctl2_0       = 0xfc,
3731         .iophy_misc_pad_p4_ctl2_0       = 0x100,
3732         .iophy_misc_pad_p2_ctl3_0       = 0x104,
3733         .iophy_misc_pad_p3_ctl3_0       = 0x108,
3734         .iophy_misc_pad_p4_ctl3_0       = 0x10c,
3735         .iophy_misc_pad_p2_ctl4_0       = 0x110,
3736         .iophy_misc_pad_p3_ctl4_0       = 0x114,
3737         .iophy_misc_pad_p4_ctl4_0       = 0x118,
3738         .iophy_misc_pad_p2_ctl5_0       = 0x11c,
3739         .iophy_misc_pad_p3_ctl5_0       = 0x120,
3740         .iophy_misc_pad_p4_ctl5_0       = 0x124,
3741         .iophy_misc_pad_p2_ctl6_0       = 0x128,
3742         .iophy_misc_pad_p3_ctl6_0       = 0x12c,
3743         .iophy_misc_pad_p4_ctl6_0       = 0x130,
3744         .usb3_pad_mux_0                 = 0x134,
3745         .iophy_pll_s0_ctl1_0            = 0x138,
3746         .iophy_pll_s0_ctl2_0            = 0x13c,
3747         .iophy_pll_s0_ctl3_0            = 0x140,
3748         .iophy_pll_s0_ctl4_0            = 0x144,
3749         .iophy_misc_pad_s0_ctl1_0       = 0x148,
3750         .iophy_misc_pad_s0_ctl2_0       = 0x14c,
3751         .iophy_misc_pad_s0_ctl3_0       = 0x150,
3752         .iophy_misc_pad_s0_ctl4_0       = 0x154,
3753         .iophy_misc_pad_s0_ctl5_0       = 0x158,
3754         .iophy_misc_pad_s0_ctl6_0       = 0x15c,
3755 };
3756
3757 /* TODO: we have to refine error handling in tegra_xhci_probe() */
3758 static int tegra_xhci_probe(struct platform_device *pdev)
3759 {
3760         const struct hc_driver *driver;
3761         struct xhci_hcd *xhci;
3762         struct tegra_xhci_hcd *tegra;
3763         struct resource *res;
3764         struct usb_hcd  *hcd;
3765         unsigned pad;
3766         u32 val;
3767         int ret;
3768         int irq;
3769
3770         BUILD_BUG_ON(sizeof(struct cfgtbl) != 256);
3771
3772         if (usb_disabled())
3773                 return -ENODEV;
3774
3775         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
3776         if (!tegra) {
3777                 dev_err(&pdev->dev, "memory alloc failed\n");
3778                 return -ENOMEM;
3779         }
3780         tegra->pdev = pdev;
3781         tegra->pdata = dev_get_platdata(&pdev->dev);
3782         tegra->bdata = tegra->pdata->bdata;
3783
3784         ret = tegra_xhci_request_mem_region(pdev, "padctl",
3785                         &tegra->padctl_base);
3786         if (ret) {
3787                 dev_err(&pdev->dev, "failed to map padctl\n");
3788                 return ret;
3789         }
3790
3791         ret = tegra_xhci_request_mem_region(pdev, "fpci", &tegra->fpci_base);
3792         if (ret) {
3793                 dev_err(&pdev->dev, "failed to map fpci\n");
3794                 return ret;
3795         }
3796
3797         ret = tegra_xhci_request_mem_region(pdev, "ipfs", &tegra->ipfs_base);
3798         if (ret) {
3799                 dev_err(&pdev->dev, "failed to map ipfs\n");
3800                 return ret;
3801         }
3802
3803         ret = tegra_xusb_partitions_clk_init(tegra);
3804         if (ret) {
3805                 dev_err(&pdev->dev,
3806                         "failed to initialize xusb partitions clocks\n");
3807                 return ret;
3808         }
3809
3810         /* Enable power rails to the PAD,VBUS
3811          * and pull-up voltage.Initialize the regulators
3812          */
3813         ret = tegra_xusb_regulator_init(tegra, pdev);
3814         if (ret) {
3815                 dev_err(&pdev->dev, "failed to initialize xusb regulator\n");
3816                 goto err_deinit_xusb_partition_clk;
3817         }
3818
3819         /* Enable UTMIP, PLLU and PLLE */
3820         ret = tegra_usb2_clocks_init(tegra);
3821         if (ret) {
3822                 dev_err(&pdev->dev, "error initializing usb2 clocks\n");
3823                 goto err_deinit_tegra_xusb_regulator;
3824         }
3825
3826         /* tegra_unpowergate_partition also does partition reset deassert */
3827         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBA);
3828         if (ret)
3829                 dev_err(&pdev->dev, "could not unpowergate xusba partition\n");
3830
3831         /* tegra_unpowergate_partition also does partition reset deassert */
3832         ret = tegra_unpowergate_partition(TEGRA_POWERGATE_XUSBC);
3833         if (ret)
3834                 dev_err(&pdev->dev, "could not unpowergate xusbc partition\n");
3835
3836         ret = tegra_enable_xusb_clk(tegra, pdev);
3837         if (ret)
3838                 dev_err(&pdev->dev, "could not enable partition clock\n");
3839
3840         /* reset the pointer back to NULL. driver uses it */
3841         /* platform_set_drvdata(pdev, NULL); */
3842
3843         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "host");
3844         if (!res) {
3845                 dev_err(&pdev->dev, "mem resource host doesn't exist\n");
3846                 ret = -ENODEV;
3847                 goto err_deinit_usb2_clocks;
3848         }
3849         tegra->host_phy_base = res->start;
3850
3851         tegra->host_phy_virt_base = devm_ioremap(&pdev->dev,
3852                                 res->start, resource_size(res));
3853         if (!tegra->host_phy_virt_base) {
3854                 dev_err(&pdev->dev, "error mapping host phy memory\n");
3855                 ret = -ENOMEM;
3856                 goto err_deinit_usb2_clocks;
3857         }
3858
3859         /* Setup IPFS access and BAR0 space */
3860         tegra_xhci_cfg(tegra);
3861
3862         val = readl(tegra->fpci_base + XUSB_CFG_0);
3863         tegra->device_id = (val >> 16) & 0xffff;
3864
3865         dev_info(&pdev->dev, "XUSB device id = 0x%x (%s)\n", tegra->device_id,
3866                 (XUSB_DEVICE_ID_T114 == tegra->device_id) ? "T114" : "T124+");
3867
3868         if (XUSB_DEVICE_ID_T114 == tegra->device_id) {
3869                 tegra->padregs = &t114_padregs_offset;
3870         } else if (XUSB_DEVICE_ID_T124 == tegra->device_id) {
3871                 tegra->padregs = &t124_padregs_offset;
3872         } else {
3873                 dev_info(&pdev->dev, "XUSB device_id neither T114 nor T124!\n");
3874                 dev_info(&pdev->dev, "XUSB using T124 pad register offsets!\n");
3875                 tegra->padregs = &t124_padregs_offset;
3876         }
3877
3878         /* calculate rctrl_val and tctrl_val once at boot time */
3879         /* Issue is only applicable for T114 */
3880         if (XUSB_DEVICE_ID_T114 == tegra->device_id)
3881                 tegra_xhci_war_for_tctrl_rctrl(tegra);
3882
3883         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
3884                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap)
3885                         hsic_power_rail_enable(tegra);
3886         }
3887
3888         /* Program the XUSB pads to take ownership of ports */
3889         tegra_xhci_padctl_portmap_and_caps(tegra);
3890
3891         /* Release XUSB wake logic state latching */
3892         tegra_xhci_ss_wake_signal(tegra->bdata->portmap, false);
3893         tegra_xhci_ss_vcore(tegra->bdata->portmap, false);
3894
3895         /* Deassert reset to XUSB host, ss, dev clocks */
3896         tegra_periph_reset_deassert(tegra->host_clk);
3897         tegra_periph_reset_deassert(tegra->ss_clk);
3898
3899         fw_log_init(tegra);
3900         ret = init_firmware(tegra);
3901         if (ret < 0) {
3902                 dev_err(&pdev->dev, "failed to init firmware\n");
3903                 ret = -ENODEV;
3904                 goto err_deinit_usb2_clocks;
3905         }
3906
3907         ret = load_firmware(tegra, true /* do reset ARU */);
3908         if (ret < 0) {
3909                 dev_err(&pdev->dev, "failed to load firmware\n");
3910                 ret = -ENODEV;
3911                 goto err_deinit_firmware;
3912         }
3913
3914         spin_lock_init(&tegra->lock);
3915         mutex_init(&tegra->sync_lock);
3916         mutex_init(&tegra->mbox_lock);
3917         pmc_init(tegra);
3918
3919         device_init_wakeup(&pdev->dev, 1);
3920         driver = &tegra_plat_xhci_driver;
3921
3922         hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
3923         if (!hcd) {
3924                 dev_err(&pdev->dev, "failed to create usb2 hcd\n");
3925                 ret = -ENOMEM;
3926                 goto err_deinit_firmware;
3927         }
3928
3929         ret = tegra_xhci_request_mem_region(pdev, "host", &hcd->regs);
3930         if (ret) {
3931                 dev_err(&pdev->dev, "failed to map host\n");
3932                 goto err_put_usb2_hcd;
3933         }
3934         hcd->rsrc_start = res->start;
3935         hcd->rsrc_len = resource_size(res);
3936
3937         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "host");
3938         if (!res) {
3939                 dev_err(&pdev->dev, "irq resource host doesn't exist\n");
3940                 ret = -ENODEV;
3941                 goto err_put_usb2_hcd;
3942         }
3943         irq = res->start;
3944         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
3945         if (ret) {
3946                 dev_err(&pdev->dev, "failed to add usb2hcd, error = %d\n", ret);
3947                 goto err_put_usb2_hcd;
3948         }
3949
3950         /* USB 2.0 roothub is stored in the platform_device now. */
3951         hcd = dev_get_drvdata(&pdev->dev);
3952         xhci = hcd_to_xhci(hcd);
3953         tegra->xhci = xhci;
3954         platform_set_drvdata(pdev, tegra);
3955
3956         xhci->shared_hcd = usb_create_shared_hcd(driver, &pdev->dev,
3957                                                 dev_name(&pdev->dev), hcd);
3958         if (!xhci->shared_hcd) {
3959                 dev_err(&pdev->dev, "failed to create usb3 hcd\n");
3960                 ret = -ENOMEM;
3961                 goto err_remove_usb2_hcd;
3962         }
3963
3964         /*
3965          * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
3966          * is called by usb_add_hcd().
3967          */
3968         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
3969
3970         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
3971         if (ret) {
3972                 dev_err(&pdev->dev, "failed to add usb3hcd, error = %d\n", ret);
3973                 goto err_put_usb3_hcd;
3974         }
3975
3976         device_init_wakeup(&hcd->self.root_hub->dev, 1);
3977         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, 1);
3978
3979         /* do mailbox related initializations */
3980         tegra->mbox_owner = 0xffff;
3981         INIT_WORK(&tegra->mbox_work, tegra_xhci_process_mbox_message);
3982
3983         tegra_xhci_enable_fw_message(tegra);
3984
3985         /* do ss partition elpg exit related initialization */
3986         INIT_WORK(&tegra->ss_elpg_exit_work, ss_partition_elpg_exit_work);
3987
3988         /* do host partition elpg exit related initialization */
3989         INIT_WORK(&tegra->host_elpg_exit_work, host_partition_elpg_exit_work);
3990
3991         /* Register interrupt handler for SMI line to handle mailbox
3992          * interrupt from firmware
3993          */
3994         ret = tegra_xhci_request_irq(pdev, "host-smi", tegra_xhci_smi_irq,
3995                         IRQF_SHARED, "tegra_xhci_mbox_irq", &tegra->smi_irq);
3996         if (ret != 0)
3997                 goto err_remove_usb3_hcd;
3998
3999         /* Register interrupt handler for PADCTRL line to
4000          * handle wake on connect irqs interrupt from
4001          * firmware
4002          */
4003         ret = tegra_xhci_request_irq(pdev, "padctl", tegra_xhci_padctl_irq,
4004                         IRQF_SHARED | IRQF_TRIGGER_HIGH,
4005                         "tegra_xhci_padctl_irq", &tegra->padctl_irq);
4006         if (ret != 0)
4007                 goto err_remove_usb3_hcd;
4008
4009         ret = tegra_xhci_request_irq(pdev, "usb2", pmc_usb_phy_wake_isr,
4010                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4011                 &tegra->usb2_irq);
4012         if (ret != 0)
4013                 goto err_remove_usb3_hcd;
4014
4015         ret = tegra_xhci_request_irq(pdev, "usb3", pmc_usb_phy_wake_isr,
4016                 IRQF_SHARED | IRQF_TRIGGER_HIGH, "pmc_usb_phy_wake_isr",
4017                 &tegra->usb3_irq);
4018         if (ret != 0)
4019                 goto err_remove_usb3_hcd;
4020
4021         tegra->ss_pwr_gated = false;
4022         tegra->host_pwr_gated = false;
4023         tegra->hc_in_elpg = false;
4024         tegra->hs_wake_event = false;
4025         tegra->host_resume_req = false;
4026         tegra->lp0_exit = false;
4027         tegra->dfe_ctle_ctx_saved = false;
4028
4029         tegra_xhci_debug_read_pads(tegra);
4030         utmi_phy_pad_enable();
4031         utmi_phy_iddq_override(false);
4032
4033         tegra_pd_add_device(&pdev->dev);
4034
4035         return 0;
4036
4037 err_remove_usb3_hcd:
4038         usb_remove_hcd(xhci->shared_hcd);
4039 err_put_usb3_hcd:
4040         usb_put_hcd(xhci->shared_hcd);
4041 err_remove_usb2_hcd:
4042         kfree(tegra->xhci);
4043         usb_remove_hcd(hcd);
4044 err_put_usb2_hcd:
4045         usb_put_hcd(hcd);
4046 err_deinit_firmware:
4047         deinit_firmware(tegra);
4048 err_deinit_usb2_clocks:
4049         tegra_usb2_clocks_deinit(tegra);
4050 err_deinit_tegra_xusb_regulator:
4051         tegra_xusb_regulator_deinit(tegra);
4052 err_deinit_xusb_partition_clk:
4053         tegra_xusb_partitions_clk_deinit(tegra);
4054
4055         return ret;
4056 }
4057
4058 static int tegra_xhci_remove(struct platform_device *pdev)
4059 {
4060         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4061         struct xhci_hcd *xhci = NULL;
4062         struct usb_hcd *hcd = NULL;
4063         unsigned pad;
4064
4065         if (tegra == NULL)
4066                 return -EINVAL;
4067
4068         xhci = tegra->xhci;
4069         hcd = xhci_to_hcd(xhci);
4070
4071         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
4072                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap)
4073                         hsic_pad_disable(tegra, pad);
4074         }
4075
4076         for (pad = 0; pad < XUSB_HSIC_COUNT; pad++) {
4077                 if (BIT(XUSB_HSIC_INDEX + pad) & tegra->bdata->portmap)
4078                         hsic_power_rail_disable(tegra);
4079         }
4080
4081         devm_free_irq(&pdev->dev, tegra->usb3_irq, tegra);
4082         devm_free_irq(&pdev->dev, tegra->padctl_irq, tegra);
4083         devm_free_irq(&pdev->dev, tegra->smi_irq, tegra);
4084         usb_remove_hcd(xhci->shared_hcd);
4085         usb_put_hcd(xhci->shared_hcd);
4086         usb_remove_hcd(hcd);
4087         usb_put_hcd(hcd);
4088         kfree(xhci);
4089
4090         deinit_firmware(tegra);
4091         fw_log_deinit(tegra);
4092         tegra_xusb_regulator_deinit(tegra);
4093         tegra_usb2_clocks_deinit(tegra);
4094         if (!tegra->hc_in_elpg)
4095                 tegra_xusb_partitions_clk_deinit(tegra);
4096         utmi_phy_pad_disable();
4097         utmi_phy_iddq_override(true);
4098
4099         tegra_pd_remove_device(&pdev->dev);
4100         return 0;
4101 }
4102
4103 static void tegra_xhci_shutdown(struct platform_device *pdev)
4104 {
4105         struct tegra_xhci_hcd *tegra = platform_get_drvdata(pdev);
4106         struct xhci_hcd *xhci = NULL;
4107         struct usb_hcd *hcd = NULL;
4108
4109         if (tegra == NULL)
4110                 return;
4111
4112         if (tegra->hc_in_elpg) {
4113                 mutex_lock(&tegra->sync_lock);
4114                 pmc_setup(tegra, 0);
4115                 mutex_unlock(&tegra->sync_lock);
4116         } else {
4117                 xhci = tegra->xhci;
4118                 hcd = xhci_to_hcd(xhci);
4119                 xhci_shutdown(hcd);
4120         }
4121 }
4122
4123 static struct platform_driver tegra_xhci_driver = {
4124         .probe  = tegra_xhci_probe,
4125         .remove = tegra_xhci_remove,
4126         .shutdown = tegra_xhci_shutdown,
4127 #ifdef CONFIG_PM
4128         .suspend = tegra_xhci_suspend,
4129         .resume  = tegra_xhci_resume,
4130 #endif
4131         .driver = {
4132                 .name = "tegra-xhci",
4133         },
4134 };
4135 MODULE_ALIAS("platform:tegra-xhci");
4136
4137 int tegra_xhci_register_plat(void)
4138 {
4139         return platform_driver_register(&tegra_xhci_driver);
4140 }
4141
4142 void tegra_xhci_unregister_plat(void)
4143 {
4144         platform_driver_unregister(&tegra_xhci_driver);
4145 }