Merge linux-3.10.67 into dev-kernel-3.10
[linux-3.10.git] / drivers / usb / host / xhci-ring.c
1 /*
2  * xHCI host controller driver
3  *
4  * Copyright (C) 2008 Intel Corp.
5  *
6  * Author: Sarah Sharp
7  * Some code borrowed from the Linux EHCI driver.
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but
14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
16  * for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software Foundation,
20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  */
22
23 /*
24  * Ring initialization rules:
25  * 1. Each segment is initialized to zero, except for link TRBs.
26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
27  *    Consumer Cycle State (CCS), depending on ring function.
28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
29  *
30  * Ring behavior rules:
31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
32  *    least one free TRB in the ring.  This is useful if you want to turn that
33  *    into a link TRB and expand the ring.
34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35  *    link TRB, then load the pointer with the address in the link TRB.  If the
36  *    link TRB had its toggle bit set, you may need to update the ring cycle
37  *    state (see cycle bit rules).  You may have to do this multiple times
38  *    until you reach a non-link TRB.
39  * 3. A ring is full if enqueue++ (for the definition of increment above)
40  *    equals the dequeue pointer.
41  *
42  * Cycle bit rules:
43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44  *    in a link TRB, it must toggle the ring cycle state.
45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46  *    in a link TRB, it must toggle the ring cycle state.
47  *
48  * Producer rules:
49  * 1. Check if ring is full before you enqueue.
50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51  *    Update enqueue pointer between each write (which may update the ring
52  *    cycle state).
53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
54  *    and endpoint rings.  If HC is the producer for the event ring,
55  *    and it generates an interrupt according to interrupt modulation rules.
56  *
57  * Consumer rules:
58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
59  *    the TRB is owned by the consumer.
60  * 2. Update dequeue pointer (which may update the ring cycle state) and
61  *    continue processing TRBs until you reach a TRB which is not owned by you.
62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
64  *   endpoint rings; it generates events on the event ring for these.
65  */
66
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
69 #include "xhci.h"
70
71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
72                 struct xhci_virt_device *virt_dev,
73                 struct xhci_event_cmd *event);
74
75 /*
76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
77  * address of the TRB.
78  */
79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
80                 union xhci_trb *trb)
81 {
82         unsigned long segment_offset;
83
84         if (!seg || !trb || trb < seg->trbs)
85                 return 0;
86         /* offset in TRBs */
87         segment_offset = trb - seg->trbs;
88         if (segment_offset > TRBS_PER_SEGMENT)
89                 return 0;
90         return seg->dma + (segment_offset * sizeof(*trb));
91 }
92
93 /* Does this link TRB point to the first segment in a ring,
94  * or was the previous TRB the last TRB on the last segment in the ERST?
95  */
96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
97                 struct xhci_segment *seg, union xhci_trb *trb)
98 {
99         if (ring == xhci->event_ring)
100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
101                         (seg->next == xhci->event_ring->first_seg);
102         else
103                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
104 }
105
106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107  * segment?  I.e. would the updated event TRB pointer step off the end of the
108  * event seg?
109  */
110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
111                 struct xhci_segment *seg, union xhci_trb *trb)
112 {
113         if (ring == xhci->event_ring)
114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
115         else
116                 return TRB_TYPE_LINK_LE32(trb->link.control);
117 }
118
119 static int enqueue_is_link_trb(struct xhci_ring *ring)
120 {
121         struct xhci_link_trb *link = &ring->enqueue->link;
122         return TRB_TYPE_LINK_LE32(link->control);
123 }
124
125 union xhci_trb *xhci_find_next_enqueue(struct xhci_ring *ring)
126 {
127         /* Enqueue pointer can be left pointing to the link TRB,
128          * we must handle that
129          */
130         if (TRB_TYPE_LINK_LE32(ring->enqueue->link.control))
131                 return ring->enq_seg->next->trbs;
132         return ring->enqueue;
133 }
134
135 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
136  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
137  * effect the ring dequeue or enqueue pointers.
138  */
139 static void next_trb(struct xhci_hcd *xhci,
140                 struct xhci_ring *ring,
141                 struct xhci_segment **seg,
142                 union xhci_trb **trb)
143 {
144         if (last_trb(xhci, ring, *seg, *trb)) {
145                 *seg = (*seg)->next;
146                 *trb = ((*seg)->trbs);
147         } else {
148                 (*trb)++;
149         }
150 }
151
152 /*
153  * See Cycle bit rules. SW is the consumer for the event ring only.
154  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
155  */
156 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
157 {
158         unsigned long long addr;
159
160         ring->deq_updates++;
161
162         /*
163          * If this is not event ring, and the dequeue pointer
164          * is not on a link TRB, there is one more usable TRB
165          */
166         if (ring->type != TYPE_EVENT &&
167                         !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
168                 ring->num_trbs_free++;
169
170         do {
171                 /*
172                  * Update the dequeue pointer further if that was a link TRB or
173                  * we're at the end of an event ring segment (which doesn't have
174                  * link TRBS)
175                  */
176                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
177                         if (ring->type == TYPE_EVENT &&
178                                         last_trb_on_last_seg(xhci, ring,
179                                                 ring->deq_seg, ring->dequeue)) {
180                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
181                         }
182                         ring->deq_seg = ring->deq_seg->next;
183                         ring->dequeue = ring->deq_seg->trbs;
184                 } else {
185                         ring->dequeue++;
186                 }
187         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
188
189         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
190 }
191
192 /*
193  * See Cycle bit rules. SW is the consumer for the event ring only.
194  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
195  *
196  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
197  * chain bit is set), then set the chain bit in all the following link TRBs.
198  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
199  * have their chain bit cleared (so that each Link TRB is a separate TD).
200  *
201  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
202  * set, but other sections talk about dealing with the chain bit set.  This was
203  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
204  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
205  *
206  * @more_trbs_coming:   Will you enqueue more TRBs before calling
207  *                      prepare_transfer()?
208  */
209 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
210                         bool more_trbs_coming)
211 {
212         u32 chain;
213         union xhci_trb *next;
214         unsigned long long addr;
215
216         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
217         /* If this is not event ring, there is one less usable TRB */
218         if (ring->type != TYPE_EVENT &&
219                         !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
220                 ring->num_trbs_free--;
221         next = ++(ring->enqueue);
222
223         ring->enq_updates++;
224         /* Update the dequeue pointer further if that was a link TRB or we're at
225          * the end of an event ring segment (which doesn't have link TRBS)
226          */
227         while (last_trb(xhci, ring, ring->enq_seg, next)) {
228                 if (ring->type != TYPE_EVENT) {
229                         /*
230                          * If the caller doesn't plan on enqueueing more
231                          * TDs before ringing the doorbell, then we
232                          * don't want to give the link TRB to the
233                          * hardware just yet.  We'll give the link TRB
234                          * back in prepare_ring() just before we enqueue
235                          * the TD at the top of the ring.
236                          */
237                         if (!chain && !more_trbs_coming)
238                                 break;
239
240                         /* If we're not dealing with 0.95 hardware or
241                          * isoc rings on AMD 0.96 host,
242                          * carry over the chain bit of the previous TRB
243                          * (which may mean the chain bit is cleared).
244                          */
245                         if (!(ring->type == TYPE_ISOC &&
246                                         (xhci->quirks & XHCI_AMD_0x96_HOST))
247                                                 && !xhci_link_trb_quirk(xhci)) {
248                                 next->link.control &=
249                                         cpu_to_le32(~TRB_CHAIN);
250                                 next->link.control |=
251                                         cpu_to_le32(chain);
252                         }
253                         /* Give this link TRB to the hardware */
254                         wmb();
255                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
256
257                         /* Toggle the cycle bit after the last ring segment. */
258                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
259                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
260                         }
261                 }
262                 ring->enq_seg = ring->enq_seg->next;
263                 ring->enqueue = ring->enq_seg->trbs;
264                 next = ring->enqueue;
265         }
266         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
267 }
268
269 /*
270  * Check to see if there's room to enqueue num_trbs on the ring and make sure
271  * enqueue pointer will not advance into dequeue segment. See rules above.
272  */
273 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
274                 unsigned int num_trbs)
275 {
276         int num_trbs_in_deq_seg;
277
278         if (ring->num_trbs_free < num_trbs)
279                 return 0;
280
281         if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
282                 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
283                 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
284                         return 0;
285         }
286
287         return 1;
288 }
289
290 /* Ring the host controller doorbell after placing a command on the ring */
291 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
292 {
293         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
294                 return;
295
296         xhci_dbg(xhci, "// Ding dong!\n");
297         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
298         /* Flush PCI posted writes */
299         xhci_readl(xhci, &xhci->dba->doorbell[0]);
300 }
301
302 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
303 {
304         u64 temp_64;
305         int ret;
306
307         xhci_dbg(xhci, "Abort command ring\n");
308
309         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
310                 xhci_dbg(xhci, "The command ring isn't running, "
311                                 "Have the command ring been stopped?\n");
312                 return 0;
313         }
314
315         temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
316         if (!(temp_64 & CMD_RING_RUNNING)) {
317                 xhci_dbg(xhci, "Command ring had been stopped\n");
318                 return 0;
319         }
320         xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
321         xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
322                         &xhci->op_regs->cmd_ring);
323
324         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
325          * time the completion od all xHCI commands, including
326          * the Command Abort operation. If software doesn't see
327          * CRR negated in a timely manner (e.g. longer than 5
328          * seconds), then it should assume that the there are
329          * larger problems with the xHC and assert HCRST.
330          */
331         ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
332                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
333         if (ret < 0) {
334                 xhci_err(xhci, "Stopped the command ring failed, "
335                                 "maybe the host is dead\n");
336                 xhci->xhc_state |= XHCI_STATE_DYING;
337                 xhci_quiesce(xhci);
338                 xhci_halt(xhci);
339                 return -ESHUTDOWN;
340         }
341
342         return 0;
343 }
344
345 static int xhci_queue_cd(struct xhci_hcd *xhci,
346                 struct xhci_command *command,
347                 union xhci_trb *cmd_trb)
348 {
349         struct xhci_cd *cd;
350         cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
351         if (!cd)
352                 return -ENOMEM;
353         INIT_LIST_HEAD(&cd->cancel_cmd_list);
354
355         cd->command = command;
356         cd->cmd_trb = cmd_trb;
357         list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
358
359         return 0;
360 }
361
362 /*
363  * Cancel the command which has issue.
364  *
365  * Some commands may hang due to waiting for acknowledgement from
366  * usb device. It is outside of the xHC's ability to control and
367  * will cause the command ring is blocked. When it occurs software
368  * should intervene to recover the command ring.
369  * See Section 4.6.1.1 and 4.6.1.2
370  */
371 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
372                 union xhci_trb *cmd_trb)
373 {
374         int retval = 0;
375         unsigned long flags;
376
377         spin_lock_irqsave(&xhci->lock, flags);
378
379         if (xhci->xhc_state & XHCI_STATE_DYING) {
380                 xhci_warn(xhci, "Abort the command ring,"
381                                 " but the xHCI is dead.\n");
382                 retval = -ESHUTDOWN;
383                 goto fail;
384         }
385
386         /* queue the cmd desriptor to cancel_cmd_list */
387         retval = xhci_queue_cd(xhci, command, cmd_trb);
388         if (retval) {
389                 xhci_warn(xhci, "Queuing command descriptor failed.\n");
390                 goto fail;
391         }
392
393         /* abort command ring */
394         retval = xhci_abort_cmd_ring(xhci);
395         if (retval) {
396                 xhci_err(xhci, "Abort command ring failed\n");
397                 if (unlikely(retval == -ESHUTDOWN)) {
398                         spin_unlock_irqrestore(&xhci->lock, flags);
399                         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
400                         xhci_dbg(xhci, "xHCI host controller is dead.\n");
401                         return retval;
402                 }
403         }
404
405 fail:
406         spin_unlock_irqrestore(&xhci->lock, flags);
407         return retval;
408 }
409
410 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
411                 unsigned int slot_id,
412                 unsigned int ep_index,
413                 unsigned int stream_id)
414 {
415         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
416         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
417         unsigned int ep_state = ep->ep_state;
418
419         /* Don't ring the doorbell for this endpoint if there are pending
420          * cancellations because we don't want to interrupt processing.
421          * We don't want to restart any stream rings if there's a set dequeue
422          * pointer command pending because the device can choose to start any
423          * stream once the endpoint is on the HW schedule.
424          * FIXME - check all the stream rings for pending cancellations.
425          */
426         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
427             (ep_state & EP_HALTED))
428                 return;
429         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
430         /* The CPU has better things to do at this point than wait for a
431          * write-posting flush.  It'll get there soon enough.
432          */
433 }
434
435 /* Ring the doorbell for any rings with pending URBs */
436 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
437                 unsigned int slot_id,
438                 unsigned int ep_index)
439 {
440         unsigned int stream_id;
441         struct xhci_virt_ep *ep;
442
443         ep = &xhci->devs[slot_id]->eps[ep_index];
444
445         /* A ring has pending URBs if its TD list is not empty */
446         if (!(ep->ep_state & EP_HAS_STREAMS)) {
447                 if (ep->ring && !(list_empty(&ep->ring->td_list)))
448                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
449                 return;
450         }
451
452         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
453                         stream_id++) {
454                 struct xhci_stream_info *stream_info = ep->stream_info;
455                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
456                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
457                                                 stream_id);
458         }
459 }
460
461 /*
462  * Find the segment that trb is in.  Start searching in start_seg.
463  * If we must move past a segment that has a link TRB with a toggle cycle state
464  * bit set, then we will toggle the value pointed at by cycle_state.
465  */
466 static struct xhci_segment *find_trb_seg(
467                 struct xhci_segment *start_seg,
468                 union xhci_trb  *trb, int *cycle_state)
469 {
470         struct xhci_segment *cur_seg = start_seg;
471         struct xhci_generic_trb *generic_trb;
472
473         while (cur_seg->trbs > trb ||
474                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
475                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
476                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
477                         *cycle_state ^= 0x1;
478                 cur_seg = cur_seg->next;
479                 if (cur_seg == start_seg)
480                         /* Looped over the entire list.  Oops! */
481                         return NULL;
482         }
483         return cur_seg;
484 }
485
486
487 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
488                 unsigned int slot_id, unsigned int ep_index,
489                 unsigned int stream_id)
490 {
491         struct xhci_virt_ep *ep;
492
493         ep = &xhci->devs[slot_id]->eps[ep_index];
494         /* Common case: no streams */
495         if (!(ep->ep_state & EP_HAS_STREAMS))
496                 return ep->ring;
497
498         if (stream_id == 0) {
499                 xhci_warn(xhci,
500                                 "WARN: Slot ID %u, ep index %u has streams, "
501                                 "but URB has no stream ID.\n",
502                                 slot_id, ep_index);
503                 return NULL;
504         }
505
506         if (stream_id < ep->stream_info->num_streams)
507                 return ep->stream_info->stream_rings[stream_id];
508
509         xhci_warn(xhci,
510                         "WARN: Slot ID %u, ep index %u has "
511                         "stream IDs 1 to %u allocated, "
512                         "but stream ID %u is requested.\n",
513                         slot_id, ep_index,
514                         ep->stream_info->num_streams - 1,
515                         stream_id);
516         return NULL;
517 }
518
519 /* Get the right ring for the given URB.
520  * If the endpoint supports streams, boundary check the URB's stream ID.
521  * If the endpoint doesn't support streams, return the singular endpoint ring.
522  */
523 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
524                 struct urb *urb)
525 {
526         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
527                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
528 }
529
530 /*
531  * Move the xHC's endpoint ring dequeue pointer past cur_td.
532  * Record the new state of the xHC's endpoint ring dequeue segment,
533  * dequeue pointer, and new consumer cycle state in state.
534  * Update our internal representation of the ring's dequeue pointer.
535  *
536  * We do this in three jumps:
537  *  - First we update our new ring state to be the same as when the xHC stopped.
538  *  - Then we traverse the ring to find the segment that contains
539  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
540  *    any link TRBs with the toggle cycle bit set.
541  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
542  *    if we've moved it past a link TRB with the toggle cycle bit set.
543  *
544  * Some of the uses of xhci_generic_trb are grotty, but if they're done
545  * with correct __le32 accesses they should work fine.  Only users of this are
546  * in here.
547  */
548 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
549                 unsigned int slot_id, unsigned int ep_index,
550                 unsigned int stream_id, struct xhci_td *cur_td,
551                 struct xhci_dequeue_state *state)
552 {
553         struct xhci_virt_device *dev = xhci->devs[slot_id];
554         struct xhci_ring *ep_ring;
555         struct xhci_generic_trb *trb;
556         struct xhci_ep_ctx *ep_ctx;
557         dma_addr_t addr;
558
559         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
560                         ep_index, stream_id);
561         if (!ep_ring) {
562                 xhci_warn(xhci, "WARN can't find new dequeue state "
563                                 "for invalid stream ID %u.\n",
564                                 stream_id);
565                 return;
566         }
567         state->new_cycle_state = 0;
568         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
569         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
570                         dev->eps[ep_index].stopped_trb,
571                         &state->new_cycle_state);
572         if (!state->new_deq_seg) {
573                 WARN_ON(1);
574                 return;
575         }
576
577         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
578         xhci_dbg(xhci, "Finding endpoint context\n");
579         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
580         state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
581
582         state->new_deq_ptr = cur_td->last_trb;
583         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
584         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
585                         state->new_deq_ptr,
586                         &state->new_cycle_state);
587         if (!state->new_deq_seg) {
588                 WARN_ON(1);
589                 return;
590         }
591
592         trb = &state->new_deq_ptr->generic;
593         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
594             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
595                 state->new_cycle_state ^= 0x1;
596         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
597
598         /*
599          * If there is only one segment in a ring, find_trb_seg()'s while loop
600          * will not run, and it will return before it has a chance to see if it
601          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
602          * ended just before the link TRB on a one-segment ring, or if the TD
603          * wrapped around the top of the ring, because it doesn't have the TD in
604          * question.  Look for the one-segment case where stalled TRB's address
605          * is greater than the new dequeue pointer address.
606          */
607         if (ep_ring->first_seg == ep_ring->first_seg->next &&
608                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
609                 state->new_cycle_state ^= 0x1;
610         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
611
612         /* Don't update the ring cycle state for the producer (us). */
613         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
614                         state->new_deq_seg);
615         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
616         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
617                         (unsigned long long) addr);
618 }
619
620 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
621  * (The last TRB actually points to the ring enqueue pointer, which is not part
622  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
623  */
624 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
625                 struct xhci_td *cur_td, bool flip_cycle)
626 {
627         struct xhci_segment *cur_seg;
628         union xhci_trb *cur_trb;
629
630         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
631                         true;
632                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
633                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
634                         /* Unchain any chained Link TRBs, but
635                          * leave the pointers intact.
636                          */
637                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
638                         /* Flip the cycle bit (link TRBs can't be the first
639                          * or last TRB).
640                          */
641                         if (flip_cycle)
642                                 cur_trb->generic.field[3] ^=
643                                         cpu_to_le32(TRB_CYCLE);
644                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
645                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
646                                         "in seg %p (0x%llx dma)\n",
647                                         cur_trb,
648                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
649                                         cur_seg,
650                                         (unsigned long long)cur_seg->dma);
651                 } else {
652                         cur_trb->generic.field[0] = 0;
653                         cur_trb->generic.field[1] = 0;
654                         cur_trb->generic.field[2] = 0;
655                         /* Preserve only the cycle bit of this TRB */
656                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
657                         /* Flip the cycle bit except on the first or last TRB */
658                         if (flip_cycle && cur_trb != cur_td->first_trb &&
659                                         cur_trb != cur_td->last_trb)
660                                 cur_trb->generic.field[3] ^=
661                                         cpu_to_le32(TRB_CYCLE);
662                         cur_trb->generic.field[3] |= cpu_to_le32(
663                                 TRB_TYPE(TRB_TR_NOOP));
664                         xhci_dbg(xhci, "TRB to noop at offset 0x%llx\n",
665                                         (unsigned long long)
666                                         xhci_trb_virt_to_dma(cur_seg, cur_trb));
667                 }
668                 if (cur_trb == cur_td->last_trb)
669                         break;
670         }
671 }
672
673 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
674                 unsigned int ep_index, unsigned int stream_id,
675                 struct xhci_segment *deq_seg,
676                 union xhci_trb *deq_ptr, u32 cycle_state);
677
678 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
679                 unsigned int slot_id, unsigned int ep_index,
680                 unsigned int stream_id,
681                 struct xhci_dequeue_state *deq_state)
682 {
683         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
684
685         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
686                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
687                         deq_state->new_deq_seg,
688                         (unsigned long long)deq_state->new_deq_seg->dma,
689                         deq_state->new_deq_ptr,
690                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
691                         deq_state->new_cycle_state);
692         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
693                         deq_state->new_deq_seg,
694                         deq_state->new_deq_ptr,
695                         (u32) deq_state->new_cycle_state);
696         /* Stop the TD queueing code from ringing the doorbell until
697          * this command completes.  The HC won't set the dequeue pointer
698          * if the ring is running, and ringing the doorbell starts the
699          * ring running.
700          */
701         ep->ep_state |= SET_DEQ_PENDING;
702 }
703
704 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
705                 struct xhci_virt_ep *ep)
706 {
707         ep->ep_state &= ~EP_HALT_PENDING;
708         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
709          * timer is running on another CPU, we don't decrement stop_cmds_pending
710          * (since we didn't successfully stop the watchdog timer).
711          */
712         if (del_timer(&ep->stop_cmd_timer))
713                 ep->stop_cmds_pending--;
714 }
715
716 /* Must be called with xhci->lock held in interrupt context */
717 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
718                 struct xhci_td *cur_td, int status, char *adjective)
719 {
720         struct usb_hcd *hcd;
721         struct urb      *urb;
722         struct urb_priv *urb_priv;
723
724         urb = cur_td->urb;
725         urb_priv = urb->hcpriv;
726         urb_priv->td_cnt++;
727         hcd = bus_to_hcd(urb->dev->bus);
728
729         /* Only giveback urb when this is the last td in urb */
730         if (urb_priv->td_cnt == urb_priv->length) {
731                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
732                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
733                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
734                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
735                                         usb_amd_quirk_pll_enable();
736                         }
737                 }
738                 usb_hcd_unlink_urb_from_ep(hcd, urb);
739
740                 spin_unlock(&xhci->lock);
741                 usb_hcd_giveback_urb(hcd, urb, status);
742                 xhci_urb_free_priv(xhci, urb_priv);
743                 spin_lock(&xhci->lock);
744         }
745 }
746
747 /*
748  * When we get a command completion for a Stop Endpoint Command, we need to
749  * unlink any cancelled TDs from the ring.  There are two ways to do that:
750  *
751  *  1. If the HW was in the middle of processing the TD that needs to be
752  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
753  *     in the TD with a Set Dequeue Pointer Command.
754  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
755  *     bit cleared) so that the HW will skip over them.
756  */
757 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
758                 union xhci_trb *trb, struct xhci_event_cmd *event)
759 {
760         unsigned int slot_id;
761         unsigned int ep_index;
762         struct xhci_virt_device *virt_dev;
763         struct xhci_ring *ep_ring;
764         struct xhci_virt_ep *ep;
765         struct list_head *entry;
766         struct xhci_td *cur_td = NULL;
767         struct xhci_td *last_unlinked_td;
768
769         struct xhci_dequeue_state deq_state;
770
771         if (unlikely(TRB_TO_SUSPEND_PORT(
772                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
773                 slot_id = TRB_TO_SLOT_ID(
774                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
775                 virt_dev = xhci->devs[slot_id];
776                 if (virt_dev)
777                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
778                                 event);
779                 else
780                         xhci_warn(xhci, "Stop endpoint command "
781                                 "completion for disabled slot %u\n",
782                                 slot_id);
783                 return;
784         }
785
786         memset(&deq_state, 0, sizeof(deq_state));
787         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
788         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
789         ep = &xhci->devs[slot_id]->eps[ep_index];
790
791         if (list_empty(&ep->cancelled_td_list)) {
792                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
793                 ep->stopped_td = NULL;
794                 ep->stopped_trb = NULL;
795                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
796                 return;
797         }
798
799         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
800          * We have the xHCI lock, so nothing can modify this list until we drop
801          * it.  We're also in the event handler, so we can't get re-interrupted
802          * if another Stop Endpoint command completes
803          */
804         list_for_each(entry, &ep->cancelled_td_list) {
805                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
806                 xhci_dbg(xhci, "Removing canceled TD starting at 0x%llx (dma).\n",
807                                 (unsigned long long)xhci_trb_virt_to_dma(
808                                         cur_td->start_seg, cur_td->first_trb));
809                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
810                 if (!ep_ring) {
811                         /* This shouldn't happen unless a driver is mucking
812                          * with the stream ID after submission.  This will
813                          * leave the TD on the hardware ring, and the hardware
814                          * will try to execute it, and may access a buffer
815                          * that has already been freed.  In the best case, the
816                          * hardware will execute it, and the event handler will
817                          * ignore the completion event for that TD, since it was
818                          * removed from the td_list for that endpoint.  In
819                          * short, don't muck with the stream ID after
820                          * submission.
821                          */
822                         xhci_warn(xhci, "WARN Cancelled URB %p "
823                                         "has invalid stream ID %u.\n",
824                                         cur_td->urb,
825                                         cur_td->urb->stream_id);
826                         goto remove_finished_td;
827                 }
828                 /*
829                  * If we stopped on the TD we need to cancel, then we have to
830                  * move the xHC endpoint ring dequeue pointer past this TD.
831                  */
832                 if (cur_td == ep->stopped_td)
833                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
834                                         cur_td->urb->stream_id,
835                                         cur_td, &deq_state);
836                 else
837                         td_to_noop(xhci, ep_ring, cur_td, false);
838 remove_finished_td:
839                 /*
840                  * The event handler won't see a completion for this TD anymore,
841                  * so remove it from the endpoint ring's TD list.  Keep it in
842                  * the cancelled TD list for URB completion later.
843                  */
844                 list_del_init(&cur_td->td_list);
845         }
846         last_unlinked_td = cur_td;
847         xhci_stop_watchdog_timer_in_irq(xhci, ep);
848
849         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
850         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
851                 xhci_queue_new_dequeue_state(xhci,
852                                 slot_id, ep_index,
853                                 ep->stopped_td->urb->stream_id,
854                                 &deq_state);
855                 xhci_ring_cmd_db(xhci);
856         } else {
857                 /* Otherwise ring the doorbell(s) to restart queued transfers */
858                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
859         }
860
861         /* Clear stopped_td and stopped_trb if endpoint is not halted */
862         if (!(ep->ep_state & EP_HALTED)) {
863                 ep->stopped_td = NULL;
864                 ep->stopped_trb = NULL;
865         }
866
867         /*
868          * Drop the lock and complete the URBs in the cancelled TD list.
869          * New TDs to be cancelled might be added to the end of the list before
870          * we can complete all the URBs for the TDs we already unlinked.
871          * So stop when we've completed the URB for the last TD we unlinked.
872          */
873         do {
874                 cur_td = list_entry(ep->cancelled_td_list.next,
875                                 struct xhci_td, cancelled_td_list);
876                 list_del_init(&cur_td->cancelled_td_list);
877
878                 /* Clean up the cancelled URB */
879                 /* Doesn't matter what we pass for status, since the core will
880                  * just overwrite it (because the URB has been unlinked).
881                  */
882                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
883
884                 /* Stop processing the cancelled list if the watchdog timer is
885                  * running.
886                  */
887                 if (xhci->xhc_state & XHCI_STATE_DYING)
888                         return;
889         } while (cur_td != last_unlinked_td);
890
891         /* Return to the event handler with xhci->lock re-acquired */
892 }
893
894 /* Watchdog timer function for when a stop endpoint command fails to complete.
895  * In this case, we assume the host controller is broken or dying or dead.  The
896  * host may still be completing some other events, so we have to be careful to
897  * let the event ring handler and the URB dequeueing/enqueueing functions know
898  * through xhci->state.
899  *
900  * The timer may also fire if the host takes a very long time to respond to the
901  * command, and the stop endpoint command completion handler cannot delete the
902  * timer before the timer function is called.  Another endpoint cancellation may
903  * sneak in before the timer function can grab the lock, and that may queue
904  * another stop endpoint command and add the timer back.  So we cannot use a
905  * simple flag to say whether there is a pending stop endpoint command for a
906  * particular endpoint.
907  *
908  * Instead we use a combination of that flag and a counter for the number of
909  * pending stop endpoint commands.  If the timer is the tail end of the last
910  * stop endpoint command, and the endpoint's command is still pending, we assume
911  * the host is dying.
912  */
913 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
914 {
915         struct xhci_hcd *xhci;
916         struct xhci_virt_ep *ep;
917         struct xhci_virt_ep *temp_ep;
918         struct xhci_ring *ring;
919         struct xhci_td *cur_td;
920         int ret, i, j;
921         unsigned long flags;
922
923         ep = (struct xhci_virt_ep *) arg;
924         xhci = ep->xhci;
925
926         spin_lock_irqsave(&xhci->lock, flags);
927
928         ep->stop_cmds_pending--;
929         if (xhci->xhc_state & XHCI_STATE_DYING) {
930                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
931                                 "xHCI as DYING, exiting.\n");
932                 spin_unlock_irqrestore(&xhci->lock, flags);
933                 return;
934         }
935         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
936                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
937                                 "exiting.\n");
938                 spin_unlock_irqrestore(&xhci->lock, flags);
939                 return;
940         }
941
942         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
943         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
944         /* Oops, HC is dead or dying or at least not responding to the stop
945          * endpoint command.
946          */
947         xhci->xhc_state |= XHCI_STATE_DYING;
948         /* Disable interrupts from the host controller and start halting it */
949         xhci_quiesce(xhci);
950         spin_unlock_irqrestore(&xhci->lock, flags);
951
952         ret = xhci_halt(xhci);
953
954         spin_lock_irqsave(&xhci->lock, flags);
955         if (ret < 0) {
956                 /* This is bad; the host is not responding to commands and it's
957                  * not allowing itself to be halted.  At least interrupts are
958                  * disabled. If we call usb_hc_died(), it will attempt to
959                  * disconnect all device drivers under this host.  Those
960                  * disconnect() methods will wait for all URBs to be unlinked,
961                  * so we must complete them.
962                  */
963                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
964                 xhci_warn(xhci, "Completing active URBs anyway.\n");
965                 /* We could turn all TDs on the rings to no-ops.  This won't
966                  * help if the host has cached part of the ring, and is slow if
967                  * we want to preserve the cycle bit.  Skip it and hope the host
968                  * doesn't touch the memory.
969                  */
970         }
971         for (i = 0; i < MAX_HC_SLOTS; i++) {
972                 if (!xhci->devs[i])
973                         continue;
974                 for (j = 0; j < 31; j++) {
975                         temp_ep = &xhci->devs[i]->eps[j];
976                         ring = temp_ep->ring;
977                         if (!ring)
978                                 continue;
979                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
980                                         "ep index %u\n", i, j);
981                         while (!list_empty(&ring->td_list)) {
982                                 cur_td = list_first_entry(&ring->td_list,
983                                                 struct xhci_td,
984                                                 td_list);
985                                 list_del_init(&cur_td->td_list);
986                                 if (!list_empty(&cur_td->cancelled_td_list))
987                                         list_del_init(&cur_td->cancelled_td_list);
988                                 xhci_giveback_urb_in_irq(xhci, cur_td,
989                                                 -ESHUTDOWN, "killed");
990                         }
991                         while (!list_empty(&temp_ep->cancelled_td_list)) {
992                                 cur_td = list_first_entry(
993                                                 &temp_ep->cancelled_td_list,
994                                                 struct xhci_td,
995                                                 cancelled_td_list);
996                                 list_del_init(&cur_td->cancelled_td_list);
997                                 xhci_giveback_urb_in_irq(xhci, cur_td,
998                                                 -ESHUTDOWN, "killed");
999                         }
1000                 }
1001         }
1002         spin_unlock_irqrestore(&xhci->lock, flags);
1003         xhci_dbg(xhci, "Calling usb_hc_died()\n");
1004         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1005         xhci_dbg(xhci, "xHCI host controller is dead.\n");
1006 }
1007
1008
1009 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1010                 struct xhci_virt_device *dev,
1011                 struct xhci_ring *ep_ring,
1012                 unsigned int ep_index)
1013 {
1014         union xhci_trb *dequeue_temp;
1015         int num_trbs_free_temp;
1016         bool revert = false;
1017
1018         num_trbs_free_temp = ep_ring->num_trbs_free;
1019         dequeue_temp = ep_ring->dequeue;
1020
1021         /* If we get two back-to-back stalls, and the first stalled transfer
1022          * ends just before a link TRB, the dequeue pointer will be left on
1023          * the link TRB by the code in the while loop.  So we have to update
1024          * the dequeue pointer one segment further, or we'll jump off
1025          * the segment into la-la-land.
1026          */
1027         if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
1028                 ep_ring->deq_seg = ep_ring->deq_seg->next;
1029                 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1030         }
1031
1032         while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1033                 /* We have more usable TRBs */
1034                 ep_ring->num_trbs_free++;
1035                 ep_ring->dequeue++;
1036                 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
1037                                 ep_ring->dequeue)) {
1038                         if (ep_ring->dequeue ==
1039                                         dev->eps[ep_index].queued_deq_ptr)
1040                                 break;
1041                         ep_ring->deq_seg = ep_ring->deq_seg->next;
1042                         ep_ring->dequeue = ep_ring->deq_seg->trbs;
1043                 }
1044                 if (ep_ring->dequeue == dequeue_temp) {
1045                         revert = true;
1046                         break;
1047                 }
1048         }
1049
1050         if (revert) {
1051                 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1052                 ep_ring->num_trbs_free = num_trbs_free_temp;
1053         }
1054 }
1055
1056 /*
1057  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1058  * we need to clear the set deq pending flag in the endpoint ring state, so that
1059  * the TD queueing code can ring the doorbell again.  We also need to ring the
1060  * endpoint doorbell to restart the ring, but only if there aren't more
1061  * cancellations pending.
1062  */
1063 static void handle_set_deq_completion(struct xhci_hcd *xhci,
1064                 struct xhci_event_cmd *event,
1065                 union xhci_trb *trb)
1066 {
1067         unsigned int slot_id;
1068         unsigned int ep_index;
1069         unsigned int stream_id;
1070         struct xhci_ring *ep_ring;
1071         struct xhci_virt_device *dev;
1072         struct xhci_ep_ctx *ep_ctx;
1073         struct xhci_slot_ctx *slot_ctx;
1074
1075         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1076         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1077         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1078         dev = xhci->devs[slot_id];
1079
1080         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1081         if (!ep_ring) {
1082                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1083                                 "freed stream ID %u\n",
1084                                 stream_id);
1085                 /* XXX: Harmless??? */
1086                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1087                 return;
1088         }
1089
1090         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1091         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1092
1093         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1094                 unsigned int ep_state;
1095                 unsigned int slot_state;
1096
1097                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1098                 case COMP_TRB_ERR:
1099                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1100                                         "of stream ID configuration\n");
1101                         break;
1102                 case COMP_CTX_STATE:
1103                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1104                                         "to incorrect slot or ep state.\n");
1105                         ep_state = le32_to_cpu(ep_ctx->ep_info);
1106                         ep_state &= EP_STATE_MASK;
1107                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1108                         slot_state = GET_SLOT_STATE(slot_state);
1109                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
1110                                         slot_state, ep_state);
1111                         break;
1112                 case COMP_EBADSLT:
1113                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1114                                         "slot %u was not enabled.\n", slot_id);
1115                         break;
1116                 default:
1117                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1118                                         "completion code of %u.\n",
1119                                   GET_COMP_CODE(le32_to_cpu(event->status)));
1120                         break;
1121                 }
1122                 /* OK what do we do now?  The endpoint state is hosed, and we
1123                  * should never get to this point if the synchronization between
1124                  * queueing, and endpoint state are correct.  This might happen
1125                  * if the device gets disconnected after we've finished
1126                  * cancelling URBs, which might not be an error...
1127                  */
1128         } else {
1129                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1130                          le64_to_cpu(ep_ctx->deq));
1131                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1132                                          dev->eps[ep_index].queued_deq_ptr) ==
1133                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1134                         /* Update the ring's dequeue segment and dequeue pointer
1135                          * to reflect the new position.
1136                          */
1137                         update_ring_for_set_deq_completion(xhci, dev,
1138                                 ep_ring, ep_index);
1139                 } else {
1140                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1141                                         "Ptr command & xHCI internal state.\n");
1142                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1143                                         dev->eps[ep_index].queued_deq_seg,
1144                                         dev->eps[ep_index].queued_deq_ptr);
1145                 }
1146         }
1147
1148         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1149         dev->eps[ep_index].queued_deq_seg = NULL;
1150         dev->eps[ep_index].queued_deq_ptr = NULL;
1151         /* Restart any rings with pending URBs */
1152         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1153 }
1154
1155 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1156                 struct xhci_event_cmd *event,
1157                 union xhci_trb *trb)
1158 {
1159         int slot_id;
1160         unsigned int ep_index;
1161
1162         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1163         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1164         /* This command will only fail if the endpoint wasn't halted,
1165          * but we don't care.
1166          */
1167         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1168                  GET_COMP_CODE(le32_to_cpu(event->status)));
1169
1170         /* HW with the reset endpoint quirk needs to have a configure endpoint
1171          * command complete before the endpoint can be used.  Queue that here
1172          * because the HW can't handle two commands being queued in a row.
1173          */
1174         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1175                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1176                 xhci_queue_configure_endpoint(xhci,
1177                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1178                                 false);
1179                 xhci_ring_cmd_db(xhci);
1180         } else {
1181                 /* Clear our internal halted state */
1182                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1183         }
1184 }
1185
1186 /* Complete the command and detele it from the devcie's command queue.
1187  */
1188 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1189                 struct xhci_command *command, u32 status)
1190 {
1191         command->status = status;
1192         list_del(&command->cmd_list);
1193         if (command->completion)
1194                 complete(command->completion);
1195         else
1196                 xhci_free_command(xhci, command);
1197 }
1198
1199
1200 /* Check to see if a command in the device's command queue matches this one.
1201  * Signal the completion or free the command, and return 1.  Return 0 if the
1202  * completed command isn't at the head of the command list.
1203  */
1204 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1205                 struct xhci_virt_device *virt_dev,
1206                 struct xhci_event_cmd *event)
1207 {
1208         struct xhci_command *command;
1209
1210         if (list_empty(&virt_dev->cmd_list))
1211                 return 0;
1212
1213         command = list_entry(virt_dev->cmd_list.next,
1214                         struct xhci_command, cmd_list);
1215         if (xhci->cmd_ring->dequeue != command->command_trb)
1216                 return 0;
1217
1218         xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1219                         GET_COMP_CODE(le32_to_cpu(event->status)));
1220         return 1;
1221 }
1222
1223 /*
1224  * Finding the command trb need to be cancelled and modifying it to
1225  * NO OP command. And if the command is in device's command wait
1226  * list, finishing and freeing it.
1227  *
1228  * If we can't find the command trb, we think it had already been
1229  * executed.
1230  */
1231 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1232 {
1233         struct xhci_segment *cur_seg;
1234         union xhci_trb *cmd_trb;
1235         u32 cycle_state = 0;
1236
1237         if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1238                 return;
1239
1240         /* find the current segment of command ring */
1241         cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1242                         xhci->cmd_ring->dequeue, &cycle_state);
1243
1244         if (!cur_seg) {
1245                 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1246                                 xhci->cmd_ring->dequeue,
1247                                 (unsigned long long)
1248                                 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1249                                         xhci->cmd_ring->dequeue));
1250                 xhci_debug_ring(xhci, xhci->cmd_ring);
1251                 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1252                 return;
1253         }
1254
1255         /* find the command trb matched by cd from command ring */
1256         for (cmd_trb = xhci->cmd_ring->dequeue;
1257                         cmd_trb != xhci->cmd_ring->enqueue;
1258                         next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1259                 /* If the trb is link trb, continue */
1260                 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1261                         continue;
1262
1263                 if (cur_cd->cmd_trb == cmd_trb) {
1264
1265                         /* If the command in device's command list, we should
1266                          * finish it and free the command structure.
1267                          */
1268                         if (cur_cd->command)
1269                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1270                                         cur_cd->command, COMP_CMD_STOP);
1271
1272                         /* get cycle state from the origin command trb */
1273                         cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1274                                 & TRB_CYCLE;
1275
1276                         /* modify the command trb to NO OP command */
1277                         cmd_trb->generic.field[0] = 0;
1278                         cmd_trb->generic.field[1] = 0;
1279                         cmd_trb->generic.field[2] = 0;
1280                         cmd_trb->generic.field[3] = cpu_to_le32(
1281                                         TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1282                         break;
1283                 }
1284         }
1285 }
1286
1287 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1288 {
1289         struct xhci_cd *cur_cd, *next_cd;
1290
1291         if (list_empty(&xhci->cancel_cmd_list))
1292                 return;
1293
1294         list_for_each_entry_safe(cur_cd, next_cd,
1295                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1296                 xhci_cmd_to_noop(xhci, cur_cd);
1297                 list_del(&cur_cd->cancel_cmd_list);
1298                 kfree(cur_cd);
1299         }
1300 }
1301
1302 /*
1303  * traversing the cancel_cmd_list. If the command descriptor according
1304  * to cmd_trb is found, the function free it and return 1, otherwise
1305  * return 0.
1306  */
1307 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1308                 union xhci_trb *cmd_trb)
1309 {
1310         struct xhci_cd *cur_cd, *next_cd;
1311
1312         if (list_empty(&xhci->cancel_cmd_list))
1313                 return 0;
1314
1315         list_for_each_entry_safe(cur_cd, next_cd,
1316                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1317                 if (cur_cd->cmd_trb == cmd_trb) {
1318                         if (cur_cd->command)
1319                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1320                                         cur_cd->command, COMP_CMD_STOP);
1321                         list_del(&cur_cd->cancel_cmd_list);
1322                         kfree(cur_cd);
1323                         return 1;
1324                 }
1325         }
1326
1327         return 0;
1328 }
1329
1330 /*
1331  * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1332  * trb pointed by the command ring dequeue pointer is the trb we want to
1333  * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1334  * traverse the cancel_cmd_list to trun the all of the commands according
1335  * to command descriptor to NO-OP trb.
1336  */
1337 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1338                 int cmd_trb_comp_code)
1339 {
1340         int cur_trb_is_good = 0;
1341
1342         /* Searching the cmd trb pointed by the command ring dequeue
1343          * pointer in command descriptor list. If it is found, free it.
1344          */
1345         cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1346                         xhci->cmd_ring->dequeue);
1347
1348         if (cmd_trb_comp_code == COMP_CMD_ABORT)
1349                 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1350         else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1351                 /* traversing the cancel_cmd_list and canceling
1352                  * the command according to command descriptor
1353                  */
1354                 xhci_cancel_cmd_in_cd_list(xhci);
1355
1356                 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1357                 /*
1358                  * ring command ring doorbell again to restart the
1359                  * command ring
1360                  */
1361                 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1362                         xhci_ring_cmd_db(xhci);
1363         }
1364         return cur_trb_is_good;
1365 }
1366
1367 static void handle_cmd_completion(struct xhci_hcd *xhci,
1368                 struct xhci_event_cmd *event)
1369 {
1370         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1371         u64 cmd_dma;
1372         dma_addr_t cmd_dequeue_dma;
1373         struct xhci_input_control_ctx *ctrl_ctx;
1374         struct xhci_virt_device *virt_dev;
1375         unsigned int ep_index;
1376         struct xhci_ring *ep_ring;
1377         unsigned int ep_state;
1378
1379         cmd_dma = le64_to_cpu(event->cmd_trb);
1380         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1381                         xhci->cmd_ring->dequeue);
1382         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1383         if (cmd_dequeue_dma == 0) {
1384                 xhci->error_bitmask |= 1 << 4;
1385                 return;
1386         }
1387         /* Does the DMA address match our internal dequeue pointer address? */
1388         if (cmd_dma != (u64) cmd_dequeue_dma) {
1389                 xhci->error_bitmask |= 1 << 5;
1390                 return;
1391         }
1392
1393         if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) ||
1394                 (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) {
1395                 /* If the return value is 0, we think the trb pointed by
1396                  * command ring dequeue pointer is a good trb. The good
1397                  * trb means we don't want to cancel the trb, but it have
1398                  * been stopped by host. So we should handle it normally.
1399                  * Otherwise, driver should invoke inc_deq() and return.
1400                  */
1401                 if (handle_stopped_cmd_ring(xhci,
1402                                 GET_COMP_CODE(le32_to_cpu(event->status)))) {
1403                         inc_deq(xhci, xhci->cmd_ring);
1404                         return;
1405                 }
1406                 /* There is no command to handle if we get a stop event when the
1407                  * command ring is empty, event->cmd_trb points to the next
1408                  * unset command
1409                  */
1410                 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1411                         return;
1412         }
1413
1414         /* return if command ring is empty */
1415         if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1416                 return;
1417
1418         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1419                 & TRB_TYPE_BITMASK) {
1420         case TRB_TYPE(TRB_ENABLE_SLOT):
1421                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1422                         xhci->slot_id = slot_id;
1423                 else
1424                         xhci->slot_id = 0;
1425                 complete(&xhci->addr_dev);
1426                 break;
1427         case TRB_TYPE(TRB_DISABLE_SLOT):
1428                 if (xhci->devs[slot_id]) {
1429                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1430                                 /* Delete default control endpoint resources */
1431                                 xhci_free_device_endpoint_resources(xhci,
1432                                                 xhci->devs[slot_id], true);
1433                         xhci_free_virt_device(xhci, slot_id);
1434                 }
1435                 break;
1436         case TRB_TYPE(TRB_CONFIG_EP):
1437                 virt_dev = xhci->devs[slot_id];
1438                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1439                         break;
1440                 /*
1441                  * Configure endpoint commands can come from the USB core
1442                  * configuration or alt setting changes, or because the HW
1443                  * needed an extra configure endpoint command after a reset
1444                  * endpoint command or streams were being configured.
1445                  * If the command was for a halted endpoint, the xHCI driver
1446                  * is not waiting on the configure endpoint command.
1447                  */
1448                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1449                                 virt_dev->in_ctx);
1450                 /* Input ctx add_flags are the endpoint index plus one */
1451                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1452                 /* A usb_set_interface() call directly after clearing a halted
1453                  * condition may race on this quirky hardware.  Not worth
1454                  * worrying about, since this is prototype hardware.  Not sure
1455                  * if this will work for streams, but streams support was
1456                  * untested on this prototype.
1457                  */
1458                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1459                                 ep_index != (unsigned int) -1 &&
1460                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1461                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1462                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1463                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1464                         if (!(ep_state & EP_HALTED))
1465                                 goto bandwidth_change;
1466                         xhci_dbg(xhci, "Completed config ep cmd - "
1467                                         "last ep index = %d, state = %d\n",
1468                                         ep_index, ep_state);
1469                         /* Clear internal halted state and restart ring(s) */
1470                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1471                                 ~EP_HALTED;
1472                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1473                         break;
1474                 }
1475 bandwidth_change:
1476                 xhci_dbg(xhci, "Completed config ep cmd\n");
1477                 xhci->devs[slot_id]->cmd_status =
1478                         GET_COMP_CODE(le32_to_cpu(event->status));
1479                 complete(&xhci->devs[slot_id]->cmd_completion);
1480                 break;
1481         case TRB_TYPE(TRB_EVAL_CONTEXT):
1482                 virt_dev = xhci->devs[slot_id];
1483                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1484                         break;
1485                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1486                 complete(&xhci->devs[slot_id]->cmd_completion);
1487                 break;
1488         case TRB_TYPE(TRB_ADDR_DEV):
1489                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1490                 complete(&xhci->addr_dev);
1491                 break;
1492         case TRB_TYPE(TRB_STOP_RING):
1493                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1494                 break;
1495         case TRB_TYPE(TRB_SET_DEQ):
1496                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1497                 break;
1498         case TRB_TYPE(TRB_CMD_NOOP):
1499                 break;
1500         case TRB_TYPE(TRB_RESET_EP):
1501                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1502                 break;
1503         case TRB_TYPE(TRB_RESET_DEV):
1504                 xhci_dbg(xhci, "Completed reset device command.\n");
1505                 slot_id = TRB_TO_SLOT_ID(
1506                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1507                 virt_dev = xhci->devs[slot_id];
1508                 if (virt_dev)
1509                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1510                 else
1511                         xhci_warn(xhci, "Reset device command completion "
1512                                         "for disabled slot %u\n", slot_id);
1513                 break;
1514         case TRB_TYPE(TRB_NEC_GET_FW):
1515                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1516                         xhci->error_bitmask |= 1 << 6;
1517                         break;
1518                 }
1519                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1520                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1521                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1522                 break;
1523         default:
1524                 /* Skip over unknown commands on the event ring */
1525                 xhci->error_bitmask |= 1 << 6;
1526                 break;
1527         }
1528         inc_deq(xhci, xhci->cmd_ring);
1529 }
1530
1531 static void handle_vendor_event(struct xhci_hcd *xhci,
1532                 union xhci_trb *event)
1533 {
1534         u32 trb_type;
1535
1536         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1537         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1538         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1539                 handle_cmd_completion(xhci, &event->event_cmd);
1540 }
1541
1542 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1543  * port registers -- USB 3.0 and USB 2.0).
1544  *
1545  * Returns a zero-based port number, which is suitable for indexing into each of
1546  * the split roothubs' port arrays and bus state arrays.
1547  * Add one to it in order to call xhci_find_slot_id_by_port.
1548  */
1549 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1550                 struct xhci_hcd *xhci, u32 port_id)
1551 {
1552         unsigned int i;
1553         unsigned int num_similar_speed_ports = 0;
1554
1555         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1556          * and usb2_ports are 0-based indexes.  Count the number of similar
1557          * speed ports, up to 1 port before this port.
1558          */
1559         for (i = 0; i < (port_id - 1); i++) {
1560                 u8 port_speed = xhci->port_array[i];
1561
1562                 /*
1563                  * Skip ports that don't have known speeds, or have duplicate
1564                  * Extended Capabilities port speed entries.
1565                  */
1566                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1567                         continue;
1568
1569                 /*
1570                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1571                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1572                  * matches the device speed, it's a similar speed port.
1573                  */
1574                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1575                         num_similar_speed_ports++;
1576         }
1577         return num_similar_speed_ports;
1578 }
1579
1580 static void handle_device_notification(struct xhci_hcd *xhci,
1581                 union xhci_trb *event)
1582 {
1583         u32 slot_id;
1584         struct usb_device *udev;
1585
1586         slot_id = TRB_TO_SLOT_ID(event->generic.field[3]);
1587         if (!xhci->devs[slot_id]) {
1588                 xhci_warn(xhci, "Device Notification event for "
1589                                 "unused slot %u\n", slot_id);
1590                 return;
1591         }
1592
1593         xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1594                         slot_id);
1595         udev = xhci->devs[slot_id]->udev;
1596         if (udev && udev->parent)
1597                 usb_wakeup_notification(udev->parent, udev->portnum);
1598 }
1599
1600 static void handle_port_status(struct xhci_hcd *xhci,
1601                 union xhci_trb *event)
1602 {
1603         struct usb_hcd *hcd;
1604         u32 port_id;
1605         u32 temp, temp1;
1606         int max_ports;
1607         int slot_id;
1608         unsigned int faked_port_index;
1609         u8 major_revision;
1610         struct xhci_bus_state *bus_state;
1611         __le32 __iomem **port_array;
1612         bool bogus_port_status = false;
1613
1614         /* Port status change events always have a successful completion code */
1615         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1616                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1617                 xhci->error_bitmask |= 1 << 8;
1618         }
1619         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1620         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1621
1622         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1623         if ((port_id <= 0) || (port_id > max_ports)) {
1624                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1625                 inc_deq(xhci, xhci->event_ring);
1626                 return;
1627         }
1628
1629         /* Figure out which usb_hcd this port is attached to:
1630          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1631          */
1632         major_revision = xhci->port_array[port_id - 1];
1633
1634         /* Find the right roothub. */
1635         hcd = xhci_to_hcd(xhci);
1636         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1637                 hcd = xhci->shared_hcd;
1638
1639         if (major_revision == 0) {
1640                 xhci_warn(xhci, "Event for port %u not in "
1641                                 "Extended Capabilities, ignoring.\n",
1642                                 port_id);
1643                 bogus_port_status = true;
1644                 goto cleanup;
1645         }
1646         if (major_revision == DUPLICATE_ENTRY) {
1647                 xhci_warn(xhci, "Event for port %u duplicated in"
1648                                 "Extended Capabilities, ignoring.\n",
1649                                 port_id);
1650                 bogus_port_status = true;
1651                 goto cleanup;
1652         }
1653
1654         /*
1655          * Hardware port IDs reported by a Port Status Change Event include USB
1656          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1657          * resume event, but we first need to translate the hardware port ID
1658          * into the index into the ports on the correct split roothub, and the
1659          * correct bus_state structure.
1660          */
1661         bus_state = &xhci->bus_state[hcd_index(hcd)];
1662         if (hcd->speed == HCD_USB3)
1663                 port_array = xhci->usb3_ports;
1664         else
1665                 port_array = xhci->usb2_ports;
1666         /* Find the faked port hub number */
1667         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1668                         port_id);
1669
1670         temp = xhci_readl(xhci, port_array[faked_port_index]);
1671         if (hcd->state == HC_STATE_SUSPENDED) {
1672                 xhci_dbg(xhci, "resume root hub\n");
1673                 usb_hcd_resume_root_hub(hcd);
1674         }
1675
1676         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1677                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1678
1679                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1680                 if (!(temp1 & CMD_RUN)) {
1681                         xhci_warn(xhci, "xHC is not running.\n");
1682                         goto cleanup;
1683                 }
1684
1685                 if (DEV_SUPERSPEED(temp)) {
1686                         xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1687                         /* Set a flag to say the port signaled remote wakeup,
1688                          * so we can tell the difference between the end of
1689                          * device and host initiated resume.
1690                          */
1691                         bus_state->port_remote_wakeup |= 1 << faked_port_index;
1692                         xhci_test_and_clear_bit(xhci, port_array,
1693                                         faked_port_index, PORT_PLC);
1694                         xhci_set_link_state(xhci, port_array, faked_port_index,
1695                                                 XDEV_U0);
1696                         /* Need to wait until the next link state change
1697                          * indicates the device is actually in U0.
1698                          */
1699                         bogus_port_status = true;
1700                         goto cleanup;
1701                 } else {
1702                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1703                         bus_state->resume_done[faked_port_index] = jiffies +
1704                                 msecs_to_jiffies(20);
1705                         set_bit(faked_port_index, &bus_state->resuming_ports);
1706                         mod_timer(&hcd->rh_timer,
1707                                   bus_state->resume_done[faked_port_index]);
1708                         /* Do the rest in GetPortStatus */
1709                 }
1710         }
1711
1712         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1713                         DEV_SUPERSPEED(temp)) {
1714                 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1715                 /* We've just brought the device into U0 through either the
1716                  * Resume state after a device remote wakeup, or through the
1717                  * U3Exit state after a host-initiated resume.  If it's a device
1718                  * initiated remote wake, don't pass up the link state change,
1719                  * so the roothub behavior is consistent with external
1720                  * USB 3.0 hub behavior.
1721                  */
1722                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1723                                 faked_port_index + 1);
1724                 if (slot_id && xhci->devs[slot_id])
1725                         xhci_ring_device(xhci, slot_id);
1726                 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1727                         bus_state->port_remote_wakeup &=
1728                                 ~(1 << faked_port_index);
1729                         xhci_test_and_clear_bit(xhci, port_array,
1730                                         faked_port_index, PORT_PLC);
1731                         usb_wakeup_notification(hcd->self.root_hub,
1732                                         faked_port_index + 1);
1733                         bogus_port_status = true;
1734                         goto cleanup;
1735                 }
1736         }
1737
1738         if (hcd->speed != HCD_USB3)
1739                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1740                                         PORT_PLC);
1741
1742 cleanup:
1743         /* Update event ring dequeue pointer before dropping the lock */
1744         inc_deq(xhci, xhci->event_ring);
1745
1746         /* Don't make the USB core poll the roothub if we got a bad port status
1747          * change event.  Besides, at that point we can't tell which roothub
1748          * (USB 2.0 or USB 3.0) to kick.
1749          */
1750         if (bogus_port_status)
1751                 return;
1752
1753         /*
1754          * xHCI port-status-change events occur when the "or" of all the
1755          * status-change bits in the portsc register changes from 0 to 1.
1756          * New status changes won't cause an event if any other change
1757          * bits are still set.  When an event occurs, switch over to
1758          * polling to avoid losing status changes.
1759          */
1760         xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1761         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1762         spin_unlock(&xhci->lock);
1763         /* Pass this up to the core */
1764         usb_hcd_poll_rh_status(hcd);
1765         spin_lock(&xhci->lock);
1766 }
1767
1768 /*
1769  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1770  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1771  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1772  * returns 0.
1773  */
1774 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1775                 union xhci_trb  *start_trb,
1776                 union xhci_trb  *end_trb,
1777                 dma_addr_t      suspect_dma)
1778 {
1779         dma_addr_t start_dma;
1780         dma_addr_t end_seg_dma;
1781         dma_addr_t end_trb_dma;
1782         struct xhci_segment *cur_seg;
1783
1784         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1785         cur_seg = start_seg;
1786
1787         do {
1788                 if (start_dma == 0)
1789                         return NULL;
1790                 /* We may get an event for a Link TRB in the middle of a TD */
1791                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1792                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1793                 /* If the end TRB isn't in this segment, this is set to 0 */
1794                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1795
1796                 if (end_trb_dma > 0) {
1797                         /* The end TRB is in this segment, so suspect should be here */
1798                         if (start_dma <= end_trb_dma) {
1799                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1800                                         return cur_seg;
1801                         } else {
1802                                 /* Case for one segment with
1803                                  * a TD wrapped around to the top
1804                                  */
1805                                 if ((suspect_dma >= start_dma &&
1806                                                         suspect_dma <= end_seg_dma) ||
1807                                                 (suspect_dma >= cur_seg->dma &&
1808                                                  suspect_dma <= end_trb_dma))
1809                                         return cur_seg;
1810                         }
1811                         return NULL;
1812                 } else {
1813                         /* Might still be somewhere in this segment */
1814                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1815                                 return cur_seg;
1816                 }
1817                 cur_seg = cur_seg->next;
1818                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1819         } while (cur_seg != start_seg);
1820
1821         return NULL;
1822 }
1823
1824 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1825                 unsigned int slot_id, unsigned int ep_index,
1826                 unsigned int stream_id,
1827                 struct xhci_td *td, union xhci_trb *event_trb)
1828 {
1829         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1830         ep->ep_state |= EP_HALTED;
1831         ep->stopped_td = td;
1832         ep->stopped_trb = event_trb;
1833         ep->stopped_stream = stream_id;
1834
1835         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1836         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1837
1838         ep->stopped_td = NULL;
1839         ep->stopped_trb = NULL;
1840         ep->stopped_stream = 0;
1841
1842         xhci_ring_cmd_db(xhci);
1843 }
1844
1845 /* Check if an error has halted the endpoint ring.  The class driver will
1846  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1847  * However, a babble and other errors also halt the endpoint ring, and the class
1848  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1849  * Ring Dequeue Pointer command manually.
1850  */
1851 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1852                 struct xhci_ep_ctx *ep_ctx,
1853                 unsigned int trb_comp_code)
1854 {
1855         /* TRB completion codes that may require a manual halt cleanup */
1856         if (trb_comp_code == COMP_TX_ERR ||
1857                         trb_comp_code == COMP_BABBLE ||
1858                         trb_comp_code == COMP_SPLIT_ERR)
1859                 /* The 0.96 spec says a babbling control endpoint
1860                  * is not halted. The 0.96 spec says it is.  Some HW
1861                  * claims to be 0.95 compliant, but it halts the control
1862                  * endpoint anyway.  Check if a babble halted the
1863                  * endpoint.
1864                  */
1865                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1866                     cpu_to_le32(EP_STATE_HALTED))
1867                         return 1;
1868
1869         return 0;
1870 }
1871
1872 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1873 {
1874         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1875                 /* Vendor defined "informational" completion code,
1876                  * treat as not-an-error.
1877                  */
1878                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1879                                 trb_comp_code);
1880                 xhci_dbg(xhci, "Treating code as success.\n");
1881                 return 1;
1882         }
1883         return 0;
1884 }
1885
1886 /*
1887  * Finish the td processing, remove the td from td list;
1888  * Return 1 if the urb can be given back.
1889  */
1890 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1891         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1892         struct xhci_virt_ep *ep, int *status, bool skip)
1893 {
1894         struct xhci_virt_device *xdev;
1895         struct xhci_ring *ep_ring;
1896         unsigned int slot_id;
1897         int ep_index;
1898         struct urb *urb = NULL;
1899         struct xhci_ep_ctx *ep_ctx;
1900         int ret = 0;
1901         struct urb_priv *urb_priv;
1902         u32 trb_comp_code;
1903
1904         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1905         xdev = xhci->devs[slot_id];
1906         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1907         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1908         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1909         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1910
1911         if (skip)
1912                 goto td_cleanup;
1913
1914         if (trb_comp_code == COMP_STOP_INVAL ||
1915                         trb_comp_code == COMP_STOP) {
1916                 /* The Endpoint Stop Command completion will take care of any
1917                  * stopped TDs.  A stopped TD may be restarted, so don't update
1918                  * the ring dequeue pointer or take this TD off any lists yet.
1919                  */
1920                 ep->stopped_td = td;
1921                 ep->stopped_trb = event_trb;
1922                 return 0;
1923         } else {
1924                 if (trb_comp_code == COMP_STALL) {
1925                         /* The transfer is completed from the driver's
1926                          * perspective, but we need to issue a set dequeue
1927                          * command for this stalled endpoint to move the dequeue
1928                          * pointer past the TD.  We can't do that here because
1929                          * the halt condition must be cleared first.  Let the
1930                          * USB class driver clear the stall later.
1931                          */
1932                         ep->stopped_td = td;
1933                         ep->stopped_trb = event_trb;
1934                         ep->stopped_stream = ep_ring->stream_id;
1935                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1936                                         ep_ctx, trb_comp_code)) {
1937                         /* Other types of errors halt the endpoint, but the
1938                          * class driver doesn't call usb_reset_endpoint() unless
1939                          * the error is -EPIPE.  Clear the halted status in the
1940                          * xHCI hardware manually.
1941                          */
1942                         xhci_cleanup_halted_endpoint(xhci,
1943                                         slot_id, ep_index, ep_ring->stream_id,
1944                                         td, event_trb);
1945                 } else {
1946                         /* Update ring dequeue pointer */
1947                         while (ep_ring->dequeue != td->last_trb)
1948                                 inc_deq(xhci, ep_ring);
1949                         inc_deq(xhci, ep_ring);
1950                 }
1951
1952 td_cleanup:
1953                 /* Clean up the endpoint's TD list */
1954                 urb = td->urb;
1955                 urb_priv = urb->hcpriv;
1956
1957                 /* Do one last check of the actual transfer length.
1958                  * If the host controller said we transferred more data than
1959                  * the buffer length, urb->actual_length will be a very big
1960                  * number (since it's unsigned).  Play it safe and say we didn't
1961                  * transfer anything.
1962                  */
1963                 if (urb->actual_length > urb->transfer_buffer_length) {
1964                         xhci_warn(xhci, "URB transfer length is wrong, "
1965                                         "xHC issue? req. len = %u, "
1966                                         "act. len = %u\n",
1967                                         urb->transfer_buffer_length,
1968                                         urb->actual_length);
1969                         urb->actual_length = 0;
1970                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1971                                 *status = -EREMOTEIO;
1972                         else
1973                                 *status = 0;
1974                 }
1975                 list_del_init(&td->td_list);
1976                 /* Was this TD slated to be cancelled but completed anyway? */
1977                 if (!list_empty(&td->cancelled_td_list))
1978                         list_del_init(&td->cancelled_td_list);
1979
1980                 urb_priv->td_cnt++;
1981                 /* Giveback the urb when all the tds are completed */
1982                 if (urb_priv->td_cnt == urb_priv->length) {
1983                         ret = 1;
1984                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1985                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1986                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1987                                         == 0) {
1988                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1989                                                 usb_amd_quirk_pll_enable();
1990                                 }
1991                         }
1992                 }
1993         }
1994
1995         return ret;
1996 }
1997
1998 /*
1999  * Process control tds, update urb status and actual_length.
2000  */
2001 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2002         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2003         struct xhci_virt_ep *ep, int *status)
2004 {
2005         struct xhci_virt_device *xdev;
2006         struct xhci_ring *ep_ring;
2007         unsigned int slot_id;
2008         int ep_index;
2009         struct xhci_ep_ctx *ep_ctx;
2010         u32 trb_comp_code;
2011
2012         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2013         xdev = xhci->devs[slot_id];
2014         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2015         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2016         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2017         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2018
2019         switch (trb_comp_code) {
2020         case COMP_SUCCESS:
2021                 if (event_trb == ep_ring->dequeue) {
2022                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
2023                                         "without IOC set??\n");
2024                         *status = -ESHUTDOWN;
2025                 } else if (event_trb != td->last_trb) {
2026                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
2027                                         "without IOC set??\n");
2028                         *status = -ESHUTDOWN;
2029                 } else {
2030                         *status = 0;
2031                 }
2032                 break;
2033         case COMP_SHORT_TX:
2034                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2035                         *status = -EREMOTEIO;
2036                 else
2037                         *status = 0;
2038                 break;
2039         case COMP_STOP_INVAL:
2040         case COMP_STOP:
2041                 return finish_td(xhci, td, event_trb, event, ep, status, false);
2042         default:
2043                 if (!xhci_requires_manual_halt_cleanup(xhci,
2044                                         ep_ctx, trb_comp_code))
2045                         break;
2046                 xhci_dbg(xhci, "TRB error code %u, "
2047                                 "halted endpoint index = %u\n",
2048                                 trb_comp_code, ep_index);
2049                 /* else fall through */
2050         case COMP_STALL:
2051                 /* Did we transfer part of the data (middle) phase? */
2052                 if (event_trb != ep_ring->dequeue &&
2053                                 event_trb != td->last_trb)
2054                         td->urb->actual_length =
2055                                 td->urb->transfer_buffer_length -
2056                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2057                 else
2058                         td->urb->actual_length = 0;
2059
2060                 xhci_cleanup_halted_endpoint(xhci,
2061                         slot_id, ep_index, 0, td, event_trb);
2062                 return finish_td(xhci, td, event_trb, event, ep, status, true);
2063         }
2064         /*
2065          * Did we transfer any data, despite the errors that might have
2066          * happened?  I.e. did we get past the setup stage?
2067          */
2068         if (event_trb != ep_ring->dequeue) {
2069                 /* The event was for the status stage */
2070                 if (event_trb == td->last_trb) {
2071                         if (td->urb->actual_length != 0) {
2072                                 /* Don't overwrite a previously set error code
2073                                  */
2074                                 if ((*status == -EINPROGRESS || *status == 0) &&
2075                                                 (td->urb->transfer_flags
2076                                                  & URB_SHORT_NOT_OK))
2077                                         /* Did we already see a short data
2078                                          * stage? */
2079                                         *status = -EREMOTEIO;
2080                         } else {
2081                                 td->urb->actual_length =
2082                                         td->urb->transfer_buffer_length;
2083                         }
2084                 } else {
2085                 /* Maybe the event was for the data stage? */
2086                         td->urb->actual_length =
2087                                 td->urb->transfer_buffer_length -
2088                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2089                         xhci_dbg(xhci, "Waiting for status "
2090                                         "stage event\n");
2091                         return 0;
2092                 }
2093         }
2094
2095         return finish_td(xhci, td, event_trb, event, ep, status, false);
2096 }
2097
2098 /*
2099  * Process isochronous tds, update urb packet status and actual_length.
2100  */
2101 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2102         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2103         struct xhci_virt_ep *ep, int *status)
2104 {
2105         struct xhci_ring *ep_ring;
2106         struct urb_priv *urb_priv;
2107         int idx;
2108         int len = 0;
2109         union xhci_trb *cur_trb;
2110         struct xhci_segment *cur_seg;
2111         struct usb_iso_packet_descriptor *frame;
2112         u32 trb_comp_code;
2113         bool skip_td = false;
2114
2115         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2116         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2117         urb_priv = td->urb->hcpriv;
2118         idx = urb_priv->td_cnt;
2119         frame = &td->urb->iso_frame_desc[idx];
2120
2121         /* handle completion code */
2122         switch (trb_comp_code) {
2123         case COMP_SUCCESS:
2124                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2125                         frame->status = 0;
2126                         break;
2127                 }
2128                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2129                         trb_comp_code = COMP_SHORT_TX;
2130         case COMP_SHORT_TX:
2131                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2132                                 -EREMOTEIO : 0;
2133                 break;
2134         case COMP_BW_OVER:
2135                 frame->status = -ECOMM;
2136                 skip_td = true;
2137                 break;
2138         case COMP_BUFF_OVER:
2139         case COMP_BABBLE:
2140                 frame->status = -EOVERFLOW;
2141                 skip_td = true;
2142                 break;
2143         case COMP_DEV_ERR:
2144         case COMP_STALL:
2145         case COMP_TX_ERR:
2146                 frame->status = -EPROTO;
2147                 skip_td = true;
2148                 break;
2149         case COMP_STOP:
2150         case COMP_STOP_INVAL:
2151                 break;
2152         default:
2153                 frame->status = -1;
2154                 break;
2155         }
2156
2157         if (trb_comp_code == COMP_SUCCESS || skip_td) {
2158                 frame->actual_length = frame->length;
2159                 td->urb->actual_length += frame->length;
2160         } else {
2161                 if (urb_priv->finishing_short_td &&
2162                                 (event_trb == td->last_trb)) {
2163                         urb_priv->finishing_short_td = false;
2164                         /* get event for last trb, can finish this short td */
2165                         goto finish_td;
2166                 }
2167                 for (cur_trb = ep_ring->dequeue,
2168                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2169                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2170                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2171                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2172                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2173                 }
2174                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2175                         EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2176
2177                 if (trb_comp_code != COMP_STOP_INVAL) {
2178                         frame->actual_length = len;
2179                         td->urb->actual_length += len;
2180                 }
2181                 if ((trb_comp_code == COMP_SHORT_TX) &&
2182                                 (event_trb != td->last_trb)) {
2183                         /* last trb has IOC, expect HC to send event for it */
2184                         while (ep_ring->dequeue != td->last_trb)
2185                                 inc_deq(xhci, ep_ring);
2186                         urb_priv->finishing_short_td = true;
2187                         return 0;
2188                 }
2189         }
2190
2191 finish_td:
2192         return finish_td(xhci, td, event_trb, event, ep, status, false);
2193 }
2194
2195 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2196                         struct xhci_transfer_event *event,
2197                         struct xhci_virt_ep *ep, int *status)
2198 {
2199         struct xhci_ring *ep_ring;
2200         struct urb_priv *urb_priv;
2201         struct usb_iso_packet_descriptor *frame;
2202         int idx;
2203
2204         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2205         urb_priv = td->urb->hcpriv;
2206         idx = urb_priv->td_cnt;
2207         frame = &td->urb->iso_frame_desc[idx];
2208
2209         /* The transfer is partly done. */
2210         frame->status = -EXDEV;
2211
2212         /* calc actual length */
2213         frame->actual_length = 0;
2214
2215         /* Update ring dequeue pointer */
2216         while (ep_ring->dequeue != td->last_trb)
2217                 inc_deq(xhci, ep_ring);
2218         inc_deq(xhci, ep_ring);
2219
2220         return finish_td(xhci, td, NULL, event, ep, status, true);
2221 }
2222
2223 /*
2224  * Process bulk and interrupt tds, update urb status and actual_length.
2225  */
2226 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2227         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2228         struct xhci_virt_ep *ep, int *status)
2229 {
2230         struct xhci_ring *ep_ring;
2231         union xhci_trb *cur_trb;
2232         struct xhci_segment *cur_seg;
2233         u32 trb_comp_code;
2234
2235         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2236         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2237
2238         switch (trb_comp_code) {
2239         case COMP_SUCCESS:
2240                 /* Double check that the HW transferred everything. */
2241                 if (event_trb != td->last_trb ||
2242                     EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2243                         xhci_warn(xhci, "WARN Successful completion "
2244                                         "on short TX\n");
2245                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2246                                 *status = -EREMOTEIO;
2247                         else
2248                                 *status = 0;
2249                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2250                                 trb_comp_code = COMP_SHORT_TX;
2251                 } else {
2252                         *status = 0;
2253                 }
2254                 break;
2255         case COMP_SHORT_TX:
2256                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2257                         *status = -EREMOTEIO;
2258                 else
2259                         *status = 0;
2260                 break;
2261         default:
2262                 /* Others already handled above */
2263                 break;
2264         }
2265         if (trb_comp_code == COMP_SHORT_TX)
2266                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2267                                 "%d bytes untransferred\n",
2268                                 td->urb->ep->desc.bEndpointAddress,
2269                                 td->urb->transfer_buffer_length,
2270                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2271         /* Fast path - was this the last TRB in the TD for this URB? */
2272         if (event_trb == td->last_trb) {
2273                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2274                         td->urb->actual_length =
2275                                 td->urb->transfer_buffer_length -
2276                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2277                         if (td->urb->transfer_buffer_length <
2278                                         td->urb->actual_length) {
2279                                 xhci_warn(xhci, "HC gave bad length "
2280                                                 "of %d bytes left\n",
2281                                           EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2282                                 td->urb->actual_length = 0;
2283                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2284                                         *status = -EREMOTEIO;
2285                                 else
2286                                         *status = 0;
2287                         }
2288                         /* Don't overwrite a previously set error code */
2289                         if (*status == -EINPROGRESS) {
2290                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2291                                         *status = -EREMOTEIO;
2292                                 else
2293                                         *status = 0;
2294                         }
2295                 } else {
2296                         td->urb->actual_length =
2297                                 td->urb->transfer_buffer_length;
2298                         /* Ignore a short packet completion if the
2299                          * untransferred length was zero.
2300                          */
2301                         if (*status == -EREMOTEIO)
2302                                 *status = 0;
2303                 }
2304         } else {
2305                 /* Slow path - walk the list, starting from the dequeue
2306                  * pointer, to get the actual length transferred.
2307                  */
2308                 td->urb->actual_length = 0;
2309                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2310                                 cur_trb != event_trb;
2311                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2312                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2313                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2314                                 td->urb->actual_length +=
2315                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2316                 }
2317                 /* If the ring didn't stop on a Link or No-op TRB, add
2318                  * in the actual bytes transferred from the Normal TRB
2319                  */
2320                 if (trb_comp_code != COMP_STOP_INVAL)
2321                         td->urb->actual_length +=
2322                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2323                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2324         }
2325
2326         return finish_td(xhci, td, event_trb, event, ep, status, false);
2327 }
2328
2329 /*
2330  * If this function returns an error condition, it means it got a Transfer
2331  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2332  * At this point, the host controller is probably hosed and should be reset.
2333  */
2334 static int handle_tx_event(struct xhci_hcd *xhci,
2335                 struct xhci_transfer_event *event)
2336         __releases(&xhci->lock)
2337         __acquires(&xhci->lock)
2338 {
2339         struct xhci_virt_device *xdev;
2340         struct xhci_virt_ep *ep;
2341         struct xhci_ring *ep_ring;
2342         unsigned int slot_id;
2343         int ep_index;
2344         struct xhci_td *td = NULL;
2345         dma_addr_t event_dma;
2346         struct xhci_segment *event_seg;
2347         union xhci_trb *event_trb;
2348         struct urb *urb = NULL;
2349         int status = -EINPROGRESS;
2350         struct urb_priv *urb_priv;
2351         struct xhci_ep_ctx *ep_ctx;
2352         struct list_head *tmp;
2353         u32 trb_comp_code;
2354         int ret = 0;
2355         int td_num = 0;
2356
2357         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2358         xdev = xhci->devs[slot_id];
2359         if (!xdev) {
2360                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2361                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2362                          (unsigned long long) xhci_trb_virt_to_dma(
2363                                  xhci->event_ring->deq_seg,
2364                                  xhci->event_ring->dequeue),
2365                          lower_32_bits(le64_to_cpu(event->buffer)),
2366                          upper_32_bits(le64_to_cpu(event->buffer)),
2367                          le32_to_cpu(event->transfer_len),
2368                          le32_to_cpu(event->flags));
2369                 xhci_dbg(xhci, "Event ring:\n");
2370                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2371                 return -ENODEV;
2372         }
2373
2374         /* Endpoint ID is 1 based, our index is zero based */
2375         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2376         ep = &xdev->eps[ep_index];
2377         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2378         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2379         if (!ep_ring ||
2380             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2381             EP_STATE_DISABLED) {
2382                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2383                                 "or incorrect stream ring\n");
2384                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2385                          (unsigned long long) xhci_trb_virt_to_dma(
2386                                  xhci->event_ring->deq_seg,
2387                                  xhci->event_ring->dequeue),
2388                          lower_32_bits(le64_to_cpu(event->buffer)),
2389                          upper_32_bits(le64_to_cpu(event->buffer)),
2390                          le32_to_cpu(event->transfer_len),
2391                          le32_to_cpu(event->flags));
2392                 xhci_dbg(xhci, "Event ring:\n");
2393                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2394                 return -ENODEV;
2395         }
2396
2397         /* Count current td numbers if ep->skip is set */
2398         if (ep->skip) {
2399                 list_for_each(tmp, &ep_ring->td_list)
2400                         td_num++;
2401         }
2402
2403         event_dma = le64_to_cpu(event->buffer);
2404         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2405         /* Look for common error cases */
2406         switch (trb_comp_code) {
2407         /* Skip codes that require special handling depending on
2408          * transfer type
2409          */
2410         case COMP_SUCCESS:
2411                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2412                         break;
2413                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2414                         trb_comp_code = COMP_SHORT_TX;
2415                 else
2416                         xhci_warn_ratelimited(xhci,
2417                                         "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2418         case COMP_SHORT_TX:
2419                 break;
2420         case COMP_STOP:
2421                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2422                 break;
2423         case COMP_STOP_INVAL:
2424                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2425                 break;
2426         case COMP_STALL:
2427                 xhci_dbg(xhci, "Stalled endpoint\n");
2428                 ep->ep_state |= EP_HALTED;
2429                 status = -EPIPE;
2430                 break;
2431         case COMP_TRB_ERR:
2432                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2433                 status = -EILSEQ;
2434                 break;
2435         case COMP_SPLIT_ERR:
2436         case COMP_TX_ERR:
2437                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2438                 status = -EPROTO;
2439                 break;
2440         case COMP_BABBLE:
2441                 xhci_dbg(xhci, "Babble error on endpoint\n");
2442                 status = -EOVERFLOW;
2443                 break;
2444         case COMP_DB_ERR:
2445                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2446                 status = -ENOSR;
2447                 break;
2448         case COMP_BW_OVER:
2449                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2450                 break;
2451         case COMP_BUFF_OVER:
2452                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2453                 break;
2454         case COMP_UNDERRUN:
2455                 /*
2456                  * When the Isoch ring is empty, the xHC will generate
2457                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2458                  * Underrun Event for OUT Isoch endpoint.
2459                  */
2460                 xhci_dbg(xhci, "underrun event on endpoint\n");
2461                 if (!list_empty(&ep_ring->td_list))
2462                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2463                                         "still with TDs queued?\n",
2464                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2465                                  ep_index);
2466                 goto cleanup;
2467         case COMP_OVERRUN:
2468                 xhci_dbg(xhci, "overrun event on endpoint\n");
2469                 if (!list_empty(&ep_ring->td_list))
2470                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2471                                         "still with TDs queued?\n",
2472                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2473                                  ep_index);
2474                 goto cleanup;
2475         case COMP_DEV_ERR:
2476                 xhci_warn(xhci, "WARN: detect an incompatible device");
2477                 status = -EPROTO;
2478                 break;
2479         case COMP_MISSED_INT:
2480                 /*
2481                  * When encounter missed service error, one or more isoc tds
2482                  * may be missed by xHC.
2483                  * Set skip flag of the ep_ring; Complete the missed tds as
2484                  * short transfer when process the ep_ring next time.
2485                  */
2486                 ep->skip = true;
2487                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2488                 goto cleanup;
2489         default:
2490                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2491                         status = 0;
2492                         break;
2493                 }
2494                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2495                                 "busted\n");
2496                 goto cleanup;
2497         }
2498
2499         do {
2500                 /* This TRB should be in the TD at the head of this ring's
2501                  * TD list.
2502                  */
2503                 if (list_empty(&ep_ring->td_list)) {
2504                         /*
2505                          * A stopped endpoint may generate an extra completion
2506                          * event if the device was suspended.  Don't print
2507                          * warnings.
2508                          */
2509                         if (!(trb_comp_code == COMP_STOP ||
2510                                                 trb_comp_code == COMP_STOP_INVAL)) {
2511                                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2512                                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2513                                                 ep_index);
2514                                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2515                                                 (le32_to_cpu(event->flags) &
2516                                                  TRB_TYPE_BITMASK)>>10);
2517                                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2518                         }
2519                         if (ep->skip) {
2520                                 ep->skip = false;
2521                                 xhci_dbg(xhci, "td_list is empty while skip "
2522                                                 "flag set. Clear skip flag.\n");
2523                         }
2524                         ret = 0;
2525                         goto cleanup;
2526                 }
2527
2528                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2529                 if (ep->skip && td_num == 0) {
2530                         ep->skip = false;
2531                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2532                                                 "Clear skip flag.\n");
2533                         ret = 0;
2534                         goto cleanup;
2535                 }
2536
2537                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2538                 if (ep->skip)
2539                         td_num--;
2540
2541                 /* Is this a TRB in the currently executing TD? */
2542                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2543                                 td->last_trb, event_dma);
2544
2545                 /*
2546                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2547                  * is not in the current TD pointed by ep_ring->dequeue because
2548                  * that the hardware dequeue pointer still at the previous TRB
2549                  * of the current TD. The previous TRB maybe a Link TD or the
2550                  * last TRB of the previous TD. The command completion handle
2551                  * will take care the rest.
2552                  */
2553                 if (!event_seg && (trb_comp_code == COMP_STOP ||
2554                                    trb_comp_code == COMP_STOP_INVAL)) {
2555                         ret = 0;
2556                         goto cleanup;
2557                 }
2558
2559                 if (!event_seg) {
2560                         if (!ep->skip ||
2561                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2562                                 /* Some host controllers give a spurious
2563                                  * successful event after a short transfer.
2564                                  * Ignore it.
2565                                  */
2566                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && 
2567                                                 ep_ring->last_td_was_short) {
2568                                         ep_ring->last_td_was_short = false;
2569                                         ret = 0;
2570                                         goto cleanup;
2571                                 }
2572                                 /* HC is busted, give up! */
2573                                 xhci_err(xhci,
2574                                         "ERROR Transfer event TRB DMA ptr not "
2575                                         "part of current TD\n");
2576                                 return -ESHUTDOWN;
2577                         }
2578
2579                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2580                         goto cleanup;
2581                 }
2582                 if (trb_comp_code == COMP_SHORT_TX)
2583                         ep_ring->last_td_was_short = true;
2584                 else
2585                         ep_ring->last_td_was_short = false;
2586
2587                 if (ep->skip) {
2588                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2589                         ep->skip = false;
2590                 }
2591
2592                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2593                                                 sizeof(*event_trb)];
2594                 /*
2595                  * No-op TRB should not trigger interrupts.
2596                  * If event_trb is a no-op TRB, it means the
2597                  * corresponding TD has been cancelled. Just ignore
2598                  * the TD.
2599                  */
2600                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2601                         xhci_dbg(xhci,
2602                                  "event_trb is a no-op TRB. Skip it\n");
2603                         goto cleanup;
2604                 }
2605
2606                 /* Now update the urb's actual_length and give back to
2607                  * the core
2608                  */
2609                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2610                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2611                                                  &status);
2612                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2613                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2614                                                  &status);
2615                 else
2616                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2617                                                  ep, &status);
2618
2619 cleanup:
2620                 /*
2621                  * Do not update event ring dequeue pointer if ep->skip is set.
2622                  * Will roll back to continue process missed tds.
2623                  */
2624                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2625                         inc_deq(xhci, xhci->event_ring);
2626                 }
2627
2628                 if (ret) {
2629                         urb = td->urb;
2630                         urb_priv = urb->hcpriv;
2631                         /* Leave the TD around for the reset endpoint function
2632                          * to use(but only if it's not a control endpoint,
2633                          * since we already queued the Set TR dequeue pointer
2634                          * command for stalled control endpoints).
2635                          */
2636                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2637                                 (trb_comp_code != COMP_STALL &&
2638                                         trb_comp_code != COMP_BABBLE))
2639                                 xhci_urb_free_priv(xhci, urb_priv);
2640                         else
2641                                 kfree(urb_priv);
2642
2643                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2644                         if ((urb->actual_length != urb->transfer_buffer_length &&
2645                                                 (urb->transfer_flags &
2646                                                  URB_SHORT_NOT_OK)) ||
2647                                         (status != 0 &&
2648                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2649                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2650                                                 "expected = %d, status = %d\n",
2651                                                 urb, urb->actual_length,
2652                                                 urb->transfer_buffer_length,
2653                                                 status);
2654                         spin_unlock(&xhci->lock);
2655                         /* EHCI, UHCI, and OHCI always unconditionally set the
2656                          * urb->status of an isochronous endpoint to 0.
2657                          */
2658                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2659                                 status = 0;
2660                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2661                         spin_lock(&xhci->lock);
2662                 }
2663
2664         /*
2665          * If ep->skip is set, it means there are missed tds on the
2666          * endpoint ring need to take care of.
2667          * Process them as short transfer until reach the td pointed by
2668          * the event.
2669          */
2670         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2671
2672         return 0;
2673 }
2674
2675 /*
2676  * This function handles all OS-owned events on the event ring.  It may drop
2677  * xhci->lock between event processing (e.g. to pass up port status changes).
2678  * Returns >0 for "possibly more events to process" (caller should call again),
2679  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2680  */
2681 static int xhci_handle_event(struct xhci_hcd *xhci)
2682 {
2683         union xhci_trb *event;
2684         int update_ptrs = 1;
2685         int ret;
2686
2687         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2688                 xhci->error_bitmask |= 1 << 1;
2689                 return 0;
2690         }
2691
2692         event = xhci->event_ring->dequeue;
2693         /* Does the HC or OS own the TRB? */
2694         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2695             xhci->event_ring->cycle_state) {
2696                 xhci->error_bitmask |= 1 << 2;
2697                 return 0;
2698         }
2699
2700         /*
2701          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2702          * speculative reads of the event's flags/data below.
2703          */
2704         rmb();
2705         /* FIXME: Handle more event types. */
2706         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2707         case TRB_TYPE(TRB_COMPLETION):
2708                 handle_cmd_completion(xhci, &event->event_cmd);
2709                 break;
2710         case TRB_TYPE(TRB_PORT_STATUS):
2711                 handle_port_status(xhci, event);
2712                 update_ptrs = 0;
2713                 break;
2714         case TRB_TYPE(TRB_TRANSFER):
2715                 ret = handle_tx_event(xhci, &event->trans_event);
2716                 if (ret < 0)
2717                         xhci->error_bitmask |= 1 << 9;
2718                 else
2719                         update_ptrs = 0;
2720                 break;
2721         case TRB_TYPE(TRB_DEV_NOTE):
2722                 handle_device_notification(xhci, event);
2723                 break;
2724         default:
2725                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2726                     TRB_TYPE(48))
2727                         handle_vendor_event(xhci, event);
2728                 else
2729                         xhci->error_bitmask |= 1 << 3;
2730         }
2731         /* Any of the above functions may drop and re-acquire the lock, so check
2732          * to make sure a watchdog timer didn't mark the host as non-responsive.
2733          */
2734         if (xhci->xhc_state & XHCI_STATE_DYING) {
2735                 xhci_dbg(xhci, "xHCI host dying, returning from "
2736                                 "event handler.\n");
2737                 return 0;
2738         }
2739
2740         if (update_ptrs)
2741                 /* Update SW event ring dequeue pointer */
2742                 inc_deq(xhci, xhci->event_ring);
2743
2744         /* Are there more items on the event ring?  Caller will call us again to
2745          * check.
2746          */
2747         return 1;
2748 }
2749
2750 /*
2751  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2752  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2753  * indicators of an event TRB error, but we check the status *first* to be safe.
2754  */
2755 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2756 {
2757         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2758         u32 status;
2759         u64 temp_64;
2760         union xhci_trb *event_ring_deq;
2761         dma_addr_t deq;
2762
2763         spin_lock(&xhci->lock);
2764         /* Check if the xHC generated the interrupt, or the irq is shared */
2765         status = xhci_readl(xhci, &xhci->op_regs->status);
2766         if (status == 0xffffffff)
2767                 goto hw_died;
2768
2769         if (!(status & STS_EINT)) {
2770                 spin_unlock(&xhci->lock);
2771                 return IRQ_NONE;
2772         }
2773         if (status & STS_FATAL) {
2774                 xhci_warn(xhci, "WARNING: Host System Error\n");
2775                 xhci_halt(xhci);
2776 hw_died:
2777                 spin_unlock(&xhci->lock);
2778                 return -ESHUTDOWN;
2779         }
2780
2781         /*
2782          * Clear the op reg interrupt status first,
2783          * so we can receive interrupts from other MSI-X interrupters.
2784          * Write 1 to clear the interrupt status.
2785          */
2786         status |= STS_EINT;
2787         xhci_writel(xhci, status, &xhci->op_regs->status);
2788         /* FIXME when MSI-X is supported and there are multiple vectors */
2789         /* Clear the MSI-X event interrupt status */
2790
2791         if (hcd->irq) {
2792                 u32 irq_pending;
2793                 /* Acknowledge the PCI interrupt */
2794                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2795                 irq_pending |= IMAN_IP;
2796                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2797         }
2798
2799         if (xhci->xhc_state & XHCI_STATE_DYING) {
2800                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2801                                 "Shouldn't IRQs be disabled?\n");
2802                 /* Clear the event handler busy flag (RW1C);
2803                  * the event ring should be empty.
2804                  */
2805                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2806                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2807                                 &xhci->ir_set->erst_dequeue);
2808                 spin_unlock(&xhci->lock);
2809
2810                 return IRQ_HANDLED;
2811         }
2812
2813         event_ring_deq = xhci->event_ring->dequeue;
2814         /* FIXME this should be a delayed service routine
2815          * that clears the EHB.
2816          */
2817         while (xhci_handle_event(xhci) > 0) {}
2818
2819         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2820         /* If necessary, update the HW's version of the event ring deq ptr. */
2821         if (event_ring_deq != xhci->event_ring->dequeue) {
2822                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2823                                 xhci->event_ring->dequeue);
2824                 if (deq == 0)
2825                         xhci_warn(xhci, "WARN something wrong with SW event "
2826                                         "ring dequeue ptr.\n");
2827                 /* Update HC event ring dequeue pointer */
2828                 temp_64 &= ERST_PTR_MASK;
2829                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2830         }
2831
2832         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2833         temp_64 |= ERST_EHB;
2834         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2835
2836         spin_unlock(&xhci->lock);
2837
2838         return IRQ_HANDLED;
2839 }
2840
2841 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2842 {
2843         return xhci_irq(hcd);
2844 }
2845
2846 /****           Endpoint Ring Operations        ****/
2847
2848 /*
2849  * Generic function for queueing a TRB on a ring.
2850  * The caller must have checked to make sure there's room on the ring.
2851  *
2852  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2853  *                      prepare_transfer()?
2854  */
2855 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2856                 bool more_trbs_coming,
2857                 u32 field1, u32 field2, u32 field3, u32 field4)
2858 {
2859         struct xhci_generic_trb *trb;
2860
2861         trb = &ring->enqueue->generic;
2862         trb->field[0] = cpu_to_le32(field1);
2863         trb->field[1] = cpu_to_le32(field2);
2864         trb->field[2] = cpu_to_le32(field3);
2865         trb->field[3] = cpu_to_le32(field4);
2866         inc_enq(xhci, ring, more_trbs_coming);
2867 }
2868
2869 /*
2870  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2871  * FIXME allocate segments if the ring is full.
2872  */
2873 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2874                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2875 {
2876         unsigned int num_trbs_needed;
2877
2878         /* Make sure the endpoint has been added to xHC schedule */
2879         switch (ep_state) {
2880         case EP_STATE_DISABLED:
2881                 /*
2882                  * USB core changed config/interfaces without notifying us,
2883                  * or hardware is reporting the wrong state.
2884                  */
2885                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2886                 return -ENOENT;
2887         case EP_STATE_ERROR:
2888                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2889                 /* FIXME event handling code for error needs to clear it */
2890                 /* XXX not sure if this should be -ENOENT or not */
2891                 return -EINVAL;
2892         case EP_STATE_HALTED:
2893                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2894         case EP_STATE_STOPPED:
2895         case EP_STATE_RUNNING:
2896                 break;
2897         default:
2898                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2899                 /*
2900                  * FIXME issue Configure Endpoint command to try to get the HC
2901                  * back into a known state.
2902                  */
2903                 return -EINVAL;
2904         }
2905
2906         while (1) {
2907                 if (room_on_ring(xhci, ep_ring, num_trbs))
2908                         break;
2909
2910                 if (ep_ring == xhci->cmd_ring) {
2911                         xhci_err(xhci, "Do not support expand command ring\n");
2912                         return -ENOMEM;
2913                 }
2914
2915                 xhci_dbg(xhci, "ERROR no room on ep ring, "
2916                                         "try ring expansion\n");
2917                 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2918                 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2919                                         mem_flags)) {
2920                         xhci_err(xhci, "Ring expansion failed\n");
2921                         return -ENOMEM;
2922                 }
2923         }
2924
2925         if (enqueue_is_link_trb(ep_ring)) {
2926                 struct xhci_ring *ring = ep_ring;
2927                 union xhci_trb *next;
2928
2929                 next = ring->enqueue;
2930
2931                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2932                         /* If we're not dealing with 0.95 hardware or isoc rings
2933                          * on AMD 0.96 host, clear the chain bit.
2934                          */
2935                         if (!xhci_link_trb_quirk(xhci) &&
2936                                         !(ring->type == TYPE_ISOC &&
2937                                          (xhci->quirks & XHCI_AMD_0x96_HOST)))
2938                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2939                         else
2940                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2941
2942                         wmb();
2943                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2944
2945                         /* Toggle the cycle bit after the last ring segment. */
2946                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2947                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2948                         }
2949                         ring->enq_seg = ring->enq_seg->next;
2950                         ring->enqueue = ring->enq_seg->trbs;
2951                         next = ring->enqueue;
2952                 }
2953         }
2954
2955         return 0;
2956 }
2957
2958 static int prepare_transfer(struct xhci_hcd *xhci,
2959                 struct xhci_virt_device *xdev,
2960                 unsigned int ep_index,
2961                 unsigned int stream_id,
2962                 unsigned int num_trbs,
2963                 struct urb *urb,
2964                 unsigned int td_index,
2965                 gfp_t mem_flags)
2966 {
2967         int ret;
2968         struct urb_priv *urb_priv;
2969         struct xhci_td  *td;
2970         struct xhci_ring *ep_ring;
2971         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2972
2973         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2974         if (!ep_ring) {
2975                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2976                                 stream_id);
2977                 return -EINVAL;
2978         }
2979
2980         ret = prepare_ring(xhci, ep_ring,
2981                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2982                            num_trbs, mem_flags);
2983         if (ret)
2984                 return ret;
2985
2986         urb_priv = urb->hcpriv;
2987         td = urb_priv->td[td_index];
2988
2989         INIT_LIST_HEAD(&td->td_list);
2990         INIT_LIST_HEAD(&td->cancelled_td_list);
2991
2992         if (td_index == 0) {
2993                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2994                 if (unlikely(ret))
2995                         return ret;
2996         }
2997
2998         td->urb = urb;
2999         /* Add this TD to the tail of the endpoint ring's TD list */
3000         list_add_tail(&td->td_list, &ep_ring->td_list);
3001         td->start_seg = ep_ring->enq_seg;
3002         td->first_trb = ep_ring->enqueue;
3003
3004         urb_priv->td[td_index] = td;
3005
3006         return 0;
3007 }
3008
3009 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
3010 {
3011         int num_sgs, num_trbs, running_total, temp, i;
3012         struct scatterlist *sg;
3013
3014         sg = NULL;
3015         num_sgs = urb->num_mapped_sgs;
3016         temp = urb->transfer_buffer_length;
3017
3018         num_trbs = 0;
3019         for_each_sg(urb->sg, sg, num_sgs, i) {
3020                 unsigned int len = sg_dma_len(sg);
3021
3022                 /* Scatter gather list entries may cross 64KB boundaries */
3023                 running_total = TRB_MAX_BUFF_SIZE -
3024                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
3025                 running_total &= TRB_MAX_BUFF_SIZE - 1;
3026                 if (running_total != 0)
3027                         num_trbs++;
3028
3029                 /* How many more 64KB chunks to transfer, how many more TRBs? */
3030                 while (running_total < sg_dma_len(sg) && running_total < temp) {
3031                         num_trbs++;
3032                         running_total += TRB_MAX_BUFF_SIZE;
3033                 }
3034                 len = min_t(int, len, temp);
3035                 temp -= len;
3036                 if (temp == 0)
3037                         break;
3038         }
3039         return num_trbs;
3040 }
3041
3042 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
3043 {
3044         if (num_trbs != 0)
3045                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
3046                                 "TRBs, %d left\n", __func__,
3047                                 urb->ep->desc.bEndpointAddress, num_trbs);
3048         if (running_total != urb->transfer_buffer_length)
3049                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3050                                 "queued %#x (%d), asked for %#x (%d)\n",
3051                                 __func__,
3052                                 urb->ep->desc.bEndpointAddress,
3053                                 running_total, running_total,
3054                                 urb->transfer_buffer_length,
3055                                 urb->transfer_buffer_length);
3056 }
3057
3058 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3059                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3060                 struct xhci_generic_trb *start_trb)
3061 {
3062         /*
3063          * Pass all the TRBs to the hardware at once and make sure this write
3064          * isn't reordered.
3065          */
3066         wmb();
3067         if (start_cycle)
3068                 start_trb->field[3] |= cpu_to_le32(start_cycle);
3069         else
3070                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3071         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3072 }
3073
3074 /*
3075  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
3076  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
3077  * (comprised of sg list entries) can take several service intervals to
3078  * transmit.
3079  */
3080 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3081                 struct urb *urb, int slot_id, unsigned int ep_index)
3082 {
3083         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3084                         xhci->devs[slot_id]->out_ctx, ep_index);
3085         int xhci_interval;
3086         int ep_interval;
3087
3088         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3089         ep_interval = urb->interval;
3090         /* Convert to microframes */
3091         if (urb->dev->speed == USB_SPEED_LOW ||
3092                         urb->dev->speed == USB_SPEED_FULL)
3093                 ep_interval *= 8;
3094         /* FIXME change this to a warning and a suggestion to use the new API
3095          * to set the polling interval (once the API is added).
3096          */
3097         if (xhci_interval != ep_interval) {
3098                 if (printk_ratelimit())
3099                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3100                                         " (%d microframe%s) than xHCI "
3101                                         "(%d microframe%s)\n",
3102                                         ep_interval,
3103                                         ep_interval == 1 ? "" : "s",
3104                                         xhci_interval,
3105                                         xhci_interval == 1 ? "" : "s");
3106                 urb->interval = xhci_interval;
3107                 /* Convert back to frames for LS/FS devices */
3108                 if (urb->dev->speed == USB_SPEED_LOW ||
3109                                 urb->dev->speed == USB_SPEED_FULL)
3110                         urb->interval /= 8;
3111         }
3112         return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3113 }
3114
3115 /*
3116  * The TD size is the number of bytes remaining in the TD (including this TRB),
3117  * right shifted by 10.
3118  * It must fit in bits 21:17, so it can't be bigger than 31.
3119  */
3120 static u32 xhci_td_remainder(unsigned int remainder)
3121 {
3122         u32 max = (1 << (21 - 17 + 1)) - 1;
3123
3124         if ((remainder >> 10) >= max)
3125                 return max << 17;
3126         else
3127                 return (remainder >> 10) << 17;
3128 }
3129
3130 /*
3131  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3132  * packets remaining in the TD (*not* including this TRB).
3133  *
3134  * Total TD packet count = total_packet_count =
3135  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3136  *
3137  * Packets transferred up to and including this TRB = packets_transferred =
3138  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3139  *
3140  * TD size = total_packet_count - packets_transferred
3141  *
3142  * It must fit in bits 21:17, so it can't be bigger than 31.
3143  * The last TRB in a TD must have the TD size set to zero.
3144  */
3145 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3146                 unsigned int total_packet_count, struct urb *urb,
3147                 unsigned int num_trbs_left)
3148 {
3149         int packets_transferred;
3150
3151         /* One TRB with a zero-length data packet. */
3152         if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3153                 return 0;
3154
3155         /* All the TRB queueing functions don't count the current TRB in
3156          * running_total.
3157          */
3158         packets_transferred = (running_total + trb_buff_len) /
3159                 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3160
3161         if ((total_packet_count - packets_transferred) > 31)
3162                 return 31 << 17;
3163         return (total_packet_count - packets_transferred) << 17;
3164 }
3165
3166 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3167                 struct urb *urb, int slot_id, unsigned int ep_index)
3168 {
3169         struct xhci_ring *ep_ring;
3170         unsigned int num_trbs;
3171         struct urb_priv *urb_priv;
3172         struct xhci_td *td;
3173         struct scatterlist *sg;
3174         int num_sgs;
3175         int trb_buff_len, this_sg_len, running_total;
3176         unsigned int total_packet_count;
3177         bool first_trb;
3178         u64 addr;
3179         bool more_trbs_coming;
3180
3181         struct xhci_generic_trb *start_trb;
3182         int start_cycle;
3183
3184         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3185         if (!ep_ring)
3186                 return -EINVAL;
3187
3188         num_trbs = count_sg_trbs_needed(xhci, urb);
3189         num_sgs = urb->num_mapped_sgs;
3190         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3191                         usb_endpoint_maxp(&urb->ep->desc));
3192
3193         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3194                         ep_index, urb->stream_id,
3195                         num_trbs, urb, 0, mem_flags);
3196         if (trb_buff_len < 0)
3197                 return trb_buff_len;
3198
3199         urb_priv = urb->hcpriv;
3200         td = urb_priv->td[0];
3201
3202         /*
3203          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3204          * until we've finished creating all the other TRBs.  The ring's cycle
3205          * state may change as we enqueue the other TRBs, so save it too.
3206          */
3207         start_trb = &ep_ring->enqueue->generic;
3208         start_cycle = ep_ring->cycle_state;
3209
3210         running_total = 0;
3211         /*
3212          * How much data is in the first TRB?
3213          *
3214          * There are three forces at work for TRB buffer pointers and lengths:
3215          * 1. We don't want to walk off the end of this sg-list entry buffer.
3216          * 2. The transfer length that the driver requested may be smaller than
3217          *    the amount of memory allocated for this scatter-gather list.
3218          * 3. TRBs buffers can't cross 64KB boundaries.
3219          */
3220         sg = urb->sg;
3221         addr = (u64) sg_dma_address(sg);
3222         this_sg_len = sg_dma_len(sg);
3223         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3224         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3225         if (trb_buff_len > urb->transfer_buffer_length)
3226                 trb_buff_len = urb->transfer_buffer_length;
3227
3228         first_trb = true;
3229         /* Queue the first TRB, even if it's zero-length */
3230         do {
3231                 u32 field = 0;
3232                 u32 length_field = 0;
3233                 u32 remainder = 0;
3234
3235                 /* Don't change the cycle bit of the first TRB until later */
3236                 if (first_trb) {
3237                         first_trb = false;
3238                         if (start_cycle == 0)
3239                                 field |= 0x1;
3240                 } else
3241                         field |= ep_ring->cycle_state;
3242
3243                 /* Chain all the TRBs together; clear the chain bit in the last
3244                  * TRB to indicate it's the last TRB in the chain.
3245                  */
3246                 if (num_trbs > 1) {
3247                         field |= TRB_CHAIN;
3248                 } else {
3249                         /* FIXME - add check for ZERO_PACKET flag before this */
3250                         td->last_trb = ep_ring->enqueue;
3251                         field |= TRB_IOC;
3252                 }
3253
3254                 /* Only set interrupt on short packet for IN endpoints */
3255                 if (usb_urb_dir_in(urb))
3256                         field |= TRB_ISP;
3257
3258                 if (TRB_MAX_BUFF_SIZE -
3259                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3260                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3261                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3262                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3263                                         (unsigned int) addr + trb_buff_len);
3264                 }
3265
3266                 /* Set the TRB length, TD size, and interrupter fields. */
3267                 if (xhci->hci_version < 0x100) {
3268                         remainder = xhci_td_remainder(
3269                                         urb->transfer_buffer_length -
3270                                         running_total);
3271                 } else {
3272                         remainder = xhci_v1_0_td_remainder(running_total,
3273                                         trb_buff_len, total_packet_count, urb,
3274                                         num_trbs - 1);
3275                 }
3276                 length_field = TRB_LEN(trb_buff_len) |
3277                         remainder |
3278                         TRB_INTR_TARGET(0);
3279
3280                 if (num_trbs > 1)
3281                         more_trbs_coming = true;
3282                 else
3283                         more_trbs_coming = false;
3284                 queue_trb(xhci, ep_ring, more_trbs_coming,
3285                                 lower_32_bits(addr),
3286                                 upper_32_bits(addr),
3287                                 length_field,
3288                                 field | TRB_TYPE(TRB_NORMAL));
3289                 --num_trbs;
3290                 running_total += trb_buff_len;
3291
3292                 /* Calculate length for next transfer --
3293                  * Are we done queueing all the TRBs for this sg entry?
3294                  */
3295                 this_sg_len -= trb_buff_len;
3296                 if (this_sg_len == 0) {
3297                         --num_sgs;
3298                         if (num_sgs == 0)
3299                                 break;
3300                         sg = sg_next(sg);
3301                         addr = (u64) sg_dma_address(sg);
3302                         this_sg_len = sg_dma_len(sg);
3303                 } else {
3304                         addr += trb_buff_len;
3305                 }
3306
3307                 trb_buff_len = TRB_MAX_BUFF_SIZE -
3308                         (addr & (TRB_MAX_BUFF_SIZE - 1));
3309                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3310                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3311                         trb_buff_len =
3312                                 urb->transfer_buffer_length - running_total;
3313         } while (running_total < urb->transfer_buffer_length);
3314
3315         check_trb_math(urb, num_trbs, running_total);
3316         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3317                         start_cycle, start_trb);
3318         return 0;
3319 }
3320
3321 /* This is very similar to what ehci-q.c qtd_fill() does */
3322 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3323                 struct urb *urb, int slot_id, unsigned int ep_index)
3324 {
3325         struct xhci_ring *ep_ring;
3326         struct urb_priv *urb_priv;
3327         struct xhci_td *td;
3328         int num_trbs;
3329         struct xhci_generic_trb *start_trb;
3330         bool first_trb;
3331         bool more_trbs_coming;
3332         int start_cycle;
3333         u32 field, length_field;
3334
3335         int running_total, trb_buff_len, ret;
3336         unsigned int total_packet_count;
3337         u64 addr;
3338
3339         if (urb->num_sgs)
3340                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3341
3342         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3343         if (!ep_ring)
3344                 return -EINVAL;
3345
3346         num_trbs = 0;
3347         /* How much data is (potentially) left before the 64KB boundary? */
3348         running_total = TRB_MAX_BUFF_SIZE -
3349                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3350         running_total &= TRB_MAX_BUFF_SIZE - 1;
3351
3352         /* If there's some data on this 64KB chunk, or we have to send a
3353          * zero-length transfer, we need at least one TRB
3354          */
3355         if (running_total != 0 || urb->transfer_buffer_length == 0)
3356                 num_trbs++;
3357         /* How many more 64KB chunks to transfer, how many more TRBs? */
3358         while (running_total < urb->transfer_buffer_length) {
3359                 num_trbs++;
3360                 running_total += TRB_MAX_BUFF_SIZE;
3361         }
3362         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3363
3364         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3365                         ep_index, urb->stream_id,
3366                         num_trbs, urb, 0, mem_flags);
3367         if (ret < 0)
3368                 return ret;
3369
3370         urb_priv = urb->hcpriv;
3371         td = urb_priv->td[0];
3372
3373         /*
3374          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3375          * until we've finished creating all the other TRBs.  The ring's cycle
3376          * state may change as we enqueue the other TRBs, so save it too.
3377          */
3378         start_trb = &ep_ring->enqueue->generic;
3379         start_cycle = ep_ring->cycle_state;
3380
3381         running_total = 0;
3382         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3383                         usb_endpoint_maxp(&urb->ep->desc));
3384         /* How much data is in the first TRB? */
3385         addr = (u64) urb->transfer_dma;
3386         trb_buff_len = TRB_MAX_BUFF_SIZE -
3387                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3388         if (trb_buff_len > urb->transfer_buffer_length)
3389                 trb_buff_len = urb->transfer_buffer_length;
3390
3391         first_trb = true;
3392
3393         /* Queue the first TRB, even if it's zero-length */
3394         do {
3395                 u32 remainder = 0;
3396                 field = 0;
3397
3398                 /* Don't change the cycle bit of the first TRB until later */
3399                 if (first_trb) {
3400                         first_trb = false;
3401                         if (start_cycle == 0)
3402                                 field |= 0x1;
3403                 } else
3404                         field |= ep_ring->cycle_state;
3405
3406                 /* Chain all the TRBs together; clear the chain bit in the last
3407                  * TRB to indicate it's the last TRB in the chain.
3408                  */
3409                 if (num_trbs > 1) {
3410                         field |= TRB_CHAIN;
3411                 } else {
3412                         /* FIXME - add check for ZERO_PACKET flag before this */
3413                         td->last_trb = ep_ring->enqueue;
3414                         field |= TRB_IOC;
3415                 }
3416
3417                 /* Only set interrupt on short packet for IN endpoints */
3418                 if (usb_urb_dir_in(urb))
3419                         field |= TRB_ISP;
3420
3421                 /* Set the TRB length, TD size, and interrupter fields. */
3422                 if (xhci->hci_version < 0x100) {
3423                         remainder = xhci_td_remainder(
3424                                         urb->transfer_buffer_length -
3425                                         running_total);
3426                 } else {
3427                         remainder = xhci_v1_0_td_remainder(running_total,
3428                                         trb_buff_len, total_packet_count, urb,
3429                                         num_trbs - 1);
3430                 }
3431                 length_field = TRB_LEN(trb_buff_len) |
3432                         remainder |
3433                         TRB_INTR_TARGET(0);
3434
3435                 if (num_trbs > 1)
3436                         more_trbs_coming = true;
3437                 else
3438                         more_trbs_coming = false;
3439                 queue_trb(xhci, ep_ring, more_trbs_coming,
3440                                 lower_32_bits(addr),
3441                                 upper_32_bits(addr),
3442                                 length_field,
3443                                 field | TRB_TYPE(TRB_NORMAL));
3444                 --num_trbs;
3445                 running_total += trb_buff_len;
3446
3447                 /* Calculate length for next transfer */
3448                 addr += trb_buff_len;
3449                 trb_buff_len = urb->transfer_buffer_length - running_total;
3450                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3451                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3452         } while (running_total < urb->transfer_buffer_length);
3453
3454         check_trb_math(urb, num_trbs, running_total);
3455         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3456                         start_cycle, start_trb);
3457         return 0;
3458 }
3459
3460 /* Caller must have locked xhci->lock */
3461 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3462                 struct urb *urb, int slot_id, unsigned int ep_index)
3463 {
3464         struct xhci_ring *ep_ring;
3465         int num_trbs;
3466         int ret;
3467         struct usb_ctrlrequest *setup;
3468         struct xhci_generic_trb *start_trb;
3469         int start_cycle;
3470         u32 field, length_field;
3471         struct urb_priv *urb_priv;
3472         struct xhci_td *td;
3473
3474         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3475         if (!ep_ring)
3476                 return -EINVAL;
3477
3478         /*
3479          * Need to copy setup packet into setup TRB, so we can't use the setup
3480          * DMA address.
3481          */
3482         if (!urb->setup_packet)
3483                 return -EINVAL;
3484
3485         /* 1 TRB for setup, 1 for status */
3486         num_trbs = 2;
3487         /*
3488          * Don't need to check if we need additional event data and normal TRBs,
3489          * since data in control transfers will never get bigger than 16MB
3490          * XXX: can we get a buffer that crosses 64KB boundaries?
3491          */
3492         if (urb->transfer_buffer_length > 0)
3493                 num_trbs++;
3494         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3495                         ep_index, urb->stream_id,
3496                         num_trbs, urb, 0, mem_flags);
3497         if (ret < 0)
3498                 return ret;
3499
3500         urb_priv = urb->hcpriv;
3501         td = urb_priv->td[0];
3502
3503         /*
3504          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3505          * until we've finished creating all the other TRBs.  The ring's cycle
3506          * state may change as we enqueue the other TRBs, so save it too.
3507          */
3508         start_trb = &ep_ring->enqueue->generic;
3509         start_cycle = ep_ring->cycle_state;
3510
3511         /* Queue setup TRB - see section 6.4.1.2.1 */
3512         /* FIXME better way to translate setup_packet into two u32 fields? */
3513         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3514         field = 0;
3515         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3516         if (start_cycle == 0)
3517                 field |= 0x1;
3518
3519         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3520         if (xhci->hci_version == 0x100) {
3521                 if (urb->transfer_buffer_length > 0) {
3522                         if (setup->bRequestType & USB_DIR_IN)
3523                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3524                         else
3525                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3526                 }
3527         }
3528
3529         queue_trb(xhci, ep_ring, true,
3530                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3531                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3532                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3533                   /* Immediate data in pointer */
3534                   field);
3535
3536         /* If there's data, queue data TRBs */
3537         /* Only set interrupt on short packet for IN endpoints */
3538         if (usb_urb_dir_in(urb))
3539                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3540         else
3541                 field = TRB_TYPE(TRB_DATA);
3542
3543         length_field = TRB_LEN(urb->transfer_buffer_length) |
3544                 xhci_td_remainder(urb->transfer_buffer_length) |
3545                 TRB_INTR_TARGET(0);
3546         if (urb->transfer_buffer_length > 0) {
3547                 if (setup->bRequestType & USB_DIR_IN)
3548                         field |= TRB_DIR_IN;
3549                 queue_trb(xhci, ep_ring, true,
3550                                 lower_32_bits(urb->transfer_dma),
3551                                 upper_32_bits(urb->transfer_dma),
3552                                 length_field,
3553                                 field | ep_ring->cycle_state);
3554         }
3555
3556         /* Save the DMA address of the last TRB in the TD */
3557         td->last_trb = ep_ring->enqueue;
3558
3559         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3560         /* If the device sent data, the status stage is an OUT transfer */
3561         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3562                 field = 0;
3563         else
3564                 field = TRB_DIR_IN;
3565         queue_trb(xhci, ep_ring, false,
3566                         0,
3567                         0,
3568                         TRB_INTR_TARGET(0),
3569                         /* Event on completion */
3570                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3571
3572         giveback_first_trb(xhci, slot_id, ep_index, 0,
3573                         start_cycle, start_trb);
3574         return 0;
3575 }
3576
3577 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3578                 struct urb *urb, int i)
3579 {
3580         int num_trbs = 0;
3581         u64 addr, td_len;
3582
3583         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3584         td_len = urb->iso_frame_desc[i].length;
3585
3586         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3587                         TRB_MAX_BUFF_SIZE);
3588         if (num_trbs == 0)
3589                 num_trbs++;
3590
3591         return num_trbs;
3592 }
3593
3594 /*
3595  * The transfer burst count field of the isochronous TRB defines the number of
3596  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3597  * devices can burst up to bMaxBurst number of packets per service interval.
3598  * This field is zero based, meaning a value of zero in the field means one
3599  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3600  * zero.  Only xHCI 1.0 host controllers support this field.
3601  */
3602 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3603                 struct usb_device *udev,
3604                 struct urb *urb, unsigned int total_packet_count)
3605 {
3606         unsigned int max_burst;
3607
3608         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3609                 return 0;
3610
3611         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3612         return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3613 }
3614
3615 /*
3616  * Returns the number of packets in the last "burst" of packets.  This field is
3617  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3618  * the last burst packet count is equal to the total number of packets in the
3619  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3620  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3621  * contain 1 to (bMaxBurst + 1) packets.
3622  */
3623 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3624                 struct usb_device *udev,
3625                 struct urb *urb, unsigned int total_packet_count)
3626 {
3627         unsigned int max_burst;
3628         unsigned int residue;
3629
3630         if (xhci->hci_version < 0x100)
3631                 return 0;
3632
3633         switch (udev->speed) {
3634         case USB_SPEED_SUPER:
3635                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3636                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3637                 residue = total_packet_count % (max_burst + 1);
3638                 /* If residue is zero, the last burst contains (max_burst + 1)
3639                  * number of packets, but the TLBPC field is zero-based.
3640                  */
3641                 if (residue == 0)
3642                         return max_burst;
3643                 return residue - 1;
3644         default:
3645                 if (total_packet_count == 0)
3646                         return 0;
3647                 return total_packet_count - 1;
3648         }
3649 }
3650
3651 /* This is for isoc transfer */
3652 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3653                 struct urb *urb, int slot_id, unsigned int ep_index)
3654 {
3655         struct xhci_ring *ep_ring;
3656         struct urb_priv *urb_priv;
3657         struct xhci_td *td;
3658         int num_tds, trbs_per_td;
3659         struct xhci_generic_trb *start_trb;
3660         bool first_trb;
3661         int start_cycle;
3662         u32 field, length_field;
3663         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3664         u64 start_addr, addr;
3665         int i, j;
3666         bool more_trbs_coming;
3667
3668         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3669
3670         num_tds = urb->number_of_packets;
3671         if (num_tds < 1) {
3672                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3673                 return -EINVAL;
3674         }
3675
3676         start_addr = (u64) urb->transfer_dma;
3677         start_trb = &ep_ring->enqueue->generic;
3678         start_cycle = ep_ring->cycle_state;
3679
3680         urb_priv = urb->hcpriv;
3681         /* Queue the first TRB, even if it's zero-length */
3682         for (i = 0; i < num_tds; i++) {
3683                 unsigned int total_packet_count;
3684                 unsigned int burst_count;
3685                 unsigned int residue;
3686
3687                 first_trb = true;
3688                 running_total = 0;
3689                 addr = start_addr + urb->iso_frame_desc[i].offset;
3690                 td_len = urb->iso_frame_desc[i].length;
3691                 td_remain_len = td_len;
3692                 total_packet_count = DIV_ROUND_UP(td_len,
3693                                 GET_MAX_PACKET(
3694                                         usb_endpoint_maxp(&urb->ep->desc)));
3695                 /* A zero-length transfer still involves at least one packet. */
3696                 if (total_packet_count == 0)
3697                         total_packet_count++;
3698                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3699                                 total_packet_count);
3700                 residue = xhci_get_last_burst_packet_count(xhci,
3701                                 urb->dev, urb, total_packet_count);
3702
3703                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3704
3705                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3706                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3707                 if (ret < 0) {
3708                         if (i == 0)
3709                                 return ret;
3710                         goto cleanup;
3711                 }
3712
3713                 td = urb_priv->td[i];
3714                 for (j = 0; j < trbs_per_td; j++) {
3715                         u32 remainder = 0;
3716                         field = 0;
3717
3718                         if (first_trb) {
3719                                 field = TRB_TBC(burst_count) |
3720                                         TRB_TLBPC(residue);
3721                                 /* Queue the isoc TRB */
3722                                 field |= TRB_TYPE(TRB_ISOC);
3723                                 /* Assume URB_ISO_ASAP is set */
3724                                 field |= TRB_SIA;
3725                                 if (i == 0) {
3726                                         if (start_cycle == 0)
3727                                                 field |= 0x1;
3728                                 } else
3729                                         field |= ep_ring->cycle_state;
3730                                 first_trb = false;
3731                         } else {
3732                                 /* Queue other normal TRBs */
3733                                 field |= TRB_TYPE(TRB_NORMAL);
3734                                 field |= ep_ring->cycle_state;
3735                         }
3736
3737                         /* Only set interrupt on short packet for IN EPs */
3738                         if (usb_urb_dir_in(urb))
3739                                 field |= TRB_ISP;
3740
3741                         /* Chain all the TRBs together; clear the chain bit in
3742                          * the last TRB to indicate it's the last TRB in the
3743                          * chain.
3744                          */
3745                         if (j < trbs_per_td - 1) {
3746                                 field |= TRB_CHAIN;
3747                                 more_trbs_coming = true;
3748                         } else {
3749                                 td->last_trb = ep_ring->enqueue;
3750                                 field |= TRB_IOC;
3751                                 if (xhci->hci_version == 0x100 &&
3752                                                 !(xhci->quirks &
3753                                                         XHCI_AVOID_BEI)) {
3754                                         /* Set BEI bit except for the last td */
3755                                         if (i < num_tds - 1)
3756                                                 field |= TRB_BEI;
3757                                 }
3758                                 more_trbs_coming = false;
3759                         }
3760
3761                         /* Calculate TRB length */
3762                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3763                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3764                         if (trb_buff_len > td_remain_len)
3765                                 trb_buff_len = td_remain_len;
3766
3767                         /* Set the TRB length, TD size, & interrupter fields. */
3768                         if (xhci->hci_version < 0x100) {
3769                                 remainder = xhci_td_remainder(
3770                                                 td_len - running_total);
3771                         } else {
3772                                 remainder = xhci_v1_0_td_remainder(
3773                                                 running_total, trb_buff_len,
3774                                                 total_packet_count, urb,
3775                                                 (trbs_per_td - j - 1));
3776                         }
3777                         length_field = TRB_LEN(trb_buff_len) |
3778                                 remainder |
3779                                 TRB_INTR_TARGET(0);
3780
3781                         queue_trb(xhci, ep_ring, more_trbs_coming,
3782                                 lower_32_bits(addr),
3783                                 upper_32_bits(addr),
3784                                 length_field,
3785                                 field);
3786                         running_total += trb_buff_len;
3787
3788                         addr += trb_buff_len;
3789                         td_remain_len -= trb_buff_len;
3790                 }
3791
3792                 /* Check TD length */
3793                 if (running_total != td_len) {
3794                         xhci_err(xhci, "ISOC TD length unmatch\n");
3795                         ret = -EINVAL;
3796                         goto cleanup;
3797                 }
3798         }
3799
3800         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3801                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3802                         usb_amd_quirk_pll_disable();
3803         }
3804         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3805
3806         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3807                         start_cycle, start_trb);
3808         return 0;
3809 cleanup:
3810         /* Clean up a partially enqueued isoc transfer. */
3811
3812         for (i--; i >= 0; i--)
3813                 list_del_init(&urb_priv->td[i]->td_list);
3814
3815         /* Use the first TD as a temporary variable to turn the TDs we've queued
3816          * into No-ops with a software-owned cycle bit. That way the hardware
3817          * won't accidentally start executing bogus TDs when we partially
3818          * overwrite them.  td->first_trb and td->start_seg are already set.
3819          */
3820         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3821         /* Every TRB except the first & last will have its cycle bit flipped. */
3822         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3823
3824         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3825         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3826         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3827         ep_ring->cycle_state = start_cycle;
3828         ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3829         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3830         return ret;
3831 }
3832
3833 /*
3834  * Check transfer ring to guarantee there is enough room for the urb.
3835  * Update ISO URB start_frame and interval.
3836  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3837  * update the urb->start_frame by now.
3838  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3839  */
3840 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3841                 struct urb *urb, int slot_id, unsigned int ep_index)
3842 {
3843         struct xhci_virt_device *xdev;
3844         struct xhci_ring *ep_ring;
3845         struct xhci_ep_ctx *ep_ctx;
3846         int start_frame;
3847         int xhci_interval;
3848         int ep_interval;
3849         int num_tds, num_trbs, i;
3850         int ret;
3851
3852         xdev = xhci->devs[slot_id];
3853         ep_ring = xdev->eps[ep_index].ring;
3854         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3855
3856         num_trbs = 0;
3857         num_tds = urb->number_of_packets;
3858         for (i = 0; i < num_tds; i++)
3859                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3860
3861         /* Check the ring to guarantee there is enough room for the whole urb.
3862          * Do not insert any td of the urb to the ring if the check failed.
3863          */
3864         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3865                            num_trbs, mem_flags);
3866         if (ret)
3867                 return ret;
3868
3869         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3870         start_frame &= 0x3fff;
3871
3872         urb->start_frame = start_frame;
3873         if (urb->dev->speed == USB_SPEED_LOW ||
3874                         urb->dev->speed == USB_SPEED_FULL)
3875                 urb->start_frame >>= 3;
3876
3877         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3878         ep_interval = urb->interval;
3879         /* Convert to microframes */
3880         if (urb->dev->speed == USB_SPEED_LOW ||
3881                         urb->dev->speed == USB_SPEED_FULL)
3882                 ep_interval *= 8;
3883         /* FIXME change this to a warning and a suggestion to use the new API
3884          * to set the polling interval (once the API is added).
3885          */
3886         if (xhci_interval != ep_interval) {
3887                 if (printk_ratelimit())
3888                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3889                                         " (%d microframe%s) than xHCI "
3890                                         "(%d microframe%s)\n",
3891                                         ep_interval,
3892                                         ep_interval == 1 ? "" : "s",
3893                                         xhci_interval,
3894                                         xhci_interval == 1 ? "" : "s");
3895                 urb->interval = xhci_interval;
3896                 /* Convert back to frames for LS/FS devices */
3897                 if (urb->dev->speed == USB_SPEED_LOW ||
3898                                 urb->dev->speed == USB_SPEED_FULL)
3899                         urb->interval /= 8;
3900         }
3901         ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3902
3903         return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3904 }
3905
3906 /****           Command Ring Operations         ****/
3907
3908 /* Generic function for queueing a command TRB on the command ring.
3909  * Check to make sure there's room on the command ring for one command TRB.
3910  * Also check that there's room reserved for commands that must not fail.
3911  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3912  * then only check for the number of reserved spots.
3913  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3914  * because the command event handler may want to resubmit a failed command.
3915  */
3916 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3917                 u32 field3, u32 field4, bool command_must_succeed)
3918 {
3919         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3920         int ret;
3921
3922         if (!command_must_succeed)
3923                 reserved_trbs++;
3924
3925         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3926                         reserved_trbs, GFP_ATOMIC);
3927         if (ret < 0) {
3928                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3929                 if (command_must_succeed)
3930                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3931                                         "unfailable commands failed.\n");
3932                 return ret;
3933         }
3934         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3935                         field4 | xhci->cmd_ring->cycle_state);
3936         return 0;
3937 }
3938
3939 /* Queue a slot enable or disable request on the command ring */
3940 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3941 {
3942         return queue_command(xhci, 0, 0, 0,
3943                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3944 }
3945
3946 /* Queue an address device command TRB */
3947 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3948                 u32 slot_id)
3949 {
3950         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3951                         upper_32_bits(in_ctx_ptr), 0,
3952                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3953                         false);
3954 }
3955
3956 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3957                 u32 field1, u32 field2, u32 field3, u32 field4)
3958 {
3959         return queue_command(xhci, field1, field2, field3, field4, false);
3960 }
3961
3962 /* Queue a reset device command TRB */
3963 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3964 {
3965         return queue_command(xhci, 0, 0, 0,
3966                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3967                         false);
3968 }
3969
3970 /* Queue a configure endpoint command TRB */
3971 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3972                 u32 slot_id, bool command_must_succeed)
3973 {
3974         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3975                         upper_32_bits(in_ctx_ptr), 0,
3976                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3977                         command_must_succeed);
3978 }
3979
3980 /* Queue an evaluate context command TRB */
3981 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3982                 u32 slot_id, bool command_must_succeed)
3983 {
3984         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3985                         upper_32_bits(in_ctx_ptr), 0,
3986                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3987                         command_must_succeed);
3988 }
3989
3990 /*
3991  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3992  * activity on an endpoint that is about to be suspended.
3993  */
3994 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3995                 unsigned int ep_index, int suspend)
3996 {
3997         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3998         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3999         u32 type = TRB_TYPE(TRB_STOP_RING);
4000         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4001
4002         return queue_command(xhci, 0, 0, 0,
4003                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
4004 }
4005
4006 /* Set Transfer Ring Dequeue Pointer command.
4007  * This should not be used for endpoints that have streams enabled.
4008  */
4009 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
4010                 unsigned int ep_index, unsigned int stream_id,
4011                 struct xhci_segment *deq_seg,
4012                 union xhci_trb *deq_ptr, u32 cycle_state)
4013 {
4014         dma_addr_t addr;
4015         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4016         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4017         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
4018         u32 type = TRB_TYPE(TRB_SET_DEQ);
4019         struct xhci_virt_ep *ep;
4020
4021         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
4022         if (addr == 0) {
4023                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4024                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4025                                 deq_seg, deq_ptr);
4026                 return 0;
4027         }
4028         ep = &xhci->devs[slot_id]->eps[ep_index];
4029         if ((ep->ep_state & SET_DEQ_PENDING)) {
4030                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4031                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4032                 return 0;
4033         }
4034         ep->queued_deq_seg = deq_seg;
4035         ep->queued_deq_ptr = deq_ptr;
4036         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
4037                         upper_32_bits(addr), trb_stream_id,
4038                         trb_slot_id | trb_ep_index | type, false);
4039 }
4040
4041 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
4042                 unsigned int ep_index)
4043 {
4044         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4045         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4046         u32 type = TRB_TYPE(TRB_RESET_EP);
4047
4048         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
4049                         false);
4050 }