81f0389fcc94bfe97c82ab4e7e2937c5fa651492
[linux-3.10.git] / drivers / usb / gadget / omap_udc.c
1 /*
2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
3  *
4  * Copyright (C) 2004 Texas Instruments, Inc.
5  * Copyright (C) 2004-2005 David Brownell
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20  */
21
22 #undef  DEBUG
23 #undef  VERBOSE
24
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/ioport.h>
28 #include <linux/types.h>
29 #include <linux/errno.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <linux/init.h>
34 #include <linux/timer.h>
35 #include <linux/list.h>
36 #include <linux/interrupt.h>
37 #include <linux/proc_fs.h>
38 #include <linux/mm.h>
39 #include <linux/moduleparam.h>
40 #include <linux/platform_device.h>
41 #include <linux/usb_ch9.h>
42 #include <linux/usb_gadget.h>
43 #include <linux/usb/otg.h>
44 #include <linux/dma-mapping.h>
45
46 #include <asm/byteorder.h>
47 #include <asm/io.h>
48 #include <asm/irq.h>
49 #include <asm/system.h>
50 #include <asm/unaligned.h>
51 #include <asm/mach-types.h>
52
53 #include <asm/arch/dma.h>
54 #include <asm/arch/usb.h>
55
56 #include "omap_udc.h"
57
58 #undef  USB_TRACE
59
60 /* bulk DMA seems to be behaving for both IN and OUT */
61 #define USE_DMA
62
63 /* ISO too */
64 #define USE_ISO
65
66 #define DRIVER_DESC     "OMAP UDC driver"
67 #define DRIVER_VERSION  "4 October 2004"
68
69 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
70
71
72 /*
73  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
74  * D+ pullup to allow enumeration.  That's too early for the gadget
75  * framework to use from usb_endpoint_enable(), which happens after
76  * enumeration as part of activating an interface.  (But if we add an
77  * optional new "UDC not yet running" state to the gadget driver model,
78  * even just during driver binding, the endpoint autoconfig logic is the
79  * natural spot to manufacture new endpoints.)
80  *
81  * So instead of using endpoint enable calls to control the hardware setup,
82  * this driver defines a "fifo mode" parameter.  It's used during driver
83  * initialization to choose among a set of pre-defined endpoint configs.
84  * See omap_udc_setup() for available modes, or to add others.  That code
85  * lives in an init section, so use this driver as a module if you need
86  * to change the fifo mode after the kernel boots.
87  *
88  * Gadget drivers normally ignore endpoints they don't care about, and
89  * won't include them in configuration descriptors.  That means only
90  * misbehaving hosts would even notice they exist.
91  */
92 #ifdef  USE_ISO
93 static unsigned fifo_mode = 3;
94 #else
95 static unsigned fifo_mode = 0;
96 #endif
97
98 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
99  * boot parameter "omap_udc:fifo_mode=42"
100  */
101 module_param (fifo_mode, uint, 0);
102 MODULE_PARM_DESC (fifo_mode, "endpoint setup (0 == default)");
103
104 #ifdef  USE_DMA
105 static unsigned use_dma = 1;
106
107 /* "modprobe omap_udc use_dma=y", or else as a kernel
108  * boot parameter "omap_udc:use_dma=y"
109  */
110 module_param (use_dma, bool, 0);
111 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
112 #else   /* !USE_DMA */
113
114 /* save a bit of code */
115 #define use_dma         0
116 #endif  /* !USE_DMA */
117
118
119 static const char driver_name [] = "omap_udc";
120 static const char driver_desc [] = DRIVER_DESC;
121
122 /*-------------------------------------------------------------------------*/
123
124 /* there's a notion of "current endpoint" for modifying endpoint
125  * state, and PIO access to its FIFO.  
126  */
127
128 static void use_ep(struct omap_ep *ep, u16 select)
129 {
130         u16     num = ep->bEndpointAddress & 0x0f;
131
132         if (ep->bEndpointAddress & USB_DIR_IN)
133                 num |= UDC_EP_DIR;
134         UDC_EP_NUM_REG = num | select;
135         /* when select, MUST deselect later !! */
136 }
137
138 static inline void deselect_ep(void)
139 {
140         UDC_EP_NUM_REG &= ~UDC_EP_SEL;
141         /* 6 wait states before TX will happen */
142 }
143
144 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
145
146 /*-------------------------------------------------------------------------*/
147
148 static int omap_ep_enable(struct usb_ep *_ep,
149                 const struct usb_endpoint_descriptor *desc)
150 {
151         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
152         struct omap_udc *udc;
153         unsigned long   flags;
154         u16             maxp;
155
156         /* catch various bogus parameters */
157         if (!_ep || !desc || ep->desc
158                         || desc->bDescriptorType != USB_DT_ENDPOINT
159                         || ep->bEndpointAddress != desc->bEndpointAddress
160                         || ep->maxpacket < le16_to_cpu
161                                                 (desc->wMaxPacketSize)) {
162                 DBG("%s, bad ep or descriptor\n", __FUNCTION__);
163                 return -EINVAL;
164         }
165         maxp = le16_to_cpu (desc->wMaxPacketSize);
166         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
167                                 && maxp != ep->maxpacket)
168                         || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
169                         || !desc->wMaxPacketSize) {
170                 DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
171                 return -ERANGE;
172         }
173
174 #ifdef  USE_ISO
175         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
176                                 && desc->bInterval != 1)) {
177                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
178                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
179                                 1 << (desc->bInterval - 1));
180                 return -EDOM;
181         }
182 #else
183         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
184                 DBG("%s, ISO nyet\n", _ep->name);
185                 return -EDOM;
186         }
187 #endif
188
189         /* xfer types must match, except that interrupt ~= bulk */
190         if (ep->bmAttributes != desc->bmAttributes
191                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
192                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
193                 DBG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
194                 return -EINVAL;
195         }
196
197         udc = ep->udc;
198         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
199                 DBG("%s, bogus device state\n", __FUNCTION__);
200                 return -ESHUTDOWN;
201         }
202
203         spin_lock_irqsave(&udc->lock, flags);
204
205         ep->desc = desc;
206         ep->irqs = 0;
207         ep->stopped = 0;
208         ep->ep.maxpacket = maxp;
209
210         /* set endpoint to initial state */
211         ep->dma_channel = 0;
212         ep->has_dma = 0;
213         ep->lch = -1;
214         use_ep(ep, UDC_EP_SEL);
215         UDC_CTRL_REG = udc->clr_halt;
216         ep->ackwait = 0;
217         deselect_ep();
218
219         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
220                 list_add(&ep->iso, &udc->iso);
221
222         /* maybe assign a DMA channel to this endpoint */
223         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
224                 /* FIXME ISO can dma, but prefers first channel */
225                 dma_channel_claim(ep, 0);
226
227         /* PIO OUT may RX packets */
228         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
229                         && !ep->has_dma
230                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
231                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
232                 ep->ackwait = 1 + ep->double_buf;
233         }
234
235         spin_unlock_irqrestore(&udc->lock, flags);
236         VDBG("%s enabled\n", _ep->name);
237         return 0;
238 }
239
240 static void nuke(struct omap_ep *, int status);
241
242 static int omap_ep_disable(struct usb_ep *_ep)
243 {
244         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
245         unsigned long   flags;
246
247         if (!_ep || !ep->desc) {
248                 DBG("%s, %s not enabled\n", __FUNCTION__,
249                         _ep ? ep->ep.name : NULL);
250                 return -EINVAL;
251         }
252
253         spin_lock_irqsave(&ep->udc->lock, flags);
254         ep->desc = NULL;
255         nuke (ep, -ESHUTDOWN);
256         ep->ep.maxpacket = ep->maxpacket;
257         ep->has_dma = 0;
258         UDC_CTRL_REG = UDC_SET_HALT;
259         list_del_init(&ep->iso);
260         del_timer(&ep->timer);
261
262         spin_unlock_irqrestore(&ep->udc->lock, flags);
263
264         VDBG("%s disabled\n", _ep->name);
265         return 0;
266 }
267
268 /*-------------------------------------------------------------------------*/
269
270 static struct usb_request *
271 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
272 {
273         struct omap_req *req;
274
275         req = kzalloc(sizeof(*req), gfp_flags);
276         if (req) {
277                 req->req.dma = DMA_ADDR_INVALID;
278                 INIT_LIST_HEAD (&req->queue);
279         }
280         return &req->req;
281 }
282
283 static void
284 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
285 {
286         struct omap_req *req = container_of(_req, struct omap_req, req);
287
288         if (_req)
289                 kfree (req);
290 }
291
292 /*-------------------------------------------------------------------------*/
293
294 static void *
295 omap_alloc_buffer(
296         struct usb_ep   *_ep,
297         unsigned        bytes,
298         dma_addr_t      *dma,
299         gfp_t           gfp_flags
300 )
301 {
302         void            *retval;
303         struct omap_ep  *ep;
304
305         ep = container_of(_ep, struct omap_ep, ep);
306         if (use_dma && ep->has_dma) {
307                 static int      warned;
308                 if (!warned && bytes < PAGE_SIZE) {
309                         dev_warn(ep->udc->gadget.dev.parent,
310                                 "using dma_alloc_coherent for "
311                                 "small allocations wastes memory\n");
312                         warned++;
313                 }
314                 return dma_alloc_coherent(ep->udc->gadget.dev.parent,
315                                 bytes, dma, gfp_flags);
316         }
317
318         retval = kmalloc(bytes, gfp_flags);
319         if (retval)
320                 *dma = virt_to_phys(retval);
321         return retval;
322 }
323
324 static void omap_free_buffer(
325         struct usb_ep   *_ep,
326         void            *buf,
327         dma_addr_t      dma,
328         unsigned        bytes
329 )
330 {
331         struct omap_ep  *ep;
332
333         ep = container_of(_ep, struct omap_ep, ep);
334         if (use_dma && _ep && ep->has_dma)
335                 dma_free_coherent(ep->udc->gadget.dev.parent, bytes, buf, dma);
336         else
337                 kfree (buf);
338 }
339
340 /*-------------------------------------------------------------------------*/
341
342 static void
343 done(struct omap_ep *ep, struct omap_req *req, int status)
344 {
345         unsigned                stopped = ep->stopped;
346
347         list_del_init(&req->queue);
348
349         if (req->req.status == -EINPROGRESS)
350                 req->req.status = status;
351         else
352                 status = req->req.status;
353
354         if (use_dma && ep->has_dma) {
355                 if (req->mapped) {
356                         dma_unmap_single(ep->udc->gadget.dev.parent,
357                                 req->req.dma, req->req.length,
358                                 (ep->bEndpointAddress & USB_DIR_IN)
359                                         ? DMA_TO_DEVICE
360                                         : DMA_FROM_DEVICE);
361                         req->req.dma = DMA_ADDR_INVALID;
362                         req->mapped = 0;
363                 } else
364                         dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
365                                 req->req.dma, req->req.length,
366                                 (ep->bEndpointAddress & USB_DIR_IN)
367                                         ? DMA_TO_DEVICE
368                                         : DMA_FROM_DEVICE);
369         }
370
371 #ifndef USB_TRACE
372         if (status && status != -ESHUTDOWN)
373 #endif
374                 VDBG("complete %s req %p stat %d len %u/%u\n",
375                         ep->ep.name, &req->req, status,
376                         req->req.actual, req->req.length);
377
378         /* don't modify queue heads during completion callback */
379         ep->stopped = 1;
380         spin_unlock(&ep->udc->lock);
381         req->req.complete(&ep->ep, &req->req);
382         spin_lock(&ep->udc->lock);
383         ep->stopped = stopped;
384 }
385
386 /*-------------------------------------------------------------------------*/
387
388 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
389 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
390
391 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
392 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
393
394 static inline int 
395 write_packet(u8 *buf, struct omap_req *req, unsigned max)
396 {
397         unsigned        len;
398         u16             *wp;
399
400         len = min(req->req.length - req->req.actual, max);
401         req->req.actual += len;
402
403         max = len;
404         if (likely((((int)buf) & 1) == 0)) {
405                 wp = (u16 *)buf;
406                 while (max >= 2) {
407                         UDC_DATA_REG = *wp++;
408                         max -= 2;
409                 }
410                 buf = (u8 *)wp;
411         }
412         while (max--)
413                 *(volatile u8 *)&UDC_DATA_REG = *buf++;
414         return len;
415 }
416
417 // FIXME change r/w fifo calling convention
418
419
420 // return:  0 = still running, 1 = completed, negative = errno
421 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
422 {
423         u8              *buf;
424         unsigned        count;
425         int             is_last;
426         u16             ep_stat;
427
428         buf = req->req.buf + req->req.actual;
429         prefetch(buf);
430
431         /* PIO-IN isn't double buffered except for iso */
432         ep_stat = UDC_STAT_FLG_REG;
433         if (ep_stat & UDC_FIFO_UNWRITABLE)
434                 return 0;
435
436         count = ep->ep.maxpacket;
437         count = write_packet(buf, req, count);
438         UDC_CTRL_REG = UDC_SET_FIFO_EN;
439         ep->ackwait = 1;
440
441         /* last packet is often short (sometimes a zlp) */
442         if (count != ep->ep.maxpacket)
443                 is_last = 1;
444         else if (req->req.length == req->req.actual
445                         && !req->req.zero)
446                 is_last = 1;
447         else
448                 is_last = 0;
449
450         /* NOTE:  requests complete when all IN data is in a
451          * FIFO (or sometimes later, if a zlp was needed).
452          * Use usb_ep_fifo_status() where needed.
453          */
454         if (is_last)
455                 done(ep, req, 0);
456         return is_last;
457 }
458
459 static inline int 
460 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
461 {
462         unsigned        len;
463         u16             *wp;
464
465         len = min(req->req.length - req->req.actual, avail);
466         req->req.actual += len;
467         avail = len;
468
469         if (likely((((int)buf) & 1) == 0)) {
470                 wp = (u16 *)buf;
471                 while (avail >= 2) {
472                         *wp++ = UDC_DATA_REG;
473                         avail -= 2;
474                 }
475                 buf = (u8 *)wp;
476         }
477         while (avail--)
478                 *buf++ = *(volatile u8 *)&UDC_DATA_REG;
479         return len;
480 }
481
482 // return:  0 = still running, 1 = queue empty, negative = errno
483 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
484 {
485         u8              *buf;
486         unsigned        count, avail;
487         int             is_last;
488
489         buf = req->req.buf + req->req.actual;
490         prefetchw(buf);
491
492         for (;;) {
493                 u16     ep_stat = UDC_STAT_FLG_REG;
494
495                 is_last = 0;
496                 if (ep_stat & FIFO_EMPTY) {
497                         if (!ep->double_buf)
498                                 break;
499                         ep->fnf = 1;
500                 }
501                 if (ep_stat & UDC_EP_HALTED)
502                         break;
503
504                 if (ep_stat & UDC_FIFO_FULL)
505                         avail = ep->ep.maxpacket;
506                 else  {
507                         avail = UDC_RXFSTAT_REG;
508                         ep->fnf = ep->double_buf;
509                 }
510                 count = read_packet(buf, req, avail);
511
512                 /* partial packet reads may not be errors */
513                 if (count < ep->ep.maxpacket) {
514                         is_last = 1;
515                         /* overflowed this request?  flush extra data */
516                         if (count != avail) {
517                                 req->req.status = -EOVERFLOW;
518                                 avail -= count;
519                                 while (avail--)
520                                         (void) *(volatile u8 *)&UDC_DATA_REG;
521                         }
522                 } else if (req->req.length == req->req.actual)
523                         is_last = 1;
524                 else
525                         is_last = 0;
526
527                 if (!ep->bEndpointAddress)
528                         break;
529                 if (is_last)
530                         done(ep, req, 0);
531                 break;
532         }
533         return is_last;
534 }
535
536 /*-------------------------------------------------------------------------*/
537
538 static inline dma_addr_t dma_csac(unsigned lch)
539 {
540         dma_addr_t      csac;
541
542         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
543          * read before the DMA controller finished disabling the channel.
544          */
545         csac = omap_readw(OMAP_DMA_CSAC(lch));
546         if (csac == 0)
547                 csac = omap_readw(OMAP_DMA_CSAC(lch));
548         return csac;
549 }
550
551 static inline dma_addr_t dma_cdac(unsigned lch)
552 {
553         dma_addr_t      cdac;
554
555         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
556          * read before the DMA controller finished disabling the channel.
557          */
558         cdac = omap_readw(OMAP_DMA_CDAC(lch));
559         if (cdac == 0)
560                 cdac = omap_readw(OMAP_DMA_CDAC(lch));
561         return cdac;
562 }
563
564 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
565 {
566         dma_addr_t      end;
567
568         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
569          * the last transfer's bytecount by more than a FIFO's worth.
570          */
571         if (cpu_is_omap15xx())
572                 return 0;
573
574         end = dma_csac(ep->lch);
575         if (end == ep->dma_counter)
576                 return 0;
577
578         end |= start & (0xffff << 16);
579         if (end < start)
580                 end += 0x10000;
581         return end - start;
582 }
583
584 #define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
585                 ? omap_readw(OMAP_DMA_CSAC(x)) /* really: CPC */ \
586                 : dma_cdac(x))
587
588 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
589 {
590         dma_addr_t      end;
591
592         end = DMA_DEST_LAST(ep->lch);
593         if (end == ep->dma_counter)
594                 return 0;
595
596         end |= start & (0xffff << 16);
597         if (cpu_is_omap15xx())
598                 end++;
599         if (end < start)
600                 end += 0x10000;
601         return end - start;
602 }
603
604
605 /* Each USB transfer request using DMA maps to one or more DMA transfers.
606  * When DMA completion isn't request completion, the UDC continues with
607  * the next DMA transfer for that USB transfer.
608  */
609
610 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
611 {
612         u16             txdma_ctrl;
613         unsigned        length = req->req.length - req->req.actual;
614         const int       sync_mode = cpu_is_omap15xx()
615                                 ? OMAP_DMA_SYNC_FRAME
616                                 : OMAP_DMA_SYNC_ELEMENT;
617
618         /* measure length in either bytes or packets */
619         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
620                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
621                 txdma_ctrl = UDC_TXN_EOT | length;
622                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
623                                 length, 1, sync_mode);
624         } else {
625                 length = min(length / ep->maxpacket,
626                                 (unsigned) UDC_TXN_TSC + 1);
627                 txdma_ctrl = length;
628                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
629                                 ep->ep.maxpacket >> 1, length, sync_mode);
630                 length *= ep->maxpacket;
631         }
632         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
633                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual);
634
635         omap_start_dma(ep->lch);
636         ep->dma_counter = dma_csac(ep->lch);
637         UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
638         UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
639         req->dma_bytes = length;
640 }
641
642 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
643 {
644         if (status == 0) {
645                 req->req.actual += req->dma_bytes;
646
647                 /* return if this request needs to send data or zlp */
648                 if (req->req.actual < req->req.length)
649                         return;
650                 if (req->req.zero
651                                 && req->dma_bytes != 0
652                                 && (req->req.actual % ep->maxpacket) == 0)
653                         return;
654         } else
655                 req->req.actual += dma_src_len(ep, req->req.dma
656                                                         + req->req.actual);
657
658         /* tx completion */
659         omap_stop_dma(ep->lch);
660         UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
661         done(ep, req, status);
662 }
663
664 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
665 {
666         unsigned packets;
667
668         /* NOTE:  we filtered out "short reads" before, so we know
669          * the buffer has only whole numbers of packets.
670          */
671
672         /* set up this DMA transfer, enable the fifo, start */
673         packets = (req->req.length - req->req.actual) / ep->ep.maxpacket;
674         packets = min(packets, (unsigned)UDC_RXN_TC + 1);
675         req->dma_bytes = packets * ep->ep.maxpacket;
676         omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
677                         ep->ep.maxpacket >> 1, packets,
678                         OMAP_DMA_SYNC_ELEMENT);
679         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
680                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual);
681         ep->dma_counter = DMA_DEST_LAST(ep->lch);
682
683         UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
684         UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
685         UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
686         UDC_CTRL_REG = UDC_SET_FIFO_EN;
687
688         omap_start_dma(ep->lch);
689 }
690
691 static void
692 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
693 {
694         u16     count;
695
696         if (status == 0)
697                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
698         count = dma_dest_len(ep, req->req.dma + req->req.actual);
699         count += req->req.actual;
700         if (one)
701                 count--;
702         if (count <= req->req.length)
703                 req->req.actual = count;
704
705         if (count != req->dma_bytes || status)
706                 omap_stop_dma(ep->lch);
707
708         /* if this wasn't short, request may need another transfer */
709         else if (req->req.actual < req->req.length)
710                 return;
711
712         /* rx completion */
713         UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
714         done(ep, req, status);
715 }
716
717 static void dma_irq(struct omap_udc *udc, u16 irq_src)
718 {
719         u16             dman_stat = UDC_DMAN_STAT_REG;
720         struct omap_ep  *ep;
721         struct omap_req *req;
722
723         /* IN dma: tx to host */
724         if (irq_src & UDC_TXN_DONE) {
725                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
726                 ep->irqs++;
727                 /* can see TXN_DONE after dma abort */
728                 if (!list_empty(&ep->queue)) {
729                         req = container_of(ep->queue.next,
730                                                 struct omap_req, queue);
731                         finish_in_dma(ep, req, 0);
732                 }
733                 UDC_IRQ_SRC_REG = UDC_TXN_DONE;
734
735                 if (!list_empty (&ep->queue)) {
736                         req = container_of(ep->queue.next,
737                                         struct omap_req, queue);
738                         next_in_dma(ep, req);
739                 }
740         }
741
742         /* OUT dma: rx from host */
743         if (irq_src & UDC_RXN_EOT) {
744                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
745                 ep->irqs++;
746                 /* can see RXN_EOT after dma abort */
747                 if (!list_empty(&ep->queue)) {
748                         req = container_of(ep->queue.next,
749                                         struct omap_req, queue);
750                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
751                 }
752                 UDC_IRQ_SRC_REG = UDC_RXN_EOT;
753
754                 if (!list_empty (&ep->queue)) {
755                         req = container_of(ep->queue.next,
756                                         struct omap_req, queue);
757                         next_out_dma(ep, req);
758                 }
759         }
760
761         if (irq_src & UDC_RXN_CNT) {
762                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
763                 ep->irqs++;
764                 /* omap15xx does this unasked... */
765                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
766                 UDC_IRQ_SRC_REG = UDC_RXN_CNT;
767         }
768 }
769
770 static void dma_error(int lch, u16 ch_status, void *data)
771 {
772         struct omap_ep  *ep = data;
773
774         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
775         /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
776         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
777
778         /* complete current transfer ... */
779 }
780
781 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
782 {
783         u16     reg;
784         int     status, restart, is_in;
785
786         is_in = ep->bEndpointAddress & USB_DIR_IN;
787         if (is_in)
788                 reg = UDC_TXDMA_CFG_REG;
789         else
790                 reg = UDC_RXDMA_CFG_REG;
791         reg |= UDC_DMA_REQ;             /* "pulse" activated */
792
793         ep->dma_channel = 0;
794         ep->lch = -1;
795         if (channel == 0 || channel > 3) {
796                 if ((reg & 0x0f00) == 0)
797                         channel = 3;
798                 else if ((reg & 0x00f0) == 0)
799                         channel = 2;
800                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
801                         channel = 1;
802                 else {
803                         status = -EMLINK;
804                         goto just_restart;
805                 }
806         }
807         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
808         ep->dma_channel = channel;
809
810         if (is_in) {
811                 status = omap_request_dma(OMAP_DMA_USB_W2FC_TX0 - 1 + channel,
812                         ep->ep.name, dma_error, ep, &ep->lch);
813                 if (status == 0) {
814                         UDC_TXDMA_CFG_REG = reg;
815                         /* EMIFF */
816                         omap_set_dma_src_burst_mode(ep->lch,
817                                                 OMAP_DMA_DATA_BURST_4);
818                         omap_set_dma_src_data_pack(ep->lch, 1);
819                         /* TIPB */
820                         omap_set_dma_dest_params(ep->lch,
821                                 OMAP_DMA_PORT_TIPB,
822                                 OMAP_DMA_AMODE_CONSTANT,
823                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG));
824                 }
825         } else {
826                 status = omap_request_dma(OMAP_DMA_USB_W2FC_RX0 - 1 + channel,
827                         ep->ep.name, dma_error, ep, &ep->lch);
828                 if (status == 0) {
829                         UDC_RXDMA_CFG_REG = reg;
830                         /* TIPB */
831                         omap_set_dma_src_params(ep->lch,
832                                 OMAP_DMA_PORT_TIPB,
833                                 OMAP_DMA_AMODE_CONSTANT,
834                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG));
835                         /* EMIFF */
836                         omap_set_dma_dest_burst_mode(ep->lch,
837                                                 OMAP_DMA_DATA_BURST_4);
838                         omap_set_dma_dest_data_pack(ep->lch, 1);
839                 }
840         }
841         if (status)
842                 ep->dma_channel = 0;
843         else {
844                 ep->has_dma = 1;
845                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
846
847                 /* channel type P: hw synch (fifo) */
848                 if (!cpu_is_omap15xx())
849                         omap_writew(2, OMAP_DMA_LCH_CTRL(ep->lch));
850         }
851
852 just_restart:
853         /* restart any queue, even if the claim failed  */
854         restart = !ep->stopped && !list_empty(&ep->queue);
855
856         if (status)
857                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
858                         restart ? " (restart)" : "");
859         else
860                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
861                         is_in ? 't' : 'r',
862                         ep->dma_channel - 1, ep->lch,
863                         restart ? " (restart)" : "");
864
865         if (restart) {
866                 struct omap_req *req;
867                 req = container_of(ep->queue.next, struct omap_req, queue);
868                 if (ep->has_dma)
869                         (is_in ? next_in_dma : next_out_dma)(ep, req);
870                 else {
871                         use_ep(ep, UDC_EP_SEL);
872                         (is_in ? write_fifo : read_fifo)(ep, req);
873                         deselect_ep();
874                         if (!is_in) {
875                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
876                                 ep->ackwait = 1 + ep->double_buf;
877                         }
878                         /* IN: 6 wait states before it'll tx */
879                 }
880         }
881 }
882
883 static void dma_channel_release(struct omap_ep *ep)
884 {
885         int             shift = 4 * (ep->dma_channel - 1);
886         u16             mask = 0x0f << shift;
887         struct omap_req *req;
888         int             active;
889
890         /* abort any active usb transfer request */
891         if (!list_empty(&ep->queue))
892                 req = container_of(ep->queue.next, struct omap_req, queue);
893         else
894                 req = NULL;
895
896         active = ((1 << 7) & omap_readl(OMAP_DMA_CCR(ep->lch))) != 0;
897
898         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
899                         active ? "active" : "idle",
900                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
901                         ep->dma_channel - 1, req);
902
903         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
904          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
905          */
906
907         /* wait till current packet DMA finishes, and fifo empties */
908         if (ep->bEndpointAddress & USB_DIR_IN) {
909                 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
910
911                 if (req) {
912                         finish_in_dma(ep, req, -ECONNRESET);
913
914                         /* clear FIFO; hosts probably won't empty it */
915                         use_ep(ep, UDC_EP_SEL);
916                         UDC_CTRL_REG = UDC_CLR_EP;
917                         deselect_ep();
918                 }
919                 while (UDC_TXDMA_CFG_REG & mask)
920                         udelay(10);
921         } else {
922                 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
923
924                 /* dma empties the fifo */
925                 while (UDC_RXDMA_CFG_REG & mask)
926                         udelay(10);
927                 if (req)
928                         finish_out_dma(ep, req, -ECONNRESET, 0);
929         }
930         omap_free_dma(ep->lch);
931         ep->dma_channel = 0;
932         ep->lch = -1;
933         /* has_dma still set, till endpoint is fully quiesced */
934 }
935
936
937 /*-------------------------------------------------------------------------*/
938
939 static int
940 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
941 {
942         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
943         struct omap_req *req = container_of(_req, struct omap_req, req);
944         struct omap_udc *udc;
945         unsigned long   flags;
946         int             is_iso = 0;
947
948         /* catch various bogus parameters */
949         if (!_req || !req->req.complete || !req->req.buf
950                         || !list_empty(&req->queue)) {
951                 DBG("%s, bad params\n", __FUNCTION__);
952                 return -EINVAL;
953         }
954         if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
955                 DBG("%s, bad ep\n", __FUNCTION__);
956                 return -EINVAL;
957         }
958         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
959                 if (req->req.length > ep->ep.maxpacket)
960                         return -EMSGSIZE;
961                 is_iso = 1;
962         }
963
964         /* this isn't bogus, but OMAP DMA isn't the only hardware to
965          * have a hard time with partial packet reads...  reject it.
966          */
967         if (use_dma
968                         && ep->has_dma
969                         && ep->bEndpointAddress != 0
970                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
971                         && (req->req.length % ep->ep.maxpacket) != 0) {
972                 DBG("%s, no partial packet OUT reads\n", __FUNCTION__);
973                 return -EMSGSIZE;
974         }
975
976         udc = ep->udc;
977         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
978                 return -ESHUTDOWN;
979
980         if (use_dma && ep->has_dma) {
981                 if (req->req.dma == DMA_ADDR_INVALID) {
982                         req->req.dma = dma_map_single(
983                                 ep->udc->gadget.dev.parent,
984                                 req->req.buf,
985                                 req->req.length,
986                                 (ep->bEndpointAddress & USB_DIR_IN)
987                                         ? DMA_TO_DEVICE
988                                         : DMA_FROM_DEVICE);
989                         req->mapped = 1;
990                 } else {
991                         dma_sync_single_for_device(
992                                 ep->udc->gadget.dev.parent,
993                                 req->req.dma, req->req.length,
994                                 (ep->bEndpointAddress & USB_DIR_IN)
995                                         ? DMA_TO_DEVICE
996                                         : DMA_FROM_DEVICE);
997                         req->mapped = 0;
998                 }
999         }
1000
1001         VDBG("%s queue req %p, len %d buf %p\n",
1002                 ep->ep.name, _req, _req->length, _req->buf);
1003
1004         spin_lock_irqsave(&udc->lock, flags);
1005
1006         req->req.status = -EINPROGRESS;
1007         req->req.actual = 0;
1008
1009         /* maybe kickstart non-iso i/o queues */
1010         if (is_iso)
1011                 UDC_IRQ_EN_REG |= UDC_SOF_IE;
1012         else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
1013                 int     is_in;
1014
1015                 if (ep->bEndpointAddress == 0) {
1016                         if (!udc->ep0_pending || !list_empty (&ep->queue)) {
1017                                 spin_unlock_irqrestore(&udc->lock, flags);
1018                                 return -EL2HLT;
1019                         }
1020
1021                         /* empty DATA stage? */
1022                         is_in = udc->ep0_in;
1023                         if (!req->req.length) {
1024
1025                                 /* chip became CONFIGURED or ADDRESSED
1026                                  * earlier; drivers may already have queued
1027                                  * requests to non-control endpoints
1028                                  */
1029                                 if (udc->ep0_set_config) {
1030                                         u16     irq_en = UDC_IRQ_EN_REG;
1031
1032                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1033                                         if (!udc->ep0_reset_config)
1034                                                 irq_en |= UDC_EPN_RX_IE
1035                                                         | UDC_EPN_TX_IE;
1036                                         UDC_IRQ_EN_REG = irq_en;
1037                                 }
1038
1039                                 /* STATUS for zero length DATA stages is
1040                                  * always an IN ... even for IN transfers,
1041                                  * a wierd case which seem to stall OMAP.
1042                                  */
1043                                 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1044                                 UDC_CTRL_REG = UDC_CLR_EP;
1045                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1046                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1047
1048                                 /* cleanup */
1049                                 udc->ep0_pending = 0;
1050                                 done(ep, req, 0);
1051                                 req = NULL;
1052
1053                         /* non-empty DATA stage */
1054                         } else if (is_in) {
1055                                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1056                         } else {
1057                                 if (udc->ep0_setup)
1058                                         goto irq_wait;
1059                                 UDC_EP_NUM_REG = UDC_EP_SEL;
1060                         }
1061                 } else {
1062                         is_in = ep->bEndpointAddress & USB_DIR_IN;
1063                         if (!ep->has_dma)
1064                                 use_ep(ep, UDC_EP_SEL);
1065                         /* if ISO: SOF IRQs must be enabled/disabled! */
1066                 }
1067
1068                 if (ep->has_dma)
1069                         (is_in ? next_in_dma : next_out_dma)(ep, req);
1070                 else if (req) {
1071                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1072                                 req = NULL;
1073                         deselect_ep();
1074                         if (!is_in) {
1075                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1076                                 ep->ackwait = 1 + ep->double_buf;
1077                         }
1078                         /* IN: 6 wait states before it'll tx */
1079                 }
1080         }
1081
1082 irq_wait:
1083         /* irq handler advances the queue */
1084         if (req != NULL)
1085                 list_add_tail(&req->queue, &ep->queue);
1086         spin_unlock_irqrestore(&udc->lock, flags);
1087
1088         return 0;
1089 }
1090
1091 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1092 {
1093         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1094         struct omap_req *req;
1095         unsigned long   flags;
1096
1097         if (!_ep || !_req)
1098                 return -EINVAL;
1099
1100         spin_lock_irqsave(&ep->udc->lock, flags);
1101
1102         /* make sure it's actually queued on this endpoint */
1103         list_for_each_entry (req, &ep->queue, queue) {
1104                 if (&req->req == _req)
1105                         break;
1106         }
1107         if (&req->req != _req) {
1108                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1109                 return -EINVAL;
1110         }
1111
1112         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1113                 int channel = ep->dma_channel;
1114
1115                 /* releasing the channel cancels the request,
1116                  * reclaiming the channel restarts the queue
1117                  */
1118                 dma_channel_release(ep);
1119                 dma_channel_claim(ep, channel);
1120         } else 
1121                 done(ep, req, -ECONNRESET);
1122         spin_unlock_irqrestore(&ep->udc->lock, flags);
1123         return 0;
1124 }
1125
1126 /*-------------------------------------------------------------------------*/
1127
1128 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1129 {
1130         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1131         unsigned long   flags;
1132         int             status = -EOPNOTSUPP;
1133
1134         spin_lock_irqsave(&ep->udc->lock, flags);
1135
1136         /* just use protocol stalls for ep0; real halts are annoying */
1137         if (ep->bEndpointAddress == 0) {
1138                 if (!ep->udc->ep0_pending)
1139                         status = -EINVAL;
1140                 else if (value) {
1141                         if (ep->udc->ep0_set_config) {
1142                                 WARN("error changing config?\n");
1143                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1144                         }
1145                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1146                         ep->udc->ep0_pending = 0;
1147                         status = 0;
1148                 } else /* NOP */
1149                         status = 0;
1150
1151         /* otherwise, all active non-ISO endpoints can halt */
1152         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1153
1154                 /* IN endpoints must already be idle */
1155                 if ((ep->bEndpointAddress & USB_DIR_IN)
1156                                 && !list_empty(&ep->queue)) { 
1157                         status = -EAGAIN;
1158                         goto done;
1159                 }
1160
1161                 if (value) {
1162                         int     channel;
1163
1164                         if (use_dma && ep->dma_channel
1165                                         && !list_empty(&ep->queue)) {
1166                                 channel = ep->dma_channel;
1167                                 dma_channel_release(ep);
1168                         } else
1169                                 channel = 0;
1170
1171                         use_ep(ep, UDC_EP_SEL);
1172                         if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
1173                                 UDC_CTRL_REG = UDC_SET_HALT;
1174                                 status = 0;
1175                         } else
1176                                 status = -EAGAIN;
1177                         deselect_ep();
1178
1179                         if (channel)
1180                                 dma_channel_claim(ep, channel);
1181                 } else {
1182                         use_ep(ep, 0);
1183                         UDC_CTRL_REG = ep->udc->clr_halt;
1184                         ep->ackwait = 0;
1185                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1186                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1187                                 ep->ackwait = 1 + ep->double_buf;
1188                         }
1189                 }
1190         }
1191 done:
1192         VDBG("%s %s halt stat %d\n", ep->ep.name,
1193                 value ? "set" : "clear", status);
1194
1195         spin_unlock_irqrestore(&ep->udc->lock, flags);
1196         return status;
1197 }
1198
1199 static struct usb_ep_ops omap_ep_ops = {
1200         .enable         = omap_ep_enable,
1201         .disable        = omap_ep_disable,
1202
1203         .alloc_request  = omap_alloc_request,
1204         .free_request   = omap_free_request,
1205
1206         .alloc_buffer   = omap_alloc_buffer,
1207         .free_buffer    = omap_free_buffer,
1208
1209         .queue          = omap_ep_queue,
1210         .dequeue        = omap_ep_dequeue,
1211
1212         .set_halt       = omap_ep_set_halt,
1213         // fifo_status ... report bytes in fifo
1214         // fifo_flush ... flush fifo
1215 };
1216
1217 /*-------------------------------------------------------------------------*/
1218
1219 static int omap_get_frame(struct usb_gadget *gadget)
1220 {
1221         u16     sof = UDC_SOF_REG;
1222         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1223 }
1224
1225 static int omap_wakeup(struct usb_gadget *gadget)
1226 {
1227         struct omap_udc *udc;
1228         unsigned long   flags;
1229         int             retval = -EHOSTUNREACH;
1230
1231         udc = container_of(gadget, struct omap_udc, gadget);
1232
1233         spin_lock_irqsave(&udc->lock, flags);
1234         if (udc->devstat & UDC_SUS) {
1235                 /* NOTE:  OTG spec erratum says that OTG devices may
1236                  * issue wakeups without host enable.
1237                  */
1238                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1239                         DBG("remote wakeup...\n");
1240                         UDC_SYSCON2_REG = UDC_RMT_WKP;
1241                         retval = 0;
1242                 }
1243
1244         /* NOTE:  non-OTG systems may use SRP TOO... */
1245         } else if (!(udc->devstat & UDC_ATT)) {
1246                 if (udc->transceiver)
1247                         retval = otg_start_srp(udc->transceiver);
1248         }
1249         spin_unlock_irqrestore(&udc->lock, flags);
1250
1251         return retval;
1252 }
1253
1254 static int
1255 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1256 {
1257         struct omap_udc *udc;
1258         unsigned long   flags;
1259         u16             syscon1;
1260
1261         udc = container_of(gadget, struct omap_udc, gadget);
1262         spin_lock_irqsave(&udc->lock, flags);
1263         syscon1 = UDC_SYSCON1_REG;
1264         if (is_selfpowered)
1265                 syscon1 |= UDC_SELF_PWR;
1266         else
1267                 syscon1 &= ~UDC_SELF_PWR;
1268         UDC_SYSCON1_REG = syscon1;
1269         spin_unlock_irqrestore(&udc->lock, flags);
1270
1271         return 0;
1272 }
1273
1274 static int can_pullup(struct omap_udc *udc)
1275 {
1276         return udc->driver && udc->softconnect && udc->vbus_active;
1277 }
1278
1279 static void pullup_enable(struct omap_udc *udc)
1280 {
1281         udc->gadget.dev.parent->power.power_state = PMSG_ON;
1282         udc->gadget.dev.power.power_state = PMSG_ON;
1283         UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1284 #ifndef CONFIG_USB_OTG
1285         if (!cpu_is_omap15xx())
1286                 OTG_CTRL_REG |= OTG_BSESSVLD;
1287 #endif
1288         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1289 }
1290
1291 static void pullup_disable(struct omap_udc *udc)
1292 {
1293 #ifndef CONFIG_USB_OTG
1294         if (!cpu_is_omap15xx())
1295                 OTG_CTRL_REG &= ~OTG_BSESSVLD;
1296 #endif
1297         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1298         UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
1299 }
1300
1301 /*
1302  * Called by whatever detects VBUS sessions:  external transceiver
1303  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1304  */
1305 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1306 {
1307         struct omap_udc *udc;
1308         unsigned long   flags;
1309
1310         udc = container_of(gadget, struct omap_udc, gadget);
1311         spin_lock_irqsave(&udc->lock, flags);
1312         VDBG("VBUS %s\n", is_active ? "on" : "off");
1313         udc->vbus_active = (is_active != 0);
1314         if (cpu_is_omap15xx()) {
1315                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1316                 if (is_active)
1317                         FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
1318                 else
1319                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
1320         }
1321         if (can_pullup(udc))
1322                 pullup_enable(udc);
1323         else
1324                 pullup_disable(udc);
1325         spin_unlock_irqrestore(&udc->lock, flags);
1326         return 0;
1327 }
1328
1329 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1330 {
1331         struct omap_udc *udc;
1332
1333         udc = container_of(gadget, struct omap_udc, gadget);
1334         if (udc->transceiver)
1335                 return otg_set_power(udc->transceiver, mA);
1336         return -EOPNOTSUPP;
1337 }
1338
1339 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1340 {
1341         struct omap_udc *udc;
1342         unsigned long   flags;
1343
1344         udc = container_of(gadget, struct omap_udc, gadget);
1345         spin_lock_irqsave(&udc->lock, flags);
1346         udc->softconnect = (is_on != 0);
1347         if (can_pullup(udc))
1348                 pullup_enable(udc);
1349         else
1350                 pullup_disable(udc);
1351         spin_unlock_irqrestore(&udc->lock, flags);
1352         return 0;
1353 }
1354
1355 static struct usb_gadget_ops omap_gadget_ops = {
1356         .get_frame              = omap_get_frame,
1357         .wakeup                 = omap_wakeup,
1358         .set_selfpowered        = omap_set_selfpowered,
1359         .vbus_session           = omap_vbus_session,
1360         .vbus_draw              = omap_vbus_draw,
1361         .pullup                 = omap_pullup,
1362 };
1363
1364 /*-------------------------------------------------------------------------*/
1365
1366 /* dequeue ALL requests; caller holds udc->lock */
1367 static void nuke(struct omap_ep *ep, int status)
1368 {
1369         struct omap_req *req;
1370
1371         ep->stopped = 1;
1372
1373         if (use_dma && ep->dma_channel)
1374                 dma_channel_release(ep);
1375
1376         use_ep(ep, 0);
1377         UDC_CTRL_REG = UDC_CLR_EP;
1378         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1379                 UDC_CTRL_REG = UDC_SET_HALT;
1380
1381         while (!list_empty(&ep->queue)) {
1382                 req = list_entry(ep->queue.next, struct omap_req, queue);
1383                 done(ep, req, status);
1384         }
1385 }
1386
1387 /* caller holds udc->lock */
1388 static void udc_quiesce(struct omap_udc *udc)
1389 {
1390         struct omap_ep  *ep;
1391
1392         udc->gadget.speed = USB_SPEED_UNKNOWN;
1393         nuke(&udc->ep[0], -ESHUTDOWN);
1394         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1395                 nuke(ep, -ESHUTDOWN);
1396 }
1397
1398 /*-------------------------------------------------------------------------*/
1399
1400 static void update_otg(struct omap_udc *udc)
1401 {
1402         u16     devstat;
1403
1404         if (!udc->gadget.is_otg)
1405                 return;
1406
1407         if (OTG_CTRL_REG & OTG_ID)
1408                 devstat = UDC_DEVSTAT_REG;
1409         else
1410                 devstat = 0;
1411
1412         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1413         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1414         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1415
1416         /* Enable HNP early, avoiding races on suspend irq path.
1417          * ASSUMES OTG state machine B_BUS_REQ input is true.
1418          */
1419         if (udc->gadget.b_hnp_enable)
1420                 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
1421                                 & ~OTG_PULLUP;
1422 }
1423
1424 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1425 {
1426         struct omap_ep  *ep0 = &udc->ep[0];
1427         struct omap_req *req = NULL;
1428
1429         ep0->irqs++;
1430
1431         /* Clear any pending requests and then scrub any rx/tx state
1432          * before starting to handle the SETUP request.
1433          */
1434         if (irq_src & UDC_SETUP) {
1435                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1436
1437                 nuke(ep0, 0);
1438                 if (ack) {
1439                         UDC_IRQ_SRC_REG = ack;
1440                         irq_src = UDC_SETUP;
1441                 }
1442         }
1443
1444         /* IN/OUT packets mean we're in the DATA or STATUS stage.  
1445          * This driver uses only uses protocol stalls (ep0 never halts),
1446          * and if we got this far the gadget driver already had a
1447          * chance to stall.  Tries to be forgiving of host oddities.
1448          *
1449          * NOTE:  the last chance gadget drivers have to stall control
1450          * requests is during their request completion callback.
1451          */
1452         if (!list_empty(&ep0->queue))
1453                 req = container_of(ep0->queue.next, struct omap_req, queue);
1454
1455         /* IN == TX to host */
1456         if (irq_src & UDC_EP0_TX) {
1457                 int     stat;
1458
1459                 UDC_IRQ_SRC_REG = UDC_EP0_TX;
1460                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1461                 stat = UDC_STAT_FLG_REG;
1462                 if (stat & UDC_ACK) {
1463                         if (udc->ep0_in) {
1464                                 /* write next IN packet from response,
1465                                  * or set up the status stage.
1466                                  */
1467                                 if (req)
1468                                         stat = write_fifo(ep0, req);
1469                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1470                                 if (!req && udc->ep0_pending) {
1471                                         UDC_EP_NUM_REG = UDC_EP_SEL;
1472                                         UDC_CTRL_REG = UDC_CLR_EP;
1473                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1474                                         UDC_EP_NUM_REG = 0;
1475                                         udc->ep0_pending = 0;
1476                                 } /* else:  6 wait states before it'll tx */
1477                         } else {
1478                                 /* ack status stage of OUT transfer */
1479                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1480                                 if (req)
1481                                         done(ep0, req, 0);
1482                         }
1483                         req = NULL;
1484                 } else if (stat & UDC_STALL) {
1485                         UDC_CTRL_REG = UDC_CLR_HALT;
1486                         UDC_EP_NUM_REG = UDC_EP_DIR;
1487                 } else {
1488                         UDC_EP_NUM_REG = UDC_EP_DIR;
1489                 }
1490         }
1491
1492         /* OUT == RX from host */
1493         if (irq_src & UDC_EP0_RX) {
1494                 int     stat;
1495
1496                 UDC_IRQ_SRC_REG = UDC_EP0_RX;
1497                 UDC_EP_NUM_REG = UDC_EP_SEL;
1498                 stat = UDC_STAT_FLG_REG;
1499                 if (stat & UDC_ACK) {
1500                         if (!udc->ep0_in) {
1501                                 stat = 0;
1502                                 /* read next OUT packet of request, maybe
1503                                  * reactiviting the fifo; stall on errors.
1504                                  */
1505                                 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1506                                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1507                                         udc->ep0_pending = 0;
1508                                         stat = 0;
1509                                 } else if (stat == 0)
1510                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1511                                 UDC_EP_NUM_REG = 0;
1512                                 
1513                                 /* activate status stage */
1514                                 if (stat == 1) {
1515                                         done(ep0, req, 0);
1516                                         /* that may have STALLed ep0... */
1517                                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1518                                         UDC_CTRL_REG = UDC_CLR_EP;
1519                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1520                                         UDC_EP_NUM_REG = UDC_EP_DIR;
1521                                         udc->ep0_pending = 0;
1522                                 }
1523                         } else {
1524                                 /* ack status stage of IN transfer */
1525                                 UDC_EP_NUM_REG = 0;
1526                                 if (req)
1527                                         done(ep0, req, 0);
1528                         }
1529                 } else if (stat & UDC_STALL) {
1530                         UDC_CTRL_REG = UDC_CLR_HALT;
1531                         UDC_EP_NUM_REG = 0;
1532                 } else {
1533                         UDC_EP_NUM_REG = 0;
1534                 }
1535         }
1536
1537         /* SETUP starts all control transfers */
1538         if (irq_src & UDC_SETUP) {
1539                 union u {
1540                         u16                     word[4];
1541                         struct usb_ctrlrequest  r;
1542                 } u;
1543                 int                     status = -EINVAL;
1544                 struct omap_ep          *ep;
1545
1546                 /* read the (latest) SETUP message */
1547                 do {
1548                         UDC_EP_NUM_REG = UDC_SETUP_SEL;
1549                         /* two bytes at a time */
1550                         u.word[0] = UDC_DATA_REG;
1551                         u.word[1] = UDC_DATA_REG;
1552                         u.word[2] = UDC_DATA_REG;
1553                         u.word[3] = UDC_DATA_REG;
1554                         UDC_EP_NUM_REG = 0;
1555                 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1556
1557 #define w_value         le16_to_cpup (&u.r.wValue)
1558 #define w_index         le16_to_cpup (&u.r.wIndex)
1559 #define w_length        le16_to_cpup (&u.r.wLength)
1560
1561                 /* Delegate almost all control requests to the gadget driver,
1562                  * except for a handful of ch9 status/feature requests that
1563                  * hardware doesn't autodecode _and_ the gadget API hides.
1564                  */
1565                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1566                 udc->ep0_set_config = 0;
1567                 udc->ep0_pending = 1;
1568                 ep0->stopped = 0;
1569                 ep0->ackwait = 0;
1570                 switch (u.r.bRequest) {
1571                 case USB_REQ_SET_CONFIGURATION:
1572                         /* udc needs to know when ep != 0 is valid */
1573                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1574                                 goto delegate;
1575                         if (w_length != 0)
1576                                 goto do_stall;
1577                         udc->ep0_set_config = 1;
1578                         udc->ep0_reset_config = (w_value == 0);
1579                         VDBG("set config %d\n", w_value);
1580
1581                         /* update udc NOW since gadget driver may start
1582                          * queueing requests immediately; clear config
1583                          * later if it fails the request.
1584                          */
1585                         if (udc->ep0_reset_config)
1586                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1587                         else
1588                                 UDC_SYSCON2_REG = UDC_DEV_CFG;
1589                         update_otg(udc);
1590                         goto delegate;
1591                 case USB_REQ_CLEAR_FEATURE:
1592                         /* clear endpoint halt */
1593                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1594                                 goto delegate;
1595                         if (w_value != USB_ENDPOINT_HALT
1596                                         || w_length != 0)
1597                                 goto do_stall;
1598                         ep = &udc->ep[w_index & 0xf];
1599                         if (ep != ep0) {
1600                                 if (w_index & USB_DIR_IN)
1601                                         ep += 16;
1602                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1603                                                 || !ep->desc)
1604                                         goto do_stall;
1605                                 use_ep(ep, 0);
1606                                 UDC_CTRL_REG = udc->clr_halt;
1607                                 ep->ackwait = 0;
1608                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1609                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1610                                         ep->ackwait = 1 + ep->double_buf;
1611                                 }
1612                                 /* NOTE:  assumes the host behaves sanely,
1613                                  * only clearing real halts.  Else we may
1614                                  * need to kill pending transfers and then
1615                                  * restart the queue... very messy for DMA!
1616                                  */
1617                         }
1618                         VDBG("%s halt cleared by host\n", ep->name);
1619                         goto ep0out_status_stage;
1620                 case USB_REQ_SET_FEATURE:
1621                         /* set endpoint halt */
1622                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1623                                 goto delegate;
1624                         if (w_value != USB_ENDPOINT_HALT
1625                                         || w_length != 0)
1626                                 goto do_stall;
1627                         ep = &udc->ep[w_index & 0xf];
1628                         if (w_index & USB_DIR_IN)
1629                                 ep += 16;
1630                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1631                                         || ep == ep0 || !ep->desc)
1632                                 goto do_stall;
1633                         if (use_dma && ep->has_dma) {
1634                                 /* this has rude side-effects (aborts) and
1635                                  * can't really work if DMA-IN is active
1636                                  */
1637                                 DBG("%s host set_halt, NYET \n", ep->name);
1638                                 goto do_stall;
1639                         }
1640                         use_ep(ep, 0);
1641                         /* can't halt if fifo isn't empty... */
1642                         UDC_CTRL_REG = UDC_CLR_EP;
1643                         UDC_CTRL_REG = UDC_SET_HALT;
1644                         VDBG("%s halted by host\n", ep->name);
1645 ep0out_status_stage:
1646                         status = 0;
1647                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1648                         UDC_CTRL_REG = UDC_CLR_EP;
1649                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1650                         UDC_EP_NUM_REG = UDC_EP_DIR;
1651                         udc->ep0_pending = 0;
1652                         break;
1653                 case USB_REQ_GET_STATUS:
1654                         /* return interface status.  if we were pedantic,
1655                          * we'd detect non-existent interfaces, and stall.
1656                          */
1657                         if (u.r.bRequestType
1658                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1659                                 goto delegate;
1660                         /* return two zero bytes */
1661                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1662                         UDC_DATA_REG = 0;
1663                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1664                         UDC_EP_NUM_REG = UDC_EP_DIR;
1665                         status = 0;
1666                         VDBG("GET_STATUS, interface %d\n", w_index);
1667                         /* next, status stage */
1668                         break;
1669                 default:
1670 delegate:
1671                         /* activate the ep0out fifo right away */
1672                         if (!udc->ep0_in && w_length) {
1673                                 UDC_EP_NUM_REG = 0;
1674                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1675                         }
1676
1677                         /* gadget drivers see class/vendor specific requests,
1678                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1679                          * and more
1680                          */
1681                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1682                                 u.r.bRequestType, u.r.bRequest,
1683                                 w_value, w_index, w_length);
1684
1685 #undef  w_value
1686 #undef  w_index
1687 #undef  w_length
1688
1689                         /* The gadget driver may return an error here,
1690                          * causing an immediate protocol stall.
1691                          *
1692                          * Else it must issue a response, either queueing a
1693                          * response buffer for the DATA stage, or halting ep0
1694                          * (causing a protocol stall, not a real halt).  A
1695                          * zero length buffer means no DATA stage.
1696                          *
1697                          * It's fine to issue that response after the setup()
1698                          * call returns, and this IRQ was handled.
1699                          */
1700                         udc->ep0_setup = 1;
1701                         spin_unlock(&udc->lock);
1702                         status = udc->driver->setup (&udc->gadget, &u.r);
1703                         spin_lock(&udc->lock);
1704                         udc->ep0_setup = 0;
1705                 }
1706
1707                 if (status < 0) {
1708 do_stall:
1709                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1710                                         u.r.bRequestType, u.r.bRequest, status);
1711                         if (udc->ep0_set_config) {
1712                                 if (udc->ep0_reset_config)
1713                                         WARN("error resetting config?\n");
1714                                 else
1715                                         UDC_SYSCON2_REG = UDC_CLR_CFG;
1716                         }
1717                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1718                         udc->ep0_pending = 0;
1719                 }
1720         }
1721 }
1722
1723 /*-------------------------------------------------------------------------*/
1724
1725 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1726
1727 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1728 {
1729         u16     devstat, change;
1730
1731         devstat = UDC_DEVSTAT_REG;
1732         change = devstat ^ udc->devstat;
1733         udc->devstat = devstat;
1734
1735         if (change & (UDC_USB_RESET|UDC_ATT)) {
1736                 udc_quiesce(udc);
1737
1738                 if (change & UDC_ATT) {
1739                         /* driver for any external transceiver will
1740                          * have called omap_vbus_session() already
1741                          */
1742                         if (devstat & UDC_ATT) {
1743                                 udc->gadget.speed = USB_SPEED_FULL;
1744                                 VDBG("connect\n");
1745                                 if (!udc->transceiver)
1746                                         pullup_enable(udc);
1747                                 // if (driver->connect) call it
1748                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1749                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1750                                 if (!udc->transceiver)
1751                                         pullup_disable(udc);
1752                                 DBG("disconnect, gadget %s\n",
1753                                         udc->driver->driver.name);
1754                                 if (udc->driver->disconnect) {
1755                                         spin_unlock(&udc->lock);
1756                                         udc->driver->disconnect(&udc->gadget);
1757                                         spin_lock(&udc->lock);
1758                                 }
1759                         }
1760                         change &= ~UDC_ATT;
1761                 }
1762
1763                 if (change & UDC_USB_RESET) {
1764                         if (devstat & UDC_USB_RESET) {
1765                                 VDBG("RESET=1\n");
1766                         } else {
1767                                 udc->gadget.speed = USB_SPEED_FULL;
1768                                 INFO("USB reset done, gadget %s\n",
1769                                         udc->driver->driver.name);
1770                                 /* ep0 traffic is legal from now on */
1771                                 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
1772                         }
1773                         change &= ~UDC_USB_RESET;
1774                 }
1775         }
1776         if (change & UDC_SUS) {
1777                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1778                         // FIXME tell isp1301 to suspend/resume (?)
1779                         if (devstat & UDC_SUS) {
1780                                 VDBG("suspend\n");
1781                                 update_otg(udc);
1782                                 /* HNP could be under way already */
1783                                 if (udc->gadget.speed == USB_SPEED_FULL
1784                                                 && udc->driver->suspend) {
1785                                         spin_unlock(&udc->lock);
1786                                         udc->driver->suspend(&udc->gadget);
1787                                         spin_lock(&udc->lock);
1788                                 }
1789                                 if (udc->transceiver)
1790                                         otg_set_suspend(udc->transceiver, 1);
1791                         } else {
1792                                 VDBG("resume\n");
1793                                 if (udc->transceiver)
1794                                         otg_set_suspend(udc->transceiver, 0);
1795                                 if (udc->gadget.speed == USB_SPEED_FULL
1796                                                 && udc->driver->resume) {
1797                                         spin_unlock(&udc->lock);
1798                                         udc->driver->resume(&udc->gadget);
1799                                         spin_lock(&udc->lock);
1800                                 }
1801                         }
1802                 }
1803                 change &= ~UDC_SUS;
1804         }
1805         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1806                 update_otg(udc);
1807                 change &= ~OTG_FLAGS;
1808         }
1809
1810         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1811         if (change)
1812                 VDBG("devstat %03x, ignore change %03x\n",
1813                         devstat,  change);
1814
1815         UDC_IRQ_SRC_REG = UDC_DS_CHG;
1816 }
1817
1818 static irqreturn_t
1819 omap_udc_irq(int irq, void *_udc, struct pt_regs *r)
1820 {
1821         struct omap_udc *udc = _udc;
1822         u16             irq_src;
1823         irqreturn_t     status = IRQ_NONE;
1824         unsigned long   flags;
1825
1826         spin_lock_irqsave(&udc->lock, flags);
1827         irq_src = UDC_IRQ_SRC_REG;
1828
1829         /* Device state change (usb ch9 stuff) */
1830         if (irq_src & UDC_DS_CHG) {
1831                 devstate_irq(_udc, irq_src);
1832                 status = IRQ_HANDLED;
1833                 irq_src &= ~UDC_DS_CHG;
1834         }
1835
1836         /* EP0 control transfers */
1837         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1838                 ep0_irq(_udc, irq_src);
1839                 status = IRQ_HANDLED;
1840                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1841         }
1842
1843         /* DMA transfer completion */
1844         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1845                 dma_irq(_udc, irq_src);
1846                 status = IRQ_HANDLED;
1847                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1848         }
1849
1850         irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
1851         if (irq_src)
1852                 DBG("udc_irq, unhandled %03x\n", irq_src);
1853         spin_unlock_irqrestore(&udc->lock, flags);
1854
1855         return status;
1856 }
1857
1858 /* workaround for seemingly-lost IRQs for RX ACKs... */
1859 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1860 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1861
1862 static void pio_out_timer(unsigned long _ep)
1863 {
1864         struct omap_ep  *ep = (void *) _ep;
1865         unsigned long   flags;
1866         u16             stat_flg;
1867
1868         spin_lock_irqsave(&ep->udc->lock, flags);
1869         if (!list_empty(&ep->queue) && ep->ackwait) {
1870                 use_ep(ep, 0);
1871                 stat_flg = UDC_STAT_FLG_REG;
1872
1873                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1874                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1875                         struct omap_req *req;
1876
1877                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1878                         req = container_of(ep->queue.next,
1879                                         struct omap_req, queue);
1880                         UDC_EP_NUM_REG = ep->bEndpointAddress | UDC_EP_SEL;
1881                         (void) read_fifo(ep, req);
1882                         UDC_EP_NUM_REG = ep->bEndpointAddress;
1883                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1884                         ep->ackwait = 1 + ep->double_buf;
1885                 }
1886         }
1887         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1888         spin_unlock_irqrestore(&ep->udc->lock, flags);
1889 }
1890
1891 static irqreturn_t
1892 omap_udc_pio_irq(int irq, void *_dev, struct pt_regs *r)
1893 {
1894         u16             epn_stat, irq_src;
1895         irqreturn_t     status = IRQ_NONE;
1896         struct omap_ep  *ep;
1897         int             epnum;
1898         struct omap_udc *udc = _dev;
1899         struct omap_req *req;
1900         unsigned long   flags;
1901
1902         spin_lock_irqsave(&udc->lock, flags);
1903         epn_stat = UDC_EPN_STAT_REG;
1904         irq_src = UDC_IRQ_SRC_REG;
1905
1906         /* handle OUT first, to avoid some wasteful NAKs */
1907         if (irq_src & UDC_EPN_RX) {
1908                 epnum = (epn_stat >> 8) & 0x0f;
1909                 UDC_IRQ_SRC_REG = UDC_EPN_RX;
1910                 status = IRQ_HANDLED;
1911                 ep = &udc->ep[epnum];
1912                 ep->irqs++;
1913
1914                 UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
1915                 ep->fnf = 0;
1916                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1917                         ep->ackwait--;
1918                         if (!list_empty(&ep->queue)) {
1919                                 int stat;
1920                                 req = container_of(ep->queue.next,
1921                                                 struct omap_req, queue);
1922                                 stat = read_fifo(ep, req);
1923                                 if (!ep->double_buf)
1924                                         ep->fnf = 1;
1925                         }
1926                 }
1927                 /* min 6 clock delay before clearing EP_SEL ... */
1928                 epn_stat = UDC_EPN_STAT_REG;
1929                 epn_stat = UDC_EPN_STAT_REG;
1930                 UDC_EP_NUM_REG = epnum;
1931
1932                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1933                  * reduces lossage; timer still needed though (sigh).
1934                  */
1935                 if (ep->fnf) {
1936                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1937                         ep->ackwait = 1 + ep->double_buf;
1938                 }
1939                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1940         }
1941
1942         /* then IN transfers */
1943         else if (irq_src & UDC_EPN_TX) {
1944                 epnum = epn_stat & 0x0f;
1945                 UDC_IRQ_SRC_REG = UDC_EPN_TX;
1946                 status = IRQ_HANDLED;
1947                 ep = &udc->ep[16 + epnum];
1948                 ep->irqs++;
1949
1950                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
1951                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1952                         ep->ackwait = 0;
1953                         if (!list_empty(&ep->queue)) {
1954                                 req = container_of(ep->queue.next,
1955                                                 struct omap_req, queue);
1956                                 (void) write_fifo(ep, req);
1957                         }
1958                 }
1959                 /* min 6 clock delay before clearing EP_SEL ... */
1960                 epn_stat = UDC_EPN_STAT_REG;
1961                 epn_stat = UDC_EPN_STAT_REG;
1962                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
1963                 /* then 6 clocks before it'd tx */
1964         }
1965
1966         spin_unlock_irqrestore(&udc->lock, flags);
1967         return status;
1968 }
1969
1970 #ifdef  USE_ISO
1971 static irqreturn_t
1972 omap_udc_iso_irq(int irq, void *_dev, struct pt_regs *r)
1973 {
1974         struct omap_udc *udc = _dev;
1975         struct omap_ep  *ep;
1976         int             pending = 0;
1977         unsigned long   flags;
1978
1979         spin_lock_irqsave(&udc->lock, flags);
1980
1981         /* handle all non-DMA ISO transfers */
1982         list_for_each_entry (ep, &udc->iso, iso) {
1983                 u16             stat;
1984                 struct omap_req *req;
1985
1986                 if (ep->has_dma || list_empty(&ep->queue))
1987                         continue;
1988                 req = list_entry(ep->queue.next, struct omap_req, queue);
1989
1990                 use_ep(ep, UDC_EP_SEL);
1991                 stat = UDC_STAT_FLG_REG;
1992
1993                 /* NOTE: like the other controller drivers, this isn't
1994                  * currently reporting lost or damaged frames.
1995                  */
1996                 if (ep->bEndpointAddress & USB_DIR_IN) {
1997                         if (stat & UDC_MISS_IN)
1998                                 /* done(ep, req, -EPROTO) */;
1999                         else
2000                                 write_fifo(ep, req);
2001                 } else {
2002                         int     status = 0;
2003
2004                         if (stat & UDC_NO_RXPACKET)
2005                                 status = -EREMOTEIO;
2006                         else if (stat & UDC_ISO_ERR)
2007                                 status = -EILSEQ;
2008                         else if (stat & UDC_DATA_FLUSH)
2009                                 status = -ENOSR;
2010
2011                         if (status)
2012                                 /* done(ep, req, status) */;
2013                         else
2014                                 read_fifo(ep, req);
2015                 }
2016                 deselect_ep();
2017                 /* 6 wait states before next EP */
2018
2019                 ep->irqs++;
2020                 if (!list_empty(&ep->queue))
2021                         pending = 1;
2022         }
2023         if (!pending)
2024                 UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
2025         UDC_IRQ_SRC_REG = UDC_SOF;
2026
2027         spin_unlock_irqrestore(&udc->lock, flags);
2028         return IRQ_HANDLED;
2029 }
2030 #endif
2031
2032 /*-------------------------------------------------------------------------*/
2033
2034 static struct omap_udc *udc;
2035
2036 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2037 {
2038         int             status = -ENODEV;
2039         struct omap_ep  *ep;
2040         unsigned long   flags;
2041
2042         /* basic sanity tests */
2043         if (!udc)
2044                 return -ENODEV;
2045         if (!driver
2046                         // FIXME if otg, check:  driver->is_otg
2047                         || driver->speed < USB_SPEED_FULL
2048                         || !driver->bind
2049                         || !driver->unbind
2050                         || !driver->setup)
2051                 return -EINVAL;
2052
2053         spin_lock_irqsave(&udc->lock, flags);
2054         if (udc->driver) {
2055                 spin_unlock_irqrestore(&udc->lock, flags);
2056                 return -EBUSY;
2057         }
2058
2059         /* reset state */
2060         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2061                 ep->irqs = 0;
2062                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2063                         continue;
2064                 use_ep(ep, 0);
2065                 UDC_CTRL_REG = UDC_SET_HALT;
2066         }
2067         udc->ep0_pending = 0;
2068         udc->ep[0].irqs = 0;
2069         udc->softconnect = 1;
2070
2071         /* hook up the driver */
2072         driver->driver.bus = NULL;
2073         udc->driver = driver;
2074         udc->gadget.dev.driver = &driver->driver;
2075         spin_unlock_irqrestore(&udc->lock, flags);
2076
2077         status = driver->bind (&udc->gadget);
2078         if (status) {
2079                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2080                 udc->gadget.dev.driver = NULL;
2081                 udc->driver = NULL;
2082                 goto done;
2083         }
2084         DBG("bound to driver %s\n", driver->driver.name);
2085
2086         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2087
2088         /* connect to bus through transceiver */
2089         if (udc->transceiver) {
2090                 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2091                 if (status < 0) {
2092                         ERR("can't bind to transceiver\n");
2093                         driver->unbind (&udc->gadget);
2094                         udc->gadget.dev.driver = NULL;
2095                         udc->driver = NULL;
2096                         goto done;
2097                 }
2098         } else {
2099                 if (can_pullup(udc))
2100                         pullup_enable (udc);
2101                 else
2102                         pullup_disable (udc);
2103         }
2104
2105         /* boards that don't have VBUS sensing can't autogate 48MHz;
2106          * can't enter deep sleep while a gadget driver is active.
2107          */
2108         if (machine_is_omap_innovator() || machine_is_omap_osk())
2109                 omap_vbus_session(&udc->gadget, 1);
2110
2111 done:
2112         return status;
2113 }
2114 EXPORT_SYMBOL(usb_gadget_register_driver);
2115
2116 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2117 {
2118         unsigned long   flags;
2119         int             status = -ENODEV;
2120
2121         if (!udc)
2122                 return -ENODEV;
2123         if (!driver || driver != udc->driver)
2124                 return -EINVAL;
2125
2126         if (machine_is_omap_innovator() || machine_is_omap_osk())
2127                 omap_vbus_session(&udc->gadget, 0);
2128
2129         if (udc->transceiver)
2130                 (void) otg_set_peripheral(udc->transceiver, NULL);
2131         else
2132                 pullup_disable(udc);
2133
2134         spin_lock_irqsave(&udc->lock, flags);
2135         udc_quiesce(udc);
2136         spin_unlock_irqrestore(&udc->lock, flags);
2137
2138         driver->unbind(&udc->gadget);
2139         udc->gadget.dev.driver = NULL;
2140         udc->driver = NULL;
2141
2142         DBG("unregistered driver '%s'\n", driver->driver.name);
2143         return status;
2144 }
2145 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2146
2147
2148 /*-------------------------------------------------------------------------*/
2149
2150 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2151
2152 #include <linux/seq_file.h>
2153
2154 static const char proc_filename[] = "driver/udc";
2155
2156 #define FOURBITS "%s%s%s%s"
2157 #define EIGHTBITS FOURBITS FOURBITS
2158
2159 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2160 {
2161         u16             stat_flg;
2162         struct omap_req *req;
2163         char            buf[20];
2164
2165         use_ep(ep, 0);
2166
2167         if (use_dma && ep->has_dma)
2168                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2169                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2170                         ep->dma_channel - 1, ep->lch);
2171         else
2172                 buf[0] = 0;
2173
2174         stat_flg = UDC_STAT_FLG_REG;
2175         seq_printf(s,
2176                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2177                 ep->name, buf,
2178                 ep->double_buf ? "dbuf " : "",
2179                 ({char *s; switch(ep->ackwait){
2180                 case 0: s = ""; break;
2181                 case 1: s = "(ackw) "; break;
2182                 case 2: s = "(ackw2) "; break;
2183                 default: s = "(?) "; break;
2184                 } s;}),
2185                 ep->irqs, stat_flg,
2186                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2187                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2188                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2189                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2190                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2191                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2192                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2193                 (stat_flg & UDC_STALL) ? "STALL " : "",
2194                 (stat_flg & UDC_NAK) ? "NAK " : "",
2195                 (stat_flg & UDC_ACK) ? "ACK " : "",
2196                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2197                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2198                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2199
2200         if (list_empty (&ep->queue))
2201                 seq_printf(s, "\t(queue empty)\n");
2202         else
2203                 list_for_each_entry (req, &ep->queue, queue) {
2204                         unsigned        length = req->req.actual;
2205
2206                         if (use_dma && buf[0]) {
2207                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2208                                                 ? dma_src_len : dma_dest_len)
2209                                         (ep, req->req.dma + length);
2210                                 buf[0] = 0;
2211                         }
2212                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2213                                         &req->req, length,
2214                                         req->req.length, req->req.buf);
2215                 }
2216 }
2217
2218 static char *trx_mode(unsigned m, int enabled)
2219 {
2220         switch (m) {
2221         case 0:         return enabled ? "*6wire" : "unused";
2222         case 1:         return "4wire";
2223         case 2:         return "3wire";
2224         case 3:         return "6wire";
2225         default:        return "unknown";
2226         }
2227 }
2228
2229 static int proc_otg_show(struct seq_file *s)
2230 {
2231         u32             tmp;
2232         u32             trans;
2233
2234         tmp = OTG_REV_REG;
2235         trans = USB_TRANSCEIVER_CTRL_REG;
2236         seq_printf(s, "\nOTG rev %d.%d, transceiver_ctrl %05x\n",
2237                 tmp >> 4, tmp & 0xf, trans);
2238         tmp = OTG_SYSCON_1_REG;
2239         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2240                         FOURBITS "\n", tmp,
2241                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2242                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2243                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2244                         ? "internal"
2245                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2246                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2247                 (tmp & HST_IDLE_EN) ? " !host" : "",
2248                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2249                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2250         tmp = OTG_SYSCON_2_REG;
2251         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2252                         " b_ase_brst=%d hmc=%d\n", tmp,
2253                 (tmp & OTG_EN) ? " otg_en" : "",
2254                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2255                 // much more SRP stuff
2256                 (tmp & SRP_DATA) ? " srp_data" : "",
2257                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2258                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2259                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2260                 (tmp & UHOST_EN) ? " uhost_en" : "",
2261                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2262                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2263                 B_ASE_BRST(tmp),
2264                 OTG_HMC(tmp));
2265         tmp = OTG_CTRL_REG;
2266         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2267                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2268                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2269                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2270                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2271                 (tmp & OTG_ID) ? " id" : "",
2272                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2273                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2274                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2275                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2276                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2277                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2278                 (tmp & OTG_PULLDOWN) ? " down" : "",
2279                 (tmp & OTG_PULLUP) ? " up" : "",
2280                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2281                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2282                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2283                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2284                 );
2285         tmp = OTG_IRQ_EN_REG;
2286         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2287         tmp = OTG_IRQ_SRC_REG;
2288         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2289         tmp = OTG_OUTCTRL_REG;
2290         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2291         tmp = OTG_TEST_REG;
2292         seq_printf(s, "otg_test    %04x" "\n", tmp);
2293         return 0;
2294 }
2295
2296 static int proc_udc_show(struct seq_file *s, void *_)
2297 {
2298         u32             tmp;
2299         struct omap_ep  *ep;
2300         unsigned long   flags;
2301
2302         spin_lock_irqsave(&udc->lock, flags);
2303
2304         seq_printf(s, "%s, version: " DRIVER_VERSION
2305 #ifdef  USE_ISO
2306                 " (iso)"
2307 #endif
2308                 "%s\n",
2309                 driver_desc,
2310                 use_dma ?  " (dma)" : "");
2311
2312         tmp = UDC_REV_REG & 0xff; 
2313         seq_printf(s,
2314                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2315                 "hmc %d, transceiver %s\n",
2316                 tmp >> 4, tmp & 0xf,
2317                 fifo_mode,
2318                 udc->driver ? udc->driver->driver.name : "(none)",
2319                 HMC,
2320                 udc->transceiver ? udc->transceiver->label : "(none)");
2321         seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2322                 __REG16(ULPD_CLOCK_CTRL),
2323                 __REG16(ULPD_SOFT_REQ),
2324                 __REG16(ULPD_STATUS_REQ));
2325
2326         /* OTG controller registers */
2327         if (!cpu_is_omap15xx())
2328                 proc_otg_show(s);
2329
2330         tmp = UDC_SYSCON1_REG;
2331         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2332                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2333                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2334                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2335                 (tmp & UDC_NAK_EN) ? " nak" : "",
2336                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2337                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2338                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2339                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2340         // syscon2 is write-only
2341
2342         /* UDC controller registers */
2343         if (!(tmp & UDC_PULLUP_EN)) {
2344                 seq_printf(s, "(suspended)\n");
2345                 spin_unlock_irqrestore(&udc->lock, flags);
2346                 return 0;
2347         }
2348
2349         tmp = UDC_DEVSTAT_REG;
2350         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2351                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2352                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2353                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2354                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2355                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2356                 (tmp & UDC_SUS) ? " SUS" : "",
2357                 (tmp & UDC_CFG) ? " CFG" : "",
2358                 (tmp & UDC_ADD) ? " ADD" : "",
2359                 (tmp & UDC_DEF) ? " DEF" : "",
2360                 (tmp & UDC_ATT) ? " ATT" : "");
2361         seq_printf(s, "sof         %04x\n", UDC_SOF_REG);
2362         tmp = UDC_IRQ_EN_REG;
2363         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2364                 (tmp & UDC_SOF_IE) ? " sof" : "",
2365                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2366                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2367                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2368                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2369         tmp = UDC_IRQ_SRC_REG;
2370         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2371                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2372                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2373                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2374                 (tmp & UDC_SOF) ? " sof" : "",
2375                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2376                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2377                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2378                 (tmp & UDC_SETUP) ? " setup" : "",
2379                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2380                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2381         if (use_dma) {
2382                 unsigned i;
2383
2384                 tmp = UDC_DMA_IRQ_EN_REG;
2385                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2386                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2387                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2388                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2389
2390                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2391                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2392                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2393
2394                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2395                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2396                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2397
2398                 tmp = UDC_RXDMA_CFG_REG;
2399                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2400                 if (tmp) {
2401                         for (i = 0; i < 3; i++) {
2402                                 if ((tmp & (0x0f << (i * 4))) == 0)
2403                                         continue;
2404                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2405                                                 UDC_RXDMA_REG(i + 1));
2406                         }
2407                 }
2408                 tmp = UDC_TXDMA_CFG_REG;
2409                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2410                 if (tmp) {
2411                         for (i = 0; i < 3; i++) {
2412                                 if (!(tmp & (0x0f << (i * 4))))
2413                                         continue;
2414                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2415                                                 UDC_TXDMA_REG(i + 1));
2416                         }
2417                 }
2418         }
2419
2420         tmp = UDC_DEVSTAT_REG;
2421         if (tmp & UDC_ATT) {
2422                 proc_ep_show(s, &udc->ep[0]);
2423                 if (tmp & UDC_ADD) {
2424                         list_for_each_entry (ep, &udc->gadget.ep_list,
2425                                         ep.ep_list) {
2426                                 if (ep->desc)
2427                                         proc_ep_show(s, ep);
2428                         }
2429                 }
2430         }
2431         spin_unlock_irqrestore(&udc->lock, flags);
2432         return 0;
2433 }
2434
2435 static int proc_udc_open(struct inode *inode, struct file *file)
2436 {
2437         return single_open(file, proc_udc_show, NULL);
2438 }
2439
2440 static struct file_operations proc_ops = {
2441         .open           = proc_udc_open,
2442         .read           = seq_read,
2443         .llseek         = seq_lseek,
2444         .release        = single_release,
2445 };
2446
2447 static void create_proc_file(void)
2448 {
2449         struct proc_dir_entry *pde;
2450
2451         pde = create_proc_entry (proc_filename, 0, NULL);
2452         if (pde)
2453                 pde->proc_fops = &proc_ops;
2454 }
2455
2456 static void remove_proc_file(void)
2457 {
2458         remove_proc_entry(proc_filename, NULL);
2459 }
2460
2461 #else
2462
2463 static inline void create_proc_file(void) {}
2464 static inline void remove_proc_file(void) {}
2465
2466 #endif
2467
2468 /*-------------------------------------------------------------------------*/
2469
2470 /* Before this controller can enumerate, we need to pick an endpoint
2471  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2472  * buffer space among the endpoints we'll be operating.
2473  *
2474  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2475  * UDC_SYSCON_1_REG.CFG_LOCK is set can now work.  We won't use that
2476  * capability yet though.
2477  */
2478 static unsigned __init
2479 omap_ep_setup(char *name, u8 addr, u8 type,
2480                 unsigned buf, unsigned maxp, int dbuf)
2481 {
2482         struct omap_ep  *ep;
2483         u16             epn_rxtx = 0;
2484
2485         /* OUT endpoints first, then IN */
2486         ep = &udc->ep[addr & 0xf];
2487         if (addr & USB_DIR_IN)
2488                 ep += 16;
2489
2490         /* in case of ep init table bugs */
2491         BUG_ON(ep->name[0]);
2492
2493         /* chip setup ... bit values are same for IN, OUT */
2494         if (type == USB_ENDPOINT_XFER_ISOC) {
2495                 switch (maxp) {
2496                 case 8:         epn_rxtx = 0 << 12; break;
2497                 case 16:        epn_rxtx = 1 << 12; break;
2498                 case 32:        epn_rxtx = 2 << 12; break;
2499                 case 64:        epn_rxtx = 3 << 12; break;
2500                 case 128:       epn_rxtx = 4 << 12; break;
2501                 case 256:       epn_rxtx = 5 << 12; break;
2502                 case 512:       epn_rxtx = 6 << 12; break;
2503                 default:        BUG();
2504                 }
2505                 epn_rxtx |= UDC_EPN_RX_ISO;
2506                 dbuf = 1;
2507         } else {
2508                 /* double-buffering "not supported" on 15xx,
2509                  * and ignored for PIO-IN on 16xx
2510                  */
2511                 if (!use_dma || cpu_is_omap15xx())
2512                         dbuf = 0;
2513
2514                 switch (maxp) {
2515                 case 8:         epn_rxtx = 0 << 12; break;
2516                 case 16:        epn_rxtx = 1 << 12; break;
2517                 case 32:        epn_rxtx = 2 << 12; break;
2518                 case 64:        epn_rxtx = 3 << 12; break;
2519                 default:        BUG();
2520                 }
2521                 if (dbuf && addr)
2522                         epn_rxtx |= UDC_EPN_RX_DB;
2523                 init_timer(&ep->timer);
2524                 ep->timer.function = pio_out_timer;
2525                 ep->timer.data = (unsigned long) ep;
2526         }
2527         if (addr)
2528                 epn_rxtx |= UDC_EPN_RX_VALID;
2529         BUG_ON(buf & 0x07);
2530         epn_rxtx |= buf >> 3;
2531
2532         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2533                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2534
2535         if (addr & USB_DIR_IN)
2536                 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
2537         else
2538                 UDC_EP_RX_REG(addr) = epn_rxtx;
2539
2540         /* next endpoint's buffer starts after this one's */
2541         buf += maxp;
2542         if (dbuf)
2543                 buf += maxp;
2544         BUG_ON(buf > 2048);
2545
2546         /* set up driver data structures */
2547         BUG_ON(strlen(name) >= sizeof ep->name);
2548         strlcpy(ep->name, name, sizeof ep->name);
2549         INIT_LIST_HEAD(&ep->queue);
2550         INIT_LIST_HEAD(&ep->iso);
2551         ep->bEndpointAddress = addr;
2552         ep->bmAttributes = type;
2553         ep->double_buf = dbuf;
2554         ep->udc = udc; 
2555
2556         ep->ep.name = ep->name;
2557         ep->ep.ops = &omap_ep_ops;
2558         ep->ep.maxpacket = ep->maxpacket = maxp;
2559         list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2560
2561         return buf;
2562 }
2563
2564 static void omap_udc_release(struct device *dev)
2565 {
2566         complete(udc->done);
2567         kfree (udc);
2568         udc = NULL;
2569 }
2570
2571 static int __init
2572 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2573 {
2574         unsigned        tmp, buf;
2575
2576         /* abolish any previous hardware state */
2577         UDC_SYSCON1_REG = 0;
2578         UDC_IRQ_EN_REG = 0;
2579         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2580         UDC_DMA_IRQ_EN_REG = 0;
2581         UDC_RXDMA_CFG_REG = 0;
2582         UDC_TXDMA_CFG_REG = 0;
2583
2584         /* UDC_PULLUP_EN gates the chip clock */
2585         // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
2586
2587         udc = kzalloc(sizeof(*udc), SLAB_KERNEL);
2588         if (!udc)
2589                 return -ENOMEM;
2590
2591         spin_lock_init (&udc->lock);
2592
2593         udc->gadget.ops = &omap_gadget_ops;
2594         udc->gadget.ep0 = &udc->ep[0].ep;
2595         INIT_LIST_HEAD(&udc->gadget.ep_list);
2596         INIT_LIST_HEAD(&udc->iso);
2597         udc->gadget.speed = USB_SPEED_UNKNOWN;
2598         udc->gadget.name = driver_name;
2599
2600         device_initialize(&udc->gadget.dev);
2601         strcpy (udc->gadget.dev.bus_id, "gadget");
2602         udc->gadget.dev.release = omap_udc_release;
2603         udc->gadget.dev.parent = &odev->dev;
2604         if (use_dma)
2605                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2606
2607         udc->transceiver = xceiv;
2608
2609         /* ep0 is special; put it right after the SETUP buffer */
2610         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2611                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2612         list_del_init(&udc->ep[0].ep.ep_list);
2613
2614         /* initially disable all non-ep0 endpoints */
2615         for (tmp = 1; tmp < 15; tmp++) {
2616                 UDC_EP_RX_REG(tmp) = 0;
2617                 UDC_EP_TX_REG(tmp) = 0;
2618         }
2619
2620 #define OMAP_BULK_EP(name,addr) \
2621         buf = omap_ep_setup(name "-bulk", addr, \
2622                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2623 #define OMAP_INT_EP(name,addr, maxp) \
2624         buf = omap_ep_setup(name "-int", addr, \
2625                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2626 #define OMAP_ISO_EP(name,addr, maxp) \
2627         buf = omap_ep_setup(name "-iso", addr, \
2628                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2629
2630         switch (fifo_mode) {
2631         case 0:
2632                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2633                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2634                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2635                 break;
2636         case 1:
2637                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2638                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2639                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2640
2641                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2642                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2643                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2644
2645                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2646                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2647                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2648
2649                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2650                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2651                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2652
2653                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2654                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2655                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2656                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2657
2658                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2659                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2660                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2661                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2662
2663                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2664                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2665
2666                 break;
2667
2668 #ifdef  USE_ISO
2669         case 2:                 /* mixed iso/bulk */
2670                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2671                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2672                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2673                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2674
2675                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2676
2677                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2678                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2679                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2680                 break;
2681         case 3:                 /* mixed bulk/iso */
2682                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2683                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2684                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2685
2686                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2687                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2688                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2689
2690                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2691                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2692                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2693                 break;
2694 #endif
2695
2696         /* add more modes as needed */
2697
2698         default:
2699                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2700                 return -ENODEV;
2701         }
2702         UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
2703         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2704         return 0;
2705 }
2706
2707 static int __init omap_udc_probe(struct platform_device *pdev)
2708 {
2709         int                     status = -ENODEV;
2710         int                     hmc;
2711         struct otg_transceiver  *xceiv = NULL;
2712         const char              *type = NULL;
2713         struct omap_usb_config  *config = pdev->dev.platform_data;
2714
2715         /* NOTE:  "knows" the order of the resources! */
2716         if (!request_mem_region(pdev->resource[0].start, 
2717                         pdev->resource[0].end - pdev->resource[0].start + 1,
2718                         driver_name)) {
2719                 DBG("request_mem_region failed\n");
2720                 return -EBUSY;
2721         }
2722
2723         INFO("OMAP UDC rev %d.%d%s\n",
2724                 UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
2725                 config->otg ? ", Mini-AB" : "");
2726
2727         /* use the mode given to us by board init code */
2728         if (cpu_is_omap15xx()) {
2729                 hmc = HMC_1510;
2730                 type = "(unknown)";
2731
2732                 if (machine_is_omap_innovator()) {
2733                         /* just set up software VBUS detect, and then
2734                          * later rig it so we always report VBUS.
2735                          * FIXME without really sensing VBUS, we can't
2736                          * know when to turn PULLUP_EN on/off; and that
2737                          * means we always "need" the 48MHz clock.
2738                          */
2739                         u32 tmp = FUNC_MUX_CTRL_0_REG;
2740
2741                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
2742                         tmp |= VBUS_MODE_1510;
2743                         tmp &= ~VBUS_CTRL_1510;
2744                         FUNC_MUX_CTRL_0_REG = tmp;
2745                 }
2746         } else {
2747                 /* The transceiver may package some GPIO logic or handle
2748                  * loopback and/or transceiverless setup; if we find one,
2749                  * use it.  Except for OTG, we don't _need_ to talk to one;
2750                  * but not having one probably means no VBUS detection.
2751                  */
2752                 xceiv = otg_get_transceiver();
2753                 if (xceiv)
2754                         type = xceiv->label;
2755                 else if (config->otg) {
2756                         DBG("OTG requires external transceiver!\n");
2757                         goto cleanup0;
2758                 }
2759
2760                 hmc = HMC_1610;
2761                 switch (hmc) {
2762                 case 0:                 /* POWERUP DEFAULT == 0 */
2763                 case 4:
2764                 case 12:
2765                 case 20:
2766                         if (!cpu_is_omap1710()) {
2767                                 type = "integrated";
2768                                 break;
2769                         }
2770                         /* FALL THROUGH */
2771                 case 3:
2772                 case 11:
2773                 case 16:
2774                 case 19:
2775                 case 25:
2776                         if (!xceiv) {
2777                                 DBG("external transceiver not registered!\n");
2778                                 type = "unknown";
2779                         }
2780                         break;
2781                 case 21:                        /* internal loopback */
2782                         type = "loopback";
2783                         break;
2784                 case 14:                        /* transceiverless */
2785                         if (cpu_is_omap1710())
2786                                 goto bad_on_1710;
2787                         /* FALL THROUGH */
2788                 case 13:
2789                 case 15:
2790                         type = "no";
2791                         break;
2792
2793                 default:
2794 bad_on_1710:
2795                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2796                         goto cleanup0;
2797                 }
2798         }
2799         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2800
2801         /* a "gadget" abstracts/virtualizes the controller */
2802         status = omap_udc_setup(pdev, xceiv);
2803         if (status) {
2804                 goto cleanup0;
2805         }
2806         xceiv = NULL;
2807         // "udc" is now valid
2808         pullup_disable(udc);
2809 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2810         udc->gadget.is_otg = (config->otg != 0);
2811 #endif
2812
2813         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2814         if (UDC_REV_REG >= 0x61)
2815                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2816         else
2817                 udc->clr_halt = UDC_RESET_EP;
2818
2819         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2820         status = request_irq(pdev->resource[1].start, omap_udc_irq,
2821                         IRQF_SAMPLE_RANDOM, driver_name, udc);
2822         if (status != 0) {
2823                 ERR( "can't get irq %ld, err %d\n",
2824                         pdev->resource[1].start, status);
2825                 goto cleanup1;
2826         }
2827
2828         /* USB "non-iso" IRQ (PIO for all but ep0) */
2829         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2830                         IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2831         if (status != 0) {
2832                 ERR( "can't get irq %ld, err %d\n",
2833                         pdev->resource[2].start, status);
2834                 goto cleanup2;
2835         }
2836 #ifdef  USE_ISO
2837         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2838                         IRQF_DISABLED, "omap_udc iso", udc);
2839         if (status != 0) {
2840                 ERR("can't get irq %ld, err %d\n",
2841                         pdev->resource[3].start, status);
2842                 goto cleanup3;
2843         }
2844 #endif
2845
2846         create_proc_file();
2847         device_add(&udc->gadget.dev);
2848         return 0;
2849
2850 #ifdef  USE_ISO
2851 cleanup3:
2852         free_irq(pdev->resource[2].start, udc);
2853 #endif
2854
2855 cleanup2:
2856         free_irq(pdev->resource[1].start, udc);
2857
2858 cleanup1:
2859         kfree (udc);
2860         udc = NULL;
2861
2862 cleanup0:
2863         if (xceiv)
2864                 put_device(xceiv->dev);
2865         release_mem_region(pdev->resource[0].start,
2866                         pdev->resource[0].end - pdev->resource[0].start + 1);
2867         return status;
2868 }
2869
2870 static int __exit omap_udc_remove(struct platform_device *pdev)
2871 {
2872         DECLARE_COMPLETION(done);
2873
2874         if (!udc)
2875                 return -ENODEV;
2876
2877         udc->done = &done;
2878
2879         pullup_disable(udc);
2880         if (udc->transceiver) {
2881                 put_device(udc->transceiver->dev);
2882                 udc->transceiver = NULL;
2883         }
2884         UDC_SYSCON1_REG = 0;
2885
2886         remove_proc_file();
2887
2888 #ifdef  USE_ISO
2889         free_irq(pdev->resource[3].start, udc);
2890 #endif
2891         free_irq(pdev->resource[2].start, udc);
2892         free_irq(pdev->resource[1].start, udc);
2893
2894         release_mem_region(pdev->resource[0].start,
2895                         pdev->resource[0].end - pdev->resource[0].start + 1);
2896
2897         device_unregister(&udc->gadget.dev);
2898         wait_for_completion(&done);
2899
2900         return 0;
2901 }
2902
2903 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
2904  * system is forced into deep sleep
2905  *
2906  * REVISIT we should probably reject suspend requests when there's a host
2907  * session active, rather than disconnecting, at least on boards that can
2908  * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT).  And in any case, we need to
2909  * make host resumes and VBUS detection trigger OMAP wakeup events; that
2910  * may involve talking to an external transceiver (e.g. isp1301).
2911  */
2912
2913 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
2914 {
2915         u32     devstat;
2916
2917         devstat = UDC_DEVSTAT_REG;
2918
2919         /* we're requesting 48 MHz clock if the pullup is enabled
2920          * (== we're attached to the host) and we're not suspended,
2921          * which would prevent entry to deep sleep...
2922          */
2923         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
2924                 WARN("session active; suspend requires disconnect\n");
2925                 omap_pullup(&udc->gadget, 0);
2926         }
2927
2928         udc->gadget.dev.power.power_state = PMSG_SUSPEND;
2929         udc->gadget.dev.parent->power.power_state = PMSG_SUSPEND;
2930         return 0;
2931 }
2932
2933 static int omap_udc_resume(struct platform_device *dev)
2934 {
2935         DBG("resume + wakeup/SRP\n");
2936         omap_pullup(&udc->gadget, 1);
2937
2938         /* maybe the host would enumerate us if we nudged it */
2939         msleep(100);
2940         return omap_wakeup(&udc->gadget);
2941 }
2942
2943 /*-------------------------------------------------------------------------*/
2944
2945 static struct platform_driver udc_driver = {
2946         .probe          = omap_udc_probe,
2947         .remove         = __exit_p(omap_udc_remove),
2948         .suspend        = omap_udc_suspend,
2949         .resume         = omap_udc_resume,
2950         .driver         = {
2951                 .owner  = THIS_MODULE,
2952                 .name   = (char *) driver_name,
2953         },
2954 };
2955
2956 static int __init udc_init(void)
2957 {
2958         INFO("%s, version: " DRIVER_VERSION
2959 #ifdef  USE_ISO
2960                 " (iso)"
2961 #endif
2962                 "%s\n", driver_desc,
2963                 use_dma ?  " (dma)" : "");
2964         return platform_driver_register(&udc_driver);
2965 }
2966 module_init(udc_init);
2967
2968 static void __exit udc_exit(void)
2969 {
2970         platform_driver_unregister(&udc_driver);
2971 }
2972 module_exit(udc_exit);
2973
2974 MODULE_DESCRIPTION(DRIVER_DESC);
2975 MODULE_LICENSE("GPL");
2976