2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
5 * Copyright (C) 2010 Texas Instruments.
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
36 #include <linux/clk.h>
37 #include <linux/serial_core.h>
38 #include <linux/irq.h>
39 #include <linux/pm_runtime.h>
41 #include <linux/gpio.h>
43 #include <plat/dmtimer.h>
44 #include <plat/omap-serial.h>
46 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
48 #define OMAP_UART_REV_42 0x0402
49 #define OMAP_UART_REV_46 0x0406
50 #define OMAP_UART_REV_52 0x0502
51 #define OMAP_UART_REV_63 0x0603
53 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
55 /* SCR register bitmasks */
56 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
58 /* FCR register bitmasks */
59 #define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT 6
60 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
62 /* MVR register bitmasks */
63 #define OMAP_UART_MVR_SCHEME_SHIFT 30
65 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
66 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
67 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
69 #define OMAP_UART_MVR_MAJ_MASK 0x700
70 #define OMAP_UART_MVR_MAJ_SHIFT 8
71 #define OMAP_UART_MVR_MIN_MASK 0x3f
73 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
75 /* Forward declaration of functions */
76 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
78 static struct workqueue_struct *serial_omap_uart_wq;
80 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
82 offset <<= up->port.regshift;
83 return readw(up->port.membase + offset);
86 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
88 offset <<= up->port.regshift;
89 writew(value, up->port.membase + offset);
92 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
94 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
95 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
96 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
97 serial_out(up, UART_FCR, 0);
100 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
102 struct omap_uart_port_info *pdata = up->dev->platform_data;
104 if (!pdata->get_context_loss_count)
107 return pdata->get_context_loss_count(up->dev);
110 static void serial_omap_set_forceidle(struct uart_omap_port *up)
112 struct omap_uart_port_info *pdata = up->dev->platform_data;
114 if (pdata->set_forceidle)
115 pdata->set_forceidle(up->dev);
118 static void serial_omap_set_noidle(struct uart_omap_port *up)
120 struct omap_uart_port_info *pdata = up->dev->platform_data;
122 if (pdata->set_noidle)
123 pdata->set_noidle(up->dev);
126 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
128 struct omap_uart_port_info *pdata = up->dev->platform_data;
130 if (pdata->enable_wakeup)
131 pdata->enable_wakeup(up->dev, enable);
135 * serial_omap_get_divisor - calculate divisor value
136 * @port: uart port info
137 * @baud: baudrate for which divisor needs to be calculated.
139 * We have written our own function to get the divisor so as to support
140 * 13x mode. 3Mbps Baudrate as an different divisor.
141 * Reference OMAP TRM Chapter 17:
142 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
143 * referring to oversampling - divisor value
144 * baudrate 460,800 to 3,686,400 all have divisor 13
145 * except 3,000,000 which has divisor value 16
148 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
150 unsigned int divisor;
152 if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
156 return port->uartclk/(baud * divisor);
159 static void serial_omap_enable_ms(struct uart_port *port)
161 struct uart_omap_port *up = to_uart_omap_port(port);
163 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
165 pm_runtime_get_sync(up->dev);
166 up->ier |= UART_IER_MSI;
167 serial_out(up, UART_IER, up->ier);
168 pm_runtime_mark_last_busy(up->dev);
169 pm_runtime_put_autosuspend(up->dev);
172 static void serial_omap_stop_tx(struct uart_port *port)
174 struct uart_omap_port *up = to_uart_omap_port(port);
176 pm_runtime_get_sync(up->dev);
177 if (up->ier & UART_IER_THRI) {
178 up->ier &= ~UART_IER_THRI;
179 serial_out(up, UART_IER, up->ier);
182 serial_omap_set_forceidle(up);
184 pm_runtime_mark_last_busy(up->dev);
185 pm_runtime_put_autosuspend(up->dev);
188 static void serial_omap_stop_rx(struct uart_port *port)
190 struct uart_omap_port *up = to_uart_omap_port(port);
192 pm_runtime_get_sync(up->dev);
193 up->ier &= ~UART_IER_RLSI;
194 up->port.read_status_mask &= ~UART_LSR_DR;
195 serial_out(up, UART_IER, up->ier);
196 pm_runtime_mark_last_busy(up->dev);
197 pm_runtime_put_autosuspend(up->dev);
200 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
202 struct circ_buf *xmit = &up->port.state->xmit;
205 if (!(lsr & UART_LSR_THRE))
208 if (up->port.x_char) {
209 serial_out(up, UART_TX, up->port.x_char);
210 up->port.icount.tx++;
214 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
215 serial_omap_stop_tx(&up->port);
218 count = up->port.fifosize / 4;
220 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
221 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
222 up->port.icount.tx++;
223 if (uart_circ_empty(xmit))
225 } while (--count > 0);
227 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
228 spin_unlock(&up->port.lock);
229 uart_write_wakeup(&up->port);
230 spin_lock(&up->port.lock);
233 if (uart_circ_empty(xmit))
234 serial_omap_stop_tx(&up->port);
237 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
239 if (!(up->ier & UART_IER_THRI)) {
240 up->ier |= UART_IER_THRI;
241 serial_out(up, UART_IER, up->ier);
245 static void serial_omap_start_tx(struct uart_port *port)
247 struct uart_omap_port *up = to_uart_omap_port(port);
249 pm_runtime_get_sync(up->dev);
250 serial_omap_enable_ier_thri(up);
251 serial_omap_set_noidle(up);
252 pm_runtime_mark_last_busy(up->dev);
253 pm_runtime_put_autosuspend(up->dev);
256 static unsigned int check_modem_status(struct uart_omap_port *up)
260 status = serial_in(up, UART_MSR);
261 status |= up->msr_saved_flags;
262 up->msr_saved_flags = 0;
263 if ((status & UART_MSR_ANY_DELTA) == 0)
266 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
267 up->port.state != NULL) {
268 if (status & UART_MSR_TERI)
269 up->port.icount.rng++;
270 if (status & UART_MSR_DDSR)
271 up->port.icount.dsr++;
272 if (status & UART_MSR_DDCD)
273 uart_handle_dcd_change
274 (&up->port, status & UART_MSR_DCD);
275 if (status & UART_MSR_DCTS)
276 uart_handle_cts_change
277 (&up->port, status & UART_MSR_CTS);
278 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
284 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
288 up->port.icount.rx++;
291 if (lsr & UART_LSR_BI) {
293 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
294 up->port.icount.brk++;
296 * We do the SysRQ and SAK checking
297 * here because otherwise the break
298 * may get masked by ignore_status_mask
299 * or read_status_mask.
301 if (uart_handle_break(&up->port))
306 if (lsr & UART_LSR_PE) {
308 up->port.icount.parity++;
311 if (lsr & UART_LSR_FE) {
313 up->port.icount.frame++;
316 if (lsr & UART_LSR_OE)
317 up->port.icount.overrun++;
319 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
320 if (up->port.line == up->port.cons->index) {
321 /* Recover the break flag from console xmit */
322 lsr |= up->lsr_break_flag;
325 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
328 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
330 unsigned char ch = 0;
333 if (!(lsr & UART_LSR_DR))
336 ch = serial_in(up, UART_RX);
338 up->port.icount.rx++;
340 if (uart_handle_sysrq_char(&up->port, ch))
343 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
347 * serial_omap_irq() - This handles the interrupt from one port
348 * @irq: uart port irq number
349 * @dev_id: uart port info
351 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
353 struct uart_omap_port *up = dev_id;
354 struct tty_struct *tty = up->port.state->port.tty;
355 unsigned int iir, lsr;
357 irqreturn_t ret = IRQ_NONE;
360 spin_lock(&up->port.lock);
361 pm_runtime_get_sync(up->dev);
364 iir = serial_in(up, UART_IIR);
365 if (iir & UART_IIR_NO_INT)
369 lsr = serial_in(up, UART_LSR);
371 /* extract IRQ type from IIR register */
376 check_modem_status(up);
379 transmit_chars(up, lsr);
381 case UART_IIR_RX_TIMEOUT:
384 serial_omap_rdi(up, lsr);
387 serial_omap_rlsi(up, lsr);
389 case UART_IIR_CTS_RTS_DSR:
390 /* simply try again */
397 } while (!(iir & UART_IIR_NO_INT) && max_count--);
399 spin_unlock(&up->port.lock);
401 tty_flip_buffer_push(tty);
403 pm_runtime_mark_last_busy(up->dev);
404 pm_runtime_put_autosuspend(up->dev);
405 up->port_activity = jiffies;
410 static unsigned int serial_omap_tx_empty(struct uart_port *port)
412 struct uart_omap_port *up = to_uart_omap_port(port);
413 unsigned long flags = 0;
414 unsigned int ret = 0;
416 pm_runtime_get_sync(up->dev);
417 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
418 spin_lock_irqsave(&up->port.lock, flags);
419 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
420 spin_unlock_irqrestore(&up->port.lock, flags);
421 pm_runtime_mark_last_busy(up->dev);
422 pm_runtime_put_autosuspend(up->dev);
426 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
428 struct uart_omap_port *up = to_uart_omap_port(port);
430 unsigned int ret = 0;
432 pm_runtime_get_sync(up->dev);
433 status = check_modem_status(up);
434 pm_runtime_mark_last_busy(up->dev);
435 pm_runtime_put_autosuspend(up->dev);
437 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
439 if (status & UART_MSR_DCD)
441 if (status & UART_MSR_RI)
443 if (status & UART_MSR_DSR)
445 if (status & UART_MSR_CTS)
450 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
452 struct uart_omap_port *up = to_uart_omap_port(port);
453 unsigned char mcr = 0;
455 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
456 if (mctrl & TIOCM_RTS)
458 if (mctrl & TIOCM_DTR)
460 if (mctrl & TIOCM_OUT1)
461 mcr |= UART_MCR_OUT1;
462 if (mctrl & TIOCM_OUT2)
463 mcr |= UART_MCR_OUT2;
464 if (mctrl & TIOCM_LOOP)
465 mcr |= UART_MCR_LOOP;
467 pm_runtime_get_sync(up->dev);
468 up->mcr = serial_in(up, UART_MCR);
470 serial_out(up, UART_MCR, up->mcr);
471 pm_runtime_mark_last_busy(up->dev);
472 pm_runtime_put_autosuspend(up->dev);
474 if (gpio_is_valid(up->DTR_gpio) &&
475 !!(mctrl & TIOCM_DTR) != up->DTR_active) {
476 up->DTR_active = !up->DTR_active;
477 if (gpio_cansleep(up->DTR_gpio))
478 schedule_work(&up->qos_work);
480 gpio_set_value(up->DTR_gpio,
481 up->DTR_active != up->DTR_inverted);
485 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
487 struct uart_omap_port *up = to_uart_omap_port(port);
488 unsigned long flags = 0;
490 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
491 pm_runtime_get_sync(up->dev);
492 spin_lock_irqsave(&up->port.lock, flags);
493 if (break_state == -1)
494 up->lcr |= UART_LCR_SBC;
496 up->lcr &= ~UART_LCR_SBC;
497 serial_out(up, UART_LCR, up->lcr);
498 spin_unlock_irqrestore(&up->port.lock, flags);
499 pm_runtime_mark_last_busy(up->dev);
500 pm_runtime_put_autosuspend(up->dev);
503 static int serial_omap_startup(struct uart_port *port)
505 struct uart_omap_port *up = to_uart_omap_port(port);
506 unsigned long flags = 0;
512 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
517 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
519 pm_runtime_get_sync(up->dev);
521 * Clear the FIFO buffers and disable them.
522 * (they will be reenabled in set_termios())
524 serial_omap_clear_fifos(up);
525 /* For Hardware flow control */
526 serial_out(up, UART_MCR, UART_MCR_RTS);
529 * Clear the interrupt registers.
531 (void) serial_in(up, UART_LSR);
532 if (serial_in(up, UART_LSR) & UART_LSR_DR)
533 (void) serial_in(up, UART_RX);
534 (void) serial_in(up, UART_IIR);
535 (void) serial_in(up, UART_MSR);
538 * Now, initialize the UART
540 serial_out(up, UART_LCR, UART_LCR_WLEN8);
541 spin_lock_irqsave(&up->port.lock, flags);
543 * Most PC uarts need OUT2 raised to enable interrupts.
545 up->port.mctrl |= TIOCM_OUT2;
546 serial_omap_set_mctrl(&up->port, up->port.mctrl);
547 spin_unlock_irqrestore(&up->port.lock, flags);
549 up->msr_saved_flags = 0;
551 * Finally, enable interrupts. Note: Modem status interrupts
552 * are set via set_termios(), which will be occurring imminently
553 * anyway, so we don't enable them here.
555 up->ier = UART_IER_RLSI | UART_IER_RDI;
556 serial_out(up, UART_IER, up->ier);
558 /* Enable module level wake up */
559 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
561 pm_runtime_mark_last_busy(up->dev);
562 pm_runtime_put_autosuspend(up->dev);
563 up->port_activity = jiffies;
567 static void serial_omap_shutdown(struct uart_port *port)
569 struct uart_omap_port *up = to_uart_omap_port(port);
570 unsigned long flags = 0;
572 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
574 pm_runtime_get_sync(up->dev);
576 * Disable interrupts from this port
579 serial_out(up, UART_IER, 0);
581 spin_lock_irqsave(&up->port.lock, flags);
582 up->port.mctrl &= ~TIOCM_OUT2;
583 serial_omap_set_mctrl(&up->port, up->port.mctrl);
584 spin_unlock_irqrestore(&up->port.lock, flags);
587 * Disable break condition and FIFOs
589 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
590 serial_omap_clear_fifos(up);
593 * Read data port to reset things, and then free the irq
595 if (serial_in(up, UART_LSR) & UART_LSR_DR)
596 (void) serial_in(up, UART_RX);
598 pm_runtime_mark_last_busy(up->dev);
599 pm_runtime_put_autosuspend(up->dev);
600 free_irq(up->port.irq, up);
604 serial_omap_configure_xonxoff
605 (struct uart_omap_port *up, struct ktermios *termios)
607 up->lcr = serial_in(up, UART_LCR);
608 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
609 up->efr = serial_in(up, UART_EFR);
610 serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
612 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
613 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
615 /* clear SW control mode bits */
616 up->efr &= OMAP_UART_SW_CLR;
620 * Enable XON/XOFF flow control on output.
621 * Transmit XON1, XOFF1
623 if (termios->c_iflag & IXON)
624 up->efr |= OMAP_UART_SW_TX;
628 * Enable XON/XOFF flow control on input.
629 * Receiver compares XON1, XOFF1.
631 if (termios->c_iflag & IXOFF)
632 up->efr |= OMAP_UART_SW_RX;
634 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
635 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
637 up->mcr = serial_in(up, UART_MCR);
641 * Enable any character to restart output.
642 * Operation resumes after receiving any
643 * character after recognition of the XOFF character
645 if (termios->c_iflag & IXANY)
646 up->mcr |= UART_MCR_XONANY;
648 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
649 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
650 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
651 /* Enable special char function UARTi.EFR_REG[5] and
652 * load the new software flow control mode IXON or IXOFF
653 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
655 serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
656 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
658 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
659 serial_out(up, UART_LCR, up->lcr);
662 static void serial_omap_uart_qos_work(struct work_struct *work)
664 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
667 pm_qos_update_request(&up->pm_qos_request, up->latency);
668 if (gpio_is_valid(up->DTR_gpio))
669 gpio_set_value_cansleep(up->DTR_gpio,
670 up->DTR_active != up->DTR_inverted);
674 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
675 struct ktermios *old)
677 struct uart_omap_port *up = to_uart_omap_port(port);
678 unsigned char cval = 0;
679 unsigned char efr = 0;
680 unsigned long flags = 0;
681 unsigned int baud, quot;
683 switch (termios->c_cflag & CSIZE) {
685 cval = UART_LCR_WLEN5;
688 cval = UART_LCR_WLEN6;
691 cval = UART_LCR_WLEN7;
695 cval = UART_LCR_WLEN8;
699 if (termios->c_cflag & CSTOPB)
700 cval |= UART_LCR_STOP;
701 if (termios->c_cflag & PARENB)
702 cval |= UART_LCR_PARITY;
703 if (!(termios->c_cflag & PARODD))
704 cval |= UART_LCR_EPAR;
707 * Ask the core to calculate the divisor for us.
710 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
711 quot = serial_omap_get_divisor(port, baud);
713 /* calculate wakeup latency constraint */
714 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
715 up->latency = up->calc_latency;
716 schedule_work(&up->qos_work);
718 up->dll = quot & 0xff;
720 up->mdr1 = UART_OMAP_MDR1_DISABLE;
722 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
723 UART_FCR_ENABLE_FIFO;
726 * Ok, we're now changing the port state. Do it with
727 * interrupts disabled.
729 pm_runtime_get_sync(up->dev);
730 spin_lock_irqsave(&up->port.lock, flags);
733 * Update the per-port timeout.
735 uart_update_timeout(port, termios->c_cflag, baud);
737 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
738 if (termios->c_iflag & INPCK)
739 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
740 if (termios->c_iflag & (BRKINT | PARMRK))
741 up->port.read_status_mask |= UART_LSR_BI;
744 * Characters to ignore
746 up->port.ignore_status_mask = 0;
747 if (termios->c_iflag & IGNPAR)
748 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
749 if (termios->c_iflag & IGNBRK) {
750 up->port.ignore_status_mask |= UART_LSR_BI;
752 * If we're ignoring parity and break indicators,
753 * ignore overruns too (for real raw support).
755 if (termios->c_iflag & IGNPAR)
756 up->port.ignore_status_mask |= UART_LSR_OE;
760 * ignore all characters if CREAD is not set
762 if ((termios->c_cflag & CREAD) == 0)
763 up->port.ignore_status_mask |= UART_LSR_DR;
766 * Modem status interrupts
768 up->ier &= ~UART_IER_MSI;
769 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
770 up->ier |= UART_IER_MSI;
771 serial_out(up, UART_IER, up->ier);
772 serial_out(up, UART_LCR, cval); /* reset DLAB */
774 up->scr = OMAP_UART_SCR_TX_EMPTY;
776 /* FIFOs and DMA Settings */
778 /* FCR can be changed only when the
779 * baud clock is not running
780 * DLL_REG and DLH_REG set to 0.
782 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
783 serial_out(up, UART_DLL, 0);
784 serial_out(up, UART_DLM, 0);
785 serial_out(up, UART_LCR, 0);
787 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
789 up->efr = serial_in(up, UART_EFR);
790 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
792 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
793 up->mcr = serial_in(up, UART_MCR);
794 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
795 /* FIFO ENABLE, DMA MODE */
797 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
799 /* Set receive FIFO threshold to 1 byte */
800 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
801 up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
803 serial_out(up, UART_FCR, up->fcr);
804 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
806 serial_out(up, UART_OMAP_SCR, up->scr);
808 serial_out(up, UART_EFR, up->efr);
809 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
810 serial_out(up, UART_MCR, up->mcr);
812 /* Protocol, Baud Rate, and Interrupt Settings */
814 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
815 serial_omap_mdr1_errataset(up, up->mdr1);
817 serial_out(up, UART_OMAP_MDR1, up->mdr1);
819 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
821 up->efr = serial_in(up, UART_EFR);
822 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
824 serial_out(up, UART_LCR, 0);
825 serial_out(up, UART_IER, 0);
826 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
828 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
829 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
831 serial_out(up, UART_LCR, 0);
832 serial_out(up, UART_IER, up->ier);
833 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
835 serial_out(up, UART_EFR, up->efr);
836 serial_out(up, UART_LCR, cval);
838 if (baud > 230400 && baud != 3000000)
839 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
841 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
843 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
844 serial_omap_mdr1_errataset(up, up->mdr1);
846 serial_out(up, UART_OMAP_MDR1, up->mdr1);
848 /* Hardware Flow Control Configuration */
850 if (termios->c_cflag & CRTSCTS) {
851 efr |= (UART_EFR_CTS | UART_EFR_RTS);
852 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
854 up->mcr = serial_in(up, UART_MCR);
855 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
857 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
858 up->efr = serial_in(up, UART_EFR);
859 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
861 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
862 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
863 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
864 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
865 serial_out(up, UART_LCR, cval);
868 serial_omap_set_mctrl(&up->port, up->port.mctrl);
869 /* Software Flow Control Configuration */
870 serial_omap_configure_xonxoff(up, termios);
872 spin_unlock_irqrestore(&up->port.lock, flags);
873 pm_runtime_mark_last_busy(up->dev);
874 pm_runtime_put_autosuspend(up->dev);
875 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
878 static int serial_omap_set_wake(struct uart_port *port, unsigned int state)
880 struct uart_omap_port *up = to_uart_omap_port(port);
882 serial_omap_enable_wakeup(up, state);
888 serial_omap_pm(struct uart_port *port, unsigned int state,
889 unsigned int oldstate)
891 struct uart_omap_port *up = to_uart_omap_port(port);
894 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
896 pm_runtime_get_sync(up->dev);
897 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
898 efr = serial_in(up, UART_EFR);
899 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
900 serial_out(up, UART_LCR, 0);
902 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
903 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
904 serial_out(up, UART_EFR, efr);
905 serial_out(up, UART_LCR, 0);
907 if (!device_may_wakeup(up->dev)) {
909 pm_runtime_forbid(up->dev);
911 pm_runtime_allow(up->dev);
914 pm_runtime_mark_last_busy(up->dev);
915 pm_runtime_put_autosuspend(up->dev);
918 static void serial_omap_release_port(struct uart_port *port)
920 dev_dbg(port->dev, "serial_omap_release_port+\n");
923 static int serial_omap_request_port(struct uart_port *port)
925 dev_dbg(port->dev, "serial_omap_request_port+\n");
929 static void serial_omap_config_port(struct uart_port *port, int flags)
931 struct uart_omap_port *up = to_uart_omap_port(port);
933 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
935 up->port.type = PORT_OMAP;
939 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
941 /* we don't want the core code to modify any port params */
942 dev_dbg(port->dev, "serial_omap_verify_port+\n");
947 serial_omap_type(struct uart_port *port)
949 struct uart_omap_port *up = to_uart_omap_port(port);
951 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
955 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
957 static inline void wait_for_xmitr(struct uart_omap_port *up)
959 unsigned int status, tmout = 10000;
961 /* Wait up to 10ms for the character(s) to be sent. */
963 status = serial_in(up, UART_LSR);
965 if (status & UART_LSR_BI)
966 up->lsr_break_flag = UART_LSR_BI;
971 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
973 /* Wait up to 1s for flow control if necessary */
974 if (up->port.flags & UPF_CONS_FLOW) {
976 for (tmout = 1000000; tmout; tmout--) {
977 unsigned int msr = serial_in(up, UART_MSR);
979 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
980 if (msr & UART_MSR_CTS)
988 #ifdef CONFIG_CONSOLE_POLL
990 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
992 struct uart_omap_port *up = to_uart_omap_port(port);
994 pm_runtime_get_sync(up->dev);
996 serial_out(up, UART_TX, ch);
997 pm_runtime_mark_last_busy(up->dev);
998 pm_runtime_put_autosuspend(up->dev);
1001 static int serial_omap_poll_get_char(struct uart_port *port)
1003 struct uart_omap_port *up = to_uart_omap_port(port);
1004 unsigned int status;
1006 pm_runtime_get_sync(up->dev);
1007 status = serial_in(up, UART_LSR);
1008 if (!(status & UART_LSR_DR))
1009 return NO_POLL_CHAR;
1011 status = serial_in(up, UART_RX);
1012 pm_runtime_mark_last_busy(up->dev);
1013 pm_runtime_put_autosuspend(up->dev);
1017 #endif /* CONFIG_CONSOLE_POLL */
1019 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1021 static struct uart_omap_port *serial_omap_console_ports[4];
1023 static struct uart_driver serial_omap_reg;
1025 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1027 struct uart_omap_port *up = to_uart_omap_port(port);
1030 serial_out(up, UART_TX, ch);
1034 serial_omap_console_write(struct console *co, const char *s,
1037 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1038 unsigned long flags;
1042 pm_runtime_get_sync(up->dev);
1044 local_irq_save(flags);
1047 else if (oops_in_progress)
1048 locked = spin_trylock(&up->port.lock);
1050 spin_lock(&up->port.lock);
1053 * First save the IER then disable the interrupts
1055 ier = serial_in(up, UART_IER);
1056 serial_out(up, UART_IER, 0);
1058 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1061 * Finally, wait for transmitter to become empty
1062 * and restore the IER
1065 serial_out(up, UART_IER, ier);
1067 * The receive handling will happen properly because the
1068 * receive ready bit will still be set; it is not cleared
1069 * on read. However, modem control will not, we must
1070 * call it if we have saved something in the saved flags
1071 * while processing with interrupts off.
1073 if (up->msr_saved_flags)
1074 check_modem_status(up);
1076 pm_runtime_mark_last_busy(up->dev);
1077 pm_runtime_put_autosuspend(up->dev);
1079 spin_unlock(&up->port.lock);
1080 local_irq_restore(flags);
1084 serial_omap_console_setup(struct console *co, char *options)
1086 struct uart_omap_port *up;
1092 if (serial_omap_console_ports[co->index] == NULL)
1094 up = serial_omap_console_ports[co->index];
1097 uart_parse_options(options, &baud, &parity, &bits, &flow);
1099 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1102 static struct console serial_omap_console = {
1103 .name = OMAP_SERIAL_NAME,
1104 .write = serial_omap_console_write,
1105 .device = uart_console_device,
1106 .setup = serial_omap_console_setup,
1107 .flags = CON_PRINTBUFFER,
1109 .data = &serial_omap_reg,
1112 static void serial_omap_add_console_port(struct uart_omap_port *up)
1114 serial_omap_console_ports[up->port.line] = up;
1117 #define OMAP_CONSOLE (&serial_omap_console)
1121 #define OMAP_CONSOLE NULL
1123 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1128 static struct uart_ops serial_omap_pops = {
1129 .tx_empty = serial_omap_tx_empty,
1130 .set_mctrl = serial_omap_set_mctrl,
1131 .get_mctrl = serial_omap_get_mctrl,
1132 .stop_tx = serial_omap_stop_tx,
1133 .start_tx = serial_omap_start_tx,
1134 .stop_rx = serial_omap_stop_rx,
1135 .enable_ms = serial_omap_enable_ms,
1136 .break_ctl = serial_omap_break_ctl,
1137 .startup = serial_omap_startup,
1138 .shutdown = serial_omap_shutdown,
1139 .set_termios = serial_omap_set_termios,
1140 .pm = serial_omap_pm,
1141 .set_wake = serial_omap_set_wake,
1142 .type = serial_omap_type,
1143 .release_port = serial_omap_release_port,
1144 .request_port = serial_omap_request_port,
1145 .config_port = serial_omap_config_port,
1146 .verify_port = serial_omap_verify_port,
1147 #ifdef CONFIG_CONSOLE_POLL
1148 .poll_put_char = serial_omap_poll_put_char,
1149 .poll_get_char = serial_omap_poll_get_char,
1153 static struct uart_driver serial_omap_reg = {
1154 .owner = THIS_MODULE,
1155 .driver_name = "OMAP-SERIAL",
1156 .dev_name = OMAP_SERIAL_NAME,
1157 .nr = OMAP_MAX_HSUART_PORTS,
1158 .cons = OMAP_CONSOLE,
1161 #ifdef CONFIG_PM_SLEEP
1162 static int serial_omap_suspend(struct device *dev)
1164 struct uart_omap_port *up = dev_get_drvdata(dev);
1167 uart_suspend_port(&serial_omap_reg, &up->port);
1168 flush_work_sync(&up->qos_work);
1174 static int serial_omap_resume(struct device *dev)
1176 struct uart_omap_port *up = dev_get_drvdata(dev);
1179 uart_resume_port(&serial_omap_reg, &up->port);
1184 static void __devinit omap_serial_fill_features_erratas(struct uart_omap_port *up)
1187 u16 revision, major, minor;
1189 mvr = serial_in(up, UART_OMAP_MVER);
1191 /* Check revision register scheme */
1192 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1195 case 0: /* Legacy Scheme: OMAP2/3 */
1196 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1197 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1198 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1199 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1202 /* New Scheme: OMAP4+ */
1203 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1204 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1205 OMAP_UART_MVR_MAJ_SHIFT;
1206 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1210 "Unknown %s revision, defaulting to highest\n",
1212 /* highest possible revision */
1217 /* normalize revision for the driver */
1218 revision = UART_BUILD_REVISION(major, minor);
1221 case OMAP_UART_REV_46:
1222 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1223 UART_ERRATA_i291_DMA_FORCEIDLE);
1225 case OMAP_UART_REV_52:
1226 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1227 UART_ERRATA_i291_DMA_FORCEIDLE);
1229 case OMAP_UART_REV_63:
1230 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1237 static __devinit struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1239 struct omap_uart_port_info *omap_up_info;
1241 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1243 return NULL; /* out of memory */
1245 of_property_read_u32(dev->of_node, "clock-frequency",
1246 &omap_up_info->uartclk);
1247 return omap_up_info;
1250 static int __devinit serial_omap_probe(struct platform_device *pdev)
1252 struct uart_omap_port *up;
1253 struct resource *mem, *irq;
1254 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1257 if (pdev->dev.of_node)
1258 omap_up_info = of_get_uart_port_info(&pdev->dev);
1260 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1262 dev_err(&pdev->dev, "no mem resource?\n");
1266 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1268 dev_err(&pdev->dev, "no irq resource?\n");
1272 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1273 pdev->dev.driver->name)) {
1274 dev_err(&pdev->dev, "memory region already claimed\n");
1278 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1279 omap_up_info->DTR_present) {
1280 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1283 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1284 omap_up_info->DTR_inverted);
1289 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1293 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1294 omap_up_info->DTR_present) {
1295 up->DTR_gpio = omap_up_info->DTR_gpio;
1296 up->DTR_inverted = omap_up_info->DTR_inverted;
1298 up->DTR_gpio = -EINVAL;
1301 up->dev = &pdev->dev;
1302 up->port.dev = &pdev->dev;
1303 up->port.type = PORT_OMAP;
1304 up->port.iotype = UPIO_MEM;
1305 up->port.irq = irq->start;
1307 up->port.regshift = 2;
1308 up->port.fifosize = 64;
1309 up->port.ops = &serial_omap_pops;
1311 if (pdev->dev.of_node)
1312 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1314 up->port.line = pdev->id;
1316 if (up->port.line < 0) {
1317 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1323 sprintf(up->name, "OMAP UART%d", up->port.line);
1324 up->port.mapbase = mem->start;
1325 up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1326 resource_size(mem));
1327 if (!up->port.membase) {
1328 dev_err(&pdev->dev, "can't ioremap UART\n");
1333 up->port.flags = omap_up_info->flags;
1334 up->port.uartclk = omap_up_info->uartclk;
1335 if (!up->port.uartclk) {
1336 up->port.uartclk = DEFAULT_CLK_SPEED;
1337 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1338 "%d\n", DEFAULT_CLK_SPEED);
1341 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1342 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1343 pm_qos_add_request(&up->pm_qos_request,
1344 PM_QOS_CPU_DMA_LATENCY, up->latency);
1345 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1346 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1348 platform_set_drvdata(pdev, up);
1349 pm_runtime_enable(&pdev->dev);
1350 pm_runtime_use_autosuspend(&pdev->dev);
1351 pm_runtime_set_autosuspend_delay(&pdev->dev,
1352 omap_up_info->autosuspend_timeout);
1354 pm_runtime_irq_safe(&pdev->dev);
1355 pm_runtime_get_sync(&pdev->dev);
1357 omap_serial_fill_features_erratas(up);
1359 ui[up->port.line] = up;
1360 serial_omap_add_console_port(up);
1362 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1366 pm_runtime_mark_last_busy(up->dev);
1367 pm_runtime_put_autosuspend(up->dev);
1371 pm_runtime_put(&pdev->dev);
1372 pm_runtime_disable(&pdev->dev);
1375 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1376 pdev->id, __func__, ret);
1380 static int __devexit serial_omap_remove(struct platform_device *dev)
1382 struct uart_omap_port *up = platform_get_drvdata(dev);
1384 pm_runtime_put_sync(up->dev);
1385 pm_runtime_disable(up->dev);
1386 uart_remove_one_port(&serial_omap_reg, &up->port);
1387 pm_qos_remove_request(&up->pm_qos_request);
1393 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1394 * The access to uart register after MDR1 Access
1395 * causes UART to corrupt data.
1398 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1399 * give 10 times as much
1401 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1405 serial_out(up, UART_OMAP_MDR1, mdr1);
1407 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1408 UART_FCR_CLEAR_RCVR);
1410 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1411 * TX_FIFO_E bit is 1.
1413 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1414 (UART_LSR_THRE | UART_LSR_DR))) {
1417 /* Should *never* happen. we warn and carry on */
1418 dev_crit(up->dev, "Errata i202: timedout %x\n",
1419 serial_in(up, UART_LSR));
1426 #ifdef CONFIG_PM_RUNTIME
1427 static void serial_omap_restore_context(struct uart_omap_port *up)
1429 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1430 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1432 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1434 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1435 serial_out(up, UART_EFR, UART_EFR_ECB);
1436 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1437 serial_out(up, UART_IER, 0x0);
1438 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1439 serial_out(up, UART_DLL, up->dll);
1440 serial_out(up, UART_DLM, up->dlh);
1441 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1442 serial_out(up, UART_IER, up->ier);
1443 serial_out(up, UART_FCR, up->fcr);
1444 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1445 serial_out(up, UART_MCR, up->mcr);
1446 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1447 serial_out(up, UART_OMAP_SCR, up->scr);
1448 serial_out(up, UART_EFR, up->efr);
1449 serial_out(up, UART_LCR, up->lcr);
1450 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1451 serial_omap_mdr1_errataset(up, up->mdr1);
1453 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1456 static int serial_omap_runtime_suspend(struct device *dev)
1458 struct uart_omap_port *up = dev_get_drvdata(dev);
1459 struct omap_uart_port_info *pdata = dev->platform_data;
1467 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1469 if (device_may_wakeup(dev)) {
1470 if (!up->wakeups_enabled) {
1471 serial_omap_enable_wakeup(up, true);
1472 up->wakeups_enabled = true;
1475 if (up->wakeups_enabled) {
1476 serial_omap_enable_wakeup(up, false);
1477 up->wakeups_enabled = false;
1481 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1482 schedule_work(&up->qos_work);
1487 static int serial_omap_runtime_resume(struct device *dev)
1489 struct uart_omap_port *up = dev_get_drvdata(dev);
1490 struct omap_uart_port_info *pdata = dev->platform_data;
1493 u32 loss_cnt = serial_omap_get_context_loss_count(up);
1495 if (up->context_loss_cnt != loss_cnt)
1496 serial_omap_restore_context(up);
1498 up->latency = up->calc_latency;
1499 schedule_work(&up->qos_work);
1506 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1507 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1508 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1509 serial_omap_runtime_resume, NULL)
1512 #if defined(CONFIG_OF)
1513 static const struct of_device_id omap_serial_of_match[] = {
1514 { .compatible = "ti,omap2-uart" },
1515 { .compatible = "ti,omap3-uart" },
1516 { .compatible = "ti,omap4-uart" },
1519 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1522 static struct platform_driver serial_omap_driver = {
1523 .probe = serial_omap_probe,
1524 .remove = __devexit_p(serial_omap_remove),
1526 .name = DRIVER_NAME,
1527 .pm = &serial_omap_dev_pm_ops,
1528 .of_match_table = of_match_ptr(omap_serial_of_match),
1532 static int __init serial_omap_init(void)
1536 ret = uart_register_driver(&serial_omap_reg);
1539 ret = platform_driver_register(&serial_omap_driver);
1541 uart_unregister_driver(&serial_omap_reg);
1545 static void __exit serial_omap_exit(void)
1547 platform_driver_unregister(&serial_omap_driver);
1548 uart_unregister_driver(&serial_omap_reg);
1551 module_init(serial_omap_init);
1552 module_exit(serial_omap_exit);
1554 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1555 MODULE_LICENSE("GPL");
1556 MODULE_AUTHOR("Texas Instruments Inc");