c8448e6f52e580b662d273fb56e8555b31f1e4bb
[linux-3.10.git] / drivers / tty / serial / lpc32xx_hs.c
1 /*
2  * High Speed Serial Ports on NXP LPC32xx SoC
3  *
4  * Authors: Kevin Wells <kevin.wells@nxp.com>
5  *          Roland Stigge <stigge@antcom.de>
6  *
7  * Copyright (C) 2010 NXP Semiconductors
8  * Copyright (C) 2012 Roland Stigge
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  */
20
21 #include <linux/module.h>
22 #include <linux/ioport.h>
23 #include <linux/init.h>
24 #include <linux/console.h>
25 #include <linux/sysrq.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/serial_core.h>
29 #include <linux/serial.h>
30 #include <linux/platform_device.h>
31 #include <linux/delay.h>
32 #include <linux/nmi.h>
33 #include <linux/io.h>
34 #include <linux/irq.h>
35 #include <linux/gpio.h>
36 #include <linux/of.h>
37 #include <mach/platform.h>
38 #include <mach/hardware.h>
39
40 /*
41  * High Speed UART register offsets
42  */
43 #define LPC32XX_HSUART_FIFO(x)                  ((x) + 0x00)
44 #define LPC32XX_HSUART_LEVEL(x)                 ((x) + 0x04)
45 #define LPC32XX_HSUART_IIR(x)                   ((x) + 0x08)
46 #define LPC32XX_HSUART_CTRL(x)                  ((x) + 0x0C)
47 #define LPC32XX_HSUART_RATE(x)                  ((x) + 0x10)
48
49 #define LPC32XX_HSU_BREAK_DATA                  (1 << 10)
50 #define LPC32XX_HSU_ERROR_DATA                  (1 << 9)
51 #define LPC32XX_HSU_RX_EMPTY                    (1 << 8)
52
53 #define LPC32XX_HSU_TX_LEV(n)                   (((n) >> 8) & 0xFF)
54 #define LPC32XX_HSU_RX_LEV(n)                   ((n) & 0xFF)
55
56 #define LPC32XX_HSU_TX_INT_SET                  (1 << 6)
57 #define LPC32XX_HSU_RX_OE_INT                   (1 << 5)
58 #define LPC32XX_HSU_BRK_INT                     (1 << 4)
59 #define LPC32XX_HSU_FE_INT                      (1 << 3)
60 #define LPC32XX_HSU_RX_TIMEOUT_INT              (1 << 2)
61 #define LPC32XX_HSU_RX_TRIG_INT                 (1 << 1)
62 #define LPC32XX_HSU_TX_INT                      (1 << 0)
63
64 #define LPC32XX_HSU_HRTS_INV                    (1 << 21)
65 #define LPC32XX_HSU_HRTS_TRIG_8B                (0x0 << 19)
66 #define LPC32XX_HSU_HRTS_TRIG_16B               (0x1 << 19)
67 #define LPC32XX_HSU_HRTS_TRIG_32B               (0x2 << 19)
68 #define LPC32XX_HSU_HRTS_TRIG_48B               (0x3 << 19)
69 #define LPC32XX_HSU_HRTS_EN                     (1 << 18)
70 #define LPC32XX_HSU_TMO_DISABLED                (0x0 << 16)
71 #define LPC32XX_HSU_TMO_INACT_4B                (0x1 << 16)
72 #define LPC32XX_HSU_TMO_INACT_8B                (0x2 << 16)
73 #define LPC32XX_HSU_TMO_INACT_16B               (0x3 << 16)
74 #define LPC32XX_HSU_HCTS_INV                    (1 << 15)
75 #define LPC32XX_HSU_HCTS_EN                     (1 << 14)
76 #define LPC32XX_HSU_OFFSET(n)                   ((n) << 9)
77 #define LPC32XX_HSU_BREAK                       (1 << 8)
78 #define LPC32XX_HSU_ERR_INT_EN                  (1 << 7)
79 #define LPC32XX_HSU_RX_INT_EN                   (1 << 6)
80 #define LPC32XX_HSU_TX_INT_EN                   (1 << 5)
81 #define LPC32XX_HSU_RX_TL1B                     (0x0 << 2)
82 #define LPC32XX_HSU_RX_TL4B                     (0x1 << 2)
83 #define LPC32XX_HSU_RX_TL8B                     (0x2 << 2)
84 #define LPC32XX_HSU_RX_TL16B                    (0x3 << 2)
85 #define LPC32XX_HSU_RX_TL32B                    (0x4 << 2)
86 #define LPC32XX_HSU_RX_TL48B                    (0x5 << 2)
87 #define LPC32XX_HSU_TX_TLEMPTY                  (0x0 << 0)
88 #define LPC32XX_HSU_TX_TL0B                     (0x0 << 0)
89 #define LPC32XX_HSU_TX_TL4B                     (0x1 << 0)
90 #define LPC32XX_HSU_TX_TL8B                     (0x2 << 0)
91 #define LPC32XX_HSU_TX_TL16B                    (0x3 << 0)
92
93 #define MODNAME "lpc32xx_hsuart"
94
95 struct lpc32xx_hsuart_port {
96         struct uart_port port;
97 };
98
99 #define FIFO_READ_LIMIT 128
100 #define MAX_PORTS 3
101 #define LPC32XX_TTY_NAME "ttyTX"
102 static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
103
104 #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
105 static void wait_for_xmit_empty(struct uart_port *port)
106 {
107         unsigned int timeout = 10000;
108
109         do {
110                 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
111                                                         port->membase))) == 0)
112                         break;
113                 if (--timeout == 0)
114                         break;
115                 udelay(1);
116         } while (1);
117 }
118
119 static void wait_for_xmit_ready(struct uart_port *port)
120 {
121         unsigned int timeout = 10000;
122
123         while (1) {
124                 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
125                                                         port->membase))) < 32)
126                         break;
127                 if (--timeout == 0)
128                         break;
129                 udelay(1);
130         }
131 }
132
133 static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch)
134 {
135         wait_for_xmit_ready(port);
136         writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
137 }
138
139 static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
140                                          unsigned int count)
141 {
142         struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
143         unsigned long flags;
144         int locked = 1;
145
146         touch_nmi_watchdog();
147         local_irq_save(flags);
148         if (up->port.sysrq)
149                 locked = 0;
150         else if (oops_in_progress)
151                 locked = spin_trylock(&up->port.lock);
152         else
153                 spin_lock(&up->port.lock);
154
155         uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar);
156         wait_for_xmit_empty(&up->port);
157
158         if (locked)
159                 spin_unlock(&up->port.lock);
160         local_irq_restore(flags);
161 }
162
163 static int __init lpc32xx_hsuart_console_setup(struct console *co,
164                                                char *options)
165 {
166         struct uart_port *port;
167         int baud = 115200;
168         int bits = 8;
169         int parity = 'n';
170         int flow = 'n';
171
172         if (co->index >= MAX_PORTS)
173                 co->index = 0;
174
175         port = &lpc32xx_hs_ports[co->index].port;
176         if (!port->membase)
177                 return -ENODEV;
178
179         if (options)
180                 uart_parse_options(options, &baud, &parity, &bits, &flow);
181
182         return uart_set_options(port, co, baud, parity, bits, flow);
183 }
184
185 static struct uart_driver lpc32xx_hsuart_reg;
186 static struct console lpc32xx_hsuart_console = {
187         .name           = LPC32XX_TTY_NAME,
188         .write          = lpc32xx_hsuart_console_write,
189         .device         = uart_console_device,
190         .setup          = lpc32xx_hsuart_console_setup,
191         .flags          = CON_PRINTBUFFER,
192         .index          = -1,
193         .data           = &lpc32xx_hsuart_reg,
194 };
195
196 static int __init lpc32xx_hsuart_console_init(void)
197 {
198         register_console(&lpc32xx_hsuart_console);
199         return 0;
200 }
201 console_initcall(lpc32xx_hsuart_console_init);
202
203 #define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
204 #else
205 #define LPC32XX_HSUART_CONSOLE NULL
206 #endif
207
208 static struct uart_driver lpc32xx_hs_reg = {
209         .owner          = THIS_MODULE,
210         .driver_name    = MODNAME,
211         .dev_name       = LPC32XX_TTY_NAME,
212         .nr             = MAX_PORTS,
213         .cons           = LPC32XX_HSUART_CONSOLE,
214 };
215 static int uarts_registered;
216
217 static unsigned int __serial_get_clock_div(unsigned long uartclk,
218                                            unsigned long rate)
219 {
220         u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
221         u32 rate_diff;
222
223         /* Find the closest divider to get the desired clock rate */
224         div = uartclk / rate;
225         goodrate = hsu_rate = (div / 14) - 1;
226         if (hsu_rate != 0)
227                 hsu_rate--;
228
229         /* Tweak divider */
230         l_hsu_rate = hsu_rate + 3;
231         rate_diff = 0xFFFFFFFF;
232
233         while (hsu_rate < l_hsu_rate) {
234                 comprate = uartclk / ((hsu_rate + 1) * 14);
235                 if (abs(comprate - rate) < rate_diff) {
236                         goodrate = hsu_rate;
237                         rate_diff = abs(comprate - rate);
238                 }
239
240                 hsu_rate++;
241         }
242         if (hsu_rate > 0xFF)
243                 hsu_rate = 0xFF;
244
245         return goodrate;
246 }
247
248 static void __serial_uart_flush(struct uart_port *port)
249 {
250         u32 tmp;
251         int cnt = 0;
252
253         while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
254                (cnt++ < FIFO_READ_LIMIT))
255                 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
256 }
257
258 static void __serial_lpc32xx_rx(struct uart_port *port)
259 {
260         struct tty_port *tport = &port->state->port;
261         unsigned int tmp, flag;
262
263         /* Read data from FIFO and push into terminal */
264         tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
265         while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
266                 flag = TTY_NORMAL;
267                 port->icount.rx++;
268
269                 if (tmp & LPC32XX_HSU_ERROR_DATA) {
270                         /* Framing error */
271                         writel(LPC32XX_HSU_FE_INT,
272                                LPC32XX_HSUART_IIR(port->membase));
273                         port->icount.frame++;
274                         flag = TTY_FRAME;
275                         tty_insert_flip_char(tport, 0, TTY_FRAME);
276                 }
277
278                 tty_insert_flip_char(tport, (tmp & 0xFF), flag);
279
280                 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
281         }
282         tty_flip_buffer_push(tport);
283 }
284
285 static void __serial_lpc32xx_tx(struct uart_port *port)
286 {
287         struct circ_buf *xmit = &port->state->xmit;
288         unsigned int tmp;
289
290         if (port->x_char) {
291                 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase));
292                 port->icount.tx++;
293                 port->x_char = 0;
294                 return;
295         }
296
297         if (uart_circ_empty(xmit) || uart_tx_stopped(port))
298                 goto exit_tx;
299
300         /* Transfer data */
301         while (LPC32XX_HSU_TX_LEV(readl(
302                 LPC32XX_HSUART_LEVEL(port->membase))) < 64) {
303                 writel((u32) xmit->buf[xmit->tail],
304                        LPC32XX_HSUART_FIFO(port->membase));
305                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
306                 port->icount.tx++;
307                 if (uart_circ_empty(xmit))
308                         break;
309         }
310
311         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
312                 uart_write_wakeup(port);
313
314 exit_tx:
315         if (uart_circ_empty(xmit)) {
316                 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
317                 tmp &= ~LPC32XX_HSU_TX_INT_EN;
318                 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
319         }
320 }
321
322 static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
323 {
324         struct uart_port *port = dev_id;
325         struct tty_port *port = &port->state->port;
326         struct tty_struct *tty = tty_port_tty_get(tport);
327         u32 status;
328
329         spin_lock(&port->lock);
330
331         /* Read UART status and clear latched interrupts */
332         status = readl(LPC32XX_HSUART_IIR(port->membase));
333
334         if (status & LPC32XX_HSU_BRK_INT) {
335                 /* Break received */
336                 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
337                 port->icount.brk++;
338                 uart_handle_break(port);
339         }
340
341         /* Framing error */
342         if (status & LPC32XX_HSU_FE_INT)
343                 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
344
345         if (status & LPC32XX_HSU_RX_OE_INT) {
346                 /* Receive FIFO overrun */
347                 writel(LPC32XX_HSU_RX_OE_INT,
348                        LPC32XX_HSUART_IIR(port->membase));
349                 port->icount.overrun++;
350                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
351                 if (tty) {
352                         tty_schedule_flip(tty);
353                 }
354         }
355
356         /* Data received? */
357         if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) {
358                 __serial_lpc32xx_rx(port);
359                 tty_flip_buffer_push(tport);
360         }
361
362         /* Transmit data request? */
363         if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
364                 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
365                 __serial_lpc32xx_tx(port);
366         }
367
368         spin_unlock(&port->lock);
369         tty_kref_put(tty);
370
371         return IRQ_HANDLED;
372 }
373
374 /* port->lock is not held.  */
375 static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
376 {
377         unsigned int ret = 0;
378
379         if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0)
380                 ret = TIOCSER_TEMT;
381
382         return ret;
383 }
384
385 /* port->lock held by caller.  */
386 static void serial_lpc32xx_set_mctrl(struct uart_port *port,
387                                      unsigned int mctrl)
388 {
389         /* No signals are supported on HS UARTs */
390 }
391
392 /* port->lock is held by caller and interrupts are disabled.  */
393 static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
394 {
395         /* No signals are supported on HS UARTs */
396         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
397 }
398
399 /* port->lock held by caller.  */
400 static void serial_lpc32xx_stop_tx(struct uart_port *port)
401 {
402         u32 tmp;
403
404         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
405         tmp &= ~LPC32XX_HSU_TX_INT_EN;
406         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
407 }
408
409 /* port->lock held by caller.  */
410 static void serial_lpc32xx_start_tx(struct uart_port *port)
411 {
412         u32 tmp;
413
414         __serial_lpc32xx_tx(port);
415         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
416         tmp |= LPC32XX_HSU_TX_INT_EN;
417         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
418 }
419
420 /* port->lock held by caller.  */
421 static void serial_lpc32xx_stop_rx(struct uart_port *port)
422 {
423         u32 tmp;
424
425         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
426         tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
427         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
428
429         writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
430                 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
431 }
432
433 /* port->lock held by caller.  */
434 static void serial_lpc32xx_enable_ms(struct uart_port *port)
435 {
436         /* Modem status is not supported */
437 }
438
439 /* port->lock is not held.  */
440 static void serial_lpc32xx_break_ctl(struct uart_port *port,
441                                      int break_state)
442 {
443         unsigned long flags;
444         u32 tmp;
445
446         spin_lock_irqsave(&port->lock, flags);
447         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
448         if (break_state != 0)
449                 tmp |= LPC32XX_HSU_BREAK;
450         else
451                 tmp &= ~LPC32XX_HSU_BREAK;
452         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
453         spin_unlock_irqrestore(&port->lock, flags);
454 }
455
456 /* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
457 static void lpc32xx_loopback_set(resource_size_t mapbase, int state)
458 {
459         int bit;
460         u32 tmp;
461
462         switch (mapbase) {
463         case LPC32XX_HS_UART1_BASE:
464                 bit = 0;
465                 break;
466         case LPC32XX_HS_UART2_BASE:
467                 bit = 1;
468                 break;
469         case LPC32XX_HS_UART7_BASE:
470                 bit = 6;
471                 break;
472         default:
473                 WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
474                 return;
475         }
476
477         tmp = readl(LPC32XX_UARTCTL_CLOOP);
478         if (state)
479                 tmp |= (1 << bit);
480         else
481                 tmp &= ~(1 << bit);
482         writel(tmp, LPC32XX_UARTCTL_CLOOP);
483 }
484
485 /* port->lock is not held.  */
486 static int serial_lpc32xx_startup(struct uart_port *port)
487 {
488         int retval;
489         unsigned long flags;
490         u32 tmp;
491
492         spin_lock_irqsave(&port->lock, flags);
493
494         __serial_uart_flush(port);
495
496         writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
497                 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
498                LPC32XX_HSUART_IIR(port->membase));
499
500         writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
501
502         /*
503          * Set receiver timeout, HSU offset of 20, no break, no interrupts,
504          * and default FIFO trigger levels
505          */
506         tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
507                 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
508         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
509
510         lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
511
512         spin_unlock_irqrestore(&port->lock, flags);
513
514         retval = request_irq(port->irq, serial_lpc32xx_interrupt,
515                              0, MODNAME, port);
516         if (!retval)
517                 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
518                        LPC32XX_HSUART_CTRL(port->membase));
519
520         return retval;
521 }
522
523 /* port->lock is not held.  */
524 static void serial_lpc32xx_shutdown(struct uart_port *port)
525 {
526         u32 tmp;
527         unsigned long flags;
528
529         spin_lock_irqsave(&port->lock, flags);
530
531         tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
532                 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
533         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
534
535         lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */
536
537         spin_unlock_irqrestore(&port->lock, flags);
538
539         free_irq(port->irq, port);
540 }
541
542 /* port->lock is not held.  */
543 static void serial_lpc32xx_set_termios(struct uart_port *port,
544                                        struct ktermios *termios,
545                                        struct ktermios *old)
546 {
547         unsigned long flags;
548         unsigned int baud, quot;
549         u32 tmp;
550
551         /* Always 8-bit, no parity, 1 stop bit */
552         termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
553         termios->c_cflag |= CS8;
554
555         termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
556
557         baud = uart_get_baud_rate(port, termios, old, 0,
558                                   port->uartclk / 14);
559
560         quot = __serial_get_clock_div(port->uartclk, baud);
561
562         spin_lock_irqsave(&port->lock, flags);
563
564         /* Ignore characters? */
565         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
566         if ((termios->c_cflag & CREAD) == 0)
567                 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
568         else
569                 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
570         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
571
572         writel(quot, LPC32XX_HSUART_RATE(port->membase));
573
574         uart_update_timeout(port, termios->c_cflag, baud);
575
576         spin_unlock_irqrestore(&port->lock, flags);
577
578         /* Don't rewrite B0 */
579         if (tty_termios_baud_rate(termios))
580                 tty_termios_encode_baud_rate(termios, baud, baud);
581 }
582
583 static const char *serial_lpc32xx_type(struct uart_port *port)
584 {
585         return MODNAME;
586 }
587
588 static void serial_lpc32xx_release_port(struct uart_port *port)
589 {
590         if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
591                 if (port->flags & UPF_IOREMAP) {
592                         iounmap(port->membase);
593                         port->membase = NULL;
594                 }
595
596                 release_mem_region(port->mapbase, SZ_4K);
597         }
598 }
599
600 static int serial_lpc32xx_request_port(struct uart_port *port)
601 {
602         int ret = -ENODEV;
603
604         if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
605                 ret = 0;
606
607                 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
608                         ret = -EBUSY;
609                 else if (port->flags & UPF_IOREMAP) {
610                         port->membase = ioremap(port->mapbase, SZ_4K);
611                         if (!port->membase) {
612                                 release_mem_region(port->mapbase, SZ_4K);
613                                 ret = -ENOMEM;
614                         }
615                 }
616         }
617
618         return ret;
619 }
620
621 static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
622 {
623         int ret;
624
625         ret = serial_lpc32xx_request_port(port);
626         if (ret < 0)
627                 return;
628         port->type = PORT_UART00;
629         port->fifosize = 64;
630
631         __serial_uart_flush(port);
632
633         writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
634                 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
635                LPC32XX_HSUART_IIR(port->membase));
636
637         writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
638
639         /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
640            and default FIFO trigger levels */
641         writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
642                LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
643                LPC32XX_HSUART_CTRL(port->membase));
644 }
645
646 static int serial_lpc32xx_verify_port(struct uart_port *port,
647                                       struct serial_struct *ser)
648 {
649         int ret = 0;
650
651         if (ser->type != PORT_UART00)
652                 ret = -EINVAL;
653
654         return ret;
655 }
656
657 static struct uart_ops serial_lpc32xx_pops = {
658         .tx_empty       = serial_lpc32xx_tx_empty,
659         .set_mctrl      = serial_lpc32xx_set_mctrl,
660         .get_mctrl      = serial_lpc32xx_get_mctrl,
661         .stop_tx        = serial_lpc32xx_stop_tx,
662         .start_tx       = serial_lpc32xx_start_tx,
663         .stop_rx        = serial_lpc32xx_stop_rx,
664         .enable_ms      = serial_lpc32xx_enable_ms,
665         .break_ctl      = serial_lpc32xx_break_ctl,
666         .startup        = serial_lpc32xx_startup,
667         .shutdown       = serial_lpc32xx_shutdown,
668         .set_termios    = serial_lpc32xx_set_termios,
669         .type           = serial_lpc32xx_type,
670         .release_port   = serial_lpc32xx_release_port,
671         .request_port   = serial_lpc32xx_request_port,
672         .config_port    = serial_lpc32xx_config_port,
673         .verify_port    = serial_lpc32xx_verify_port,
674 };
675
676 /*
677  * Register a set of serial devices attached to a platform device
678  */
679 static int serial_hs_lpc32xx_probe(struct platform_device *pdev)
680 {
681         struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered];
682         int ret = 0;
683         struct resource *res;
684
685         if (uarts_registered >= MAX_PORTS) {
686                 dev_err(&pdev->dev,
687                         "Error: Number of possible ports exceeded (%d)!\n",
688                         uarts_registered + 1);
689                 return -ENXIO;
690         }
691
692         memset(p, 0, sizeof(*p));
693
694         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
695         if (!res) {
696                 dev_err(&pdev->dev,
697                         "Error getting mem resource for HS UART port %d\n",
698                         uarts_registered);
699                 return -ENXIO;
700         }
701         p->port.mapbase = res->start;
702         p->port.membase = NULL;
703
704         p->port.irq = platform_get_irq(pdev, 0);
705         if (p->port.irq < 0) {
706                 dev_err(&pdev->dev, "Error getting irq for HS UART port %d\n",
707                         uarts_registered);
708                 return p->port.irq;
709         }
710
711         p->port.iotype = UPIO_MEM32;
712         p->port.uartclk = LPC32XX_MAIN_OSC_FREQ;
713         p->port.regshift = 2;
714         p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP;
715         p->port.dev = &pdev->dev;
716         p->port.ops = &serial_lpc32xx_pops;
717         p->port.line = uarts_registered++;
718         spin_lock_init(&p->port.lock);
719
720         /* send port to loopback mode by default */
721         lpc32xx_loopback_set(p->port.mapbase, 1);
722
723         ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port);
724
725         platform_set_drvdata(pdev, p);
726
727         return ret;
728 }
729
730 /*
731  * Remove serial ports registered against a platform device.
732  */
733 static int serial_hs_lpc32xx_remove(struct platform_device *pdev)
734 {
735         struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
736
737         uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
738
739         return 0;
740 }
741
742
743 #ifdef CONFIG_PM
744 static int serial_hs_lpc32xx_suspend(struct platform_device *pdev,
745                                      pm_message_t state)
746 {
747         struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
748
749         uart_suspend_port(&lpc32xx_hs_reg, &p->port);
750
751         return 0;
752 }
753
754 static int serial_hs_lpc32xx_resume(struct platform_device *pdev)
755 {
756         struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
757
758         uart_resume_port(&lpc32xx_hs_reg, &p->port);
759
760         return 0;
761 }
762 #else
763 #define serial_hs_lpc32xx_suspend       NULL
764 #define serial_hs_lpc32xx_resume        NULL
765 #endif
766
767 static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = {
768         { .compatible = "nxp,lpc3220-hsuart" },
769         { /* sentinel */ }
770 };
771
772 MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids);
773
774 static struct platform_driver serial_hs_lpc32xx_driver = {
775         .probe          = serial_hs_lpc32xx_probe,
776         .remove         = serial_hs_lpc32xx_remove,
777         .suspend        = serial_hs_lpc32xx_suspend,
778         .resume         = serial_hs_lpc32xx_resume,
779         .driver         = {
780                 .name   = MODNAME,
781                 .owner  = THIS_MODULE,
782                 .of_match_table = serial_hs_lpc32xx_dt_ids,
783         },
784 };
785
786 static int __init lpc32xx_hsuart_init(void)
787 {
788         int ret;
789
790         ret = uart_register_driver(&lpc32xx_hs_reg);
791         if (ret)
792                 return ret;
793
794         ret = platform_driver_register(&serial_hs_lpc32xx_driver);
795         if (ret)
796                 uart_unregister_driver(&lpc32xx_hs_reg);
797
798         return ret;
799 }
800
801 static void __exit lpc32xx_hsuart_exit(void)
802 {
803         platform_driver_unregister(&serial_hs_lpc32xx_driver);
804         uart_unregister_driver(&lpc32xx_hs_reg);
805 }
806
807 module_init(lpc32xx_hsuart_init);
808 module_exit(lpc32xx_hsuart_exit);
809
810 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
811 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
812 MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
813 MODULE_LICENSE("GPL");