TTY: switch tty_schedule_flip
[linux-3.10.git] / drivers / tty / serial / lpc32xx_hs.c
1 /*
2  * High Speed Serial Ports on NXP LPC32xx SoC
3  *
4  * Authors: Kevin Wells <kevin.wells@nxp.com>
5  *          Roland Stigge <stigge@antcom.de>
6  *
7  * Copyright (C) 2010 NXP Semiconductors
8  * Copyright (C) 2012 Roland Stigge
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  */
20
21 #include <linux/module.h>
22 #include <linux/ioport.h>
23 #include <linux/init.h>
24 #include <linux/console.h>
25 #include <linux/sysrq.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/serial_core.h>
29 #include <linux/serial.h>
30 #include <linux/platform_device.h>
31 #include <linux/delay.h>
32 #include <linux/nmi.h>
33 #include <linux/io.h>
34 #include <linux/irq.h>
35 #include <linux/gpio.h>
36 #include <linux/of.h>
37 #include <mach/platform.h>
38 #include <mach/hardware.h>
39
40 /*
41  * High Speed UART register offsets
42  */
43 #define LPC32XX_HSUART_FIFO(x)                  ((x) + 0x00)
44 #define LPC32XX_HSUART_LEVEL(x)                 ((x) + 0x04)
45 #define LPC32XX_HSUART_IIR(x)                   ((x) + 0x08)
46 #define LPC32XX_HSUART_CTRL(x)                  ((x) + 0x0C)
47 #define LPC32XX_HSUART_RATE(x)                  ((x) + 0x10)
48
49 #define LPC32XX_HSU_BREAK_DATA                  (1 << 10)
50 #define LPC32XX_HSU_ERROR_DATA                  (1 << 9)
51 #define LPC32XX_HSU_RX_EMPTY                    (1 << 8)
52
53 #define LPC32XX_HSU_TX_LEV(n)                   (((n) >> 8) & 0xFF)
54 #define LPC32XX_HSU_RX_LEV(n)                   ((n) & 0xFF)
55
56 #define LPC32XX_HSU_TX_INT_SET                  (1 << 6)
57 #define LPC32XX_HSU_RX_OE_INT                   (1 << 5)
58 #define LPC32XX_HSU_BRK_INT                     (1 << 4)
59 #define LPC32XX_HSU_FE_INT                      (1 << 3)
60 #define LPC32XX_HSU_RX_TIMEOUT_INT              (1 << 2)
61 #define LPC32XX_HSU_RX_TRIG_INT                 (1 << 1)
62 #define LPC32XX_HSU_TX_INT                      (1 << 0)
63
64 #define LPC32XX_HSU_HRTS_INV                    (1 << 21)
65 #define LPC32XX_HSU_HRTS_TRIG_8B                (0x0 << 19)
66 #define LPC32XX_HSU_HRTS_TRIG_16B               (0x1 << 19)
67 #define LPC32XX_HSU_HRTS_TRIG_32B               (0x2 << 19)
68 #define LPC32XX_HSU_HRTS_TRIG_48B               (0x3 << 19)
69 #define LPC32XX_HSU_HRTS_EN                     (1 << 18)
70 #define LPC32XX_HSU_TMO_DISABLED                (0x0 << 16)
71 #define LPC32XX_HSU_TMO_INACT_4B                (0x1 << 16)
72 #define LPC32XX_HSU_TMO_INACT_8B                (0x2 << 16)
73 #define LPC32XX_HSU_TMO_INACT_16B               (0x3 << 16)
74 #define LPC32XX_HSU_HCTS_INV                    (1 << 15)
75 #define LPC32XX_HSU_HCTS_EN                     (1 << 14)
76 #define LPC32XX_HSU_OFFSET(n)                   ((n) << 9)
77 #define LPC32XX_HSU_BREAK                       (1 << 8)
78 #define LPC32XX_HSU_ERR_INT_EN                  (1 << 7)
79 #define LPC32XX_HSU_RX_INT_EN                   (1 << 6)
80 #define LPC32XX_HSU_TX_INT_EN                   (1 << 5)
81 #define LPC32XX_HSU_RX_TL1B                     (0x0 << 2)
82 #define LPC32XX_HSU_RX_TL4B                     (0x1 << 2)
83 #define LPC32XX_HSU_RX_TL8B                     (0x2 << 2)
84 #define LPC32XX_HSU_RX_TL16B                    (0x3 << 2)
85 #define LPC32XX_HSU_RX_TL32B                    (0x4 << 2)
86 #define LPC32XX_HSU_RX_TL48B                    (0x5 << 2)
87 #define LPC32XX_HSU_TX_TLEMPTY                  (0x0 << 0)
88 #define LPC32XX_HSU_TX_TL0B                     (0x0 << 0)
89 #define LPC32XX_HSU_TX_TL4B                     (0x1 << 0)
90 #define LPC32XX_HSU_TX_TL8B                     (0x2 << 0)
91 #define LPC32XX_HSU_TX_TL16B                    (0x3 << 0)
92
93 #define MODNAME "lpc32xx_hsuart"
94
95 struct lpc32xx_hsuart_port {
96         struct uart_port port;
97 };
98
99 #define FIFO_READ_LIMIT 128
100 #define MAX_PORTS 3
101 #define LPC32XX_TTY_NAME "ttyTX"
102 static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
103
104 #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
105 static void wait_for_xmit_empty(struct uart_port *port)
106 {
107         unsigned int timeout = 10000;
108
109         do {
110                 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
111                                                         port->membase))) == 0)
112                         break;
113                 if (--timeout == 0)
114                         break;
115                 udelay(1);
116         } while (1);
117 }
118
119 static void wait_for_xmit_ready(struct uart_port *port)
120 {
121         unsigned int timeout = 10000;
122
123         while (1) {
124                 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
125                                                         port->membase))) < 32)
126                         break;
127                 if (--timeout == 0)
128                         break;
129                 udelay(1);
130         }
131 }
132
133 static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch)
134 {
135         wait_for_xmit_ready(port);
136         writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
137 }
138
139 static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
140                                          unsigned int count)
141 {
142         struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
143         unsigned long flags;
144         int locked = 1;
145
146         touch_nmi_watchdog();
147         local_irq_save(flags);
148         if (up->port.sysrq)
149                 locked = 0;
150         else if (oops_in_progress)
151                 locked = spin_trylock(&up->port.lock);
152         else
153                 spin_lock(&up->port.lock);
154
155         uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar);
156         wait_for_xmit_empty(&up->port);
157
158         if (locked)
159                 spin_unlock(&up->port.lock);
160         local_irq_restore(flags);
161 }
162
163 static int __init lpc32xx_hsuart_console_setup(struct console *co,
164                                                char *options)
165 {
166         struct uart_port *port;
167         int baud = 115200;
168         int bits = 8;
169         int parity = 'n';
170         int flow = 'n';
171
172         if (co->index >= MAX_PORTS)
173                 co->index = 0;
174
175         port = &lpc32xx_hs_ports[co->index].port;
176         if (!port->membase)
177                 return -ENODEV;
178
179         if (options)
180                 uart_parse_options(options, &baud, &parity, &bits, &flow);
181
182         return uart_set_options(port, co, baud, parity, bits, flow);
183 }
184
185 static struct uart_driver lpc32xx_hsuart_reg;
186 static struct console lpc32xx_hsuart_console = {
187         .name           = LPC32XX_TTY_NAME,
188         .write          = lpc32xx_hsuart_console_write,
189         .device         = uart_console_device,
190         .setup          = lpc32xx_hsuart_console_setup,
191         .flags          = CON_PRINTBUFFER,
192         .index          = -1,
193         .data           = &lpc32xx_hsuart_reg,
194 };
195
196 static int __init lpc32xx_hsuart_console_init(void)
197 {
198         register_console(&lpc32xx_hsuart_console);
199         return 0;
200 }
201 console_initcall(lpc32xx_hsuart_console_init);
202
203 #define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
204 #else
205 #define LPC32XX_HSUART_CONSOLE NULL
206 #endif
207
208 static struct uart_driver lpc32xx_hs_reg = {
209         .owner          = THIS_MODULE,
210         .driver_name    = MODNAME,
211         .dev_name       = LPC32XX_TTY_NAME,
212         .nr             = MAX_PORTS,
213         .cons           = LPC32XX_HSUART_CONSOLE,
214 };
215 static int uarts_registered;
216
217 static unsigned int __serial_get_clock_div(unsigned long uartclk,
218                                            unsigned long rate)
219 {
220         u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
221         u32 rate_diff;
222
223         /* Find the closest divider to get the desired clock rate */
224         div = uartclk / rate;
225         goodrate = hsu_rate = (div / 14) - 1;
226         if (hsu_rate != 0)
227                 hsu_rate--;
228
229         /* Tweak divider */
230         l_hsu_rate = hsu_rate + 3;
231         rate_diff = 0xFFFFFFFF;
232
233         while (hsu_rate < l_hsu_rate) {
234                 comprate = uartclk / ((hsu_rate + 1) * 14);
235                 if (abs(comprate - rate) < rate_diff) {
236                         goodrate = hsu_rate;
237                         rate_diff = abs(comprate - rate);
238                 }
239
240                 hsu_rate++;
241         }
242         if (hsu_rate > 0xFF)
243                 hsu_rate = 0xFF;
244
245         return goodrate;
246 }
247
248 static void __serial_uart_flush(struct uart_port *port)
249 {
250         u32 tmp;
251         int cnt = 0;
252
253         while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
254                (cnt++ < FIFO_READ_LIMIT))
255                 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
256 }
257
258 static void __serial_lpc32xx_rx(struct uart_port *port)
259 {
260         struct tty_port *tport = &port->state->port;
261         unsigned int tmp, flag;
262
263         /* Read data from FIFO and push into terminal */
264         tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
265         while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
266                 flag = TTY_NORMAL;
267                 port->icount.rx++;
268
269                 if (tmp & LPC32XX_HSU_ERROR_DATA) {
270                         /* Framing error */
271                         writel(LPC32XX_HSU_FE_INT,
272                                LPC32XX_HSUART_IIR(port->membase));
273                         port->icount.frame++;
274                         flag = TTY_FRAME;
275                         tty_insert_flip_char(tport, 0, TTY_FRAME);
276                 }
277
278                 tty_insert_flip_char(tport, (tmp & 0xFF), flag);
279
280                 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
281         }
282         tty_flip_buffer_push(tport);
283 }
284
285 static void __serial_lpc32xx_tx(struct uart_port *port)
286 {
287         struct circ_buf *xmit = &port->state->xmit;
288         unsigned int tmp;
289
290         if (port->x_char) {
291                 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase));
292                 port->icount.tx++;
293                 port->x_char = 0;
294                 return;
295         }
296
297         if (uart_circ_empty(xmit) || uart_tx_stopped(port))
298                 goto exit_tx;
299
300         /* Transfer data */
301         while (LPC32XX_HSU_TX_LEV(readl(
302                 LPC32XX_HSUART_LEVEL(port->membase))) < 64) {
303                 writel((u32) xmit->buf[xmit->tail],
304                        LPC32XX_HSUART_FIFO(port->membase));
305                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
306                 port->icount.tx++;
307                 if (uart_circ_empty(xmit))
308                         break;
309         }
310
311         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
312                 uart_write_wakeup(port);
313
314 exit_tx:
315         if (uart_circ_empty(xmit)) {
316                 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
317                 tmp &= ~LPC32XX_HSU_TX_INT_EN;
318                 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
319         }
320 }
321
322 static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
323 {
324         struct uart_port *port = dev_id;
325         struct tty_port *port = &port->state->port;
326         u32 status;
327
328         spin_lock(&port->lock);
329
330         /* Read UART status and clear latched interrupts */
331         status = readl(LPC32XX_HSUART_IIR(port->membase));
332
333         if (status & LPC32XX_HSU_BRK_INT) {
334                 /* Break received */
335                 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
336                 port->icount.brk++;
337                 uart_handle_break(port);
338         }
339
340         /* Framing error */
341         if (status & LPC32XX_HSU_FE_INT)
342                 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
343
344         if (status & LPC32XX_HSU_RX_OE_INT) {
345                 /* Receive FIFO overrun */
346                 writel(LPC32XX_HSU_RX_OE_INT,
347                        LPC32XX_HSUART_IIR(port->membase));
348                 port->icount.overrun++;
349                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
350                 tty_schedule_flip(tport);
351         }
352
353         /* Data received? */
354         if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) {
355                 __serial_lpc32xx_rx(port);
356                 tty_flip_buffer_push(tport);
357         }
358
359         /* Transmit data request? */
360         if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
361                 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
362                 __serial_lpc32xx_tx(port);
363         }
364
365         spin_unlock(&port->lock);
366
367         return IRQ_HANDLED;
368 }
369
370 /* port->lock is not held.  */
371 static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
372 {
373         unsigned int ret = 0;
374
375         if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0)
376                 ret = TIOCSER_TEMT;
377
378         return ret;
379 }
380
381 /* port->lock held by caller.  */
382 static void serial_lpc32xx_set_mctrl(struct uart_port *port,
383                                      unsigned int mctrl)
384 {
385         /* No signals are supported on HS UARTs */
386 }
387
388 /* port->lock is held by caller and interrupts are disabled.  */
389 static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
390 {
391         /* No signals are supported on HS UARTs */
392         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
393 }
394
395 /* port->lock held by caller.  */
396 static void serial_lpc32xx_stop_tx(struct uart_port *port)
397 {
398         u32 tmp;
399
400         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
401         tmp &= ~LPC32XX_HSU_TX_INT_EN;
402         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
403 }
404
405 /* port->lock held by caller.  */
406 static void serial_lpc32xx_start_tx(struct uart_port *port)
407 {
408         u32 tmp;
409
410         __serial_lpc32xx_tx(port);
411         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
412         tmp |= LPC32XX_HSU_TX_INT_EN;
413         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
414 }
415
416 /* port->lock held by caller.  */
417 static void serial_lpc32xx_stop_rx(struct uart_port *port)
418 {
419         u32 tmp;
420
421         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
422         tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
423         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
424
425         writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
426                 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
427 }
428
429 /* port->lock held by caller.  */
430 static void serial_lpc32xx_enable_ms(struct uart_port *port)
431 {
432         /* Modem status is not supported */
433 }
434
435 /* port->lock is not held.  */
436 static void serial_lpc32xx_break_ctl(struct uart_port *port,
437                                      int break_state)
438 {
439         unsigned long flags;
440         u32 tmp;
441
442         spin_lock_irqsave(&port->lock, flags);
443         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
444         if (break_state != 0)
445                 tmp |= LPC32XX_HSU_BREAK;
446         else
447                 tmp &= ~LPC32XX_HSU_BREAK;
448         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
449         spin_unlock_irqrestore(&port->lock, flags);
450 }
451
452 /* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
453 static void lpc32xx_loopback_set(resource_size_t mapbase, int state)
454 {
455         int bit;
456         u32 tmp;
457
458         switch (mapbase) {
459         case LPC32XX_HS_UART1_BASE:
460                 bit = 0;
461                 break;
462         case LPC32XX_HS_UART2_BASE:
463                 bit = 1;
464                 break;
465         case LPC32XX_HS_UART7_BASE:
466                 bit = 6;
467                 break;
468         default:
469                 WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
470                 return;
471         }
472
473         tmp = readl(LPC32XX_UARTCTL_CLOOP);
474         if (state)
475                 tmp |= (1 << bit);
476         else
477                 tmp &= ~(1 << bit);
478         writel(tmp, LPC32XX_UARTCTL_CLOOP);
479 }
480
481 /* port->lock is not held.  */
482 static int serial_lpc32xx_startup(struct uart_port *port)
483 {
484         int retval;
485         unsigned long flags;
486         u32 tmp;
487
488         spin_lock_irqsave(&port->lock, flags);
489
490         __serial_uart_flush(port);
491
492         writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
493                 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
494                LPC32XX_HSUART_IIR(port->membase));
495
496         writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
497
498         /*
499          * Set receiver timeout, HSU offset of 20, no break, no interrupts,
500          * and default FIFO trigger levels
501          */
502         tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
503                 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
504         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
505
506         lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
507
508         spin_unlock_irqrestore(&port->lock, flags);
509
510         retval = request_irq(port->irq, serial_lpc32xx_interrupt,
511                              0, MODNAME, port);
512         if (!retval)
513                 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
514                        LPC32XX_HSUART_CTRL(port->membase));
515
516         return retval;
517 }
518
519 /* port->lock is not held.  */
520 static void serial_lpc32xx_shutdown(struct uart_port *port)
521 {
522         u32 tmp;
523         unsigned long flags;
524
525         spin_lock_irqsave(&port->lock, flags);
526
527         tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
528                 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
529         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
530
531         lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */
532
533         spin_unlock_irqrestore(&port->lock, flags);
534
535         free_irq(port->irq, port);
536 }
537
538 /* port->lock is not held.  */
539 static void serial_lpc32xx_set_termios(struct uart_port *port,
540                                        struct ktermios *termios,
541                                        struct ktermios *old)
542 {
543         unsigned long flags;
544         unsigned int baud, quot;
545         u32 tmp;
546
547         /* Always 8-bit, no parity, 1 stop bit */
548         termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
549         termios->c_cflag |= CS8;
550
551         termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
552
553         baud = uart_get_baud_rate(port, termios, old, 0,
554                                   port->uartclk / 14);
555
556         quot = __serial_get_clock_div(port->uartclk, baud);
557
558         spin_lock_irqsave(&port->lock, flags);
559
560         /* Ignore characters? */
561         tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
562         if ((termios->c_cflag & CREAD) == 0)
563                 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
564         else
565                 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
566         writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
567
568         writel(quot, LPC32XX_HSUART_RATE(port->membase));
569
570         uart_update_timeout(port, termios->c_cflag, baud);
571
572         spin_unlock_irqrestore(&port->lock, flags);
573
574         /* Don't rewrite B0 */
575         if (tty_termios_baud_rate(termios))
576                 tty_termios_encode_baud_rate(termios, baud, baud);
577 }
578
579 static const char *serial_lpc32xx_type(struct uart_port *port)
580 {
581         return MODNAME;
582 }
583
584 static void serial_lpc32xx_release_port(struct uart_port *port)
585 {
586         if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
587                 if (port->flags & UPF_IOREMAP) {
588                         iounmap(port->membase);
589                         port->membase = NULL;
590                 }
591
592                 release_mem_region(port->mapbase, SZ_4K);
593         }
594 }
595
596 static int serial_lpc32xx_request_port(struct uart_port *port)
597 {
598         int ret = -ENODEV;
599
600         if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
601                 ret = 0;
602
603                 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
604                         ret = -EBUSY;
605                 else if (port->flags & UPF_IOREMAP) {
606                         port->membase = ioremap(port->mapbase, SZ_4K);
607                         if (!port->membase) {
608                                 release_mem_region(port->mapbase, SZ_4K);
609                                 ret = -ENOMEM;
610                         }
611                 }
612         }
613
614         return ret;
615 }
616
617 static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
618 {
619         int ret;
620
621         ret = serial_lpc32xx_request_port(port);
622         if (ret < 0)
623                 return;
624         port->type = PORT_UART00;
625         port->fifosize = 64;
626
627         __serial_uart_flush(port);
628
629         writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
630                 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
631                LPC32XX_HSUART_IIR(port->membase));
632
633         writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
634
635         /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
636            and default FIFO trigger levels */
637         writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
638                LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
639                LPC32XX_HSUART_CTRL(port->membase));
640 }
641
642 static int serial_lpc32xx_verify_port(struct uart_port *port,
643                                       struct serial_struct *ser)
644 {
645         int ret = 0;
646
647         if (ser->type != PORT_UART00)
648                 ret = -EINVAL;
649
650         return ret;
651 }
652
653 static struct uart_ops serial_lpc32xx_pops = {
654         .tx_empty       = serial_lpc32xx_tx_empty,
655         .set_mctrl      = serial_lpc32xx_set_mctrl,
656         .get_mctrl      = serial_lpc32xx_get_mctrl,
657         .stop_tx        = serial_lpc32xx_stop_tx,
658         .start_tx       = serial_lpc32xx_start_tx,
659         .stop_rx        = serial_lpc32xx_stop_rx,
660         .enable_ms      = serial_lpc32xx_enable_ms,
661         .break_ctl      = serial_lpc32xx_break_ctl,
662         .startup        = serial_lpc32xx_startup,
663         .shutdown       = serial_lpc32xx_shutdown,
664         .set_termios    = serial_lpc32xx_set_termios,
665         .type           = serial_lpc32xx_type,
666         .release_port   = serial_lpc32xx_release_port,
667         .request_port   = serial_lpc32xx_request_port,
668         .config_port    = serial_lpc32xx_config_port,
669         .verify_port    = serial_lpc32xx_verify_port,
670 };
671
672 /*
673  * Register a set of serial devices attached to a platform device
674  */
675 static int serial_hs_lpc32xx_probe(struct platform_device *pdev)
676 {
677         struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered];
678         int ret = 0;
679         struct resource *res;
680
681         if (uarts_registered >= MAX_PORTS) {
682                 dev_err(&pdev->dev,
683                         "Error: Number of possible ports exceeded (%d)!\n",
684                         uarts_registered + 1);
685                 return -ENXIO;
686         }
687
688         memset(p, 0, sizeof(*p));
689
690         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
691         if (!res) {
692                 dev_err(&pdev->dev,
693                         "Error getting mem resource for HS UART port %d\n",
694                         uarts_registered);
695                 return -ENXIO;
696         }
697         p->port.mapbase = res->start;
698         p->port.membase = NULL;
699
700         p->port.irq = platform_get_irq(pdev, 0);
701         if (p->port.irq < 0) {
702                 dev_err(&pdev->dev, "Error getting irq for HS UART port %d\n",
703                         uarts_registered);
704                 return p->port.irq;
705         }
706
707         p->port.iotype = UPIO_MEM32;
708         p->port.uartclk = LPC32XX_MAIN_OSC_FREQ;
709         p->port.regshift = 2;
710         p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP;
711         p->port.dev = &pdev->dev;
712         p->port.ops = &serial_lpc32xx_pops;
713         p->port.line = uarts_registered++;
714         spin_lock_init(&p->port.lock);
715
716         /* send port to loopback mode by default */
717         lpc32xx_loopback_set(p->port.mapbase, 1);
718
719         ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port);
720
721         platform_set_drvdata(pdev, p);
722
723         return ret;
724 }
725
726 /*
727  * Remove serial ports registered against a platform device.
728  */
729 static int serial_hs_lpc32xx_remove(struct platform_device *pdev)
730 {
731         struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
732
733         uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
734
735         return 0;
736 }
737
738
739 #ifdef CONFIG_PM
740 static int serial_hs_lpc32xx_suspend(struct platform_device *pdev,
741                                      pm_message_t state)
742 {
743         struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
744
745         uart_suspend_port(&lpc32xx_hs_reg, &p->port);
746
747         return 0;
748 }
749
750 static int serial_hs_lpc32xx_resume(struct platform_device *pdev)
751 {
752         struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
753
754         uart_resume_port(&lpc32xx_hs_reg, &p->port);
755
756         return 0;
757 }
758 #else
759 #define serial_hs_lpc32xx_suspend       NULL
760 #define serial_hs_lpc32xx_resume        NULL
761 #endif
762
763 static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = {
764         { .compatible = "nxp,lpc3220-hsuart" },
765         { /* sentinel */ }
766 };
767
768 MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids);
769
770 static struct platform_driver serial_hs_lpc32xx_driver = {
771         .probe          = serial_hs_lpc32xx_probe,
772         .remove         = serial_hs_lpc32xx_remove,
773         .suspend        = serial_hs_lpc32xx_suspend,
774         .resume         = serial_hs_lpc32xx_resume,
775         .driver         = {
776                 .name   = MODNAME,
777                 .owner  = THIS_MODULE,
778                 .of_match_table = serial_hs_lpc32xx_dt_ids,
779         },
780 };
781
782 static int __init lpc32xx_hsuart_init(void)
783 {
784         int ret;
785
786         ret = uart_register_driver(&lpc32xx_hs_reg);
787         if (ret)
788                 return ret;
789
790         ret = platform_driver_register(&serial_hs_lpc32xx_driver);
791         if (ret)
792                 uart_unregister_driver(&lpc32xx_hs_reg);
793
794         return ret;
795 }
796
797 static void __exit lpc32xx_hsuart_exit(void)
798 {
799         platform_driver_unregister(&serial_hs_lpc32xx_driver);
800         uart_unregister_driver(&lpc32xx_hs_reg);
801 }
802
803 module_init(lpc32xx_hsuart_init);
804 module_exit(lpc32xx_hsuart_exit);
805
806 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
807 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
808 MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
809 MODULE_LICENSE("GPL");