Revert "staging: iio: adc: palmas: add DT support"
[linux-3.10.git] / drivers / staging / iio / adc / palmas_gpadc.c
1 /*
2  * palmas-adc.c -- TI PALMAS GPADC.
3  *
4  * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
5  *
6  * Author: Pradeep Goudagunta <pgoudagunta@nvidia.com>
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation version 2.
11  *
12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
13  * whether express or implied; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20  * 02111-1307, USA
21  */
22 #include <linux/module.h>
23 #include <linux/err.h>
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/pm.h>
31 #include <linux/mfd/palmas.h>
32 #include <linux/completion.h>
33 #include <linux/iio/iio.h>
34 #include <linux/iio/machine.h>
35 #include <linux/iio/driver.h>
36
37 #define MOD_NAME "palmas-gpadc"
38 #define ADC_CONVERTION_TIMEOUT  (msecs_to_jiffies(5000))
39 #define TO_BE_CALCULATED 0
40
41 struct palmas_gpadc_info {
42 /* calibration codes and regs */
43         int x1;
44         int x2;
45         int v1;
46         int v2;
47         u8 trim1_reg;
48         u8 trim2_reg;
49         int gain;
50         int offset;
51         int gain_error;
52         bool is_correct_code;
53 };
54
55 #define PALMAS_ADC_INFO(_chan, _x1, _x2, _v1, _v2, _t1, _t2, _is_correct_code)\
56 [PALMAS_ADC_CH_##_chan] = {                                             \
57                 .x1 = _x1,                                              \
58                 .x2 = _x2,                                              \
59                 .v1 = _v1,                                              \
60                 .v2 = _v2,                                              \
61                 .gain = TO_BE_CALCULATED,                               \
62                 .offset = TO_BE_CALCULATED,                             \
63                 .gain_error = TO_BE_CALCULATED,                         \
64                 .trim1_reg = PALMAS_GPADC_TRIM##_t1,                    \
65                 .trim2_reg = PALMAS_GPADC_TRIM##_t2,                    \
66                 .is_correct_code = _is_correct_code                     \
67         }
68
69 static struct palmas_gpadc_info palmas_gpadc_info[] = {
70         PALMAS_ADC_INFO(IN0, 2064, 3112, 630, 950, 1, 2, false),
71         PALMAS_ADC_INFO(IN1, 2064, 3112, 630, 950, 1, 2, false),
72         PALMAS_ADC_INFO(IN2, 2064, 3112, 1260, 1900, 3, 4, false),
73         PALMAS_ADC_INFO(IN3, 2064, 3112, 630, 950, 1, 2, false),
74         PALMAS_ADC_INFO(IN4, 2064, 3112, 630, 950, 1, 2, false),
75         PALMAS_ADC_INFO(IN5, 2064, 3112, 630, 950, 1, 2, false),
76         PALMAS_ADC_INFO(IN6, 2064, 3112, 2520, 3800, 5, 6, false),
77         PALMAS_ADC_INFO(IN7, 2064, 3112, 2520, 3800, 7, 8, false),
78         PALMAS_ADC_INFO(IN8, 2064, 3112, 3150, 4750, 9, 10, false),
79         PALMAS_ADC_INFO(IN9, 2064, 3112, 5670, 8550, 11, 12, false),
80         PALMAS_ADC_INFO(IN10, 2064, 3112, 3465, 5225, 13, 14, false),
81         PALMAS_ADC_INFO(IN11, 0, 0, 0, 0, INVALID, INVALID, true),
82         PALMAS_ADC_INFO(IN12, 0, 0, 0, 0, INVALID, INVALID, true),
83         PALMAS_ADC_INFO(IN13, 0, 0, 0, 0, INVALID, INVALID, true),
84         PALMAS_ADC_INFO(IN14, 2064, 3112, 3645, 5225, 15, 16, false),
85         PALMAS_ADC_INFO(IN15, 0, 0, 0, 0, INVALID, INVALID, true),
86 };
87
88 struct palmas_gpadc {
89         struct device                   *dev;
90         struct palmas                   *palmas;
91         u8                              ch0_current;
92         u8                              ch3_current;
93         bool                            ch3_dual_current;
94         bool                            extended_delay;
95         int                             irq;
96         int                             irq_auto_0;
97         int                             irq_auto_1;
98         struct palmas_gpadc_info        *adc_info;
99         struct completion               conv_completion;
100         struct palmas_adc_wakeup_property wakeup1_data;
101         struct palmas_adc_wakeup_property wakeup2_data;
102         bool                            wakeup1_enable;
103         bool                            wakeup2_enable;
104         int                             auto_conversion_period;
105 };
106
107 /*
108  * GPADC lock issue in AUTO mode.
109  * Impact: In AUTO mode, GPADC conversion can be locked after disabling AUTO
110  *         mode feature.
111  * Details:
112  *      When the AUTO mode is the only conversion mode enabled, if the AUTO
113  *      mode feature is disabled with bit GPADC_AUTO_CTRL.  AUTO_CONV1_EN = 0
114  *      or bit GPADC_AUTO_CTRL.  AUTO_CONV0_EN = 0 during a conversion, the
115  *      conversion mechanism can be seen as locked meaning that all following
116  *      conversion will give 0 as a result.  Bit GPADC_STATUS.GPADC_AVAILABLE
117  *      will stay at 0 meaning that GPADC is busy.  An RT conversion can unlock
118  *      the GPADC.
119  *
120  * Workaround(s):
121  *      To avoid the lock mechanism, the workaround to follow before any stop
122  *      conversion request is:
123  *      Force the GPADC state machine to be ON by using the GPADC_CTRL1.
124  *              GPADC_FORCE bit = 1
125  *      Shutdown the GPADC AUTO conversion using
126  *              GPADC_AUTO_CTRL.SHUTDOWN_CONV[01] = 0.
127  *      After 100us, force the GPADC state machine to be OFF by using the
128  *              GPADC_CTRL1.  GPADC_FORCE bit = 0
129  */
130 static int palmas_disable_auto_conversion(struct palmas_gpadc *adc)
131 {
132         int ret;
133
134         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
135                         PALMAS_GPADC_CTRL1,
136                         PALMAS_GPADC_CTRL1_GPADC_FORCE,
137                         PALMAS_GPADC_CTRL1_GPADC_FORCE);
138         if (ret < 0) {
139                 dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
140                 return ret;
141         }
142
143         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
144                         PALMAS_GPADC_AUTO_CTRL,
145                         PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 |
146                         PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0,
147                         0);
148         if (ret < 0) {
149                 dev_err(adc->dev, "AUTO_CTRL update failed: %d\n", ret);
150                 return ret;
151         }
152
153         udelay(100);
154
155         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
156                         PALMAS_GPADC_CTRL1,
157                         PALMAS_GPADC_CTRL1_GPADC_FORCE, 0);
158         if (ret < 0) {
159                 dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
160                 return ret;
161         }
162         return 0;
163 }
164
165 static irqreturn_t palmas_gpadc_irq(int irq, void *data)
166 {
167         struct palmas_gpadc *adc = data;
168
169         complete(&adc->conv_completion);
170         return IRQ_HANDLED;
171 }
172
173 static irqreturn_t palmas_gpadc_irq_auto(int irq, void *data)
174 {
175         struct palmas_gpadc *adc = data;
176
177         dev_info(adc->dev, "Threshold interrupt %d occurs\n", irq);
178         palmas_disable_auto_conversion(adc);
179         return IRQ_HANDLED;
180 }
181
182 static int palmas_gpadc_start_mask_interrupt(struct palmas_gpadc *adc, int mask)
183 {
184         int ret;
185
186         if (!mask)
187                 ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
188                                         PALMAS_INT3_MASK,
189                                         PALMAS_INT3_MASK_GPADC_EOC_SW, 0);
190         else
191                 ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
192                                         PALMAS_INT3_MASK,
193                                         PALMAS_INT3_MASK_GPADC_EOC_SW,
194                                         PALMAS_INT3_MASK_GPADC_EOC_SW);
195         if (ret < 0)
196                 dev_err(adc->dev, "GPADC INT MASK update failed: %d\n", ret);
197
198         return ret;
199 }
200
201 static int palmas_gpadc_enable(struct palmas_gpadc *adc, int adc_chan,
202                                int enable)
203 {
204         unsigned int mask, val;
205         int ret;
206
207         if (enable) {
208                 val = (adc->extended_delay
209                         << PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT);
210                 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
211                                         PALMAS_GPADC_RT_CTRL,
212                                         PALMAS_GPADC_RT_CTRL_EXTEND_DELAY, val);
213                 if (ret < 0) {
214                         dev_err(adc->dev, "RT_CTRL update failed: %d\n", ret);
215                         return ret;
216                 }
217
218                 mask = (PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK |
219                         PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK |
220                         PALMAS_GPADC_CTRL1_GPADC_FORCE);
221                 val = (adc->ch0_current
222                         << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT);
223                 val |= (adc->ch3_current
224                         << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT);
225                 val |= PALMAS_GPADC_CTRL1_GPADC_FORCE;
226                 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
227                                 PALMAS_GPADC_CTRL1, mask, val);
228                 if (ret < 0) {
229                         dev_err(adc->dev,
230                                 "Failed to update current setting: %d\n", ret);
231                         return ret;
232                 }
233
234                 mask = (PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK |
235                         PALMAS_GPADC_SW_SELECT_SW_CONV_EN);
236                 val = (adc_chan | PALMAS_GPADC_SW_SELECT_SW_CONV_EN);
237                 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
238                                 PALMAS_GPADC_SW_SELECT, mask, val);
239                 if (ret < 0) {
240                         dev_err(adc->dev, "SW_SELECT update failed: %d\n", ret);
241                         return ret;
242                 }
243         } else {
244                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
245                                 PALMAS_GPADC_SW_SELECT, 0);
246                 if (ret < 0)
247                         dev_err(adc->dev, "SW_SELECT write failed: %d\n", ret);
248
249                 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
250                                 PALMAS_GPADC_CTRL1,
251                                 PALMAS_GPADC_CTRL1_GPADC_FORCE, 0);
252                 if (ret < 0) {
253                         dev_err(adc->dev, "CTRL1 update failed: %d\n", ret);
254                         return ret;
255                 }
256         }
257
258         return ret;
259 }
260
261 static int palmas_gpadc_read_prepare(struct palmas_gpadc *adc, int adc_chan)
262 {
263         int ret;
264
265         ret = palmas_gpadc_enable(adc, adc_chan, true);
266         if (ret < 0)
267                 return ret;
268
269         return palmas_gpadc_start_mask_interrupt(adc, 0);
270 }
271
272 static void palmas_gpadc_read_done(struct palmas_gpadc *adc, int adc_chan)
273 {
274         palmas_gpadc_start_mask_interrupt(adc, 1);
275         palmas_gpadc_enable(adc, adc_chan, false);
276 }
277
278 static int palmas_gpadc_calibrate(struct palmas_gpadc *adc, int adc_chan)
279 {
280         int k;
281         int d1;
282         int d2;
283         int ret;
284         int gain;
285         int x1 =  adc->adc_info[adc_chan].x1;
286         int x2 =  adc->adc_info[adc_chan].x2;
287         int v1 = adc->adc_info[adc_chan].v1;
288         int v2 = adc->adc_info[adc_chan].v2;
289
290         ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
291                                 adc->adc_info[adc_chan].trim1_reg, &d1);
292         if (ret < 0) {
293                 dev_err(adc->dev, "TRIM read failed: %d\n", ret);
294                 goto scrub;
295         }
296
297         ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
298                                 adc->adc_info[adc_chan].trim2_reg, &d2);
299         if (ret < 0) {
300                 dev_err(adc->dev, "TRIM read failed: %d\n", ret);
301                 goto scrub;
302         }
303
304         /*Gain error Calculation*/
305         k = (1000 + (1000 * (d2 - d1)) / (x2 - x1));
306
307         /*Gain Calculation*/
308         gain = ((v2 - v1) * 1000) / (x2 - x1);
309
310         adc->adc_info[adc_chan].gain_error = k;
311         adc->adc_info[adc_chan].gain = gain;
312         /*offset Calculation*/
313         adc->adc_info[adc_chan].offset = (d1 * 1000) - ((k - 1000) * x1);
314
315 scrub:
316         return ret;
317 }
318
319 static int palmas_gpadc_start_convertion(struct palmas_gpadc *adc, int adc_chan)
320 {
321         unsigned int val;
322         int ret;
323
324         INIT_COMPLETION(adc->conv_completion);
325         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
326                                 PALMAS_GPADC_SW_SELECT,
327                                 PALMAS_GPADC_SW_SELECT_SW_START_CONV0,
328                                 PALMAS_GPADC_SW_SELECT_SW_START_CONV0);
329         if (ret < 0) {
330                 dev_err(adc->dev, "ADC_SW_START write failed: %d\n", ret);
331                 return ret;
332         }
333
334         ret = wait_for_completion_timeout(&adc->conv_completion,
335                                 ADC_CONVERTION_TIMEOUT);
336         if (ret == 0) {
337                 dev_err(adc->dev, "ADC conversion not completed\n");
338                 ret = -ETIMEDOUT;
339                 return ret;
340         }
341
342         ret = palmas_bulk_read(adc->palmas, PALMAS_GPADC_BASE,
343                                 PALMAS_GPADC_SW_CONV0_LSB, &val, 2);
344         if (ret < 0) {
345                 dev_err(adc->dev, "ADCDATA read failed: %d\n", ret);
346                 return ret;
347         }
348
349         ret = (val & 0xFFF);
350         return ret;
351 }
352
353 static int palmas_gpadc_get_calibrated_code(struct palmas_gpadc *adc,
354                                                 int adc_chan, int val)
355 {
356         if (((val*1000) - adc->adc_info[adc_chan].offset) < 0) {
357                 dev_err(adc->dev, "No Input Connected\n");
358                 return 0;
359         }
360
361         if (!(adc->adc_info[adc_chan].is_correct_code))
362                 val  = ((val*1000) - adc->adc_info[adc_chan].offset) /
363                                         adc->adc_info[adc_chan].gain_error;
364
365         val = (val * adc->adc_info[adc_chan].gain) / 1000;
366         return val;
367 }
368
369 static int palmas_gpadc_read_raw(struct iio_dev *indio_dev,
370         struct iio_chan_spec const *chan, int *val, int *val2, long mask)
371 {
372         struct  palmas_gpadc *adc = iio_priv(indio_dev);
373         int adc_chan = chan->channel;
374         int ret = 0;
375
376         if (adc_chan > PALMAS_ADC_CH_MAX)
377                 return -EINVAL;
378
379         mutex_lock(&indio_dev->mlock);
380
381         switch (mask) {
382         case IIO_CHAN_INFO_RAW:
383         case IIO_CHAN_INFO_PROCESSED:
384                 ret = palmas_gpadc_read_prepare(adc, adc_chan);
385                 if (ret < 0)
386                         goto out;
387
388                 ret = palmas_gpadc_start_convertion(adc, adc_chan);
389                 if (ret < 0) {
390                         dev_err(adc->dev,
391                         "ADC start coversion failed\n");
392                         goto out;
393                 }
394
395                 if (mask == IIO_CHAN_INFO_PROCESSED)
396                         ret = palmas_gpadc_get_calibrated_code(
397                                                         adc, adc_chan, ret);
398
399                 *val = ret;
400
401                 ret = IIO_VAL_INT;
402                 goto out;
403
404         case IIO_CHAN_INFO_RAW_DUAL:
405         case IIO_CHAN_INFO_PROCESSED_DUAL:
406                 ret = palmas_gpadc_read_prepare(adc, adc_chan);
407                 if (ret < 0)
408                         goto out;
409
410                 ret = palmas_gpadc_start_convertion(adc, adc_chan);
411                 if (ret < 0) {
412                         dev_err(adc->dev,
413                                 "ADC start coversion failed\n");
414                         goto out;
415                 }
416
417                 if (mask == IIO_CHAN_INFO_PROCESSED_DUAL)
418                         ret = palmas_gpadc_get_calibrated_code(
419                                                         adc, adc_chan, ret);
420
421                 *val = ret;
422
423                 if ((adc_chan == PALMAS_ADC_CH_IN3)
424                                 && adc->ch3_dual_current && val2) {
425                         unsigned int reg_mask, reg_val;
426
427                         reg_mask = PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK;
428                         reg_val = (adc->ch3_current
429                                 << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT);
430                         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
431                                                 PALMAS_GPADC_CTRL1,
432                                                 reg_mask, reg_val);
433                         if (ret < 0) {
434                                 dev_err(adc->dev, "CTRL1 update failed\n");
435                                 goto out;
436                         }
437
438                         ret = palmas_gpadc_start_convertion(adc, adc_chan);
439                         if (ret < 0) {
440                                 dev_err(adc->dev,
441                                         "ADC start coversion failed\n");
442                                 goto out;
443                         }
444
445                         if (mask == IIO_CHAN_INFO_PROCESSED_DUAL)
446                                 ret = palmas_gpadc_get_calibrated_code(
447                                                         adc, adc_chan, ret);
448
449                         *val2 = ret;
450                 }
451
452                 ret = IIO_VAL_INT;
453                 goto out;
454         }
455
456         mutex_unlock(&indio_dev->mlock);
457         return ret;
458
459 out:
460         palmas_gpadc_read_done(adc, adc_chan);
461         mutex_unlock(&indio_dev->mlock);
462         return ret;
463 }
464
465 static const struct iio_info palmas_gpadc_iio_info = {
466         .read_raw = palmas_gpadc_read_raw,
467         .driver_module = THIS_MODULE,
468 };
469
470 #define PALMAS_ADC_CHAN_IIO(chan)                                       \
471 {                                                                       \
472         .datasheet_name = PALMAS_DATASHEET_NAME(chan),                  \
473         .type = IIO_VOLTAGE,                                            \
474         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |                  \
475                         BIT(IIO_CHAN_INFO_CALIBSCALE),                  \
476         .indexed = 1,                                                   \
477         .channel = PALMAS_ADC_CH_##chan,                                \
478 }
479
480 #define PALMAS_ADC_CHAN_DUAL_IIO(chan)                                  \
481 {                                                                       \
482         .datasheet_name = PALMAS_DATASHEET_NAME(chan),                  \
483         .type = IIO_VOLTAGE,                                            \
484         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |                  \
485                         BIT(IIO_CHAN_INFO_PROCESSED) |                  \
486                         BIT(IIO_CHAN_INFO_RAW_DUAL) |                   \
487                         BIT(IIO_CHAN_INFO_PROCESSED_DUAL),              \
488         .indexed = 1,                                                   \
489         .channel = PALMAS_ADC_CH_##chan,                                \
490 }
491
492 static const struct iio_chan_spec palmas_gpadc_iio_channel[] = {
493         PALMAS_ADC_CHAN_IIO(IN0),
494         PALMAS_ADC_CHAN_IIO(IN1),
495         PALMAS_ADC_CHAN_IIO(IN2),
496         PALMAS_ADC_CHAN_DUAL_IIO(IN3),
497         PALMAS_ADC_CHAN_IIO(IN4),
498         PALMAS_ADC_CHAN_IIO(IN5),
499         PALMAS_ADC_CHAN_IIO(IN6),
500         PALMAS_ADC_CHAN_IIO(IN7),
501         PALMAS_ADC_CHAN_IIO(IN8),
502         PALMAS_ADC_CHAN_IIO(IN9),
503         PALMAS_ADC_CHAN_IIO(IN10),
504         PALMAS_ADC_CHAN_IIO(IN11),
505         PALMAS_ADC_CHAN_IIO(IN12),
506         PALMAS_ADC_CHAN_IIO(IN13),
507         PALMAS_ADC_CHAN_IIO(IN14),
508         PALMAS_ADC_CHAN_IIO(IN15),
509 };
510
511 static int palmas_gpadc_probe(struct platform_device *pdev)
512 {
513         struct palmas_gpadc *adc;
514         struct palmas_platform_data *pdata;
515         struct palmas_gpadc_platform_data *adc_pdata;
516         struct iio_dev *iodev;
517         int ret, i;
518
519         pdata = dev_get_platdata(pdev->dev.parent);
520         if (!pdata || !pdata->gpadc_pdata) {
521                 dev_err(&pdev->dev, "No platform data\n");
522                 return -ENODEV;
523         }
524         adc_pdata = pdata->gpadc_pdata;
525
526         iodev = iio_device_alloc(sizeof(*adc));
527         if (!iodev) {
528                 dev_err(&pdev->dev, "iio_device_alloc failed\n");
529                 return -ENOMEM;
530         }
531
532         if (adc_pdata->iio_maps) {
533                 ret = iio_map_array_register(iodev, adc_pdata->iio_maps);
534                 if (ret < 0) {
535                         dev_err(&pdev->dev, "iio_map_array_register failed\n");
536                         goto out;
537                 }
538         }
539
540         adc = iio_priv(iodev);
541         adc->dev = &pdev->dev;
542         adc->palmas = dev_get_drvdata(pdev->dev.parent);
543         adc->adc_info = palmas_gpadc_info;
544         init_completion(&adc->conv_completion);
545         dev_set_drvdata(&pdev->dev, iodev);
546
547         adc->auto_conversion_period = adc_pdata->auto_conversion_period_ms;
548         adc->irq = palmas_irq_get_virq(adc->palmas, PALMAS_GPADC_EOC_SW_IRQ);
549         ret = request_threaded_irq(adc->irq, NULL,
550                 palmas_gpadc_irq,
551                 IRQF_ONESHOT | IRQF_EARLY_RESUME, dev_name(adc->dev),
552                 adc);
553         if (ret < 0) {
554                 dev_err(adc->dev,
555                         "request irq %d failed: %dn", adc->irq, ret);
556                 goto out_unregister_map;
557         }
558
559         if (adc_pdata->adc_wakeup1_data) {
560                 memcpy(&adc->wakeup1_data, adc_pdata->adc_wakeup1_data,
561                         sizeof(adc->wakeup1_data));
562                 adc->wakeup1_enable = true;
563                 adc->irq_auto_0 =  platform_get_irq(pdev, 1);
564                 ret = request_threaded_irq(adc->irq_auto_0, NULL,
565                                 palmas_gpadc_irq_auto,
566                                 IRQF_ONESHOT | IRQF_EARLY_RESUME,
567                                 "palmas-adc-auto-0", adc);
568                 if (ret < 0) {
569                         dev_err(adc->dev, "request auto0 irq %d failed: %dn",
570                                 adc->irq_auto_0, ret);
571                         goto out_irq_free;
572                 }
573         }
574
575         if (adc_pdata->adc_wakeup2_data) {
576                 memcpy(&adc->wakeup2_data, adc_pdata->adc_wakeup2_data,
577                                 sizeof(adc->wakeup2_data));
578                 adc->wakeup2_enable = true;
579                 adc->irq_auto_1 =  platform_get_irq(pdev, 2);
580                 ret = request_threaded_irq(adc->irq_auto_1, NULL,
581                                 palmas_gpadc_irq_auto,
582                                 IRQF_ONESHOT | IRQF_EARLY_RESUME,
583                                 "palmas-adc-auto-1", adc);
584                 if (ret < 0) {
585                         dev_err(adc->dev, "request auto1 irq %d failed: %dn",
586                                 adc->irq_auto_1, ret);
587                         goto out_irq_auto0_free;
588                 }
589         }
590
591         if (adc_pdata->ch0_current == 0)
592                 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_0;
593         else if (adc_pdata->ch0_current <= 5)
594                 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_5;
595         else if (adc_pdata->ch0_current <= 15)
596                 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_15;
597         else
598                 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_20;
599
600         if (adc_pdata->ch3_current == 0)
601                 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_0;
602         else if (adc_pdata->ch3_current <= 10)
603                 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_10;
604         else if (adc_pdata->ch3_current <= 400)
605                 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_400;
606         else
607                 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_800;
608
609         /* If ch3_dual_current is true, it will measure ch3 input signal with
610          * ch3_current and the next current of ch3_current. */
611         adc->ch3_dual_current = adc_pdata->ch3_dual_current;
612         if (adc->ch3_dual_current &&
613                         (adc->ch3_current == PALMAS_ADC_CH3_CURRENT_SRC_800)) {
614                 dev_warn(adc->dev,
615                         "Disable ch3_dual_current by wrong current setting\n");
616                 adc->ch3_dual_current = false;
617         }
618
619         adc->extended_delay = adc_pdata->extended_delay;
620
621         iodev->name = MOD_NAME;
622         iodev->dev.parent = &pdev->dev;
623         iodev->info = &palmas_gpadc_iio_info;
624         iodev->modes = INDIO_DIRECT_MODE;
625         iodev->channels = palmas_gpadc_iio_channel;
626         iodev->num_channels = ARRAY_SIZE(palmas_gpadc_iio_channel);
627
628         ret = iio_device_register(iodev);
629         if (ret < 0) {
630                 dev_err(adc->dev, "iio_device_register() failed: %d\n", ret);
631                 goto out_irq_auto1_free;
632         }
633
634         device_set_wakeup_capable(&pdev->dev, 1);
635         for (i = 0; i < PALMAS_ADC_CH_MAX; i++) {
636                 if (!(adc->adc_info[i].is_correct_code))
637                         palmas_gpadc_calibrate(adc, i);
638         }
639
640         if (adc->wakeup1_enable || adc->wakeup2_enable)
641                 device_wakeup_enable(&pdev->dev);
642         return 0;
643
644 out_irq_auto1_free:
645         if (adc_pdata->adc_wakeup2_data)
646                 free_irq(adc->irq_auto_1, adc);
647 out_irq_auto0_free:
648         if (adc_pdata->adc_wakeup1_data)
649                 free_irq(adc->irq_auto_0, adc);
650 out_irq_free:
651         free_irq(adc->irq, adc);
652 out_unregister_map:
653         if (adc_pdata->iio_maps)
654                 iio_map_array_unregister(iodev);
655 out:
656         iio_device_free(iodev);
657         return ret;
658 }
659
660 static int palmas_gpadc_remove(struct platform_device *pdev)
661 {
662         struct iio_dev *iodev = dev_to_iio_dev(&pdev->dev);
663         struct palmas_gpadc *adc = iio_priv(iodev);
664         struct palmas_platform_data *pdata = dev_get_platdata(pdev->dev.parent);
665         if (pdata->gpadc_pdata->iio_maps)
666                 iio_map_array_unregister(iodev);
667         iio_device_unregister(iodev);
668         free_irq(adc->irq, adc);
669         if (adc->wakeup1_enable)
670                 free_irq(adc->irq_auto_0, adc);
671         if (adc->wakeup2_enable)
672                 free_irq(adc->irq_auto_1, adc);
673         iio_device_free(iodev);
674         return 0;
675 }
676
677 #ifdef CONFIG_PM_SLEEP
678 static int palmas_adc_wakeup_configure(struct palmas_gpadc *adc)
679 {
680         int adc_period, conv;
681         int i;
682         int ch0 = 0, ch1 = 0;
683         int thres;
684         int ret;
685
686         adc_period = adc->auto_conversion_period;
687         for (i = 0; i < 16; ++i) {
688                 if (((1000 * (1 << i))/32) < adc_period)
689                         continue;
690         }
691         if (i > 0)
692                 i--;
693         adc_period = i;
694         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
695                         PALMAS_GPADC_AUTO_CTRL,
696                         PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK,
697                         adc_period);
698         if (ret < 0) {
699                 dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
700                 return ret;
701         }
702
703         conv = 0;
704         if (adc->wakeup1_enable) {
705                 int is_high;
706
707                 ch0 = adc->wakeup1_data.adc_channel_number;
708                 conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN;
709                 if (adc->wakeup1_data.adc_high_threshold > 0) {
710                         thres = adc->wakeup1_data.adc_high_threshold;
711                         is_high = 0;
712                 } else {
713                         thres = adc->wakeup1_data.adc_low_threshold;
714                         is_high = BIT(7);
715                 }
716
717                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
718                                 PALMAS_GPADC_THRES_CONV0_LSB, thres & 0xFF);
719                 if (ret < 0) {
720                         dev_err(adc->dev,
721                                 "THRES_CONV0_LSB write failed: %d\n", ret);
722                         return ret;
723                 }
724
725                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
726                                 PALMAS_GPADC_THRES_CONV0_MSB,
727                                 ((thres >> 8) & 0xF) | is_high);
728                 if (ret < 0) {
729                         dev_err(adc->dev,
730                                 "THRES_CONV0_MSB write failed: %d\n", ret);
731                         return ret;
732                 }
733         }
734
735         if (adc->wakeup2_enable) {
736                 int is_high;
737
738                 ch1 = adc->wakeup2_data.adc_channel_number;
739                 conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN;
740                 if (adc->wakeup2_data.adc_high_threshold > 0) {
741                         thres = adc->wakeup2_data.adc_high_threshold;
742                         is_high = 0;
743                 } else {
744                         thres = adc->wakeup2_data.adc_low_threshold;
745                         is_high = BIT(7);
746                 }
747
748                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
749                                 PALMAS_GPADC_THRES_CONV1_LSB, thres & 0xFF);
750                 if (ret < 0) {
751                         dev_err(adc->dev,
752                                 "THRES_CONV1_LSB write failed: %d\n", ret);
753                         return ret;
754                 }
755
756                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
757                                 PALMAS_GPADC_THRES_CONV1_MSB,
758                                 ((thres >> 8) & 0xF) | is_high);
759                 if (ret < 0) {
760                         dev_err(adc->dev,
761                                 "THRES_CONV1_MSB write failed: %d\n", ret);
762                         return ret;
763                 }
764         }
765
766         ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
767                         PALMAS_GPADC_AUTO_SELECT, (ch1 << 4) | ch0);
768         if (ret < 0) {
769                 dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
770                 return ret;
771         }
772
773         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
774                         PALMAS_GPADC_AUTO_CTRL,
775                         PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN |
776                         PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN, conv);
777         if (ret < 0) {
778                 dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
779                 return ret;
780         }
781         return 0;
782 }
783
784 static int palmas_adc_wakeup_reset(struct palmas_gpadc *adc)
785 {
786         int ret;
787
788         ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
789                         PALMAS_GPADC_AUTO_SELECT, 0);
790         if (ret < 0) {
791                 dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
792                 return ret;
793         }
794
795         ret = palmas_disable_auto_conversion(adc);
796         if (ret < 0) {
797                 dev_err(adc->dev, "Disable auto conversion failed: %d\n", ret);
798                 return ret;
799         }
800         return 0;
801 }
802
803 static int palmas_gpadc_suspend(struct device *dev)
804 {
805         struct iio_dev *iodev = dev_to_iio_dev(dev);
806         struct palmas_gpadc *adc = iio_priv(iodev);
807         int wakeup = adc->wakeup1_enable || adc->wakeup2_enable;
808         int ret;
809
810         if (!device_may_wakeup(dev) || !wakeup)
811                 return 0;
812
813         ret = palmas_adc_wakeup_configure(adc);
814         if (ret < 0)
815                 return ret;
816
817         if (adc->wakeup1_enable)
818                 enable_irq_wake(adc->irq_auto_0);
819
820         if (adc->wakeup2_enable)
821                 enable_irq_wake(adc->irq_auto_1);
822         return 0;
823 }
824
825 static int palmas_gpadc_resume(struct device *dev)
826 {
827         struct iio_dev *iodev = dev_to_iio_dev(dev);
828         struct palmas_gpadc *adc = iio_priv(iodev);
829         int wakeup = adc->wakeup1_enable || adc->wakeup2_enable;
830         int ret;
831
832         if (!device_may_wakeup(dev) || !wakeup)
833                 return 0;
834
835         ret = palmas_adc_wakeup_reset(adc);
836         if (ret < 0)
837                 return ret;
838
839         if (adc->wakeup1_enable)
840                 disable_irq_wake(adc->irq_auto_0);
841
842         if (adc->wakeup2_enable)
843                 disable_irq_wake(adc->irq_auto_1);
844
845         return 0;
846 };
847 #endif
848
849 static const struct dev_pm_ops palmas_pm_ops = {
850         SET_SYSTEM_SLEEP_PM_OPS(palmas_gpadc_suspend,
851                                 palmas_gpadc_resume)
852 };
853
854 static struct platform_driver palmas_gpadc_driver = {
855         .probe = palmas_gpadc_probe,
856         .remove = palmas_gpadc_remove,
857         .driver = {
858                 .name = MOD_NAME,
859                 .owner = THIS_MODULE,
860                 .pm = &palmas_pm_ops,
861         },
862 };
863
864 static int __init palmas_gpadc_init(void)
865 {
866         return platform_driver_register(&palmas_gpadc_driver);
867 }
868 module_init(palmas_gpadc_init);
869
870 static void __exit palmas_gpadc_exit(void)
871 {
872         platform_driver_unregister(&palmas_gpadc_driver);
873 }
874 module_exit(palmas_gpadc_exit);
875
876 MODULE_DESCRIPTION("palmas GPADC driver");
877 MODULE_AUTHOR("Pradeep Goudagunta<pgoudagunta@nvidia.com>");
878 MODULE_ALIAS("platform:palmas-gpadc");
879 MODULE_LICENSE("GPL v2");