gpu: nvgpu: Increase PBDMA timeout
[linux-3.10.git] / drivers / spi / spi-tegra114.c
1 /*
2  * SPI driver for NVIDIA's Tegra114 SPI Controller.
3  *
4  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
22 #include <linux/dmaengine.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmapool.h>
25 #include <linux/err.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/io.h>
29 #include <linux/kernel.h>
30 #include <linux/kthread.h>
31 #include <linux/module.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/of.h>
35 #include <linux/of_device.h>
36 #include <linux/spi/spi.h>
37 #include <linux/spi/spi-tegra.h>
38 #include <linux/clk/tegra.h>
39
40 #define SPI_COMMAND1                            0x000
41 #define SPI_BIT_LENGTH(x)                       (((x) & 0x1f) << 0)
42 #define SPI_PACKED                              (1 << 5)
43 #define SPI_TX_EN                               (1 << 11)
44 #define SPI_RX_EN                               (1 << 12)
45 #define SPI_BOTH_EN_BYTE                        (1 << 13)
46 #define SPI_BOTH_EN_BIT                         (1 << 14)
47 #define SPI_LSBYTE_FE                           (1 << 15)
48 #define SPI_LSBIT_FE                            (1 << 16)
49 #define SPI_BIDIROE                             (1 << 17)
50 #define SPI_IDLE_SDA_DRIVE_LOW                  (0 << 18)
51 #define SPI_IDLE_SDA_DRIVE_HIGH                 (1 << 18)
52 #define SPI_IDLE_SDA_PULL_LOW                   (2 << 18)
53 #define SPI_IDLE_SDA_PULL_HIGH                  (3 << 18)
54 #define SPI_IDLE_SDA_MASK                       (3 << 18)
55 #define SPI_CS_SS_VAL                           (1 << 20)
56 #define SPI_CS_SW_HW                            (1 << 21)
57 /* SPI_CS_POL_INACTIVE bits are default high */
58 #define SPI_CS_POL_INACTIVE                     22
59 #define SPI_CS_POL_INACTIVE_0                   (1 << 22)
60 #define SPI_CS_POL_INACTIVE_1                   (1 << 23)
61 #define SPI_CS_POL_INACTIVE_2                   (1 << 24)
62 #define SPI_CS_POL_INACTIVE_3                   (1 << 25)
63 #define SPI_CS_POL_INACTIVE_MASK                (0xF << 22)
64
65 #define SPI_CS_SEL_0                            (0 << 26)
66 #define SPI_CS_SEL_1                            (1 << 26)
67 #define SPI_CS_SEL_2                            (2 << 26)
68 #define SPI_CS_SEL_3                            (3 << 26)
69 #define SPI_CS_SEL_MASK                         (3 << 26)
70 #define SPI_CS_SEL(x)                           (((x) & 0x3) << 26)
71 #define SPI_CONTROL_MODE_0                      (0 << 28)
72 #define SPI_CONTROL_MODE_1                      (1 << 28)
73 #define SPI_CONTROL_MODE_2                      (2 << 28)
74 #define SPI_CONTROL_MODE_3                      (3 << 28)
75 #define SPI_CONTROL_MODE_MASK                   (3 << 28)
76 #define SPI_MODE_SEL(x)                         (((x) & 0x3) << 28)
77 #define SPI_M_S                                 (1 << 30)
78 #define SPI_PIO                                 (1 << 31)
79
80 #define SPI_COMMAND2                            0x004
81 #define SPI_TX_TAP_DELAY(x)                     (((x) & 0x3F) << 6)
82 #define SPI_RX_TAP_DELAY(x)                     (((x) & 0x3F) << 0)
83
84 #define SPI_CS_TIMING1                          0x008
85 #define SPI_SETUP_HOLD(setup, hold)             (((setup) << 4) | (hold))
86 #define SPI_CS_SETUP_HOLD(reg, cs, val)                 \
87                 ((((val) & 0xFFu) << ((cs) * 8)) |      \
88                 ((reg) & ~(0xFFu << ((cs) * 8))))
89
90 #define SPI_CS_TIMING2                          0x00C
91 #define CYCLES_BETWEEN_PACKETS_0(x)             (((x) & 0x1F) << 0)
92 #define CS_ACTIVE_BETWEEN_PACKETS_0             (1 << 5)
93 #define CYCLES_BETWEEN_PACKETS_1(x)             (((x) & 0x1F) << 8)
94 #define CS_ACTIVE_BETWEEN_PACKETS_1             (1 << 13)
95 #define CYCLES_BETWEEN_PACKETS_2(x)             (((x) & 0x1F) << 16)
96 #define CS_ACTIVE_BETWEEN_PACKETS_2             (1 << 21)
97 #define CYCLES_BETWEEN_PACKETS_3(x)             (((x) & 0x1F) << 24)
98 #define CS_ACTIVE_BETWEEN_PACKETS_3             (1 << 29)
99 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val)         \
100                 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) |      \
101                         ((reg) & ~(1 << ((cs) * 8 + 5))))
102 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val)            \
103                 (reg = (((val) & 0xF) << ((cs) * 8)) |          \
104                         ((reg) & ~(0xF << ((cs) * 8))))
105
106 #define SPI_TRANS_STATUS                        0x010
107 #define SPI_BLK_CNT(val)                        (((val) >> 0) & 0xFFFF)
108 #define SPI_SLV_IDLE_COUNT(val)                 (((val) >> 16) & 0xFF)
109 #define SPI_RDY                                 (1 << 30)
110
111 #define SPI_FIFO_STATUS                         0x014
112 #define SPI_RX_FIFO_EMPTY                       (1 << 0)
113 #define SPI_RX_FIFO_FULL                        (1 << 1)
114 #define SPI_TX_FIFO_EMPTY                       (1 << 2)
115 #define SPI_TX_FIFO_FULL                        (1 << 3)
116 #define SPI_RX_FIFO_UNF                         (1 << 4)
117 #define SPI_RX_FIFO_OVF                         (1 << 5)
118 #define SPI_TX_FIFO_UNF                         (1 << 6)
119 #define SPI_TX_FIFO_OVF                         (1 << 7)
120 #define SPI_ERR                                 (1 << 8)
121 #define SPI_TX_FIFO_FLUSH                       (1 << 14)
122 #define SPI_RX_FIFO_FLUSH                       (1 << 15)
123 #define SPI_TX_FIFO_EMPTY_COUNT(val)            (((val) >> 16) & 0x7F)
124 #define SPI_RX_FIFO_FULL_COUNT(val)             (((val) >> 23) & 0x7F)
125 #define SPI_FRAME_END                           (1 << 30)
126 #define SPI_CS_INACTIVE                         (1 << 31)
127
128 #define SPI_FIFO_ERROR                          (SPI_RX_FIFO_UNF | \
129                         SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
130 #define SPI_FIFO_EMPTY                  (SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
131
132 #define SPI_TX_DATA                             0x018
133 #define SPI_RX_DATA                             0x01C
134
135 #define SPI_DMA_CTL                             0x020
136 #define SPI_TX_TRIG_1                           (0 << 15)
137 #define SPI_TX_TRIG_4                           (1 << 15)
138 #define SPI_TX_TRIG_8                           (2 << 15)
139 #define SPI_TX_TRIG_16                          (3 << 15)
140 #define SPI_TX_TRIG_MASK                        (3 << 15)
141 #define SPI_RX_TRIG_1                           (0 << 19)
142 #define SPI_RX_TRIG_4                           (1 << 19)
143 #define SPI_RX_TRIG_8                           (2 << 19)
144 #define SPI_RX_TRIG_16                          (3 << 19)
145 #define SPI_RX_TRIG_MASK                        (3 << 19)
146 #define SPI_IE_TX                               (1 << 28)
147 #define SPI_IE_RX                               (1 << 29)
148 #define SPI_CONT                                (1 << 30)
149 #define SPI_DMA                                 (1 << 31)
150 #define SPI_DMA_EN                              SPI_DMA
151
152 #define SPI_DMA_BLK                             0x024
153 #define SPI_DMA_BLK_SET(x)                      (((x) & 0xFFFF) << 0)
154
155 #define SPI_TX_FIFO                             0x108
156 #define SPI_RX_FIFO                             0x188
157 #define MAX_CHIP_SELECT                         4
158 #define SPI_FIFO_DEPTH                          64
159 #define DATA_DIR_TX                             (1 << 0)
160 #define DATA_DIR_RX                             (1 << 1)
161
162 #define SPI_DMA_TIMEOUT                         (msecs_to_jiffies(10000))
163 #define DEFAULT_SPI_DMA_BUF_LEN                 (16*1024)
164 #define TX_FIFO_EMPTY_COUNT_MAX                 SPI_TX_FIFO_EMPTY_COUNT(0x40)
165 #define RX_FIFO_FULL_COUNT_ZERO                 SPI_RX_FIFO_FULL_COUNT(0)
166 #define MAX_HOLD_CYCLES                         16
167 #define SPI_DEFAULT_SPEED                       25000000
168
169 #define MAX_CHIP_SELECT                         4
170 #define SPI_FIFO_DEPTH                          64
171
172 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
173 #define SPI_SPEED_TAP_DELAY_MARGIN 35000000
174 #define SPI_DEFAULT_RX_TAP_DELAY 10
175 #endif
176
177 struct tegra_spi_data {
178         struct device                           *dev;
179         struct spi_master                       *master;
180         spinlock_t                              lock;
181
182         struct clk                              *clk;
183         void __iomem                            *base;
184         phys_addr_t                             phys;
185         unsigned                                irq;
186         bool                                    clock_always_on;
187         u32                                     spi_max_frequency;
188         u32                                     cur_speed;
189
190         struct spi_device                       *cur_spi;
191         unsigned                                cur_pos;
192         unsigned                                cur_len;
193         unsigned                                words_per_32bit;
194         unsigned                                bytes_per_word;
195         unsigned                                curr_dma_words;
196         unsigned                                cur_direction;
197
198         unsigned                                cur_rx_pos;
199         unsigned                                cur_tx_pos;
200
201         unsigned                                dma_buf_size;
202         unsigned                                max_buf_size;
203         bool                                    is_curr_dma_xfer;
204         bool                                    is_hw_based_cs;
205
206         struct completion                       rx_dma_complete;
207         struct completion                       tx_dma_complete;
208
209         u32                                     tx_status;
210         u32                                     rx_status;
211         u32                                     status_reg;
212         bool                                    is_packed;
213         unsigned long                           packed_size;
214
215         u32                                     command1_reg;
216         u32                                     dma_control_reg;
217         u32                                     def_command1_reg;
218         u32                                     def_command2_reg;
219         u32                                     spi_cs_timing;
220
221         struct completion                       xfer_completion;
222         struct spi_transfer                     *curr_xfer;
223         struct dma_chan                         *rx_dma_chan;
224         u32                                     *rx_dma_buf;
225         dma_addr_t                              rx_dma_phys;
226         struct dma_async_tx_descriptor          *rx_dma_desc;
227
228         struct dma_chan                         *tx_dma_chan;
229         u32                                     *tx_dma_buf;
230         dma_addr_t                              tx_dma_phys;
231         struct dma_async_tx_descriptor          *tx_dma_desc;
232 };
233
234 static int tegra_spi_runtime_suspend(struct device *dev);
235 static int tegra_spi_runtime_resume(struct device *dev);
236
237 static inline unsigned long tegra_spi_readl(struct tegra_spi_data *tspi,
238                 unsigned long reg)
239 {
240         return readl(tspi->base + reg);
241 }
242
243 static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
244                 unsigned long val, unsigned long reg)
245 {
246         writel(val, tspi->base + reg);
247
248         /* Read back register to make sure that register writes completed */
249         if (reg != SPI_TX_FIFO)
250                 readl(tspi->base + SPI_COMMAND1);
251 }
252
253 static void tegra_spi_clear_status(struct tegra_spi_data *tspi)
254 {
255         unsigned long val;
256
257         /* Write 1 to clear status register */
258         val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
259         tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
260
261         /* Clear fifo status error if any */
262         val = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
263         if (val & SPI_ERR)
264                 tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR,
265                                 SPI_FIFO_STATUS);
266 }
267
268 static unsigned tegra_spi_calculate_curr_xfer_param(
269         struct spi_device *spi, struct tegra_spi_data *tspi,
270         struct spi_transfer *t)
271 {
272         unsigned remain_len = t->len - tspi->cur_pos;
273         unsigned max_word;
274         unsigned bits_per_word ;
275         unsigned max_len;
276         unsigned total_fifo_words;
277
278         bits_per_word = t->bits_per_word ? t->bits_per_word :
279                                                 spi->bits_per_word;
280         tspi->bytes_per_word = (bits_per_word - 1) / 8 + 1;
281
282         if (bits_per_word == 8 || bits_per_word == 16) {
283                 tspi->is_packed = 1;
284                 tspi->words_per_32bit = 32/bits_per_word;
285         } else {
286                 tspi->is_packed = 0;
287                 tspi->words_per_32bit = 1;
288         }
289
290         if (tspi->is_packed) {
291                 max_len = min(remain_len, tspi->max_buf_size);
292                 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
293                 total_fifo_words = (max_len + 3)/4;
294         } else {
295                 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
296                 max_word = min(max_word, tspi->max_buf_size/4);
297                 tspi->curr_dma_words = max_word;
298                 total_fifo_words = max_word;
299         }
300         return total_fifo_words;
301 }
302
303 static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
304         struct tegra_spi_data *tspi, struct spi_transfer *t)
305 {
306         unsigned nbytes;
307         unsigned tx_empty_count;
308         unsigned long fifo_status;
309         unsigned max_n_32bit;
310         unsigned i, count;
311         unsigned long x;
312         unsigned int written_words;
313         unsigned fifo_words_left;
314         u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
315
316         fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
317         tx_empty_count = SPI_TX_FIFO_EMPTY_COUNT(fifo_status);
318
319         if (tspi->is_packed) {
320                 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
321                 written_words = min(fifo_words_left, tspi->curr_dma_words);
322                 nbytes = written_words * tspi->bytes_per_word;
323                 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
324                 for (count = 0; count < max_n_32bit; count++) {
325                         x = 0;
326                         for (i = 0; (i < 4) && nbytes; i++, nbytes--)
327                                 x |= (*tx_buf++) << (i*8);
328                         tegra_spi_writel(tspi, x, SPI_TX_FIFO);
329                 }
330         } else {
331                 max_n_32bit = min(tspi->curr_dma_words,  tx_empty_count);
332                 written_words = max_n_32bit;
333                 nbytes = written_words * tspi->bytes_per_word;
334                 for (count = 0; count < max_n_32bit; count++) {
335                         x = 0;
336                         for (i = 0; nbytes && (i < tspi->bytes_per_word);
337                                                         i++, nbytes--)
338                                 x |= ((*tx_buf++) << i*8);
339                         tegra_spi_writel(tspi, x, SPI_TX_FIFO);
340                 }
341         }
342         tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
343         return written_words;
344 }
345
346 static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
347                 struct tegra_spi_data *tspi, struct spi_transfer *t)
348 {
349         unsigned rx_full_count;
350         unsigned long fifo_status;
351         unsigned i, count;
352         unsigned long x;
353         unsigned int read_words = 0;
354         unsigned len;
355         u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
356
357         fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
358         rx_full_count = SPI_RX_FIFO_FULL_COUNT(fifo_status);
359         if (tspi->is_packed) {
360                 len = tspi->curr_dma_words * tspi->bytes_per_word;
361                 for (count = 0; count < rx_full_count; count++) {
362                         x = tegra_spi_readl(tspi, SPI_RX_FIFO);
363                         for (i = 0; len && (i < 4); i++, len--)
364                                 *rx_buf++ = (x >> i*8) & 0xFF;
365                 }
366                 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
367                 read_words += tspi->curr_dma_words;
368         } else {
369                 unsigned int bits_per_word;
370
371                 bits_per_word = t->bits_per_word ? t->bits_per_word :
372                                                 tspi->cur_spi->bits_per_word;
373                 for (count = 0; count < rx_full_count; count++) {
374                         x = tegra_spi_readl(tspi, SPI_RX_FIFO);
375                         for (i = 0; (i < tspi->bytes_per_word); i++)
376                                 *rx_buf++ = (x >> (i*8)) & 0xFF;
377                 }
378                 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
379                 read_words += rx_full_count;
380         }
381         return read_words;
382 }
383
384 static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
385                 struct tegra_spi_data *tspi, struct spi_transfer *t)
386 {
387         unsigned len;
388
389         /* Make the dma buffer to read by cpu */
390         dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
391                                 tspi->dma_buf_size, DMA_TO_DEVICE);
392
393         if (tspi->is_packed) {
394                 len = tspi->curr_dma_words * tspi->bytes_per_word;
395                 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
396         } else {
397                 unsigned int i;
398                 unsigned int count;
399                 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
400                 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
401                 unsigned int x;
402
403                 for (count = 0; count < tspi->curr_dma_words; count++) {
404                         x = 0;
405                         for (i = 0; consume && (i < tspi->bytes_per_word);
406                                                         i++, consume--)
407                                 x |= ((*tx_buf++) << i * 8);
408                         tspi->tx_dma_buf[count] = x;
409                 }
410         }
411         tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
412
413         /* Make the dma buffer to read by dma */
414         dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
415                                 tspi->dma_buf_size, DMA_TO_DEVICE);
416 }
417
418 static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
419                 struct tegra_spi_data *tspi, struct spi_transfer *t)
420 {
421         unsigned len;
422
423         /* Make the dma buffer to read by cpu */
424         dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
425                 tspi->dma_buf_size, DMA_FROM_DEVICE);
426
427         if (tspi->is_packed) {
428                 len = tspi->curr_dma_words * tspi->bytes_per_word;
429                 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
430         } else {
431                 unsigned int i;
432                 unsigned int count;
433                 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
434                 unsigned int x;
435                 unsigned int rx_mask, bits_per_word;
436
437                 bits_per_word = t->bits_per_word ? t->bits_per_word :
438                                                 tspi->cur_spi->bits_per_word;
439                 rx_mask = (1 << bits_per_word) - 1;
440                 for (count = 0; count < tspi->curr_dma_words; count++) {
441                         x = tspi->rx_dma_buf[count];
442                         x &= rx_mask;
443                         for (i = 0; (i < tspi->bytes_per_word); i++)
444                                 *rx_buf++ = (x >> (i*8)) & 0xFF;
445                 }
446         }
447         tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
448
449         /* Make the dma buffer to read by dma */
450         dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
451                 tspi->dma_buf_size, DMA_FROM_DEVICE);
452 }
453
454 static void tegra_spi_dma_complete(void *args)
455 {
456         struct completion *dma_complete = args;
457
458         complete(dma_complete);
459 }
460
461 static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len)
462 {
463         INIT_COMPLETION(tspi->tx_dma_complete);
464         tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
465                                 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
466                                 DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
467         if (!tspi->tx_dma_desc) {
468                 dev_err(tspi->dev, "Not able to get desc for Tx\n");
469                 return -EIO;
470         }
471
472         tspi->tx_dma_desc->callback = tegra_spi_dma_complete;
473         tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
474
475         dmaengine_submit(tspi->tx_dma_desc);
476         dma_async_issue_pending(tspi->tx_dma_chan);
477         return 0;
478 }
479
480 static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
481 {
482         INIT_COMPLETION(tspi->rx_dma_complete);
483         tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
484                                 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
485                                 DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
486         if (!tspi->rx_dma_desc) {
487                 dev_err(tspi->dev, "Not able to get desc for Rx\n");
488                 return -EIO;
489         }
490
491         tspi->rx_dma_desc->callback = tegra_spi_dma_complete;
492         tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
493
494         dmaengine_submit(tspi->rx_dma_desc);
495         dma_async_issue_pending(tspi->rx_dma_chan);
496         return 0;
497 }
498
499 static int tegra_spi_start_dma_based_transfer(
500                 struct tegra_spi_data *tspi, struct spi_transfer *t)
501 {
502         unsigned long val;
503         unsigned int len;
504         int ret = 0;
505         unsigned long status;
506
507         /* Make sure that Rx and Tx fifo are empty */
508         status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
509         if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
510                 dev_err(tspi->dev,
511                         "Rx/Tx fifo are not empty status 0x%08lx\n", status);
512                 return -EIO;
513         }
514
515         val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
516         tegra_spi_writel(tspi, val, SPI_DMA_BLK);
517
518         if (tspi->is_packed)
519                 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
520                                         4) * 4;
521         else
522                 len = tspi->curr_dma_words * 4;
523
524         /* Set attention level based on length of transfer */
525         if (len & 0xF)
526                 val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1;
527         else if (((len) >> 4) & 0x1)
528                 val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4;
529         else
530                 val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8;
531
532         if (tspi->cur_direction & DATA_DIR_TX)
533                 val |= SPI_IE_TX;
534
535         if (tspi->cur_direction & DATA_DIR_RX)
536                 val |= SPI_IE_RX;
537
538         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
539         tspi->dma_control_reg = val;
540
541         if (tspi->cur_direction & DATA_DIR_TX) {
542                 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t);
543                 ret = tegra_spi_start_tx_dma(tspi, len);
544                 if (ret < 0) {
545                         dev_err(tspi->dev,
546                                 "Starting tx dma failed, err %d\n", ret);
547                         return ret;
548                 }
549         }
550
551         if (tspi->cur_direction & DATA_DIR_RX) {
552                 /* Make the dma buffer to read by dma */
553                 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
554                                 tspi->dma_buf_size, DMA_FROM_DEVICE);
555
556                 ret = tegra_spi_start_rx_dma(tspi, len);
557                 if (ret < 0) {
558                         dev_err(tspi->dev,
559                                 "Starting rx dma failed, err %d\n", ret);
560                         if (tspi->cur_direction & DATA_DIR_TX)
561                                 dmaengine_terminate_all(tspi->tx_dma_chan);
562                         return ret;
563                 }
564         }
565         tspi->is_curr_dma_xfer = true;
566         tspi->dma_control_reg = val;
567
568         val |= SPI_DMA_EN;
569         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
570         return ret;
571 }
572
573 static int tegra_spi_start_cpu_based_transfer(
574                 struct tegra_spi_data *tspi, struct spi_transfer *t)
575 {
576         unsigned long val;
577         unsigned cur_words;
578
579         if (tspi->cur_direction & DATA_DIR_TX)
580                 cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t);
581         else
582                 cur_words = tspi->curr_dma_words;
583
584         val = SPI_DMA_BLK_SET(cur_words - 1);
585         tegra_spi_writel(tspi, val, SPI_DMA_BLK);
586
587         val = 0;
588         if (tspi->cur_direction & DATA_DIR_TX)
589                 val |= SPI_IE_TX;
590
591         if (tspi->cur_direction & DATA_DIR_RX)
592                 val |= SPI_IE_RX;
593
594         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
595         tspi->dma_control_reg = val;
596
597         tspi->is_curr_dma_xfer = false;
598         val = tspi->command1_reg;
599         val |= SPI_PIO;
600         tegra_spi_writel(tspi, val, SPI_COMMAND1);
601         return 0;
602 }
603
604 static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
605                         bool dma_to_memory)
606 {
607         struct dma_chan *dma_chan;
608         u32 *dma_buf;
609         dma_addr_t dma_phys;
610         int ret;
611         struct dma_slave_config dma_sconfig;
612
613         dma_chan = dma_request_slave_channel_reason(tspi->dev,
614                                         dma_to_memory ? "rx" : "tx");
615         if (IS_ERR(dma_chan)) {
616                 ret = PTR_ERR(dma_chan);
617                 if (ret != -EPROBE_DEFER)
618                         dev_err(tspi->dev,
619                                 "Dma channel is not available: %d\n", ret);
620                 return ret;
621         }
622
623         dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
624                                 &dma_phys, GFP_KERNEL);
625         if (!dma_buf) {
626                 dev_err(tspi->dev, "Not able to allocate the dma buffer\n");
627                 dma_release_channel(dma_chan);
628                 return -ENOMEM;
629         }
630
631         if (dma_to_memory) {
632                 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
633                 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
634                 dma_sconfig.src_maxburst = 0;
635         } else {
636                 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO;
637                 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
638                 dma_sconfig.dst_maxburst = 0;
639         }
640
641         ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
642         if (ret)
643                 goto scrub;
644         if (dma_to_memory) {
645                 tspi->rx_dma_chan = dma_chan;
646                 tspi->rx_dma_buf = dma_buf;
647                 tspi->rx_dma_phys = dma_phys;
648         } else {
649                 tspi->tx_dma_chan = dma_chan;
650                 tspi->tx_dma_buf = dma_buf;
651                 tspi->tx_dma_phys = dma_phys;
652         }
653         return 0;
654
655 scrub:
656         dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
657         dma_release_channel(dma_chan);
658         return ret;
659 }
660
661 static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
662         bool dma_to_memory)
663 {
664         u32 *dma_buf;
665         dma_addr_t dma_phys;
666         struct dma_chan *dma_chan;
667
668         if (dma_to_memory) {
669                 dma_buf = tspi->rx_dma_buf;
670                 dma_chan = tspi->rx_dma_chan;
671                 dma_phys = tspi->rx_dma_phys;
672                 tspi->rx_dma_chan = NULL;
673                 tspi->rx_dma_buf = NULL;
674         } else {
675                 dma_buf = tspi->tx_dma_buf;
676                 dma_chan = tspi->tx_dma_chan;
677                 dma_phys = tspi->tx_dma_phys;
678                 tspi->tx_dma_buf = NULL;
679                 tspi->tx_dma_chan = NULL;
680         }
681         if (!dma_chan)
682                 return;
683
684         dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
685         dma_release_channel(dma_chan);
686 }
687
688 static int tegra_spi_start_transfer_one(struct spi_device *spi,
689                 struct spi_transfer *t, bool is_first_of_msg,
690                 bool is_single_xfer)
691 {
692         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
693         u32 speed;
694         u8 bits_per_word;
695         unsigned total_fifo_words;
696         int ret;
697         struct tegra_spi_device_controller_data *cdata = spi->controller_data;
698         unsigned long command1;
699         int req_mode;
700
701         bits_per_word = t->bits_per_word;
702         speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz;
703         if (!speed)
704                 speed = tspi->spi_max_frequency;
705         if (speed != tspi->cur_speed) {
706                 clk_set_rate(tspi->clk, speed);
707                 tspi->cur_speed = speed;
708         }
709
710         tspi->cur_spi = spi;
711         tspi->cur_pos = 0;
712         tspi->cur_rx_pos = 0;
713         tspi->cur_tx_pos = 0;
714         tspi->curr_xfer = t;
715         tspi->tx_status = 0;
716         tspi->rx_status = 0;
717         total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t);
718
719         if (is_first_of_msg) {
720                 tegra_spi_clear_status(tspi);
721
722                 command1 = tspi->def_command1_reg;
723                 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
724
725                 command1 &= ~SPI_CONTROL_MODE_MASK;
726                 req_mode = spi->mode & 0x3;
727                 if (req_mode == SPI_MODE_0)
728                         command1 |= SPI_CONTROL_MODE_0;
729                 else if (req_mode == SPI_MODE_1)
730                         command1 |= SPI_CONTROL_MODE_1;
731                 else if (req_mode == SPI_MODE_2)
732                         command1 |= SPI_CONTROL_MODE_2;
733                 else if (req_mode == SPI_MODE_3)
734                         command1 |= SPI_CONTROL_MODE_3;
735
736                 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
737
738                 /* possibly use the hw based chip select */
739                 tspi->is_hw_based_cs = false;
740                 if (cdata && cdata->is_hw_based_cs && is_single_xfer &&
741                         ((tspi->curr_dma_words * tspi->bytes_per_word) ==
742                                                 (t->len - tspi->cur_pos))) {
743                         u32 set_count;
744                         u32 hold_count;
745                         u32 spi_cs_timing;
746                         u32 spi_cs_setup;
747
748                         set_count = min(cdata->cs_setup_clk_count, 16);
749                         if (set_count)
750                                 set_count--;
751
752                         hold_count = min(cdata->cs_hold_clk_count, 16);
753                         if (hold_count)
754                                 hold_count--;
755
756                         spi_cs_setup = SPI_SETUP_HOLD(set_count,
757                                         hold_count);
758                         spi_cs_timing = tspi->spi_cs_timing;
759                         spi_cs_timing = SPI_CS_SETUP_HOLD(spi_cs_timing,
760                                                 spi->chip_select,
761                                                 spi_cs_setup);
762                         tspi->spi_cs_timing = spi_cs_timing;
763                         tegra_spi_writel(tspi, spi_cs_timing,
764                                                 SPI_CS_TIMING1);
765                         tspi->is_hw_based_cs = true;
766                 }
767
768                 if (!tspi->is_hw_based_cs) {
769                         command1 |= SPI_CS_SW_HW;
770                         if (spi->mode & SPI_CS_HIGH)
771                                 command1 |= SPI_CS_SS_VAL;
772                         else
773                                 command1 &= ~SPI_CS_SS_VAL;
774                 } else {
775                         command1 &= ~SPI_CS_SW_HW;
776                         command1 &= ~SPI_CS_SS_VAL;
777                 }
778
779                 if (cdata) {
780                         u32 command2_reg;
781                         u32 rx_tap_delay;
782                         u32 tx_tap_delay;
783                         int rx_clk_tap_delay;
784
785                         rx_clk_tap_delay = cdata->rx_clk_tap_delay;
786 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
787                         if (rx_clk_tap_delay == 0)
788                                 if (speed > SPI_SPEED_TAP_DELAY_MARGIN)
789                                         rx_clk_tap_delay =
790                                                 SPI_DEFAULT_RX_TAP_DELAY;
791 #endif
792                         rx_tap_delay = min(rx_clk_tap_delay, 63);
793                         tx_tap_delay = min(cdata->tx_clk_tap_delay, 63);
794                         command2_reg = SPI_TX_TAP_DELAY(tx_tap_delay) |
795                                         SPI_RX_TAP_DELAY(rx_tap_delay);
796                         tegra_spi_writel(tspi, command2_reg, SPI_COMMAND2);
797                 } else {
798                         u32 command2_reg;
799                         command2_reg = tspi->def_command2_reg;
800 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
801                         if (speed > SPI_SPEED_TAP_DELAY_MARGIN) {
802                                 command2_reg = command2_reg &
803                                         (~SPI_RX_TAP_DELAY(63));
804                                 command2_reg = command2_reg |
805                                         SPI_RX_TAP_DELAY(
806                                         SPI_DEFAULT_RX_TAP_DELAY);
807                         }
808 #endif
809                         tegra_spi_writel(tspi, command2_reg, SPI_COMMAND2);
810                 }
811         } else {
812                 command1 = tspi->command1_reg;
813                 command1 &= ~SPI_BIT_LENGTH(~0);
814                 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
815         }
816
817         if (tspi->is_packed)
818                 command1 |= SPI_PACKED;
819
820         command1 &= ~(SPI_CS_SEL_MASK | SPI_TX_EN | SPI_RX_EN);
821         tspi->cur_direction = 0;
822         if (t->rx_buf) {
823                 command1 |= SPI_RX_EN;
824                 tspi->cur_direction |= DATA_DIR_RX;
825         }
826         if (t->tx_buf) {
827                 command1 |= SPI_TX_EN;
828                 tspi->cur_direction |= DATA_DIR_TX;
829         }
830         command1 |= SPI_CS_SEL(spi->chip_select);
831         tegra_spi_writel(tspi, command1, SPI_COMMAND1);
832         tspi->command1_reg = command1;
833
834         dev_dbg(tspi->dev, "The def 0x%x and written 0x%lx\n",
835                                 tspi->def_command1_reg, command1);
836
837         if (total_fifo_words > SPI_FIFO_DEPTH)
838                 ret = tegra_spi_start_dma_based_transfer(tspi, t);
839         else
840                 ret = tegra_spi_start_cpu_based_transfer(tspi, t);
841         return ret;
842 }
843
844 static struct tegra_spi_device_controller_data
845         *tegra_spi_get_cdata_dt(struct spi_device *spi)
846 {
847         struct tegra_spi_device_controller_data *cdata;
848         struct device_node *slave_np, *data_np;
849         int ret;
850
851         slave_np = spi->dev.of_node;
852         if (!slave_np) {
853                 dev_dbg(&spi->dev, "device node not found\n");
854                 return NULL;
855         }
856
857         data_np = of_get_child_by_name(slave_np, "controller-data");
858         if (!data_np) {
859                 dev_dbg(&spi->dev, "child node 'controller-data' not found\n");
860                 return NULL;
861         }
862
863         cdata = devm_kzalloc(&spi->dev, sizeof(*cdata),
864                         GFP_KERNEL);
865         if (!cdata) {
866                 dev_err(&spi->dev, "Memory alloc for cdata failed\n");
867                 of_node_put(data_np);
868                 return NULL;
869         }
870
871         ret = of_property_read_bool(data_np, "nvidia,enable-hw-based-cs");
872         if (ret)
873                 cdata->is_hw_based_cs = 1;
874
875         of_property_read_u32(data_np, "nvidia,cs-setup-clk-count",
876                         &cdata->cs_setup_clk_count);
877         of_property_read_u32(data_np, "nvidia,cs-hold-clk-count",
878                         &cdata->cs_hold_clk_count);
879         of_property_read_u32(data_np, "nvidia,rx-clk-tap-delay",
880                         &cdata->rx_clk_tap_delay);
881         of_property_read_u32(data_np, "nvidia,tx-clk-tap-delay",
882                         &cdata->tx_clk_tap_delay);
883
884         of_node_put(data_np);
885         return cdata;
886 }
887
888 static int tegra_spi_setup(struct spi_device *spi)
889 {
890         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
891         struct tegra_spi_device_controller_data *cdata = spi->controller_data;
892         unsigned long val;
893         unsigned long flags;
894         int ret;
895         unsigned int cs_pol_bit[MAX_CHIP_SELECT] = {
896                         SPI_CS_POL_INACTIVE_0,
897                         SPI_CS_POL_INACTIVE_1,
898                         SPI_CS_POL_INACTIVE_2,
899                         SPI_CS_POL_INACTIVE_3,
900         };
901
902         dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
903                 spi->bits_per_word,
904                 spi->mode & SPI_CPOL ? "" : "~",
905                 spi->mode & SPI_CPHA ? "" : "~",
906                 spi->max_speed_hz);
907
908         BUG_ON(spi->chip_select >= MAX_CHIP_SELECT);
909
910         if (!cdata) {
911                 cdata = tegra_spi_get_cdata_dt(spi);
912                 spi->controller_data = cdata;
913         }
914
915         /* Set speed to the spi max fequency if spi device has not set */
916         spi->max_speed_hz = spi->max_speed_hz ? : tspi->spi_max_frequency;
917
918         ret = pm_runtime_get_sync(tspi->dev);
919         if (ret < 0) {
920                 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
921                 return ret;
922         }
923
924         spin_lock_irqsave(&tspi->lock, flags);
925         val = tspi->def_command1_reg;
926         if (spi->mode & SPI_CS_HIGH)
927                 val &= ~cs_pol_bit[spi->chip_select];
928         else
929                 val |= cs_pol_bit[spi->chip_select];
930         tspi->def_command1_reg = val;
931         tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
932         spin_unlock_irqrestore(&tspi->lock, flags);
933
934         pm_runtime_put(tspi->dev);
935         return 0;
936 }
937
938 static  int tegra_spi_cs_low(struct spi_device *spi,
939                 bool state)
940 {
941         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
942         int ret;
943         unsigned long val;
944         unsigned long flags;
945         unsigned int cs_pol_bit[MAX_CHIP_SELECT] = {
946                         SPI_CS_POL_INACTIVE_0,
947                         SPI_CS_POL_INACTIVE_1,
948                         SPI_CS_POL_INACTIVE_2,
949                         SPI_CS_POL_INACTIVE_3,
950         };
951
952         BUG_ON(spi->chip_select >= MAX_CHIP_SELECT);
953
954         ret = pm_runtime_get_sync(tspi->dev);
955         if (ret < 0) {
956                 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
957                 return ret;
958         }
959
960         spin_lock_irqsave(&tspi->lock, flags);
961         if (!(spi->mode & SPI_CS_HIGH)) {
962                 val = tegra_spi_readl(tspi, SPI_COMMAND1);
963                 if (state)
964                         val &= ~cs_pol_bit[spi->chip_select];
965                 else
966                         val |= cs_pol_bit[spi->chip_select];
967                 tegra_spi_writel(tspi, val, SPI_COMMAND1);
968         }
969
970         spin_unlock_irqrestore(&tspi->lock, flags);
971         pm_runtime_put(tspi->dev);
972         return 0;
973 }
974
975 static int tegra_spi_wait_on_message_xfer(struct tegra_spi_data *tspi)
976 {
977         int ret;
978
979         ret = wait_for_completion_timeout(&tspi->xfer_completion,
980                         SPI_DMA_TIMEOUT);
981         if (WARN_ON(ret == 0)) {
982                 dev_err(tspi->dev,
983                                 "spi trasfer timeout, err %d\n", ret);
984                 if (tspi->is_curr_dma_xfer &&
985                                 (tspi->cur_direction & DATA_DIR_TX))
986                         dmaengine_terminate_all(tspi->tx_dma_chan);
987                 if (tspi->is_curr_dma_xfer &&
988                                 (tspi->cur_direction & DATA_DIR_RX))
989                         dmaengine_terminate_all(tspi->rx_dma_chan);
990                 ret = -EIO;
991                 return ret;
992         }
993         if (tspi->tx_status ||  tspi->rx_status) {
994                 dev_err(tspi->dev, "Error in Transfer\n");
995                 ret = -EIO;
996         }
997
998         return 0;
999 }
1000
1001 static int tegra_spi_wait_remain_message(struct tegra_spi_data *tspi,
1002                 struct spi_transfer *xfer)
1003 {
1004         unsigned total_fifo_words;
1005         int ret = 0;
1006
1007         INIT_COMPLETION(tspi->xfer_completion);
1008
1009         if (tspi->is_curr_dma_xfer) {
1010                 total_fifo_words = tegra_spi_calculate_curr_xfer_param(
1011                                 tspi->cur_spi, tspi, xfer);
1012                 if (total_fifo_words > SPI_FIFO_DEPTH)
1013                         ret = tegra_spi_start_dma_based_transfer(tspi, xfer);
1014                 else
1015                         ret = tegra_spi_start_cpu_based_transfer(tspi, xfer);
1016         } else {
1017                 tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, xfer);
1018                 tegra_spi_start_cpu_based_transfer(tspi, xfer);
1019         }
1020
1021         ret = tegra_spi_wait_on_message_xfer(tspi);
1022
1023         return ret;
1024 }
1025
1026 static int tegra_spi_handle_message(struct tegra_spi_data *tspi,
1027                 struct spi_transfer *xfer)
1028 {
1029         int ret = 0;
1030         long wait_status;
1031
1032         if (!tspi->is_curr_dma_xfer) {
1033                 if (tspi->cur_direction & DATA_DIR_RX)
1034                         tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, xfer);
1035                 if (tspi->cur_direction & DATA_DIR_TX)
1036                         tspi->cur_pos = tspi->cur_tx_pos;
1037                 else if (tspi->cur_direction & DATA_DIR_RX)
1038                         tspi->cur_pos = tspi->cur_rx_pos;
1039                 else
1040                         WARN_ON(1);
1041         } else {
1042                 if (tspi->cur_direction & DATA_DIR_TX) {
1043                         wait_status = wait_for_completion_interruptible_timeout(
1044                                         &tspi->tx_dma_complete,
1045                                         SPI_DMA_TIMEOUT);
1046                         if (wait_status <= 0) {
1047                                 dmaengine_terminate_all(tspi->tx_dma_chan);
1048                                 dev_err(tspi->dev, "TxDma Xfer failed\n");
1049                                 ret = -EIO;
1050                                 return ret;
1051                         }
1052                 }
1053                 if (tspi->cur_direction & DATA_DIR_RX) {
1054                         wait_status = wait_for_completion_interruptible_timeout(
1055                                         &tspi->rx_dma_complete,
1056                                         SPI_DMA_TIMEOUT);
1057                         if (wait_status <= 0) {
1058                                 dmaengine_terminate_all(tspi->rx_dma_chan);
1059                                 dev_err(tspi->dev,
1060                                                 "RxDma Xfer failed\n");
1061                                 ret = -EIO;
1062                                 return ret;
1063                         }
1064                 }
1065                 if (tspi->cur_direction & DATA_DIR_RX)
1066                         tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, xfer);
1067
1068                 if (tspi->cur_direction & DATA_DIR_TX)
1069                         tspi->cur_pos = tspi->cur_tx_pos;
1070                 else
1071                         tspi->cur_pos = tspi->cur_rx_pos;
1072
1073         }
1074         return 0;
1075 }
1076
1077 static int tegra_spi_transfer_one_message(struct spi_master *master,
1078                         struct spi_message *msg)
1079 {
1080         bool is_first_msg = true;
1081         bool is_new_msg = true;
1082         int single_xfer;
1083         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1084         struct spi_transfer *xfer;
1085         struct spi_device *spi = msg->spi;
1086         int ret;
1087
1088         msg->status = 0;
1089         msg->actual_length = 0;
1090
1091         ret = pm_runtime_get_sync(tspi->dev);
1092         if (ret < 0) {
1093                 dev_err(tspi->dev, "runtime PM get failed: %d\n", ret);
1094                 msg->status = ret;
1095                 spi_finalize_current_message(master);
1096                 return ret;
1097         }
1098
1099         single_xfer = list_is_singular(&msg->transfers);
1100         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1101                 while (1) {
1102                         if (is_new_msg) {
1103                                 INIT_COMPLETION(tspi->xfer_completion);
1104                                 ret = tegra_spi_start_transfer_one(spi, xfer,
1105                                                 is_first_msg, single_xfer);
1106                                 if (ret < 0) {
1107                                         dev_err(tspi->dev,
1108                                                         "spi cannot start transfer,err %d\n",
1109                                                         ret);
1110                                         goto exit;
1111                                 }
1112                                 is_first_msg = false;
1113                                 is_new_msg = false;
1114                                 ret = tegra_spi_wait_on_message_xfer(tspi);
1115                                 if (ret)
1116                                         goto exit;
1117                                 ret = tegra_spi_handle_message(tspi, xfer);
1118                                 if (ret)
1119                                         goto exit;
1120                                 if (tspi->cur_pos == xfer->len) {
1121                                         is_new_msg = true;
1122                                         break;
1123                                 }
1124                         } else {
1125                                 ret = tegra_spi_wait_remain_message(tspi, xfer);
1126                                 if (ret)
1127                                         goto exit;
1128                                 ret = tegra_spi_handle_message(tspi, xfer);
1129                                 if (ret)
1130                                         goto exit;
1131                                 if (tspi->cur_pos == xfer->len) {
1132                                         is_new_msg = true;
1133                                         break;
1134                                 }
1135                         }
1136                 } /* End of while */
1137                 msg->actual_length += xfer->len;
1138                 if (xfer->cs_change && xfer->delay_usecs) {
1139                         tegra_spi_writel(tspi, tspi->def_command1_reg,
1140                                         SPI_COMMAND1);
1141                         udelay(xfer->delay_usecs);
1142                 }
1143         }
1144         ret = 0;
1145 exit:
1146         tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1147         pm_runtime_put(tspi->dev);
1148         msg->status = ret;
1149         spi_finalize_current_message(master);
1150         return ret;
1151 }
1152
1153 static void handle_cpu_based_err_xfer(struct tegra_spi_data *tspi)
1154 {
1155         unsigned long flags;
1156
1157         spin_lock_irqsave(&tspi->lock, flags);
1158         if (tspi->tx_status ||  tspi->rx_status) {
1159                 dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n",
1160                         tspi->status_reg);
1161                 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
1162                         tspi->command1_reg, tspi->dma_control_reg);
1163                 tegra_periph_reset_assert(tspi->clk);
1164                 udelay(2);
1165                 tegra_periph_reset_deassert(tspi->clk);
1166         }
1167         spin_unlock_irqrestore(&tspi->lock, flags);
1168 }
1169
1170 static void handle_dma_based_err_xfer(struct tegra_spi_data *tspi)
1171 {
1172         int err = 0;
1173         unsigned long flags;
1174
1175         spin_lock_irqsave(&tspi->lock, flags);
1176         /* Abort dmas if any error */
1177         if (tspi->cur_direction & DATA_DIR_TX) {
1178                 if (tspi->tx_status) {
1179                         dmaengine_terminate_all(tspi->tx_dma_chan);
1180                         err += 1;
1181                 }
1182         }
1183
1184         if (tspi->cur_direction & DATA_DIR_RX) {
1185                 if (tspi->rx_status) {
1186                         dmaengine_terminate_all(tspi->rx_dma_chan);
1187                         err += 2;
1188                 }
1189         }
1190
1191         if (err) {
1192                 dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n",
1193                         tspi->status_reg);
1194                 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
1195                         tspi->command1_reg, tspi->dma_control_reg);
1196                 tegra_periph_reset_assert(tspi->clk);
1197                 udelay(2);
1198                 tegra_periph_reset_deassert(tspi->clk);
1199         }
1200         spin_unlock_irqrestore(&tspi->lock, flags);
1201 }
1202
1203 static irqreturn_t tegra_spi_isr(int irq, void *context_data)
1204 {
1205         struct tegra_spi_data *tspi = context_data;
1206
1207         tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1208         if (tspi->cur_direction & DATA_DIR_TX)
1209                 tspi->tx_status = tspi->status_reg &
1210                                         (SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF);
1211
1212         if (tspi->cur_direction & DATA_DIR_RX)
1213                 tspi->rx_status = tspi->status_reg &
1214                                         (SPI_RX_FIFO_OVF | SPI_RX_FIFO_UNF);
1215
1216         if (!(tspi->cur_direction & DATA_DIR_TX) &&
1217                         !(tspi->cur_direction & DATA_DIR_RX))
1218                 dev_err(tspi->dev, "spurious interrupt, status_reg = 0x%x\n",
1219                                 tspi->status_reg);
1220
1221         tegra_spi_clear_status(tspi);
1222         if (!tspi->is_curr_dma_xfer)
1223                 handle_cpu_based_err_xfer(tspi);
1224         else
1225                 handle_dma_based_err_xfer(tspi);
1226
1227         complete(&tspi->xfer_completion);
1228         return IRQ_HANDLED;
1229 }
1230
1231 static struct tegra_spi_platform_data *tegra_spi_parse_dt(
1232                 struct platform_device *pdev)
1233 {
1234         struct tegra_spi_platform_data *pdata;
1235         const unsigned int *prop;
1236         struct device_node *np = pdev->dev.of_node;
1237
1238         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1239         if (!pdata) {
1240                 dev_err(&pdev->dev, "Memory alloc for pdata failed\n");
1241                 return NULL;
1242         }
1243
1244         prop = of_get_property(np, "spi-max-frequency", NULL);
1245         if (prop)
1246                 pdata->spi_max_frequency = be32_to_cpup(prop);
1247
1248         if (of_find_property(np, "nvidia,clock-always-on", NULL))
1249                 pdata->is_clkon_always = true;
1250
1251         return pdata;
1252 }
1253
1254 static struct of_device_id tegra_spi_of_match[] = {
1255         { .compatible = "nvidia,tegra114-spi", },
1256         {}
1257 };
1258 MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
1259
1260 static int tegra_spi_probe(struct platform_device *pdev)
1261 {
1262         struct spi_master       *master;
1263         struct tegra_spi_data   *tspi;
1264         struct resource         *r;
1265         struct tegra_spi_platform_data *pdata = pdev->dev.platform_data;
1266         int ret, spi_irq;
1267         int bus_num;
1268
1269         if (pdev->dev.of_node) {
1270                 bus_num = of_alias_get_id(pdev->dev.of_node, "spi");
1271                 if (bus_num < 0) {
1272                         dev_warn(&pdev->dev,
1273                                 "Dynamic bus number will be registerd\n");
1274                         bus_num = -1;
1275                 }
1276         } else {
1277                 bus_num = pdev->id;
1278         }
1279
1280         if (!pdata && pdev->dev.of_node)
1281                 pdata = tegra_spi_parse_dt(pdev);
1282
1283         if (!pdata) {
1284                 dev_err(&pdev->dev, "No platform data, exiting\n");
1285                 return -ENODEV;
1286         }
1287
1288         if (!pdata->spi_max_frequency)
1289                 pdata->spi_max_frequency = 25000000; /* 25MHz */
1290
1291         master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1292         if (!master) {
1293                 dev_err(&pdev->dev, "master allocation failed\n");
1294                 return -ENOMEM;
1295         }
1296
1297         /* the spi->mode bits understood by this driver: */
1298         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1299         master->setup = tegra_spi_setup;
1300         master->transfer_one_message = tegra_spi_transfer_one_message;
1301         master->num_chipselect = MAX_CHIP_SELECT;
1302         master->bus_num = bus_num;
1303         master->spi_cs_low  = tegra_spi_cs_low;
1304
1305         dev_set_drvdata(&pdev->dev, master);
1306         tspi = spi_master_get_devdata(master);
1307         tspi->master = master;
1308         tspi->clock_always_on = pdata->is_clkon_always;
1309         tspi->dev = &pdev->dev;
1310         spin_lock_init(&tspi->lock);
1311
1312         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1313         if (!r) {
1314                 dev_err(&pdev->dev, "No IO memory resource\n");
1315                 ret = -ENODEV;
1316                 goto exit_free_master;
1317         }
1318         tspi->phys = r->start;
1319         tspi->base = devm_request_and_ioremap(&pdev->dev, r);
1320         if (!tspi->base) {
1321                 dev_err(&pdev->dev,
1322                         "Cannot request memregion/iomap dma address\n");
1323                 ret = -EADDRNOTAVAIL;
1324                 goto exit_free_master;
1325         }
1326
1327         spi_irq = platform_get_irq(pdev, 0);
1328         tspi->irq = spi_irq;
1329         ret = request_irq(tspi->irq, tegra_spi_isr, 0,
1330                         dev_name(&pdev->dev), tspi);
1331         if (ret < 0) {
1332                 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1333                                         tspi->irq);
1334                 goto exit_free_master;
1335         }
1336
1337         tspi->clk = devm_clk_get(&pdev->dev, "spi");
1338         if (IS_ERR(tspi->clk)) {
1339                 dev_err(&pdev->dev, "can not get clock\n");
1340                 ret = PTR_ERR(tspi->clk);
1341                 goto exit_free_irq;
1342         }
1343
1344         tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
1345         tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1346         tspi->spi_max_frequency = pdata->spi_max_frequency;
1347
1348         ret = tegra_spi_init_dma_param(tspi, true);
1349         if (ret < 0)
1350                 goto exit_free_irq;
1351         ret = tegra_spi_init_dma_param(tspi, false);
1352         if (ret < 0)
1353                 goto exit_rx_dma_free;
1354         tspi->max_buf_size = tspi->dma_buf_size;
1355         init_completion(&tspi->tx_dma_complete);
1356         init_completion(&tspi->rx_dma_complete);
1357
1358         init_completion(&tspi->xfer_completion);
1359
1360         if (tspi->clock_always_on) {
1361                 ret = clk_prepare_enable(tspi->clk);
1362                 if (ret < 0) {
1363                         dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1364                         goto exit_deinit_dma;
1365                 }
1366         }
1367         pm_runtime_enable(&pdev->dev);
1368         if (!pm_runtime_enabled(&pdev->dev)) {
1369                 ret = tegra_spi_runtime_resume(&pdev->dev);
1370                 if (ret)
1371                         goto exit_pm_disable;
1372         }
1373
1374         ret = pm_runtime_get_sync(&pdev->dev);
1375         if (ret < 0) {
1376                 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1377                 goto exit_pm_disable;
1378         }
1379         tspi->def_command1_reg  = SPI_M_S | SPI_LSBYTE_FE;
1380         tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1381         tspi->def_command2_reg = tegra_spi_readl(tspi, SPI_COMMAND2);
1382         pm_runtime_put(&pdev->dev);
1383
1384         master->dev.of_node = pdev->dev.of_node;
1385         ret = spi_register_master(master);
1386         if (ret < 0) {
1387                 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1388                 goto exit_pm_disable;
1389         }
1390         return ret;
1391
1392 exit_pm_disable:
1393         pm_runtime_disable(&pdev->dev);
1394         if (!pm_runtime_status_suspended(&pdev->dev))
1395                 tegra_spi_runtime_suspend(&pdev->dev);
1396         if (tspi->clock_always_on)
1397                 clk_disable_unprepare(tspi->clk);
1398 exit_deinit_dma:
1399         tegra_spi_deinit_dma_param(tspi, false);
1400 exit_rx_dma_free:
1401         tegra_spi_deinit_dma_param(tspi, true);
1402 exit_free_irq:
1403         free_irq(spi_irq, tspi);
1404 exit_free_master:
1405         spi_master_put(master);
1406         return ret;
1407 }
1408
1409 static int tegra_spi_remove(struct platform_device *pdev)
1410 {
1411         struct spi_master *master = dev_get_drvdata(&pdev->dev);
1412         struct tegra_spi_data   *tspi = spi_master_get_devdata(master);
1413
1414         free_irq(tspi->irq, tspi);
1415         spi_unregister_master(master);
1416
1417         if (tspi->tx_dma_chan)
1418                 tegra_spi_deinit_dma_param(tspi, false);
1419
1420         if (tspi->rx_dma_chan)
1421                 tegra_spi_deinit_dma_param(tspi, true);
1422
1423         pm_runtime_disable(&pdev->dev);
1424         if (!pm_runtime_status_suspended(&pdev->dev))
1425                 tegra_spi_runtime_suspend(&pdev->dev);
1426
1427         if (tspi->clock_always_on)
1428                 clk_disable_unprepare(tspi->clk);
1429
1430         return 0;
1431 }
1432
1433 #ifdef CONFIG_PM_SLEEP
1434 static int tegra_spi_suspend(struct device *dev)
1435 {
1436         struct spi_master *master = dev_get_drvdata(dev);
1437         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1438         int ret;
1439
1440         ret = spi_master_suspend(master);
1441
1442         if (tspi->clock_always_on)
1443                 clk_disable_unprepare(tspi->clk);
1444
1445         return ret;
1446 }
1447
1448 static int tegra_spi_resume(struct device *dev)
1449 {
1450         struct spi_master *master = dev_get_drvdata(dev);
1451         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1452         int ret;
1453
1454         if (tspi->clock_always_on) {
1455                 ret = clk_prepare_enable(tspi->clk);
1456                 if (ret < 0) {
1457                         dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1458                         return ret;
1459                 }
1460         }
1461
1462         ret = pm_runtime_get_sync(dev);
1463         if (ret < 0) {
1464                 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1465                 return ret;
1466         }
1467         tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
1468         tegra_spi_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2);
1469         pm_runtime_put(dev);
1470
1471         return spi_master_resume(master);
1472 }
1473 #endif
1474
1475 static int tegra_spi_runtime_suspend(struct device *dev)
1476 {
1477         struct spi_master *master = dev_get_drvdata(dev);
1478         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1479
1480         /* Flush all write which are in PPSB queue by reading back */
1481         tegra_spi_readl(tspi, SPI_COMMAND1);
1482
1483         clk_disable_unprepare(tspi->clk);
1484         return 0;
1485 }
1486
1487 static int tegra_spi_runtime_resume(struct device *dev)
1488 {
1489         struct spi_master *master = dev_get_drvdata(dev);
1490         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1491         int ret;
1492
1493         ret = clk_prepare_enable(tspi->clk);
1494         if (ret < 0) {
1495                 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1496                 return ret;
1497         }
1498         return 0;
1499 }
1500
1501 static const struct dev_pm_ops tegra_spi_pm_ops = {
1502         SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend,
1503                 tegra_spi_runtime_resume, NULL)
1504         SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend, tegra_spi_resume)
1505 };
1506 static struct platform_driver tegra_spi_driver = {
1507         .driver = {
1508                 .name           = "spi-tegra114",
1509                 .owner          = THIS_MODULE,
1510                 .pm             = &tegra_spi_pm_ops,
1511                 .of_match_table = of_match_ptr(tegra_spi_of_match),
1512         },
1513         .probe =        tegra_spi_probe,
1514         .remove =       tegra_spi_remove,
1515 };
1516 module_platform_driver(tegra_spi_driver);
1517
1518 MODULE_ALIAS("platform:spi-tegra114");
1519 MODULE_DESCRIPTION("NVIDIA Tegra114/124 SPI Controller Driver");
1520 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1521 MODULE_LICENSE("GPL v2");