Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty-2.6
[linux-3.10.git] / drivers / serial / mfd.c
1 /*
2  * mfd.c: driver for High Speed UART device of Intel Medfield platform
3  *
4  * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
5  *
6  * (C) Copyright 2010 Intel Corporation
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * as published by the Free Software Foundation; version 2
11  * of the License.
12  */
13
14 /* Notes:
15  * 1. DMA channel allocation: 0/1 channel are assigned to port 0,
16  *    2/3 chan to port 1, 4/5 chan to port 3. Even number chans
17  *    are used for RX, odd chans for TX
18  *
19  * 2. In A0 stepping, UART will not support TX half empty flag
20  *
21  * 3. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
22  *    asserted, only when the HW is reset the DDCD and DDSR will
23  *    be triggered
24  */
25
26 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <linux/console.h>
29 #include <linux/sysrq.h>
30 #include <linux/slab.h>
31 #include <linux/serial_reg.h>
32 #include <linux/circ_buf.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/tty.h>
36 #include <linux/tty_flip.h>
37 #include <linux/serial_core.h>
38 #include <linux/serial_mfd.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/pci.h>
41 #include <linux/io.h>
42 #include <linux/debugfs.h>
43
44 #define  MFD_HSU_A0_STEPPING    1
45
46 #define HSU_DMA_BUF_SIZE        2048
47
48 #define chan_readl(chan, offset)        readl(chan->reg + offset)
49 #define chan_writel(chan, offset, val)  writel(val, chan->reg + offset)
50
51 #define mfd_readl(obj, offset)          readl(obj->reg + offset)
52 #define mfd_writel(obj, offset, val)    writel(val, obj->reg + offset)
53
54 #define HSU_DMA_TIMEOUT_CHECK_FREQ      (HZ/10)
55
56 struct hsu_dma_buffer {
57         u8              *buf;
58         dma_addr_t      dma_addr;
59         u32             dma_size;
60         u32             ofs;
61 };
62
63 struct hsu_dma_chan {
64         u32     id;
65         enum dma_data_direction dirt;
66         struct uart_hsu_port    *uport;
67         void __iomem            *reg;
68         struct timer_list       rx_timer; /* only needed by RX channel */
69 };
70
71 struct uart_hsu_port {
72         struct uart_port        port;
73         unsigned char           ier;
74         unsigned char           lcr;
75         unsigned char           mcr;
76         unsigned int            lsr_break_flag;
77         char                    name[12];
78         int                     index;
79         struct device           *dev;
80
81         struct hsu_dma_chan     *txc;
82         struct hsu_dma_chan     *rxc;
83         struct hsu_dma_buffer   txbuf;
84         struct hsu_dma_buffer   rxbuf;
85         int                     use_dma;        /* flag for DMA/PIO */
86         int                     running;
87         int                     dma_tx_on;
88 };
89
90 /* Top level data structure of HSU */
91 struct hsu_port {
92         void __iomem    *reg;
93         unsigned long   paddr;
94         unsigned long   iolen;
95         u32             irq;
96
97         struct uart_hsu_port    port[3];
98         struct hsu_dma_chan     chans[10];
99
100         struct dentry *debugfs;
101 };
102
103 static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
104 {
105         unsigned int val;
106
107         if (offset > UART_MSR) {
108                 offset <<= 2;
109                 val = readl(up->port.membase + offset);
110         } else
111                 val = (unsigned int)readb(up->port.membase + offset);
112
113         return val;
114 }
115
116 static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
117 {
118         if (offset > UART_MSR) {
119                 offset <<= 2;
120                 writel(value, up->port.membase + offset);
121         } else {
122                 unsigned char val = value & 0xff;
123                 writeb(val, up->port.membase + offset);
124         }
125 }
126
127 #ifdef CONFIG_DEBUG_FS
128
129 #define HSU_REGS_BUFSIZE        1024
130
131 static int hsu_show_regs_open(struct inode *inode, struct file *file)
132 {
133         file->private_data = inode->i_private;
134         return 0;
135 }
136
137 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
138                                 size_t count, loff_t *ppos)
139 {
140         struct uart_hsu_port *up = file->private_data;
141         char *buf;
142         u32 len = 0;
143         ssize_t ret;
144
145         buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
146         if (!buf)
147                 return 0;
148
149         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
150                         "MFD HSU port[%d] regs:\n", up->index);
151
152         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
153                         "=================================\n");
154         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
155                         "IER: \t\t0x%08x\n", serial_in(up, UART_IER));
156         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
157                         "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
158         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
159                         "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
160         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
161                         "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
162         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
163                         "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
164         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
165                         "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
166         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
167                         "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
168         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
169                         "PS: \t\t0x%08x\n", serial_in(up, UART_PS));
170         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
171                         "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
172         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
173                         "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
174
175         if (len > HSU_REGS_BUFSIZE)
176                 len = HSU_REGS_BUFSIZE;
177
178         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
179         kfree(buf);
180         return ret;
181 }
182
183 static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
184                                 size_t count, loff_t *ppos)
185 {
186         struct hsu_dma_chan *chan = file->private_data;
187         char *buf;
188         u32 len = 0;
189         ssize_t ret;
190
191         buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
192         if (!buf)
193                 return 0;
194
195         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
196                         "MFD HSU DMA channel [%d] regs:\n", chan->id);
197
198         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
199                         "=================================\n");
200         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
201                         "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR));
202         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
203                         "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR));
204         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
205                         "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR));
206         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
207                         "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR));
208         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
209                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR));
210         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
211                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR));
212         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
213                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR));
214         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
215                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR));
216         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
217                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR));
218         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
219                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR));
220         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
221                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR));
222         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
223                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
224
225         if (len > HSU_REGS_BUFSIZE)
226                 len = HSU_REGS_BUFSIZE;
227
228         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
229         kfree(buf);
230         return ret;
231 }
232
233 static const struct file_operations port_regs_ops = {
234         .owner          = THIS_MODULE,
235         .open           = hsu_show_regs_open,
236         .read           = port_show_regs,
237         .llseek         = default_llseek,
238 };
239
240 static const struct file_operations dma_regs_ops = {
241         .owner          = THIS_MODULE,
242         .open           = hsu_show_regs_open,
243         .read           = dma_show_regs,
244         .llseek         = default_llseek,
245 };
246
247 static int hsu_debugfs_init(struct hsu_port *hsu)
248 {
249         int i;
250         char name[32];
251
252         hsu->debugfs = debugfs_create_dir("hsu", NULL);
253         if (!hsu->debugfs)
254                 return -ENOMEM;
255
256         for (i = 0; i < 3; i++) {
257                 snprintf(name, sizeof(name), "port_%d_regs", i);
258                 debugfs_create_file(name, S_IFREG | S_IRUGO,
259                         hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops);
260         }
261
262         for (i = 0; i < 6; i++) {
263                 snprintf(name, sizeof(name), "dma_chan_%d_regs", i);
264                 debugfs_create_file(name, S_IFREG | S_IRUGO,
265                         hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops);
266         }
267
268         return 0;
269 }
270
271 static void hsu_debugfs_remove(struct hsu_port *hsu)
272 {
273         if (hsu->debugfs)
274                 debugfs_remove_recursive(hsu->debugfs);
275 }
276
277 #else
278 static inline int hsu_debugfs_init(struct hsu_port *hsu)
279 {
280         return 0;
281 }
282
283 static inline void hsu_debugfs_remove(struct hsu_port *hsu)
284 {
285 }
286 #endif /* CONFIG_DEBUG_FS */
287
288 static void serial_hsu_enable_ms(struct uart_port *port)
289 {
290         struct uart_hsu_port *up =
291                 container_of(port, struct uart_hsu_port, port);
292
293         up->ier |= UART_IER_MSI;
294         serial_out(up, UART_IER, up->ier);
295 }
296
297 void hsu_dma_tx(struct uart_hsu_port *up)
298 {
299         struct circ_buf *xmit = &up->port.state->xmit;
300         struct hsu_dma_buffer *dbuf = &up->txbuf;
301         int count;
302
303         /* test_and_set_bit may be better, but anyway it's in lock protected mode */
304         if (up->dma_tx_on)
305                 return;
306
307         /* Update the circ buf info */
308         xmit->tail += dbuf->ofs;
309         xmit->tail &= UART_XMIT_SIZE - 1;
310
311         up->port.icount.tx += dbuf->ofs;
312         dbuf->ofs = 0;
313
314         /* Disable the channel */
315         chan_writel(up->txc, HSU_CH_CR, 0x0);
316
317         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
318                 dma_sync_single_for_device(up->port.dev,
319                                            dbuf->dma_addr,
320                                            dbuf->dma_size,
321                                            DMA_TO_DEVICE);
322
323                 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
324                 dbuf->ofs = count;
325
326                 /* Reprogram the channel */
327                 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
328                 chan_writel(up->txc, HSU_CH_D0TSR, count);
329
330                 /* Reenable the channel */
331                 chan_writel(up->txc, HSU_CH_DCR, 0x1
332                                                  | (0x1 << 8)
333                                                  | (0x1 << 16)
334                                                  | (0x1 << 24));
335                 up->dma_tx_on = 1;
336                 chan_writel(up->txc, HSU_CH_CR, 0x1);
337         }
338
339         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
340                 uart_write_wakeup(&up->port);
341 }
342
343 /* The buffer is already cache coherent */
344 void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf)
345 {
346         dbuf->ofs = 0;
347
348         chan_writel(rxc, HSU_CH_BSR, 32);
349         chan_writel(rxc, HSU_CH_MOTSR, 4);
350
351         chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr);
352         chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size);
353         chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8)
354                                          | (0x1 << 16)
355                                          | (0x1 << 24)  /* timeout bit, see HSU Errata 1 */
356                                          );
357         chan_writel(rxc, HSU_CH_CR, 0x3);
358
359         mod_timer(&rxc->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
360 }
361
362 /* Protected by spin_lock_irqsave(port->lock) */
363 static void serial_hsu_start_tx(struct uart_port *port)
364 {
365         struct uart_hsu_port *up =
366                 container_of(port, struct uart_hsu_port, port);
367
368         if (up->use_dma) {
369                 hsu_dma_tx(up);
370         } else if (!(up->ier & UART_IER_THRI)) {
371                 up->ier |= UART_IER_THRI;
372                 serial_out(up, UART_IER, up->ier);
373         }
374 }
375
376 static void serial_hsu_stop_tx(struct uart_port *port)
377 {
378         struct uart_hsu_port *up =
379                 container_of(port, struct uart_hsu_port, port);
380         struct hsu_dma_chan *txc = up->txc;
381
382         if (up->use_dma)
383                 chan_writel(txc, HSU_CH_CR, 0x0);
384         else if (up->ier & UART_IER_THRI) {
385                 up->ier &= ~UART_IER_THRI;
386                 serial_out(up, UART_IER, up->ier);
387         }
388 }
389
390 /* This is always called in spinlock protected mode, so
391  * modify timeout timer is safe here */
392 void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
393 {
394         struct hsu_dma_buffer *dbuf = &up->rxbuf;
395         struct hsu_dma_chan *chan = up->rxc;
396         struct uart_port *port = &up->port;
397         struct tty_struct *tty = port->state->port.tty;
398         int count;
399
400         if (!tty)
401                 return;
402
403         /*
404          * First need to know how many is already transferred,
405          * then check if its a timeout DMA irq, and return
406          * the trail bytes out, push them up and reenable the
407          * channel
408          */
409
410         /* Timeout IRQ, need wait some time, see Errata 2 */
411         if (int_sts & 0xf00)
412                 udelay(2);
413
414         /* Stop the channel */
415         chan_writel(chan, HSU_CH_CR, 0x0);
416
417         count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
418         if (!count) {
419                 /* Restart the channel before we leave */
420                 chan_writel(chan, HSU_CH_CR, 0x3);
421                 return;
422         }
423         del_timer(&chan->rx_timer);
424
425         dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
426                         dbuf->dma_size, DMA_FROM_DEVICE);
427
428         /*
429          * Head will only wrap around when we recycle
430          * the DMA buffer, and when that happens, we
431          * explicitly set tail to 0. So head will
432          * always be greater than tail.
433          */
434         tty_insert_flip_string(tty, dbuf->buf, count);
435         port->icount.rx += count;
436
437         dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
438                         dbuf->dma_size, DMA_FROM_DEVICE);
439
440         /* Reprogram the channel */
441         chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr);
442         chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size);
443         chan_writel(chan, HSU_CH_DCR, 0x1
444                                          | (0x1 << 8)
445                                          | (0x1 << 16)
446                                          | (0x1 << 24)  /* timeout bit, see HSU Errata 1 */
447                                          );
448         tty_flip_buffer_push(tty);
449
450         chan_writel(chan, HSU_CH_CR, 0x3);
451         chan->rx_timer.expires = jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ;
452         add_timer(&chan->rx_timer);
453
454 }
455
456 static void serial_hsu_stop_rx(struct uart_port *port)
457 {
458         struct uart_hsu_port *up =
459                 container_of(port, struct uart_hsu_port, port);
460         struct hsu_dma_chan *chan = up->rxc;
461
462         if (up->use_dma)
463                 chan_writel(chan, HSU_CH_CR, 0x2);
464         else {
465                 up->ier &= ~UART_IER_RLSI;
466                 up->port.read_status_mask &= ~UART_LSR_DR;
467                 serial_out(up, UART_IER, up->ier);
468         }
469 }
470
471 static inline void receive_chars(struct uart_hsu_port *up, int *status)
472 {
473         struct tty_struct *tty = up->port.state->port.tty;
474         unsigned int ch, flag;
475         unsigned int max_count = 256;
476
477         if (!tty)
478                 return;
479
480         do {
481                 ch = serial_in(up, UART_RX);
482                 flag = TTY_NORMAL;
483                 up->port.icount.rx++;
484
485                 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
486                                        UART_LSR_FE | UART_LSR_OE))) {
487
488                         dev_warn(up->dev, "We really rush into ERR/BI case"
489                                 "status = 0x%02x", *status);
490                         /* For statistics only */
491                         if (*status & UART_LSR_BI) {
492                                 *status &= ~(UART_LSR_FE | UART_LSR_PE);
493                                 up->port.icount.brk++;
494                                 /*
495                                  * We do the SysRQ and SAK checking
496                                  * here because otherwise the break
497                                  * may get masked by ignore_status_mask
498                                  * or read_status_mask.
499                                  */
500                                 if (uart_handle_break(&up->port))
501                                         goto ignore_char;
502                         } else if (*status & UART_LSR_PE)
503                                 up->port.icount.parity++;
504                         else if (*status & UART_LSR_FE)
505                                 up->port.icount.frame++;
506                         if (*status & UART_LSR_OE)
507                                 up->port.icount.overrun++;
508
509                         /* Mask off conditions which should be ignored. */
510                         *status &= up->port.read_status_mask;
511
512 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
513                         if (up->port.cons &&
514                                 up->port.cons->index == up->port.line) {
515                                 /* Recover the break flag from console xmit */
516                                 *status |= up->lsr_break_flag;
517                                 up->lsr_break_flag = 0;
518                         }
519 #endif
520                         if (*status & UART_LSR_BI) {
521                                 flag = TTY_BREAK;
522                         } else if (*status & UART_LSR_PE)
523                                 flag = TTY_PARITY;
524                         else if (*status & UART_LSR_FE)
525                                 flag = TTY_FRAME;
526                 }
527
528                 if (uart_handle_sysrq_char(&up->port, ch))
529                         goto ignore_char;
530
531                 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
532         ignore_char:
533                 *status = serial_in(up, UART_LSR);
534         } while ((*status & UART_LSR_DR) && max_count--);
535         tty_flip_buffer_push(tty);
536 }
537
538 static void transmit_chars(struct uart_hsu_port *up)
539 {
540         struct circ_buf *xmit = &up->port.state->xmit;
541         int count;
542
543         if (up->port.x_char) {
544                 serial_out(up, UART_TX, up->port.x_char);
545                 up->port.icount.tx++;
546                 up->port.x_char = 0;
547                 return;
548         }
549         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
550                 serial_hsu_stop_tx(&up->port);
551                 return;
552         }
553
554 #ifndef MFD_HSU_A0_STEPPING
555         count = up->port.fifosize / 2;
556 #else
557         /*
558          * A0 only supports fully empty IRQ, and the first char written
559          * into it won't clear the EMPT bit, so we may need be cautious
560          * by useing a shorter buffer
561          */
562         count = up->port.fifosize - 4;
563 #endif
564         do {
565                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
566                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
567
568                 up->port.icount.tx++;
569                 if (uart_circ_empty(xmit))
570                         break;
571         } while (--count > 0);
572
573         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
574                 uart_write_wakeup(&up->port);
575
576         if (uart_circ_empty(xmit))
577                 serial_hsu_stop_tx(&up->port);
578 }
579
580 static inline void check_modem_status(struct uart_hsu_port *up)
581 {
582         int status;
583
584         status = serial_in(up, UART_MSR);
585
586         if ((status & UART_MSR_ANY_DELTA) == 0)
587                 return;
588
589         if (status & UART_MSR_TERI)
590                 up->port.icount.rng++;
591         if (status & UART_MSR_DDSR)
592                 up->port.icount.dsr++;
593         /* We may only get DDCD when HW init and reset */
594         if (status & UART_MSR_DDCD)
595                 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
596         /* Will start/stop_tx accordingly */
597         if (status & UART_MSR_DCTS)
598                 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
599
600         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
601 }
602
603 /*
604  * This handles the interrupt from one port.
605  */
606 static irqreturn_t port_irq(int irq, void *dev_id)
607 {
608         struct uart_hsu_port *up = dev_id;
609         unsigned int iir, lsr;
610         unsigned long flags;
611
612         if (unlikely(!up->running))
613                 return IRQ_NONE;
614
615         spin_lock_irqsave(&up->port.lock, flags);
616         if (up->use_dma) {
617                 lsr = serial_in(up, UART_LSR);
618                 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
619                                        UART_LSR_FE | UART_LSR_OE)))
620                         dev_warn(up->dev,
621                                 "Got lsr irq while using DMA, lsr = 0x%2x\n",
622                                 lsr);
623                 check_modem_status(up);
624                 spin_unlock_irqrestore(&up->port.lock, flags);
625                 return IRQ_HANDLED;
626         }
627
628         iir = serial_in(up, UART_IIR);
629         if (iir & UART_IIR_NO_INT) {
630                 spin_unlock_irqrestore(&up->port.lock, flags);
631                 return IRQ_NONE;
632         }
633
634         lsr = serial_in(up, UART_LSR);
635         if (lsr & UART_LSR_DR)
636                 receive_chars(up, &lsr);
637         check_modem_status(up);
638
639         /* lsr will be renewed during the receive_chars */
640         if (lsr & UART_LSR_THRE)
641                 transmit_chars(up);
642
643         spin_unlock_irqrestore(&up->port.lock, flags);
644         return IRQ_HANDLED;
645 }
646
647 static inline void dma_chan_irq(struct hsu_dma_chan *chan)
648 {
649         struct uart_hsu_port *up = chan->uport;
650         unsigned long flags;
651         u32 int_sts;
652
653         spin_lock_irqsave(&up->port.lock, flags);
654
655         if (!up->use_dma || !up->running)
656                 goto exit;
657
658         /*
659          * No matter what situation, need read clear the IRQ status
660          * There is a bug, see Errata 5, HSD 2900918
661          */
662         int_sts = chan_readl(chan, HSU_CH_SR);
663
664         /* Rx channel */
665         if (chan->dirt == DMA_FROM_DEVICE)
666                 hsu_dma_rx(up, int_sts);
667
668         /* Tx channel */
669         if (chan->dirt == DMA_TO_DEVICE) {
670                 chan_writel(chan, HSU_CH_CR, 0x0);
671                 up->dma_tx_on = 0;
672                 hsu_dma_tx(up);
673         }
674
675 exit:
676         spin_unlock_irqrestore(&up->port.lock, flags);
677         return;
678 }
679
680 static irqreturn_t dma_irq(int irq, void *dev_id)
681 {
682         struct hsu_port *hsu = dev_id;
683         u32 int_sts, i;
684
685         int_sts = mfd_readl(hsu, HSU_GBL_DMAISR);
686
687         /* Currently we only have 6 channels may be used */
688         for (i = 0; i < 6; i++) {
689                 if (int_sts & 0x1)
690                         dma_chan_irq(&hsu->chans[i]);
691                 int_sts >>= 1;
692         }
693
694         return IRQ_HANDLED;
695 }
696
697 static unsigned int serial_hsu_tx_empty(struct uart_port *port)
698 {
699         struct uart_hsu_port *up =
700                 container_of(port, struct uart_hsu_port, port);
701         unsigned long flags;
702         unsigned int ret;
703
704         spin_lock_irqsave(&up->port.lock, flags);
705         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
706         spin_unlock_irqrestore(&up->port.lock, flags);
707
708         return ret;
709 }
710
711 static unsigned int serial_hsu_get_mctrl(struct uart_port *port)
712 {
713         struct uart_hsu_port *up =
714                 container_of(port, struct uart_hsu_port, port);
715         unsigned char status;
716         unsigned int ret;
717
718         status = serial_in(up, UART_MSR);
719
720         ret = 0;
721         if (status & UART_MSR_DCD)
722                 ret |= TIOCM_CAR;
723         if (status & UART_MSR_RI)
724                 ret |= TIOCM_RNG;
725         if (status & UART_MSR_DSR)
726                 ret |= TIOCM_DSR;
727         if (status & UART_MSR_CTS)
728                 ret |= TIOCM_CTS;
729         return ret;
730 }
731
732 static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
733 {
734         struct uart_hsu_port *up =
735                 container_of(port, struct uart_hsu_port, port);
736         unsigned char mcr = 0;
737
738         if (mctrl & TIOCM_RTS)
739                 mcr |= UART_MCR_RTS;
740         if (mctrl & TIOCM_DTR)
741                 mcr |= UART_MCR_DTR;
742         if (mctrl & TIOCM_OUT1)
743                 mcr |= UART_MCR_OUT1;
744         if (mctrl & TIOCM_OUT2)
745                 mcr |= UART_MCR_OUT2;
746         if (mctrl & TIOCM_LOOP)
747                 mcr |= UART_MCR_LOOP;
748
749         mcr |= up->mcr;
750
751         serial_out(up, UART_MCR, mcr);
752 }
753
754 static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
755 {
756         struct uart_hsu_port *up =
757                 container_of(port, struct uart_hsu_port, port);
758         unsigned long flags;
759
760         spin_lock_irqsave(&up->port.lock, flags);
761         if (break_state == -1)
762                 up->lcr |= UART_LCR_SBC;
763         else
764                 up->lcr &= ~UART_LCR_SBC;
765         serial_out(up, UART_LCR, up->lcr);
766         spin_unlock_irqrestore(&up->port.lock, flags);
767 }
768
769 /*
770  * What special to do:
771  * 1. chose the 64B fifo mode
772  * 2. make sure not to select half empty mode for A0 stepping
773  * 3. start dma or pio depends on configuration
774  * 4. we only allocate dma memory when needed
775  */
776 static int serial_hsu_startup(struct uart_port *port)
777 {
778         struct uart_hsu_port *up =
779                 container_of(port, struct uart_hsu_port, port);
780         unsigned long flags;
781
782         /*
783          * Clear the FIFO buffers and disable them.
784          * (they will be reenabled in set_termios())
785          */
786         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
787         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
788                         UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
789         serial_out(up, UART_FCR, 0);
790
791         /* Clear the interrupt registers. */
792         (void) serial_in(up, UART_LSR);
793         (void) serial_in(up, UART_RX);
794         (void) serial_in(up, UART_IIR);
795         (void) serial_in(up, UART_MSR);
796
797         /* Now, initialize the UART, default is 8n1 */
798         serial_out(up, UART_LCR, UART_LCR_WLEN8);
799
800         spin_lock_irqsave(&up->port.lock, flags);
801
802         up->port.mctrl |= TIOCM_OUT2;
803         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
804
805         /*
806          * Finally, enable interrupts.  Note: Modem status interrupts
807          * are set via set_termios(), which will be occurring imminently
808          * anyway, so we don't enable them here.
809          */
810         if (!up->use_dma)
811                 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
812         else
813                 up->ier = 0;
814         serial_out(up, UART_IER, up->ier);
815
816         spin_unlock_irqrestore(&up->port.lock, flags);
817
818         /* DMA init */
819         if (up->use_dma) {
820                 struct hsu_dma_buffer *dbuf;
821                 struct circ_buf *xmit = &port->state->xmit;
822
823                 up->dma_tx_on = 0;
824
825                 /* First allocate the RX buffer */
826                 dbuf = &up->rxbuf;
827                 dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL);
828                 if (!dbuf->buf) {
829                         up->use_dma = 0;
830                         goto exit;
831                 }
832                 dbuf->dma_addr = dma_map_single(port->dev,
833                                                 dbuf->buf,
834                                                 HSU_DMA_BUF_SIZE,
835                                                 DMA_FROM_DEVICE);
836                 dbuf->dma_size = HSU_DMA_BUF_SIZE;
837
838                 /* Start the RX channel right now */
839                 hsu_dma_start_rx_chan(up->rxc, dbuf);
840
841                 /* Next init the TX DMA */
842                 dbuf = &up->txbuf;
843                 dbuf->buf = xmit->buf;
844                 dbuf->dma_addr = dma_map_single(port->dev,
845                                                dbuf->buf,
846                                                UART_XMIT_SIZE,
847                                                DMA_TO_DEVICE);
848                 dbuf->dma_size = UART_XMIT_SIZE;
849
850                 /* This should not be changed all around */
851                 chan_writel(up->txc, HSU_CH_BSR, 32);
852                 chan_writel(up->txc, HSU_CH_MOTSR, 4);
853                 dbuf->ofs = 0;
854         }
855
856 exit:
857          /* And clear the interrupt registers again for luck. */
858         (void) serial_in(up, UART_LSR);
859         (void) serial_in(up, UART_RX);
860         (void) serial_in(up, UART_IIR);
861         (void) serial_in(up, UART_MSR);
862
863         up->running = 1;
864         return 0;
865 }
866
867 static void serial_hsu_shutdown(struct uart_port *port)
868 {
869         struct uart_hsu_port *up =
870                 container_of(port, struct uart_hsu_port, port);
871         unsigned long flags;
872
873         del_timer_sync(&up->rxc->rx_timer);
874
875         /* Disable interrupts from this port */
876         up->ier = 0;
877         serial_out(up, UART_IER, 0);
878         up->running = 0;
879
880         spin_lock_irqsave(&up->port.lock, flags);
881         up->port.mctrl &= ~TIOCM_OUT2;
882         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
883         spin_unlock_irqrestore(&up->port.lock, flags);
884
885         /* Disable break condition and FIFOs */
886         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
887         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
888                                   UART_FCR_CLEAR_RCVR |
889                                   UART_FCR_CLEAR_XMIT);
890         serial_out(up, UART_FCR, 0);
891 }
892
893 static void
894 serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
895                        struct ktermios *old)
896 {
897         struct uart_hsu_port *up =
898                         container_of(port, struct uart_hsu_port, port);
899         struct tty_struct *tty = port->state->port.tty;
900         unsigned char cval, fcr = 0;
901         unsigned long flags;
902         unsigned int baud, quot;
903         u32 mul = 0x3600;
904         u32 ps = 0x10;
905
906         switch (termios->c_cflag & CSIZE) {
907         case CS5:
908                 cval = UART_LCR_WLEN5;
909                 break;
910         case CS6:
911                 cval = UART_LCR_WLEN6;
912                 break;
913         case CS7:
914                 cval = UART_LCR_WLEN7;
915                 break;
916         default:
917         case CS8:
918                 cval = UART_LCR_WLEN8;
919                 break;
920         }
921
922         /* CMSPAR isn't supported by this driver */
923         if (tty)
924                 tty->termios->c_cflag &= ~CMSPAR;
925
926         if (termios->c_cflag & CSTOPB)
927                 cval |= UART_LCR_STOP;
928         if (termios->c_cflag & PARENB)
929                 cval |= UART_LCR_PARITY;
930         if (!(termios->c_cflag & PARODD))
931                 cval |= UART_LCR_EPAR;
932
933         /*
934          * The base clk is 50Mhz, and the baud rate come from:
935          *      baud = 50M * MUL / (DIV * PS * DLAB)
936          *
937          * For those basic low baud rate we can get the direct
938          * scalar from 2746800, like 115200 = 2746800/24. For those
939          * higher baud rate, we handle them case by case, mainly by
940          * adjusting the MUL/PS registers, and DIV register is kept
941          * as default value 0x3d09 to make things simple
942          */
943         baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
944
945         quot = 1;
946         switch (baud) {
947         case 3500000:
948                 mul = 0x3345;
949                 ps = 0xC;
950                 break;
951         case 3000000:
952                 mul = 0x2EE0;
953                 break;
954         case 2500000:
955                 mul = 0x2710;
956                 break;
957         case 2000000:
958                 mul = 0x1F40;
959                 break;
960         case 1843200:
961                 mul = 0x2400;
962                 break;
963         case 1500000:
964                 mul = 0x1770;
965                 break;
966         case 1000000:
967                 mul = 0xFA0;
968                 break;
969         case 500000:
970                 mul = 0x7D0;
971                 break;
972         default:
973                 /* Use uart_get_divisor to get quot for other baud rates */
974                 quot = 0;
975         }
976
977         if (!quot)
978                 quot = uart_get_divisor(port, baud);
979
980         if ((up->port.uartclk / quot) < (2400 * 16))
981                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
982         else if ((up->port.uartclk / quot) < (230400 * 16))
983                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B;
984         else
985                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
986
987         fcr |= UART_FCR_HSU_64B_FIFO;
988 #ifdef MFD_HSU_A0_STEPPING
989         /* A0 doesn't support half empty IRQ */
990         fcr |= UART_FCR_FULL_EMPT_TXI;
991 #endif
992
993         /*
994          * Ok, we're now changing the port state.  Do it with
995          * interrupts disabled.
996          */
997         spin_lock_irqsave(&up->port.lock, flags);
998
999         /* Update the per-port timeout */
1000         uart_update_timeout(port, termios->c_cflag, baud);
1001
1002         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1003         if (termios->c_iflag & INPCK)
1004                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1005         if (termios->c_iflag & (BRKINT | PARMRK))
1006                 up->port.read_status_mask |= UART_LSR_BI;
1007
1008         /* Characters to ignore */
1009         up->port.ignore_status_mask = 0;
1010         if (termios->c_iflag & IGNPAR)
1011                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1012         if (termios->c_iflag & IGNBRK) {
1013                 up->port.ignore_status_mask |= UART_LSR_BI;
1014                 /*
1015                  * If we're ignoring parity and break indicators,
1016                  * ignore overruns too (for real raw support).
1017                  */
1018                 if (termios->c_iflag & IGNPAR)
1019                         up->port.ignore_status_mask |= UART_LSR_OE;
1020         }
1021
1022         /* Ignore all characters if CREAD is not set */
1023         if ((termios->c_cflag & CREAD) == 0)
1024                 up->port.ignore_status_mask |= UART_LSR_DR;
1025
1026         /*
1027          * CTS flow control flag and modem status interrupts, disable
1028          * MSI by default
1029          */
1030         up->ier &= ~UART_IER_MSI;
1031         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1032                 up->ier |= UART_IER_MSI;
1033
1034         serial_out(up, UART_IER, up->ier);
1035
1036         if (termios->c_cflag & CRTSCTS)
1037                 up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
1038         else
1039                 up->mcr &= ~UART_MCR_AFE;
1040
1041         serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1042         serial_out(up, UART_DLL, quot & 0xff);          /* LS of divisor */
1043         serial_out(up, UART_DLM, quot >> 8);            /* MS of divisor */
1044         serial_out(up, UART_LCR, cval);                 /* reset DLAB */
1045         serial_out(up, UART_MUL, mul);                  /* set MUL */
1046         serial_out(up, UART_PS, ps);                    /* set PS */
1047         up->lcr = cval;                                 /* Save LCR */
1048         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
1049         serial_out(up, UART_FCR, fcr);
1050         spin_unlock_irqrestore(&up->port.lock, flags);
1051 }
1052
1053 static void
1054 serial_hsu_pm(struct uart_port *port, unsigned int state,
1055               unsigned int oldstate)
1056 {
1057 }
1058
1059 static void serial_hsu_release_port(struct uart_port *port)
1060 {
1061 }
1062
1063 static int serial_hsu_request_port(struct uart_port *port)
1064 {
1065         return 0;
1066 }
1067
1068 static void serial_hsu_config_port(struct uart_port *port, int flags)
1069 {
1070         struct uart_hsu_port *up =
1071                 container_of(port, struct uart_hsu_port, port);
1072         up->port.type = PORT_MFD;
1073 }
1074
1075 static int
1076 serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser)
1077 {
1078         /* We don't want the core code to modify any port params */
1079         return -EINVAL;
1080 }
1081
1082 static const char *
1083 serial_hsu_type(struct uart_port *port)
1084 {
1085         struct uart_hsu_port *up =
1086                 container_of(port, struct uart_hsu_port, port);
1087         return up->name;
1088 }
1089
1090 /* Mainly for uart console use */
1091 static struct uart_hsu_port *serial_hsu_ports[3];
1092 static struct uart_driver serial_hsu_reg;
1093
1094 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1095
1096 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1097
1098 /* Wait for transmitter & holding register to empty */
1099 static inline void wait_for_xmitr(struct uart_hsu_port *up)
1100 {
1101         unsigned int status, tmout = 1000;
1102
1103         /* Wait up to 1ms for the character to be sent. */
1104         do {
1105                 status = serial_in(up, UART_LSR);
1106
1107                 if (status & UART_LSR_BI)
1108                         up->lsr_break_flag = UART_LSR_BI;
1109
1110                 if (--tmout == 0)
1111                         break;
1112                 udelay(1);
1113         } while (!(status & BOTH_EMPTY));
1114
1115         /* Wait up to 1s for flow control if necessary */
1116         if (up->port.flags & UPF_CONS_FLOW) {
1117                 tmout = 1000000;
1118                 while (--tmout &&
1119                        ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1120                         udelay(1);
1121         }
1122 }
1123
1124 static void serial_hsu_console_putchar(struct uart_port *port, int ch)
1125 {
1126         struct uart_hsu_port *up =
1127                 container_of(port, struct uart_hsu_port, port);
1128
1129         wait_for_xmitr(up);
1130         serial_out(up, UART_TX, ch);
1131 }
1132
1133 /*
1134  * Print a string to the serial port trying not to disturb
1135  * any possible real use of the port...
1136  *
1137  *      The console_lock must be held when we get here.
1138  */
1139 static void
1140 serial_hsu_console_write(struct console *co, const char *s, unsigned int count)
1141 {
1142         struct uart_hsu_port *up = serial_hsu_ports[co->index];
1143         unsigned long flags;
1144         unsigned int ier;
1145         int locked = 1;
1146
1147         local_irq_save(flags);
1148         if (up->port.sysrq)
1149                 locked = 0;
1150         else if (oops_in_progress) {
1151                 locked = spin_trylock(&up->port.lock);
1152         } else
1153                 spin_lock(&up->port.lock);
1154
1155         /* First save the IER then disable the interrupts */
1156         ier = serial_in(up, UART_IER);
1157         serial_out(up, UART_IER, 0);
1158
1159         uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
1160
1161         /*
1162          * Finally, wait for transmitter to become empty
1163          * and restore the IER
1164          */
1165         wait_for_xmitr(up);
1166         serial_out(up, UART_IER, ier);
1167
1168         if (locked)
1169                 spin_unlock(&up->port.lock);
1170         local_irq_restore(flags);
1171 }
1172
1173 static struct console serial_hsu_console;
1174
1175 static int __init
1176 serial_hsu_console_setup(struct console *co, char *options)
1177 {
1178         struct uart_hsu_port *up;
1179         int baud = 115200;
1180         int bits = 8;
1181         int parity = 'n';
1182         int flow = 'n';
1183         int ret;
1184
1185         if (co->index == -1 || co->index >= serial_hsu_reg.nr)
1186                 co->index = 0;
1187         up = serial_hsu_ports[co->index];
1188         if (!up)
1189                 return -ENODEV;
1190
1191         if (options)
1192                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1193
1194         ret = uart_set_options(&up->port, co, baud, parity, bits, flow);
1195
1196         return ret;
1197 }
1198
1199 static struct console serial_hsu_console = {
1200         .name           = "ttyMFD",
1201         .write          = serial_hsu_console_write,
1202         .device         = uart_console_device,
1203         .setup          = serial_hsu_console_setup,
1204         .flags          = CON_PRINTBUFFER,
1205         .index          = 2,
1206         .data           = &serial_hsu_reg,
1207 };
1208 #endif
1209
1210 struct uart_ops serial_hsu_pops = {
1211         .tx_empty       = serial_hsu_tx_empty,
1212         .set_mctrl      = serial_hsu_set_mctrl,
1213         .get_mctrl      = serial_hsu_get_mctrl,
1214         .stop_tx        = serial_hsu_stop_tx,
1215         .start_tx       = serial_hsu_start_tx,
1216         .stop_rx        = serial_hsu_stop_rx,
1217         .enable_ms      = serial_hsu_enable_ms,
1218         .break_ctl      = serial_hsu_break_ctl,
1219         .startup        = serial_hsu_startup,
1220         .shutdown       = serial_hsu_shutdown,
1221         .set_termios    = serial_hsu_set_termios,
1222         .pm             = serial_hsu_pm,
1223         .type           = serial_hsu_type,
1224         .release_port   = serial_hsu_release_port,
1225         .request_port   = serial_hsu_request_port,
1226         .config_port    = serial_hsu_config_port,
1227         .verify_port    = serial_hsu_verify_port,
1228 };
1229
1230 static struct uart_driver serial_hsu_reg = {
1231         .owner          = THIS_MODULE,
1232         .driver_name    = "MFD serial",
1233         .dev_name       = "ttyMFD",
1234         .major          = TTY_MAJOR,
1235         .minor          = 128,
1236         .nr             = 3,
1237 };
1238
1239 #ifdef CONFIG_PM
1240 static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state)
1241 {
1242         void *priv = pci_get_drvdata(pdev);
1243         struct uart_hsu_port *up;
1244
1245         /* Make sure this is not the internal dma controller */
1246         if (priv && (pdev->device != 0x081E)) {
1247                 up = priv;
1248                 uart_suspend_port(&serial_hsu_reg, &up->port);
1249         }
1250
1251         pci_save_state(pdev);
1252         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1253         return 0;
1254 }
1255
1256 static int serial_hsu_resume(struct pci_dev *pdev)
1257 {
1258         void *priv = pci_get_drvdata(pdev);
1259         struct uart_hsu_port *up;
1260         int ret;
1261
1262         pci_set_power_state(pdev, PCI_D0);
1263         pci_restore_state(pdev);
1264
1265         ret = pci_enable_device(pdev);
1266         if (ret)
1267                 dev_warn(&pdev->dev,
1268                         "HSU: can't re-enable device, try to continue\n");
1269
1270         if (priv && (pdev->device != 0x081E)) {
1271                 up = priv;
1272                 uart_resume_port(&serial_hsu_reg, &up->port);
1273         }
1274         return 0;
1275 }
1276 #else
1277 #define serial_hsu_suspend      NULL
1278 #define serial_hsu_resume       NULL
1279 #endif
1280
1281 /* temp global pointer before we settle down on using one or four PCI dev */
1282 static struct hsu_port *phsu;
1283
1284 static int serial_hsu_probe(struct pci_dev *pdev,
1285                                 const struct pci_device_id *ent)
1286 {
1287         struct uart_hsu_port *uport;
1288         int index, ret;
1289
1290         printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1291                 pdev->vendor, pdev->device);
1292
1293         switch (pdev->device) {
1294         case 0x081B:
1295                 index = 0;
1296                 break;
1297         case 0x081C:
1298                 index = 1;
1299                 break;
1300         case 0x081D:
1301                 index = 2;
1302                 break;
1303         case 0x081E:
1304                 /* internal DMA controller */
1305                 index = 3;
1306                 break;
1307         default:
1308                 dev_err(&pdev->dev, "HSU: out of index!");
1309                 return -ENODEV;
1310         }
1311
1312         ret = pci_enable_device(pdev);
1313         if (ret)
1314                 return ret;
1315
1316         if (index == 3) {
1317                 /* DMA controller */
1318                 ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu);
1319                 if (ret) {
1320                         dev_err(&pdev->dev, "can not get IRQ\n");
1321                         goto err_disable;
1322                 }
1323                 pci_set_drvdata(pdev, phsu);
1324         } else {
1325                 /* UART port 0~2 */
1326                 uport = &phsu->port[index];
1327                 uport->port.irq = pdev->irq;
1328                 uport->port.dev = &pdev->dev;
1329                 uport->dev = &pdev->dev;
1330
1331                 ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport);
1332                 if (ret) {
1333                         dev_err(&pdev->dev, "can not get IRQ\n");
1334                         goto err_disable;
1335                 }
1336                 uart_add_one_port(&serial_hsu_reg, &uport->port);
1337
1338 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1339                 if (index == 2) {
1340                         register_console(&serial_hsu_console);
1341                         uport->port.cons = &serial_hsu_console;
1342                 }
1343 #endif
1344                 pci_set_drvdata(pdev, uport);
1345         }
1346
1347         return 0;
1348
1349 err_disable:
1350         pci_disable_device(pdev);
1351         return ret;
1352 }
1353
1354 static void hsu_dma_rx_timeout(unsigned long data)
1355 {
1356         struct hsu_dma_chan *chan = (void *)data;
1357         struct uart_hsu_port *up = chan->uport;
1358         struct hsu_dma_buffer *dbuf = &up->rxbuf;
1359         int count = 0;
1360         unsigned long flags;
1361
1362         spin_lock_irqsave(&up->port.lock, flags);
1363
1364         count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
1365
1366         if (!count) {
1367                 mod_timer(&chan->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
1368                 goto exit;
1369         }
1370
1371         hsu_dma_rx(up, 0);
1372 exit:
1373         spin_unlock_irqrestore(&up->port.lock, flags);
1374 }
1375
1376 static void hsu_global_init(void)
1377 {
1378         struct hsu_port *hsu;
1379         struct uart_hsu_port *uport;
1380         struct hsu_dma_chan *dchan;
1381         int i, ret;
1382
1383         hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL);
1384         if (!hsu)
1385                 return;
1386
1387         /* Get basic io resource and map it */
1388         hsu->paddr = 0xffa28000;
1389         hsu->iolen = 0x1000;
1390
1391         if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global")))
1392                 pr_warning("HSU: error in request mem region\n");
1393
1394         hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen);
1395         if (!hsu->reg) {
1396                 pr_err("HSU: error in ioremap\n");
1397                 ret = -ENOMEM;
1398                 goto err_free_region;
1399         }
1400
1401         /* Initialise the 3 UART ports */
1402         uport = hsu->port;
1403         for (i = 0; i < 3; i++) {
1404                 uport->port.type = PORT_MFD;
1405                 uport->port.iotype = UPIO_MEM;
1406                 uport->port.mapbase = (resource_size_t)hsu->paddr
1407                                         + HSU_PORT_REG_OFFSET
1408                                         + i * HSU_PORT_REG_LENGTH;
1409                 uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET
1410                                         + i * HSU_PORT_REG_LENGTH;
1411
1412                 sprintf(uport->name, "hsu_port%d", i);
1413                 uport->port.fifosize = 64;
1414                 uport->port.ops = &serial_hsu_pops;
1415                 uport->port.line = i;
1416                 uport->port.flags = UPF_IOREMAP;
1417                 /* set the scalable maxim support rate to 2746800 bps */
1418                 uport->port.uartclk = 115200 * 24 * 16;
1419
1420                 uport->running = 0;
1421                 uport->txc = &hsu->chans[i * 2];
1422                 uport->rxc = &hsu->chans[i * 2 + 1];
1423
1424                 serial_hsu_ports[i] = uport;
1425                 uport->index = i;
1426                 uport++;
1427         }
1428
1429         /* Initialise 6 dma channels */
1430         dchan = hsu->chans;
1431         for (i = 0; i < 6; i++) {
1432                 dchan->id = i;
1433                 dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1434                 dchan->uport = &hsu->port[i/2];
1435                 dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
1436                                 i * HSU_DMA_CHANS_REG_LENGTH;
1437
1438                 /* Work around for RX */
1439                 if (dchan->dirt == DMA_FROM_DEVICE) {
1440                         init_timer(&dchan->rx_timer);
1441                         dchan->rx_timer.function = hsu_dma_rx_timeout;
1442                         dchan->rx_timer.data = (unsigned long)dchan;
1443                 }
1444                 dchan++;
1445         }
1446
1447         phsu = hsu;
1448         hsu_debugfs_init(hsu);
1449         return;
1450
1451 err_free_region:
1452         release_mem_region(hsu->paddr, hsu->iolen);
1453         kfree(hsu);
1454         return;
1455 }
1456
1457 static void serial_hsu_remove(struct pci_dev *pdev)
1458 {
1459         void *priv = pci_get_drvdata(pdev);
1460         struct uart_hsu_port *up;
1461
1462         if (!priv)
1463                 return;
1464
1465         /* For port 0/1/2, priv is the address of uart_hsu_port */
1466         if (pdev->device != 0x081E) {
1467                 up = priv;
1468                 uart_remove_one_port(&serial_hsu_reg, &up->port);
1469         }
1470
1471         pci_set_drvdata(pdev, NULL);
1472         free_irq(pdev->irq, priv);
1473         pci_disable_device(pdev);
1474 }
1475
1476 /* First 3 are UART ports, and the 4th is the DMA */
1477 static const struct pci_device_id pci_ids[] __devinitdata = {
1478         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) },
1479         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) },
1480         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) },
1481         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) },
1482         {},
1483 };
1484
1485 static struct pci_driver hsu_pci_driver = {
1486         .name =         "HSU serial",
1487         .id_table =     pci_ids,
1488         .probe =        serial_hsu_probe,
1489         .remove =       __devexit_p(serial_hsu_remove),
1490         .suspend =      serial_hsu_suspend,
1491         .resume =       serial_hsu_resume,
1492 };
1493
1494 static int __init hsu_pci_init(void)
1495 {
1496         int ret;
1497
1498         hsu_global_init();
1499
1500         ret = uart_register_driver(&serial_hsu_reg);
1501         if (ret)
1502                 return ret;
1503
1504         return pci_register_driver(&hsu_pci_driver);
1505 }
1506
1507 static void __exit hsu_pci_exit(void)
1508 {
1509         pci_unregister_driver(&hsu_pci_driver);
1510         uart_unregister_driver(&serial_hsu_reg);
1511
1512         hsu_debugfs_remove(phsu);
1513
1514         kfree(phsu);
1515 }
1516
1517 module_init(hsu_pci_init);
1518 module_exit(hsu_pci_exit);
1519
1520 MODULE_LICENSE("GPL v2");
1521 MODULE_ALIAS("platform:medfield-hsu");