2 * drivers/platform/tegra/tegra21_dvfs.c
4 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/string.h>
20 #include <linux/module.h>
21 #include <linux/clk.h>
22 #include <linux/kobject.h>
23 #include <linux/err.h>
24 #include <linux/tegra-fuse.h>
29 #include "tegra_cl_dvfs.h"
30 #include "tegra_core_sysfs_limits.h"
32 static bool tegra_dvfs_cpu_disabled;
33 static bool tegra_dvfs_core_disabled;
34 static bool tegra_dvfs_gpu_disabled;
39 /* FIXME: need tegra21 step */
40 #define VDD_SAFE_STEP 100
42 static int vdd_core_therm_trips_table[MAX_THERMAL_LIMITS] = { 20, };
43 static int vdd_core_therm_floors_table[MAX_THERMAL_LIMITS] = { 950, };
45 static struct tegra_cooling_device cpu_cdev = {
46 .cdev_type = "cpu_cold",
49 static struct tegra_cooling_device core_cdev = {
50 .cdev_type = "core_cold",
53 static struct dvfs_rail tegra21_dvfs_rail_vdd_cpu = {
55 .max_millivolts = 1400,
56 .min_millivolts = 800,
57 .step = VDD_SAFE_STEP,
59 .vmin_cdev = &cpu_cdev,
61 .step_uv = 10000, /* 10mV */
64 .bin_uV = 10000, /* 10mV */
68 static struct dvfs_rail tegra21_dvfs_rail_vdd_core = {
70 .max_millivolts = 1400,
71 .min_millivolts = 800,
72 .step = VDD_SAFE_STEP,
73 .vmin_cdev = &core_cdev,
76 /* TBD: fill in actual hw number */
77 static struct dvfs_rail tegra21_dvfs_rail_vdd_gpu = {
79 .max_millivolts = 1350,
80 .min_millivolts = 700,
81 .step = VDD_SAFE_STEP,
83 .step_uv = 10000, /* 10mV */
86 .bin_uV = 10000, /* 10mV */
90 static struct dvfs_rail *tegra21_dvfs_rails[] = {
91 &tegra21_dvfs_rail_vdd_cpu,
92 &tegra21_dvfs_rail_vdd_core,
93 &tegra21_dvfs_rail_vdd_gpu,
96 void __init tegra21x_vdd_cpu_align(int step_uv, int offset_uv)
98 tegra21_dvfs_rail_vdd_cpu.alignment.step_uv = step_uv;
99 tegra21_dvfs_rail_vdd_cpu.alignment.offset_uv = offset_uv;
102 /* CPU DVFS tables */
103 static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = {
109 .tune0_high_mv = 0x00f0409f,
111 .droop_rate_min = 1000000,
112 .min_millivolts = 800,
117 .voltage_scale = 1000,
119 /*f dfll: c0, c1, c2 pll: c0, c1, c2 */
120 {408000 , {2244479, -117955, 2292}, { 960000, 0, 0}},
121 {510000 , {2279779, -119575, 2292}, { 960000, 0, 0}},
122 {612000 , {2317504, -121185, 2292}, { 960000, 0, 0}},
123 {714000 , {2357653, -122795, 2292}, { 972000, 0, 0}},
124 {816000 , {2400228, -124415, 2292}, { 984000, 0, 0}},
125 {918000 , {2445228, -126025, 2292}, { 996000, 0, 0}},
126 {1020000, {2492653, -127635, 2292}, { 1020000, 0, 0}},
127 {1122000, {2542502, -129255, 2292}, { 1032000, 0, 0}},
128 {1224000, {2594777, -130865, 2292}, { 1056000, 0, 0}},
129 {1326000, {2649477, -132475, 2292}, { 1092000, 0, 0}},
130 {1428000, {2706601, -134095, 2292}, { 1116000, 0, 0}},
131 {1530000, {2766150, -135705, 2292}, { 1152000, 0, 0}},
132 {1632000, {2828125, -137315, 2292}, { 1188000, 0, 0}},
133 {1734000, {2892524, -138935, 2292}, { 1224000, 0, 0}},
134 {1836000, {2959348, -140545, 2292}, { 1260000, 0, 0}},
135 {1913000, {3028598, -142155, 2292}, { 1308000, 0, 0}},
136 {2015000, {3100272, -143775, 2292}, { 1356000, 0, 0}},
137 {2117000, {3174371, -145385, 2292}, { 1404000, 0, 0}},
138 { 0, { 0, 0, 0}, { 0, 0, 0}},
140 .vmin_trips_table = { 20, },
141 .therm_floors_table = { 1000, },
148 .tune0_high_mv = 0x00f0409f,
150 .droop_rate_min = 1000000,
151 .min_millivolts = 800,
156 .voltage_scale = 1000,
158 /*f dfll: c0, c1, c2 pll: c0, c1, c2 */
159 {408000 , {2244479, -117955, 2292}, { 912000 , 0, 0}},
160 {510000 , {2279779, -119575, 2292}, { 912000 , 0, 0}},
161 {612000 , {2317504, -121185, 2292}, { 924000 , 0, 0}},
162 {714000 , {2357653, -122795, 2292}, { 924000 , 0, 0}},
163 {816000 , {2400228, -124415, 2292}, { 936000 , 0, 0}},
164 {918000 , {2445228, -126025, 2292}, { 948000 , 0, 0}},
165 {1020000, {2492653, -127635, 2292}, { 960000 , 0, 0}},
166 {1122000, {2542502, -129255, 2292}, { 972000 , 0, 0}},
167 {1224000, {2594777, -130865, 2292}, { 996000 , 0, 0}},
168 {1326000, {2649477, -132475, 2292}, { 1020000 , 0, 0}},
169 {1428000, {2706601, -134095, 2292}, { 1044000 , 0, 0}},
170 {1530000, {2766150, -135705, 2292}, { 1068000 , 0, 0}},
171 {1632000, {2828125, -137315, 2292}, { 1104000 , 0, 0}},
172 {1734000, {2892524, -138935, 2292}, { 1140000 , 0, 0}},
173 {1836000, {2959348, -140545, 2292}, { 1176000 , 0, 0}},
174 {1913000, {3028598, -142155, 2292}, { 1224000 , 0, 0}},
175 {2015000, {3100272, -143775, 2292}, { 1260000 , 0, 0}},
176 {2117000, {3174371, -145385, 2292}, { 1308000 , 0, 0}},
177 {2219000, {3250895, -146995, 2292}, { 1356000 , 0, 0}},
178 {2321000, {3329844, -148615, 2292}, { 1404000 , 0, 0}},
179 { 0, { 0, 0, 0}, { 0, 0, 0}},
181 .vmin_trips_table = { 20, },
182 .therm_floors_table = { 1000, },
186 static int cpu_millivolts[MAX_DVFS_FREQS];
187 static int cpu_dfll_millivolts[MAX_DVFS_FREQS];
189 static struct dvfs cpu_dvfs = {
191 .millivolts = cpu_millivolts,
192 .dfll_millivolts = cpu_dfll_millivolts,
194 .dvfs_rail = &tegra21_dvfs_rail_vdd_cpu,
197 /* Core DVFS tables */
198 /* FIXME: real data */
199 static const int core_millivolts[MAX_DVFS_FREQS] = {
200 810, 860, 900, 1000, 1100};
202 #define CORE_DVFS(_clk_name, _speedo_id, _process_id, _auto, _mult, _freqs...) \
204 .clk_name = _clk_name, \
205 .speedo_id = _speedo_id, \
206 .process_id = _process_id, \
208 .freqs_mult = _mult, \
209 .millivolts = core_millivolts, \
210 .auto_dvfs = _auto, \
211 .dvfs_rail = &tegra21_dvfs_rail_vdd_core, \
214 static struct dvfs core_dvfs_table[] = {
215 /* Core voltages (mV): 810, 860, 900, 1000, 1100*/
216 /* Clock limits for internal blocks, PLLs */
217 CORE_DVFS("emc", -1, -1, 1, KHZ, 264000, 348000, 384000, 528000, 1599000),
219 CORE_DVFS("cpu_lp", -1, -1, 1, KHZ, 144000, 252000, 288000, 444000, 624000),
221 CORE_DVFS("sbus", -1, -1, 1, KHZ, 81600, 102000, 136000, 204000, 204000),
223 CORE_DVFS("vic03", -1, -1, 1, KHZ, 120000, 144000, 168000, 216000, 372000),
224 CORE_DVFS("tsec", -1, -1, 1, KHZ, 120000, 144000, 168000, 216000, 372000),
225 CORE_DVFS("tsecb", -1, -1, 1, KHZ, 120000, 144000, 168000, 216000, 372000),
227 CORE_DVFS("msenc", -1, -1, 1, KHZ, 72000, 84000, 102000, 180000, 252000),
228 CORE_DVFS("nvdec", -1, -1, 1, KHZ, 72000, 84000, 102000, 180000, 252000),
229 CORE_DVFS("nvjpg", -1, -1, 1, KHZ, 72000, 84000, 102000, 180000, 252000),
230 CORE_DVFS("se", -1, -1, 1, KHZ, 72000, 84000, 102000, 180000, 252000),
231 CORE_DVFS("vde", -1, -1, 1, KHZ, 72000, 84000, 102000, 180000, 252000),
233 CORE_DVFS("host1x", -1, -1, 1, KHZ, 81600, 102000, 136000, 163000, 204000),
235 CORE_DVFS("vi", -1, -1, 1, KHZ, 120000, 156000, 182000, 312000, 444000),
236 CORE_DVFS("isp", -1, -1, 1, KHZ, 120000, 156000, 182000, 312000, 444000),
238 #ifdef CONFIG_TEGRA_DUAL_CBUS
239 CORE_DVFS("c2bus", -1, -1, 1, KHZ, 72000, 84000, 102000, 180000, 252000),
240 CORE_DVFS("c3bus", -1, -1, 1, KHZ, 120000, 144000, 168000, 216000, 372000),
242 CORE_DVFS("cbus", -1, -1, 1, KHZ, 120000, 144000, 168000, 216000, 372000),
244 CORE_DVFS("c4bus", -1, -1, 1, KHZ, 120000, 156000, 182000, 312000, 444000),
246 CORE_DVFS("pll_m", -1, -1, 1, KHZ, 800000, 800000, 1066000, 1066000, 1599000),
247 CORE_DVFS("pll_c", -1, -1, 1, KHZ, 800000, 800000, 1066000, 1066000, 1066000),
248 CORE_DVFS("pll_c2", -1, -1, 1, KHZ, 800000, 800000, 1066000, 1066000, 1066000),
249 CORE_DVFS("pll_c3", -1, -1, 1, KHZ, 800000, 800000, 1066000, 1066000, 1066000),
251 /* Core voltages (mV): 810, 860, 900, 990, 1080*/
252 /* Clock limits for I/O peripherals */
253 CORE_DVFS("sbc1", -1, -1, 1, KHZ, 24000, 24000, 48000, 48000, 48000),
254 CORE_DVFS("sbc2", -1, -1, 1, KHZ, 24000, 24000, 48000, 48000, 48000),
255 CORE_DVFS("sbc3", -1, -1, 1, KHZ, 24000, 24000, 48000, 48000, 48000),
256 CORE_DVFS("sbc4", -1, -1, 1, KHZ, 24000, 24000, 48000, 48000, 48000),
257 CORE_DVFS("sbc5", -1, -1, 1, KHZ, 24000, 24000, 48000, 48000, 48000),
258 CORE_DVFS("sbc6", -1, -1, 1, KHZ, 24000, 24000, 48000, 48000, 48000),
260 CORE_DVFS("sdmmc1", -1, -1, 1, KHZ, 102000, 102000, 163200, 163200, 163200),
261 CORE_DVFS("sdmmc3", -1, -1, 1, KHZ, 102000, 102000, 163200, 163200, 163200),
262 CORE_DVFS("sdmmc4", -1, -1, 1, KHZ, 102000, 102000, 178200, 178200, 178200),
264 CORE_DVFS("hdmi", -1, -1, 1, KHZ, 99000, 118800, 148500, 198000, 198000),
265 CORE_DVFS("pciex", -1, -1, 1, KHZ, 250000, 250000, 250000, 500000, 500000),
268 * The clock rate for the display controllers that determines the
269 * necessary core voltage depends on a divider that is internal
270 * to the display block. Disable auto-dvfs on the display clocks,
271 * and let the display driver call tegra_dvfs_set_rate manually
273 CORE_DVFS("disp1", -1, -1, 0, KHZ, 108000, 120000, 144000, 192000, 240000),
274 CORE_DVFS("disp2", -1, -1, 0, KHZ, 108000, 120000, 144000, 192000, 240000),
277 CORE_DVFS("xusb_falcon_src", -1, -1, 1, KHZ, 204000, 204000, 204000, 336000, 336000),
278 CORE_DVFS("xusb_host_src", -1, -1, 1, KHZ, 58300, 58300, 58300, 112000, 112000),
279 CORE_DVFS("xusb_dev_src", -1, -1, 1, KHZ, 58300, 58300, 58300, 112000, 112000),
280 CORE_DVFS("xusb_ss_src", -1, -1, 1, KHZ, 60000, 60000, 60000, 120000, 120000),
281 CORE_DVFS("xusb_fs_src", -1, -1, 1, KHZ, 0, 48000, 48000, 48000, 48000),
282 CORE_DVFS("xusb_hs_src", -1, -1, 1, KHZ, 0, 60000, 60000, 60000, 60000),
285 /* TBD: fill in actual hw numbers */
286 static struct gpu_cvb_dvfs gpu_cvb_dvfs_table[] = {
293 .voltage_scale = 1000,
295 /*f dfll pll: c0, c1, c2 */
296 { 204000, { }, { 810000, 0, 0}, },
297 { 264000, { }, { 860000, 0, 0}, },
298 { 351000, { }, { 900000, 0, 0}, },
299 { 492000, { }, { 990000, 0, 0}, },
300 { 624000, { }, { 1080000, 0, 0}, },
301 { 0, { }, { 0, 0, 0}, },
306 static int gpu_millivolts[MAX_DVFS_FREQS];
307 static struct dvfs gpu_dvfs = {
309 .millivolts = gpu_millivolts,
311 .dvfs_rail = &tegra21_dvfs_rail_vdd_gpu,
314 int read_gpu_dvfs_table(int **millivolts, unsigned long **freqs)
316 *millivolts = gpu_dvfs.millivolts;
317 *freqs = gpu_dvfs.freqs;
321 EXPORT_SYMBOL(read_gpu_dvfs_table);
323 int tegra_dvfs_disable_core_set(const char *arg, const struct kernel_param *kp)
327 ret = param_set_bool(arg, kp);
331 if (tegra_dvfs_core_disabled)
332 tegra_dvfs_rail_disable(&tegra21_dvfs_rail_vdd_core);
334 tegra_dvfs_rail_enable(&tegra21_dvfs_rail_vdd_core);
339 int tegra_dvfs_disable_cpu_set(const char *arg, const struct kernel_param *kp)
343 ret = param_set_bool(arg, kp);
347 if (tegra_dvfs_cpu_disabled)
348 tegra_dvfs_rail_disable(&tegra21_dvfs_rail_vdd_cpu);
350 tegra_dvfs_rail_enable(&tegra21_dvfs_rail_vdd_cpu);
355 int tegra_dvfs_disable_gpu_set(const char *arg, const struct kernel_param *kp)
359 ret = param_set_bool(arg, kp);
363 if (tegra_dvfs_gpu_disabled)
364 tegra_dvfs_rail_disable(&tegra21_dvfs_rail_vdd_gpu);
366 tegra_dvfs_rail_enable(&tegra21_dvfs_rail_vdd_gpu);
371 int tegra_dvfs_disable_get(char *buffer, const struct kernel_param *kp)
373 return param_get_bool(buffer, kp);
376 static struct kernel_param_ops tegra_dvfs_disable_core_ops = {
377 .set = tegra_dvfs_disable_core_set,
378 .get = tegra_dvfs_disable_get,
381 static struct kernel_param_ops tegra_dvfs_disable_cpu_ops = {
382 .set = tegra_dvfs_disable_cpu_set,
383 .get = tegra_dvfs_disable_get,
386 static struct kernel_param_ops tegra_dvfs_disable_gpu_ops = {
387 .set = tegra_dvfs_disable_gpu_set,
388 .get = tegra_dvfs_disable_get,
391 module_param_cb(disable_core, &tegra_dvfs_disable_core_ops,
392 &tegra_dvfs_core_disabled, 0644);
393 module_param_cb(disable_cpu, &tegra_dvfs_disable_cpu_ops,
394 &tegra_dvfs_cpu_disabled, 0644);
395 module_param_cb(disable_gpu, &tegra_dvfs_disable_gpu_ops,
396 &tegra_dvfs_gpu_disabled, 0644);
399 * Install rail thermal profile provided:
400 * - voltage floors are descending with temperature increasing
401 * - and the lowest floor is above rail minimum voltage in pll and
402 * in dfll mode (if applicable)
404 static void __init init_rail_thermal_profile(
405 int *therm_trips_table, int *therm_floors_table,
406 struct dvfs_rail *rail, struct dvfs_dfll_data *d)
410 for (i = 0; i < MAX_THERMAL_LIMITS - 1; i++) {
411 if (!therm_floors_table[i+1])
414 if ((therm_trips_table[i] >= therm_trips_table[i+1]) ||
415 (therm_floors_table[i] < therm_floors_table[i+1])) {
416 WARN(1, "%s: invalid thermal floors\n", rail->reg_id);
421 min_mv = max(rail->min_millivolts, d ? d->min_millivolts : 0);
422 if (therm_floors_table[i] < min_mv) {
423 WARN(1, "%s: thermal floor below Vmin\n", rail->reg_id);
427 /* Install validated thermal floors */
428 rail->therm_mv_floors = therm_floors_table;
429 rail->therm_mv_floors_num = i + 1;
431 /* Setup trip-points, use the same trips in dfll mode (if applicable) */
432 if (rail->vmin_cdev) {
433 rail->vmin_cdev->trip_temperatures_num = i + 1;
434 rail->vmin_cdev->trip_temperatures = therm_trips_table;
438 static bool __init can_update_max_rate(struct clk *c, struct dvfs *d)
440 /* Don't update manual dvfs clocks */
445 * Don't update EMC shared bus, since EMC dvfs is board dependent: max
446 * rate and EMC scaling frequencies are determined by tegra BCT (flashed
447 * together with the image) and board specific EMC DFS table; we will
448 * check the scaling ladder against nominal core voltage when the table
449 * is loaded (and if on particular board the table is not loaded, EMC
450 * scaling is disabled).
452 if (c->ops->shared_bus_update && (c->flags & PERIPH_EMC_ENB))
456 * Don't update shared cbus, and don't propagate common cbus dvfs
457 * limit down to shared users, but set maximum rate for each user
458 * equal to the respective client limit.
460 if (c->ops->shared_bus_update && (c->flags & PERIPH_ON_CBUS)) {
465 user, &c->shared_bus_list, u.shared_bus_user.node) {
466 if (user->u.shared_bus_user.client) {
467 rate = user->u.shared_bus_user.client->max_rate;
468 user->max_rate = rate;
469 user->u.shared_bus_user.rate = rate;
475 /* Other, than EMC and cbus, auto-dvfs clocks can be updated */
479 static void __init init_dvfs_one(struct dvfs *d, int max_freq_index)
482 struct clk *c = tegra_get_clock_by_name(d->clk_name);
485 pr_debug("tegra21_dvfs: no clock found for %s\n",
490 /* Update max rate for auto-dvfs clocks, with shared bus exceptions */
491 if (can_update_max_rate(c, d)) {
492 BUG_ON(!d->freqs[max_freq_index]);
494 c, d->freqs[max_freq_index] * d->freqs_mult);
496 d->max_millivolts = d->dvfs_rail->nominal_millivolts;
498 ret = tegra_enable_dvfs_on_clk(c, d);
500 pr_err("tegra21_dvfs: failed to enable dvfs on %s\n", c->name);
503 static bool __init match_dvfs_one(const char *name,
504 int dvfs_speedo_id, int dvfs_process_id,
505 int speedo_id, int process_id)
507 if ((dvfs_process_id != -1 && dvfs_process_id != process_id) ||
508 (dvfs_speedo_id != -1 && dvfs_speedo_id != speedo_id)) {
509 pr_debug("tegra21_dvfs: rejected %s speedo %d, process %d\n",
510 name, dvfs_speedo_id, dvfs_process_id);
516 /* cvb_mv = ((c2 * speedo / s_scale + c1) * speedo / s_scale + c0) / v_scale */
517 static inline int get_cvb_voltage(int speedo, int s_scale,
518 struct cvb_dvfs_parameters *cvb)
520 /* apply only speedo scale: output mv = cvb_mv * v_scale */
522 mv = DIV_ROUND_CLOSEST(cvb->c2 * speedo, s_scale);
523 mv = DIV_ROUND_CLOSEST((mv + cvb->c1) * speedo, s_scale) + cvb->c0;
527 static int round_cvb_voltage(int mv, int v_scale, struct rail_alignment *align)
529 /* combined: apply voltage scale and round to cvb alignment step */
531 int step = (align->step_uv ? : 1000) * v_scale;
532 int offset = align->offset_uv * v_scale;
534 uv = max(mv * 1000, offset) - offset;
535 uv = DIV_ROUND_UP(uv, step) * align->step_uv + align->offset_uv;
539 static int __init set_cpu_dvfs_data(
540 struct cpu_cvb_dvfs *d, struct dvfs *cpu_dvfs, int *max_freq_index)
542 int i, j, mv, dfll_mv, min_dfll_mv;
543 unsigned long fmax_at_vmin = 0;
544 unsigned long fmax_pll_mode = 0;
545 unsigned long fmin_use_dfll = 0;
546 struct cvb_dvfs_table *table = NULL;
547 int speedo = tegra_cpu_speedo_value();
548 struct rail_alignment *align = &tegra21_dvfs_rail_vdd_cpu.alignment;
550 min_dfll_mv = d->dfll_tune_data.min_millivolts;
551 min_dfll_mv = round_cvb_voltage(min_dfll_mv * 1000, 1000, align);
552 d->max_mv = round_cvb_voltage(d->max_mv * 1000, 1000, align);
553 BUG_ON(min_dfll_mv < tegra21_dvfs_rail_vdd_cpu.min_millivolts);
556 * Use CVB table to fill in CPU dvfs frequencies and voltages. Each
557 * CVB entry specifies CPU frequency and CVB coefficients to calculate
558 * the respective voltage when either DFLL or PLL is used as CPU clock
561 * Minimum voltage limit is applied only to DFLL source. For PLL source
562 * voltage can go as low as table specifies. Maximum voltage limit is
563 * applied to both sources, but differently: directly clip voltage for
564 * DFLL, and limit maximum frequency for PLL.
566 for (i = 0, j = 0; i < MAX_DVFS_FREQS; i++) {
567 table = &d->cvb_table[i];
571 dfll_mv = get_cvb_voltage(
572 speedo, d->speedo_scale, &table->cvb_dfll_param);
573 dfll_mv = round_cvb_voltage(dfll_mv, d->voltage_scale, align);
575 mv = get_cvb_voltage(
576 speedo, d->speedo_scale, &table->cvb_pll_param);
577 mv = round_cvb_voltage(mv, d->voltage_scale, align);
580 * Check maximum frequency at minimum voltage for dfll source;
581 * round down unless all table entries are above Vmin, then use
582 * the 1st entry as is.
584 dfll_mv = max(dfll_mv, min_dfll_mv);
585 if (dfll_mv > min_dfll_mv) {
587 fmax_at_vmin = table->freq;
589 fmax_at_vmin = cpu_dvfs->freqs[j - 1];
592 /* Clip maximum frequency at maximum voltage for pll source */
593 if (mv > d->max_mv) {
595 break; /* 1st entry already above Vmax */
597 fmax_pll_mode = cpu_dvfs->freqs[j - 1];
600 /* Minimum rate with pll source voltage above dfll Vmin */
601 if ((mv >= min_dfll_mv) && (!fmin_use_dfll))
602 fmin_use_dfll = table->freq;
604 /* fill in dvfs tables */
605 cpu_dvfs->freqs[j] = table->freq;
606 cpu_dfll_millivolts[j] = min(dfll_mv, d->max_mv);
607 cpu_millivolts[j] = mv;
611 * "Round-up" frequency list cut-off (keep first entry that
612 * exceeds max voltage - the voltage limit will be enforced
613 * anyway, so when requested this frequency dfll will settle
614 * at whatever high frequency it can on the particular chip)
616 if (dfll_mv > d->max_mv)
620 /* Table must not be empty, must have at least one entry above Vmin */
621 if (!i || !j || !fmax_at_vmin) {
622 pr_err("tegra21_dvfs: invalid cpu dvfs table\n");
626 /* In the dfll operating range dfll voltage at any rate should be
627 better (below) than pll voltage */
628 if (!fmin_use_dfll || (fmin_use_dfll > fmax_at_vmin)) {
629 WARN(1, "tegra21_dvfs: pll voltage is below dfll in the dfll"
630 " operating range\n");
631 fmin_use_dfll = fmax_at_vmin;
634 /* dvfs tables are successfully populated - fill in the rest */
635 cpu_dvfs->speedo_id = d->speedo_id;
636 cpu_dvfs->process_id = d->process_id;
637 cpu_dvfs->freqs_mult = d->freqs_mult;
638 cpu_dvfs->dvfs_rail->nominal_millivolts = min(d->max_mv,
639 max(cpu_millivolts[j - 1], cpu_dfll_millivolts[j - 1]));
640 *max_freq_index = j - 1;
642 cpu_dvfs->dfll_data = d->dfll_tune_data;
643 cpu_dvfs->dfll_data.max_rate_boost = fmax_pll_mode ?
644 (cpu_dvfs->freqs[j - 1] - fmax_pll_mode) * d->freqs_mult : 0;
645 cpu_dvfs->dfll_data.out_rate_min = fmax_at_vmin * d->freqs_mult;
646 cpu_dvfs->dfll_data.use_dfll_rate_min = fmin_use_dfll * d->freqs_mult;
647 cpu_dvfs->dfll_data.min_millivolts = min_dfll_mv;
652 static int __init set_gpu_dvfs_data(
653 struct gpu_cvb_dvfs *d, struct dvfs *gpu_dvfs, int *max_freq_index)
656 struct cvb_dvfs_table *table = NULL;
657 int speedo = tegra_gpu_speedo_value();
658 struct rail_alignment *align = &tegra21_dvfs_rail_vdd_gpu.alignment;
660 d->max_mv = round_cvb_voltage(d->max_mv * 1000, 1000, align);
663 * Use CVB table to fill in gpu dvfs frequencies and voltages. Each
664 * CVB entry specifies gpu frequency and CVB coefficients to calculate
665 * the respective voltage.
667 for (i = 0, j = 0; i < MAX_DVFS_FREQS; i++) {
668 table = &d->cvb_table[i];
672 mv = get_cvb_voltage(
673 speedo, d->speedo_scale, &table->cvb_pll_param);
674 mv = round_cvb_voltage(mv, d->voltage_scale, align);
679 /* fill in gpu dvfs tables */
680 if (!j || (mv > gpu_millivolts[j - 1])) {
681 gpu_millivolts[j] = mv;
682 gpu_dvfs->freqs[j] = table->freq;
685 gpu_dvfs->freqs[j - 1] = table->freq;
688 /* Table must not be empty, must have at least one entry in range */
689 if (!i || !j || (gpu_millivolts[j - 1] <
690 tegra21_dvfs_rail_vdd_gpu.min_millivolts)) {
691 pr_err("tegra14_dvfs: invalid gpu dvfs table\n");
695 /* dvfs tables are successfully populated - fill in the gpu dvfs */
696 gpu_dvfs->speedo_id = d->speedo_id;
697 gpu_dvfs->process_id = d->process_id;
698 gpu_dvfs->freqs_mult = d->freqs_mult;
699 gpu_dvfs->dvfs_rail->nominal_millivolts =
700 min(d->max_mv, gpu_millivolts[j - 1]);
702 *max_freq_index = j - 1;
706 static int __init get_core_nominal_mv_index(int speedo_id)
709 int mv = tegra_core_speedo_mv();
710 int core_edp_voltage = get_core_edp();
713 * Start with nominal level for the chips with this speedo_id. Then,
714 * make sure core nominal voltage is below edp limit for the board
715 * (if edp limit is set).
717 if (!core_edp_voltage)
718 core_edp_voltage = 1100; /* default 1.1V EDP limit */
720 mv = min(mv, core_edp_voltage);
722 /* Round nominal level down to the nearest core scaling step */
723 for (i = 0; i < MAX_DVFS_FREQS; i++) {
724 if ((core_millivolts[i] == 0) || (mv < core_millivolts[i]))
729 pr_err("tegra21_dvfs: unable to adjust core dvfs table to"
730 " nominal voltage %d\n", mv);
736 int tegra_cpu_dvfs_alter(int edp_thermal_index, const cpumask_t *cpus,
737 bool before_clk_update, int cpu_event)
739 /* empty definition for tegra21 */
743 void __init tegra21x_init_dvfs(void)
745 int cpu_speedo_id = tegra_cpu_speedo_id();
746 int cpu_process_id = tegra_cpu_process_id();
747 int soc_speedo_id = tegra_soc_speedo_id();
748 int core_process_id = tegra_core_process_id();
749 int gpu_speedo_id = tegra_gpu_speedo_id();
750 int gpu_process_id = tegra_gpu_process_id();
753 int core_nominal_mv_index;
754 int gpu_max_freq_index = 0;
755 int cpu_max_freq_index = 0;
757 #ifndef CONFIG_TEGRA_CORE_DVFS
758 tegra_dvfs_core_disabled = true;
760 #ifndef CONFIG_TEGRA_CPU_DVFS
761 tegra_dvfs_cpu_disabled = true;
763 #ifndef CONFIG_TEGRA_GPU_DVFS
764 tegra_dvfs_gpu_disabled = true;
768 * Find nominal voltages for core (1st) and cpu rails before rail
769 * init. Nominal voltage index in core scaling ladder can also be
770 * used to determine max dvfs frequencies for all core clocks. In
771 * case of error disable core scaling and set index to 0, so that
772 * core clocks would not exceed rates allowed at minimum voltage.
774 core_nominal_mv_index = get_core_nominal_mv_index(soc_speedo_id);
775 if (core_nominal_mv_index < 0) {
776 tegra21_dvfs_rail_vdd_core.disabled = true;
777 tegra_dvfs_core_disabled = true;
778 core_nominal_mv_index = 0;
780 tegra21_dvfs_rail_vdd_core.nominal_millivolts =
781 core_millivolts[core_nominal_mv_index];
784 * Setup cpu dvfs and dfll tables from cvb data, determine nominal
785 * voltage for cpu rail, and cpu maximum frequency. Note that entire
786 * frequency range is guaranteed only when dfll is used as cpu clock
787 * source. Reaching maximum frequency with pll as cpu clock source
788 * may not be possible within nominal voltage range (dvfs mechanism
789 * would automatically fail frequency request in this case, so that
790 * voltage limit is not violated). Error when cpu dvfs table can not
791 * be constructed must never happen.
793 for (ret = 0, i = 0; i < ARRAY_SIZE(cpu_cvb_dvfs_table); i++) {
794 struct cpu_cvb_dvfs *d = &cpu_cvb_dvfs_table[i];
795 if (match_dvfs_one("cpu cvb", d->speedo_id, d->process_id,
796 cpu_speedo_id, cpu_process_id)) {
797 ret = set_cpu_dvfs_data(
798 d, &cpu_dvfs, &cpu_max_freq_index);
802 BUG_ON((i == ARRAY_SIZE(cpu_cvb_dvfs_table)) || ret);
805 * Setup gpu dvfs tables from cvb data, determine nominal voltage for
806 * gpu rail, and gpu maximum frequency. Error when gpu dvfs table can
807 * not be constructed must never happen.
809 for (ret = 0, i = 0; i < ARRAY_SIZE(gpu_cvb_dvfs_table); i++) {
810 struct gpu_cvb_dvfs *d = &gpu_cvb_dvfs_table[i];
811 if (match_dvfs_one("gpu cvb", d->speedo_id, d->process_id,
812 gpu_speedo_id, gpu_process_id)) {
813 ret = set_gpu_dvfs_data(
814 d, &gpu_dvfs, &gpu_max_freq_index);
818 BUG_ON((i == ARRAY_SIZE(gpu_cvb_dvfs_table)) || ret);
820 /* Init thermal floors */
821 /* FIXME: Uncomment when proper values are available later */
822 /* init_rail_thermal_profile(cpu_cvb_dvfs_table[i].therm_trips_table,
823 cpu_cvb_dvfs_table[i].therm_floors_table,
824 &tegra21_dvfs_rail_vdd_cpu, &cpu_dvfs.dfll_data);
825 init_rail_thermal_profile(vdd_core_therm_trips_table,
826 vdd_core_therm_floors_table, &tegra21_dvfs_rail_vdd_core, NULL);*/
828 /* Init rail structures and dependencies */
829 tegra_dvfs_init_rails(tegra21_dvfs_rails,
830 ARRAY_SIZE(tegra21_dvfs_rails));
832 /* Search core dvfs table for speedo/process matching entries and
833 initialize dvfs-ed clocks */
834 if (!tegra_platform_is_linsim()) {
835 for (i = 0; i < ARRAY_SIZE(core_dvfs_table); i++) {
836 struct dvfs *d = &core_dvfs_table[i];
837 if (!match_dvfs_one(d->clk_name, d->speedo_id,
838 d->process_id, soc_speedo_id, core_process_id))
840 init_dvfs_one(d, core_nominal_mv_index);
844 /* Initialize matching gpu dvfs entry already found when nominal
845 voltage was determined */
846 init_dvfs_one(&gpu_dvfs, gpu_max_freq_index);
848 /* Initialize matching cpu dvfs entry already found when nominal
849 voltage was determined */
850 init_dvfs_one(&cpu_dvfs, cpu_max_freq_index);
852 /* Finally disable dvfs on rails if necessary */
853 if (tegra_dvfs_core_disabled)
854 tegra_dvfs_rail_disable(&tegra21_dvfs_rail_vdd_core);
855 if (tegra_dvfs_cpu_disabled)
856 tegra_dvfs_rail_disable(&tegra21_dvfs_rail_vdd_cpu);
857 if (tegra_dvfs_gpu_disabled)
858 tegra_dvfs_rail_disable(&tegra21_dvfs_rail_vdd_gpu);
860 pr_info("tegra dvfs: VDD_CPU nominal %dmV, scaling %s\n",
861 tegra21_dvfs_rail_vdd_cpu.nominal_millivolts,
862 tegra_dvfs_cpu_disabled ? "disabled" : "enabled");
863 pr_info("tegra dvfs: VDD_CORE nominal %dmV, scaling %s\n",
864 tegra21_dvfs_rail_vdd_core.nominal_millivolts,
865 tegra_dvfs_core_disabled ? "disabled" : "enabled");
866 pr_info("tegra dvfs: VDD_GPU nominal %dmV, scaling %s\n",
867 tegra21_dvfs_rail_vdd_gpu.nominal_millivolts,
868 tegra_dvfs_gpu_disabled ? "disabled" : "enabled");
871 int tegra_dvfs_rail_disable_prepare(struct dvfs_rail *rail)
876 int tegra_dvfs_rail_post_enable(struct dvfs_rail *rail)
881 /* Core voltage and bus cap object and tables */
882 static struct kobject *cap_kobj;
884 static struct core_dvfs_cap_table tegra21_core_cap_table[] = {
885 #ifdef CONFIG_TEGRA_DUAL_CBUS
886 { .cap_name = "cap.c2bus" },
887 { .cap_name = "cap.c3bus" },
889 { .cap_name = "cap.cbus" },
891 { .cap_name = "cap.sclk" },
892 { .cap_name = "cap.emc" },
896 * Keep sys file names the same for dual and single cbus configurations to
897 * avoid changes in user space GPU capping interface.
899 static struct core_bus_limit_table tegra21_bus_cap_table[] = {
900 #ifdef CONFIG_TEGRA_DUAL_CBUS
901 { .limit_clk_name = "cap.profile.c2bus",
902 .refcnt_attr = {.attr = {.name = "cbus_cap_state", .mode = 0644} },
903 .level_attr = {.attr = {.name = "cbus_cap_level", .mode = 0644} },
906 { .limit_clk_name = "cap.profile.cbus",
907 .refcnt_attr = {.attr = {.name = "cbus_cap_state", .mode = 0644} },
908 .level_attr = {.attr = {.name = "cbus_cap_level", .mode = 0644} },
913 static int __init tegra21_dvfs_init_core_cap(void)
916 const int hack_core_millivolts = 0;
918 cap_kobj = kobject_create_and_add("tegra_cap", kernel_kobj);
920 pr_err("tegra21_dvfs: failed to create sysfs cap object\n");
924 ret = tegra_init_shared_bus_cap(
925 tegra21_bus_cap_table, ARRAY_SIZE(tegra21_bus_cap_table),
928 pr_err("tegra21_dvfs: failed to init bus cap interface (%d)\n",
930 kobject_del(cap_kobj);
934 /* FIXME: skip core cap init b/c it's too slow on QT */
935 if (tegra_platform_is_qt())
936 ret = tegra_init_core_cap(
937 tegra21_core_cap_table, ARRAY_SIZE(tegra21_core_cap_table),
938 &hack_core_millivolts, 1, cap_kobj);
940 ret = tegra_init_core_cap(
941 tegra21_core_cap_table, ARRAY_SIZE(tegra21_core_cap_table),
942 core_millivolts, ARRAY_SIZE(core_millivolts), cap_kobj);
945 pr_err("tegra21_dvfs: failed to init core cap interface (%d)\n",
947 kobject_del(cap_kobj);
950 pr_info("tegra dvfs: tegra sysfs cap interface is initialized\n");
954 late_initcall(tegra21_dvfs_init_core_cap);