2da5478b38958744cb086196e6c18dd797e82895
[linux-3.10.git] / drivers / pinctrl / pinctrl-tegra124.c
1 /*
2  * Pinctrl data for the NVIDIA Tegra124 pinmux
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  */
15
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/tegra-pmc.h>
22
23 #include "mach/pinmux-defines.h"
24 #include "pinctrl-tegra.h"
25
26 /*
27  * Most pins affected by the pinmux can also be GPIOs. Define these first.
28  * These must match how the GPIO driver names/numbers its pins.
29  */
30 #define _GPIO(offset)                           (offset)
31
32 #define TEGRA_PIN_CLK_32K_OUT_PA0               _GPIO(0)
33 #define TEGRA_PIN_UART3_CTS_N_PA1               _GPIO(1)
34 #define TEGRA_PIN_DAP2_FS_PA2                   _GPIO(2)
35 #define TEGRA_PIN_DAP2_SCLK_PA3                 _GPIO(3)
36 #define TEGRA_PIN_DAP2_DIN_PA4                  _GPIO(4)
37 #define TEGRA_PIN_DAP2_DOUT_PA5                 _GPIO(5)
38 #define TEGRA_PIN_SDMMC3_CLK_PA6                _GPIO(6)
39 #define TEGRA_PIN_SDMMC3_CMD_PA7                _GPIO(7)
40 #define TEGRA_PIN_PB0                           _GPIO(8)
41 #define TEGRA_PIN_PB1                           _GPIO(9)
42 #define TEGRA_PIN_SDMMC3_DAT3_PB4               _GPIO(12)
43 #define TEGRA_PIN_SDMMC3_DAT2_PB5               _GPIO(13)
44 #define TEGRA_PIN_SDMMC3_DAT1_PB6               _GPIO(14)
45 #define TEGRA_PIN_SDMMC3_DAT0_PB7               _GPIO(15)
46 #define TEGRA_PIN_UART3_RTS_N_PC0               _GPIO(16)
47 #define TEGRA_PIN_UART2_TXD_PC2                 _GPIO(18)
48 #define TEGRA_PIN_UART2_RXD_PC3                 _GPIO(19)
49 #define TEGRA_PIN_GEN1_I2C_SCL_PC4              _GPIO(20)
50 #define TEGRA_PIN_GEN1_I2C_SDA_PC5              _GPIO(21)
51 #define TEGRA_PIN_PC7                           _GPIO(23)
52 #define TEGRA_PIN_PG0                           _GPIO(48)
53 #define TEGRA_PIN_PG1                           _GPIO(49)
54 #define TEGRA_PIN_PG2                           _GPIO(50)
55 #define TEGRA_PIN_PG3                           _GPIO(51)
56 #define TEGRA_PIN_PG4                           _GPIO(52)
57 #define TEGRA_PIN_PG5                           _GPIO(53)
58 #define TEGRA_PIN_PG6                           _GPIO(54)
59 #define TEGRA_PIN_PG7                           _GPIO(55)
60 #define TEGRA_PIN_PH0                           _GPIO(56)
61 #define TEGRA_PIN_PH1                           _GPIO(57)
62 #define TEGRA_PIN_PH2                           _GPIO(58)
63 #define TEGRA_PIN_PH3                           _GPIO(59)
64 #define TEGRA_PIN_PH4                           _GPIO(60)
65 #define TEGRA_PIN_PH5                           _GPIO(61)
66 #define TEGRA_PIN_PH6                           _GPIO(62)
67 #define TEGRA_PIN_PH7                           _GPIO(63)
68 #define TEGRA_PIN_PI0                           _GPIO(64)
69 #define TEGRA_PIN_PI1                           _GPIO(65)
70 #define TEGRA_PIN_PI2                           _GPIO(66)
71 #define TEGRA_PIN_PI3                           _GPIO(67)
72 #define TEGRA_PIN_PI4                           _GPIO(68)
73 #define TEGRA_PIN_PI5                           _GPIO(69)
74 #define TEGRA_PIN_PI6                           _GPIO(70)
75 #define TEGRA_PIN_PI7                           _GPIO(71)
76 #define TEGRA_PIN_PJ0                           _GPIO(72)
77 #define TEGRA_PIN_PJ2                           _GPIO(74)
78 #define TEGRA_PIN_UART2_CTS_N_PJ5               _GPIO(77)
79 #define TEGRA_PIN_UART2_RTS_N_PJ6               _GPIO(78)
80 #define TEGRA_PIN_PJ7                           _GPIO(79)
81 #define TEGRA_PIN_PK0                           _GPIO(80)
82 #define TEGRA_PIN_PK1                           _GPIO(81)
83 #define TEGRA_PIN_PK2                           _GPIO(82)
84 #define TEGRA_PIN_PK3                           _GPIO(83)
85 #define TEGRA_PIN_PK4                           _GPIO(84)
86 #define TEGRA_PIN_SPDIF_OUT_PK5                 _GPIO(85)
87 #define TEGRA_PIN_SPDIF_IN_PK6                  _GPIO(86)
88 #define TEGRA_PIN_PK7                           _GPIO(87)
89 #define TEGRA_PIN_DAP1_FS_PN0                   _GPIO(104)
90 #define TEGRA_PIN_DAP1_DIN_PN1                  _GPIO(105)
91 #define TEGRA_PIN_DAP1_DOUT_PN2                 _GPIO(106)
92 #define TEGRA_PIN_DAP1_SCLK_PN3                 _GPIO(107)
93 #define TEGRA_PIN_USB_VBUS_EN0_PN4              _GPIO(108)
94 #define TEGRA_PIN_USB_VBUS_EN1_PN5              _GPIO(109)
95 #define TEGRA_PIN_HDMI_INT_PN7                  _GPIO(111)
96 #define TEGRA_PIN_ULPI_DATA7_PO0                _GPIO(112)
97 #define TEGRA_PIN_ULPI_DATA0_PO1                _GPIO(113)
98 #define TEGRA_PIN_ULPI_DATA1_PO2                _GPIO(114)
99 #define TEGRA_PIN_ULPI_DATA2_PO3                _GPIO(115)
100 #define TEGRA_PIN_ULPI_DATA3_PO4                _GPIO(116)
101 #define TEGRA_PIN_ULPI_DATA4_PO5                _GPIO(117)
102 #define TEGRA_PIN_ULPI_DATA5_PO6                _GPIO(118)
103 #define TEGRA_PIN_ULPI_DATA6_PO7                _GPIO(119)
104 #define TEGRA_PIN_DAP3_FS_PP0                   _GPIO(120)
105 #define TEGRA_PIN_DAP3_DIN_PP1                  _GPIO(121)
106 #define TEGRA_PIN_DAP3_DOUT_PP2                 _GPIO(122)
107 #define TEGRA_PIN_DAP3_SCLK_PP3                 _GPIO(123)
108 #define TEGRA_PIN_DAP4_FS_PP4                   _GPIO(124)
109 #define TEGRA_PIN_DAP4_DIN_PP5                  _GPIO(125)
110 #define TEGRA_PIN_DAP4_DOUT_PP6                 _GPIO(126)
111 #define TEGRA_PIN_DAP4_SCLK_PP7                 _GPIO(127)
112 #define TEGRA_PIN_KB_COL0_PQ0                   _GPIO(128)
113 #define TEGRA_PIN_KB_COL1_PQ1                   _GPIO(129)
114 #define TEGRA_PIN_KB_COL2_PQ2                   _GPIO(130)
115 #define TEGRA_PIN_KB_COL3_PQ3                   _GPIO(131)
116 #define TEGRA_PIN_KB_COL4_PQ4                   _GPIO(132)
117 #define TEGRA_PIN_KB_COL5_PQ5                   _GPIO(133)
118 #define TEGRA_PIN_KB_COL6_PQ6                   _GPIO(134)
119 #define TEGRA_PIN_KB_COL7_PQ7                   _GPIO(135)
120 #define TEGRA_PIN_KB_ROW0_PR0                   _GPIO(136)
121 #define TEGRA_PIN_KB_ROW1_PR1                   _GPIO(137)
122 #define TEGRA_PIN_KB_ROW2_PR2                   _GPIO(138)
123 #define TEGRA_PIN_KB_ROW3_PR3                   _GPIO(139)
124 #define TEGRA_PIN_KB_ROW4_PR4                   _GPIO(140)
125 #define TEGRA_PIN_KB_ROW5_PR5                   _GPIO(141)
126 #define TEGRA_PIN_KB_ROW6_PR6                   _GPIO(142)
127 #define TEGRA_PIN_KB_ROW7_PR7                   _GPIO(143)
128 #define TEGRA_PIN_KB_ROW8_PS0                   _GPIO(144)
129 #define TEGRA_PIN_KB_ROW9_PS1                   _GPIO(145)
130 #define TEGRA_PIN_KB_ROW10_PS2                  _GPIO(146)
131 #define TEGRA_PIN_KB_ROW11_PS3                  _GPIO(147)
132 #define TEGRA_PIN_KB_ROW12_PS4                  _GPIO(148)
133 #define TEGRA_PIN_KB_ROW13_PS5                  _GPIO(149)
134 #define TEGRA_PIN_KB_ROW14_PS6                  _GPIO(150)
135 #define TEGRA_PIN_KB_ROW15_PS7                  _GPIO(151)
136 #define TEGRA_PIN_KB_ROW16_PT0                  _GPIO(152)
137 #define TEGRA_PIN_KB_ROW17_PT1                  _GPIO(153)
138 #define TEGRA_PIN_GEN2_I2C_SCL_PT5              _GPIO(157)
139 #define TEGRA_PIN_GEN2_I2C_SDA_PT6              _GPIO(158)
140 #define TEGRA_PIN_SDMMC4_CMD_PT7                _GPIO(159)
141 #define TEGRA_PIN_PU0                           _GPIO(160)
142 #define TEGRA_PIN_PU1                           _GPIO(161)
143 #define TEGRA_PIN_PU2                           _GPIO(162)
144 #define TEGRA_PIN_PU3                           _GPIO(163)
145 #define TEGRA_PIN_PU4                           _GPIO(164)
146 #define TEGRA_PIN_PU5                           _GPIO(165)
147 #define TEGRA_PIN_PU6                           _GPIO(166)
148 #define TEGRA_PIN_PV0                           _GPIO(168)
149 #define TEGRA_PIN_PV1                           _GPIO(169)
150 #define TEGRA_PIN_SDMMC3_CD_N_PV2               _GPIO(170)
151 #define TEGRA_PIN_SDMMC1_WP_N_PV3               _GPIO(171)
152 #define TEGRA_PIN_DDC_SCL_PV4                   _GPIO(172)
153 #define TEGRA_PIN_DDC_SDA_PV5                   _GPIO(173)
154 #define TEGRA_PIN_GPIO_W2_AUD_PW2               _GPIO(178)
155 #define TEGRA_PIN_GPIO_W3_AUD_PW3               _GPIO(179)
156 #define TEGRA_PIN_DAP_MCLK1_PW4                 _GPIO(180)
157 #define TEGRA_PIN_CLK2_OUT_PW5                  _GPIO(181)
158 #define TEGRA_PIN_UART3_TXD_PW6                 _GPIO(182)
159 #define TEGRA_PIN_UART3_RXD_PW7                 _GPIO(183)
160 #define TEGRA_PIN_DVFS_PWM_PX0                  _GPIO(184)
161 #define TEGRA_PIN_GPIO_X1_AUD_PX1               _GPIO(185)
162 #define TEGRA_PIN_DVFS_CLK_PX2                  _GPIO(186)
163 #define TEGRA_PIN_GPIO_X3_AUD_PX3               _GPIO(187)
164 #define TEGRA_PIN_GPIO_X4_AUD_PX4               _GPIO(188)
165 #define TEGRA_PIN_GPIO_X5_AUD_PX5               _GPIO(189)
166 #define TEGRA_PIN_GPIO_X6_AUD_PX6               _GPIO(190)
167 #define TEGRA_PIN_GPIO_X7_AUD_PX7               _GPIO(191)
168 #define TEGRA_PIN_ULPI_CLK_PY0                  _GPIO(192)
169 #define TEGRA_PIN_ULPI_DIR_PY1                  _GPIO(193)
170 #define TEGRA_PIN_ULPI_NXT_PY2                  _GPIO(194)
171 #define TEGRA_PIN_ULPI_STP_PY3                  _GPIO(195)
172 #define TEGRA_PIN_SDMMC1_DAT3_PY4               _GPIO(196)
173 #define TEGRA_PIN_SDMMC1_DAT2_PY5               _GPIO(197)
174 #define TEGRA_PIN_SDMMC1_DAT1_PY6               _GPIO(198)
175 #define TEGRA_PIN_SDMMC1_DAT0_PY7               _GPIO(199)
176 #define TEGRA_PIN_SDMMC1_CLK_PZ0                _GPIO(200)
177 #define TEGRA_PIN_SDMMC1_CMD_PZ1                _GPIO(201)
178 #define TEGRA_PIN_PWR_I2C_SCL_PZ6               _GPIO(206)
179 #define TEGRA_PIN_PWR_I2C_SDA_PZ7               _GPIO(207)
180 #define TEGRA_PIN_SDMMC4_DAT0_PAA0              _GPIO(208)
181 #define TEGRA_PIN_SDMMC4_DAT1_PAA1              _GPIO(209)
182 #define TEGRA_PIN_SDMMC4_DAT2_PAA2              _GPIO(210)
183 #define TEGRA_PIN_SDMMC4_DAT3_PAA3              _GPIO(211)
184 #define TEGRA_PIN_SDMMC4_DAT4_PAA4              _GPIO(212)
185 #define TEGRA_PIN_SDMMC4_DAT5_PAA5              _GPIO(213)
186 #define TEGRA_PIN_SDMMC4_DAT6_PAA6              _GPIO(214)
187 #define TEGRA_PIN_SDMMC4_DAT7_PAA7              _GPIO(215)
188 #define TEGRA_PIN_PBB0                          _GPIO(216)
189 #define TEGRA_PIN_CAM_I2C_SCL_PBB1              _GPIO(217)
190 #define TEGRA_PIN_CAM_I2C_SDA_PBB2              _GPIO(218)
191 #define TEGRA_PIN_PBB3                          _GPIO(219)
192 #define TEGRA_PIN_PBB4                          _GPIO(220)
193 #define TEGRA_PIN_PBB5                          _GPIO(221)
194 #define TEGRA_PIN_PBB6                          _GPIO(222)
195 #define TEGRA_PIN_PBB7                          _GPIO(223)
196 #define TEGRA_PIN_CAM_MCLK_PCC0                 _GPIO(224)
197 #define TEGRA_PIN_PCC1                          _GPIO(225)
198 #define TEGRA_PIN_PCC2                          _GPIO(226)
199 #define TEGRA_PIN_SDMMC4_CLK_PCC4               _GPIO(228)
200 #define TEGRA_PIN_CLK2_REQ_PCC5                 _GPIO(229)
201 #define TEGRA_PIN_PEX_L0_RST_N_PDD1             _GPIO(233)
202 #define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2          _GPIO(234)
203 #define TEGRA_PIN_PEX_WAKE_N_PDD3               _GPIO(235)
204 #define TEGRA_PIN_PEX_L1_RST_N_PDD5             _GPIO(237)
205 #define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6          _GPIO(238)
206 #define TEGRA_PIN_CLK3_OUT_PEE0                 _GPIO(240)
207 #define TEGRA_PIN_CLK3_REQ_PEE1                 _GPIO(241)
208 #define TEGRA_PIN_DAP_MCLK1_REQ_PEE2            _GPIO(242)
209 #define TEGRA_PIN_HDMI_CEC_PEE3                 _GPIO(243)
210 #define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4        _GPIO(244)
211 #define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5         _GPIO(245)
212 #define TEGRA_PIN_DP_HPD_PFF0                   _GPIO(248)
213 #define TEGRA_PIN_USB_VBUS_EN2_PFF1             _GPIO(249)
214 #define TEGRA_PIN_PFF2                          _GPIO(250)
215
216 /* All non-GPIO pins follow */
217 #define NUM_GPIOS       (TEGRA_PIN_PFF2 + 1)
218 #define _PIN(offset)    (NUM_GPIOS + (offset))
219
220 /* Non-GPIO pins */
221 #define TEGRA_PIN_CORE_PWR_REQ                  _PIN(0)
222 #define TEGRA_PIN_CPU_PWR_REQ                   _PIN(1)
223 #define TEGRA_PIN_PWR_INT_N                     _PIN(2)
224 #define TEGRA_PIN_GMI_CLK_LB                    _PIN(3)
225 #define TEGRA_PIN_RESET_OUT_N                   _PIN(4)
226 #define TEGRA_PIN_OWR                           _PIN(5)
227 #define TEGRA_PIN_CLK_32K_IN                    _PIN(6)
228 #define TEGRA_PIN_JTAG_RTCK                     _PIN(7)
229
230 static const struct pinctrl_pin_desc  tegra124_pins[] = {
231         PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
232         PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
233         PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
234         PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
235         PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
236         PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
237         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
238         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
239         PINCTRL_PIN(TEGRA_PIN_PB0, "PB0"),
240         PINCTRL_PIN(TEGRA_PIN_PB1, "PB1"),
241         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
242         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
243         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
244         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
245         PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
246         PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
247         PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
248         PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
249         PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
250         PINCTRL_PIN(TEGRA_PIN_PC7, "PC7"),
251         PINCTRL_PIN(TEGRA_PIN_PG0, "PG0"),
252         PINCTRL_PIN(TEGRA_PIN_PG1, "PG1"),
253         PINCTRL_PIN(TEGRA_PIN_PG2, "PG2"),
254         PINCTRL_PIN(TEGRA_PIN_PG3, "PG3"),
255         PINCTRL_PIN(TEGRA_PIN_PG4, "PG4"),
256         PINCTRL_PIN(TEGRA_PIN_PG5, "PG5"),
257         PINCTRL_PIN(TEGRA_PIN_PG6, "PG6"),
258         PINCTRL_PIN(TEGRA_PIN_PG7, "PG7"),
259         PINCTRL_PIN(TEGRA_PIN_PH0, "PH0"),
260         PINCTRL_PIN(TEGRA_PIN_PH1, "PH1"),
261         PINCTRL_PIN(TEGRA_PIN_PH2, "PH2"),
262         PINCTRL_PIN(TEGRA_PIN_PH3, "PH3"),
263         PINCTRL_PIN(TEGRA_PIN_PH4, "PH4"),
264         PINCTRL_PIN(TEGRA_PIN_PH5, "PH5"),
265         PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"),
266         PINCTRL_PIN(TEGRA_PIN_PH7, "PH7"),
267         PINCTRL_PIN(TEGRA_PIN_PI0, "PI0"),
268         PINCTRL_PIN(TEGRA_PIN_PI1, "PI1"),
269         PINCTRL_PIN(TEGRA_PIN_PI2, "PI2"),
270         PINCTRL_PIN(TEGRA_PIN_PI3, "PI3"),
271         PINCTRL_PIN(TEGRA_PIN_PI4, "PI4"),
272         PINCTRL_PIN(TEGRA_PIN_PI5, "PI5"),
273         PINCTRL_PIN(TEGRA_PIN_PI6, "PI6"),
274         PINCTRL_PIN(TEGRA_PIN_PI7, "PI7"),
275         PINCTRL_PIN(TEGRA_PIN_PJ0, "PJ0"),
276         PINCTRL_PIN(TEGRA_PIN_PJ2, "PJ2"),
277         PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
278         PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
279         PINCTRL_PIN(TEGRA_PIN_PJ7, "PJ7"),
280         PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"),
281         PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"),
282         PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"),
283         PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"),
284         PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"),
285         PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
286         PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
287         PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"),
288         PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
289         PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
290         PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
291         PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
292         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
293         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
294         PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
295         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
296         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
297         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
298         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
299         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
300         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
301         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
302         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
303         PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
304         PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
305         PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
306         PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
307         PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
308         PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
309         PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
310         PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
311         PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
312         PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
313         PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
314         PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
315         PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
316         PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
317         PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
318         PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
319         PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
320         PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
321         PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
322         PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
323         PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
324         PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
325         PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
326         PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
327         PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
328         PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
329         PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
330         PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW10 PS3"),
331         PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW10 PS4"),
332         PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW10 PS5"),
333         PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW10 PS6"),
334         PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW10 PS7"),
335         PINCTRL_PIN(TEGRA_PIN_KB_ROW16_PT0, "KB_ROW10 PT0"),
336         PINCTRL_PIN(TEGRA_PIN_KB_ROW17_PT1, "KB_ROW10 PT1"),
337         PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
338         PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
339         PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
340         PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
341         PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
342         PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
343         PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
344         PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
345         PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
346         PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
347         PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
348         PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
349         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
350         PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
351         PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
352         PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
353         PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
354         PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
355         PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
356         PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
357         PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
358         PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
359         PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
360         PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
361         PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
362         PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
363         PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
364         PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
365         PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
366         PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
367         PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
368         PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
369         PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
370         PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
371         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
372         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
373         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
374         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
375         PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
376         PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
377         PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
378         PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
379         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
380         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
381         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
382         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
383         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
384         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
385         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
386         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
387         PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
388         PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
389         PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
390         PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
391         PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
392         PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
393         PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
394         PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
395         PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
396         PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
397         PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
398         PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
399         PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
400         PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
401         PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
402         PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
403         PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
404         PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
405         PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
406         PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
407         PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_REQ_PEE2, "DAP_MCLK1_REQ PEE2"),
408         PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
409         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
410         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
411         PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
412         PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
413         PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
414         PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
415         PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
416         PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"),
417         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"),
418         PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"),
419         PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
420         PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
421         PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
422 };
423
424 static const unsigned clk_32k_out_pa0_pins[] = {
425         TEGRA_PIN_CLK_32K_OUT_PA0,
426 };
427
428 static const unsigned uart3_cts_n_pa1_pins[] = {
429         TEGRA_PIN_UART3_CTS_N_PA1,
430 };
431
432 static const unsigned dap2_fs_pa2_pins[] = {
433         TEGRA_PIN_DAP2_FS_PA2,
434 };
435
436 static const unsigned dap2_sclk_pa3_pins[] = {
437         TEGRA_PIN_DAP2_SCLK_PA3,
438 };
439
440 static const unsigned dap2_din_pa4_pins[] = {
441         TEGRA_PIN_DAP2_DIN_PA4,
442 };
443
444 static const unsigned dap2_dout_pa5_pins[] = {
445         TEGRA_PIN_DAP2_DOUT_PA5,
446 };
447
448 static const unsigned sdmmc3_clk_pa6_pins[] = {
449         TEGRA_PIN_SDMMC3_CLK_PA6,
450 };
451
452 static const unsigned sdmmc3_cmd_pa7_pins[] = {
453         TEGRA_PIN_SDMMC3_CMD_PA7,
454 };
455
456 static const unsigned pb0_pins[] = {
457         TEGRA_PIN_PB0,
458 };
459
460 static const unsigned pb1_pins[] = {
461         TEGRA_PIN_PB1,
462 };
463
464 static const unsigned sdmmc3_dat3_pb4_pins[] = {
465         TEGRA_PIN_SDMMC3_DAT3_PB4,
466 };
467
468 static const unsigned sdmmc3_dat2_pb5_pins[] = {
469         TEGRA_PIN_SDMMC3_DAT2_PB5,
470 };
471
472 static const unsigned sdmmc3_dat1_pb6_pins[] = {
473         TEGRA_PIN_SDMMC3_DAT1_PB6,
474 };
475
476 static const unsigned sdmmc3_dat0_pb7_pins[] = {
477         TEGRA_PIN_SDMMC3_DAT0_PB7,
478 };
479
480 static const unsigned uart3_rts_n_pc0_pins[] = {
481         TEGRA_PIN_UART3_RTS_N_PC0,
482 };
483
484 static const unsigned uart2_txd_pc2_pins[] = {
485         TEGRA_PIN_UART2_TXD_PC2,
486 };
487
488 static const unsigned uart2_rxd_pc3_pins[] = {
489         TEGRA_PIN_UART2_RXD_PC3,
490 };
491
492 static const unsigned gen1_i2c_scl_pc4_pins[] = {
493         TEGRA_PIN_GEN1_I2C_SCL_PC4,
494 };
495
496 static const unsigned gen1_i2c_sda_pc5_pins[] = {
497         TEGRA_PIN_GEN1_I2C_SDA_PC5,
498 };
499
500 static const unsigned pc7_pins[] = {
501         TEGRA_PIN_PC7,
502 };
503
504 static const unsigned pg0_pins[] = {
505         TEGRA_PIN_PG0,
506 };
507
508 static const unsigned pg1_pins[] = {
509         TEGRA_PIN_PG1,
510 };
511
512 static const unsigned pg2_pins[] = {
513         TEGRA_PIN_PG2,
514 };
515
516 static const unsigned pg3_pins[] = {
517         TEGRA_PIN_PG3,
518 };
519
520 static const unsigned pg4_pins[] = {
521         TEGRA_PIN_PG4,
522 };
523
524 static const unsigned pg5_pins[] = {
525         TEGRA_PIN_PG5,
526 };
527
528 static const unsigned pg6_pins[] = {
529         TEGRA_PIN_PG6,
530 };
531
532 static const unsigned pg7_pins[] = {
533         TEGRA_PIN_PG7,
534 };
535
536 static const unsigned ph0_pins[] = {
537         TEGRA_PIN_PH0,
538 };
539
540 static const unsigned ph1_pins[] = {
541         TEGRA_PIN_PH1,
542 };
543
544 static const unsigned ph2_pins[] = {
545         TEGRA_PIN_PH2,
546 };
547
548 static const unsigned ph3_pins[] = {
549         TEGRA_PIN_PH3,
550 };
551
552 static const unsigned ph4_pins[] = {
553         TEGRA_PIN_PH4,
554 };
555
556 static const unsigned ph5_pins[] = {
557         TEGRA_PIN_PH5,
558 };
559
560 static const unsigned ph6_pins[] = {
561         TEGRA_PIN_PH6,
562 };
563
564 static const unsigned ph7_pins[] = {
565         TEGRA_PIN_PH7,
566 };
567
568 static const unsigned pi0_pins[] = {
569         TEGRA_PIN_PI0,
570 };
571
572 static const unsigned pi1_pins[] = {
573         TEGRA_PIN_PI1,
574 };
575
576 static const unsigned pi2_pins[] = {
577         TEGRA_PIN_PI2,
578 };
579
580 static const unsigned pi3_pins[] = {
581         TEGRA_PIN_PI3,
582 };
583
584 static const unsigned pi4_pins[] = {
585         TEGRA_PIN_PI4,
586 };
587
588 static const unsigned pi5_pins[] = {
589         TEGRA_PIN_PI5,
590 };
591
592 static const unsigned pi6_pins[] = {
593         TEGRA_PIN_PI6,
594 };
595
596 static const unsigned pi7_pins[] = {
597         TEGRA_PIN_PI7,
598 };
599
600 static const unsigned pj0_pins[] = {
601         TEGRA_PIN_PJ0,
602 };
603
604 static const unsigned pj2_pins[] = {
605         TEGRA_PIN_PJ2,
606 };
607
608 static const unsigned uart2_cts_n_pj5_pins[] = {
609         TEGRA_PIN_UART2_CTS_N_PJ5,
610 };
611
612 static const unsigned uart2_rts_n_pj6_pins[] = {
613         TEGRA_PIN_UART2_RTS_N_PJ6,
614 };
615
616 static const unsigned pj7_pins[] = {
617         TEGRA_PIN_PJ7,
618 };
619
620 static const unsigned pk0_pins[] = {
621         TEGRA_PIN_PK0,
622 };
623
624 static const unsigned pk1_pins[] = {
625         TEGRA_PIN_PK1,
626 };
627
628 static const unsigned pk2_pins[] = {
629         TEGRA_PIN_PK2,
630 };
631
632 static const unsigned pk3_pins[] = {
633         TEGRA_PIN_PK3,
634 };
635
636 static const unsigned pk4_pins[] = {
637         TEGRA_PIN_PK4,
638 };
639
640 static const unsigned spdif_out_pk5_pins[] = {
641         TEGRA_PIN_SPDIF_OUT_PK5,
642 };
643
644 static const unsigned spdif_in_pk6_pins[] = {
645         TEGRA_PIN_SPDIF_IN_PK6,
646 };
647
648 static const unsigned pk7_pins[] = {
649         TEGRA_PIN_PK7,
650 };
651
652 static const unsigned dap1_fs_pn0_pins[] = {
653         TEGRA_PIN_DAP1_FS_PN0,
654 };
655
656 static const unsigned dap1_din_pn1_pins[] = {
657         TEGRA_PIN_DAP1_DIN_PN1,
658 };
659
660 static const unsigned dap1_dout_pn2_pins[] = {
661         TEGRA_PIN_DAP1_DOUT_PN2,
662 };
663
664 static const unsigned dap1_sclk_pn3_pins[] = {
665         TEGRA_PIN_DAP1_SCLK_PN3,
666 };
667
668 static const unsigned usb_vbus_en0_pn4_pins[] = {
669         TEGRA_PIN_USB_VBUS_EN0_PN4,
670 };
671
672 static const unsigned usb_vbus_en1_pn5_pins[] = {
673         TEGRA_PIN_USB_VBUS_EN1_PN5,
674 };
675
676 static const unsigned hdmi_int_pn7_pins[] = {
677         TEGRA_PIN_HDMI_INT_PN7,
678 };
679
680 static const unsigned ulpi_data7_po0_pins[] = {
681         TEGRA_PIN_ULPI_DATA7_PO0,
682 };
683
684 static const unsigned ulpi_data0_po1_pins[] = {
685         TEGRA_PIN_ULPI_DATA0_PO1,
686 };
687
688 static const unsigned ulpi_data1_po2_pins[] = {
689         TEGRA_PIN_ULPI_DATA1_PO2,
690 };
691
692 static const unsigned ulpi_data2_po3_pins[] = {
693         TEGRA_PIN_ULPI_DATA2_PO3,
694 };
695
696 static const unsigned ulpi_data3_po4_pins[] = {
697         TEGRA_PIN_ULPI_DATA3_PO4,
698 };
699
700 static const unsigned ulpi_data4_po5_pins[] = {
701         TEGRA_PIN_ULPI_DATA4_PO5,
702 };
703
704 static const unsigned ulpi_data5_po6_pins[] = {
705         TEGRA_PIN_ULPI_DATA5_PO6,
706 };
707
708 static const unsigned ulpi_data6_po7_pins[] = {
709         TEGRA_PIN_ULPI_DATA6_PO7,
710 };
711
712 static const unsigned dap3_fs_pp0_pins[] = {
713         TEGRA_PIN_DAP3_FS_PP0,
714 };
715
716 static const unsigned dap3_din_pp1_pins[] = {
717         TEGRA_PIN_DAP3_DIN_PP1,
718 };
719
720 static const unsigned dap3_dout_pp2_pins[] = {
721         TEGRA_PIN_DAP3_DOUT_PP2,
722 };
723
724 static const unsigned dap3_sclk_pp3_pins[] = {
725         TEGRA_PIN_DAP3_SCLK_PP3,
726 };
727
728 static const unsigned dap4_fs_pp4_pins[] = {
729         TEGRA_PIN_DAP4_FS_PP4,
730 };
731
732 static const unsigned dap4_din_pp5_pins[] = {
733         TEGRA_PIN_DAP4_DIN_PP5,
734 };
735
736 static const unsigned dap4_dout_pp6_pins[] = {
737         TEGRA_PIN_DAP4_DOUT_PP6,
738 };
739
740 static const unsigned dap4_sclk_pp7_pins[] = {
741         TEGRA_PIN_DAP4_SCLK_PP7,
742 };
743
744 static const unsigned kb_col0_pq0_pins[] = {
745         TEGRA_PIN_KB_COL0_PQ0,
746 };
747
748 static const unsigned kb_col1_pq1_pins[] = {
749         TEGRA_PIN_KB_COL1_PQ1,
750 };
751
752 static const unsigned kb_col2_pq2_pins[] = {
753         TEGRA_PIN_KB_COL2_PQ2,
754 };
755
756 static const unsigned kb_col3_pq3_pins[] = {
757         TEGRA_PIN_KB_COL3_PQ3,
758 };
759
760 static const unsigned kb_col4_pq4_pins[] = {
761         TEGRA_PIN_KB_COL4_PQ4,
762 };
763
764 static const unsigned kb_col5_pq5_pins[] = {
765         TEGRA_PIN_KB_COL5_PQ5,
766 };
767
768 static const unsigned kb_col6_pq6_pins[] = {
769         TEGRA_PIN_KB_COL6_PQ6,
770 };
771
772 static const unsigned kb_col7_pq7_pins[] = {
773         TEGRA_PIN_KB_COL7_PQ7,
774 };
775
776 static const unsigned kb_row0_pr0_pins[] = {
777         TEGRA_PIN_KB_ROW0_PR0,
778 };
779
780 static const unsigned kb_row1_pr1_pins[] = {
781         TEGRA_PIN_KB_ROW1_PR1,
782 };
783
784 static const unsigned kb_row2_pr2_pins[] = {
785         TEGRA_PIN_KB_ROW2_PR2,
786 };
787
788 static const unsigned kb_row3_pr3_pins[] = {
789         TEGRA_PIN_KB_ROW3_PR3,
790 };
791
792 static const unsigned kb_row4_pr4_pins[] = {
793         TEGRA_PIN_KB_ROW4_PR4,
794 };
795
796 static const unsigned kb_row5_pr5_pins[] = {
797         TEGRA_PIN_KB_ROW5_PR5,
798 };
799
800 static const unsigned kb_row6_pr6_pins[] = {
801         TEGRA_PIN_KB_ROW6_PR6,
802 };
803
804 static const unsigned kb_row7_pr7_pins[] = {
805         TEGRA_PIN_KB_ROW7_PR7,
806 };
807
808 static const unsigned kb_row8_ps0_pins[] = {
809         TEGRA_PIN_KB_ROW8_PS0,
810 };
811
812 static const unsigned kb_row9_ps1_pins[] = {
813         TEGRA_PIN_KB_ROW9_PS1,
814 };
815
816 static const unsigned kb_row10_ps2_pins[] = {
817         TEGRA_PIN_KB_ROW10_PS2,
818 };
819
820 static const unsigned kb_row11_ps3_pins[] = {
821         TEGRA_PIN_KB_ROW11_PS3,
822 };
823
824 static const unsigned kb_row12_ps4_pins[] = {
825         TEGRA_PIN_KB_ROW12_PS4,
826 };
827
828 static const unsigned kb_row13_ps5_pins[] = {
829         TEGRA_PIN_KB_ROW13_PS5,
830 };
831
832 static const unsigned kb_row14_ps6_pins[] = {
833         TEGRA_PIN_KB_ROW14_PS6,
834 };
835
836 static const unsigned kb_row15_ps7_pins[] = {
837         TEGRA_PIN_KB_ROW15_PS7,
838 };
839
840 static const unsigned kb_row16_pt0_pins[] = {
841         TEGRA_PIN_KB_ROW16_PT0,
842 };
843
844 static const unsigned kb_row17_pt1_pins[] = {
845         TEGRA_PIN_KB_ROW17_PT1,
846 };
847
848 static const unsigned gen2_i2c_scl_pt5_pins[] = {
849         TEGRA_PIN_GEN2_I2C_SCL_PT5,
850 };
851
852 static const unsigned gen2_i2c_sda_pt6_pins[] = {
853         TEGRA_PIN_GEN2_I2C_SDA_PT6,
854 };
855
856 static const unsigned sdmmc4_cmd_pt7_pins[] = {
857         TEGRA_PIN_SDMMC4_CMD_PT7,
858 };
859
860 static const unsigned pu0_pins[] = {
861         TEGRA_PIN_PU0,
862 };
863
864 static const unsigned pu1_pins[] = {
865         TEGRA_PIN_PU1,
866 };
867
868 static const unsigned pu2_pins[] = {
869         TEGRA_PIN_PU2,
870 };
871
872 static const unsigned pu3_pins[] = {
873         TEGRA_PIN_PU3,
874 };
875
876 static const unsigned pu4_pins[] = {
877         TEGRA_PIN_PU4,
878 };
879
880 static const unsigned pu5_pins[] = {
881         TEGRA_PIN_PU5,
882 };
883
884 static const unsigned pu6_pins[] = {
885         TEGRA_PIN_PU6,
886 };
887
888 static const unsigned pv0_pins[] = {
889         TEGRA_PIN_PV0,
890 };
891
892 static const unsigned pv1_pins[] = {
893         TEGRA_PIN_PV1,
894 };
895
896 static const unsigned sdmmc3_cd_n_pv2_pins[] = {
897         TEGRA_PIN_SDMMC3_CD_N_PV2,
898 };
899
900 static const unsigned sdmmc1_wp_n_pv3_pins[] = {
901         TEGRA_PIN_SDMMC1_WP_N_PV3,
902 };
903
904 static const unsigned ddc_scl_pv4_pins[] = {
905         TEGRA_PIN_DDC_SCL_PV4,
906 };
907
908 static const unsigned ddc_sda_pv5_pins[] = {
909         TEGRA_PIN_DDC_SDA_PV5,
910 };
911
912 static const unsigned gpio_w2_aud_pw2_pins[] = {
913         TEGRA_PIN_GPIO_W2_AUD_PW2,
914 };
915
916 static const unsigned gpio_w3_aud_pw3_pins[] = {
917         TEGRA_PIN_GPIO_W3_AUD_PW3,
918 };
919
920 static const unsigned dap_mclk1_pw4_pins[] = {
921         TEGRA_PIN_DAP_MCLK1_PW4,
922 };
923
924 static const unsigned clk2_out_pw5_pins[] = {
925         TEGRA_PIN_CLK2_OUT_PW5,
926 };
927
928 static const unsigned uart3_txd_pw6_pins[] = {
929         TEGRA_PIN_UART3_TXD_PW6,
930 };
931
932 static const unsigned uart3_rxd_pw7_pins[] = {
933         TEGRA_PIN_UART3_RXD_PW7,
934 };
935
936 static const unsigned dvfs_pwm_px0_pins[] = {
937         TEGRA_PIN_DVFS_PWM_PX0,
938 };
939
940 static const unsigned gpio_x1_aud_px1_pins[] = {
941         TEGRA_PIN_GPIO_X1_AUD_PX1,
942 };
943
944 static const unsigned dvfs_clk_px2_pins[] = {
945         TEGRA_PIN_DVFS_CLK_PX2,
946 };
947
948 static const unsigned gpio_x3_aud_px3_pins[] = {
949         TEGRA_PIN_GPIO_X3_AUD_PX3,
950 };
951
952 static const unsigned gpio_x4_aud_px4_pins[] = {
953         TEGRA_PIN_GPIO_X4_AUD_PX4,
954 };
955
956 static const unsigned gpio_x5_aud_px5_pins[] = {
957         TEGRA_PIN_GPIO_X5_AUD_PX5,
958 };
959
960 static const unsigned gpio_x6_aud_px6_pins[] = {
961         TEGRA_PIN_GPIO_X6_AUD_PX6,
962 };
963
964 static const unsigned gpio_x7_aud_px7_pins[] = {
965         TEGRA_PIN_GPIO_X7_AUD_PX7,
966 };
967
968 static const unsigned ulpi_clk_py0_pins[] = {
969         TEGRA_PIN_ULPI_CLK_PY0,
970 };
971
972 static const unsigned ulpi_dir_py1_pins[] = {
973         TEGRA_PIN_ULPI_DIR_PY1,
974 };
975
976 static const unsigned ulpi_nxt_py2_pins[] = {
977         TEGRA_PIN_ULPI_NXT_PY2,
978 };
979
980 static const unsigned ulpi_stp_py3_pins[] = {
981         TEGRA_PIN_ULPI_STP_PY3,
982 };
983
984 static const unsigned sdmmc1_dat3_py4_pins[] = {
985         TEGRA_PIN_SDMMC1_DAT3_PY4,
986 };
987
988 static const unsigned sdmmc1_dat2_py5_pins[] = {
989         TEGRA_PIN_SDMMC1_DAT2_PY5,
990 };
991
992 static const unsigned sdmmc1_dat1_py6_pins[] = {
993         TEGRA_PIN_SDMMC1_DAT1_PY6,
994 };
995
996 static const unsigned sdmmc1_dat0_py7_pins[] = {
997         TEGRA_PIN_SDMMC1_DAT0_PY7,
998 };
999
1000 static const unsigned sdmmc1_clk_pz0_pins[] = {
1001         TEGRA_PIN_SDMMC1_CLK_PZ0,
1002 };
1003
1004 static const unsigned sdmmc1_cmd_pz1_pins[] = {
1005         TEGRA_PIN_SDMMC1_CMD_PZ1,
1006 };
1007
1008 static const unsigned pwr_i2c_scl_pz6_pins[] = {
1009         TEGRA_PIN_PWR_I2C_SCL_PZ6,
1010 };
1011
1012 static const unsigned pwr_i2c_sda_pz7_pins[] = {
1013         TEGRA_PIN_PWR_I2C_SDA_PZ7,
1014 };
1015
1016 static const unsigned sdmmc4_dat0_paa0_pins[] = {
1017         TEGRA_PIN_SDMMC4_DAT0_PAA0,
1018 };
1019
1020 static const unsigned sdmmc4_dat1_paa1_pins[] = {
1021         TEGRA_PIN_SDMMC4_DAT1_PAA1,
1022 };
1023
1024 static const unsigned sdmmc4_dat2_paa2_pins[] = {
1025         TEGRA_PIN_SDMMC4_DAT2_PAA2,
1026 };
1027
1028 static const unsigned sdmmc4_dat3_paa3_pins[] = {
1029         TEGRA_PIN_SDMMC4_DAT3_PAA3,
1030 };
1031
1032 static const unsigned sdmmc4_dat4_paa4_pins[] = {
1033         TEGRA_PIN_SDMMC4_DAT4_PAA4,
1034 };
1035
1036 static const unsigned sdmmc4_dat5_paa5_pins[] = {
1037         TEGRA_PIN_SDMMC4_DAT5_PAA5,
1038 };
1039
1040 static const unsigned sdmmc4_dat6_paa6_pins[] = {
1041         TEGRA_PIN_SDMMC4_DAT6_PAA6,
1042 };
1043
1044 static const unsigned sdmmc4_dat7_paa7_pins[] = {
1045         TEGRA_PIN_SDMMC4_DAT7_PAA7,
1046 };
1047
1048 static const unsigned pbb0_pins[] = {
1049         TEGRA_PIN_PBB0,
1050 };
1051
1052 static const unsigned cam_i2c_scl_pbb1_pins[] = {
1053         TEGRA_PIN_CAM_I2C_SCL_PBB1,
1054 };
1055
1056 static const unsigned cam_i2c_sda_pbb2_pins[] = {
1057         TEGRA_PIN_CAM_I2C_SDA_PBB2,
1058 };
1059
1060 static const unsigned pbb3_pins[] = {
1061         TEGRA_PIN_PBB3,
1062 };
1063
1064 static const unsigned pbb4_pins[] = {
1065         TEGRA_PIN_PBB4,
1066 };
1067
1068 static const unsigned pbb5_pins[] = {
1069         TEGRA_PIN_PBB5,
1070 };
1071
1072 static const unsigned pbb6_pins[] = {
1073         TEGRA_PIN_PBB6,
1074 };
1075
1076 static const unsigned pbb7_pins[] = {
1077         TEGRA_PIN_PBB7,
1078 };
1079
1080 static const unsigned cam_mclk_pcc0_pins[] = {
1081         TEGRA_PIN_CAM_MCLK_PCC0,
1082 };
1083
1084 static const unsigned pcc1_pins[] = {
1085         TEGRA_PIN_PCC1,
1086 };
1087
1088 static const unsigned pcc2_pins[] = {
1089         TEGRA_PIN_PCC2,
1090 };
1091
1092 static const unsigned sdmmc4_clk_pcc4_pins[] = {
1093         TEGRA_PIN_SDMMC4_CLK_PCC4,
1094 };
1095
1096 static const unsigned clk2_req_pcc5_pins[] = {
1097         TEGRA_PIN_CLK2_REQ_PCC5,
1098 };
1099
1100 static const unsigned pex_l0_rst_n_pdd1_pins[] = {
1101         TEGRA_PIN_PEX_L0_RST_N_PDD1,
1102 };
1103
1104 static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
1105         TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1106 };
1107
1108 static const unsigned pex_wake_n_pdd3_pins[] = {
1109         TEGRA_PIN_PEX_WAKE_N_PDD3,
1110 };
1111
1112 static const unsigned pex_l1_rst_n_pdd5_pins[] = {
1113         TEGRA_PIN_PEX_L1_RST_N_PDD5,
1114 };
1115
1116 static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
1117         TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1118 };
1119
1120 static const unsigned clk3_out_pee0_pins[] = {
1121         TEGRA_PIN_CLK3_OUT_PEE0,
1122 };
1123
1124 static const unsigned clk3_req_pee1_pins[] = {
1125         TEGRA_PIN_CLK3_REQ_PEE1,
1126 };
1127
1128 static const unsigned dap_mclk1_req_pee2_pins[] = {
1129         TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
1130 };
1131
1132 static const unsigned hdmi_cec_pee3_pins[] = {
1133         TEGRA_PIN_HDMI_CEC_PEE3,
1134 };
1135
1136 static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
1137         TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1138 };
1139
1140 static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
1141         TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1142 };
1143 static const unsigned dp_hpd_pff0_pins[] = {
1144         TEGRA_PIN_DP_HPD_PFF0,
1145 };
1146
1147 static const unsigned usb_vbus_en2_pff1_pins[] = {
1148         TEGRA_PIN_USB_VBUS_EN2_PFF1,
1149 };
1150
1151 static const unsigned pff2_pins[] = {
1152         TEGRA_PIN_PFF2,
1153 };
1154
1155 static const unsigned core_pwr_req_pins[] = {
1156         TEGRA_PIN_CORE_PWR_REQ,
1157 };
1158
1159 static const unsigned cpu_pwr_req_pins[] = {
1160         TEGRA_PIN_CPU_PWR_REQ,
1161 };
1162
1163 static const unsigned owr_pins[] = {
1164         TEGRA_PIN_OWR,
1165 };
1166
1167 static const unsigned pwr_int_n_pins[] = {
1168         TEGRA_PIN_PWR_INT_N,
1169 };
1170
1171 static const unsigned reset_out_n_pins[] = {
1172         TEGRA_PIN_RESET_OUT_N,
1173 };
1174
1175 static const unsigned clk_32k_in_pins[] = {
1176         TEGRA_PIN_CLK_32K_IN,
1177 };
1178
1179 static const unsigned gmi_clk_lb_pins[] = {
1180         TEGRA_PIN_GMI_CLK_LB,
1181 };
1182
1183 static const unsigned jtag_rtck_pins[] = {
1184         TEGRA_PIN_JTAG_RTCK,
1185 };
1186
1187 static const unsigned drive_ao1_pins[] = {
1188         TEGRA_PIN_KB_ROW0_PR0,
1189         TEGRA_PIN_KB_ROW1_PR1,
1190         TEGRA_PIN_KB_ROW2_PR2,
1191         TEGRA_PIN_KB_ROW3_PR3,
1192         TEGRA_PIN_KB_ROW4_PR4,
1193         TEGRA_PIN_KB_ROW5_PR5,
1194         TEGRA_PIN_KB_ROW6_PR6,
1195         TEGRA_PIN_KB_ROW7_PR7,
1196         TEGRA_PIN_PWR_I2C_SCL_PZ6,
1197         TEGRA_PIN_PWR_I2C_SDA_PZ7,
1198 };
1199
1200 static const unsigned drive_ao2_pins[] = {
1201         TEGRA_PIN_CLK_32K_OUT_PA0,
1202         TEGRA_PIN_CLK_32K_IN,
1203         TEGRA_PIN_KB_COL0_PQ0,
1204         TEGRA_PIN_KB_COL1_PQ1,
1205         TEGRA_PIN_KB_COL2_PQ2,
1206         TEGRA_PIN_KB_COL3_PQ3,
1207         TEGRA_PIN_KB_COL4_PQ4,
1208         TEGRA_PIN_KB_COL5_PQ5,
1209         TEGRA_PIN_KB_COL6_PQ6,
1210         TEGRA_PIN_KB_COL7_PQ7,
1211         TEGRA_PIN_KB_ROW8_PS0,
1212         TEGRA_PIN_KB_ROW9_PS1,
1213         TEGRA_PIN_KB_ROW10_PS2,
1214         TEGRA_PIN_KB_ROW11_PS3,
1215         TEGRA_PIN_KB_ROW12_PS4,
1216         TEGRA_PIN_KB_ROW13_PS5,
1217         TEGRA_PIN_KB_ROW14_PS6,
1218         TEGRA_PIN_KB_ROW15_PS7,
1219         TEGRA_PIN_KB_ROW16_PT0,
1220         TEGRA_PIN_KB_ROW17_PT1,
1221         TEGRA_PIN_SDMMC3_CD_N_PV2,
1222         TEGRA_PIN_CORE_PWR_REQ,
1223         TEGRA_PIN_CPU_PWR_REQ,
1224         TEGRA_PIN_PWR_INT_N,
1225 };
1226
1227 static const unsigned drive_at1_pins[] = {
1228         TEGRA_PIN_PH0,
1229         TEGRA_PIN_PH1,
1230         TEGRA_PIN_PH2,
1231         TEGRA_PIN_PH3,
1232 };
1233
1234 static const unsigned drive_at2_pins[] = {
1235         TEGRA_PIN_PG0,
1236         TEGRA_PIN_PG1,
1237         TEGRA_PIN_PG2,
1238         TEGRA_PIN_PG3,
1239         TEGRA_PIN_PG4,
1240         TEGRA_PIN_PG5,
1241         TEGRA_PIN_PG6,
1242         TEGRA_PIN_PG7,
1243         TEGRA_PIN_PI0,
1244         TEGRA_PIN_PI1,
1245         TEGRA_PIN_PI3,
1246         TEGRA_PIN_PI4,
1247         TEGRA_PIN_PI7,
1248         TEGRA_PIN_PK0,
1249         TEGRA_PIN_PK2,
1250 };
1251
1252 static const unsigned drive_at3_pins[] = {
1253         TEGRA_PIN_PC7,
1254         TEGRA_PIN_PJ0,
1255 };
1256
1257 static const unsigned drive_at4_pins[] = {
1258         TEGRA_PIN_PB0,
1259         TEGRA_PIN_PB1,
1260         TEGRA_PIN_PJ0,
1261         TEGRA_PIN_PJ7,
1262         TEGRA_PIN_PK7,
1263 };
1264
1265 static const unsigned drive_at5_pins[] = {
1266         TEGRA_PIN_GEN2_I2C_SCL_PT5,
1267         TEGRA_PIN_GEN2_I2C_SDA_PT6,
1268 };
1269
1270 static const unsigned drive_cdev1_pins[] = {
1271         TEGRA_PIN_DAP_MCLK1_PW4,
1272         TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
1273 };
1274
1275 static const unsigned drive_cdev2_pins[] = {
1276         TEGRA_PIN_CLK2_OUT_PW5,
1277         TEGRA_PIN_CLK2_REQ_PCC5,
1278 };
1279
1280 static const unsigned drive_dap1_pins[] = {
1281         TEGRA_PIN_DAP1_FS_PN0,
1282         TEGRA_PIN_DAP1_DIN_PN1,
1283         TEGRA_PIN_DAP1_DOUT_PN2,
1284         TEGRA_PIN_DAP1_SCLK_PN3,
1285 };
1286
1287 static const unsigned drive_dap2_pins[] = {
1288         TEGRA_PIN_DAP2_FS_PA2,
1289         TEGRA_PIN_DAP2_SCLK_PA3,
1290         TEGRA_PIN_DAP2_DIN_PA4,
1291         TEGRA_PIN_DAP2_DOUT_PA5,
1292 };
1293
1294 static const unsigned drive_dap3_pins[] = {
1295         TEGRA_PIN_DAP3_FS_PP0,
1296         TEGRA_PIN_DAP3_DIN_PP1,
1297         TEGRA_PIN_DAP3_DOUT_PP2,
1298         TEGRA_PIN_DAP3_SCLK_PP3,
1299 };
1300
1301 static const unsigned drive_dap4_pins[] = {
1302         TEGRA_PIN_DAP4_FS_PP4,
1303         TEGRA_PIN_DAP4_DIN_PP5,
1304         TEGRA_PIN_DAP4_DOUT_PP6,
1305         TEGRA_PIN_DAP4_SCLK_PP7,
1306 };
1307
1308 static const unsigned drive_dbg_pins[] = {
1309         TEGRA_PIN_GEN1_I2C_SCL_PC4,
1310         TEGRA_PIN_GEN1_I2C_SDA_PC5,
1311         TEGRA_PIN_PU0,
1312         TEGRA_PIN_PU1,
1313         TEGRA_PIN_PU2,
1314         TEGRA_PIN_PU3,
1315         TEGRA_PIN_PU4,
1316         TEGRA_PIN_PU5,
1317         TEGRA_PIN_PU6,
1318 };
1319
1320 static const unsigned drive_sdio3_pins[] = {
1321         TEGRA_PIN_SDMMC3_CLK_PA6,
1322         TEGRA_PIN_SDMMC3_CMD_PA7,
1323         TEGRA_PIN_SDMMC3_DAT3_PB4,
1324         TEGRA_PIN_SDMMC3_DAT2_PB5,
1325         TEGRA_PIN_SDMMC3_DAT1_PB6,
1326         TEGRA_PIN_SDMMC3_DAT0_PB7,
1327         TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1328         TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1329 };
1330
1331 static const unsigned drive_spi_pins[] = {
1332         TEGRA_PIN_DVFS_PWM_PX0,
1333         TEGRA_PIN_GPIO_X1_AUD_PX1,
1334         TEGRA_PIN_DVFS_CLK_PX2,
1335         TEGRA_PIN_GPIO_X3_AUD_PX3,
1336         TEGRA_PIN_GPIO_X4_AUD_PX4,
1337         TEGRA_PIN_GPIO_X5_AUD_PX5,
1338         TEGRA_PIN_GPIO_X6_AUD_PX6,
1339         TEGRA_PIN_GPIO_X7_AUD_PX7,
1340         TEGRA_PIN_GPIO_W2_AUD_PW2,
1341         TEGRA_PIN_GPIO_W3_AUD_PW3,
1342 };
1343
1344 static const unsigned drive_uaa_pins[] = {
1345         TEGRA_PIN_ULPI_DATA0_PO1,
1346         TEGRA_PIN_ULPI_DATA1_PO2,
1347         TEGRA_PIN_ULPI_DATA2_PO3,
1348         TEGRA_PIN_ULPI_DATA3_PO4,
1349 };
1350
1351 static const unsigned drive_uab_pins[] = {
1352         TEGRA_PIN_ULPI_DATA7_PO0,
1353         TEGRA_PIN_ULPI_DATA4_PO5,
1354         TEGRA_PIN_ULPI_DATA5_PO6,
1355         TEGRA_PIN_ULPI_DATA6_PO7,
1356         TEGRA_PIN_PV0,
1357         TEGRA_PIN_PV1,
1358 };
1359
1360 static const unsigned drive_uart2_pins[] = {
1361         TEGRA_PIN_UART2_TXD_PC2,
1362         TEGRA_PIN_UART2_RXD_PC3,
1363         TEGRA_PIN_UART2_CTS_N_PJ5,
1364         TEGRA_PIN_UART2_RTS_N_PJ6,
1365 };
1366
1367 static const unsigned drive_uart3_pins[] = {
1368         TEGRA_PIN_UART3_CTS_N_PA1,
1369         TEGRA_PIN_UART3_RTS_N_PC0,
1370         TEGRA_PIN_UART3_TXD_PW6,
1371         TEGRA_PIN_UART3_RXD_PW7,
1372 };
1373
1374 static const unsigned drive_sdio1_pins[] = {
1375         TEGRA_PIN_SDMMC1_DAT3_PY4,
1376         TEGRA_PIN_SDMMC1_DAT2_PY5,
1377         TEGRA_PIN_SDMMC1_DAT1_PY6,
1378         TEGRA_PIN_SDMMC1_DAT0_PY7,
1379         TEGRA_PIN_SDMMC1_CLK_PZ0,
1380         TEGRA_PIN_SDMMC1_CMD_PZ1,
1381 };
1382
1383 static const unsigned drive_ddc_pins[] = {
1384         TEGRA_PIN_DDC_SCL_PV4,
1385         TEGRA_PIN_DDC_SDA_PV5,
1386 };
1387
1388 static const unsigned drive_gma_pins[] = {
1389         TEGRA_PIN_SDMMC4_CLK_PCC4,
1390         TEGRA_PIN_SDMMC4_CMD_PT7,
1391         TEGRA_PIN_SDMMC4_DAT0_PAA0,
1392         TEGRA_PIN_SDMMC4_DAT1_PAA1,
1393         TEGRA_PIN_SDMMC4_DAT2_PAA2,
1394         TEGRA_PIN_SDMMC4_DAT3_PAA3,
1395         TEGRA_PIN_SDMMC4_DAT4_PAA4,
1396         TEGRA_PIN_SDMMC4_DAT5_PAA5,
1397         TEGRA_PIN_SDMMC4_DAT6_PAA6,
1398         TEGRA_PIN_SDMMC4_DAT7_PAA7,
1399 };
1400
1401 static const unsigned drive_gme_pins[] = {
1402         TEGRA_PIN_PBB0,
1403         TEGRA_PIN_CAM_I2C_SCL_PBB1,
1404         TEGRA_PIN_CAM_I2C_SDA_PBB2,
1405         TEGRA_PIN_PBB3,
1406         TEGRA_PIN_PCC2,
1407 };
1408
1409 static const unsigned drive_gmf_pins[] = {
1410         TEGRA_PIN_PBB4,
1411         TEGRA_PIN_PBB5,
1412         TEGRA_PIN_PBB6,
1413         TEGRA_PIN_PBB7,
1414 };
1415
1416 static const unsigned drive_gmg_pins[] = {
1417         TEGRA_PIN_CAM_MCLK_PCC0,
1418 };
1419
1420 static const unsigned drive_gmh_pins[] = {
1421         TEGRA_PIN_PCC1,
1422 };
1423
1424 static const unsigned drive_owr_pins[] = {
1425         TEGRA_PIN_SDMMC3_CD_N_PV2,
1426         TEGRA_PIN_OWR,
1427 };
1428
1429 static const unsigned drive_uda_pins[] = {
1430         TEGRA_PIN_ULPI_CLK_PY0,
1431         TEGRA_PIN_ULPI_DIR_PY1,
1432         TEGRA_PIN_ULPI_NXT_PY2,
1433         TEGRA_PIN_ULPI_STP_PY3,
1434 };
1435
1436 static const unsigned drive_gpv_pins[] = {
1437         TEGRA_PIN_PEX_L0_RST_N_PDD1,
1438         TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1439         TEGRA_PIN_PEX_WAKE_N_PDD3,
1440         TEGRA_PIN_PEX_L1_RST_N_PDD5,
1441         TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1442         TEGRA_PIN_USB_VBUS_EN2_PFF1,
1443         TEGRA_PIN_PFF2,
1444 };
1445
1446 static const unsigned drive_cec_pins[] = {
1447         TEGRA_PIN_HDMI_CEC_PEE3,
1448 };
1449
1450 static const unsigned drive_dev3_pins[] = {
1451         TEGRA_PIN_CLK3_OUT_PEE0,
1452         TEGRA_PIN_CLK3_REQ_PEE1,
1453 };
1454
1455 static const unsigned drive_at6_pins[] = {
1456         TEGRA_PIN_PK1,
1457         TEGRA_PIN_PK3,
1458         TEGRA_PIN_PK4,
1459         TEGRA_PIN_PI2,
1460         TEGRA_PIN_PI5,
1461         TEGRA_PIN_PI6,
1462         TEGRA_PIN_PH4,
1463         TEGRA_PIN_PH5,
1464         TEGRA_PIN_PH6,
1465         TEGRA_PIN_PH7,
1466 };
1467
1468 static const unsigned drive_dap5_pins[] = {
1469         TEGRA_PIN_SPDIF_IN_PK6,
1470         TEGRA_PIN_SPDIF_OUT_PK5,
1471         TEGRA_PIN_DP_HPD_PFF0,
1472 };
1473
1474 static const unsigned drive_usb_vbus_en_pins[] = {
1475         TEGRA_PIN_USB_VBUS_EN0_PN4,
1476         TEGRA_PIN_USB_VBUS_EN1_PN5,
1477 };
1478
1479 static const unsigned drive_ao3_pins[] = {
1480         TEGRA_PIN_RESET_OUT_N,
1481 };
1482
1483 static const unsigned drive_ao0_pins[] = {
1484         TEGRA_PIN_JTAG_RTCK,
1485 };
1486
1487 static const unsigned drive_hv0_pins[] = {
1488         TEGRA_PIN_HDMI_INT_PN7,
1489 };
1490
1491 static const unsigned drive_sdio4_pins[] = {
1492         TEGRA_PIN_SDMMC1_WP_N_PV3,
1493 };
1494
1495 static const unsigned drive_ao4_pins[] = {
1496         TEGRA_PIN_JTAG_RTCK,
1497 };
1498
1499 enum tegra_mux_dt {
1500         TEGRA_MUX_DT_SAFE,
1501         TEGRA_MUX_DT_BLINK,
1502         TEGRA_MUX_DT_CEC,
1503         TEGRA_MUX_DT_CLDVFS,
1504         TEGRA_MUX_DT_CLK12,
1505         TEGRA_MUX_DT_CPU,
1506         TEGRA_MUX_DT_DAP,
1507         TEGRA_MUX_DT_DAP1,
1508         TEGRA_MUX_DT_DAP2,
1509         TEGRA_MUX_DT_DEV3,
1510         TEGRA_MUX_DT_DISPLAYA,
1511         TEGRA_MUX_DT_DISPLAYA_ALT,
1512         TEGRA_MUX_DT_DISPLAYB,
1513         TEGRA_MUX_DT_DTV,
1514         TEGRA_MUX_DT_EXTPERIPH1,
1515         TEGRA_MUX_DT_EXTPERIPH2,
1516         TEGRA_MUX_DT_EXTPERIPH3,
1517         TEGRA_MUX_DT_GMI,
1518         TEGRA_MUX_DT_GMI_ALT,
1519         TEGRA_MUX_DT_HDA,
1520         TEGRA_MUX_DT_HSI,
1521         TEGRA_MUX_DT_I2C1,
1522         TEGRA_MUX_DT_I2C2,
1523         TEGRA_MUX_DT_I2C3,
1524         TEGRA_MUX_DT_I2C4,
1525         TEGRA_MUX_DT_I2CPWR,
1526         TEGRA_MUX_DT_I2S0,
1527         TEGRA_MUX_DT_I2S1,
1528         TEGRA_MUX_DT_I2S2,
1529         TEGRA_MUX_DT_I2S3,
1530         TEGRA_MUX_DT_I2S4,
1531         TEGRA_MUX_DT_IRDA,
1532         TEGRA_MUX_DT_KBC,
1533         TEGRA_MUX_DT_OWR,
1534         TEGRA_MUX_DT_PMI,
1535         TEGRA_MUX_DT_PWM0,
1536         TEGRA_MUX_DT_PWM1,
1537         TEGRA_MUX_DT_PWM2,
1538         TEGRA_MUX_DT_PWM3,
1539         TEGRA_MUX_DT_PWRON,
1540         TEGRA_MUX_DT_RESET_OUT_N,
1541         TEGRA_MUX_DT_RSVD1,
1542         TEGRA_MUX_DT_RSVD2,
1543         TEGRA_MUX_DT_RSVD3,
1544         TEGRA_MUX_DT_RSVD4,
1545         TEGRA_MUX_DT_SDMMC1,
1546         TEGRA_MUX_DT_SDMMC2,
1547         TEGRA_MUX_DT_SDMMC3,
1548         TEGRA_MUX_DT_SDMMC4,
1549         TEGRA_MUX_DT_SOC,
1550         TEGRA_MUX_DT_SPDIF,
1551         TEGRA_MUX_DT_SPI1,
1552         TEGRA_MUX_DT_SPI2,
1553         TEGRA_MUX_DT_SPI3,
1554         TEGRA_MUX_DT_SPI4,
1555         TEGRA_MUX_DT_SPI5,
1556         TEGRA_MUX_DT_SPI6,
1557         TEGRA_MUX_DT_TRACE,
1558         TEGRA_MUX_DT_UARTA,
1559         TEGRA_MUX_DT_UARTB,
1560         TEGRA_MUX_DT_UARTC,
1561         TEGRA_MUX_DT_UARTD,
1562         TEGRA_MUX_DT_ULPI,
1563         TEGRA_MUX_DT_USB,
1564         TEGRA_MUX_DT_VGP1,
1565         TEGRA_MUX_DT_VGP2,
1566         TEGRA_MUX_DT_VGP3,
1567         TEGRA_MUX_DT_VGP4,
1568         TEGRA_MUX_DT_VGP5,
1569         TEGRA_MUX_DT_VGP6,
1570         TEGRA_MUX_DT_VI,
1571         TEGRA_MUX_DT_VI_ALT1,
1572         TEGRA_MUX_DT_VI_ALT3,
1573         TEGRA_MUX_DT_VIMCLK2,
1574         TEGRA_MUX_DT_VIMCLK2_ALT,
1575         TEGRA_MUX_DT_SATA,
1576         TEGRA_MUX_DT_CCLA,
1577         TEGRA_MUX_DT_PE0,
1578         TEGRA_MUX_DT_PE,
1579         TEGRA_MUX_DT_PE1,
1580         TEGRA_MUX_DT_DP,
1581         TEGRA_MUX_DT_RTCK,
1582         TEGRA_MUX_DT_SYS,
1583         TEGRA_MUX_DT_CLK,
1584         TEGRA_MUX_DT_TMDS,
1585 };
1586
1587 static const char * const blink_groups[] = {
1588         "clk_32k_out_pa0",
1589 };
1590
1591 static const char * const cec_groups[] = {
1592         "hdmi_cec_pee3",
1593 };
1594
1595 static const char * const cldvfs_groups[] = {
1596         "ph2",
1597         "ph3",
1598         "kb_row7_pr7",
1599         "kb_row8_ps0",
1600         "dvfs_pwm_px0",
1601         "dvfs_clk_px2",
1602 };
1603
1604 static const char * const clk12_groups[] = {
1605         "sdmmc1_wp_n_pv3",
1606         "sdmmc1_clk_pz0",
1607 };
1608
1609 static const char * const cpu_groups[] = {
1610         "cpu_pwr_req",
1611 };
1612
1613 static const char * const dap_groups[] = {
1614         "dap_mclk1_pee2",
1615         "clk2_req_pcc5",
1616 };
1617
1618 static const char * const dap1_groups[] = {
1619         "dap_mclk1_pee2",
1620 };
1621
1622 static const char * const dap2_groups[] = {
1623         "dap_mclk1_pw4",
1624         "gpio_x4_aud_px4",
1625 };
1626
1627 static const char * const dev3_groups[] = {
1628         "clk3_req_pee1",
1629 };
1630
1631 static const char * const displaya_groups[] = {
1632         "dap3_fs_pp0",
1633         "dap3_din_pp1",
1634         "dap3_dout_pp2",
1635         "ph1",
1636         "pi4",
1637         "pbb3",
1638         "pbb4",
1639         "pbb5",
1640         "kb_row3_pr3",
1641         "kb_row4_pr4",
1642         "kb_row5_pr5",
1643         "kb_row6_pr6",
1644         "kb_col3_pq3",
1645         "sdmmc3_dat2_pb5",
1646 };
1647
1648 static const char * const displaya_alt_groups[] = {
1649         "kb_row6_pr6",
1650 };
1651
1652 static const char * const displayb_groups[] = {
1653         "dap3_fs_pp0",
1654         "dap3_din_pp1",
1655         "dap3_sclk_pp3",
1656
1657         "pu3",
1658         "pu4",
1659         "pu5",
1660
1661         "pbb3",
1662         "pbb4",
1663         "pbb6",
1664
1665         "kb_row3_pr3",
1666         "kb_row4_pr4",
1667         "kb_row5_pr5",
1668         "kb_row6_pr6",
1669
1670         "sdmmc3_dat3_pb4",
1671 };
1672
1673 static const char * const dtv_groups[] = {
1674         "uart3_cts_n_pa1",
1675         "uart3_rts_n_pc0",
1676         "dap4_fs_pp4",
1677         "dap4_dout_pp6",
1678         "pi7",
1679         "ph0",
1680         "ph6",
1681         "ph7",
1682 };
1683
1684 static const char * const extperiph1_groups[] = {
1685         "dap_mclk1_pw4",
1686 };
1687
1688 static const char * const extperiph2_groups[] = {
1689         "clk2_out_pw5",
1690 };
1691
1692 static const char * const extperiph3_groups[] = {
1693         "clk3_out_pee0",
1694 };
1695
1696 static const char * const gmi_groups[] = {
1697         "uart2_cts_n_pj5",
1698         "uart2_rts_n_pj6",
1699         "uart3_txd_pw6",
1700         "uart3_rxd_pw7",
1701         "uart3_cts_n_pa1",
1702         "uart3_rts_n_pc0",
1703
1704         "pu0",
1705         "pu1",
1706         "pu2",
1707         "pu3",
1708         "pu4",
1709         "pu5",
1710         "pu6",
1711
1712         "dap4_fs_pp4",
1713         "dap4_din_pp5",
1714         "dap4_dout_pp6",
1715         "dap4_sclk_pp7",
1716
1717         "pc7",
1718
1719         "pg0",
1720         "pg1",
1721         "pg2",
1722         "pg3",
1723         "pg4",
1724         "pg5",
1725         "pg6",
1726         "pg7",
1727
1728         "ph0",
1729         "ph1",
1730         "ph2",
1731         "ph3",
1732         "ph4",
1733         "ph5",
1734         "ph6",
1735         "ph7",
1736
1737         "pi0",
1738         "pi1",
1739         "pi2",
1740         "pi3",
1741         "pi4",
1742         "pi5",
1743         "pi6",
1744         "pi7",
1745
1746         "pj0",
1747         "pj2",
1748
1749         "pk0",
1750         "pk1",
1751         "pk2",
1752         "pk3",
1753         "pk4",
1754
1755         "pj7",
1756         "pb0",
1757         "pb1",
1758         "pk7",
1759
1760         "gen2_i2c_scl_pt5",
1761         "gen2_i2c_sda_pt6",
1762
1763         "sdmmc4_dat0_paa0",
1764         "sdmmc4_dat1_paa1",
1765         "sdmmc4_dat2_paa2",
1766         "sdmmc4_dat3_paa3",
1767         "sdmmc4_dat4_paa4",
1768         "sdmmc4_dat6_paa6",
1769         "sdmmc4_dat7_paa7",
1770         "sdmmc4_clk_pcc4",
1771         "sdmmc4_cmd_pt7",
1772         "gmi_clk_lb",
1773
1774         "dap1_fs_pn0",
1775         "dap1_din_pn1",
1776         "dap1_dout_pn2",
1777         "dap1_sclk_pn3",
1778
1779         "dap2_fs_pa2",
1780         "dap2_din_pa4",
1781         "dap2_dout_pa5",
1782         "dap2_sclk_pa3",
1783
1784         "dvfs_pwm_px0",
1785         "dvfs_clk_px2",
1786         "gpio_x1_aud_px1",
1787         "gpio_x3_aud_px3",
1788         "gpio_x4_aud_px4",
1789         "gpio_x5_aud_px5",
1790         "gpio_x6_aud_px6",
1791 };
1792
1793 static const char * const gmi_alt_groups[] = {
1794         "pc7",
1795         "pk4",
1796         "pj7",
1797 };
1798
1799 static const char * const hda_groups[] = {
1800         "dap1_fs_pn0",
1801         "dap1_din_pn1",
1802         "dap1_dout_pn2",
1803         "dap1_sclk_pn3",
1804         "dap2_fs_pa2",
1805         "dap2_sclk_pa3",
1806         "dap2_din_pa4",
1807         "dap2_dout_pa5",
1808 };
1809
1810 static const char * const hsi_groups[] = {
1811         "ulpi_data0_po1",
1812         "ulpi_data1_po2",
1813         "ulpi_data2_po3",
1814         "ulpi_data3_po4",
1815         "ulpi_data4_po5",
1816         "ulpi_data5_po6",
1817         "ulpi_data6_po7",
1818         "ulpi_data7_po0",
1819 };
1820
1821 static const char * const i2c1_groups[] = {
1822         "gen1_i2c_scl_pc4",
1823         "gen1_i2c_sda_pc5",
1824         "gpio_w2_aud_pw2",
1825         "gpio_w3_aud_pw3",
1826 };
1827
1828 static const char * const i2c2_groups[] = {
1829         "gen2_i2c_scl_pt5",
1830         "gen2_i2c_sda_pt6",
1831 };
1832
1833 static const char * const i2c3_groups[] = {
1834         "spdif_in_pk6",
1835         "spdif_out_pk5",
1836         "cam_i2c_scl_pbb1",
1837         "cam_i2c_sda_pbb2",
1838 };
1839
1840 static const char * const i2c4_groups[] = {
1841         "ddc_scl_pv4",
1842         "ddc_sda_pv5",
1843 };
1844
1845 static const char * const i2cpwr_groups[] = {
1846         "pwr_i2c_scl_pz6",
1847         "pwr_i2c_sda_pz7",
1848 };
1849
1850 static const char * const i2s0_groups[] = {
1851         "dap1_fs_pn0",
1852         "dap1_din_pn1",
1853         "dap1_dout_pn2",
1854         "dap1_sclk_pn3",
1855 };
1856
1857 static const char * const i2s1_groups[] = {
1858         "dap2_fs_pa2",
1859         "dap2_sclk_pa3",
1860         "dap2_din_pa4",
1861         "dap2_dout_pa5",
1862 };
1863
1864 static const char * const i2s2_groups[] = {
1865         "dap3_fs_pp0",
1866         "dap3_din_pp1",
1867         "dap3_dout_pp2",
1868         "dap3_sclk_pp3",
1869 };
1870
1871 static const char * const i2s3_groups[] = {
1872         "dap4_fs_pp4",
1873         "dap4_din_pp5",
1874         "dap4_dout_pp6",
1875         "dap4_sclk_pp7",
1876 };
1877
1878 static const char * const i2s4_groups[] = {
1879         "pcc1",
1880         "pbb6",
1881         "pbb7",
1882         "pcc2",
1883 };
1884
1885 static const char * const irda_groups[] = {
1886         "uart2_rxd_pc3",
1887         "uart2_txd_pc2",
1888         "kb_row11_ps3",
1889         "kb_row12_ps4",
1890 };
1891
1892 static const char * const kbc_groups[] = {
1893         "kb_row0_pr0",
1894         "kb_row1_pr1",
1895         "kb_row2_pr2",
1896         "kb_row3_pr3",
1897         "kb_row4_pr4",
1898         "kb_row5_pr5",
1899         "kb_row6_pr6",
1900         "kb_row7_pr7",
1901         "kb_row8_ps0",
1902         "kb_row9_ps1",
1903         "kb_row10_ps2",
1904         "kb_row11_ps3",
1905         "kb_row12_ps4",
1906         "kb_row13_ps5",
1907         "kb_row14_ps6",
1908         "kb_row15_ps7",
1909         "kb_row16_pt0",
1910         "kb_row17_pt1",
1911
1912         "kb_col0_pq0",
1913         "kb_col1_pq1",
1914         "kb_col2_pq2",
1915         "kb_col3_pq3",
1916         "kb_col4_pq4",
1917         "kb_col5_pq5",
1918         "kb_col6_pq6",
1919         "kb_col7_pq7",
1920 };
1921
1922 static const char * const owr_groups[] = {
1923         "pu0",
1924         "kb_col4_pq4",
1925         "owr",
1926         "sdmmc3_cd_n_pv2",
1927 };
1928
1929 static const char * const pmi_groups[] = {
1930         "pwr_int_n",
1931 };
1932
1933 static const char * const pwm0_groups[] = {
1934         "sdmmc1_dat2_py5",
1935         "uart3_rts_n_pc0",
1936         "pu3",
1937         "ph0",
1938         "sdmmc3_dat3_pb4",
1939 };
1940
1941 static const char * const pwm1_groups[] = {
1942         "sdmmc1_dat1_py6",
1943         "pu4",
1944         "ph1",
1945         "sdmmc3_dat2_pb5",
1946 };
1947
1948 static const char * const pwm2_groups[] = {
1949         "pu5",
1950         "ph2",
1951         "kb_col3_pq3",
1952         "sdmmc3_dat1_pb6",
1953 };
1954
1955 static const char * const pwm3_groups[] = {
1956         "pu6",
1957         "ph3",
1958         "sdmmc3_cmd_pa7",
1959 };
1960
1961 static const char * const pwron_groups[] = {
1962         "core_pwr_req",
1963 };
1964
1965 static const char * const reset_out_n_groups[] = {
1966         "reset_out_n",
1967 };
1968
1969 static const char * const rsvd1_groups[] = {
1970         "pv0",
1971         "pv1",
1972
1973         "hdmi_int_pn7",
1974         "pu1",
1975         "pu2",
1976         "pc7",
1977         "pi7",
1978         "pk0",
1979         "pj0",
1980         "pj2",
1981         "pk2",
1982         "pi3",
1983         "pi6",
1984
1985         "pg0",
1986         "pg1",
1987         "pg2",
1988         "pg3",
1989         "pg4",
1990         "pg5",
1991         "pg6",
1992         "pg7",
1993
1994         "pi0",
1995         "pi1",
1996
1997         "gpio_x7_aud_px7",
1998
1999         "reset_out_n",
2000 };
2001
2002 static const char * const rsvd2_groups[] = {
2003         "pv0",
2004         "pv1",
2005
2006         "sdmmc1_dat0_py7",
2007         "clk2_out_pw5",
2008         "clk2_req_pcc5",
2009         "hdmi_int_pn7",
2010         "ddc_scl_pv4",
2011         "ddc_sda_pv5",
2012
2013         "uart3_txd_pw6",
2014         "uart3_rxd_pw7",
2015
2016         "gen1_i2c_scl_pc4",
2017         "gen1_i2c_sda_pc5",
2018
2019         "clk2_out_pee0",
2020         "clk2_req_pee1",
2021         "pc7",
2022         "pi5",
2023         "pj0",
2024         "pj2",
2025
2026         "pk4",
2027         "pk2",
2028         "pi3",
2029         "pi6",
2030         "pg0",
2031         "pg1",
2032         "pg5",
2033         "pg6",
2034         "pg7",
2035
2036         "ph4",
2037         "ph5",
2038         "pj7",
2039         "pb0",
2040         "pb1",
2041         "pk7",
2042         "pi0",
2043         "pi1",
2044
2045         "gen2_i2c_scl_pt5",
2046         "gen2_i2c_sda_pt6",
2047         "sdmmc4_clk_pcc4",
2048         "sdmmc4_cmd_pt7",
2049         "sdmmc4_dat7_paa7",
2050         "pcc1",
2051         "pbb6",
2052         "pbb7",
2053         "pcc2",
2054         "jtag_rtck",
2055
2056         "pwr_i2c_scl_pz6",
2057         "pwr_i2c_sda_pz7",
2058
2059         "kb_row0_pr0",
2060         "kb_row1_pr1",
2061         "kb_row2_pr2",
2062         "kb_row7_pr7",
2063         "kb_row8_ps0",
2064         "kb_row9_ps1",
2065         "kb_row10_ps2",
2066         "kb_row11_ps3",
2067         "kb_row12_ps4",
2068         "kb_row13_ps5",
2069         "kb_row14_ps6",
2070
2071         "kb_col0_pq0",
2072         "kb_col1_pq1",
2073         "kb_col2_pq2",
2074         "kb_col5_pq5",
2075         "kb_col6_pq6",
2076         "kb_col7_pq7",
2077
2078         "core_pwr_req",
2079         "cpu_pwr_req",
2080         "pwr_int_n",
2081         "clk_32k_in",
2082         "owr",
2083
2084         "spdif_in_pk6",
2085         "spdif_out_pk5",
2086         "gpio_x1_aud_px1",
2087
2088         "sdmmc3_clk_pa6",
2089         "sdmmc3_dat0_pb7",
2090
2091         "pex_l0_rst_n_pdd1",
2092         "pex_l0_clkreq_n_pdd2",
2093         "pex_wake_n_pdd3",
2094         "pex_l1_rst_n_pdd5",
2095         "pex_l1_clkreq_n_pdd6",
2096         "hdmi_cec_pee3",
2097
2098         "gpio_w2_aud_pw2",
2099         "usb_vbus_en0_pn4",
2100         "usb_vbus_en1_pn5",
2101         "sdmmc3_clk_lb_out_pee4",
2102         "sdmmc3_clk_lb_in_pee5",
2103         "gmi_clk_lb",
2104         "reset_out_n",
2105         "kb_row16_pt0",
2106         "kb_row17_pt1",
2107         "dp_hpd_pff0",
2108         "usb_vbus_en2_pff1",
2109         "pff2",
2110 };
2111
2112 static const char * const rsvd3_groups[] = {
2113         "dap3_sclk_pp3",
2114         "pv0",
2115         "pv1",
2116         "sdmmc1_clk_pz0",
2117         "clk2_out_pw5",
2118         "clk2_req_pcc5",
2119         "hdmi_int_pn7",
2120
2121         "ddc_scl_pv4",
2122         "ddc_sda_pv5",
2123
2124         "pu6",
2125
2126         "gen1_i2c_scl_pc4",
2127         "gen1_i2c_sda_pc5",
2128
2129         "dap4_din_pp5",
2130         "dap4_sclk_pp7",
2131
2132         "clk3_out_pee0",
2133         "clk3_req_pee1",
2134
2135         "sdmmc4_dat5_paa5",
2136         "gpio_pcc1",
2137         "cam_i2c_scl_pbb1",
2138         "cam_i2c_sda_pbb2",
2139         "pbb5",
2140         "pbb7",
2141         "jtag_rtck",
2142         "pwr_i2c_scl_pz6",
2143         "pwr_i2c_sda_pz7",
2144
2145         "kb_row0_pr0",
2146         "kb_row1_pr1",
2147         "kb_row2_pr2",
2148         "kb_row4_pr4",
2149         "kb_row5_pr5",
2150         "kb_row9_ps1",
2151         "kb_row10_ps2",
2152         "kb_row11_ps3",
2153         "kb_row12_ps4",
2154         "kb_row15_ps7",
2155
2156         "clk_32k_out_pa0",
2157         "core_pwr_req",
2158         "cpu_pwr_req",
2159         "pwr_int_n",
2160         "clk_32k_in",
2161         "owr",
2162
2163         "dap_mclk1_pw4",
2164         "spdif_in_pk6",
2165         "spdif_out_pk5",
2166         "sdmmc3_clk_pa6",
2167         "sdmmc3_dat0_pb7",
2168
2169         "pex_l0_rst_n_pdd1",
2170         "pex_l0_clkreq_n_pdd2",
2171         "pex_wake_n_pdd3",
2172         "pex_l1_rst_n_pdd5",
2173         "pex_l1_clkreq_n_pdd6",
2174         "hdmi_cec_pee3",
2175
2176         "sdmmc3_cd_n_pv2",
2177         "usb_vbus_en0_pn4",
2178         "usb_vbus_en1_pn5",
2179         "sdmmc3_clk_lb_out_pee4",
2180         "sdmmc3_clk_lb_in_pee5",
2181         "reset_out_n",
2182         "kb_row16_pt0",
2183         "kb_row17_pt1",
2184         "dp_hpd_pff0",
2185         "usb_vbus_en2_pff1",
2186         "pff2",
2187 };
2188
2189 static const char * const rsvd4_groups[] = {
2190         "dap3_dout_pp2",
2191         "pv0",
2192         "pv1",
2193         "sdmmc1_clk_pz0",
2194
2195         "clk2_out_pw5",
2196         "clk2_req_pcc5",
2197         "hdmi_int_pn7",
2198         "ddc_scl_pv4",
2199         "ddc_sda_pv5",
2200
2201         "uart2_rts_n_pj6",
2202         "uart2_cts_n_pj5",
2203         "uart3_txd_pw6",
2204         "uart3_rxd_pw7",
2205
2206         "pu0",
2207         "pu1",
2208         "pu2",
2209
2210         "gen1_i2c_scl_pc4",
2211         "gen1_i2c_sda_pc5",
2212
2213         "dap4_fs_pp4",
2214         "dap4_dout_pp6",
2215         "dap4_din_pp5",
2216         "dap4_sclk_pp7",
2217
2218         "clk3_out_pee0",
2219         "clk3_req_pee1",
2220
2221         "pi5",
2222         "pk1",
2223         "pk2",
2224         "pg0",
2225         "pg1",
2226         "pg2",
2227         "pg3",
2228         "ph4",
2229         "ph5",
2230         "pb0",
2231         "pb1",
2232         "pk7",
2233         "pi0",
2234         "pi1",
2235         "pi2",
2236
2237         "gen2_i2c_scl_pt5",
2238         "gen2_i2c_sda_pt6",
2239
2240         "sdmmc4_cmd_pt7",
2241         "sdmmc4_dat0_paa0",
2242         "sdmmc4_dat1_paa1",
2243         "sdmmc4_dat2_paa2",
2244         "sdmmc4_dat3_paa3",
2245         "sdmmc4_dat4_paa4",
2246         "sdmmc4_dat5_paa5",
2247         "sdmmc4_dat6_paa6",
2248         "sdmmc4_dat7_paa7",
2249
2250         "jtag_rtck",
2251         "pwr_i2c_scl_pz6",
2252         "pwr_i2c_sda_pz7",
2253
2254         "kb_row0_pr0",
2255         "kb_row1_pr1",
2256         "kb_row2_pr2",
2257         "kb_row13_ps5",
2258         "kb_row14_ps6",
2259         "kb_row15_ps7",
2260
2261         "kb_col0_pq0",
2262         "kb_col1_pq1",
2263         "kb_col2_pq2",
2264         "kb_col5_pq5",
2265
2266         "clk_32k_out_pa0",
2267         "core_pwr_req",
2268         "cpu_pwr_req",
2269         "pwr_int_n",
2270         "clk_32k_in",
2271         "owr",
2272
2273         "dap1_fs_pn0",
2274         "dap1_din_pn1",
2275         "dap1_sclk_pn3",
2276         "dap_mclk1_req_pee2",
2277         "dap_mclk1_pw5",
2278
2279         "dap2_fs_pa2",
2280         "dap2_din_pa4",
2281         "dap2_dout_pa5",
2282         "dap2_sclk_pa3",
2283
2284         "dvfs_pwm_px0",
2285         "dvfs_clk_px2",
2286         "gpio_x1_aud_px1",
2287         "gpio_x3_aud_px3",
2288
2289         "gpio_x5_aud_px5",
2290         "gpio_x7_aud_px7",
2291
2292         "pex_l0_rst_n_pdd1",
2293         "pex_l0_clkreq_n_pdd2",
2294         "pex_wake_n_pdd3",
2295         "pex_l1_rst_n_pdd5",
2296         "pex_l1_clkreq_n_pdd6",
2297         "hdmi_cec_pee3",
2298
2299         "sdmmc3_cd_n_pv2",
2300         "usb_vbus_en0_pn4",
2301         "usb_vbus_en1_pn5",
2302         "sdmmc3_clk_lb_out_pee4",
2303         "sdmmc3_clk_lb_in_pee5",
2304         "gmi_clk_lb",
2305
2306         "dp_hpd_pff0",
2307         "usb_vbus_en2_pff1",
2308         "pff2",
2309 };
2310
2311 static const char * const sdmmc1_groups[] = {
2312         "sdmmc1_clk_pz0",
2313         "sdmmc1_cmd_pz1",
2314         "sdmmc1_dat3_py4",
2315         "sdmmc1_dat2_py5",
2316         "sdmmc1_dat1_py6",
2317         "sdmmc1_dat0_py7",
2318         "clk2_out_pw5",
2319         "clk2_req_pcc",
2320         "uart3_cts_n_pa1",
2321         "sdmmc1_wp_n_pv3",
2322 };
2323
2324 static const char * const sdmmc2_groups[] = {
2325         "pi5",
2326         "pk1",
2327         "pk3",
2328         "pk4",
2329         "pi6",
2330         "ph4",
2331         "ph5",
2332         "ph6",
2333         "ph7",
2334         "pi2",
2335         "cam_mclk_pcc0",
2336         "pcc1",
2337         "pbb0",
2338         "cam_i2c_scl_pbb1",
2339         "cam_i2c_sda_pbb2",
2340         "pbb3",
2341         "pbb4",
2342         "pbb5",
2343         "pbb6",
2344         "pbb7",
2345         "pcc2",
2346         "gmi_clk_lb",
2347 };
2348
2349 static const char * const sdmmc3_groups[] = {
2350         "pk0",
2351         "pcc2",
2352
2353         "kb_col4_pq4",
2354         "kb_col5_pq5",
2355
2356         "sdmmc3_clk_pa6",
2357         "sdmmc3_cmd_pa7",
2358         "sdmmc3_dat0_pb7",
2359         "sdmmc3_dat1_pb6",
2360         "sdmmc3_dat2_pb5",
2361         "sdmmc3_dat3_pb4",
2362
2363         "sdmmc3_cd_n_pv2",
2364         "sdmmc3_clk_lb_in_pee5",
2365         "sdmmc3_clk_lb_out_pee4",
2366 };
2367
2368 static const char * const sdmmc4_groups[] = {
2369         "sdmmc4_clk_pcc4",
2370         "sdmmc4_cmd_pt7",
2371         "sdmmc4_dat0_paa0",
2372         "sdmmc4_dat1_paa1",
2373         "sdmmc4_dat2_paa2",
2374         "sdmmc4_dat3_paa3",
2375         "sdmmc4_dat4_paa4",
2376         "sdmmc4_dat5_paa5",
2377         "sdmmc4_dat6_paa6",
2378         "sdmmc4_dat7_paa7",
2379 };
2380
2381 static const char * const soc_groups[] = {
2382         "pk0",
2383         "pj2",
2384         "kb_row15_ps7",
2385         "clk_32k_out_pa0",
2386 };
2387
2388 static const char * const spdif_groups[] = {
2389         "sdmmc1_cmd_pz1",
2390         "sdmmc1_dat3_py4",
2391         "uart2_rxd_pc3",
2392         "uart2_txd_pc2",
2393         "spdif_in_pk6",
2394         "spdif_out_pk5",
2395 };
2396
2397 static const char * const spi1_groups[] = {
2398         "ulpi_clk_py0",
2399         "ulpi_dir_py1",
2400         "ulpi_nxt_py2",
2401         "ulpi_stp_py3",
2402         "gpio_x3_aud_px3",
2403         "gpio_x4_aud_px4",
2404         "gpio_x5_aud_px5",
2405         "gpio_x6_aud_px6",
2406         "gpio_x7_aud_px7",
2407         "gpio_w3_aud_pw3",
2408 };
2409
2410 static const char * const spi2_groups[] = {
2411         "ulpi_data4_po5",
2412         "ulpi_data5_po6",
2413         "ulpi_data6_po7",
2414         "ulpi_data7_po0",
2415
2416         "kb_row13_ps5",
2417         "kb_row14_ps6",
2418         "kb_row15_ps7",
2419         "kb_col0_pq0",
2420         "kb_col1_pq1",
2421         "kb_col2_pq2",
2422         "kb_col6_pq6",
2423         "kb_col7_pq7",
2424         "gpio_x4_aud_px4",
2425         "gpio_x5_aud_px5",
2426         "gpio_x6_aud_px6",
2427         "gpio_x7_aud_px7",
2428         "gpio_w2_aud_pw2",
2429         "gpio_w3_aud_pw3",
2430 };
2431
2432 static const char * const spi3_groups[] = {
2433         "ulpi_data0_po1",
2434         "ulpi_data1_po2",
2435         "ulpi_data2_po3",
2436         "ulpi_data3_po4",
2437         "sdmmc4_dat0_paa0",
2438         "sdmmc4_dat1_paa1",
2439         "sdmmc4_dat2_paa2",
2440         "sdmmc4_dat3_paa3",
2441         "sdmmc4_dat4_paa4",
2442         "sdmmc4_dat5_paa5",
2443         "sdmmc4_dat6_paa6",
2444         "sdmmc3_clk_pa6",
2445         "sdmmc3_cmd_pa7",
2446         "sdmmc3_dat0_pb7",
2447         "sdmmc3_dat1_pb6",
2448         "sdmmc3_dat2_pb5",
2449         "sdmmc3_dat3_pb4",
2450 };
2451
2452 static const char * const spi4_groups[] = {
2453         "sdmmc1_cmd_pz1",
2454         "sdmmc1_dat3_py4",
2455         "sdmmc1_dat2_py5",
2456         "sdmmc1_dat1_py6",
2457         "sdmmc1_dat0_py7",
2458
2459         "uart2_rxd_pc3",
2460         "uart2_txd_pc2",
2461         "uart2_rts_n_pj6",
2462         "uart2_cts_n_pj5",
2463         "uart3_txd_pw6",
2464         "uart3_rxd_pw7",
2465
2466         "pi3",
2467         "pg4",
2468         "pg5",
2469         "pg6",
2470         "pg7",
2471         "ph3",
2472         "pi4",
2473         "sdmmc1_wp_n_pv3",
2474 };
2475
2476 static const char * const spi5_groups[] = {
2477         "ulpi_clk_py0",
2478         "ulpi_dir_py1",
2479         "ulpi_nxt_py2",
2480         "ulpi_stp_py3",
2481         "dap3_fs_pp0",
2482         "dap3_din_pp1",
2483         "dap3_dout_pp2",
2484         "dap3_sclk_pp3",
2485 };
2486
2487 static const char * const spi6_groups[] = {
2488         "dvfs_pwm_px0",
2489         "gpio_x1_aud_px1",
2490         "gpio_x3_aud_px3",
2491         "dvfs_clk_px2",
2492         "gpio_x6_aud_px6",
2493         "gpio_w2_aud_pw2",
2494         "gpio_w3_aud_pw3",
2495 };
2496
2497 static const char * const trace_groups[] = {
2498         "pi2",
2499         "pi4",
2500         "pi7",
2501         "ph0",
2502         "ph6",
2503         "ph7",
2504         "pg2",
2505         "pg3",
2506         "pk1",
2507         "pk3",
2508 };
2509
2510 static const char * const uarta_groups[] = {
2511         "ulpi_data0_po1",
2512         "ulpi_data1_po2",
2513         "ulpi_data2_po3",
2514         "ulpi_data3_po4",
2515         "ulpi_data4_po5",
2516         "ulpi_data5_po6",
2517         "ulpi_data6_po7",
2518         "ulpi_data7_po0",
2519
2520         "sdmmc1_cmd_pz1",
2521         "sdmmc1_dat3_py4",
2522         "sdmmc1_dat2_py5",
2523         "sdmmc1_dat1_py6",
2524         "sdmmc1_dat0_py7",
2525
2526
2527         "uart2_rxd_pc3",
2528         "uart2_txd_pc2",
2529         "uart2_rts_n_pj6",
2530         "uart2_cts_n_pj5",
2531
2532         "pu0",
2533         "pu1",
2534         "pu2",
2535         "pu3",
2536         "pu4",
2537         "pu5",
2538         "pu6",
2539
2540         "kb_row7_pr7",
2541         "kb_row8_ps0",
2542         "kb_row9_ps1",
2543         "kb_row10_ps2",
2544         "kb_col3_pq3",
2545         "kb_col4_pq4",
2546
2547         "sdmmc3_cmd_pa7",
2548         "sdmmc3_dat1_pb6",
2549         "sdmmc1_wp_n_pv3",
2550
2551 };
2552
2553 static const char * const uartb_groups[] = {
2554         "uart2_rts_n_pj6",
2555         "uart2_cts_n_pj5",
2556 };
2557
2558 static const char * const uartc_groups[] = {
2559         "uart3_txd_pw6",
2560         "uart3_rxd_pw7",
2561         "uart3_cts_n_pa1",
2562         "uart3_rts_n_pc0",
2563         "kb_row16_pt0",
2564         "kn_row17_pt1",
2565 };
2566
2567 static const char * const uartd_groups[] = {
2568         "ulpi_clk_py0",
2569         "ulpi_dir_py1",
2570         "ulpi_nxt_py2",
2571         "ulpi_stp_py3",
2572         "pj7",
2573         "pb0",
2574         "pb1",
2575         "pk7",
2576         "kb_col6_pq6",
2577         "kb_col7_pq7",
2578 };
2579
2580 static const char * const ulpi_groups[] = {
2581         "ulpi_data0_po1",
2582         "ulpi_data1_po2",
2583         "ulpi_data2_po3",
2584         "ulpi_data3_po4",
2585         "ulpi_data4_po5",
2586         "ulpi_data5_po6",
2587         "ulpi_data6_po7",
2588         "ulpi_data7_po0",
2589         "ulpi_clk_py0",
2590         "ulpi_dir_py1",
2591         "ulpi_nxt_py2",
2592         "ulpi_stp_py3",
2593 };
2594
2595 static const char * const usb_groups[] = {
2596         "pj0",
2597         "usb_vbus_en0_pn4",
2598         "usb_vbus_en1_pn5",
2599         "usb_vbus_en2_pff1",
2600 };
2601
2602 static const char * const vgp1_groups[] = {
2603         "cam_i2c_scl_pbb1",
2604 };
2605
2606 static const char * const vgp2_groups[] = {
2607         "cam_i2c_sda_pbb2",
2608 };
2609
2610 static const char * const vgp3_groups[] = {
2611         "pbb3",
2612 };
2613
2614 static const char * const vgp4_groups[] = {
2615         "pbb4",
2616 };
2617
2618 static const char * const vgp5_groups[] = {
2619         "pbb5",
2620 };
2621
2622 static const char * const vgp6_groups[] = {
2623         "pbb0",
2624 };
2625
2626 static const char * const vi_groups[] = {
2627         "cam_mclk_pcc0",
2628 };
2629
2630 static const char * const vi_alt1_groups[] = {
2631         "cam_mclk_pcc0",
2632 };
2633
2634 static const char * const vi_alt3_groups[] = {
2635         "cam_mclk_pcc0",
2636 };
2637
2638 static const char * const vimclk2_groups[] = {
2639         "pbb0",
2640 };
2641
2642 static const char * const vimclk2_alt_groups[] = {
2643         "pbb0",
2644 };
2645
2646 static const char * const sata_groups[] = {
2647         "dap_mclk1_req_pee2",
2648         "dap1_dout_pn2",
2649         "pff2",
2650 };
2651
2652 static const char * const ccla_groups[] = {
2653         "pk3",
2654 };
2655
2656 static const char * const rtck_groups[] = {
2657         "jtag_rtck",
2658 };
2659
2660 static const char * const sys_groups[] = {
2661         "kb_row3_pr3",
2662 };
2663
2664 static const char * const pe0_groups[] = {
2665         "pex_l0_rst_n_pdd1",
2666         "pex_l0_clkreq_n_pdd2",
2667 };
2668
2669 static const char * const pe_groups[] = {
2670         "pex_wake_n_pdd3",
2671 };
2672
2673 static const char * const pe1_groups[] = {
2674         "pex_l1_rst_n_pdd5",
2675         "pex_l1_clkreq_n_pdd6",
2676 };
2677
2678 static const char * const dp_groups[] = {
2679         "dp_hpd_pff0",
2680 };
2681
2682 static const char * const clk_groups[] = {
2683         "clk_32k_in",
2684 };
2685
2686 static const char * const tmds_groups[] = {
2687         "pg4",
2688         "ph1",
2689         "ph2",
2690 };
2691
2692 static const char * const safe_groups[] = {
2693         "ulpi_data0_po1",
2694         "ulpi_data1_po2",
2695         "ulpi_data2_po3",
2696         "ulpi_data3_po4",
2697         "ulpi_data4_po5",
2698         "ulpi_data5_po6",
2699         "ulpi_data6_po7",
2700         "ulpi_data7_po0",
2701         "ulpi_clk_py0",
2702         "ulpi_dir_py1",
2703         "ulpi_nxt_py2",
2704         "ulpi_stp_py3",
2705         "dap3_fs_pp0",
2706         "dap3_din_pp1",
2707         "dap3_dout_pp2",
2708         "dap3_sclk_pp3",
2709         "pv0",
2710         "pv1",
2711         "sdmmc1_clk_pz0",
2712         "sdmmc1_cmd_pz1",
2713         "sdmmc1_dat3_py4",
2714         "sdmmc1_dat2_py5",
2715         "sdmmc1_dat1_py6",
2716         "sdmmc1_dat0_py7",
2717         "clk2_out_pw5",
2718         "clk2_req_pcc5",
2719         "hdmi_int_pn7",
2720         "ddc_scl_pv4",
2721         "ddc_sda_pv5",
2722         "uart2_rxd_pc3",
2723         "uart2_txd_pc2",
2724         "uart2_rts_n_pj6",
2725         "uart2_cts_n_pj5",
2726         "uart3_txd_pw6",
2727         "uart3_rxd_pw7",
2728         "uart3_cts_n_pa1",
2729         "uart3_rts_n_pc0",
2730         "pu0",
2731         "pu1",
2732         "pu2",
2733         "pu3",
2734         "pu4",
2735         "pu5",
2736         "pu6",
2737         "gen1_i2c_scl_pc4",
2738         "gen1_i2c_sda_pc5",
2739         "dap4_fs_pp4",
2740         "dap4_din_pp5",
2741         "dap4_dout_pp6",
2742         "dap4_sclk_pp7",
2743         "clk3_out_pee0",
2744         "clk3_req_pee1",
2745         "pc7",
2746         "pi5",
2747         "pi7",
2748         "pk0",
2749         "pk1",
2750         "pj0",
2751         "pj2",
2752         "pk3",
2753         "pk4",
2754         "pk2",
2755         "pi3",
2756         "pi6",
2757         "pg0",
2758         "pg1",
2759         "pg2",
2760         "pg3",
2761         "pg4",
2762         "pg5",
2763         "pg6",
2764         "pg7",
2765         "ph0",
2766         "ph1",
2767         "ph2",
2768         "ph3",
2769         "ph4",
2770         "ph5",
2771         "ph6",
2772         "ph7",
2773         "pj7",
2774         "pb0",
2775         "pb1",
2776         "pk7",
2777         "pi0",
2778         "pi1",
2779         "pi2",
2780         "pi4",
2781         "gen2_i2c_scl_pt5",
2782         "gen2_i2c_sda_pt6",
2783         "sdmmc4_clk_pcc4",
2784         "sdmmc4_cmd_pt7",
2785         "sdmmc4_dat0_paa0",
2786         "sdmmc4_dat1_paa1",
2787         "sdmmc4_dat2_paa2",
2788         "sdmmc4_dat3_paa3",
2789         "sdmmc4_dat4_paa4",
2790         "sdmmc4_dat5_paa5",
2791         "sdmmc4_dat6_paa6",
2792         "sdmmc4_dat7_paa7",
2793         "cam_mclk_pcc0",
2794         "pcc1",
2795         "pbb0",
2796         "cam_i2c_scl_pbb1",
2797         "cam_i2c_sda_pbb2",
2798         "pbb3",
2799         "pbb4",
2800         "pbb5",
2801         "pbb6",
2802         "pbb7",
2803         "pcc2",
2804         "jtag_rtck",
2805         "pwr_i2c_scl_pz6",
2806         "pwr_i2c_sda_pz7",
2807         "kb_row0_pr0",
2808         "kb_row1_pr1",
2809         "kb_row2_pr2",
2810         "kb_row3_pr3",
2811         "kb_row4_pr4",
2812         "kb_row5_pr5",
2813         "kb_row6_pr6",
2814         "kb_row7_pr7",
2815         "kb_row8_ps0",
2816         "kb_row9_ps1",
2817         "kb_row10_ps2",
2818         "kb_row11_ps3",
2819         "kb_row12_ps4",
2820         "kb_row13_ps5",
2821         "kb_row14_ps6",
2822         "kb_row15_ps7",
2823         "kb_col0_pq0",
2824         "kb_col1_pq1",
2825         "kb_col2_pq2",
2826         "kb_col3_pq3",
2827         "kb_col4_pq4",
2828         "kb_col5_pq5",
2829         "kb_col6_pq6",
2830         "kb_col7_pq7",
2831         "clk_32k_out_pa0",
2832         "core_pwr_req",
2833         "cpu_pwr_req",
2834         "pwr_int_n",
2835         "clk_32k_in",
2836         "owr",
2837         "dap1_fs_pn0",
2838         "dap1_din_pn1",
2839         "dap1_dout_pn2",
2840         "dap1_sclk_pn3",
2841         "dap_mclk1_req_pee2",
2842         "dap_mclk1_pw4",
2843         "spdif_in_pk6",
2844         "spdif_out_pk5",
2845         "dap2_fs_pa2",
2846         "dap2_din_pa4",
2847         "dap2_dout_pa5",
2848         "dap2_sclk_pa3",
2849         "dvfs_pwm_px0",
2850         "gpio_x1_aud_px1",
2851         "gpio_x3_aud_px3",
2852         "dvfs_clk_px2",
2853         "gpio_x4_aud_px4",
2854         "gpio_x5_aud_px5",
2855         "gpio_x6_aud_px6",
2856         "gpio_x7_aud_px7",
2857         "sdmmc3_clk_pa6",
2858         "sdmmc3_cmd_pa7",
2859         "sdmmc3_dat0_pb7",
2860         "sdmmc3_dat1_pb6",
2861         "sdmmc3_dat2_pb5",
2862         "sdmmc3_dat3_pb4",
2863         "pex_l0_rst_n_pdd1",
2864         "pex_l0_clkreq_n_pdd2",
2865         "pex_wake_n_pdd3",
2866         "pex_l1_rst_n_pdd5",
2867         "pex_l1_clkreq_n_pdd6",
2868         "hdmi_cec_pee3",
2869         "sdmmc1_wp_n_pv3",
2870         "sdmmc3_cd_n_pv2",
2871         "gpio_w2_aud_pw2",
2872         "gpio_w3_aud_pw3",
2873         "usb_vbus_en0_pn4",
2874         "usb_vbus_en1_pn5",
2875         "sdmmc3_clk_lb_out_pee4",
2876         "sdmmc3_clk_lb_in_pee5",
2877         "gmi_clk_lb",
2878         "reset_out_n",
2879         "kb_row16_pt0",
2880         "kb_row17_pt1",
2881         "usb_vbus_en2_pff1",
2882         "pff2",
2883         "dp_hpd_pff0",
2884 };
2885
2886 #define FUNCTION(fname)                                 \
2887         {                                               \
2888                 .name = #fname,                         \
2889                 .groups = fname##_groups,               \
2890                 .ngroups = ARRAY_SIZE(fname##_groups),  \
2891         }
2892
2893 static const struct tegra_function tegra124_functions[] = {
2894         FUNCTION(safe),
2895         FUNCTION(blink),
2896         FUNCTION(cec),
2897         FUNCTION(cldvfs),
2898         FUNCTION(clk12),
2899         FUNCTION(cpu),
2900         FUNCTION(dap),
2901         FUNCTION(dap1),
2902         FUNCTION(dap2),
2903         FUNCTION(dev3),
2904         FUNCTION(displaya),
2905         FUNCTION(displaya_alt),
2906         FUNCTION(displayb),
2907         FUNCTION(dtv),
2908         FUNCTION(extperiph1),
2909         FUNCTION(extperiph2),
2910         FUNCTION(extperiph3),
2911         FUNCTION(gmi),
2912         FUNCTION(gmi_alt),
2913         FUNCTION(hda),
2914         FUNCTION(hsi),
2915         FUNCTION(i2c1),
2916         FUNCTION(i2c2),
2917         FUNCTION(i2c3),
2918         FUNCTION(i2c4),
2919         FUNCTION(i2cpwr),
2920         FUNCTION(i2s0),
2921         FUNCTION(i2s1),
2922         FUNCTION(i2s2),
2923         FUNCTION(i2s3),
2924         FUNCTION(i2s4),
2925         FUNCTION(irda),
2926         FUNCTION(kbc),
2927         FUNCTION(owr),
2928         FUNCTION(pmi),
2929         FUNCTION(pwm0),
2930         FUNCTION(pwm1),
2931         FUNCTION(pwm2),
2932         FUNCTION(pwm3),
2933         FUNCTION(pwron),
2934         FUNCTION(reset_out_n),
2935         FUNCTION(rsvd1),
2936         FUNCTION(rsvd2),
2937         FUNCTION(rsvd3),
2938         FUNCTION(rsvd4),
2939         FUNCTION(sdmmc1),
2940         FUNCTION(sdmmc2),
2941         FUNCTION(sdmmc3),
2942         FUNCTION(sdmmc4),
2943         FUNCTION(soc),
2944         FUNCTION(spdif),
2945         FUNCTION(spi1),
2946         FUNCTION(spi2),
2947         FUNCTION(spi3),
2948         FUNCTION(spi4),
2949         FUNCTION(spi5),
2950         FUNCTION(spi6),
2951         FUNCTION(trace),
2952         FUNCTION(uarta),
2953         FUNCTION(uartb),
2954         FUNCTION(uartc),
2955         FUNCTION(uartd),
2956         FUNCTION(ulpi),
2957         FUNCTION(usb),
2958         FUNCTION(vgp1),
2959         FUNCTION(vgp2),
2960         FUNCTION(vgp3),
2961         FUNCTION(vgp4),
2962         FUNCTION(vgp5),
2963         FUNCTION(vgp6),
2964         FUNCTION(vi),
2965         FUNCTION(vi_alt1),
2966         FUNCTION(vi_alt3),
2967         FUNCTION(vimclk2),
2968         FUNCTION(vimclk2_alt),
2969         FUNCTION(sata),
2970         FUNCTION(ccla),
2971         FUNCTION(pe0),
2972         FUNCTION(pe),
2973         FUNCTION(pe1),
2974         FUNCTION(dp),
2975         FUNCTION(rtck),
2976         FUNCTION(sys),
2977         FUNCTION(clk),
2978         FUNCTION(tmds),
2979 };
2980
2981 #define DRV_PINGROUP_REG_A      0x868   /* bank 0 */
2982 #define PINGROUP_REG_A          0x3000  /* bank 1 */
2983
2984 #define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A)
2985 #define PINGROUP_REG_N(r) -1
2986
2987 #define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel)  \
2988         {                                                       \
2989                 .name = #pg_name,                               \
2990                 .pins = pg_name##_pins,                         \
2991                 .npins = ARRAY_SIZE(pg_name##_pins),            \
2992                 .funcs = {                                      \
2993                         TEGRA_MUX_DT_ ## f0,                    \
2994                         TEGRA_MUX_DT_ ## f1,                    \
2995                         TEGRA_MUX_DT_ ## f2,                    \
2996                         TEGRA_MUX_DT_ ## f3,                    \
2997                 },                                              \
2998                 .func_safe = TEGRA_MUX_DT_ ## f_safe,           \
2999                 .funcs_non_dt = {                               \
3000                         TEGRA_MUX_ ## f0,                       \
3001                         TEGRA_MUX_ ## f1,                       \
3002                         TEGRA_MUX_ ## f2,                       \
3003                         TEGRA_MUX_ ## f3,                       \
3004                 },                                              \
3005                 .func_safe_non_dt = TEGRA_MUX_## f_safe,        \
3006                 .mux_reg = PINGROUP_REG_Y(r),                   \
3007                 .mux_bank = 1,                                  \
3008                 .mux_bit = 0,                                   \
3009                 .pupd_reg = PINGROUP_REG_Y(r),                  \
3010                 .pupd_bank = 1,                                 \
3011                 .pupd_bit = 2,                                  \
3012                 .tri_reg = PINGROUP_REG_Y(r),                   \
3013                 .tri_bank = 1,                                  \
3014                 .tri_bit = 4,                                   \
3015                 .einput_reg = PINGROUP_REG_Y(r),                \
3016                 .einput_bank = 1,                               \
3017                 .einput_bit = 5,                                \
3018                 .odrain_reg = PINGROUP_REG_##od(r),             \
3019                 .odrain_bank = 1,                               \
3020                 .odrain_bit = 6,                                \
3021                 .lock_reg = PINGROUP_REG_Y(r),                  \
3022                 .lock_bank = 1,                                 \
3023                 .lock_bit = 7,                                  \
3024                 .ioreset_reg = PINGROUP_REG_##ior(r),           \
3025                 .ioreset_bank = 1,                              \
3026                 .ioreset_bit = 8,                               \
3027                 .rcv_sel_reg = PINGROUP_REG_##rcv_sel(r),       \
3028                 .rcv_sel_bank = 1,                              \
3029                 .rcv_sel_bit = 9,                               \
3030                 .drv_reg = -1,                                  \
3031                 .drvtype_reg = -1,                              \
3032         }
3033
3034 #define DRV_PINGROUP_DVRTYPE_Y(r) ((r) - DRV_PINGROUP_REG_A)
3035 #define DRV_PINGROUP_DVRTYPE_N(r) -1
3036
3037 #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b,      \
3038                      drvdn_b, drvdn_w, drvup_b, drvup_w,        \
3039                      slwr_b, slwr_w, slwf_b, slwf_w,            \
3040                      drvtype)                                   \
3041         {                                                       \
3042                 .name = "drive_" #pg_name,                      \
3043                 .pins = drive_##pg_name##_pins,                 \
3044                 .npins = ARRAY_SIZE(drive_##pg_name##_pins),    \
3045                 .mux_reg = -1,                                  \
3046                 .pupd_reg = -1,                                 \
3047                 .tri_reg = -1,                                  \
3048                 .einput_reg = -1,                               \
3049                 .odrain_reg = -1,                               \
3050                 .lock_reg = -1,                                 \
3051                 .ioreset_reg = -1,                              \
3052                 .rcv_sel_reg = -1,                              \
3053                 .drv_reg = DRV_PINGROUP_DVRTYPE_Y(r),           \
3054                 .drv_bank = 0,                                  \
3055                 .hsm_bit = hsm_b,                               \
3056                 .schmitt_bit = schmitt_b,                       \
3057                 .lpmd_bit = lpmd_b,                             \
3058                 .drvdn_bit = drvdn_b,                           \
3059                 .drvdn_width = drvdn_w,                         \
3060                 .drvup_bit = drvup_b,                           \
3061                 .drvup_width = drvup_w,                         \
3062                 .slwr_bit = slwr_b,                             \
3063                 .slwr_width = slwr_w,                           \
3064                 .slwf_bit = slwf_b,                             \
3065                 .slwf_width = slwf_w,                           \
3066                 .drvtype_reg = DRV_PINGROUP_DVRTYPE_##drvtype(r),       \
3067                 .drvtype_bank = 0,                              \
3068                 .drvtype_bit = 6,                               \
3069                 .drvtype_width = 2,                             \
3070         }
3071
3072 static const struct tegra_pingroup tegra124_groups[] = {
3073         /*       pg_name,                f0,         f1,         f2,           f3,          safe,     r,      od, ior, rcv_sel */
3074         /* FIXME: Fill in correct data in safe column */
3075         PINGROUP(ulpi_data0_po1,        SPI3,           HSI,            UARTA,          ULPI,           SPI3,           0x3000,  N,  N,  N),
3076         PINGROUP(ulpi_data1_po2,        SPI3,           HSI,            UARTA,          ULPI,           SPI3,           0x3004,  N,  N,  N),
3077         PINGROUP(ulpi_data2_po3,        SPI3,           HSI,            UARTA,          ULPI,           SPI3,           0x3008,  N,  N,  N),
3078         PINGROUP(ulpi_data3_po4,        SPI3,           HSI,            UARTA,          ULPI,           SPI3,           0x300c,  N,  N,  N),
3079         PINGROUP(ulpi_data4_po5,        SPI2,           HSI,            UARTA,          ULPI,           SPI2,           0x3010,  N,  N,  N),
3080         PINGROUP(ulpi_data5_po6,        SPI2,           HSI,            UARTA,          ULPI,           SPI2,           0x3014,  N,  N,  N),
3081         PINGROUP(ulpi_data6_po7,        SPI2,           HSI,            UARTA,          ULPI,           SPI2,           0x3018,  N,  N,  N),
3082         PINGROUP(ulpi_data7_po0,        SPI2,           HSI,            UARTA,          ULPI,           SPI2,           0x301c,  N,  N,  N),
3083         PINGROUP(ulpi_clk_py0,          SPI1,           SPI5,           UARTD,          ULPI,           SPI1,           0x3020,  N,  N,  N),
3084         PINGROUP(ulpi_dir_py1,          SPI1,           SPI5,           UARTD,          ULPI,           SPI1,           0x3024,  N,  N,  N),
3085         PINGROUP(ulpi_nxt_py2,          SPI1,           SPI5,           UARTD,          ULPI,           SPI1,           0x3028,  N,  N,  N),
3086         PINGROUP(ulpi_stp_py3,          SPI1,           SPI5,           UARTD,          ULPI,           SPI1,           0x302c,  N,  N,  N),
3087         PINGROUP(dap3_fs_pp0,           I2S2,           SPI5,           DISPLAYA,       DISPLAYB,       I2S2,           0x3030,  N,  N,  N),
3088         PINGROUP(dap3_din_pp1,          I2S2,           SPI5,           DISPLAYA,       DISPLAYB,       I2S2,           0x3034,  N,  N,  N),
3089         PINGROUP(dap3_dout_pp2,         I2S2,           SPI5,           DISPLAYA,       RSVD4,          I2S2,           0x3038,  N,  N,  N),
3090         PINGROUP(dap3_sclk_pp3,         I2S2,           SPI5,           RSVD3,          DISPLAYB,       I2S2,           0x303c,  N,  N,  N),
3091         PINGROUP(pv0,                   RSVD1,          RSVD2,          RSVD3,          RSVD4,          RSVD1,          0x3040,  N,  N,  N),
3092         PINGROUP(pv1,                   RSVD1,          RSVD2,          RSVD3,          RSVD4,          RSVD1,          0x3044,  N,  N,  N),
3093         PINGROUP(sdmmc1_clk_pz0,        SDMMC1,         CLK12,          RSVD3,          RSVD4,          RSVD3,          0x3048,  N,  N,  N),
3094         PINGROUP(sdmmc1_cmd_pz1,        SDMMC1,         SPDIF,          SPI4,           UARTA,          SDMMC1,         0x304c,  N,  N,  N),
3095         PINGROUP(sdmmc1_dat3_py4,       SDMMC1,         SPDIF,          SPI4,           UARTA,          SDMMC1,         0x3050,  N,  N,  N),
3096         PINGROUP(sdmmc1_dat2_py5,       SDMMC1,         PWM0,           SPI4,           UARTA,          SDMMC1,         0x3054,  N,  N,  N),
3097         PINGROUP(sdmmc1_dat1_py6,       SDMMC1,         PWM1,           SPI4,           UARTA,          SDMMC1,         0x3058,  N,  N,  N),
3098         PINGROUP(sdmmc1_dat0_py7,       SDMMC1,         RSVD2,          SPI4,           UARTA,          SDMMC1,         0x305c,  N,  N,  N),
3099         PINGROUP(clk2_out_pw5,          EXTPERIPH2,     RSVD2,          RSVD3,          RSVD4,          EXTPERIPH2,     0x3068,  N,  N,  N),
3100         PINGROUP(clk2_req_pcc5,         DAP,            RSVD2,          RSVD3,          RSVD4,          DAP,            0x306c,  N,  N,  N),
3101         PINGROUP(hdmi_int_pn7,          RSVD1,          RSVD2,          RSVD3,          RSVD4,          RSVD1,          0x3110,  N,  N,  Y),
3102         PINGROUP(ddc_scl_pv4,           I2C4,           RSVD2,          RSVD3,          RSVD4,          I2C4,           0x3114,  N,  N,  Y),
3103         PINGROUP(ddc_sda_pv5,           I2C4,           RSVD2,          RSVD3,          RSVD4,          I2C4,           0x3118,  N,  N,  Y),
3104         PINGROUP(uart2_rxd_pc3,         IRDA,           SPDIF,          UARTA,          SPI4,           IRDA,           0x3164,  N,  N,  N),
3105         PINGROUP(uart2_txd_pc2,         IRDA,           SPDIF,          UARTA,          SPI4,           IRDA,           0x3168,  N,  N,  N),
3106         PINGROUP(uart2_rts_n_pj6,       UARTA,          UARTB,          GMI,            SPI4,           UARTA,          0x316c,  N,  N,  N),
3107         PINGROUP(uart2_cts_n_pj5,       UARTA,          UARTB,          GMI,            SPI4,           UARTA,          0x3170,  N,  N,  N),
3108         PINGROUP(uart3_txd_pw6,         UARTC,          RSVD2,          GMI,            SPI4,           UARTC,          0x3174,  N,  N,  N),
3109         PINGROUP(uart3_rxd_pw7,         UARTC,          RSVD2,          GMI,            SPI4,           UARTC,          0x3178,  N,  N,  N),
3110         PINGROUP(uart3_cts_n_pa1,       UARTC,          SDMMC1,         DTV,            GMI,            UARTC,          0x317c,  N,  N,  N),
3111         PINGROUP(uart3_rts_n_pc0,       UARTC,          PWM0,           DTV,            GMI,            UARTC,          0x3180,  N,  N,  N),
3112         PINGROUP(pu0,                   OWR,            UARTA,          GMI,            RSVD4,          RSVD4,          0x3184,  N,  N,  N),
3113         PINGROUP(pu1,                   RSVD1,          UARTA,          GMI,            RSVD4,          RSVD4,          0x3188,  N,  N,  N),
3114         PINGROUP(pu2,                   RSVD1,          UARTA,          GMI,            RSVD4,          RSVD4,          0x318c,  N,  N,  N),
3115         PINGROUP(pu3,                   PWM0,           UARTA,          GMI,            DISPLAYB,       PWM0,           0x3190,  N,  N,  N),
3116         PINGROUP(pu4,                   PWM1,           UARTA,          GMI,            DISPLAYB,       PWM1,           0x3194,  N,  N,  N),
3117         PINGROUP(pu5,                   PWM2,           UARTA,          GMI,            DISPLAYB,       PWM2,           0x3198,  N,  N,  N),
3118         PINGROUP(pu6,                   PWM3,           UARTA,          RSVD3,          GMI,            RSVD3,          0x319c,  N,  N,  N),
3119         PINGROUP(gen1_i2c_scl_pc4,      I2C1,           RSVD2,          RSVD3,          RSVD4,          I2C1,           0x31a0,  Y,  N,  N),
3120         PINGROUP(gen1_i2c_sda_pc5,      I2C1,           RSVD2,          RSVD3,          RSVD4,          I2C1,           0x31a4,  Y,  N,  N),
3121         PINGROUP(dap4_fs_pp4,           I2S3,           GMI,            DTV,            RSVD4,          I2S3,           0x31a8,  N,  N,  N),
3122         PINGROUP(dap4_din_pp5,          I2S3,           GMI,            RSVD3,          RSVD4,          I2S3,           0x31ac,  N,  N,  N),
3123         PINGROUP(dap4_dout_pp6,         I2S3,           GMI,            DTV,            RSVD4,          I2S3,           0x31b0,  N,  N,  N),
3124         PINGROUP(dap4_sclk_pp7,         I2S3,           GMI,            RSVD3,          RSVD4,          I2S3,           0x31b4,  N,  N,  N),
3125         PINGROUP(clk3_out_pee0,         EXTPERIPH3,     RSVD2,          RSVD3,          RSVD4,          RSVD3,          0x31b8,  N,  N,  N),
3126         PINGROUP(clk3_req_pee1,         DEV3,           RSVD2,          RSVD3,          RSVD4,          RSVD4,          0x31bc,  N,  N,  N),
3127         PINGROUP(pc7,                   RSVD1,          RSVD2,          GMI,            GMI_ALT,        RSVD1,          0x31c0,  N,  N,  N),
3128         PINGROUP(pi5,                   SDMMC2,         RSVD2,          GMI,            RSVD4,          GMI,            0x31c4,  N,  N,  N),
3129         PINGROUP(pi7,                   RSVD1,          TRACE,          GMI,            DTV,            RSVD1,          0x31c8,  N,  N,  N),
3130         PINGROUP(pk0,                   RSVD1,          SDMMC3,         GMI,            SOC,            RSVD1,          0x31cc,  N,  N,  N),
3131         PINGROUP(pk1,                   SDMMC2,         TRACE,          GMI,            RSVD4,          GMI,            0x31d0,  N,  N,  N),
3132         PINGROUP(pj0,                   RSVD1,          RSVD2,          GMI,            USB,            RSVD1,          0x31d4,  N,  N,  N),
3133         PINGROUP(pj2,                   RSVD1,          RSVD2,          GMI,            SOC,            RSVD1,          0x31d8,  N,  N,  N),
3134         PINGROUP(pk3,                   SDMMC2,         TRACE,          GMI,            CCLA,           GMI,            0x31dc,  N,  N,  N),
3135         PINGROUP(pk4,                   SDMMC2,         RSVD2,          GMI,            GMI_ALT,        GMI,            0x31e0,  N,  N,  N),
3136         PINGROUP(pk2,                   RSVD1,          RSVD2,          GMI,            RSVD4,          RSVD4,          0x31e4,  N,  N,  N),
3137         PINGROUP(pi3,                   RSVD1,          RSVD2,          GMI,            SPI4,           RSVD1,          0x31e8,  N,  N,  N),
3138         PINGROUP(pi6,                   RSVD1,          RSVD2,          GMI,            SDMMC2,         RSVD1,          0x31ec,  N,  N,  N),
3139         PINGROUP(pg0,                   RSVD1,          RSVD2,          GMI,            RSVD4,          RSVD4,          0x31f0,  N,  N,  N),
3140         PINGROUP(pg1,                   RSVD1,          RSVD2,          GMI,            RSVD4,          RSVD4,          0x31f4,  N,  N,  N),
3141         PINGROUP(pg2,                   RSVD1,          TRACE,          GMI,            RSVD4,          RSVD4,          0x31f8,  N,  N,  N),
3142         PINGROUP(pg3,                   RSVD1,          TRACE,          GMI,            RSVD4,          RSVD4,          0x31fc,  N,  N,  N),
3143         PINGROUP(pg4,                   RSVD1,          TMDS,           GMI,            SPI4,           RSVD1,          0x3200,  N,  N,  N),
3144         PINGROUP(pg5,                   RSVD1,          RSVD2,          GMI,            SPI4,           RSVD1,          0x3204,  N,  N,  N),
3145         PINGROUP(pg6,                   RSVD1,          RSVD2,          GMI,            SPI4,           RSVD1,          0x3208,  N,  N,  N),
3146         PINGROUP(pg7,                   RSVD1,          RSVD2,          GMI,            SPI4,           RSVD1,          0x320c,  N,  N,  N),
3147         PINGROUP(ph0,                   PWM0,           TRACE,          GMI,            DTV,            GMI,            0x3210,  N,  N,  N),
3148         PINGROUP(ph1,                   PWM1,           TMDS,           GMI,            DISPLAYA,       GMI,            0x3214,  N,  N,  N),
3149         PINGROUP(ph2,                   PWM2,           TMDS,           GMI,            CLDVFS,         GMI,            0x3218,  N,  N,  N),
3150         PINGROUP(ph3,                   PWM3,           SPI4,           GMI,            CLDVFS,         GMI,            0x321c,  N,  N,  N),
3151         PINGROUP(ph4,                   SDMMC2,         RSVD2,          GMI,            RSVD4,          GMI,            0x3220,  N,  N,  N),
3152         PINGROUP(ph5,                   SDMMC2,         RSVD2,          GMI,            RSVD4,          GMI,            0x3224,  N,  N,  N),
3153         PINGROUP(ph6,                   SDMMC2,         TRACE,          GMI,            DTV,            GMI,            0x3228,  N,  N,  N),
3154         PINGROUP(ph7,                   SDMMC2,         TRACE,          GMI,            DTV,            GMI,            0x322c,  N,  N,  N),
3155         PINGROUP(pj7,                   UARTD,          RSVD2,          GMI,            GMI_ALT,        RSVD2,          0x3230,  N,  N,  N),
3156         PINGROUP(pb0,                   UARTD,          RSVD2,          GMI,            RSVD4,          RSVD2,          0x3234,  N,  N,  N),
3157         PINGROUP(pb1,                   UARTD,          RSVD2,          GMI,            RSVD4,          RSVD2,          0x3238,  N,  N,  N),
3158         PINGROUP(pk7,                   UARTD,          RSVD2,          GMI,            RSVD4,          RSVD2,          0x323c,  N,  N,  N),
3159         PINGROUP(pi0,                   RSVD1,          RSVD2,          GMI,            RSVD4,          RSVD4,          0x3240,  N,  N,  N),
3160         PINGROUP(pi1,                   RSVD1,          RSVD2,          GMI,            RSVD4,          RSVD1,          0x3244,  N,  N,  N),
3161         PINGROUP(pi2,                   SDMMC2,         TRACE,          GMI,            RSVD4,          GMI,            0x3248,  N,  N,  N),
3162         PINGROUP(pi4,                   SPI4,           TRACE,          GMI,            DISPLAYA,       GMI,            0x324c,  N,  N,  N),
3163         PINGROUP(gen2_i2c_scl_pt5,      I2C2,           RSVD2,          GMI,            RSVD4,          RSVD2,          0x3250,  Y,  N,  N),
3164         PINGROUP(gen2_i2c_sda_pt6,      I2C2,           RSVD2,          GMI,            RSVD4,          RSVD2,          0x3254,  Y,  N,  N),
3165         PINGROUP(sdmmc4_clk_pcc4,       SDMMC4,         RSVD2,          GMI,            RSVD4,          RSVD2,          0x3258,  N,  Y,  N),
3166         PINGROUP(sdmmc4_cmd_pt7,        SDMMC4,         RSVD2,          GMI,            RSVD4,          RSVD2,          0x325c,  N,  Y,  N),
3167         PINGROUP(sdmmc4_dat0_paa0,      SDMMC4,         SPI3,           GMI,            RSVD4,          SDMMC4,         0x3260,  N,  Y,  N),
3168         PINGROUP(sdmmc4_dat1_paa1,      SDMMC4,         SPI3,           GMI,            RSVD4,          SDMMC4,         0x3264,  N,  Y,  N),
3169         PINGROUP(sdmmc4_dat2_paa2,      SDMMC4,         SPI3,           GMI,            RSVD4,          SDMMC4,         0x3268,  N,  Y,  N),
3170         PINGROUP(sdmmc4_dat3_paa3,      SDMMC4,         SPI3,           GMI,            RSVD4,          SDMMC4,         0x326c,  N,  Y,  N),
3171         PINGROUP(sdmmc4_dat4_paa4,      SDMMC4,         SPI3,           GMI,            RSVD4,          SDMMC4,         0x3270,  N,  Y,  N),
3172         PINGROUP(sdmmc4_dat5_paa5,      SDMMC4,         SPI3,           RSVD3,          RSVD4,          SDMMC4,         0x3274,  N,  Y,  N),
3173         PINGROUP(sdmmc4_dat6_paa6,      SDMMC4,         SPI3,           GMI,            RSVD4,          SDMMC4,         0x3278,  N,  Y,  N),
3174         PINGROUP(sdmmc4_dat7_paa7,      SDMMC4,         RSVD1,          GMI,            RSVD4,          SDMMC4,         0x327c,  N,  Y,  N),
3175         PINGROUP(cam_mclk_pcc0,         VI,             VI_ALT1,        VI_ALT3,        SDMMC2,         VI,             0x3284,  N,  N,  N),
3176         PINGROUP(pcc1,                  I2S4,           RSVD1,          RSVD3,          SDMMC2,         I2S4,           0x3288,  N,  N,  N),
3177         PINGROUP(pbb0,                  VGP6,           VIMCLK2,        SDMMC2,         VIMCLK2_ALT,    VGP6,           0x328c,  N,  N,  N),
3178         PINGROUP(cam_i2c_scl_pbb1,      VGP1,           I2C3,           RSVD3,          SDMMC2,         VGP1,           0x3290,  Y,  N,  N),
3179         PINGROUP(cam_i2c_sda_pbb2,      VGP2,           I2C3,           RSVD3,          SDMMC2,         VGP2,           0x3294,  Y,  N,  N),
3180         PINGROUP(pbb3,                  VGP3,           DISPLAYA,       DISPLAYB,       SDMMC2,         VGP3,           0x3298,  N,  N,  N),
3181         PINGROUP(pbb4,                  VGP4,           DISPLAYA,       DISPLAYB,       SDMMC2,         VGP4,           0x329c,  N,  N,  N),
3182         PINGROUP(pbb5,                  VGP5,           DISPLAYA,       RSVD3,          SDMMC2,         VGP5,           0x32a0,  N,  N,  N),
3183         PINGROUP(pbb6,                  I2S4,           RSVD2,          DISPLAYB,       SDMMC2,         I2S4,           0x32a4,  N,  N,  N),
3184         PINGROUP(pbb7,                  I2S4,           RSVD2,          RSVD3,          SDMMC2,         I2S4,           0x32a8,  N,  N,  N),
3185         PINGROUP(pcc2,                  I2S4,           RSVD2,          SDMMC3,         SDMMC2,         I2S4,           0x32ac,  N,  N,  N),
3186         PINGROUP(jtag_rtck,             RTCK,           RSVD2,          RSVD3,          RSVD4,          RTCK,           0x32b0,  N,  N,  N),
3187         PINGROUP(pwr_i2c_scl_pz6,       I2CPWR,         RSVD2,          RSVD3,          RSVD4,          RSVD2,          0x32b4,  Y,  N,  N),
3188         PINGROUP(pwr_i2c_sda_pz7,       I2CPWR,         RSVD2,          RSVD3,          RSVD4,          RSVD2,          0x32b8,  Y,  N,  N),
3189         PINGROUP(kb_row0_pr0,           KBC,            RSVD2,          RSVD3,          RSVD4,          RSVD4,          0x32bc,  N,  N,  N),
3190         PINGROUP(kb_row1_pr1,           KBC,            RSVD2,          RSVD3,          RSVD4,          RSVD4,          0x32c0,  N,  N,  N),
3191         PINGROUP(kb_row2_pr2,           KBC,            RSVD2,          RSVD3,          RSVD4,          RSVD4,          0x32c4,  N,  N,  N),
3192         PINGROUP(kb_row3_pr3,           KBC,            DISPLAYA,       SYS,            DISPLAYB,       KBC,            0x32c8,  N,  N,  N),
3193         PINGROUP(kb_row4_pr4,           KBC,            DISPLAYA,       RSVD3,          DISPLAYB,       RSVD3,          0x32cc,  N,  N,  N),
3194         PINGROUP(kb_row5_pr5,           KBC,            DISPLAYA,       RSVD3,          DISPLAYB,       RSVD3,          0x32d0,  N,  N,  N),
3195         PINGROUP(kb_row6_pr6,           KBC,            DISPLAYA,       DISPLAYA_ALT,   DISPLAYB,       KBC,            0x32d4,  N,  N,  N),
3196         PINGROUP(kb_row7_pr7,           KBC,            RSVD2,          CLDVFS,         UARTA,          RSVD2,          0x32d8,  N,  N,  N),
3197         PINGROUP(kb_row8_ps0,           KBC,            RSVD2,          CLDVFS,         UARTA,          RSVD2,          0x32dc,  N,  N,  N),
3198         PINGROUP(kb_row9_ps1,           KBC,            RSVD2,          RSVD3,          UARTA,          KBC,            0x32e0,  N,  N,  N),
3199         PINGROUP(kb_row10_ps2,          KBC,            RSVD2,          RSVD3,          UARTA,          KBC,            0x32e4,  N,  N,  N),
3200         PINGROUP(kb_row11_ps3,          KBC,            RSVD2,          RSVD3,          IRDA,           RSVD3,          0x32e8,  N,  N,  N),
3201         PINGROUP(kb_row12_ps4,          KBC,            RSVD2,          RSVD3,          IRDA,           RSVD3,          0x32ec,  N,  N,  N),
3202         PINGROUP(kb_row13_ps5,          KBC,            RSVD2,          SPI2,           RSVD4,          RSVD4,          0x32f0,  N,  N,  N),
3203         PINGROUP(kb_row14_ps6,          KBC,            RSVD2,          SPI2,           RSVD4,          RSVD4,          0x32f4,  N,  N,  N),
3204         PINGROUP(kb_row15_ps7,          KBC,            SOC,            RSVD3,          RSVD4,          KBC,            0x32f8,  N,  N,  N),
3205         PINGROUP(kb_col0_pq0,           KBC,            RSVD2,          SPI2,           RSVD4,          RSVD4,          0x32fc,  N,  N,  N),
3206         PINGROUP(kb_col1_pq1,           KBC,            RSVD2,          SPI2,           RSVD4,          RSVD4,          0x3300,  N,  N,  N),
3207         PINGROUP(kb_col2_pq2,           KBC,            RSVD2,          SPI2,           RSVD4,          RSVD4,          0x3304,  N,  N,  N),
3208         PINGROUP(kb_col3_pq3,           KBC,            DISPLAYA,       PWM2,           UARTA,          KBC,            0x3308,  N,  N,  N),
3209         PINGROUP(kb_col4_pq4,           KBC,            OWR,            SDMMC3,         UARTA,          KBC,            0x330c,  N,  N,  N),
3210         PINGROUP(kb_col5_pq5,           KBC,            RSVD2,          SDMMC3,         RSVD4,          RSVD4,          0x3310,  N,  N,  N),
3211         PINGROUP(kb_col6_pq6,           KBC,            RSVD2,          SPI2,           UARTD,          RSVD2,          0x3314,  N,  N,  N),
3212         PINGROUP(kb_col7_pq7,           KBC,            RSVD2,          SPI2,           UARTD,          RSVD2,          0x3318,  N,  N,  N),
3213         PINGROUP(clk_32k_out_pa0,       BLINK,          SOC,            RSVD3,          RSVD4,          RSVD3,          0x331c,  N,  N,  N),
3214         PINGROUP(core_pwr_req,          PWRON,          RSVD2,          RSVD3,          RSVD4,          RSVD2,          0x3324,  N,  N,  N),
3215         PINGROUP(cpu_pwr_req,           CPU,            RSVD2,          RSVD3,          RSVD4,          RSVD2,          0x3328,  N,  N,  N),
3216         PINGROUP(pwr_int_n,             PMI,            RSVD2,          RSVD3,          RSVD4,          RSVD2,          0x332c,  N,  N,  N),
3217         PINGROUP(clk_32k_in,            CLK,            RSVD2,          RSVD3,          RSVD4,          RSVD2,          0x3330,  N,  N,  N),
3218         PINGROUP(owr,                   OWR,            RSVD2,          RSVD3,          RSVD4,          RSVD2,          0x3334,  N,  N,  Y),
3219         PINGROUP(dap1_fs_pn0,           I2S0,           HDA,            GMI,            RSVD4,          RSVD4,          0x3338,  N,  N,  N),
3220         PINGROUP(dap1_din_pn1,          I2S0,           HDA,            GMI,            RSVD4,          RSVD4,          0x333c,  N,  N,  N),
3221         PINGROUP(dap1_dout_pn2,         I2S0,           HDA,            GMI,            SATA,           I2S0,           0x3340,  N,  N,  N),
3222         PINGROUP(dap1_sclk_pn3,         I2S0,           HDA,            GMI,            RSVD4,          I2S0,           0x3344,  N,  N,  N),
3223         PINGROUP(dap_mclk1_req_pee2,    DAP,            DAP1,           SATA,           RSVD4,          DAP,            0x3348,  N,  N,  N),
3224         PINGROUP(dap_mclk1_pw4,         EXTPERIPH1,     DAP2,           RSVD3,          RSVD4,          RSVD3,          0x334c,  N,  N,  N),
3225         PINGROUP(spdif_in_pk6,          SPDIF,          RSVD2,          RSVD3,          I2C3,           RSVD3,          0x3350,  N,  N,  N),
3226         PINGROUP(spdif_out_pk5,         SPDIF,          RSVD2,          RSVD3,          I2C3,           RSVD3,          0x3354,  N,  N,  N),
3227         PINGROUP(dap2_fs_pa2,           I2S1,           HDA,            GMI,            RSVD4,          I2S1,           0x3358,  N,  N,  N),
3228         PINGROUP(dap2_din_pa4,          I2S1,           HDA,            GMI,            RSVD4,          I2S1,           0x335c,  N,  N,  N),
3229         PINGROUP(dap2_dout_pa5,         I2S1,           HDA,            GMI,            RSVD4,          I2S1,           0x3360,  N,  N,  N),
3230         PINGROUP(dap2_sclk_pa3,         I2S1,           HDA,            GMI,            RSVD4,          I2S1,           0x3364,  N,  N,  N),
3231         PINGROUP(dvfs_pwm_px0,          SPI6,           CLDVFS,         GMI,            RSVD4,          SPI6,           0x3368,  N,  N,  N),
3232         PINGROUP(gpio_x1_aud_px1,       SPI6,           RSVD2,          GMI,            RSVD4,          SPI6,           0x336c,  N,  N,  N),
3233         PINGROUP(gpio_x3_aud_px3,       SPI6,           SPI1,           GMI,            RSVD4,          SPI6,           0x3370,  N,  N,  N),
3234         PINGROUP(dvfs_clk_px2,          SPI6,           CLDVFS,         GMI,            RSVD4,          SPI6,           0x3374,  N,  N,  N),
3235         PINGROUP(gpio_x4_aud_px4,       GMI,            SPI1,           SPI2,           DAP2,           SPI1,           0x3378,  N,  N,  N),
3236         PINGROUP(gpio_x5_aud_px5,       GMI,            SPI1,           SPI2,           RSVD4,          SPI1,           0x337c,  N,  N,  N),
3237         PINGROUP(gpio_x6_aud_px6,       SPI6,           SPI1,           SPI2,           GMI,            SPI1,           0x3380,  N,  N,  N),
3238         PINGROUP(gpio_x7_aud_px7,       RSVD1,          SPI1,           SPI2,           RSVD4,          SPI1,           0x3384,  N,  N,  N),
3239         PINGROUP(sdmmc3_clk_pa6,        SDMMC3,         RSVD2,          RSVD3,          SPI3,           SDMMC3,         0x3390,  N,  N,  N),
3240         PINGROUP(sdmmc3_cmd_pa7,        SDMMC3,         PWM3,           UARTA,          SPI3,           SDMMC3,         0x3394,  N,  N,  N),
3241         PINGROUP(sdmmc3_dat0_pb7,       SDMMC3,         RSVD2,          RSVD3,          SPI3,           SDMMC3,         0x3398,  N,  N,  N),
3242         PINGROUP(sdmmc3_dat1_pb6,       SDMMC3,         PWM2,           UARTA,          SPI3,           SDMMC3,         0x339c,  N,  N,  N),
3243         PINGROUP(sdmmc3_dat2_pb5,       SDMMC3,         PWM1,           DISPLAYA,       SPI3,           SDMMC3,         0x33a0,  N,  N,  N),
3244         PINGROUP(sdmmc3_dat3_pb4,       SDMMC3,         PWM0,           DISPLAYB,       SPI3,           SDMMC3,         0x33a4,  N,  N,  N),
3245         PINGROUP(pex_l0_rst_n_pdd1,     PE0,            RSVD2,          RSVD3,          RSVD4,          PE0,            0x33bc,  N,  N,  N),
3246         PINGROUP(pex_l0_clkreq_n_pdd2,  PE0,            RSVD2,          RSVD3,          RSVD4,          PE0,            0x33c0,  N,  N,  N),
3247         PINGROUP(pex_wake_n_pdd3,       PE,             RSVD2,          RSVD3,          RSVD4,          PE,             0x33c4,  N,  N,  N),
3248         PINGROUP(pex_l1_rst_n_pdd5,     PE1,            RSVD2,          RSVD3,          RSVD4,          PE1,            0x33cc,  N,  N,  N),
3249         PINGROUP(pex_l1_clkreq_n_pdd6,  PE1,            RSVD2,          RSVD3,          RSVD4,          PE1,            0x33d0,  N,  N,  N),
3250         PINGROUP(hdmi_cec_pee3,         CEC,            RSVD2,          RSVD3,          RSVD4,          CEC,            0x33e0,  Y,  N,  N),
3251         PINGROUP(sdmmc1_wp_n_pv3,       SDMMC1,         CLK12,          SPI4,           UARTA,          SDMMC1,         0x33e4,  N,  N,  N),
3252         PINGROUP(sdmmc3_cd_n_pv2,       SDMMC3,         OWR,            RSVD3,          RSVD4,          SDMMC3,         0x33e8,  N,  N,  N),
3253         PINGROUP(gpio_w2_aud_pw2,       SPI6,           RSVD2,          SPI2,           I2C1,           RSVD2,          0x33ec,  N,  N,  N),
3254         PINGROUP(gpio_w3_aud_pw3,       SPI6,           SPI1,           SPI2,           I2C1,           SPI1,           0x33f0,  N,  N,  N),
3255         PINGROUP(usb_vbus_en0_pn4,      USB,            RSVD2,          RSVD3,          RSVD4,          USB,            0x33f4,  Y,  N,  N),
3256         PINGROUP(usb_vbus_en1_pn5,      USB,            RSVD2,          RSVD3,          RSVD4,          USB,            0x33f8,  Y,  N,  N),
3257         PINGROUP(sdmmc3_clk_lb_out_pee4,        SDMMC3, RSVD2,          RSVD3,          RSVD4,          SDMMC3,         0x33fc,  N,  N,  N),
3258         PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3,         RSVD2,          RSVD3,          RSVD4,          SDMMC3,         0x3400,  N,  N,  N),
3259         PINGROUP(gmi_clk_lb,            SDMMC2,         RSVD2,          GMI,            RSVD4,          SDMMC2,         0x3404,  N,  N,  N),
3260         PINGROUP(reset_out_n,           RSVD1,          RSVD2,          RSVD3,          RESET_OUT_N,    RSVD1,          0x3408,  N,  N,  N),
3261         PINGROUP(kb_row16_pt0,          KBC,            RSVD2,          RSVD3,          UARTC,          KBC,            0x340c,  N,  N,  N),
3262         PINGROUP(kb_row17_pt1,          KBC,            RSVD2,          RSVD3,          UARTC,          KBC,            0x3410,  N,  N,  N),
3263         PINGROUP(usb_vbus_en2_pff1,     USB,            RSVD2,          RSVD3,          RSVD4,          USB,            0x3414,  Y,  N,  N),
3264         PINGROUP(pff2,                  SATA,           RSVD2,          RSVD3,          RSVD4,          RSVD2,          0x3418,  Y,  N,  N),
3265         PINGROUP(dp_hpd_pff0,           DP,             RSVD2,          RSVD3,          RSVD4,          DP,             0x3430,  N,  N,  N),
3266
3267         /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
3268         DRV_PINGROUP(ao1,   0x868,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3269         DRV_PINGROUP(ao2,   0x86c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3270         DRV_PINGROUP(at1,   0x870,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
3271         DRV_PINGROUP(at2,   0x874,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
3272         DRV_PINGROUP(at3,   0x878,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
3273         DRV_PINGROUP(at4,   0x87c,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
3274         DRV_PINGROUP(at5,   0x880,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
3275         DRV_PINGROUP(cdev1, 0x884,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3276         DRV_PINGROUP(cdev2, 0x888,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3277         DRV_PINGROUP(dap1,  0x890,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3278         DRV_PINGROUP(dap2,  0x894,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3279         DRV_PINGROUP(dap3,  0x898,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3280         DRV_PINGROUP(dap4,  0x89c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3281         DRV_PINGROUP(dbg,   0x8a0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3282         DRV_PINGROUP(sdio3, 0x8b0,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
3283         DRV_PINGROUP(spi,   0x8b4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3284         DRV_PINGROUP(uaa,   0x8b8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3285         DRV_PINGROUP(uab,   0x8bc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3286         DRV_PINGROUP(uart2, 0x8c0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3287         DRV_PINGROUP(uart3, 0x8c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3288         DRV_PINGROUP(sdio1, 0x8ec,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
3289         DRV_PINGROUP(ddc,   0x8fc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3290         DRV_PINGROUP(gma,   0x900,  2,  3,  4,  14,  5,  20,  5,  28,  2,  30,  2,  Y),
3291         DRV_PINGROUP(gme,   0x910,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
3292         DRV_PINGROUP(gmf,   0x914,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
3293         DRV_PINGROUP(gmg,   0x918,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
3294         DRV_PINGROUP(gmh,   0x91c,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
3295         DRV_PINGROUP(owr,   0x920,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3296         DRV_PINGROUP(uda,   0x924,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3297         DRV_PINGROUP(gpv,   0x928,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3298         DRV_PINGROUP(dev3,  0x92c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3299         DRV_PINGROUP(cec,   0x938,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3300         DRV_PINGROUP(at6,   0x994,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
3301         DRV_PINGROUP(dap5,  0x998,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3302         DRV_PINGROUP(usb_vbus_en,  0x99c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3303         DRV_PINGROUP(ao3,   0x9a8,  2,  3,  4,  12,  5,  -1,  -1,  28,  2,  -1,  -1,  N),
3304         DRV_PINGROUP(ao0,   0x9b0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3305         DRV_PINGROUP(hv0,   0x9b4,  2,  3,  4,  12,  5,  -1,  -1,  28,  2,  -1,  -1,  N),
3306         DRV_PINGROUP(sdio4, 0x9c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
3307         DRV_PINGROUP(ao4,   0x9c8,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
3308
3309 };
3310
3311 static int tegra124_pinctrl_suspend(u32 *pg_data)
3312 {
3313         int i;
3314         u32 *ctx = pg_data;
3315
3316         for (i = 0; i <  ARRAY_SIZE(tegra124_groups); i++) {
3317                 if (tegra124_groups[i].drv_reg < 0)
3318                         *ctx++ = tegra_pinctrl_readl(tegra124_groups[i].mux_bank,
3319                                                 tegra124_groups[i].mux_reg);
3320                 else
3321                         *ctx++ = tegra_pinctrl_readl(tegra124_groups[i].drv_bank,
3322                                                 tegra124_groups[i].drv_reg);
3323         }
3324
3325         return 0;
3326 }
3327
3328 static void tegra124_pinctrl_resume(u32 *pg_data)
3329 {
3330         int i;
3331         u32 *ctx = pg_data;
3332         u32 *tmp = pg_data;
3333         u32 reg_value;
3334
3335         for (i = 0; i < ARRAY_SIZE(tegra124_groups); i++) {
3336                 if (tegra124_groups[i].drv_reg < 0) {
3337                         reg_value = *tmp++;
3338                         reg_value |= BIT(4);
3339                         tegra_pinctrl_writel(reg_value,
3340                                         tegra124_groups[i].mux_bank,
3341                                         tegra124_groups[i].mux_reg);
3342                 }
3343         }
3344
3345         tegra_pmc_remove_dpd_req();
3346         for (i = 0; i <  ARRAY_SIZE(tegra124_groups); i++) {
3347                 if (tegra124_groups[i].drv_reg < 0)
3348                         tegra_pinctrl_writel(*ctx++, tegra124_groups[i].mux_bank,
3349                                                 tegra124_groups[i].mux_reg);
3350                 else
3351                         tegra_pinctrl_writel(*ctx++, tegra124_groups[i].drv_bank,
3352                                                 tegra124_groups[i].drv_reg);
3353         }
3354         /* Clear DPD sample */
3355         tegra_pmc_clear_dpd_sample();
3356 }
3357
3358 static struct tegra_pinctrl_group_config_data t124_pin_drv_group_soc_data[] = {
3359         TEGRA_PINCTRL_SET_DRIVE(dap2, 0, 1, 3, 5, 6, 0, 0, 0),
3360         TEGRA_PINCTRL_SET_DRIVE(dap1, 0, 1, 3, 5, 6, 0, 0, 0),
3361         TEGRA_PINCTRL_SET_DRIVE(dap3, 0, 1, 3, 5, 6, 0, 0, 0),
3362         TEGRA_PINCTRL_SET_DRIVE(dap4, 0, 1, 3, 5, 6, 0, 0, 0),
3363         TEGRA_PINCTRL_SET_DRIVE(dap5, 0, 1, 3, 5, 6, 0, 0, 0),
3364         TEGRA_PINCTRL_SET_DRIVE(dbg, 1, 1, 0, 5, 5, 0, 0, 0),
3365         TEGRA_PINCTRL_SET_DRIVE(at5, 1, 1, 0, 5, 5, 0, 0, 0),
3366         TEGRA_PINCTRL_SET_DRIVE(gme, 1, 1, 0, 5, 5, 0, 0, 0),
3367         TEGRA_PINCTRL_SET_DRIVE(ddc, 1, 1, 0, 5, 5, 0, 0, 0),
3368         TEGRA_PINCTRL_SET_DRIVE(ao1, 1, 1, 0, 5, 5, 0, 0, 0),
3369         TEGRA_PINCTRL_SET_DRIVE(uart2, 0, 0, 3, 0, 0, 3, 3, 0),
3370         TEGRA_PINCTRL_SET_DRIVE(uart3, 0, 0, 3, 0, 0, 3, 3, 0),
3371         TEGRA_PINCTRL_SET_DRIVE(at2, 0, 0, 0, 55, 63, 0, 0, 0),
3372         TEGRA_PINCTRL_SET_DRIVE(uda, 0, 0, 0, 23, 23, 3, 3, 0),
3373         TEGRA_PINCTRL_SET_DRIVE(uaa, 0, 0, 0, 23, 23, 3, 3, 0),
3374 };
3375
3376 static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
3377         .ngpios = NUM_GPIOS,
3378         .pins = tegra124_pins,
3379         .npins = ARRAY_SIZE(tegra124_pins),
3380         .functions = tegra124_functions,
3381         .nfunctions = ARRAY_SIZE(tegra124_functions),
3382         .groups = tegra124_groups,
3383         .ngroups = ARRAY_SIZE(tegra124_groups),
3384         .suspend = tegra124_pinctrl_suspend,
3385         .resume = tegra124_pinctrl_resume,
3386         .config_data = t124_pin_drv_group_soc_data,
3387         .nconfig_data = ARRAY_SIZE(t124_pin_drv_group_soc_data),
3388 };
3389
3390 static int tegra124_pinctrl_probe(struct platform_device *pdev)
3391 {
3392         return tegra_pinctrl_probe(pdev, &tegra124_pinctrl);
3393 }
3394
3395 static struct of_device_id tegra124_pinctrl_of_match[] = {
3396         { .compatible = "nvidia,tegra124-pinmux", },
3397         { },
3398 };
3399 MODULE_DEVICE_TABLE(of, tegra124_pinctrl_of_match);
3400
3401 static struct platform_driver tegra124_pinctrl_driver = {
3402         .driver = {
3403                 .name = "tegra124-pinctrl",
3404                 .owner = THIS_MODULE,
3405                 .of_match_table = tegra124_pinctrl_of_match,
3406         },
3407         .probe = tegra124_pinctrl_probe,
3408         .remove = tegra_pinctrl_remove,
3409 };
3410
3411 static int __init tegra124_pinctrl_init(void)
3412 {
3413         return platform_driver_register(&tegra124_pinctrl_driver);
3414 }
3415 postcore_initcall_sync(tegra124_pinctrl_init);
3416
3417 static void __exit tegra124_pinctrl_exit(void)
3418 {
3419         platform_driver_unregister(&tegra124_pinctrl_driver);
3420 }
3421 module_exit(tegra124_pinctrl_exit);
3422
3423 MODULE_AUTHOR("Ashwini Ghuge <aghuge@nvidia.com>");
3424 MODULE_DESCRIPTION("NVIDIA Tegra124 pinctrl driver");
3425 MODULE_LICENSE("GPL v2");