Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-3.10.git] / drivers / net / wireless / rtlwifi / rtl8192c / phy_common.h
1 /******************************************************************************
2  *
3  * Copyright(c) 2009-2010  Realtek Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
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11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
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15  * this program; if not, write to the Free Software Foundation, Inc.,
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18  * The full GNU General Public License is included in this distribution in the
19  * file called LICENSE.
20  *
21  * Contact Information:
22  * wlanfae <wlanfae@realtek.com>
23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24  * Hsinchu 300, Taiwan.
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26  * Larry Finger <Larry.Finger@lwfinger.net>
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28  *****************************************************************************/
29
30 #ifndef __RTL92C_PHY_COMMON_H__
31 #define __RTL92C_PHY_COMMON_H__
32
33 #define MAX_PRECMD_CNT                  16
34 #define MAX_RFDEPENDCMD_CNT             16
35 #define MAX_POSTCMD_CNT                 16
36
37 #define MAX_DOZE_WAITING_TIMES_9x       64
38
39 #define RT_CANNOT_IO(hw)                false
40 #define HIGHPOWER_RADIOA_ARRAYLEN       22
41
42 #define IQK_ADDA_REG_NUM                16
43 #define MAX_TOLERANCE                   5
44 #define IQK_DELAY_TIME                  1
45
46 #define APK_BB_REG_NUM                  5
47 #define APK_AFE_REG_NUM                 16
48 #define APK_CURVE_REG_NUM               4
49 #define PATH_NUM                        2
50
51 #define LOOP_LIMIT                      5
52 #define MAX_STALL_TIME                  50
53 #define AntennaDiversityValue           0x80
54 #define MAX_TXPWR_IDX_NMODE_92S         63
55 #define Reset_Cnt_Limit                 3
56
57 #define IQK_ADDA_REG_NUM                16
58 #define IQK_MAC_REG_NUM                 4
59
60 #define IQK_DELAY_TIME                  1
61 #define RF90_PATH_MAX                   2
62
63 #define CT_OFFSET_MAC_ADDR              0X16
64
65 #define CT_OFFSET_CCK_TX_PWR_IDX        0x5A
66 #define CT_OFFSET_HT401S_TX_PWR_IDX     0x60
67 #define CT_OFFSET_HT402S_TX_PWR_IDX_DIF 0x66
68 #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF  0x69
69 #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF  0x6C
70
71 #define CT_OFFSET_HT40_MAX_PWR_OFFSET   0x6F
72 #define CT_OFFSET_HT20_MAX_PWR_OFFSET   0x72
73
74 #define CT_OFFSET_CHANNEL_PLAH          0x75
75 #define CT_OFFSET_THERMAL_METER         0x78
76 #define CT_OFFSET_RF_OPTION             0x79
77 #define CT_OFFSET_VERSION               0x7E
78 #define CT_OFFSET_CUSTOMER_ID           0x7F
79
80 #define RTL92C_MAX_PATH_NUM             2
81 #define LLT_LAST_ENTRY_OF_TX_PKT_BUFFER 255
82
83 enum swchnlcmd_id {
84         CMDID_END,
85         CMDID_SET_TXPOWEROWER_LEVEL,
86         CMDID_BBREGWRITE10,
87         CMDID_WRITEPORT_ULONG,
88         CMDID_WRITEPORT_USHORT,
89         CMDID_WRITEPORT_UCHAR,
90         CMDID_RF_WRITEREG,
91 };
92
93 struct swchnlcmd {
94         enum swchnlcmd_id cmdid;
95         u32 para1;
96         u32 para2;
97         u32 msdelay;
98 };
99
100 enum hw90_block_e {
101         HW90_BLOCK_MAC = 0,
102         HW90_BLOCK_PHY0 = 1,
103         HW90_BLOCK_PHY1 = 2,
104         HW90_BLOCK_RF = 3,
105         HW90_BLOCK_MAXIMUM = 4,
106 };
107
108 enum baseband_config_type {
109         BASEBAND_CONFIG_PHY_REG = 0,
110         BASEBAND_CONFIG_AGC_TAB = 1,
111 };
112
113 enum ra_offset_area {
114         RA_OFFSET_LEGACY_OFDM1,
115         RA_OFFSET_LEGACY_OFDM2,
116         RA_OFFSET_HT_OFDM1,
117         RA_OFFSET_HT_OFDM2,
118         RA_OFFSET_HT_OFDM3,
119         RA_OFFSET_HT_OFDM4,
120         RA_OFFSET_HT_CCK,
121 };
122
123 enum antenna_path {
124         ANTENNA_NONE,
125         ANTENNA_D,
126         ANTENNA_C,
127         ANTENNA_CD,
128         ANTENNA_B,
129         ANTENNA_BD,
130         ANTENNA_BC,
131         ANTENNA_BCD,
132         ANTENNA_A,
133         ANTENNA_AD,
134         ANTENNA_AC,
135         ANTENNA_ACD,
136         ANTENNA_AB,
137         ANTENNA_ABD,
138         ANTENNA_ABC,
139         ANTENNA_ABCD
140 };
141
142 struct r_antenna_select_ofdm {
143         u32 r_tx_antenna:4;
144         u32 r_ant_l:4;
145         u32 r_ant_non_ht:4;
146         u32 r_ant_ht1:4;
147         u32 r_ant_ht2:4;
148         u32 r_ant_ht_s1:4;
149         u32 r_ant_non_ht_s1:4;
150         u32 ofdm_txsc:2;
151         u32 reserved:2;
152 };
153
154 struct r_antenna_select_cck {
155         u8 r_cckrx_enable_2:2;
156         u8 r_cckrx_enable:2;
157         u8 r_ccktx_enable:4;
158 };
159
160 struct efuse_contents {
161         u8 mac_addr[ETH_ALEN];
162         u8 cck_tx_power_idx[6];
163         u8 ht40_1s_tx_power_idx[6];
164         u8 ht40_2s_tx_power_idx_diff[3];
165         u8 ht20_tx_power_idx_diff[3];
166         u8 ofdm_tx_power_idx_diff[3];
167         u8 ht40_max_power_offset[3];
168         u8 ht20_max_power_offset[3];
169         u8 channel_plan;
170         u8 thermal_meter;
171         u8 rf_option[5];
172         u8 version;
173         u8 oem_id;
174         u8 regulatory;
175 };
176
177 struct tx_power_struct {
178         u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
179         u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
180         u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
181         u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
182         u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
183         u8 legacy_ht_txpowerdiff;
184         u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
185         u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
186         u8 pwrgroup_cnt;
187         u32 mcs_original_offset[4][16];
188 };
189
190 u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw,
191                                    u32 regaddr, u32 bitmask);
192 void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
193                                   u32 regaddr, u32 bitmask, u32 data);
194 u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
195                                    enum radio_path rfpath, u32 regaddr,
196                                    u32 bitmask);
197 bool rtl92c_phy_mac_config(struct ieee80211_hw *hw);
198 bool rtl92c_phy_bb_config(struct ieee80211_hw *hw);
199 bool rtl92c_phy_rf_config(struct ieee80211_hw *hw);
200 bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
201                                                  enum radio_path rfpath);
202 void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
203 void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw,
204                                          long *powerlevel);
205 void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
206 bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw,
207                                           long power_indbm);
208 void rtl92c_phy_scan_operation_backup(struct ieee80211_hw *hw,
209                                              u8 operation);
210 void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
211                                    enum nl80211_channel_type ch_type);
212 void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw);
213 u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw);
214 void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
215 void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw,
216                                          u16 beaconinterval);
217 void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
218 void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw);
219 void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
220 bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
221                                           enum radio_path rfpath);
222 bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw,
223                                               u32 rfpath);
224 bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
225                                           enum rf_pwrstate rfpwr_state);
226 void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw);
227 void rtl92c_phy_set_io(struct ieee80211_hw *hw);
228 void rtl92c_bb_block_on(struct ieee80211_hw *hw);
229 u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask);
230 long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
231                                   enum wireless_mode wirelessmode,
232                                   u8 txpwridx);
233 u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
234                                 enum wireless_mode wirelessmode,
235                                 long power_indbm);
236 void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
237 void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw);
238 bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
239                                       u8 channel, u8 *stage, u8 *step,
240                                       u32 *delay);
241 u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw);
242 u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
243                                   enum radio_path rfpath, u32 offset);
244 void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
245                                     enum radio_path rfpath, u32 offset,
246                                     u32 data);
247 u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
248                                enum radio_path rfpath, u32 offset);
249 void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
250                                  enum radio_path rfpath, u32 offset,
251                                  u32 data);
252 bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
253 void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
254                                             u32 regaddr, u32 bitmask,
255                                             u32 data);
256 bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
257
258 #endif