Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-3.10.git] / drivers / net / wireless / rtlwifi / rtl8192c / phy_common.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2009-2010  Realtek Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  * The full GNU General Public License is included in this distribution in the
19  * file called LICENSE.
20  *
21  * Contact Information:
22  * wlanfae <wlanfae@realtek.com>
23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24  * Hsinchu 300, Taiwan.
25  *
26  * Larry Finger <Larry.Finger@lwfinger.net>
27  *
28  *****************************************************************************/
29
30 #include "../wifi.h"
31 #include "../rtl8192ce/reg.h"
32 #include "../rtl8192ce/def.h"
33 #include "dm_common.h"
34 #include "phy_common.h"
35
36 /* Define macro to shorten lines */
37 #define MCS_TXPWR       mcs_txpwrlevel_origoffset
38
39 u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
40 {
41         struct rtl_priv *rtlpriv = rtl_priv(hw);
42         u32 returnvalue, originalvalue, bitshift;
43
44         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
45                                                "bitmask(%#x)\n", regaddr,
46                                                bitmask));
47         originalvalue = rtl_read_dword(rtlpriv, regaddr);
48         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
49         returnvalue = (originalvalue & bitmask) >> bitshift;
50
51         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("BBR MASK=0x%x "
52                                                "Addr[0x%x]=0x%x\n", bitmask,
53                                                regaddr, originalvalue));
54
55         return returnvalue;
56
57 }
58 EXPORT_SYMBOL(rtl92c_phy_query_bb_reg);
59
60 void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
61                            u32 regaddr, u32 bitmask, u32 data)
62 {
63         struct rtl_priv *rtlpriv = rtl_priv(hw);
64         u32 originalvalue, bitshift;
65
66         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
67                                                " data(%#x)\n", regaddr, bitmask,
68                                                data));
69
70         if (bitmask != MASKDWORD) {
71                 originalvalue = rtl_read_dword(rtlpriv, regaddr);
72                 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
73                 data = ((originalvalue & (~bitmask)) | (data << bitshift));
74         }
75
76         rtl_write_dword(rtlpriv, regaddr, data);
77
78         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
79                                                " data(%#x)\n", regaddr, bitmask,
80                                                data));
81
82 }
83 EXPORT_SYMBOL(rtl92c_phy_set_bb_reg);
84
85 u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
86                                   enum radio_path rfpath, u32 offset)
87 {
88         RT_ASSERT(false, ("deprecated!\n"));
89         return 0;
90
91 }
92 EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_read);
93
94 void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
95                                     enum radio_path rfpath, u32 offset,
96                                     u32 data)
97 {
98         RT_ASSERT(false, ("deprecated!\n"));
99 }
100 EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_write);
101
102 u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
103                                enum radio_path rfpath, u32 offset)
104 {
105         struct rtl_priv *rtlpriv = rtl_priv(hw);
106         struct rtl_phy *rtlphy = &(rtlpriv->phy);
107         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
108         u32 newoffset;
109         u32 tmplong, tmplong2;
110         u8 rfpi_enable = 0;
111         u32 retvalue;
112
113         offset &= 0x3f;
114         newoffset = offset;
115         if (RT_CANNOT_IO(hw)) {
116                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("return all one\n"));
117                 return 0xFFFFFFFF;
118         }
119         tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
120         if (rfpath == RF90_PATH_A)
121                 tmplong2 = tmplong;
122         else
123                 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
124         tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
125             (newoffset << 23) | BLSSIREADEDGE;
126         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
127                       tmplong & (~BLSSIREADEDGE));
128         mdelay(1);
129         rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
130         mdelay(1);
131         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
132                       tmplong | BLSSIREADEDGE);
133         mdelay(1);
134         if (rfpath == RF90_PATH_A)
135                 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
136                                                  BIT(8));
137         else if (rfpath == RF90_PATH_B)
138                 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
139                                                  BIT(8));
140         if (rfpi_enable)
141                 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
142                                          BLSSIREADBACKDATA);
143         else
144                 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
145                                          BLSSIREADBACKDATA);
146         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFR-%d Addr[0x%x]=0x%x\n",
147                                                rfpath, pphyreg->rflssi_readback,
148                                                retvalue));
149         return retvalue;
150 }
151 EXPORT_SYMBOL(_rtl92c_phy_rf_serial_read);
152
153 void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
154                                  enum radio_path rfpath, u32 offset,
155                                  u32 data)
156 {
157         u32 data_and_addr;
158         u32 newoffset;
159         struct rtl_priv *rtlpriv = rtl_priv(hw);
160         struct rtl_phy *rtlphy = &(rtlpriv->phy);
161         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
162
163         if (RT_CANNOT_IO(hw)) {
164                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("stop\n"));
165                 return;
166         }
167         offset &= 0x3f;
168         newoffset = offset;
169         data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
170         rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
171         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFW-%d Addr[0x%x]=0x%x\n",
172                                                rfpath, pphyreg->rf3wire_offset,
173                                                data_and_addr));
174 }
175 EXPORT_SYMBOL(_rtl92c_phy_rf_serial_write);
176
177 u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask)
178 {
179         u32 i;
180
181         for (i = 0; i <= 31; i++) {
182                 if (((bitmask >> i) & 0x1) == 1)
183                         break;
184         }
185         return i;
186 }
187 EXPORT_SYMBOL(_rtl92c_phy_calculate_bit_shift);
188
189 static void _rtl92c_phy_bb_config_1t(struct ieee80211_hw *hw)
190 {
191         rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
192         rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
193         rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
194         rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
195         rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
196         rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
197         rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
198         rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
199         rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
200         rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
201 }
202
203 bool rtl92c_phy_rf_config(struct ieee80211_hw *hw)
204 {
205         struct rtl_priv *rtlpriv = rtl_priv(hw);
206
207         return rtlpriv->cfg->ops->phy_rf6052_config(hw);
208 }
209 EXPORT_SYMBOL(rtl92c_phy_rf_config);
210
211 bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
212 {
213         struct rtl_priv *rtlpriv = rtl_priv(hw);
214         struct rtl_phy *rtlphy = &(rtlpriv->phy);
215         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
216         bool rtstatus;
217
218         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("==>\n"));
219         rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
220                                                  BASEBAND_CONFIG_PHY_REG);
221         if (rtstatus != true) {
222                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Write BB Reg Fail!!"));
223                 return false;
224         }
225         if (rtlphy->rf_type == RF_1T2R) {
226                 _rtl92c_phy_bb_config_1t(hw);
227                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Config to 1T!!\n"));
228         }
229         if (rtlefuse->autoload_failflag == false) {
230                 rtlphy->pwrgroup_cnt = 0;
231                 rtstatus = rtlpriv->cfg->ops->config_bb_with_pgheaderfile(hw,
232                                                    BASEBAND_CONFIG_PHY_REG);
233         }
234         if (rtstatus != true) {
235                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("BB_PG Reg Fail!!"));
236                 return false;
237         }
238         rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
239                                                  BASEBAND_CONFIG_AGC_TAB);
240         if (rtstatus != true) {
241                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("AGC Table Fail\n"));
242                 return false;
243         }
244         rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
245                                                 RFPGA0_XA_HSSIPARAMETER2,
246                                                 0x200));
247
248         return true;
249 }
250 EXPORT_SYMBOL(_rtl92c_phy_bb8192c_config_parafile);
251
252 void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
253                                             u32 regaddr, u32 bitmask,
254                                             u32 data)
255 {
256         struct rtl_priv *rtlpriv = rtl_priv(hw);
257         struct rtl_phy *rtlphy = &(rtlpriv->phy);
258
259         if (regaddr == RTXAGC_A_RATE18_06) {
260                 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][0] = data;
261                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
262                          ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
263                           rtlphy->pwrgroup_cnt,
264                           rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][0]));
265         }
266         if (regaddr == RTXAGC_A_RATE54_24) {
267                 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][1] = data;
268                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
269                          ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
270                           rtlphy->pwrgroup_cnt,
271                           rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][1]));
272         }
273         if (regaddr == RTXAGC_A_CCK1_MCS32) {
274                 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][6] = data;
275                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
276                          ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
277                           rtlphy->pwrgroup_cnt,
278                           rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][6]));
279         }
280         if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
281                 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][7] = data;
282                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
283                          ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
284                           rtlphy->pwrgroup_cnt,
285                           rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][7]));
286         }
287         if (regaddr == RTXAGC_A_MCS03_MCS00) {
288                 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][2] = data;
289                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
290                          ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
291                           rtlphy->pwrgroup_cnt,
292                           rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][2]));
293         }
294         if (regaddr == RTXAGC_A_MCS07_MCS04) {
295                 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][3] = data;
296                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
297                          ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
298                           rtlphy->pwrgroup_cnt,
299                           rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][3]));
300         }
301         if (regaddr == RTXAGC_A_MCS11_MCS08) {
302                 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][4] = data;
303                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
304                          ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
305                           rtlphy->pwrgroup_cnt,
306                           rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][4]));
307         }
308         if (regaddr == RTXAGC_A_MCS15_MCS12) {
309                 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][5] = data;
310                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
311                          ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
312                           rtlphy->pwrgroup_cnt,
313                           rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][5]));
314         }
315         if (regaddr == RTXAGC_B_RATE18_06) {
316                 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][8] = data;
317                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
318                          ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
319                           rtlphy->pwrgroup_cnt,
320                           rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][8]));
321         }
322         if (regaddr == RTXAGC_B_RATE54_24) {
323                 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][9] = data;
324                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
325                          ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
326                           rtlphy->pwrgroup_cnt,
327                           rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][9]));
328         }
329         if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
330                 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][14] = data;
331                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
332                          ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
333                           rtlphy->pwrgroup_cnt,
334                           rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][14]));
335         }
336         if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
337                 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][15] = data;
338                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
339                          ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
340                           rtlphy->pwrgroup_cnt,
341                           rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][15]));
342         }
343         if (regaddr == RTXAGC_B_MCS03_MCS00) {
344                 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][10] = data;
345                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
346                          ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
347                           rtlphy->pwrgroup_cnt,
348                           rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][10]));
349         }
350         if (regaddr == RTXAGC_B_MCS07_MCS04) {
351                 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][11] = data;
352                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
353                          ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
354                           rtlphy->pwrgroup_cnt,
355                           rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][11]));
356         }
357         if (regaddr == RTXAGC_B_MCS11_MCS08) {
358                 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][12] = data;
359                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
360                          ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
361                           rtlphy->pwrgroup_cnt,
362                           rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][12]));
363         }
364         if (regaddr == RTXAGC_B_MCS15_MCS12) {
365                 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][13] = data;
366                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
367                          ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
368                           rtlphy->pwrgroup_cnt,
369                           rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][13]));
370
371                 rtlphy->pwrgroup_cnt++;
372         }
373 }
374 EXPORT_SYMBOL(_rtl92c_store_pwrIndex_diffrate_offset);
375
376 void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
377 {
378         struct rtl_priv *rtlpriv = rtl_priv(hw);
379         struct rtl_phy *rtlphy = &(rtlpriv->phy);
380
381         rtlphy->default_initialgain[0] =
382             (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
383         rtlphy->default_initialgain[1] =
384             (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
385         rtlphy->default_initialgain[2] =
386             (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
387         rtlphy->default_initialgain[3] =
388             (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
389
390         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
391                  ("Default initial gain (c50=0x%x, "
392                   "c58=0x%x, c60=0x%x, c68=0x%x\n",
393                   rtlphy->default_initialgain[0],
394                   rtlphy->default_initialgain[1],
395                   rtlphy->default_initialgain[2],
396                   rtlphy->default_initialgain[3]));
397
398         rtlphy->framesync = (u8) rtl_get_bbreg(hw,
399                                                ROFDM0_RXDETECTOR3, MASKBYTE0);
400         rtlphy->framesync_c34 = rtl_get_bbreg(hw,
401                                               ROFDM0_RXDETECTOR2, MASKDWORD);
402
403         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
404                  ("Default framesync (0x%x) = 0x%x\n",
405                   ROFDM0_RXDETECTOR3, rtlphy->framesync));
406 }
407
408 void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
409 {
410         struct rtl_priv *rtlpriv = rtl_priv(hw);
411         struct rtl_phy *rtlphy = &(rtlpriv->phy);
412
413         rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
414         rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
415         rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
416         rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
417
418         rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
419         rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
420         rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
421         rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
422
423         rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
424         rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
425
426         rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
427         rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
428
429         rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
430             RFPGA0_XA_LSSIPARAMETER;
431         rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
432             RFPGA0_XB_LSSIPARAMETER;
433
434         rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER;
435         rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;
436         rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
437         rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
438
439         rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
440         rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
441         rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
442         rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
443
444         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
445         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
446
447         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
448         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
449
450         rtlphy->phyreg_def[RF90_PATH_A].rfswitch_control =
451             RFPGA0_XAB_SWITCHCONTROL;
452         rtlphy->phyreg_def[RF90_PATH_B].rfswitch_control =
453             RFPGA0_XAB_SWITCHCONTROL;
454         rtlphy->phyreg_def[RF90_PATH_C].rfswitch_control =
455             RFPGA0_XCD_SWITCHCONTROL;
456         rtlphy->phyreg_def[RF90_PATH_D].rfswitch_control =
457             RFPGA0_XCD_SWITCHCONTROL;
458
459         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
460         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
461         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
462         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
463
464         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
465         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
466         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
467         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
468
469         rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbalance =
470             ROFDM0_XARXIQIMBALANCE;
471         rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbalance =
472             ROFDM0_XBRXIQIMBALANCE;
473         rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbalance =
474             ROFDM0_XCRXIQIMBANLANCE;
475         rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbalance =
476             ROFDM0_XDRXIQIMBALANCE;
477
478         rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
479         rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
480         rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
481         rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
482
483         rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbalance =
484             ROFDM0_XATXIQIMBALANCE;
485         rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbalance =
486             ROFDM0_XBTXIQIMBALANCE;
487         rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbalance =
488             ROFDM0_XCTXIQIMBALANCE;
489         rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbalance =
490             ROFDM0_XDTXIQIMBALANCE;
491
492         rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
493         rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
494         rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
495         rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
496
497         rtlphy->phyreg_def[RF90_PATH_A].rflssi_readback =
498             RFPGA0_XA_LSSIREADBACK;
499         rtlphy->phyreg_def[RF90_PATH_B].rflssi_readback =
500             RFPGA0_XB_LSSIREADBACK;
501         rtlphy->phyreg_def[RF90_PATH_C].rflssi_readback =
502             RFPGA0_XC_LSSIREADBACK;
503         rtlphy->phyreg_def[RF90_PATH_D].rflssi_readback =
504             RFPGA0_XD_LSSIREADBACK;
505
506         rtlphy->phyreg_def[RF90_PATH_A].rflssi_readbackpi =
507             TRANSCEIVEA_HSPI_READBACK;
508         rtlphy->phyreg_def[RF90_PATH_B].rflssi_readbackpi =
509             TRANSCEIVEB_HSPI_READBACK;
510
511 }
512 EXPORT_SYMBOL(_rtl92c_phy_init_bb_rf_register_definition);
513
514 void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
515 {
516         struct rtl_priv *rtlpriv = rtl_priv(hw);
517         struct rtl_phy *rtlphy = &(rtlpriv->phy);
518         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
519         u8 txpwr_level;
520         long txpwr_dbm;
521
522         txpwr_level = rtlphy->cur_cck_txpwridx;
523         txpwr_dbm = _rtl92c_phy_txpwr_idx_to_dbm(hw,
524                                                  WIRELESS_MODE_B, txpwr_level);
525         txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
526             rtlefuse->legacy_ht_txpowerdiff;
527         if (_rtl92c_phy_txpwr_idx_to_dbm(hw,
528                                          WIRELESS_MODE_G,
529                                          txpwr_level) > txpwr_dbm)
530                 txpwr_dbm =
531                     _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
532                                                  txpwr_level);
533         txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
534         if (_rtl92c_phy_txpwr_idx_to_dbm(hw,
535                                          WIRELESS_MODE_N_24G,
536                                          txpwr_level) > txpwr_dbm)
537                 txpwr_dbm =
538                     _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
539                                                  txpwr_level);
540         *powerlevel = txpwr_dbm;
541 }
542
543 static void _rtl92c_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
544                                       u8 *cckpowerlevel, u8 *ofdmpowerlevel)
545 {
546         struct rtl_priv *rtlpriv = rtl_priv(hw);
547         struct rtl_phy *rtlphy = &(rtlpriv->phy);
548         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
549         u8 index = (channel - 1);
550
551         cckpowerlevel[RF90_PATH_A] =
552             rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
553         cckpowerlevel[RF90_PATH_B] =
554             rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
555         if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
556                 ofdmpowerlevel[RF90_PATH_A] =
557                     rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
558                 ofdmpowerlevel[RF90_PATH_B] =
559                     rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
560         } else if (get_rf_type(rtlphy) == RF_2T2R) {
561                 ofdmpowerlevel[RF90_PATH_A] =
562                     rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
563                 ofdmpowerlevel[RF90_PATH_B] =
564                     rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
565         }
566 }
567
568 static void _rtl92c_ccxpower_index_check(struct ieee80211_hw *hw,
569                                          u8 channel, u8 *cckpowerlevel,
570                                          u8 *ofdmpowerlevel)
571 {
572         struct rtl_priv *rtlpriv = rtl_priv(hw);
573         struct rtl_phy *rtlphy = &(rtlpriv->phy);
574
575         rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
576         rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
577
578 }
579
580 void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
581 {
582         struct rtl_priv *rtlpriv = rtl_priv(hw);
583         struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
584         u8 cckpowerlevel[2], ofdmpowerlevel[2];
585
586         if (rtlefuse->txpwr_fromeprom == false)
587                 return;
588         _rtl92c_get_txpower_index(hw, channel,
589                                   &cckpowerlevel[0], &ofdmpowerlevel[0]);
590         _rtl92c_ccxpower_index_check(hw,
591                                      channel, &cckpowerlevel[0],
592                                      &ofdmpowerlevel[0]);
593         rtlpriv->cfg->ops->phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
594         rtlpriv->cfg->ops->phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0],
595                                                        channel);
596 }
597 EXPORT_SYMBOL(rtl92c_phy_set_txpower_level);
598
599 bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
600 {
601         struct rtl_priv *rtlpriv = rtl_priv(hw);
602         struct rtl_phy *rtlphy = &(rtlpriv->phy);
603         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
604         u8 idx;
605         u8 rf_path;
606         u8 ccktxpwridx = _rtl92c_phy_dbm_to_txpwr_Idx(hw,
607                                                       WIRELESS_MODE_B,
608                                                       power_indbm);
609         u8 ofdmtxpwridx = _rtl92c_phy_dbm_to_txpwr_Idx(hw,
610                                                        WIRELESS_MODE_N_24G,
611                                                        power_indbm);
612         if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
613                 ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
614         else
615                 ofdmtxpwridx = 0;
616         RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
617                  ("%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
618                   power_indbm, ccktxpwridx, ofdmtxpwridx));
619         for (idx = 0; idx < 14; idx++) {
620                 for (rf_path = 0; rf_path < 2; rf_path++) {
621                         rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
622                         rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
623                             ofdmtxpwridx;
624                         rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
625                             ofdmtxpwridx;
626                 }
627         }
628         rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
629         return true;
630 }
631 EXPORT_SYMBOL(rtl92c_phy_update_txpower_dbm);
632
633 u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
634                                 enum wireless_mode wirelessmode,
635                                 long power_indbm)
636 {
637         u8 txpwridx;
638         long offset;
639
640         switch (wirelessmode) {
641         case WIRELESS_MODE_B:
642                 offset = -7;
643                 break;
644         case WIRELESS_MODE_G:
645         case WIRELESS_MODE_N_24G:
646                 offset = -8;
647                 break;
648         default:
649                 offset = -8;
650                 break;
651         }
652
653         if ((power_indbm - offset) > 0)
654                 txpwridx = (u8) ((power_indbm - offset) * 2);
655         else
656                 txpwridx = 0;
657
658         if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
659                 txpwridx = MAX_TXPWR_IDX_NMODE_92S;
660
661         return txpwridx;
662 }
663 EXPORT_SYMBOL(_rtl92c_phy_dbm_to_txpwr_Idx);
664
665 long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
666                                   enum wireless_mode wirelessmode,
667                                   u8 txpwridx)
668 {
669         long offset;
670         long pwrout_dbm;
671
672         switch (wirelessmode) {
673         case WIRELESS_MODE_B:
674                 offset = -7;
675                 break;
676         case WIRELESS_MODE_G:
677         case WIRELESS_MODE_N_24G:
678                 offset = -8;
679                 break;
680         default:
681                 offset = -8;
682                 break;
683         }
684         pwrout_dbm = txpwridx / 2 + offset;
685         return pwrout_dbm;
686 }
687 EXPORT_SYMBOL(_rtl92c_phy_txpwr_idx_to_dbm);
688
689 void rtl92c_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
690 {
691         struct rtl_priv *rtlpriv = rtl_priv(hw);
692         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
693         enum io_type iotype;
694
695         if (!is_hal_stop(rtlhal)) {
696                 switch (operation) {
697                 case SCAN_OPT_BACKUP:
698                         iotype = IO_CMD_PAUSE_DM_BY_SCAN;
699                         rtlpriv->cfg->ops->set_hw_reg(hw,
700                                                       HW_VAR_IO_CMD,
701                                                       (u8 *)&iotype);
702
703                         break;
704                 case SCAN_OPT_RESTORE:
705                         iotype = IO_CMD_RESUME_DM_BY_SCAN;
706                         rtlpriv->cfg->ops->set_hw_reg(hw,
707                                                       HW_VAR_IO_CMD,
708                                                       (u8 *)&iotype);
709                         break;
710                 default:
711                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
712                                  ("Unknown Scan Backup operation.\n"));
713                         break;
714                 }
715         }
716 }
717 EXPORT_SYMBOL(rtl92c_phy_scan_operation_backup);
718
719 void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
720                             enum nl80211_channel_type ch_type)
721 {
722         struct rtl_priv *rtlpriv = rtl_priv(hw);
723         struct rtl_phy *rtlphy = &(rtlpriv->phy);
724         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
725         u8 tmp_bw = rtlphy->current_chan_bw;
726
727         if (rtlphy->set_bwmode_inprogress)
728                 return;
729         rtlphy->set_bwmode_inprogress = true;
730         if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
731                 rtlphy->set_bwmode_inprogress = false;
732         } else {
733                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
734                          ("FALSE driver sleep or unload\n"));
735                 rtlphy->set_bwmode_inprogress = false;
736                 rtlphy->current_chan_bw = tmp_bw;
737         }
738 }
739 EXPORT_SYMBOL(rtl92c_phy_set_bw_mode);
740
741 void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw)
742 {
743         struct rtl_priv *rtlpriv = rtl_priv(hw);
744         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
745         struct rtl_phy *rtlphy = &(rtlpriv->phy);
746         u32 delay;
747
748         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
749                  ("switch to channel%d\n", rtlphy->current_channel));
750         if (is_hal_stop(rtlhal))
751                 return;
752         do {
753                 if (!rtlphy->sw_chnl_inprogress)
754                         break;
755                 if (!_rtl92c_phy_sw_chnl_step_by_step
756                     (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
757                      &rtlphy->sw_chnl_step, &delay)) {
758                         if (delay > 0)
759                                 mdelay(delay);
760                         else
761                                 continue;
762                 } else {
763                         rtlphy->sw_chnl_inprogress = false;
764                 }
765                 break;
766         } while (true);
767         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
768 }
769 EXPORT_SYMBOL(rtl92c_phy_sw_chnl_callback);
770
771 u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw)
772 {
773         struct rtl_priv *rtlpriv = rtl_priv(hw);
774         struct rtl_phy *rtlphy = &(rtlpriv->phy);
775         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
776
777         if (rtlphy->sw_chnl_inprogress)
778                 return 0;
779         if (rtlphy->set_bwmode_inprogress)
780                 return 0;
781         RT_ASSERT((rtlphy->current_channel <= 14),
782                   ("WIRELESS_MODE_G but channel>14"));
783         rtlphy->sw_chnl_inprogress = true;
784         rtlphy->sw_chnl_stage = 0;
785         rtlphy->sw_chnl_step = 0;
786         if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
787                 rtl92c_phy_sw_chnl_callback(hw);
788                 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
789                          ("sw_chnl_inprogress false schdule workitem\n"));
790                 rtlphy->sw_chnl_inprogress = false;
791         } else {
792                 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
793                          ("sw_chnl_inprogress false driver sleep or"
794                           " unload\n"));
795                 rtlphy->sw_chnl_inprogress = false;
796         }
797         return 1;
798 }
799 EXPORT_SYMBOL(rtl92c_phy_sw_chnl);
800
801 static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
802                                              u32 cmdtableidx, u32 cmdtablesz,
803                                              enum swchnlcmd_id cmdid,
804                                              u32 para1, u32 para2, u32 msdelay)
805 {
806         struct swchnlcmd *pcmd;
807
808         if (cmdtable == NULL) {
809                 RT_ASSERT(false, ("cmdtable cannot be NULL.\n"));
810                 return false;
811         }
812
813         if (cmdtableidx >= cmdtablesz)
814                 return false;
815
816         pcmd = cmdtable + cmdtableidx;
817         pcmd->cmdid = cmdid;
818         pcmd->para1 = para1;
819         pcmd->para2 = para2;
820         pcmd->msdelay = msdelay;
821         return true;
822 }
823
824 bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
825                                       u8 channel, u8 *stage, u8 *step,
826                                       u32 *delay)
827 {
828         struct rtl_priv *rtlpriv = rtl_priv(hw);
829         struct rtl_phy *rtlphy = &(rtlpriv->phy);
830         struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
831         u32 precommoncmdcnt;
832         struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
833         u32 postcommoncmdcnt;
834         struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
835         u32 rfdependcmdcnt;
836         struct swchnlcmd *currentcmd = NULL;
837         u8 rfpath;
838         u8 num_total_rfpath = rtlphy->num_total_rfpath;
839
840         precommoncmdcnt = 0;
841         _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
842                                          MAX_PRECMD_CNT,
843                                          CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
844         _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
845                                          MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
846
847         postcommoncmdcnt = 0;
848
849         _rtl92c_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
850                                          MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
851
852         rfdependcmdcnt = 0;
853
854         RT_ASSERT((channel >= 1 && channel <= 14),
855                   ("illegal channel for Zebra: %d\n", channel));
856
857         _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
858                                          MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
859                                          RF_CHNLBW, channel, 10);
860
861         _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
862                                          MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
863                                          0);
864
865         do {
866                 switch (*stage) {
867                 case 0:
868                         currentcmd = &precommoncmd[*step];
869                         break;
870                 case 1:
871                         currentcmd = &rfdependcmd[*step];
872                         break;
873                 case 2:
874                         currentcmd = &postcommoncmd[*step];
875                         break;
876                 }
877
878                 if (currentcmd->cmdid == CMDID_END) {
879                         if ((*stage) == 2) {
880                                 return true;
881                         } else {
882                                 (*stage)++;
883                                 (*step) = 0;
884                                 continue;
885                         }
886                 }
887
888                 switch (currentcmd->cmdid) {
889                 case CMDID_SET_TXPOWEROWER_LEVEL:
890                         rtl92c_phy_set_txpower_level(hw, channel);
891                         break;
892                 case CMDID_WRITEPORT_ULONG:
893                         rtl_write_dword(rtlpriv, currentcmd->para1,
894                                         currentcmd->para2);
895                         break;
896                 case CMDID_WRITEPORT_USHORT:
897                         rtl_write_word(rtlpriv, currentcmd->para1,
898                                        (u16) currentcmd->para2);
899                         break;
900                 case CMDID_WRITEPORT_UCHAR:
901                         rtl_write_byte(rtlpriv, currentcmd->para1,
902                                        (u8) currentcmd->para2);
903                         break;
904                 case CMDID_RF_WRITEREG:
905                         for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
906                                 rtlphy->rfreg_chnlval[rfpath] =
907                                     ((rtlphy->rfreg_chnlval[rfpath] &
908                                       0xfffffc00) | currentcmd->para2);
909
910                                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
911                                               currentcmd->para1,
912                                               RFREG_OFFSET_MASK,
913                                               rtlphy->rfreg_chnlval[rfpath]);
914                         }
915                         break;
916                 default:
917                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
918                                  ("switch case not process\n"));
919                         break;
920                 }
921
922                 break;
923         } while (true);
924
925         (*delay) = currentcmd->msdelay;
926         (*step)++;
927         return false;
928 }
929
930 bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, u32 rfpath)
931 {
932         return true;
933 }
934 EXPORT_SYMBOL(rtl8192_phy_check_is_legal_rfpath);
935
936 static u8 _rtl92c_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
937 {
938         u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
939         u8 result = 0x00;
940
941         rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
942         rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
943         rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
944         rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
945                       config_pathb ? 0x28160202 : 0x28160502);
946
947         if (config_pathb) {
948                 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
949                 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
950                 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
951                 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
952         }
953
954         rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
955         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
956         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
957
958         mdelay(IQK_DELAY_TIME);
959
960         reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
961         reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
962         reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
963         reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
964
965         if (!(reg_eac & BIT(28)) &&
966             (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
967             (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
968                 result |= 0x01;
969         else
970                 return result;
971
972         if (!(reg_eac & BIT(27)) &&
973             (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
974             (((reg_eac & 0x03FF0000) >> 16) != 0x36))
975                 result |= 0x02;
976         return result;
977 }
978
979 static u8 _rtl92c_phy_path_b_iqk(struct ieee80211_hw *hw)
980 {
981         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
982         u8 result = 0x00;
983
984         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
985         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
986         mdelay(IQK_DELAY_TIME);
987         reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
988         reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
989         reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
990         reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
991         reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
992
993         if (!(reg_eac & BIT(31)) &&
994             (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
995             (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
996                 result |= 0x01;
997         else
998                 return result;
999         if (!(reg_eac & BIT(30)) &&
1000             (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
1001             (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
1002                 result |= 0x02;
1003         return result;
1004 }
1005
1006 static void _rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
1007                                                bool iqk_ok, long result[][8],
1008                                                u8 final_candidate, bool btxonly)
1009 {
1010         u32 oldval_0, x, tx0_a, reg;
1011         long y, tx0_c;
1012
1013         if (final_candidate == 0xFF) {
1014                 return;
1015         } else if (iqk_ok) {
1016                 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1017                                           MASKDWORD) >> 22) & 0x3FF;
1018                 x = result[final_candidate][0];
1019                 if ((x & 0x00000200) != 0)
1020                         x = x | 0xFFFFFC00;
1021                 tx0_a = (x * oldval_0) >> 8;
1022                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
1023                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
1024                               ((x * oldval_0 >> 7) & 0x1));
1025                 y = result[final_candidate][1];
1026                 if ((y & 0x00000200) != 0)
1027                         y = y | 0xFFFFFC00;
1028                 tx0_c = (y * oldval_0) >> 8;
1029                 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
1030                               ((tx0_c & 0x3C0) >> 6));
1031                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
1032                               (tx0_c & 0x3F));
1033                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
1034                               ((y * oldval_0 >> 7) & 0x1));
1035                 if (btxonly)
1036                         return;
1037                 reg = result[final_candidate][2];
1038                 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1039                 reg = result[final_candidate][3] & 0x3F;
1040                 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1041                 reg = (result[final_candidate][3] >> 6) & 0xF;
1042                 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1043         }
1044 }
1045
1046 static void _rtl92c_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
1047                                                bool iqk_ok, long result[][8],
1048                                                u8 final_candidate, bool btxonly)
1049 {
1050         u32 oldval_1, x, tx1_a, reg;
1051         long y, tx1_c;
1052
1053         if (final_candidate == 0xFF) {
1054                 return;
1055         } else if (iqk_ok) {
1056                 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
1057                                           MASKDWORD) >> 22) & 0x3FF;
1058                 x = result[final_candidate][4];
1059                 if ((x & 0x00000200) != 0)
1060                         x = x | 0xFFFFFC00;
1061                 tx1_a = (x * oldval_1) >> 8;
1062                 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
1063                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
1064                               ((x * oldval_1 >> 7) & 0x1));
1065                 y = result[final_candidate][5];
1066                 if ((y & 0x00000200) != 0)
1067                         y = y | 0xFFFFFC00;
1068                 tx1_c = (y * oldval_1) >> 8;
1069                 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
1070                               ((tx1_c & 0x3C0) >> 6));
1071                 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
1072                               (tx1_c & 0x3F));
1073                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
1074                               ((y * oldval_1 >> 7) & 0x1));
1075                 if (btxonly)
1076                         return;
1077                 reg = result[final_candidate][6];
1078                 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
1079                 reg = result[final_candidate][7] & 0x3F;
1080                 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
1081                 reg = (result[final_candidate][7] >> 6) & 0xF;
1082                 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
1083         }
1084 }
1085
1086 static void _rtl92c_phy_save_adda_registers(struct ieee80211_hw *hw,
1087                                             u32 *addareg, u32 *addabackup,
1088                                             u32 registernum)
1089 {
1090         u32 i;
1091
1092         for (i = 0; i < registernum; i++)
1093                 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1094 }
1095
1096 static void _rtl92c_phy_save_mac_registers(struct ieee80211_hw *hw,
1097                                            u32 *macreg, u32 *macbackup)
1098 {
1099         struct rtl_priv *rtlpriv = rtl_priv(hw);
1100         u32 i;
1101
1102         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1103                 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1104         macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1105 }
1106
1107 static void _rtl92c_phy_reload_adda_registers(struct ieee80211_hw *hw,
1108                                               u32 *addareg, u32 *addabackup,
1109                                               u32 regiesternum)
1110 {
1111         u32 i;
1112
1113         for (i = 0; i < regiesternum; i++)
1114                 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1115 }
1116
1117 static void _rtl92c_phy_reload_mac_registers(struct ieee80211_hw *hw,
1118                                              u32 *macreg, u32 *macbackup)
1119 {
1120         struct rtl_priv *rtlpriv = rtl_priv(hw);
1121         u32 i;
1122
1123         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1124                 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1125         rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1126 }
1127
1128 static void _rtl92c_phy_path_adda_on(struct ieee80211_hw *hw,
1129                                      u32 *addareg, bool is_patha_on, bool is2t)
1130 {
1131         u32 pathOn;
1132         u32 i;
1133
1134         pathOn = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1135         if (false == is2t) {
1136                 pathOn = 0x0bdb25a0;
1137                 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1138         } else {
1139                 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn);
1140         }
1141
1142         for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1143                 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn);
1144 }
1145
1146 static void _rtl92c_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1147                                                 u32 *macreg, u32 *macbackup)
1148 {
1149         struct rtl_priv *rtlpriv = rtl_priv(hw);
1150         u32 i;
1151
1152         rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1153
1154         for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1155                 rtl_write_byte(rtlpriv, macreg[i],
1156                                (u8) (macbackup[i] & (~BIT(3))));
1157         rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1158 }
1159
1160 static void _rtl92c_phy_path_a_standby(struct ieee80211_hw *hw)
1161 {
1162         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1163         rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1164         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1165 }
1166
1167 static void _rtl92c_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1168 {
1169         u32 mode;
1170
1171         mode = pi_mode ? 0x01000100 : 0x01000000;
1172         rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1173         rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1174 }
1175
1176 static bool _rtl92c_phy_simularity_compare(struct ieee80211_hw *hw,
1177                                            long result[][8], u8 c1, u8 c2)
1178 {
1179         u32 i, j, diff, simularity_bitmap, bound;
1180         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1181
1182         u8 final_candidate[2] = { 0xFF, 0xFF };
1183         bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version);
1184
1185         if (is2t)
1186                 bound = 8;
1187         else
1188                 bound = 4;
1189
1190         simularity_bitmap = 0;
1191
1192         for (i = 0; i < bound; i++) {
1193                 diff = (result[c1][i] > result[c2][i]) ?
1194                     (result[c1][i] - result[c2][i]) :
1195                     (result[c2][i] - result[c1][i]);
1196
1197                 if (diff > MAX_TOLERANCE) {
1198                         if ((i == 2 || i == 6) && !simularity_bitmap) {
1199                                 if (result[c1][i] + result[c1][i + 1] == 0)
1200                                         final_candidate[(i / 4)] = c2;
1201                                 else if (result[c2][i] + result[c2][i + 1] == 0)
1202                                         final_candidate[(i / 4)] = c1;
1203                                 else
1204                                         simularity_bitmap = simularity_bitmap |
1205                                             (1 << i);
1206                         } else
1207                                 simularity_bitmap =
1208                                     simularity_bitmap | (1 << i);
1209                 }
1210         }
1211
1212         if (simularity_bitmap == 0) {
1213                 for (i = 0; i < (bound / 4); i++) {
1214                         if (final_candidate[i] != 0xFF) {
1215                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1216                                         result[3][j] =
1217                                             result[final_candidate[i]][j];
1218                                 bresult = false;
1219                         }
1220                 }
1221                 return bresult;
1222         } else if (!(simularity_bitmap & 0x0F)) {
1223                 for (i = 0; i < 4; i++)
1224                         result[3][i] = result[c1][i];
1225                 return false;
1226         } else if (!(simularity_bitmap & 0xF0) && is2t) {
1227                 for (i = 4; i < 8; i++)
1228                         result[3][i] = result[c1][i];
1229                 return false;
1230         } else {
1231                 return false;
1232         }
1233
1234 }
1235
1236 static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
1237                                      long result[][8], u8 t, bool is2t)
1238 {
1239         struct rtl_priv *rtlpriv = rtl_priv(hw);
1240         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1241         u32 i;
1242         u8 patha_ok, pathb_ok;
1243         u32 adda_reg[IQK_ADDA_REG_NUM] = {
1244                 0x85c, 0xe6c, 0xe70, 0xe74,
1245                 0xe78, 0xe7c, 0xe80, 0xe84,
1246                 0xe88, 0xe8c, 0xed0, 0xed4,
1247                 0xed8, 0xedc, 0xee0, 0xeec
1248         };
1249
1250         u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1251                 0x522, 0x550, 0x551, 0x040
1252         };
1253
1254         const u32 retrycount = 2;
1255
1256         u32 bbvalue;
1257
1258         if (t == 0) {
1259                 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD);
1260
1261                 _rtl92c_phy_save_adda_registers(hw, adda_reg,
1262                                                 rtlphy->adda_backup, 16);
1263                 _rtl92c_phy_save_mac_registers(hw, iqk_mac_reg,
1264                                                rtlphy->iqk_mac_backup);
1265         }
1266         _rtl92c_phy_path_adda_on(hw, adda_reg, true, is2t);
1267         if (t == 0) {
1268                 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1269                                                    RFPGA0_XA_HSSIPARAMETER1,
1270                                                    BIT(8));
1271         }
1272
1273         if (!rtlphy->rfpi_enable)
1274                 _rtl92c_phy_pi_mode_switch(hw, true);
1275         if (t == 0) {
1276                 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1277                 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
1278                 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
1279         }
1280         rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1281         rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1282         rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1283         if (is2t) {
1284                 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1285                 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1286         }
1287         _rtl92c_phy_mac_setting_calibration(hw, iqk_mac_reg,
1288                                             rtlphy->iqk_mac_backup);
1289         rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
1290         if (is2t)
1291                 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
1292         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1293         rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1294         rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1295         for (i = 0; i < retrycount; i++) {
1296                 patha_ok = _rtl92c_phy_path_a_iqk(hw, is2t);
1297                 if (patha_ok == 0x03) {
1298                         result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1299                                         0x3FF0000) >> 16;
1300                         result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1301                                         0x3FF0000) >> 16;
1302                         result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1303                                         0x3FF0000) >> 16;
1304                         result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1305                                         0x3FF0000) >> 16;
1306                         break;
1307                 } else if (i == (retrycount - 1) && patha_ok == 0x01)
1308
1309                         result[t][0] = (rtl_get_bbreg(hw, 0xe94,
1310                                                       MASKDWORD) & 0x3FF0000) >>
1311                             16;
1312                 result[t][1] =
1313                     (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
1314
1315         }
1316
1317         if (is2t) {
1318                 _rtl92c_phy_path_a_standby(hw);
1319                 _rtl92c_phy_path_adda_on(hw, adda_reg, false, is2t);
1320                 for (i = 0; i < retrycount; i++) {
1321                         pathb_ok = _rtl92c_phy_path_b_iqk(hw);
1322                         if (pathb_ok == 0x03) {
1323                                 result[t][4] = (rtl_get_bbreg(hw,
1324                                                       0xeb4,
1325                                                       MASKDWORD) &
1326                                                 0x3FF0000) >> 16;
1327                                 result[t][5] =
1328                                     (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1329                                      0x3FF0000) >> 16;
1330                                 result[t][6] =
1331                                     (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1332                                      0x3FF0000) >> 16;
1333                                 result[t][7] =
1334                                     (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1335                                      0x3FF0000) >> 16;
1336                                 break;
1337                         } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1338                                 result[t][4] = (rtl_get_bbreg(hw,
1339                                                       0xeb4,
1340                                                       MASKDWORD) &
1341                                                 0x3FF0000) >> 16;
1342                         }
1343                         result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1344                                         0x3FF0000) >> 16;
1345                 }
1346         }
1347         rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
1348         rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
1349         rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
1350         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1351         rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1352         if (is2t)
1353                 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1354         if (t != 0) {
1355                 if (!rtlphy->rfpi_enable)
1356                         _rtl92c_phy_pi_mode_switch(hw, false);
1357                 _rtl92c_phy_reload_adda_registers(hw, adda_reg,
1358                                                   rtlphy->adda_backup, 16);
1359                 _rtl92c_phy_reload_mac_registers(hw, iqk_mac_reg,
1360                                                  rtlphy->iqk_mac_backup);
1361         }
1362 }
1363
1364 static void _rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw,
1365                                      char delta, bool is2t)
1366 {
1367 #if 0 /* This routine is deliberately dummied out for later fixes */
1368         struct rtl_priv *rtlpriv = rtl_priv(hw);
1369         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1370         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1371
1372         u32 reg_d[PATH_NUM];
1373         u32 tmpreg, index, offset, path, i, pathbound = PATH_NUM, apkbound;
1374
1375         u32 bb_backup[APK_BB_REG_NUM];
1376         u32 bb_reg[APK_BB_REG_NUM] = {
1377                 0x904, 0xc04, 0x800, 0xc08, 0x874
1378         };
1379         u32 bb_ap_mode[APK_BB_REG_NUM] = {
1380                 0x00000020, 0x00a05430, 0x02040000,
1381                 0x000800e4, 0x00204000
1382         };
1383         u32 bb_normal_ap_mode[APK_BB_REG_NUM] = {
1384                 0x00000020, 0x00a05430, 0x02040000,
1385                 0x000800e4, 0x22204000
1386         };
1387
1388         u32 afe_backup[APK_AFE_REG_NUM];
1389         u32 afe_reg[APK_AFE_REG_NUM] = {
1390                 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78,
1391                 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c,
1392                 0xed0, 0xed4, 0xed8, 0xedc, 0xee0,
1393                 0xeec
1394         };
1395
1396         u32 mac_backup[IQK_MAC_REG_NUM];
1397         u32 mac_reg[IQK_MAC_REG_NUM] = {
1398                 0x522, 0x550, 0x551, 0x040
1399         };
1400
1401         u32 apk_rf_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1402                 {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
1403                 {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
1404         };
1405
1406         u32 apk_normal_rf_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1407                 {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c},
1408                 {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
1409         };
1410
1411         u32 apk_rf_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1412                 {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
1413                 {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
1414         };
1415
1416         u32 apk_normal_rf_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1417                 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a},
1418                 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
1419         };
1420
1421         u32 afe_on_off[PATH_NUM] = {
1422                 0x04db25a4, 0x0b1b25a4
1423         };
1424
1425         const u32 apk_offset[PATH_NUM] = { 0xb68, 0xb6c };
1426
1427         u32 apk_normal_offset[PATH_NUM] = { 0xb28, 0xb98 };
1428
1429         u32 apk_value[PATH_NUM] = { 0x92fc0000, 0x12fc0000 };
1430
1431         u32 apk_normal_value[PATH_NUM] = { 0x92680000, 0x12680000 };
1432
1433         const char apk_delta_mapping[APK_BB_REG_NUM][13] = {
1434                 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1435                 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1436                 {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1437                 {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1438                 {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
1439         };
1440
1441         const u32 apk_normal_setting_value_1[13] = {
1442                 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
1443                 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
1444                 0x12680000, 0x00880000, 0x00880000
1445         };
1446
1447         const u32 apk_normal_setting_value_2[16] = {
1448                 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
1449                 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
1450                 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
1451                 0x00050006
1452         };
1453
1454         u32 apk_result[PATH_NUM][APK_BB_REG_NUM];
1455
1456         long bb_offset, delta_v, delta_offset;
1457
1458         if (!is2t)
1459                 pathbound = 1;
1460
1461         return;
1462
1463         for (index = 0; index < PATH_NUM; index++) {
1464                 apk_offset[index] = apk_normal_offset[index];
1465                 apk_value[index] = apk_normal_value[index];
1466                 afe_on_off[index] = 0x6fdb25a4;
1467         }
1468
1469         for (index = 0; index < APK_BB_REG_NUM; index++) {
1470                 for (path = 0; path < pathbound; path++) {
1471                         apk_rf_init_value[path][index] =
1472                             apk_normal_rf_init_value[path][index];
1473                         apk_rf_value_0[path][index] =
1474                             apk_normal_rf_value_0[path][index];
1475                 }
1476                 bb_ap_mode[index] = bb_normal_ap_mode[index];
1477
1478                 apkbound = 6;
1479         }
1480
1481         for (index = 0; index < APK_BB_REG_NUM; index++) {
1482                 if (index == 0)
1483                         continue;
1484                 bb_backup[index] = rtl_get_bbreg(hw, bb_reg[index], MASKDWORD);
1485         }
1486
1487         _rtl92c_phy_save_mac_registers(hw, mac_reg, mac_backup);
1488
1489         _rtl92c_phy_save_adda_registers(hw, afe_reg, afe_backup, 16);
1490
1491         for (path = 0; path < pathbound; path++) {
1492                 if (path == RF90_PATH_A) {
1493                         offset = 0xb00;
1494                         for (index = 0; index < 11; index++) {
1495                                 rtl_set_bbreg(hw, offset, MASKDWORD,
1496                                               apk_normal_setting_value_1
1497                                               [index]);
1498
1499                                 offset += 0x04;
1500                         }
1501
1502                         rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000);
1503
1504                         offset = 0xb68;
1505                         for (; index < 13; index++) {
1506                                 rtl_set_bbreg(hw, offset, MASKDWORD,
1507                                               apk_normal_setting_value_1
1508                                               [index]);
1509
1510                                 offset += 0x04;
1511                         }
1512
1513                         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000);
1514
1515                         offset = 0xb00;
1516                         for (index = 0; index < 16; index++) {
1517                                 rtl_set_bbreg(hw, offset, MASKDWORD,
1518                                               apk_normal_setting_value_2
1519                                               [index]);
1520
1521                                 offset += 0x04;
1522                         }
1523                         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1524                 } else if (path == RF90_PATH_B) {
1525                         offset = 0xb70;
1526                         for (index = 0; index < 10; index++) {
1527                                 rtl_set_bbreg(hw, offset, MASKDWORD,
1528                                               apk_normal_setting_value_1
1529                                               [index]);
1530
1531                                 offset += 0x04;
1532                         }
1533                         rtl_set_bbreg(hw, 0xb28, MASKDWORD, 0x12680000);
1534                         rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000);
1535
1536                         offset = 0xb68;
1537                         index = 11;
1538                         for (; index < 13; index++) {
1539                                 rtl_set_bbreg(hw, offset, MASKDWORD,
1540                                               apk_normal_setting_value_1
1541                                               [index]);
1542
1543                                 offset += 0x04;
1544                         }
1545
1546                         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000);
1547
1548                         offset = 0xb60;
1549                         for (index = 0; index < 16; index++) {
1550                                 rtl_set_bbreg(hw, offset, MASKDWORD,
1551                                               apk_normal_setting_value_2
1552                                               [index]);
1553
1554                                 offset += 0x04;
1555                         }
1556                         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1557                 }
1558
1559                 reg_d[path] = rtl_get_rfreg(hw, (enum radio_path)path,
1560                                             0xd, MASKDWORD);
1561
1562                 for (index = 0; index < APK_AFE_REG_NUM; index++)
1563                         rtl_set_bbreg(hw, afe_reg[index], MASKDWORD,
1564                                       afe_on_off[path]);
1565
1566                 if (path == RF90_PATH_A) {
1567                         for (index = 0; index < APK_BB_REG_NUM; index++) {
1568                                 if (index == 0)
1569                                         continue;
1570                                 rtl_set_bbreg(hw, bb_reg[index], MASKDWORD,
1571                                               bb_ap_mode[index]);
1572                         }
1573                 }
1574
1575                 _rtl92c_phy_mac_setting_calibration(hw, mac_reg, mac_backup);
1576
1577                 if (path == 0) {
1578                         rtl_set_rfreg(hw, RF90_PATH_B, 0x0, MASKDWORD, 0x10000);
1579                 } else {
1580                         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASKDWORD,
1581                                       0x10000);
1582                         rtl_set_rfreg(hw, RF90_PATH_A, 0x10, MASKDWORD,
1583                                       0x1000f);
1584                         rtl_set_rfreg(hw, RF90_PATH_A, 0x11, MASKDWORD,
1585                                       0x20103);
1586                 }
1587
1588                 delta_offset = ((delta + 14) / 2);
1589                 if (delta_offset < 0)
1590                         delta_offset = 0;
1591                 else if (delta_offset > 12)
1592                         delta_offset = 12;
1593
1594                 for (index = 0; index < APK_BB_REG_NUM; index++) {
1595                         if (index != 1)
1596                                 continue;
1597
1598                         tmpreg = apk_rf_init_value[path][index];
1599
1600                         if (!rtlefuse->apk_thermalmeterignore) {
1601                                 bb_offset = (tmpreg & 0xF0000) >> 16;
1602
1603                                 if (!(tmpreg & BIT(15)))
1604                                         bb_offset = -bb_offset;
1605
1606                                 delta_v =
1607                                     apk_delta_mapping[index][delta_offset];
1608
1609                                 bb_offset += delta_v;
1610
1611                                 if (bb_offset < 0) {
1612                                         tmpreg = tmpreg & (~BIT(15));
1613                                         bb_offset = -bb_offset;
1614                                 } else {
1615                                         tmpreg = tmpreg | BIT(15);
1616                                 }
1617
1618                                 tmpreg =
1619                                     (tmpreg & 0xFFF0FFFF) | (bb_offset << 16);
1620                         }
1621
1622                         rtl_set_rfreg(hw, (enum radio_path)path, 0xc,
1623                                       MASKDWORD, 0x8992e);
1624                         rtl_set_rfreg(hw, (enum radio_path)path, 0x0,
1625                                       MASKDWORD, apk_rf_value_0[path][index]);
1626                         rtl_set_rfreg(hw, (enum radio_path)path, 0xd,
1627                                       MASKDWORD, tmpreg);
1628
1629                         i = 0;
1630                         do {
1631                                 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80000000);
1632                                 rtl_set_bbreg(hw, apk_offset[path],
1633                                               MASKDWORD, apk_value[0]);
1634                                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1635                                         ("PHY_APCalibrate() offset 0x%x "
1636                                          "value 0x%x\n",
1637                                          apk_offset[path],
1638                                          rtl_get_bbreg(hw, apk_offset[path],
1639                                                        MASKDWORD)));
1640
1641                                 mdelay(3);
1642
1643                                 rtl_set_bbreg(hw, apk_offset[path],
1644                                               MASKDWORD, apk_value[1]);
1645                                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1646                                         ("PHY_APCalibrate() offset 0x%x "
1647                                          "value 0x%x\n",
1648                                          apk_offset[path],
1649                                          rtl_get_bbreg(hw, apk_offset[path],
1650                                                        MASKDWORD)));
1651
1652                                 mdelay(20);
1653
1654                                 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1655
1656                                 if (path == RF90_PATH_A)
1657                                         tmpreg = rtl_get_bbreg(hw, 0xbd8,
1658                                                                0x03E00000);
1659                                 else
1660                                         tmpreg = rtl_get_bbreg(hw, 0xbd8,
1661                                                                0xF8000000);
1662
1663                                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1664                                         ("PHY_APCalibrate() offset "
1665                                          "0xbd8[25:21] %x\n", tmpreg));
1666
1667                                 i++;
1668
1669                         } while (tmpreg > apkbound && i < 4);
1670
1671                         apk_result[path][index] = tmpreg;
1672                 }
1673         }
1674
1675         _rtl92c_phy_reload_mac_registers(hw, mac_reg, mac_backup);
1676
1677         for (index = 0; index < APK_BB_REG_NUM; index++) {
1678                 if (index == 0)
1679                         continue;
1680                 rtl_set_bbreg(hw, bb_reg[index], MASKDWORD, bb_backup[index]);
1681         }
1682
1683         _rtl92c_phy_reload_adda_registers(hw, afe_reg, afe_backup, 16);
1684
1685         for (path = 0; path < pathbound; path++) {
1686                 rtl_set_rfreg(hw, (enum radio_path)path, 0xd,
1687                               MASKDWORD, reg_d[path]);
1688
1689                 if (path == RF90_PATH_B) {
1690                         rtl_set_rfreg(hw, RF90_PATH_A, 0x10, MASKDWORD,
1691                                       0x1000f);
1692                         rtl_set_rfreg(hw, RF90_PATH_A, 0x11, MASKDWORD,
1693                                       0x20101);
1694                 }
1695
1696                 if (apk_result[path][1] > 6)
1697                         apk_result[path][1] = 6;
1698         }
1699
1700         for (path = 0; path < pathbound; path++) {
1701                 rtl_set_rfreg(hw, (enum radio_path)path, 0x3, MASKDWORD,
1702                               ((apk_result[path][1] << 15) |
1703                                (apk_result[path][1] << 10) |
1704                                (apk_result[path][1] << 5) |
1705                                apk_result[path][1]));
1706
1707                 if (path == RF90_PATH_A)
1708                         rtl_set_rfreg(hw, (enum radio_path)path, 0x4, MASKDWORD,
1709                                       ((apk_result[path][1] << 15) |
1710                                        (apk_result[path][1] << 10) |
1711                                        (0x00 << 5) | 0x05));
1712                 else
1713                         rtl_set_rfreg(hw, (enum radio_path)path, 0x4, MASKDWORD,
1714                                       ((apk_result[path][1] << 15) |
1715                                        (apk_result[path][1] << 10) |
1716                                        (0x02 << 5) | 0x05));
1717
1718                 rtl_set_rfreg(hw, (enum radio_path)path, 0xe, MASKDWORD,
1719                               ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) |
1720                                0x08));
1721
1722         }
1723         rtlphy->b_apk_done = true;
1724 #endif
1725 }
1726
1727 static void _rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1728                                           bool bmain, bool is2t)
1729 {
1730         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1731
1732         if (is_hal_stop(rtlhal)) {
1733                 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
1734                 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1735         }
1736         if (is2t) {
1737                 if (bmain)
1738                         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1739                                       BIT(5) | BIT(6), 0x1);
1740                 else
1741                         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1742                                       BIT(5) | BIT(6), 0x2);
1743         } else {
1744                 if (bmain)
1745                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
1746                 else
1747                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
1748
1749         }
1750
1751 }
1752
1753 #undef IQK_ADDA_REG_NUM
1754 #undef IQK_DELAY_TIME
1755
1756 void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1757 {
1758         struct rtl_priv *rtlpriv = rtl_priv(hw);
1759         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1760         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1761
1762         long result[4][8];
1763         u8 i, final_candidate;
1764         bool patha_ok, pathb_ok;
1765         long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4,
1766             reg_ecc, reg_tmp = 0;
1767         bool is12simular, is13simular, is23simular;
1768         bool start_conttx = false, singletone = false;
1769         u32 iqk_bb_reg[10] = {
1770                 ROFDM0_XARXIQIMBALANCE,
1771                 ROFDM0_XBRXIQIMBALANCE,
1772                 ROFDM0_ECCATHRESHOLD,
1773                 ROFDM0_AGCRSSITABLE,
1774                 ROFDM0_XATXIQIMBALANCE,
1775                 ROFDM0_XBTXIQIMBALANCE,
1776                 ROFDM0_XCTXIQIMBALANCE,
1777                 ROFDM0_XCTXAFE,
1778                 ROFDM0_XDTXAFE,
1779                 ROFDM0_RXIQEXTANTA
1780         };
1781
1782         if (recovery) {
1783                 _rtl92c_phy_reload_adda_registers(hw,
1784                                                   iqk_bb_reg,
1785                                                   rtlphy->iqk_bb_backup, 10);
1786                 return;
1787         }
1788         if (start_conttx || singletone)
1789                 return;
1790         for (i = 0; i < 8; i++) {
1791                 result[0][i] = 0;
1792                 result[1][i] = 0;
1793                 result[2][i] = 0;
1794                 result[3][i] = 0;
1795         }
1796         final_candidate = 0xff;
1797         patha_ok = false;
1798         pathb_ok = false;
1799         is12simular = false;
1800         is23simular = false;
1801         is13simular = false;
1802         for (i = 0; i < 3; i++) {
1803                 if (IS_92C_SERIAL(rtlhal->version))
1804                         _rtl92c_phy_iq_calibrate(hw, result, i, true);
1805                 else
1806                         _rtl92c_phy_iq_calibrate(hw, result, i, false);
1807                 if (i == 1) {
1808                         is12simular = _rtl92c_phy_simularity_compare(hw,
1809                                                                      result, 0,
1810                                                                      1);
1811                         if (is12simular) {
1812                                 final_candidate = 0;
1813                                 break;
1814                         }
1815                 }
1816                 if (i == 2) {
1817                         is13simular = _rtl92c_phy_simularity_compare(hw,
1818                                                                      result, 0,
1819                                                                      2);
1820                         if (is13simular) {
1821                                 final_candidate = 0;
1822                                 break;
1823                         }
1824                         is23simular = _rtl92c_phy_simularity_compare(hw,
1825                                                                      result, 1,
1826                                                                      2);
1827                         if (is23simular)
1828                                 final_candidate = 1;
1829                         else {
1830                                 for (i = 0; i < 8; i++)
1831                                         reg_tmp += result[3][i];
1832
1833                                 if (reg_tmp != 0)
1834                                         final_candidate = 3;
1835                                 else
1836                                         final_candidate = 0xFF;
1837                         }
1838                 }
1839         }
1840         for (i = 0; i < 4; i++) {
1841                 reg_e94 = result[i][0];
1842                 reg_e9c = result[i][1];
1843                 reg_ea4 = result[i][2];
1844                 reg_eac = result[i][3];
1845                 reg_eb4 = result[i][4];
1846                 reg_ebc = result[i][5];
1847                 reg_ec4 = result[i][6];
1848                 reg_ecc = result[i][7];
1849         }
1850         if (final_candidate != 0xff) {
1851                 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1852                 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1853                 reg_ea4 = result[final_candidate][2];
1854                 reg_eac = result[final_candidate][3];
1855                 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1856                 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1857                 reg_ec4 = result[final_candidate][6];
1858                 reg_ecc = result[final_candidate][7];
1859                 patha_ok = pathb_ok = true;
1860         } else {
1861                 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
1862                 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1863         }
1864         if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
1865                 _rtl92c_phy_path_a_fill_iqk_matrix(hw, patha_ok, result,
1866                                                    final_candidate,
1867                                                    (reg_ea4 == 0));
1868         if (IS_92C_SERIAL(rtlhal->version)) {
1869                 if (reg_eb4 != 0) /*&&(reg_ec4 != 0) */
1870                         _rtl92c_phy_path_b_fill_iqk_matrix(hw, pathb_ok,
1871                                                            result,
1872                                                            final_candidate,
1873                                                            (reg_ec4 == 0));
1874         }
1875         _rtl92c_phy_save_adda_registers(hw, iqk_bb_reg,
1876                                         rtlphy->iqk_bb_backup, 10);
1877 }
1878 EXPORT_SYMBOL(rtl92c_phy_iq_calibrate);
1879
1880 void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw)
1881 {
1882         struct rtl_priv *rtlpriv = rtl_priv(hw);
1883         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1884         bool start_conttx = false, singletone = false;
1885
1886         if (start_conttx || singletone)
1887                 return;
1888         if (IS_92C_SERIAL(rtlhal->version))
1889                 rtlpriv->cfg->ops->phy_lc_calibrate(hw, true);
1890         else
1891                 rtlpriv->cfg->ops->phy_lc_calibrate(hw, false);
1892 }
1893 EXPORT_SYMBOL(rtl92c_phy_lc_calibrate);
1894
1895 void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
1896 {
1897         struct rtl_priv *rtlpriv = rtl_priv(hw);
1898         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1899         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1900
1901         if (rtlphy->apk_done)
1902                 return;
1903         if (IS_92C_SERIAL(rtlhal->version))
1904                 _rtl92c_phy_ap_calibrate(hw, delta, true);
1905         else
1906                 _rtl92c_phy_ap_calibrate(hw, delta, false);
1907 }
1908 EXPORT_SYMBOL(rtl92c_phy_ap_calibrate);
1909
1910 void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
1911 {
1912         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1913
1914         if (IS_92C_SERIAL(rtlhal->version))
1915                 _rtl92c_phy_set_rfpath_switch(hw, bmain, true);
1916         else
1917                 _rtl92c_phy_set_rfpath_switch(hw, bmain, false);
1918 }
1919 EXPORT_SYMBOL(rtl92c_phy_set_rfpath_switch);
1920
1921 bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1922 {
1923         struct rtl_priv *rtlpriv = rtl_priv(hw);
1924         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1925         bool postprocessing = false;
1926
1927         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1928                  ("-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1929                   iotype, rtlphy->set_io_inprogress));
1930         do {
1931                 switch (iotype) {
1932                 case IO_CMD_RESUME_DM_BY_SCAN:
1933                         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1934                                  ("[IO CMD] Resume DM after scan.\n"));
1935                         postprocessing = true;
1936                         break;
1937                 case IO_CMD_PAUSE_DM_BY_SCAN:
1938                         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1939                                  ("[IO CMD] Pause DM before scan.\n"));
1940                         postprocessing = true;
1941                         break;
1942                 default:
1943                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1944                                  ("switch case not process\n"));
1945                         break;
1946                 }
1947         } while (false);
1948         if (postprocessing && !rtlphy->set_io_inprogress) {
1949                 rtlphy->set_io_inprogress = true;
1950                 rtlphy->current_io_type = iotype;
1951         } else {
1952                 return false;
1953         }
1954         rtl92c_phy_set_io(hw);
1955         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, ("<--IO Type(%#x)\n", iotype));
1956         return true;
1957 }
1958 EXPORT_SYMBOL(rtl92c_phy_set_io_cmd);
1959
1960 void rtl92c_phy_set_io(struct ieee80211_hw *hw)
1961 {
1962         struct rtl_priv *rtlpriv = rtl_priv(hw);
1963         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1964
1965         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1966                  ("--->Cmd(%#x), set_io_inprogress(%d)\n",
1967                   rtlphy->current_io_type, rtlphy->set_io_inprogress));
1968         switch (rtlphy->current_io_type) {
1969         case IO_CMD_RESUME_DM_BY_SCAN:
1970                 dm_digtable.cur_igvalue = rtlphy->initgain_backup.xaagccore1;
1971                 rtl92c_dm_write_dig(hw);
1972                 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1973                 break;
1974         case IO_CMD_PAUSE_DM_BY_SCAN:
1975                 rtlphy->initgain_backup.xaagccore1 = dm_digtable.cur_igvalue;
1976                 dm_digtable.cur_igvalue = 0x17;
1977                 rtl92c_dm_write_dig(hw);
1978                 break;
1979         default:
1980                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1981                          ("switch case not process\n"));
1982                 break;
1983         }
1984         rtlphy->set_io_inprogress = false;
1985         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1986                  ("<---(%#x)\n", rtlphy->current_io_type));
1987 }
1988 EXPORT_SYMBOL(rtl92c_phy_set_io);
1989
1990 void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw)
1991 {
1992         struct rtl_priv *rtlpriv = rtl_priv(hw);
1993
1994         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
1995         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1996         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1997         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1998         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1999         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2000 }
2001 EXPORT_SYMBOL(rtl92ce_phy_set_rf_on);
2002
2003 void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw)
2004 {
2005         u32 u4b_tmp;
2006         u8 delay = 5;
2007         struct rtl_priv *rtlpriv = rtl_priv(hw);
2008
2009         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2010         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2011         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
2012         u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
2013         while (u4b_tmp != 0 && delay > 0) {
2014                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
2015                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2016                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
2017                 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
2018                 delay--;
2019         }
2020         if (delay == 0) {
2021                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
2022                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2023                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2024                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2025                 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
2026                          ("Switch RF timeout !!!.\n"));
2027                 return;
2028         }
2029         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2030         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
2031 }
2032 EXPORT_SYMBOL(_rtl92c_phy_set_rf_sleep);