rt2800: add rt2800lib (part four)
[linux-3.10.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
1 /*
2         Copyright (C) 2009 Bartlomiej Zolnierkiewicz
3
4         Based on the original rt2800pci.c and rt2800usb.c:
5
6           Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
7           <http://rt2x00.serialmonkey.com>
8
9         This program is free software; you can redistribute it and/or modify
10         it under the terms of the GNU General Public License as published by
11         the Free Software Foundation; either version 2 of the License, or
12         (at your option) any later version.
13
14         This program is distributed in the hope that it will be useful,
15         but WITHOUT ANY WARRANTY; without even the implied warranty of
16         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17         GNU General Public License for more details.
18
19         You should have received a copy of the GNU General Public License
20         along with this program; if not, write to the
21         Free Software Foundation, Inc.,
22         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23  */
24
25 /*
26         Module: rt2800lib
27         Abstract: rt2800 generic device routines.
28  */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32
33 #include "rt2x00.h"
34 #ifdef CONFIG_RT2800USB
35 #include "rt2x00usb.h"
36 #endif
37 #include "rt2800lib.h"
38 #include "rt2800.h"
39 #include "rt2800usb.h"
40
41 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
42 MODULE_DESCRIPTION("rt2800 library");
43 MODULE_LICENSE("GPL");
44
45 /*
46  * Register access.
47  * All access to the CSR registers will go through the methods
48  * rt2800_register_read and rt2800_register_write.
49  * BBP and RF register require indirect register access,
50  * and use the CSR registers BBPCSR and RFCSR to achieve this.
51  * These indirect registers work with busy bits,
52  * and we will try maximal REGISTER_BUSY_COUNT times to access
53  * the register while taking a REGISTER_BUSY_DELAY us delay
54  * between each attampt. When the busy bit is still set at that time,
55  * the access attempt is considered to have failed,
56  * and we will print an error.
57  * The _lock versions must be used if you already hold the csr_mutex
58  */
59 #define WAIT_FOR_BBP(__dev, __reg) \
60         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
61 #define WAIT_FOR_RFCSR(__dev, __reg) \
62         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
63 #define WAIT_FOR_RF(__dev, __reg) \
64         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
65 #define WAIT_FOR_MCU(__dev, __reg) \
66         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
67                             H2M_MAILBOX_CSR_OWNER, (__reg))
68
69 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
70                              const unsigned int word, const u8 value)
71 {
72         u32 reg;
73
74         mutex_lock(&rt2x00dev->csr_mutex);
75
76         /*
77          * Wait until the BBP becomes available, afterwards we
78          * can safely write the new data into the register.
79          */
80         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
81                 reg = 0;
82                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
83                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
84                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
85                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
86                 if (rt2x00_intf_is_pci(rt2x00dev))
87                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
88
89                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
90         }
91
92         mutex_unlock(&rt2x00dev->csr_mutex);
93 }
94
95 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
96                             const unsigned int word, u8 *value)
97 {
98         u32 reg;
99
100         mutex_lock(&rt2x00dev->csr_mutex);
101
102         /*
103          * Wait until the BBP becomes available, afterwards we
104          * can safely write the read request into the register.
105          * After the data has been written, we wait until hardware
106          * returns the correct value, if at any time the register
107          * doesn't become available in time, reg will be 0xffffffff
108          * which means we return 0xff to the caller.
109          */
110         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
111                 reg = 0;
112                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
113                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
114                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
115                 if (rt2x00_intf_is_pci(rt2x00dev))
116                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
117
118                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
119
120                 WAIT_FOR_BBP(rt2x00dev, &reg);
121         }
122
123         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
124
125         mutex_unlock(&rt2x00dev->csr_mutex);
126 }
127
128 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
129                                const unsigned int word, const u8 value)
130 {
131         u32 reg;
132
133         mutex_lock(&rt2x00dev->csr_mutex);
134
135         /*
136          * Wait until the RFCSR becomes available, afterwards we
137          * can safely write the new data into the register.
138          */
139         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
140                 reg = 0;
141                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
142                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
143                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
144                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
145
146                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
147         }
148
149         mutex_unlock(&rt2x00dev->csr_mutex);
150 }
151
152 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
153                               const unsigned int word, u8 *value)
154 {
155         u32 reg;
156
157         mutex_lock(&rt2x00dev->csr_mutex);
158
159         /*
160          * Wait until the RFCSR becomes available, afterwards we
161          * can safely write the read request into the register.
162          * After the data has been written, we wait until hardware
163          * returns the correct value, if at any time the register
164          * doesn't become available in time, reg will be 0xffffffff
165          * which means we return 0xff to the caller.
166          */
167         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
168                 reg = 0;
169                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
170                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
171                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
172
173                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
174
175                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
176         }
177
178         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
179
180         mutex_unlock(&rt2x00dev->csr_mutex);
181 }
182
183 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
184                             const unsigned int word, const u32 value)
185 {
186         u32 reg;
187
188         mutex_lock(&rt2x00dev->csr_mutex);
189
190         /*
191          * Wait until the RF becomes available, afterwards we
192          * can safely write the new data into the register.
193          */
194         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
195                 reg = 0;
196                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
197                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
198                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
199                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
200
201                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
202                 rt2x00_rf_write(rt2x00dev, word, value);
203         }
204
205         mutex_unlock(&rt2x00dev->csr_mutex);
206 }
207
208 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
209                         const u8 command, const u8 token,
210                         const u8 arg0, const u8 arg1)
211 {
212         u32 reg;
213
214         if (rt2x00_intf_is_pci(rt2x00dev)) {
215                 /*
216                 * RT2880 and RT3052 don't support MCU requests.
217                 */
218                 if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
219                     rt2x00_rt(&rt2x00dev->chip, RT3052))
220                         return;
221         }
222
223         mutex_lock(&rt2x00dev->csr_mutex);
224
225         /*
226          * Wait until the MCU becomes available, afterwards we
227          * can safely write the new data into the register.
228          */
229         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
230                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
231                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
232                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
233                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
234                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
235
236                 reg = 0;
237                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
238                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
239         }
240
241         mutex_unlock(&rt2x00dev->csr_mutex);
242 }
243 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
244
245 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
246 const struct rt2x00debug rt2800_rt2x00debug = {
247         .owner  = THIS_MODULE,
248         .csr    = {
249                 .read           = rt2800_register_read,
250                 .write          = rt2800_register_write,
251                 .flags          = RT2X00DEBUGFS_OFFSET,
252                 .word_base      = CSR_REG_BASE,
253                 .word_size      = sizeof(u32),
254                 .word_count     = CSR_REG_SIZE / sizeof(u32),
255         },
256         .eeprom = {
257                 .read           = rt2x00_eeprom_read,
258                 .write          = rt2x00_eeprom_write,
259                 .word_base      = EEPROM_BASE,
260                 .word_size      = sizeof(u16),
261                 .word_count     = EEPROM_SIZE / sizeof(u16),
262         },
263         .bbp    = {
264                 .read           = rt2800_bbp_read,
265                 .write          = rt2800_bbp_write,
266                 .word_base      = BBP_BASE,
267                 .word_size      = sizeof(u8),
268                 .word_count     = BBP_SIZE / sizeof(u8),
269         },
270         .rf     = {
271                 .read           = rt2x00_rf_read,
272                 .write          = rt2800_rf_write,
273                 .word_base      = RF_BASE,
274                 .word_size      = sizeof(u32),
275                 .word_count     = RF_SIZE / sizeof(u32),
276         },
277 };
278 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
279 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
280
281 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
282 {
283         u32 reg;
284
285         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
286         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
287 }
288 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
289
290 #ifdef CONFIG_RT2X00_LIB_LEDS
291 static void rt2800_brightness_set(struct led_classdev *led_cdev,
292                                   enum led_brightness brightness)
293 {
294         struct rt2x00_led *led =
295             container_of(led_cdev, struct rt2x00_led, led_dev);
296         unsigned int enabled = brightness != LED_OFF;
297         unsigned int bg_mode =
298             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
299         unsigned int polarity =
300                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
301                                    EEPROM_FREQ_LED_POLARITY);
302         unsigned int ledmode =
303                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
304                                    EEPROM_FREQ_LED_MODE);
305
306         if (led->type == LED_TYPE_RADIO) {
307                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
308                                       enabled ? 0x20 : 0);
309         } else if (led->type == LED_TYPE_ASSOC) {
310                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
311                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
312         } else if (led->type == LED_TYPE_QUALITY) {
313                 /*
314                  * The brightness is divided into 6 levels (0 - 5),
315                  * The specs tell us the following levels:
316                  *      0, 1 ,3, 7, 15, 31
317                  * to determine the level in a simple way we can simply
318                  * work with bitshifting:
319                  *      (1 << level) - 1
320                  */
321                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
322                                       (1 << brightness / (LED_FULL / 6)) - 1,
323                                       polarity);
324         }
325 }
326
327 static int rt2800_blink_set(struct led_classdev *led_cdev,
328                             unsigned long *delay_on, unsigned long *delay_off)
329 {
330         struct rt2x00_led *led =
331             container_of(led_cdev, struct rt2x00_led, led_dev);
332         u32 reg;
333
334         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
335         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
336         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
337         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
338         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
339         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
340         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
341         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
342         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
343
344         return 0;
345 }
346
347 void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
348                      struct rt2x00_led *led, enum led_type type)
349 {
350         led->rt2x00dev = rt2x00dev;
351         led->type = type;
352         led->led_dev.brightness_set = rt2800_brightness_set;
353         led->led_dev.blink_set = rt2800_blink_set;
354         led->flags = LED_INITIALIZED;
355 }
356 EXPORT_SYMBOL_GPL(rt2800_init_led);
357 #endif /* CONFIG_RT2X00_LIB_LEDS */
358
359 /*
360  * Configuration handlers.
361  */
362 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
363                                     struct rt2x00lib_crypto *crypto,
364                                     struct ieee80211_key_conf *key)
365 {
366         struct mac_wcid_entry wcid_entry;
367         struct mac_iveiv_entry iveiv_entry;
368         u32 offset;
369         u32 reg;
370
371         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
372
373         rt2800_register_read(rt2x00dev, offset, &reg);
374         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
375                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
376         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
377                            (crypto->cmd == SET_KEY) * crypto->cipher);
378         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
379                            (crypto->cmd == SET_KEY) * crypto->bssidx);
380         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
381         rt2800_register_write(rt2x00dev, offset, reg);
382
383         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
384
385         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
386         if ((crypto->cipher == CIPHER_TKIP) ||
387             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
388             (crypto->cipher == CIPHER_AES))
389                 iveiv_entry.iv[3] |= 0x20;
390         iveiv_entry.iv[3] |= key->keyidx << 6;
391         rt2800_register_multiwrite(rt2x00dev, offset,
392                                       &iveiv_entry, sizeof(iveiv_entry));
393
394         offset = MAC_WCID_ENTRY(key->hw_key_idx);
395
396         memset(&wcid_entry, 0, sizeof(wcid_entry));
397         if (crypto->cmd == SET_KEY)
398                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
399         rt2800_register_multiwrite(rt2x00dev, offset,
400                                       &wcid_entry, sizeof(wcid_entry));
401 }
402
403 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
404                              struct rt2x00lib_crypto *crypto,
405                              struct ieee80211_key_conf *key)
406 {
407         struct hw_key_entry key_entry;
408         struct rt2x00_field32 field;
409         u32 offset;
410         u32 reg;
411
412         if (crypto->cmd == SET_KEY) {
413                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
414
415                 memcpy(key_entry.key, crypto->key,
416                        sizeof(key_entry.key));
417                 memcpy(key_entry.tx_mic, crypto->tx_mic,
418                        sizeof(key_entry.tx_mic));
419                 memcpy(key_entry.rx_mic, crypto->rx_mic,
420                        sizeof(key_entry.rx_mic));
421
422                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
423                 rt2800_register_multiwrite(rt2x00dev, offset,
424                                               &key_entry, sizeof(key_entry));
425         }
426
427         /*
428          * The cipher types are stored over multiple registers
429          * starting with SHARED_KEY_MODE_BASE each word will have
430          * 32 bits and contains the cipher types for 2 bssidx each.
431          * Using the correct defines correctly will cause overhead,
432          * so just calculate the correct offset.
433          */
434         field.bit_offset = 4 * (key->hw_key_idx % 8);
435         field.bit_mask = 0x7 << field.bit_offset;
436
437         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
438
439         rt2800_register_read(rt2x00dev, offset, &reg);
440         rt2x00_set_field32(&reg, field,
441                            (crypto->cmd == SET_KEY) * crypto->cipher);
442         rt2800_register_write(rt2x00dev, offset, reg);
443
444         /*
445          * Update WCID information
446          */
447         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
448
449         return 0;
450 }
451 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
452
453 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
454                                struct rt2x00lib_crypto *crypto,
455                                struct ieee80211_key_conf *key)
456 {
457         struct hw_key_entry key_entry;
458         u32 offset;
459
460         if (crypto->cmd == SET_KEY) {
461                 /*
462                  * 1 pairwise key is possible per AID, this means that the AID
463                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
464                  * last possible shared key entry.
465                  */
466                 if (crypto->aid > (256 - 32))
467                         return -ENOSPC;
468
469                 key->hw_key_idx = 32 + crypto->aid;
470
471                 memcpy(key_entry.key, crypto->key,
472                        sizeof(key_entry.key));
473                 memcpy(key_entry.tx_mic, crypto->tx_mic,
474                        sizeof(key_entry.tx_mic));
475                 memcpy(key_entry.rx_mic, crypto->rx_mic,
476                        sizeof(key_entry.rx_mic));
477
478                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
479                 rt2800_register_multiwrite(rt2x00dev, offset,
480                                               &key_entry, sizeof(key_entry));
481         }
482
483         /*
484          * Update WCID information
485          */
486         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
487
488         return 0;
489 }
490 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
491
492 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
493                           const unsigned int filter_flags)
494 {
495         u32 reg;
496
497         /*
498          * Start configuration steps.
499          * Note that the version error will always be dropped
500          * and broadcast frames will always be accepted since
501          * there is no filter for it at this time.
502          */
503         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
504         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
505                            !(filter_flags & FIF_FCSFAIL));
506         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
507                            !(filter_flags & FIF_PLCPFAIL));
508         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
509                            !(filter_flags & FIF_PROMISC_IN_BSS));
510         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
511         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
512         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
513                            !(filter_flags & FIF_ALLMULTI));
514         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
515         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
516         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
517                            !(filter_flags & FIF_CONTROL));
518         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
519                            !(filter_flags & FIF_CONTROL));
520         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
521                            !(filter_flags & FIF_CONTROL));
522         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
523                            !(filter_flags & FIF_CONTROL));
524         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
525                            !(filter_flags & FIF_CONTROL));
526         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
527                            !(filter_flags & FIF_PSPOLL));
528         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
529         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
530         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
531                            !(filter_flags & FIF_CONTROL));
532         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
533 }
534 EXPORT_SYMBOL_GPL(rt2800_config_filter);
535
536 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
537                         struct rt2x00intf_conf *conf, const unsigned int flags)
538 {
539         unsigned int beacon_base;
540         u32 reg;
541
542         if (flags & CONFIG_UPDATE_TYPE) {
543                 /*
544                  * Clear current synchronisation setup.
545                  * For the Beacon base registers we only need to clear
546                  * the first byte since that byte contains the VALID and OWNER
547                  * bits which (when set to 0) will invalidate the entire beacon.
548                  */
549                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
550                 rt2800_register_write(rt2x00dev, beacon_base, 0);
551
552                 /*
553                  * Enable synchronisation.
554                  */
555                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
556                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
557                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
558                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
559                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
560         }
561
562         if (flags & CONFIG_UPDATE_MAC) {
563                 reg = le32_to_cpu(conf->mac[1]);
564                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
565                 conf->mac[1] = cpu_to_le32(reg);
566
567                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
568                                               conf->mac, sizeof(conf->mac));
569         }
570
571         if (flags & CONFIG_UPDATE_BSSID) {
572                 reg = le32_to_cpu(conf->bssid[1]);
573                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
574                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
575                 conf->bssid[1] = cpu_to_le32(reg);
576
577                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
578                                               conf->bssid, sizeof(conf->bssid));
579         }
580 }
581 EXPORT_SYMBOL_GPL(rt2800_config_intf);
582
583 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
584 {
585         u32 reg;
586
587         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
588         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
589         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
590
591         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
592         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
593                            !!erp->short_preamble);
594         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
595                            !!erp->short_preamble);
596         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
597
598         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
599         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
600                            erp->cts_protection ? 2 : 0);
601         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
602
603         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
604                                  erp->basic_rates);
605         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
606
607         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
608         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
609         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
610         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
611
612         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
613         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
614         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
615         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
616         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
617         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
618         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
619
620         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
621         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
622                            erp->beacon_int * 16);
623         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
624 }
625 EXPORT_SYMBOL_GPL(rt2800_config_erp);
626
627 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
628 {
629         u8 r1;
630         u8 r3;
631
632         rt2800_bbp_read(rt2x00dev, 1, &r1);
633         rt2800_bbp_read(rt2x00dev, 3, &r3);
634
635         /*
636          * Configure the TX antenna.
637          */
638         switch ((int)ant->tx) {
639         case 1:
640                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
641                 if (rt2x00_intf_is_pci(rt2x00dev))
642                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
643                 break;
644         case 2:
645                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
646                 break;
647         case 3:
648                 /* Do nothing */
649                 break;
650         }
651
652         /*
653          * Configure the RX antenna.
654          */
655         switch ((int)ant->rx) {
656         case 1:
657                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
658                 break;
659         case 2:
660                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
661                 break;
662         case 3:
663                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
664                 break;
665         }
666
667         rt2800_bbp_write(rt2x00dev, 3, r3);
668         rt2800_bbp_write(rt2x00dev, 1, r1);
669 }
670 EXPORT_SYMBOL_GPL(rt2800_config_ant);
671
672 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
673                                    struct rt2x00lib_conf *libconf)
674 {
675         u16 eeprom;
676         short lna_gain;
677
678         if (libconf->rf.channel <= 14) {
679                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
680                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
681         } else if (libconf->rf.channel <= 64) {
682                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
683                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
684         } else if (libconf->rf.channel <= 128) {
685                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
686                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
687         } else {
688                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
689                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
690         }
691
692         rt2x00dev->lna_gain = lna_gain;
693 }
694
695 static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
696                                        struct ieee80211_conf *conf,
697                                        struct rf_channel *rf,
698                                        struct channel_info *info)
699 {
700         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
701
702         if (rt2x00dev->default_ant.tx == 1)
703                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
704
705         if (rt2x00dev->default_ant.rx == 1) {
706                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
707                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
708         } else if (rt2x00dev->default_ant.rx == 2)
709                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
710
711         if (rf->channel > 14) {
712                 /*
713                  * When TX power is below 0, we should increase it by 7 to
714                  * make it a positive value (Minumum value is -7).
715                  * However this means that values between 0 and 7 have
716                  * double meaning, and we should set a 7DBm boost flag.
717                  */
718                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
719                                    (info->tx_power1 >= 0));
720
721                 if (info->tx_power1 < 0)
722                         info->tx_power1 += 7;
723
724                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
725                                    TXPOWER_A_TO_DEV(info->tx_power1));
726
727                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
728                                    (info->tx_power2 >= 0));
729
730                 if (info->tx_power2 < 0)
731                         info->tx_power2 += 7;
732
733                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
734                                    TXPOWER_A_TO_DEV(info->tx_power2));
735         } else {
736                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
737                                    TXPOWER_G_TO_DEV(info->tx_power1));
738                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
739                                    TXPOWER_G_TO_DEV(info->tx_power2));
740         }
741
742         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
743
744         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
745         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
746         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
747         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
748
749         udelay(200);
750
751         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
752         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
753         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
754         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
755
756         udelay(200);
757
758         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
759         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
760         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
761         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
762 }
763
764 static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
765                                        struct ieee80211_conf *conf,
766                                        struct rf_channel *rf,
767                                        struct channel_info *info)
768 {
769         u8 rfcsr;
770
771         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
772         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf3);
773
774         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
775         rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
776         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
777
778         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
779         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
780                           TXPOWER_G_TO_DEV(info->tx_power1));
781         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
782
783         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
784         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
785         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
786
787         rt2800_rfcsr_write(rt2x00dev, 24,
788                               rt2x00dev->calibration[conf_is_ht40(conf)]);
789
790         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
791         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
792         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
793 }
794
795 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
796                                   struct ieee80211_conf *conf,
797                                   struct rf_channel *rf,
798                                   struct channel_info *info)
799 {
800         u32 reg;
801         unsigned int tx_pin;
802         u8 bbp;
803
804         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
805                 rt2800_config_channel_rt2x(rt2x00dev, conf, rf, info);
806         else
807                 rt2800_config_channel_rt3x(rt2x00dev, conf, rf, info);
808
809         /*
810          * Change BBP settings
811          */
812         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
813         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
814         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
815         rt2800_bbp_write(rt2x00dev, 86, 0);
816
817         if (rf->channel <= 14) {
818                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
819                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
820                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
821                 } else {
822                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
823                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
824                 }
825         } else {
826                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
827
828                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
829                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
830                 else
831                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
832         }
833
834         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
835         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
836         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
837         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
838         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
839
840         tx_pin = 0;
841
842         /* Turn on unused PA or LNA when not using 1T or 1R */
843         if (rt2x00dev->default_ant.tx != 1) {
844                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
845                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
846         }
847
848         /* Turn on unused PA or LNA when not using 1T or 1R */
849         if (rt2x00dev->default_ant.rx != 1) {
850                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
851                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
852         }
853
854         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
855         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
856         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
857         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
858         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
859         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
860
861         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
862
863         rt2800_bbp_read(rt2x00dev, 4, &bbp);
864         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
865         rt2800_bbp_write(rt2x00dev, 4, bbp);
866
867         rt2800_bbp_read(rt2x00dev, 3, &bbp);
868         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
869         rt2800_bbp_write(rt2x00dev, 3, bbp);
870
871         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
872                 if (conf_is_ht40(conf)) {
873                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
874                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
875                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
876                 } else {
877                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
878                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
879                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
880                 }
881         }
882
883         msleep(1);
884 }
885
886 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
887                                   const int txpower)
888 {
889         u32 reg;
890         u32 value = TXPOWER_G_TO_DEV(txpower);
891         u8 r1;
892
893         rt2800_bbp_read(rt2x00dev, 1, &r1);
894         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
895         rt2800_bbp_write(rt2x00dev, 1, r1);
896
897         rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
898         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
899         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
900         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
901         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
902         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
903         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
904         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
905         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
906         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
907
908         rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
909         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
910         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
911         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
912         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
913         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
914         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
915         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
916         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
917         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
918
919         rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
920         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
921         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
922         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
923         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
924         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
925         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
926         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
927         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
928         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
929
930         rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
931         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
932         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
933         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
934         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
935         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
936         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
937         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
938         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
939         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
940
941         rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
942         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
943         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
944         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
945         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
946         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
947 }
948
949 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
950                                       struct rt2x00lib_conf *libconf)
951 {
952         u32 reg;
953
954         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
955         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
956                            libconf->conf->short_frame_max_tx_count);
957         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
958                            libconf->conf->long_frame_max_tx_count);
959         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
960         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
961         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
962         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
963         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
964 }
965
966 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
967                              struct rt2x00lib_conf *libconf)
968 {
969         enum dev_state state =
970             (libconf->conf->flags & IEEE80211_CONF_PS) ?
971                 STATE_SLEEP : STATE_AWAKE;
972         u32 reg;
973
974         if (state == STATE_SLEEP) {
975                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
976
977                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
978                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
979                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
980                                    libconf->conf->listen_interval - 1);
981                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
982                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
983
984                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
985         } else {
986                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
987
988                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
989                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
990                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
991                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
992                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
993         }
994 }
995
996 void rt2800_config(struct rt2x00_dev *rt2x00dev,
997                    struct rt2x00lib_conf *libconf,
998                    const unsigned int flags)
999 {
1000         /* Always recalculate LNA gain before changing configuration */
1001         rt2800_config_lna_gain(rt2x00dev, libconf);
1002
1003         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1004                 rt2800_config_channel(rt2x00dev, libconf->conf,
1005                                       &libconf->rf, &libconf->channel);
1006         if (flags & IEEE80211_CONF_CHANGE_POWER)
1007                 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1008         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1009                 rt2800_config_retry_limit(rt2x00dev, libconf);
1010         if (flags & IEEE80211_CONF_CHANGE_PS)
1011                 rt2800_config_ps(rt2x00dev, libconf);
1012 }
1013 EXPORT_SYMBOL_GPL(rt2800_config);
1014
1015 /*
1016  * Link tuning
1017  */
1018 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1019 {
1020         u32 reg;
1021
1022         /*
1023          * Update FCS error count from register.
1024          */
1025         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1026         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1027 }
1028 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1029
1030 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1031 {
1032         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1033                 if (rt2x00_intf_is_usb(rt2x00dev) &&
1034                     rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1035                         return 0x1c + (2 * rt2x00dev->lna_gain);
1036                 else
1037                         return 0x2e + rt2x00dev->lna_gain;
1038         }
1039
1040         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1041                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1042         else
1043                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1044 }
1045
1046 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1047                                   struct link_qual *qual, u8 vgc_level)
1048 {
1049         if (qual->vgc_level != vgc_level) {
1050                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1051                 qual->vgc_level = vgc_level;
1052                 qual->vgc_level_reg = vgc_level;
1053         }
1054 }
1055
1056 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1057 {
1058         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1059 }
1060 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1061
1062 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1063                        const u32 count)
1064 {
1065         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1066                 return;
1067
1068         /*
1069          * When RSSI is better then -80 increase VGC level with 0x10
1070          */
1071         rt2800_set_vgc(rt2x00dev, qual,
1072                        rt2800_get_default_vgc(rt2x00dev) +
1073                        ((qual->rssi > -80) * 0x10));
1074 }
1075 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1076
1077 /*
1078  * Initialization functions.
1079  */
1080 int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1081 {
1082         u32 reg;
1083         unsigned int i;
1084
1085         if (rt2x00_intf_is_usb(rt2x00dev)) {
1086                 /*
1087                  * Wait untill BBP and RF are ready.
1088                  */
1089                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1090                         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1091                         if (reg && reg != ~0)
1092                                 break;
1093                         msleep(1);
1094                 }
1095
1096                 if (i == REGISTER_BUSY_COUNT) {
1097                         ERROR(rt2x00dev, "Unstable hardware.\n");
1098                         return -EBUSY;
1099                 }
1100
1101                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1102                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1103                                       reg & ~0x00002000);
1104         } else if (rt2x00_intf_is_pci(rt2x00dev))
1105                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1106
1107         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1108         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1109         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1110         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1111
1112         if (rt2x00_intf_is_usb(rt2x00dev)) {
1113                 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1114 #ifdef CONFIG_RT2800USB
1115                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1116                                             USB_MODE_RESET, REGISTER_TIMEOUT);
1117 #endif
1118         }
1119
1120         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1121
1122         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1123         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1124         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1125         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1126         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1127         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1128
1129         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1130         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1131         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1132         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1133         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1134         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1135
1136         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1137         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1138
1139         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1140
1141         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1142         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1143         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1144         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1145         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1146         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1147         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1148         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1149
1150         if (rt2x00_intf_is_usb(rt2x00dev) &&
1151             rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1152                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1153                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1154                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1155         } else {
1156                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1157                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1158         }
1159
1160         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1161         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1162         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1163         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1164         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1165         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1166         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1167         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1168         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1169         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1170
1171         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1172         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1173         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1174         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1175
1176         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1177         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1178         if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1179             rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1180                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1181         else
1182                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1183         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1184         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1185         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1186
1187         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1188
1189         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1190         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1191         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1192         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1193         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1194         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1195         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1196
1197         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1198         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1199         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1200         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1201         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1202         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1203         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1204         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1205         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1206         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1207         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1208
1209         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1210         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1211         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1212         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1213         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1214         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1215         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1216         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1217         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1218         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1219         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1220
1221         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1222         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1223         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1224         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1225         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1226         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1227         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1228         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1229         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1230         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1231         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1232
1233         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1234         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1235         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1236         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1237         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1238         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1239         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1240         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1241         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1242         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1243         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1244
1245         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1246         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1247         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1248         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1249         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1250         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1251         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1252         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1253         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1254         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1255         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1256
1257         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1258         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1259         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1260         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1261         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1262         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1263         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1264         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1265         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1266         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1267         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1268
1269         if (rt2x00_intf_is_usb(rt2x00dev)) {
1270                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1271
1272                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1273                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1274                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1275                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1276                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1277                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1278                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1279                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1280                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1281                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1282                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1283         }
1284
1285         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1286         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1287
1288         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1289         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1290         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1291                            IEEE80211_MAX_RTS_THRESHOLD);
1292         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1293         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1294
1295         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1296         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1297
1298         /*
1299          * ASIC will keep garbage value after boot, clear encryption keys.
1300          */
1301         for (i = 0; i < 4; i++)
1302                 rt2800_register_write(rt2x00dev,
1303                                          SHARED_KEY_MODE_ENTRY(i), 0);
1304
1305         for (i = 0; i < 256; i++) {
1306                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1307                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1308                                               wcid, sizeof(wcid));
1309
1310                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1311                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1312         }
1313
1314         /*
1315          * Clear all beacons
1316          * For the Beacon base registers we only need to clear
1317          * the first byte since that byte contains the VALID and OWNER
1318          * bits which (when set to 0) will invalidate the entire beacon.
1319          */
1320         rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1321         rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1322         rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1323         rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1324         rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1325         rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1326         rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1327         rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1328
1329         if (rt2x00_intf_is_usb(rt2x00dev)) {
1330                 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1331                 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1332                 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1333         }
1334
1335         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1336         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1337         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1338         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1339         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1340         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1341         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1342         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1343         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1344         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1345
1346         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1347         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1348         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1349         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1350         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1351         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1352         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1353         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1354         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1355         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1356
1357         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1358         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1359         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1360         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1361         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1362         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1363         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1364         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1365         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1366         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1367
1368         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1369         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1370         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1371         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1372         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1373         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1374
1375         /*
1376          * We must clear the error counters.
1377          * These registers are cleared on read,
1378          * so we may pass a useless variable to store the value.
1379          */
1380         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1381         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1382         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1383         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1384         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1385         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1386
1387         return 0;
1388 }
1389 EXPORT_SYMBOL_GPL(rt2800_init_registers);
1390
1391 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1392 {
1393         unsigned int i;
1394         u32 reg;
1395
1396         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1397                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1398                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1399                         return 0;
1400
1401                 udelay(REGISTER_BUSY_DELAY);
1402         }
1403
1404         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1405         return -EACCES;
1406 }
1407
1408 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1409 {
1410         unsigned int i;
1411         u8 value;
1412
1413         /*
1414          * BBP was enabled after firmware was loaded,
1415          * but we need to reactivate it now.
1416          */
1417         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1418         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1419         msleep(1);
1420
1421         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1422                 rt2800_bbp_read(rt2x00dev, 0, &value);
1423                 if ((value != 0xff) && (value != 0x00))
1424                         return 0;
1425                 udelay(REGISTER_BUSY_DELAY);
1426         }
1427
1428         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1429         return -EACCES;
1430 }
1431
1432 int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1433 {
1434         unsigned int i;
1435         u16 eeprom;
1436         u8 reg_id;
1437         u8 value;
1438
1439         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1440                      rt2800_wait_bbp_ready(rt2x00dev)))
1441                 return -EACCES;
1442
1443         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1444         rt2800_bbp_write(rt2x00dev, 66, 0x38);
1445         rt2800_bbp_write(rt2x00dev, 69, 0x12);
1446         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1447         rt2800_bbp_write(rt2x00dev, 73, 0x10);
1448         rt2800_bbp_write(rt2x00dev, 81, 0x37);
1449         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1450         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1451         rt2800_bbp_write(rt2x00dev, 84, 0x99);
1452         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1453         rt2800_bbp_write(rt2x00dev, 91, 0x04);
1454         rt2800_bbp_write(rt2x00dev, 92, 0x00);
1455         rt2800_bbp_write(rt2x00dev, 103, 0x00);
1456         rt2800_bbp_write(rt2x00dev, 105, 0x05);
1457
1458         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1459                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1460                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1461         }
1462
1463         if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1464                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1465
1466         if (rt2x00_intf_is_usb(rt2x00dev) &&
1467             rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1468                 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1469                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1470                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1471         }
1472
1473         if (rt2x00_intf_is_pci(rt2x00dev) &&
1474             rt2x00_rt(&rt2x00dev->chip, RT3052)) {
1475                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1476                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1477                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1478         }
1479
1480         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1481                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1482
1483                 if (eeprom != 0xffff && eeprom != 0x0000) {
1484                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1485                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1486                         rt2800_bbp_write(rt2x00dev, reg_id, value);
1487                 }
1488         }
1489
1490         return 0;
1491 }
1492 EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1493
1494 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1495                                 bool bw40, u8 rfcsr24, u8 filter_target)
1496 {
1497         unsigned int i;
1498         u8 bbp;
1499         u8 rfcsr;
1500         u8 passband;
1501         u8 stopband;
1502         u8 overtuned = 0;
1503
1504         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1505
1506         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1507         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1508         rt2800_bbp_write(rt2x00dev, 4, bbp);
1509
1510         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1511         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1512         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1513
1514         /*
1515          * Set power & frequency of passband test tone
1516          */
1517         rt2800_bbp_write(rt2x00dev, 24, 0);
1518
1519         for (i = 0; i < 100; i++) {
1520                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1521                 msleep(1);
1522
1523                 rt2800_bbp_read(rt2x00dev, 55, &passband);
1524                 if (passband)
1525                         break;
1526         }
1527
1528         /*
1529          * Set power & frequency of stopband test tone
1530          */
1531         rt2800_bbp_write(rt2x00dev, 24, 0x06);
1532
1533         for (i = 0; i < 100; i++) {
1534                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1535                 msleep(1);
1536
1537                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1538
1539                 if ((passband - stopband) <= filter_target) {
1540                         rfcsr24++;
1541                         overtuned += ((passband - stopband) == filter_target);
1542                 } else
1543                         break;
1544
1545                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1546         }
1547
1548         rfcsr24 -= !!overtuned;
1549
1550         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1551         return rfcsr24;
1552 }
1553
1554 int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1555 {
1556         u8 rfcsr;
1557         u8 bbp;
1558
1559         if (rt2x00_intf_is_usb(rt2x00dev) &&
1560             rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1561                 return 0;
1562
1563         if (rt2x00_intf_is_pci(rt2x00dev)) {
1564                 if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1565                     !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1566                     !rt2x00_rf(&rt2x00dev->chip, RF3022))
1567                         return 0;
1568         }
1569
1570         /*
1571          * Init RF calibration.
1572          */
1573         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1574         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1575         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1576         msleep(1);
1577         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1578         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1579
1580         if (rt2x00_intf_is_usb(rt2x00dev)) {
1581                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1582                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1583                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1584                 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1585                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1586                 rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
1587                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1588                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1589                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1590                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1591                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1592                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1593                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1594                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1595                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1596                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1597                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1598                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1599                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1600                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1601         } else if (rt2x00_intf_is_pci(rt2x00dev)) {
1602                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1603                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1604                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1605                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1606                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1607                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1608                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1609                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1610                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1611                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1612                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1613                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1614                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1615                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1616                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1617                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1618                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1619                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1620                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1621                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1622                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1623                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1624                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1625                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1626                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1627                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1628                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1629                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1630                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1631                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1632         }
1633
1634         /*
1635          * Set RX Filter calibration for 20MHz and 40MHz
1636          */
1637         rt2x00dev->calibration[0] =
1638             rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1639         rt2x00dev->calibration[1] =
1640             rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1641
1642         /*
1643          * Set back to initial state
1644          */
1645         rt2800_bbp_write(rt2x00dev, 24, 0);
1646
1647         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1648         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1649         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1650
1651         /*
1652          * set BBP back to BW20
1653          */
1654         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1655         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1656         rt2800_bbp_write(rt2x00dev, 4, bbp);
1657
1658         return 0;
1659 }
1660 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
1661
1662 /*
1663  * IEEE80211 stack callback functions.
1664  */
1665 static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
1666                                 u32 *iv32, u16 *iv16)
1667 {
1668         struct rt2x00_dev *rt2x00dev = hw->priv;
1669         struct mac_iveiv_entry iveiv_entry;
1670         u32 offset;
1671
1672         offset = MAC_IVEIV_ENTRY(hw_key_idx);
1673         rt2800_register_multiread(rt2x00dev, offset,
1674                                       &iveiv_entry, sizeof(iveiv_entry));
1675
1676         memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
1677         memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
1678 }
1679
1680 static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
1681 {
1682         struct rt2x00_dev *rt2x00dev = hw->priv;
1683         u32 reg;
1684         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
1685
1686         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1687         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
1688         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1689
1690         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1691         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
1692         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1693
1694         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1695         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
1696         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1697
1698         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1699         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
1700         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1701
1702         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1703         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
1704         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1705
1706         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1707         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
1708         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1709
1710         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1711         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
1712         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1713
1714         return 0;
1715 }
1716
1717 static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
1718                           const struct ieee80211_tx_queue_params *params)
1719 {
1720         struct rt2x00_dev *rt2x00dev = hw->priv;
1721         struct data_queue *queue;
1722         struct rt2x00_field32 field;
1723         int retval;
1724         u32 reg;
1725         u32 offset;
1726
1727         /*
1728          * First pass the configuration through rt2x00lib, that will
1729          * update the queue settings and validate the input. After that
1730          * we are free to update the registers based on the value
1731          * in the queue parameter.
1732          */
1733         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
1734         if (retval)
1735                 return retval;
1736
1737         /*
1738          * We only need to perform additional register initialization
1739          * for WMM queues/
1740          */
1741         if (queue_idx >= 4)
1742                 return 0;
1743
1744         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1745
1746         /* Update WMM TXOP register */
1747         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
1748         field.bit_offset = (queue_idx & 1) * 16;
1749         field.bit_mask = 0xffff << field.bit_offset;
1750
1751         rt2800_register_read(rt2x00dev, offset, &reg);
1752         rt2x00_set_field32(&reg, field, queue->txop);
1753         rt2800_register_write(rt2x00dev, offset, reg);
1754
1755         /* Update WMM registers */
1756         field.bit_offset = queue_idx * 4;
1757         field.bit_mask = 0xf << field.bit_offset;
1758
1759         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
1760         rt2x00_set_field32(&reg, field, queue->aifs);
1761         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
1762
1763         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
1764         rt2x00_set_field32(&reg, field, queue->cw_min);
1765         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
1766
1767         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
1768         rt2x00_set_field32(&reg, field, queue->cw_max);
1769         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
1770
1771         /* Update EDCA registers */
1772         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
1773
1774         rt2800_register_read(rt2x00dev, offset, &reg);
1775         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
1776         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
1777         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
1778         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
1779         rt2800_register_write(rt2x00dev, offset, reg);
1780
1781         return 0;
1782 }
1783
1784 static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
1785 {
1786         struct rt2x00_dev *rt2x00dev = hw->priv;
1787         u64 tsf;
1788         u32 reg;
1789
1790         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
1791         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
1792         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
1793         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
1794
1795         return tsf;
1796 }
1797
1798 const struct ieee80211_ops rt2800_mac80211_ops = {
1799         .tx                     = rt2x00mac_tx,
1800         .start                  = rt2x00mac_start,
1801         .stop                   = rt2x00mac_stop,
1802         .add_interface          = rt2x00mac_add_interface,
1803         .remove_interface       = rt2x00mac_remove_interface,
1804         .config                 = rt2x00mac_config,
1805         .configure_filter       = rt2x00mac_configure_filter,
1806         .set_tim                = rt2x00mac_set_tim,
1807         .set_key                = rt2x00mac_set_key,
1808         .get_stats              = rt2x00mac_get_stats,
1809         .get_tkip_seq           = rt2800_get_tkip_seq,
1810         .set_rts_threshold      = rt2800_set_rts_threshold,
1811         .bss_info_changed       = rt2x00mac_bss_info_changed,
1812         .conf_tx                = rt2800_conf_tx,
1813         .get_tx_stats           = rt2x00mac_get_tx_stats,
1814         .get_tsf                = rt2800_get_tsf,
1815         .rfkill_poll            = rt2x00mac_rfkill_poll,
1816 };
1817 EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);