Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-3.10.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4  *
5  * Portions of this file are derived from the ipw3945 project, as well
6  * as portions of the ieee80211 subsystem header files.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of version 2 of the GNU General Public License as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20  *
21  * The full GNU General Public License is included in this distribution in the
22  * file called LICENSE.
23  *
24  * Contact Information:
25  * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27  *
28  *****************************************************************************/
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/delay.h>
36 #include <linux/skbuff.h>
37 #include <linux/netdevice.h>
38 #include <linux/wireless.h>
39 #include <linux/firmware.h>
40 #include <linux/etherdevice.h>
41 #include <linux/if_arp.h>
42
43 #include <net/ieee80211_radiotap.h>
44 #include <net/lib80211.h>
45 #include <net/mac80211.h>
46
47 #include <asm/div64.h>
48
49 #include "iwl-3945-core.h"
50 #include "iwl-3945.h"
51 #include "iwl-helpers.h"
52
53 #ifdef CONFIG_IWL3945_DEBUG
54 u32 iwl3945_debug_level;
55 #endif
56
57 static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
58                                   struct iwl3945_tx_queue *txq);
59
60 /******************************************************************************
61  *
62  * module boiler plate
63  *
64  ******************************************************************************/
65
66 /* module parameters */
67 static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
68 static int iwl3945_param_debug;    /* def: 0 = minimal debug log messages */
69 static int iwl3945_param_disable;  /* def: 0 = enable radio */
70 static int iwl3945_param_antenna;  /* def: 0 = both antennas (use diversity) */
71 int iwl3945_param_hwcrypto;        /* def: 0 = use software encryption */
72 static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
73 int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
74
75 /*
76  * module name, copyright, version, etc.
77  * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
78  */
79
80 #define DRV_DESCRIPTION \
81 "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
82
83 #ifdef CONFIG_IWL3945_DEBUG
84 #define VD "d"
85 #else
86 #define VD
87 #endif
88
89 #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
90 #define VS "s"
91 #else
92 #define VS
93 #endif
94
95 #define IWLWIFI_VERSION "1.2.26k" VD VS
96 #define DRV_COPYRIGHT   "Copyright(c) 2003-2008 Intel Corporation"
97 #define DRV_VERSION     IWLWIFI_VERSION
98
99
100 MODULE_DESCRIPTION(DRV_DESCRIPTION);
101 MODULE_VERSION(DRV_VERSION);
102 MODULE_AUTHOR(DRV_COPYRIGHT);
103 MODULE_LICENSE("GPL");
104
105 static const struct ieee80211_supported_band *iwl3945_get_band(
106                 struct iwl3945_priv *priv, enum ieee80211_band band)
107 {
108         return priv->hw->wiphy->bands[band];
109 }
110
111 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
112  * DMA services
113  *
114  * Theory of operation
115  *
116  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
117  * of buffer descriptors, each of which points to one or more data buffers for
118  * the device to read from or fill.  Driver and device exchange status of each
119  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
120  * entries in each circular buffer, to protect against confusing empty and full
121  * queue states.
122  *
123  * The device reads or writes the data in the queues via the device's several
124  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
125  *
126  * For Tx queue, there are low mark and high mark limits. If, after queuing
127  * the packet for Tx, free space become < low mark, Tx queue stopped. When
128  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
129  * Tx queue resumed.
130  *
131  * The 3945 operates with six queues:  One receive queue, one transmit queue
132  * (#4) for sending commands to the device firmware, and four transmit queues
133  * (#0-3) for data tx via EDCA.  An additional 2 HCCA queues are unused.
134  ***************************************************/
135
136 int iwl3945_queue_space(const struct iwl3945_queue *q)
137 {
138         int s = q->read_ptr - q->write_ptr;
139
140         if (q->read_ptr > q->write_ptr)
141                 s -= q->n_bd;
142
143         if (s <= 0)
144                 s += q->n_window;
145         /* keep some reserve to not confuse empty and full situations */
146         s -= 2;
147         if (s < 0)
148                 s = 0;
149         return s;
150 }
151
152 int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
153 {
154         return q->write_ptr > q->read_ptr ?
155                 (i >= q->read_ptr && i < q->write_ptr) :
156                 !(i < q->read_ptr && i >= q->write_ptr);
157 }
158
159
160 static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
161 {
162         /* This is for scan command, the big buffer at end of command array */
163         if (is_huge)
164                 return q->n_window;     /* must be power of 2 */
165
166         /* Otherwise, use normal size buffers */
167         return index & (q->n_window - 1);
168 }
169
170 /**
171  * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
172  */
173 static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
174                           int count, int slots_num, u32 id)
175 {
176         q->n_bd = count;
177         q->n_window = slots_num;
178         q->id = id;
179
180         /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
181          * and iwl_queue_dec_wrap are broken. */
182         BUG_ON(!is_power_of_2(count));
183
184         /* slots_num must be power-of-two size, otherwise
185          * get_cmd_index is broken. */
186         BUG_ON(!is_power_of_2(slots_num));
187
188         q->low_mark = q->n_window / 4;
189         if (q->low_mark < 4)
190                 q->low_mark = 4;
191
192         q->high_mark = q->n_window / 8;
193         if (q->high_mark < 2)
194                 q->high_mark = 2;
195
196         q->write_ptr = q->read_ptr = 0;
197
198         return 0;
199 }
200
201 /**
202  * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
203  */
204 static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
205                               struct iwl3945_tx_queue *txq, u32 id)
206 {
207         struct pci_dev *dev = priv->pci_dev;
208
209         /* Driver private data, only for Tx (not command) queues,
210          * not shared with device. */
211         if (id != IWL_CMD_QUEUE_NUM) {
212                 txq->txb = kmalloc(sizeof(txq->txb[0]) *
213                                    TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
214                 if (!txq->txb) {
215                         IWL_ERROR("kmalloc for auxiliary BD "
216                                   "structures failed\n");
217                         goto error;
218                 }
219         } else
220                 txq->txb = NULL;
221
222         /* Circular buffer of transmit frame descriptors (TFDs),
223          * shared with device */
224         txq->bd = pci_alloc_consistent(dev,
225                         sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
226                         &txq->q.dma_addr);
227
228         if (!txq->bd) {
229                 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
230                           sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
231                 goto error;
232         }
233         txq->q.id = id;
234
235         return 0;
236
237  error:
238         kfree(txq->txb);
239         txq->txb = NULL;
240
241         return -ENOMEM;
242 }
243
244 /**
245  * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
246  */
247 int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
248                       struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
249 {
250         struct pci_dev *dev = priv->pci_dev;
251         int len;
252         int rc = 0;
253
254         /*
255          * Alloc buffer array for commands (Tx or other types of commands).
256          * For the command queue (#4), allocate command space + one big
257          * command for scan, since scan command is very huge; the system will
258          * not have two scans at the same time, so only one is needed.
259          * For data Tx queues (all other queues), no super-size command
260          * space is needed.
261          */
262         len = sizeof(struct iwl3945_cmd) * slots_num;
263         if (txq_id == IWL_CMD_QUEUE_NUM)
264                 len +=  IWL_MAX_SCAN_SIZE;
265         txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
266         if (!txq->cmd)
267                 return -ENOMEM;
268
269         /* Alloc driver data array and TFD circular buffer */
270         rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
271         if (rc) {
272                 pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
273
274                 return -ENOMEM;
275         }
276         txq->need_update = 0;
277
278         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
279          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
280         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
281
282         /* Initialize queue high/low-water, head/tail indexes */
283         iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
284
285         /* Tell device where to find queue, enable DMA channel. */
286         iwl3945_hw_tx_queue_init(priv, txq);
287
288         return 0;
289 }
290
291 /**
292  * iwl3945_tx_queue_free - Deallocate DMA queue.
293  * @txq: Transmit queue to deallocate.
294  *
295  * Empty queue by removing and destroying all BD's.
296  * Free all buffers.
297  * 0-fill, but do not free "txq" descriptor structure.
298  */
299 void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
300 {
301         struct iwl3945_queue *q = &txq->q;
302         struct pci_dev *dev = priv->pci_dev;
303         int len;
304
305         if (q->n_bd == 0)
306                 return;
307
308         /* first, empty all BD's */
309         for (; q->write_ptr != q->read_ptr;
310              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
311                 iwl3945_hw_txq_free_tfd(priv, txq);
312
313         len = sizeof(struct iwl3945_cmd) * q->n_window;
314         if (q->id == IWL_CMD_QUEUE_NUM)
315                 len += IWL_MAX_SCAN_SIZE;
316
317         /* De-alloc array of command/tx buffers */
318         pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
319
320         /* De-alloc circular buffer of TFDs */
321         if (txq->q.n_bd)
322                 pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
323                                     txq->q.n_bd, txq->bd, txq->q.dma_addr);
324
325         /* De-alloc array of per-TFD driver data */
326         kfree(txq->txb);
327         txq->txb = NULL;
328
329         /* 0-fill queue descriptor structure */
330         memset(txq, 0, sizeof(*txq));
331 }
332
333 const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
334
335 /*************** STATION TABLE MANAGEMENT ****
336  * mac80211 should be examined to determine if sta_info is duplicating
337  * the functionality provided here
338  */
339
340 /**************************************************************/
341 #if 0 /* temporary disable till we add real remove station */
342 /**
343  * iwl3945_remove_station - Remove driver's knowledge of station.
344  *
345  * NOTE:  This does not remove station from device's station table.
346  */
347 static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
348 {
349         int index = IWL_INVALID_STATION;
350         int i;
351         unsigned long flags;
352
353         spin_lock_irqsave(&priv->sta_lock, flags);
354
355         if (is_ap)
356                 index = IWL_AP_ID;
357         else if (is_broadcast_ether_addr(addr))
358                 index = priv->hw_setting.bcast_sta_id;
359         else
360                 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
361                         if (priv->stations[i].used &&
362                             !compare_ether_addr(priv->stations[i].sta.sta.addr,
363                                                 addr)) {
364                                 index = i;
365                                 break;
366                         }
367
368         if (unlikely(index == IWL_INVALID_STATION))
369                 goto out;
370
371         if (priv->stations[index].used) {
372                 priv->stations[index].used = 0;
373                 priv->num_stations--;
374         }
375
376         BUG_ON(priv->num_stations < 0);
377
378 out:
379         spin_unlock_irqrestore(&priv->sta_lock, flags);
380         return 0;
381 }
382 #endif
383
384 /**
385  * iwl3945_clear_stations_table - Clear the driver's station table
386  *
387  * NOTE:  This does not clear or otherwise alter the device's station table.
388  */
389 static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
390 {
391         unsigned long flags;
392
393         spin_lock_irqsave(&priv->sta_lock, flags);
394
395         priv->num_stations = 0;
396         memset(priv->stations, 0, sizeof(priv->stations));
397
398         spin_unlock_irqrestore(&priv->sta_lock, flags);
399 }
400
401 /**
402  * iwl3945_add_station - Add station to station tables in driver and device
403  */
404 u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
405 {
406         int i;
407         int index = IWL_INVALID_STATION;
408         struct iwl3945_station_entry *station;
409         unsigned long flags_spin;
410         u8 rate;
411
412         spin_lock_irqsave(&priv->sta_lock, flags_spin);
413         if (is_ap)
414                 index = IWL_AP_ID;
415         else if (is_broadcast_ether_addr(addr))
416                 index = priv->hw_setting.bcast_sta_id;
417         else
418                 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
419                         if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
420                                                 addr)) {
421                                 index = i;
422                                 break;
423                         }
424
425                         if (!priv->stations[i].used &&
426                             index == IWL_INVALID_STATION)
427                                 index = i;
428                 }
429
430         /* These two conditions has the same outcome but keep them separate
431           since they have different meaning */
432         if (unlikely(index == IWL_INVALID_STATION)) {
433                 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
434                 return index;
435         }
436
437         if (priv->stations[index].used &&
438            !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
439                 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
440                 return index;
441         }
442
443         IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
444         station = &priv->stations[index];
445         station->used = 1;
446         priv->num_stations++;
447
448         /* Set up the REPLY_ADD_STA command to send to device */
449         memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
450         memcpy(station->sta.sta.addr, addr, ETH_ALEN);
451         station->sta.mode = 0;
452         station->sta.sta.sta_id = index;
453         station->sta.station_flags = 0;
454
455         if (priv->band == IEEE80211_BAND_5GHZ)
456                 rate = IWL_RATE_6M_PLCP;
457         else
458                 rate =  IWL_RATE_1M_PLCP;
459
460         /* Turn on both antennas for the station... */
461         station->sta.rate_n_flags =
462                         iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
463         station->current_rate.rate_n_flags =
464                         le16_to_cpu(station->sta.rate_n_flags);
465
466         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
467
468         /* Add station to device's station table */
469         iwl3945_send_add_station(priv, &station->sta, flags);
470         return index;
471
472 }
473
474 /*************** DRIVER STATUS FUNCTIONS   *****/
475
476 static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
477 {
478         /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
479          * set but EXIT_PENDING is not */
480         return test_bit(STATUS_READY, &priv->status) &&
481                test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
482                !test_bit(STATUS_EXIT_PENDING, &priv->status);
483 }
484
485 static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
486 {
487         return test_bit(STATUS_ALIVE, &priv->status);
488 }
489
490 static inline int iwl3945_is_init(struct iwl3945_priv *priv)
491 {
492         return test_bit(STATUS_INIT, &priv->status);
493 }
494
495 static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv)
496 {
497         return test_bit(STATUS_RF_KILL_SW, &priv->status);
498 }
499
500 static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv)
501 {
502         return test_bit(STATUS_RF_KILL_HW, &priv->status);
503 }
504
505 static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
506 {
507         return iwl3945_is_rfkill_hw(priv) ||
508                 iwl3945_is_rfkill_sw(priv);
509 }
510
511 static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
512 {
513
514         if (iwl3945_is_rfkill(priv))
515                 return 0;
516
517         return iwl3945_is_ready(priv);
518 }
519
520 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
521
522 #define IWL_CMD(x) case x : return #x
523
524 static const char *get_cmd_string(u8 cmd)
525 {
526         switch (cmd) {
527                 IWL_CMD(REPLY_ALIVE);
528                 IWL_CMD(REPLY_ERROR);
529                 IWL_CMD(REPLY_RXON);
530                 IWL_CMD(REPLY_RXON_ASSOC);
531                 IWL_CMD(REPLY_QOS_PARAM);
532                 IWL_CMD(REPLY_RXON_TIMING);
533                 IWL_CMD(REPLY_ADD_STA);
534                 IWL_CMD(REPLY_REMOVE_STA);
535                 IWL_CMD(REPLY_REMOVE_ALL_STA);
536                 IWL_CMD(REPLY_3945_RX);
537                 IWL_CMD(REPLY_TX);
538                 IWL_CMD(REPLY_RATE_SCALE);
539                 IWL_CMD(REPLY_LEDS_CMD);
540                 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
541                 IWL_CMD(RADAR_NOTIFICATION);
542                 IWL_CMD(REPLY_QUIET_CMD);
543                 IWL_CMD(REPLY_CHANNEL_SWITCH);
544                 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
545                 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
546                 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
547                 IWL_CMD(POWER_TABLE_CMD);
548                 IWL_CMD(PM_SLEEP_NOTIFICATION);
549                 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
550                 IWL_CMD(REPLY_SCAN_CMD);
551                 IWL_CMD(REPLY_SCAN_ABORT_CMD);
552                 IWL_CMD(SCAN_START_NOTIFICATION);
553                 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
554                 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
555                 IWL_CMD(BEACON_NOTIFICATION);
556                 IWL_CMD(REPLY_TX_BEACON);
557                 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
558                 IWL_CMD(QUIET_NOTIFICATION);
559                 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
560                 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
561                 IWL_CMD(REPLY_BT_CONFIG);
562                 IWL_CMD(REPLY_STATISTICS_CMD);
563                 IWL_CMD(STATISTICS_NOTIFICATION);
564                 IWL_CMD(REPLY_CARD_STATE_CMD);
565                 IWL_CMD(CARD_STATE_NOTIFICATION);
566                 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
567         default:
568                 return "UNKNOWN";
569
570         }
571 }
572
573 #define HOST_COMPLETE_TIMEOUT (HZ / 2)
574
575 /**
576  * iwl3945_enqueue_hcmd - enqueue a uCode command
577  * @priv: device private data point
578  * @cmd: a point to the ucode command structure
579  *
580  * The function returns < 0 values to indicate the operation is
581  * failed. On success, it turns the index (> 0) of command in the
582  * command queue.
583  */
584 static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
585 {
586         struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
587         struct iwl3945_queue *q = &txq->q;
588         struct iwl3945_tfd_frame *tfd;
589         u32 *control_flags;
590         struct iwl3945_cmd *out_cmd;
591         u32 idx;
592         u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
593         dma_addr_t phys_addr;
594         int pad;
595         u16 count;
596         int ret;
597         unsigned long flags;
598
599         /* If any of the command structures end up being larger than
600          * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
601          * we will need to increase the size of the TFD entries */
602         BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
603                !(cmd->meta.flags & CMD_SIZE_HUGE));
604
605
606         if (iwl3945_is_rfkill(priv)) {
607                 IWL_DEBUG_INFO("Not sending command - RF KILL");
608                 return -EIO;
609         }
610
611         if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
612                 IWL_ERROR("No space for Tx\n");
613                 return -ENOSPC;
614         }
615
616         spin_lock_irqsave(&priv->hcmd_lock, flags);
617
618         tfd = &txq->bd[q->write_ptr];
619         memset(tfd, 0, sizeof(*tfd));
620
621         control_flags = (u32 *) tfd;
622
623         idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
624         out_cmd = &txq->cmd[idx];
625
626         out_cmd->hdr.cmd = cmd->id;
627         memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
628         memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
629
630         /* At this point, the out_cmd now has all of the incoming cmd
631          * information */
632
633         out_cmd->hdr.flags = 0;
634         out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
635                         INDEX_TO_SEQ(q->write_ptr));
636         if (out_cmd->meta.flags & CMD_SIZE_HUGE)
637                 out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
638
639         phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
640                         offsetof(struct iwl3945_cmd, hdr);
641         iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
642
643         pad = U32_PAD(cmd->len);
644         count = TFD_CTL_COUNT_GET(*control_flags);
645         *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
646
647         IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
648                      "%d bytes at %d[%d]:%d\n",
649                      get_cmd_string(out_cmd->hdr.cmd),
650                      out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
651                      fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
652
653         txq->need_update = 1;
654
655         /* Increment and update queue's write index */
656         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
657         ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
658
659         spin_unlock_irqrestore(&priv->hcmd_lock, flags);
660         return ret ? ret : idx;
661 }
662
663 static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
664 {
665         int ret;
666
667         BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
668
669         /* An asynchronous command can not expect an SKB to be set. */
670         BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
671
672         /* An asynchronous command MUST have a callback. */
673         BUG_ON(!cmd->meta.u.callback);
674
675         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
676                 return -EBUSY;
677
678         ret = iwl3945_enqueue_hcmd(priv, cmd);
679         if (ret < 0) {
680                 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
681                           get_cmd_string(cmd->id), ret);
682                 return ret;
683         }
684         return 0;
685 }
686
687 static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
688 {
689         int cmd_idx;
690         int ret;
691
692         BUG_ON(cmd->meta.flags & CMD_ASYNC);
693
694          /* A synchronous command can not have a callback set. */
695         BUG_ON(cmd->meta.u.callback != NULL);
696
697         if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
698                 IWL_ERROR("Error sending %s: Already sending a host command\n",
699                           get_cmd_string(cmd->id));
700                 ret = -EBUSY;
701                 goto out;
702         }
703
704         set_bit(STATUS_HCMD_ACTIVE, &priv->status);
705
706         if (cmd->meta.flags & CMD_WANT_SKB)
707                 cmd->meta.source = &cmd->meta;
708
709         cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
710         if (cmd_idx < 0) {
711                 ret = cmd_idx;
712                 IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
713                           get_cmd_string(cmd->id), ret);
714                 goto out;
715         }
716
717         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
718                         !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
719                         HOST_COMPLETE_TIMEOUT);
720         if (!ret) {
721                 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
722                         IWL_ERROR("Error sending %s: time out after %dms.\n",
723                                   get_cmd_string(cmd->id),
724                                   jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
725
726                         clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
727                         ret = -ETIMEDOUT;
728                         goto cancel;
729                 }
730         }
731
732         if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
733                 IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
734                                get_cmd_string(cmd->id));
735                 ret = -ECANCELED;
736                 goto fail;
737         }
738         if (test_bit(STATUS_FW_ERROR, &priv->status)) {
739                 IWL_DEBUG_INFO("Command %s failed: FW Error\n",
740                                get_cmd_string(cmd->id));
741                 ret = -EIO;
742                 goto fail;
743         }
744         if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
745                 IWL_ERROR("Error: Response NULL in '%s'\n",
746                           get_cmd_string(cmd->id));
747                 ret = -EIO;
748                 goto out;
749         }
750
751         ret = 0;
752         goto out;
753
754 cancel:
755         if (cmd->meta.flags & CMD_WANT_SKB) {
756                 struct iwl3945_cmd *qcmd;
757
758                 /* Cancel the CMD_WANT_SKB flag for the cmd in the
759                  * TX cmd queue. Otherwise in case the cmd comes
760                  * in later, it will possibly set an invalid
761                  * address (cmd->meta.source). */
762                 qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
763                 qcmd->meta.flags &= ~CMD_WANT_SKB;
764         }
765 fail:
766         if (cmd->meta.u.skb) {
767                 dev_kfree_skb_any(cmd->meta.u.skb);
768                 cmd->meta.u.skb = NULL;
769         }
770 out:
771         clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
772         return ret;
773 }
774
775 int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
776 {
777         if (cmd->meta.flags & CMD_ASYNC)
778                 return iwl3945_send_cmd_async(priv, cmd);
779
780         return iwl3945_send_cmd_sync(priv, cmd);
781 }
782
783 int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
784 {
785         struct iwl3945_host_cmd cmd = {
786                 .id = id,
787                 .len = len,
788                 .data = data,
789         };
790
791         return iwl3945_send_cmd_sync(priv, &cmd);
792 }
793
794 static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
795 {
796         struct iwl3945_host_cmd cmd = {
797                 .id = id,
798                 .len = sizeof(val),
799                 .data = &val,
800         };
801
802         return iwl3945_send_cmd_sync(priv, &cmd);
803 }
804
805 int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
806 {
807         return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
808 }
809
810 /**
811  * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
812  * @band: 2.4 or 5 GHz band
813  * @channel: Any channel valid for the requested band
814
815  * In addition to setting the staging RXON, priv->band is also set.
816  *
817  * NOTE:  Does not commit to the hardware; it sets appropriate bit fields
818  * in the staging RXON flag structure based on the band
819  */
820 static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
821                                     enum ieee80211_band band,
822                                     u16 channel)
823 {
824         if (!iwl3945_get_channel_info(priv, band, channel)) {
825                 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
826                                channel, band);
827                 return -EINVAL;
828         }
829
830         if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
831             (priv->band == band))
832                 return 0;
833
834         priv->staging_rxon.channel = cpu_to_le16(channel);
835         if (band == IEEE80211_BAND_5GHZ)
836                 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
837         else
838                 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
839
840         priv->band = band;
841
842         IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
843
844         return 0;
845 }
846
847 /**
848  * iwl3945_check_rxon_cmd - validate RXON structure is valid
849  *
850  * NOTE:  This is really only useful during development and can eventually
851  * be #ifdef'd out once the driver is stable and folks aren't actively
852  * making changes
853  */
854 static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
855 {
856         int error = 0;
857         int counter = 1;
858
859         if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
860                 error |= le32_to_cpu(rxon->flags &
861                                 (RXON_FLG_TGJ_NARROW_BAND_MSK |
862                                  RXON_FLG_RADAR_DETECT_MSK));
863                 if (error)
864                         IWL_WARNING("check 24G fields %d | %d\n",
865                                     counter++, error);
866         } else {
867                 error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
868                                 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
869                 if (error)
870                         IWL_WARNING("check 52 fields %d | %d\n",
871                                     counter++, error);
872                 error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
873                 if (error)
874                         IWL_WARNING("check 52 CCK %d | %d\n",
875                                     counter++, error);
876         }
877         error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
878         if (error)
879                 IWL_WARNING("check mac addr %d | %d\n", counter++, error);
880
881         /* make sure basic rates 6Mbps and 1Mbps are supported */
882         error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
883                   ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
884         if (error)
885                 IWL_WARNING("check basic rate %d | %d\n", counter++, error);
886
887         error |= (le16_to_cpu(rxon->assoc_id) > 2007);
888         if (error)
889                 IWL_WARNING("check assoc id %d | %d\n", counter++, error);
890
891         error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
892                         == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
893         if (error)
894                 IWL_WARNING("check CCK and short slot %d | %d\n",
895                             counter++, error);
896
897         error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
898                         == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
899         if (error)
900                 IWL_WARNING("check CCK & auto detect %d | %d\n",
901                             counter++, error);
902
903         error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
904                         RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
905         if (error)
906                 IWL_WARNING("check TGG and auto detect %d | %d\n",
907                             counter++, error);
908
909         if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
910                 error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
911                                 RXON_FLG_ANT_A_MSK)) == 0);
912         if (error)
913                 IWL_WARNING("check antenna %d %d\n", counter++, error);
914
915         if (error)
916                 IWL_WARNING("Tuning to channel %d\n",
917                             le16_to_cpu(rxon->channel));
918
919         if (error) {
920                 IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
921                 return -1;
922         }
923         return 0;
924 }
925
926 /**
927  * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
928  * @priv: staging_rxon is compared to active_rxon
929  *
930  * If the RXON structure is changing enough to require a new tune,
931  * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
932  * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
933  */
934 static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
935 {
936
937         /* These items are only settable from the full RXON command */
938         if (!(iwl3945_is_associated(priv)) ||
939             compare_ether_addr(priv->staging_rxon.bssid_addr,
940                                priv->active_rxon.bssid_addr) ||
941             compare_ether_addr(priv->staging_rxon.node_addr,
942                                priv->active_rxon.node_addr) ||
943             compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
944                                priv->active_rxon.wlap_bssid_addr) ||
945             (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
946             (priv->staging_rxon.channel != priv->active_rxon.channel) ||
947             (priv->staging_rxon.air_propagation !=
948              priv->active_rxon.air_propagation) ||
949             (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
950                 return 1;
951
952         /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
953          * be updated with the RXON_ASSOC command -- however only some
954          * flag transitions are allowed using RXON_ASSOC */
955
956         /* Check if we are not switching bands */
957         if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
958             (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
959                 return 1;
960
961         /* Check if we are switching association toggle */
962         if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
963                 (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
964                 return 1;
965
966         return 0;
967 }
968
969 static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
970 {
971         int rc = 0;
972         struct iwl3945_rx_packet *res = NULL;
973         struct iwl3945_rxon_assoc_cmd rxon_assoc;
974         struct iwl3945_host_cmd cmd = {
975                 .id = REPLY_RXON_ASSOC,
976                 .len = sizeof(rxon_assoc),
977                 .meta.flags = CMD_WANT_SKB,
978                 .data = &rxon_assoc,
979         };
980         const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
981         const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
982
983         if ((rxon1->flags == rxon2->flags) &&
984             (rxon1->filter_flags == rxon2->filter_flags) &&
985             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
986             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
987                 IWL_DEBUG_INFO("Using current RXON_ASSOC.  Not resending.\n");
988                 return 0;
989         }
990
991         rxon_assoc.flags = priv->staging_rxon.flags;
992         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
993         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
994         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
995         rxon_assoc.reserved = 0;
996
997         rc = iwl3945_send_cmd_sync(priv, &cmd);
998         if (rc)
999                 return rc;
1000
1001         res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
1002         if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1003                 IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
1004                 rc = -EIO;
1005         }
1006
1007         priv->alloc_rxb_skb--;
1008         dev_kfree_skb_any(cmd.meta.u.skb);
1009
1010         return rc;
1011 }
1012
1013 /**
1014  * iwl3945_commit_rxon - commit staging_rxon to hardware
1015  *
1016  * The RXON command in staging_rxon is committed to the hardware and
1017  * the active_rxon structure is updated with the new data.  This
1018  * function correctly transitions out of the RXON_ASSOC_MSK state if
1019  * a HW tune is required based on the RXON structure changes.
1020  */
1021 static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
1022 {
1023         /* cast away the const for active_rxon in this function */
1024         struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1025         int rc = 0;
1026
1027         if (!iwl3945_is_alive(priv))
1028                 return -1;
1029
1030         /* always get timestamp with Rx frame */
1031         priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
1032
1033         /* select antenna */
1034         priv->staging_rxon.flags &=
1035             ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1036         priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
1037
1038         rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
1039         if (rc) {
1040                 IWL_ERROR("Invalid RXON configuration.  Not committing.\n");
1041                 return -EINVAL;
1042         }
1043
1044         /* If we don't need to send a full RXON, we can use
1045          * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1046          * and other flags for the current radio configuration. */
1047         if (!iwl3945_full_rxon_required(priv)) {
1048                 rc = iwl3945_send_rxon_assoc(priv);
1049                 if (rc) {
1050                         IWL_ERROR("Error setting RXON_ASSOC "
1051                                   "configuration (%d).\n", rc);
1052                         return rc;
1053                 }
1054
1055                 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1056
1057                 return 0;
1058         }
1059
1060         /* If we are currently associated and the new config requires
1061          * an RXON_ASSOC and the new config wants the associated mask enabled,
1062          * we must clear the associated from the active configuration
1063          * before we apply the new config */
1064         if (iwl3945_is_associated(priv) &&
1065             (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
1066                 IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
1067                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1068
1069                 rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1070                                       sizeof(struct iwl3945_rxon_cmd),
1071                                       &priv->active_rxon);
1072
1073                 /* If the mask clearing failed then we set
1074                  * active_rxon back to what it was previously */
1075                 if (rc) {
1076                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1077                         IWL_ERROR("Error clearing ASSOC_MSK on current "
1078                                   "configuration (%d).\n", rc);
1079                         return rc;
1080                 }
1081         }
1082
1083         IWL_DEBUG_INFO("Sending RXON\n"
1084                        "* with%s RXON_FILTER_ASSOC_MSK\n"
1085                        "* channel = %d\n"
1086                        "* bssid = %pM\n",
1087                        ((priv->staging_rxon.filter_flags &
1088                          RXON_FILTER_ASSOC_MSK) ? "" : "out"),
1089                        le16_to_cpu(priv->staging_rxon.channel),
1090                        priv->staging_rxon.bssid_addr);
1091
1092         /* Apply the new configuration */
1093         rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
1094                               sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
1095         if (rc) {
1096                 IWL_ERROR("Error setting new configuration (%d).\n", rc);
1097                 return rc;
1098         }
1099
1100         memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
1101
1102         iwl3945_clear_stations_table(priv);
1103
1104         /* If we issue a new RXON command which required a tune then we must
1105          * send a new TXPOWER command or we won't be able to Tx any frames */
1106         rc = iwl3945_hw_reg_send_txpower(priv);
1107         if (rc) {
1108                 IWL_ERROR("Error setting Tx power (%d).\n", rc);
1109                 return rc;
1110         }
1111
1112         /* Add the broadcast address so we can send broadcast frames */
1113         if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
1114             IWL_INVALID_STATION) {
1115                 IWL_ERROR("Error adding BROADCAST address for transmit.\n");
1116                 return -EIO;
1117         }
1118
1119         /* If we have set the ASSOC_MSK and we are in BSS mode then
1120          * add the IWL_AP_ID to the station rate table */
1121         if (iwl3945_is_associated(priv) &&
1122             (priv->iw_mode == NL80211_IFTYPE_STATION))
1123                 if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
1124                     == IWL_INVALID_STATION) {
1125                         IWL_ERROR("Error adding AP address for transmit.\n");
1126                         return -EIO;
1127                 }
1128
1129         /* Init the hardware's rate fallback order based on the band */
1130         rc = iwl3945_init_hw_rate_table(priv);
1131         if (rc) {
1132                 IWL_ERROR("Error setting HW rate table: %02X\n", rc);
1133                 return -EIO;
1134         }
1135
1136         return 0;
1137 }
1138
1139 static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
1140 {
1141         struct iwl3945_bt_cmd bt_cmd = {
1142                 .flags = 3,
1143                 .lead_time = 0xAA,
1144                 .max_kill = 1,
1145                 .kill_ack_mask = 0,
1146                 .kill_cts_mask = 0,
1147         };
1148
1149         return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1150                                 sizeof(struct iwl3945_bt_cmd), &bt_cmd);
1151 }
1152
1153 static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
1154 {
1155         int rc = 0;
1156         struct iwl3945_rx_packet *res;
1157         struct iwl3945_host_cmd cmd = {
1158                 .id = REPLY_SCAN_ABORT_CMD,
1159                 .meta.flags = CMD_WANT_SKB,
1160         };
1161
1162         /* If there isn't a scan actively going on in the hardware
1163          * then we are in between scan bands and not actually
1164          * actively scanning, so don't send the abort command */
1165         if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1166                 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1167                 return 0;
1168         }
1169
1170         rc = iwl3945_send_cmd_sync(priv, &cmd);
1171         if (rc) {
1172                 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1173                 return rc;
1174         }
1175
1176         res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
1177         if (res->u.status != CAN_ABORT_STATUS) {
1178                 /* The scan abort will return 1 for success or
1179                  * 2 for "failure".  A failure condition can be
1180                  * due to simply not being in an active scan which
1181                  * can occur if we send the scan abort before we
1182                  * the microcode has notified us that a scan is
1183                  * completed. */
1184                 IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
1185                 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
1186                 clear_bit(STATUS_SCAN_HW, &priv->status);
1187         }
1188
1189         dev_kfree_skb_any(cmd.meta.u.skb);
1190
1191         return rc;
1192 }
1193
1194 static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
1195                                         struct iwl3945_cmd *cmd,
1196                                         struct sk_buff *skb)
1197 {
1198         return 1;
1199 }
1200
1201 /*
1202  * CARD_STATE_CMD
1203  *
1204  * Use: Sets the device's internal card state to enable, disable, or halt
1205  *
1206  * When in the 'enable' state the card operates as normal.
1207  * When in the 'disable' state, the card enters into a low power mode.
1208  * When in the 'halt' state, the card is shut down and must be fully
1209  * restarted to come back on.
1210  */
1211 static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
1212 {
1213         struct iwl3945_host_cmd cmd = {
1214                 .id = REPLY_CARD_STATE_CMD,
1215                 .len = sizeof(u32),
1216                 .data = &flags,
1217                 .meta.flags = meta_flag,
1218         };
1219
1220         if (meta_flag & CMD_ASYNC)
1221                 cmd.meta.u.callback = iwl3945_card_state_sync_callback;
1222
1223         return iwl3945_send_cmd(priv, &cmd);
1224 }
1225
1226 static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
1227                                      struct iwl3945_cmd *cmd, struct sk_buff *skb)
1228 {
1229         struct iwl3945_rx_packet *res = NULL;
1230
1231         if (!skb) {
1232                 IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
1233                 return 1;
1234         }
1235
1236         res = (struct iwl3945_rx_packet *)skb->data;
1237         if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1238                 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1239                           res->hdr.flags);
1240                 return 1;
1241         }
1242
1243         switch (res->u.add_sta.status) {
1244         case ADD_STA_SUCCESS_MSK:
1245                 break;
1246         default:
1247                 break;
1248         }
1249
1250         /* We didn't cache the SKB; let the caller free it */
1251         return 1;
1252 }
1253
1254 int iwl3945_send_add_station(struct iwl3945_priv *priv,
1255                          struct iwl3945_addsta_cmd *sta, u8 flags)
1256 {
1257         struct iwl3945_rx_packet *res = NULL;
1258         int rc = 0;
1259         struct iwl3945_host_cmd cmd = {
1260                 .id = REPLY_ADD_STA,
1261                 .len = sizeof(struct iwl3945_addsta_cmd),
1262                 .meta.flags = flags,
1263                 .data = sta,
1264         };
1265
1266         if (flags & CMD_ASYNC)
1267                 cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
1268         else
1269                 cmd.meta.flags |= CMD_WANT_SKB;
1270
1271         rc = iwl3945_send_cmd(priv, &cmd);
1272
1273         if (rc || (flags & CMD_ASYNC))
1274                 return rc;
1275
1276         res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
1277         if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1278                 IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
1279                           res->hdr.flags);
1280                 rc = -EIO;
1281         }
1282
1283         if (rc == 0) {
1284                 switch (res->u.add_sta.status) {
1285                 case ADD_STA_SUCCESS_MSK:
1286                         IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
1287                         break;
1288                 default:
1289                         rc = -EIO;
1290                         IWL_WARNING("REPLY_ADD_STA failed\n");
1291                         break;
1292                 }
1293         }
1294
1295         priv->alloc_rxb_skb--;
1296         dev_kfree_skb_any(cmd.meta.u.skb);
1297
1298         return rc;
1299 }
1300
1301 static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
1302                                    struct ieee80211_key_conf *keyconf,
1303                                    u8 sta_id)
1304 {
1305         unsigned long flags;
1306         __le16 key_flags = 0;
1307
1308         switch (keyconf->alg) {
1309         case ALG_CCMP:
1310                 key_flags |= STA_KEY_FLG_CCMP;
1311                 key_flags |= cpu_to_le16(
1312                                 keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
1313                 key_flags &= ~STA_KEY_FLG_INVALID;
1314                 break;
1315         case ALG_TKIP:
1316         case ALG_WEP:
1317         default:
1318                 return -EINVAL;
1319         }
1320         spin_lock_irqsave(&priv->sta_lock, flags);
1321         priv->stations[sta_id].keyinfo.alg = keyconf->alg;
1322         priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
1323         memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
1324                keyconf->keylen);
1325
1326         memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
1327                keyconf->keylen);
1328         priv->stations[sta_id].sta.key.key_flags = key_flags;
1329         priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1330         priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1331
1332         spin_unlock_irqrestore(&priv->sta_lock, flags);
1333
1334         IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
1335         iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
1336         return 0;
1337 }
1338
1339 static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
1340 {
1341         unsigned long flags;
1342
1343         spin_lock_irqsave(&priv->sta_lock, flags);
1344         memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
1345         memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
1346         priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
1347         priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
1348         priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
1349         spin_unlock_irqrestore(&priv->sta_lock, flags);
1350
1351         IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
1352         iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
1353         return 0;
1354 }
1355
1356 static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
1357 {
1358         struct list_head *element;
1359
1360         IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
1361                        priv->frames_count);
1362
1363         while (!list_empty(&priv->free_frames)) {
1364                 element = priv->free_frames.next;
1365                 list_del(element);
1366                 kfree(list_entry(element, struct iwl3945_frame, list));
1367                 priv->frames_count--;
1368         }
1369
1370         if (priv->frames_count) {
1371                 IWL_WARNING("%d frames still in use.  Did we lose one?\n",
1372                             priv->frames_count);
1373                 priv->frames_count = 0;
1374         }
1375 }
1376
1377 static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
1378 {
1379         struct iwl3945_frame *frame;
1380         struct list_head *element;
1381         if (list_empty(&priv->free_frames)) {
1382                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1383                 if (!frame) {
1384                         IWL_ERROR("Could not allocate frame!\n");
1385                         return NULL;
1386                 }
1387
1388                 priv->frames_count++;
1389                 return frame;
1390         }
1391
1392         element = priv->free_frames.next;
1393         list_del(element);
1394         return list_entry(element, struct iwl3945_frame, list);
1395 }
1396
1397 static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
1398 {
1399         memset(frame, 0, sizeof(*frame));
1400         list_add(&frame->list, &priv->free_frames);
1401 }
1402
1403 unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
1404                                 struct ieee80211_hdr *hdr,
1405                                 const u8 *dest, int left)
1406 {
1407
1408         if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
1409             ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
1410              (priv->iw_mode != NL80211_IFTYPE_AP)))
1411                 return 0;
1412
1413         if (priv->ibss_beacon->len > left)
1414                 return 0;
1415
1416         memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
1417
1418         return priv->ibss_beacon->len;
1419 }
1420
1421 static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
1422 {
1423         u8 i;
1424
1425         for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
1426              i = iwl3945_rates[i].next_ieee) {
1427                 if (rate_mask & (1 << i))
1428                         return iwl3945_rates[i].plcp;
1429         }
1430
1431         return IWL_RATE_INVALID;
1432 }
1433
1434 static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
1435 {
1436         struct iwl3945_frame *frame;
1437         unsigned int frame_size;
1438         int rc;
1439         u8 rate;
1440
1441         frame = iwl3945_get_free_frame(priv);
1442
1443         if (!frame) {
1444                 IWL_ERROR("Could not obtain free frame buffer for beacon "
1445                           "command.\n");
1446                 return -ENOMEM;
1447         }
1448
1449         if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
1450                 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
1451                                                 0xFF0);
1452                 if (rate == IWL_INVALID_RATE)
1453                         rate = IWL_RATE_6M_PLCP;
1454         } else {
1455                 rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
1456                 if (rate == IWL_INVALID_RATE)
1457                         rate = IWL_RATE_1M_PLCP;
1458         }
1459
1460         frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
1461
1462         rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
1463                               &frame->u.cmd[0]);
1464
1465         iwl3945_free_frame(priv, frame);
1466
1467         return rc;
1468 }
1469
1470 /******************************************************************************
1471  *
1472  * EEPROM related functions
1473  *
1474  ******************************************************************************/
1475
1476 static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
1477 {
1478         memcpy(mac, priv->eeprom.mac_address, 6);
1479 }
1480
1481 /*
1482  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
1483  * embedded controller) as EEPROM reader; each read is a series of pulses
1484  * to/from the EEPROM chip, not a single event, so even reads could conflict
1485  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
1486  * simply claims ownership, which should be safe when this function is called
1487  * (i.e. before loading uCode!).
1488  */
1489 static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
1490 {
1491         _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
1492         return 0;
1493 }
1494
1495 /**
1496  * iwl3945_eeprom_init - read EEPROM contents
1497  *
1498  * Load the EEPROM contents from adapter into priv->eeprom
1499  *
1500  * NOTE:  This routine uses the non-debug IO access functions.
1501  */
1502 int iwl3945_eeprom_init(struct iwl3945_priv *priv)
1503 {
1504         u16 *e = (u16 *)&priv->eeprom;
1505         u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
1506         u32 r;
1507         int sz = sizeof(priv->eeprom);
1508         int rc;
1509         int i;
1510         u16 addr;
1511
1512         /* The EEPROM structure has several padding buffers within it
1513          * and when adding new EEPROM maps is subject to programmer errors
1514          * which may be very difficult to identify without explicitly
1515          * checking the resulting size of the eeprom map. */
1516         BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
1517
1518         if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
1519                 IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
1520                 return -ENOENT;
1521         }
1522
1523         /* Make sure driver (instead of uCode) is allowed to read EEPROM */
1524         rc = iwl3945_eeprom_acquire_semaphore(priv);
1525         if (rc < 0) {
1526                 IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
1527                 return -ENOENT;
1528         }
1529
1530         /* eeprom is an array of 16bit values */
1531         for (addr = 0; addr < sz; addr += sizeof(u16)) {
1532                 _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
1533                 _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
1534
1535                 for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
1536                                         i += IWL_EEPROM_ACCESS_DELAY) {
1537                         r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
1538                         if (r & CSR_EEPROM_REG_READ_VALID_MSK)
1539                                 break;
1540                         udelay(IWL_EEPROM_ACCESS_DELAY);
1541                 }
1542
1543                 if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
1544                         IWL_ERROR("Time out reading EEPROM[%d]\n", addr);
1545                         return -ETIMEDOUT;
1546                 }
1547                 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
1548         }
1549
1550         return 0;
1551 }
1552
1553 static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
1554 {
1555         if (priv->hw_setting.shared_virt)
1556                 pci_free_consistent(priv->pci_dev,
1557                                     sizeof(struct iwl3945_shared),
1558                                     priv->hw_setting.shared_virt,
1559                                     priv->hw_setting.shared_phys);
1560 }
1561
1562 /**
1563  * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
1564  *
1565  * return : set the bit for each supported rate insert in ie
1566  */
1567 static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
1568                                     u16 basic_rate, int *left)
1569 {
1570         u16 ret_rates = 0, bit;
1571         int i;
1572         u8 *cnt = ie;
1573         u8 *rates = ie + 1;
1574
1575         for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
1576                 if (bit & supported_rate) {
1577                         ret_rates |= bit;
1578                         rates[*cnt] = iwl3945_rates[i].ieee |
1579                                 ((bit & basic_rate) ? 0x80 : 0x00);
1580                         (*cnt)++;
1581                         (*left)--;
1582                         if ((*left <= 0) ||
1583                             (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
1584                                 break;
1585                 }
1586         }
1587
1588         return ret_rates;
1589 }
1590
1591 /**
1592  * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
1593  */
1594 static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
1595                               struct ieee80211_mgmt *frame,
1596                               int left)
1597 {
1598         int len = 0;
1599         u8 *pos = NULL;
1600         u16 active_rates, ret_rates, cck_rates;
1601
1602         /* Make sure there is enough space for the probe request,
1603          * two mandatory IEs and the data */
1604         left -= 24;
1605         if (left < 0)
1606                 return 0;
1607         len += 24;
1608
1609         frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
1610         memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
1611         memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
1612         memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
1613         frame->seq_ctrl = 0;
1614
1615         /* fill in our indirect SSID IE */
1616         /* ...next IE... */
1617
1618         left -= 2;
1619         if (left < 0)
1620                 return 0;
1621         len += 2;
1622         pos = &(frame->u.probe_req.variable[0]);
1623         *pos++ = WLAN_EID_SSID;
1624         *pos++ = 0;
1625
1626         /* fill in supported rate */
1627         /* ...next IE... */
1628         left -= 2;
1629         if (left < 0)
1630                 return 0;
1631
1632         /* ... fill it in... */
1633         *pos++ = WLAN_EID_SUPP_RATES;
1634         *pos = 0;
1635
1636         priv->active_rate = priv->rates_mask;
1637         active_rates = priv->active_rate;
1638         priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1639
1640         cck_rates = IWL_CCK_RATES_MASK & active_rates;
1641         ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
1642                         priv->active_rate_basic, &left);
1643         active_rates &= ~ret_rates;
1644
1645         ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
1646                                  priv->active_rate_basic, &left);
1647         active_rates &= ~ret_rates;
1648
1649         len += 2 + *pos;
1650         pos += (*pos) + 1;
1651         if (active_rates == 0)
1652                 goto fill_end;
1653
1654         /* fill in supported extended rate */
1655         /* ...next IE... */
1656         left -= 2;
1657         if (left < 0)
1658                 return 0;
1659         /* ... fill it in... */
1660         *pos++ = WLAN_EID_EXT_SUPP_RATES;
1661         *pos = 0;
1662         iwl3945_supported_rate_to_ie(pos, active_rates,
1663                                  priv->active_rate_basic, &left);
1664         if (*pos > 0)
1665                 len += 2 + *pos;
1666
1667  fill_end:
1668         return (u16)len;
1669 }
1670
1671 /*
1672  * QoS  support
1673 */
1674 static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
1675                                        struct iwl3945_qosparam_cmd *qos)
1676 {
1677
1678         return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
1679                                 sizeof(struct iwl3945_qosparam_cmd), qos);
1680 }
1681
1682 static void iwl3945_reset_qos(struct iwl3945_priv *priv)
1683 {
1684         u16 cw_min = 15;
1685         u16 cw_max = 1023;
1686         u8 aifs = 2;
1687         u8 is_legacy = 0;
1688         unsigned long flags;
1689         int i;
1690
1691         spin_lock_irqsave(&priv->lock, flags);
1692         priv->qos_data.qos_active = 0;
1693
1694         if (priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1695                 if (priv->qos_data.qos_enable)
1696                         priv->qos_data.qos_active = 1;
1697                 if (!(priv->active_rate & 0xfff0)) {
1698                         cw_min = 31;
1699                         is_legacy = 1;
1700                 }
1701         } else if (priv->iw_mode == NL80211_IFTYPE_AP) {
1702                 if (priv->qos_data.qos_enable)
1703                         priv->qos_data.qos_active = 1;
1704         } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
1705                 cw_min = 31;
1706                 is_legacy = 1;
1707         }
1708
1709         if (priv->qos_data.qos_active)
1710                 aifs = 3;
1711
1712         priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
1713         priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
1714         priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
1715         priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
1716         priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
1717
1718         if (priv->qos_data.qos_active) {
1719                 i = 1;
1720                 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
1721                 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
1722                 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
1723                 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1724                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1725
1726                 i = 2;
1727                 priv->qos_data.def_qos_parm.ac[i].cw_min =
1728                         cpu_to_le16((cw_min + 1) / 2 - 1);
1729                 priv->qos_data.def_qos_parm.ac[i].cw_max =
1730                         cpu_to_le16(cw_max);
1731                 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1732                 if (is_legacy)
1733                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
1734                                 cpu_to_le16(6016);
1735                 else
1736                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
1737                                 cpu_to_le16(3008);
1738                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1739
1740                 i = 3;
1741                 priv->qos_data.def_qos_parm.ac[i].cw_min =
1742                         cpu_to_le16((cw_min + 1) / 4 - 1);
1743                 priv->qos_data.def_qos_parm.ac[i].cw_max =
1744                         cpu_to_le16((cw_max + 1) / 2 - 1);
1745                 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
1746                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1747                 if (is_legacy)
1748                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
1749                                 cpu_to_le16(3264);
1750                 else
1751                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
1752                                 cpu_to_le16(1504);
1753         } else {
1754                 for (i = 1; i < 4; i++) {
1755                         priv->qos_data.def_qos_parm.ac[i].cw_min =
1756                                 cpu_to_le16(cw_min);
1757                         priv->qos_data.def_qos_parm.ac[i].cw_max =
1758                                 cpu_to_le16(cw_max);
1759                         priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
1760                         priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
1761                         priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
1762                 }
1763         }
1764         IWL_DEBUG_QOS("set QoS to default \n");
1765
1766         spin_unlock_irqrestore(&priv->lock, flags);
1767 }
1768
1769 static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
1770 {
1771         unsigned long flags;
1772
1773         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1774                 return;
1775
1776         if (!priv->qos_data.qos_enable)
1777                 return;
1778
1779         spin_lock_irqsave(&priv->lock, flags);
1780         priv->qos_data.def_qos_parm.qos_flags = 0;
1781
1782         if (priv->qos_data.qos_cap.q_AP.queue_request &&
1783             !priv->qos_data.qos_cap.q_AP.txop_request)
1784                 priv->qos_data.def_qos_parm.qos_flags |=
1785                         QOS_PARAM_FLG_TXOP_TYPE_MSK;
1786
1787         if (priv->qos_data.qos_active)
1788                 priv->qos_data.def_qos_parm.qos_flags |=
1789                         QOS_PARAM_FLG_UPDATE_EDCA_MSK;
1790
1791         spin_unlock_irqrestore(&priv->lock, flags);
1792
1793         if (force || iwl3945_is_associated(priv)) {
1794                 IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
1795                               priv->qos_data.qos_active);
1796
1797                 iwl3945_send_qos_params_command(priv,
1798                                 &(priv->qos_data.def_qos_parm));
1799         }
1800 }
1801
1802 /*
1803  * Power management (not Tx power!) functions
1804  */
1805 #define MSEC_TO_USEC 1024
1806
1807 #define NOSLP __constant_cpu_to_le32(0)
1808 #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
1809 #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
1810 #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
1811                                      __constant_cpu_to_le32(X1), \
1812                                      __constant_cpu_to_le32(X2), \
1813                                      __constant_cpu_to_le32(X3), \
1814                                      __constant_cpu_to_le32(X4)}
1815
1816
1817 /* default power management (not Tx power) table values */
1818 /* for TIM  0-10 */
1819 static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
1820         {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1821         {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
1822         {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
1823         {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
1824         {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
1825         {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
1826 };
1827
1828 /* for TIM > 10 */
1829 static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
1830         {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
1831         {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
1832                  SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
1833         {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
1834                  SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
1835         {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
1836                  SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
1837         {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
1838         {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
1839                  SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
1840 };
1841
1842 int iwl3945_power_init_handle(struct iwl3945_priv *priv)
1843 {
1844         int rc = 0, i;
1845         struct iwl3945_power_mgr *pow_data;
1846         int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
1847         u16 pci_pm;
1848
1849         IWL_DEBUG_POWER("Initialize power \n");
1850
1851         pow_data = &(priv->power_data);
1852
1853         memset(pow_data, 0, sizeof(*pow_data));
1854
1855         pow_data->active_index = IWL_POWER_RANGE_0;
1856         pow_data->dtim_val = 0xffff;
1857
1858         memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
1859         memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
1860
1861         rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
1862         if (rc != 0)
1863                 return 0;
1864         else {
1865                 struct iwl3945_powertable_cmd *cmd;
1866
1867                 IWL_DEBUG_POWER("adjust power command flags\n");
1868
1869                 for (i = 0; i < IWL_POWER_AC; i++) {
1870                         cmd = &pow_data->pwr_range_0[i].cmd;
1871
1872                         if (pci_pm & 0x1)
1873                                 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
1874                         else
1875                                 cmd->flags |= IWL_POWER_PCI_PM_MSK;
1876                 }
1877         }
1878         return rc;
1879 }
1880
1881 static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
1882                                 struct iwl3945_powertable_cmd *cmd, u32 mode)
1883 {
1884         int rc = 0, i;
1885         u8 skip;
1886         u32 max_sleep = 0;
1887         struct iwl3945_power_vec_entry *range;
1888         u8 period = 0;
1889         struct iwl3945_power_mgr *pow_data;
1890
1891         if (mode > IWL_POWER_INDEX_5) {
1892                 IWL_DEBUG_POWER("Error invalid power mode \n");
1893                 return -1;
1894         }
1895         pow_data = &(priv->power_data);
1896
1897         if (pow_data->active_index == IWL_POWER_RANGE_0)
1898                 range = &pow_data->pwr_range_0[0];
1899         else
1900                 range = &pow_data->pwr_range_1[1];
1901
1902         memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
1903
1904 #ifdef IWL_MAC80211_DISABLE
1905         if (priv->assoc_network != NULL) {
1906                 unsigned long flags;
1907
1908                 period = priv->assoc_network->tim.tim_period;
1909         }
1910 #endif  /*IWL_MAC80211_DISABLE */
1911         skip = range[mode].no_dtim;
1912
1913         if (period == 0) {
1914                 period = 1;
1915                 skip = 0;
1916         }
1917
1918         if (skip == 0) {
1919                 max_sleep = period;
1920                 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
1921         } else {
1922                 __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
1923                 max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
1924                 cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
1925         }
1926
1927         for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
1928                 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1929                         cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1930         }
1931
1932         IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
1933         IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1934         IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1935         IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1936                         le32_to_cpu(cmd->sleep_interval[0]),
1937                         le32_to_cpu(cmd->sleep_interval[1]),
1938                         le32_to_cpu(cmd->sleep_interval[2]),
1939                         le32_to_cpu(cmd->sleep_interval[3]),
1940                         le32_to_cpu(cmd->sleep_interval[4]));
1941
1942         return rc;
1943 }
1944
1945 static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
1946 {
1947         u32 uninitialized_var(final_mode);
1948         int rc;
1949         struct iwl3945_powertable_cmd cmd;
1950
1951         /* If on battery, set to 3,
1952          * if plugged into AC power, set to CAM ("continuously aware mode"),
1953          * else user level */
1954         switch (mode) {
1955         case IWL_POWER_BATTERY:
1956                 final_mode = IWL_POWER_INDEX_3;
1957                 break;
1958         case IWL_POWER_AC:
1959                 final_mode = IWL_POWER_MODE_CAM;
1960                 break;
1961         default:
1962                 final_mode = mode;
1963                 break;
1964         }
1965
1966         iwl3945_update_power_cmd(priv, &cmd, final_mode);
1967
1968         rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
1969
1970         if (final_mode == IWL_POWER_MODE_CAM)
1971                 clear_bit(STATUS_POWER_PMI, &priv->status);
1972         else
1973                 set_bit(STATUS_POWER_PMI, &priv->status);
1974
1975         return rc;
1976 }
1977
1978 /**
1979  * iwl3945_scan_cancel - Cancel any currently executing HW scan
1980  *
1981  * NOTE: priv->mutex is not required before calling this function
1982  */
1983 static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
1984 {
1985         if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
1986                 clear_bit(STATUS_SCANNING, &priv->status);
1987                 return 0;
1988         }
1989
1990         if (test_bit(STATUS_SCANNING, &priv->status)) {
1991                 if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
1992                         IWL_DEBUG_SCAN("Queuing scan abort.\n");
1993                         set_bit(STATUS_SCAN_ABORTING, &priv->status);
1994                         queue_work(priv->workqueue, &priv->abort_scan);
1995
1996                 } else
1997                         IWL_DEBUG_SCAN("Scan abort already in progress.\n");
1998
1999                 return test_bit(STATUS_SCANNING, &priv->status);
2000         }
2001
2002         return 0;
2003 }
2004
2005 /**
2006  * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
2007  * @ms: amount of time to wait (in milliseconds) for scan to abort
2008  *
2009  * NOTE: priv->mutex must be held before calling this function
2010  */
2011 static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
2012 {
2013         unsigned long now = jiffies;
2014         int ret;
2015
2016         ret = iwl3945_scan_cancel(priv);
2017         if (ret && ms) {
2018                 mutex_unlock(&priv->mutex);
2019                 while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
2020                                 test_bit(STATUS_SCANNING, &priv->status))
2021                         msleep(1);
2022                 mutex_lock(&priv->mutex);
2023
2024                 return test_bit(STATUS_SCANNING, &priv->status);
2025         }
2026
2027         return ret;
2028 }
2029
2030 #define MAX_UCODE_BEACON_INTERVAL       1024
2031 #define INTEL_CONN_LISTEN_INTERVAL      __constant_cpu_to_le16(0xA)
2032
2033 static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
2034 {
2035         u16 new_val = 0;
2036         u16 beacon_factor = 0;
2037
2038         beacon_factor =
2039             (beacon_val + MAX_UCODE_BEACON_INTERVAL)
2040                 / MAX_UCODE_BEACON_INTERVAL;
2041         new_val = beacon_val / beacon_factor;
2042
2043         return cpu_to_le16(new_val);
2044 }
2045
2046 static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
2047 {
2048         u64 interval_tm_unit;
2049         u64 tsf, result;
2050         unsigned long flags;
2051         struct ieee80211_conf *conf = NULL;
2052         u16 beacon_int = 0;
2053
2054         conf = ieee80211_get_hw_conf(priv->hw);
2055
2056         spin_lock_irqsave(&priv->lock, flags);
2057         priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
2058         priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
2059
2060         priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
2061
2062         tsf = priv->timestamp1;
2063         tsf = ((tsf << 32) | priv->timestamp0);
2064
2065         beacon_int = priv->beacon_int;
2066         spin_unlock_irqrestore(&priv->lock, flags);
2067
2068         if (priv->iw_mode == NL80211_IFTYPE_STATION) {
2069                 if (beacon_int == 0) {
2070                         priv->rxon_timing.beacon_interval = cpu_to_le16(100);
2071                         priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
2072                 } else {
2073                         priv->rxon_timing.beacon_interval =
2074                                 cpu_to_le16(beacon_int);
2075                         priv->rxon_timing.beacon_interval =
2076                             iwl3945_adjust_beacon_interval(
2077                                 le16_to_cpu(priv->rxon_timing.beacon_interval));
2078                 }
2079
2080                 priv->rxon_timing.atim_window = 0;
2081         } else {
2082                 priv->rxon_timing.beacon_interval =
2083                         iwl3945_adjust_beacon_interval(conf->beacon_int);
2084                 /* TODO: we need to get atim_window from upper stack
2085                  * for now we set to 0 */
2086                 priv->rxon_timing.atim_window = 0;
2087         }
2088
2089         interval_tm_unit =
2090                 (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
2091         result = do_div(tsf, interval_tm_unit);
2092         priv->rxon_timing.beacon_init_val =
2093             cpu_to_le32((u32) ((u64) interval_tm_unit - result));
2094
2095         IWL_DEBUG_ASSOC
2096             ("beacon interval %d beacon timer %d beacon tim %d\n",
2097                 le16_to_cpu(priv->rxon_timing.beacon_interval),
2098                 le32_to_cpu(priv->rxon_timing.beacon_init_val),
2099                 le16_to_cpu(priv->rxon_timing.atim_window));
2100 }
2101
2102 static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
2103 {
2104         if (priv->iw_mode == NL80211_IFTYPE_AP) {
2105                 IWL_ERROR("APs don't scan.\n");
2106                 return 0;
2107         }
2108
2109         if (!iwl3945_is_ready_rf(priv)) {
2110                 IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
2111                 return -EIO;
2112         }
2113
2114         if (test_bit(STATUS_SCANNING, &priv->status)) {
2115                 IWL_DEBUG_SCAN("Scan already in progress.\n");
2116                 return -EAGAIN;
2117         }
2118
2119         if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
2120                 IWL_DEBUG_SCAN("Scan request while abort pending.  "
2121                                "Queuing.\n");
2122                 return -EAGAIN;
2123         }
2124
2125         IWL_DEBUG_INFO("Starting scan...\n");
2126         if (priv->cfg->sku & IWL_SKU_G)
2127                 priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
2128         if (priv->cfg->sku & IWL_SKU_A)
2129                 priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
2130         set_bit(STATUS_SCANNING, &priv->status);
2131         priv->scan_start = jiffies;
2132         priv->scan_pass_start = priv->scan_start;
2133
2134         queue_work(priv->workqueue, &priv->request_scan);
2135
2136         return 0;
2137 }
2138
2139 static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
2140 {
2141         struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
2142
2143         if (hw_decrypt)
2144                 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
2145         else
2146                 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
2147
2148         return 0;
2149 }
2150
2151 static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
2152                                           enum ieee80211_band band)
2153 {
2154         if (band == IEEE80211_BAND_5GHZ) {
2155                 priv->staging_rxon.flags &=
2156                     ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
2157                       | RXON_FLG_CCK_MSK);
2158                 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2159         } else {
2160                 /* Copied from iwl3945_bg_post_associate() */
2161                 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2162                         priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2163                 else
2164                         priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2165
2166                 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
2167                         priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2168
2169                 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
2170                 priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
2171                 priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
2172         }
2173 }
2174
2175 /*
2176  * initialize rxon structure with default values from eeprom
2177  */
2178 static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv,
2179                                               int mode)
2180 {
2181         const struct iwl3945_channel_info *ch_info;
2182
2183         memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
2184
2185         switch (mode) {
2186         case NL80211_IFTYPE_AP:
2187                 priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
2188                 break;
2189
2190         case NL80211_IFTYPE_STATION:
2191                 priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
2192                 priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
2193                 break;
2194
2195         case NL80211_IFTYPE_ADHOC:
2196                 priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
2197                 priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
2198                 priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
2199                                                   RXON_FILTER_ACCEPT_GRP_MSK;
2200                 break;
2201
2202         case NL80211_IFTYPE_MONITOR:
2203                 priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
2204                 priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
2205                     RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
2206                 break;
2207         default:
2208                 IWL_ERROR("Unsupported interface type %d\n", mode);
2209                 break;
2210         }
2211
2212 #if 0
2213         /* TODO:  Figure out when short_preamble would be set and cache from
2214          * that */
2215         if (!hw_to_local(priv->hw)->short_preamble)
2216                 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2217         else
2218                 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2219 #endif
2220
2221         ch_info = iwl3945_get_channel_info(priv, priv->band,
2222                                        le16_to_cpu(priv->active_rxon.channel));
2223
2224         if (!ch_info)
2225                 ch_info = &priv->channel_info[0];
2226
2227         /*
2228          * in some case A channels are all non IBSS
2229          * in this case force B/G channel
2230          */
2231         if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
2232                 ch_info = &priv->channel_info[0];
2233
2234         priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
2235         if (is_channel_a_band(ch_info))
2236                 priv->band = IEEE80211_BAND_5GHZ;
2237         else
2238                 priv->band = IEEE80211_BAND_2GHZ;
2239
2240         iwl3945_set_flags_for_phymode(priv, priv->band);
2241
2242         priv->staging_rxon.ofdm_basic_rates =
2243             (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2244         priv->staging_rxon.cck_basic_rates =
2245             (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2246 }
2247
2248 static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
2249 {
2250         if (mode == NL80211_IFTYPE_ADHOC) {
2251                 const struct iwl3945_channel_info *ch_info;
2252
2253                 ch_info = iwl3945_get_channel_info(priv,
2254                         priv->band,
2255                         le16_to_cpu(priv->staging_rxon.channel));
2256
2257                 if (!ch_info || !is_channel_ibss(ch_info)) {
2258                         IWL_ERROR("channel %d not IBSS channel\n",
2259                                   le16_to_cpu(priv->staging_rxon.channel));
2260                         return -EINVAL;
2261                 }
2262         }
2263
2264         iwl3945_connection_init_rx_config(priv, mode);
2265         memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
2266
2267         iwl3945_clear_stations_table(priv);
2268
2269         /* don't commit rxon if rf-kill is on*/
2270         if (!iwl3945_is_ready_rf(priv))
2271                 return -EAGAIN;
2272
2273         cancel_delayed_work(&priv->scan_check);
2274         if (iwl3945_scan_cancel_timeout(priv, 100)) {
2275                 IWL_WARNING("Aborted scan still in progress after 100ms\n");
2276                 IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
2277                 return -EAGAIN;
2278         }
2279
2280         iwl3945_commit_rxon(priv);
2281
2282         return 0;
2283 }
2284
2285 static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
2286                                       struct ieee80211_tx_info *info,
2287                                       struct iwl3945_cmd *cmd,
2288                                       struct sk_buff *skb_frag,
2289                                       int last_frag)
2290 {
2291         struct iwl3945_hw_key *keyinfo =
2292             &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
2293
2294         switch (keyinfo->alg) {
2295         case ALG_CCMP:
2296                 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
2297                 memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
2298                 IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
2299                 break;
2300
2301         case ALG_TKIP:
2302 #if 0
2303                 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
2304
2305                 if (last_frag)
2306                         memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
2307                                8);
2308                 else
2309                         memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
2310 #endif
2311                 break;
2312
2313         case ALG_WEP:
2314                 cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
2315                     (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
2316
2317                 if (keyinfo->keylen == 13)
2318                         cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
2319
2320                 memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
2321
2322                 IWL_DEBUG_TX("Configuring packet for WEP encryption "
2323                              "with key %d\n", info->control.hw_key->hw_key_idx);
2324                 break;
2325
2326         default:
2327                 printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
2328                 break;
2329         }
2330 }
2331
2332 /*
2333  * handle build REPLY_TX command notification.
2334  */
2335 static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
2336                                   struct iwl3945_cmd *cmd,
2337                                   struct ieee80211_tx_info *info,
2338                                   struct ieee80211_hdr *hdr,
2339                                   int is_unicast, u8 std_id)
2340 {
2341         __le16 fc = hdr->frame_control;
2342         __le32 tx_flags = cmd->cmd.tx.tx_flags;
2343         u8 rc_flags = info->control.rates[0].flags;
2344
2345         cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2346         if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
2347                 tx_flags |= TX_CMD_FLG_ACK_MSK;
2348                 if (ieee80211_is_mgmt(fc))
2349                         tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2350                 if (ieee80211_is_probe_resp(fc) &&
2351                     !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
2352                         tx_flags |= TX_CMD_FLG_TSF_MSK;
2353         } else {
2354                 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
2355                 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2356         }
2357
2358         cmd->cmd.tx.sta_id = std_id;
2359         if (ieee80211_has_morefrags(fc))
2360                 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
2361
2362         if (ieee80211_is_data_qos(fc)) {
2363                 u8 *qc = ieee80211_get_qos_ctl(hdr);
2364                 cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
2365                 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
2366         } else {
2367                 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
2368         }
2369
2370         if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
2371                 tx_flags |= TX_CMD_FLG_RTS_MSK;
2372                 tx_flags &= ~TX_CMD_FLG_CTS_MSK;
2373         } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
2374                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2375                 tx_flags |= TX_CMD_FLG_CTS_MSK;
2376         }
2377
2378         if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
2379                 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
2380
2381         tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
2382         if (ieee80211_is_mgmt(fc)) {
2383                 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
2384                         cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
2385                 else
2386                         cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
2387         } else {
2388                 cmd->cmd.tx.timeout.pm_frame_timeout = 0;
2389 #ifdef CONFIG_IWL3945_LEDS
2390                 priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
2391 #endif
2392         }
2393
2394         cmd->cmd.tx.driver_txop = 0;
2395         cmd->cmd.tx.tx_flags = tx_flags;
2396         cmd->cmd.tx.next_frame_len = 0;
2397 }
2398
2399 /**
2400  * iwl3945_get_sta_id - Find station's index within station table
2401  */
2402 static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
2403 {
2404         int sta_id;
2405         u16 fc = le16_to_cpu(hdr->frame_control);
2406
2407         /* If this frame is broadcast or management, use broadcast station id */
2408         if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
2409             is_multicast_ether_addr(hdr->addr1))
2410                 return priv->hw_setting.bcast_sta_id;
2411
2412         switch (priv->iw_mode) {
2413
2414         /* If we are a client station in a BSS network, use the special
2415          * AP station entry (that's the only station we communicate with) */
2416         case NL80211_IFTYPE_STATION:
2417                 return IWL_AP_ID;
2418
2419         /* If we are an AP, then find the station, or use BCAST */
2420         case NL80211_IFTYPE_AP:
2421                 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
2422                 if (sta_id != IWL_INVALID_STATION)
2423                         return sta_id;
2424                 return priv->hw_setting.bcast_sta_id;
2425
2426         /* If this frame is going out to an IBSS network, find the station,
2427          * or create a new station table entry */
2428         case NL80211_IFTYPE_ADHOC: {
2429                 /* Create new station table entry */
2430                 sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
2431                 if (sta_id != IWL_INVALID_STATION)
2432                         return sta_id;
2433
2434                 sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
2435
2436                 if (sta_id != IWL_INVALID_STATION)
2437                         return sta_id;
2438
2439                 IWL_DEBUG_DROP("Station %pM not in station map. "
2440                                "Defaulting to broadcast...\n",
2441                                hdr->addr1);
2442                 iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
2443                 return priv->hw_setting.bcast_sta_id;
2444         }
2445         /* If we are in monitor mode, use BCAST. This is required for
2446          * packet injection. */
2447         case NL80211_IFTYPE_MONITOR:
2448                 return priv->hw_setting.bcast_sta_id;
2449
2450         default:
2451                 IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode);
2452                 return priv->hw_setting.bcast_sta_id;
2453         }
2454 }
2455
2456 /*
2457  * start REPLY_TX command process
2458  */
2459 static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
2460 {
2461         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2462         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2463         struct iwl3945_tfd_frame *tfd;
2464         u32 *control_flags;
2465         int txq_id = skb_get_queue_mapping(skb);
2466         struct iwl3945_tx_queue *txq = NULL;
2467         struct iwl3945_queue *q = NULL;
2468         dma_addr_t phys_addr;
2469         dma_addr_t txcmd_phys;
2470         struct iwl3945_cmd *out_cmd = NULL;
2471         u16 len, idx, len_org, hdr_len;
2472         u8 id;
2473         u8 unicast;
2474         u8 sta_id;
2475         u8 tid = 0;
2476         u16 seq_number = 0;
2477         __le16 fc;
2478         u8 wait_write_ptr = 0;
2479         u8 *qc = NULL;
2480         unsigned long flags;
2481         int rc;
2482
2483         spin_lock_irqsave(&priv->lock, flags);
2484         if (iwl3945_is_rfkill(priv)) {
2485                 IWL_DEBUG_DROP("Dropping - RF KILL\n");
2486                 goto drop_unlock;
2487         }
2488
2489         if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
2490                 IWL_ERROR("ERROR: No TX rate available.\n");
2491                 goto drop_unlock;
2492         }
2493
2494         unicast = !is_multicast_ether_addr(hdr->addr1);
2495         id = 0;
2496
2497         fc = hdr->frame_control;
2498
2499 #ifdef CONFIG_IWL3945_DEBUG
2500         if (ieee80211_is_auth(fc))
2501                 IWL_DEBUG_TX("Sending AUTH frame\n");
2502         else if (ieee80211_is_assoc_req(fc))
2503                 IWL_DEBUG_TX("Sending ASSOC frame\n");
2504         else if (ieee80211_is_reassoc_req(fc))
2505                 IWL_DEBUG_TX("Sending REASSOC frame\n");
2506 #endif
2507
2508         /* drop all data frame if we are not associated */
2509         if (ieee80211_is_data(fc) &&
2510             (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
2511             (!iwl3945_is_associated(priv) ||
2512              ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
2513                 IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
2514                 goto drop_unlock;
2515         }
2516
2517         spin_unlock_irqrestore(&priv->lock, flags);
2518
2519         hdr_len = ieee80211_hdrlen(fc);
2520
2521         /* Find (or create) index into station table for destination station */
2522         sta_id = iwl3945_get_sta_id(priv, hdr);
2523         if (sta_id == IWL_INVALID_STATION) {
2524                 IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
2525                                hdr->addr1);
2526                 goto drop;
2527         }
2528
2529         IWL_DEBUG_RATE("station Id %d\n", sta_id);
2530
2531         if (ieee80211_is_data_qos(fc)) {
2532                 qc = ieee80211_get_qos_ctl(hdr);
2533                 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
2534                 seq_number = priv->stations[sta_id].tid[tid].seq_number &
2535                                 IEEE80211_SCTL_SEQ;
2536                 hdr->seq_ctrl = cpu_to_le16(seq_number) |
2537                         (hdr->seq_ctrl &
2538                                 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
2539                 seq_number += 0x10;
2540         }
2541
2542         /* Descriptor for chosen Tx queue */
2543         txq = &priv->txq[txq_id];
2544         q = &txq->q;
2545
2546         spin_lock_irqsave(&priv->lock, flags);
2547
2548         /* Set up first empty TFD within this queue's circular TFD buffer */
2549         tfd = &txq->bd[q->write_ptr];
2550         memset(tfd, 0, sizeof(*tfd));
2551         control_flags = (u32 *) tfd;
2552         idx = get_cmd_index(q, q->write_ptr, 0);
2553
2554         /* Set up driver data for this TFD */
2555         memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
2556         txq->txb[q->write_ptr].skb[0] = skb;
2557
2558         /* Init first empty entry in queue's array of Tx/cmd buffers */
2559         out_cmd = &txq->cmd[idx];
2560         memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
2561         memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
2562
2563         /*
2564          * Set up the Tx-command (not MAC!) header.
2565          * Store the chosen Tx queue and TFD index within the sequence field;
2566          * after Tx, uCode's Tx response will return this value so driver can
2567          * locate the frame within the tx queue and do post-tx processing.
2568          */
2569         out_cmd->hdr.cmd = REPLY_TX;
2570         out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2571                                 INDEX_TO_SEQ(q->write_ptr)));
2572
2573         /* Copy MAC header from skb into command buffer */
2574         memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
2575
2576         /*
2577          * Use the first empty entry in this queue's command buffer array
2578          * to contain the Tx command and MAC header concatenated together
2579          * (payload data will be in another buffer).
2580          * Size of this varies, due to varying MAC header length.
2581          * If end is not dword aligned, we'll have 2 extra bytes at the end
2582          * of the MAC header (device reads on dword boundaries).
2583          * We'll tell device about this padding later.
2584          */
2585         len = priv->hw_setting.tx_cmd_len +
2586                 sizeof(struct iwl3945_cmd_header) + hdr_len;
2587
2588         len_org = len;
2589         len = (len + 3) & ~3;
2590
2591         if (len_org != len)
2592                 len_org = 1;
2593         else
2594                 len_org = 0;
2595
2596         /* Physical address of this Tx command's header (not MAC header!),
2597          * within command buffer array. */
2598         txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
2599                      offsetof(struct iwl3945_cmd, hdr);
2600
2601         /* Add buffer containing Tx command and MAC(!) header to TFD's
2602          * first entry */
2603         iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
2604
2605         if (info->control.hw_key)
2606                 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
2607
2608         /* Set up TFD's 2nd entry to point directly to remainder of skb,
2609          * if any (802.11 null frames have no payload). */
2610         len = skb->len - hdr_len;
2611         if (len) {
2612                 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
2613                                            len, PCI_DMA_TODEVICE);
2614                 iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
2615         }
2616
2617         if (!len)
2618                 /* If there is no payload, then we use only one Tx buffer */
2619                 *control_flags = TFD_CTL_COUNT_SET(1);
2620         else
2621                 /* Else use 2 buffers.
2622                  * Tell 3945 about any padding after MAC header */
2623                 *control_flags = TFD_CTL_COUNT_SET(2) |
2624                         TFD_CTL_PAD_SET(U32_PAD(len));
2625
2626         /* Total # bytes to be transmitted */
2627         len = (u16)skb->len;
2628         out_cmd->cmd.tx.len = cpu_to_le16(len);
2629
2630         /* TODO need this for burst mode later on */
2631         iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
2632
2633         /* set is_hcca to 0; it probably will never be implemented */
2634         iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
2635
2636         out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
2637         out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
2638
2639         if (!ieee80211_has_morefrags(hdr->frame_control)) {
2640                 txq->need_update = 1;
2641                 if (qc)
2642                         priv->stations[sta_id].tid[tid].seq_number = seq_number;
2643         } else {
2644                 wait_write_ptr = 1;
2645                 txq->need_update = 0;
2646         }
2647
2648         iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
2649                            sizeof(out_cmd->cmd.tx));
2650
2651         iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
2652                            ieee80211_hdrlen(fc));
2653
2654         /* Tell device the write index *just past* this latest filled TFD */
2655         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
2656         rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
2657         spin_unlock_irqrestore(&priv->lock, flags);
2658
2659         if (rc)
2660                 return rc;
2661
2662         if ((iwl3945_queue_space(q) < q->high_mark)
2663             && priv->mac80211_registered) {
2664                 if (wait_write_ptr) {
2665                         spin_lock_irqsave(&priv->lock, flags);
2666                         txq->need_update = 1;
2667                         iwl3945_tx_queue_update_write_ptr(priv, txq);
2668                         spin_unlock_irqrestore(&priv->lock, flags);
2669                 }
2670
2671                 ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
2672         }
2673
2674         return 0;
2675
2676 drop_unlock:
2677         spin_unlock_irqrestore(&priv->lock, flags);
2678 drop:
2679         return -1;
2680 }
2681
2682 static void iwl3945_set_rate(struct iwl3945_priv *priv)
2683 {
2684         const struct ieee80211_supported_band *sband = NULL;
2685         struct ieee80211_rate *rate;
2686         int i;
2687
2688         sband = iwl3945_get_band(priv, priv->band);
2689         if (!sband) {
2690                 IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2691                 return;
2692         }
2693
2694         priv->active_rate = 0;
2695         priv->active_rate_basic = 0;
2696
2697         IWL_DEBUG_RATE("Setting rates for %s GHz\n",
2698                        sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
2699
2700         for (i = 0; i < sband->n_bitrates; i++) {
2701                 rate = &sband->bitrates[i];
2702                 if ((rate->hw_value < IWL_RATE_COUNT) &&
2703                     !(rate->flags & IEEE80211_CHAN_DISABLED)) {
2704                         IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
2705                                        rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
2706                         priv->active_rate |= (1 << rate->hw_value);
2707                 }
2708         }
2709
2710         IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
2711                        priv->active_rate, priv->active_rate_basic);
2712
2713         /*
2714          * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
2715          * otherwise set it to the default of all CCK rates and 6, 12, 24 for
2716          * OFDM
2717          */
2718         if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
2719                 priv->staging_rxon.cck_basic_rates =
2720                     ((priv->active_rate_basic &
2721                       IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
2722         else
2723                 priv->staging_rxon.cck_basic_rates =
2724                     (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
2725
2726         if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
2727                 priv->staging_rxon.ofdm_basic_rates =
2728                     ((priv->active_rate_basic &
2729                       (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
2730                       IWL_FIRST_OFDM_RATE) & 0xFF;
2731         else
2732                 priv->staging_rxon.ofdm_basic_rates =
2733                    (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2734 }
2735
2736 static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
2737 {
2738         unsigned long flags;
2739
2740         if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
2741                 return;
2742
2743         IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
2744                           disable_radio ? "OFF" : "ON");
2745
2746         if (disable_radio) {
2747                 iwl3945_scan_cancel(priv);
2748                 /* FIXME: This is a workaround for AP */
2749                 if (priv->iw_mode != NL80211_IFTYPE_AP) {
2750                         spin_lock_irqsave(&priv->lock, flags);
2751                         iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
2752                                     CSR_UCODE_SW_BIT_RFKILL);
2753                         spin_unlock_irqrestore(&priv->lock, flags);
2754                         iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
2755                         set_bit(STATUS_RF_KILL_SW, &priv->status);
2756                 }
2757                 return;
2758         }
2759
2760         spin_lock_irqsave(&priv->lock, flags);
2761         iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2762
2763         clear_bit(STATUS_RF_KILL_SW, &priv->status);
2764         spin_unlock_irqrestore(&priv->lock, flags);
2765
2766         /* wake up ucode */
2767         msleep(10);
2768
2769         spin_lock_irqsave(&priv->lock, flags);
2770         iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
2771         if (!iwl3945_grab_nic_access(priv))
2772                 iwl3945_release_nic_access(priv);
2773         spin_unlock_irqrestore(&priv->lock, flags);
2774
2775         if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2776                 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
2777                                   "disabled by HW switch\n");
2778                 return;
2779         }
2780
2781         if (priv->is_open)
2782                 queue_work(priv->workqueue, &priv->restart);
2783         return;
2784 }
2785
2786 void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
2787                             u32 decrypt_res, struct ieee80211_rx_status *stats)
2788 {
2789         u16 fc =
2790             le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
2791
2792         if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2793                 return;
2794
2795         if (!(fc & IEEE80211_FCTL_PROTECTED))
2796                 return;
2797
2798         IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2799         switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2800         case RX_RES_STATUS_SEC_TYPE_TKIP:
2801                 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2802                     RX_RES_STATUS_BAD_ICV_MIC)
2803                         stats->flag |= RX_FLAG_MMIC_ERROR;
2804         case RX_RES_STATUS_SEC_TYPE_WEP:
2805         case RX_RES_STATUS_SEC_TYPE_CCMP:
2806                 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2807                     RX_RES_STATUS_DECRYPT_OK) {
2808                         IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2809                         stats->flag |= RX_FLAG_DECRYPTED;
2810                 }
2811                 break;
2812
2813         default:
2814                 break;
2815         }
2816 }
2817
2818 #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
2819
2820 #include "iwl-spectrum.h"
2821
2822 #define BEACON_TIME_MASK_LOW    0x00FFFFFF
2823 #define BEACON_TIME_MASK_HIGH   0xFF000000
2824 #define TIME_UNIT               1024
2825
2826 /*
2827  * extended beacon time format
2828  * time in usec will be changed into a 32-bit value in 8:24 format
2829  * the high 1 byte is the beacon counts
2830  * the lower 3 bytes is the time in usec within one beacon interval
2831  */
2832
2833 static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
2834 {
2835         u32 quot;
2836         u32 rem;
2837         u32 interval = beacon_interval * 1024;
2838
2839         if (!interval || !usec)
2840                 return 0;
2841
2842         quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
2843         rem = (usec % interval) & BEACON_TIME_MASK_LOW;
2844
2845         return (quot << 24) + rem;
2846 }
2847
2848 /* base is usually what we get from ucode with each received frame,
2849  * the same as HW timer counter counting down
2850  */
2851
2852 static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
2853 {
2854         u32 base_low = base & BEACON_TIME_MASK_LOW;
2855         u32 addon_low = addon & BEACON_TIME_MASK_LOW;
2856         u32 interval = beacon_interval * TIME_UNIT;
2857         u32 res = (base & BEACON_TIME_MASK_HIGH) +
2858             (addon & BEACON_TIME_MASK_HIGH);
2859
2860         if (base_low > addon_low)
2861                 res += base_low - addon_low;
2862         else if (base_low < addon_low) {
2863                 res += interval + base_low - addon_low;
2864                 res += (1 << 24);
2865         } else
2866                 res += (1 << 24);
2867
2868         return cpu_to_le32(res);
2869 }
2870
2871 static int iwl3945_get_measurement(struct iwl3945_priv *priv,
2872                                struct ieee80211_measurement_params *params,
2873                                u8 type)
2874 {
2875         struct iwl3945_spectrum_cmd spectrum;
2876         struct iwl3945_rx_packet *res;
2877         struct iwl3945_host_cmd cmd = {
2878                 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
2879                 .data = (void *)&spectrum,
2880                 .meta.flags = CMD_WANT_SKB,
2881         };
2882         u32 add_time = le64_to_cpu(params->start_time);
2883         int rc;
2884         int spectrum_resp_status;
2885         int duration = le16_to_cpu(params->duration);
2886
2887         if (iwl3945_is_associated(priv))
2888                 add_time =
2889                     iwl3945_usecs_to_beacons(
2890                         le64_to_cpu(params->start_time) - priv->last_tsf,
2891                         le16_to_cpu(priv->rxon_timing.beacon_interval));
2892
2893         memset(&spectrum, 0, sizeof(spectrum));
2894
2895         spectrum.channel_count = cpu_to_le16(1);
2896         spectrum.flags =
2897             RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
2898         spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
2899         cmd.len = sizeof(spectrum);
2900         spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
2901
2902         if (iwl3945_is_associated(priv))
2903                 spectrum.start_time =
2904                     iwl3945_add_beacon_time(priv->last_beacon_time,
2905                                 add_time,
2906                                 le16_to_cpu(priv->rxon_timing.beacon_interval));
2907         else
2908                 spectrum.start_time = 0;
2909
2910         spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
2911         spectrum.channels[0].channel = params->channel;
2912         spectrum.channels[0].type = type;
2913         if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
2914                 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
2915                     RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
2916
2917         rc = iwl3945_send_cmd_sync(priv, &cmd);
2918         if (rc)
2919                 return rc;
2920
2921         res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
2922         if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
2923                 IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
2924                 rc = -EIO;
2925         }
2926
2927         spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
2928         switch (spectrum_resp_status) {
2929         case 0:         /* Command will be handled */
2930                 if (res->u.spectrum.id != 0xff) {
2931                         IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
2932                                                 res->u.spectrum.id);
2933                         priv->measurement_status &= ~MEASUREMENT_READY;
2934                 }
2935                 priv->measurement_status |= MEASUREMENT_ACTIVE;
2936                 rc = 0;
2937                 break;
2938
2939         case 1:         /* Command will not be handled */
2940                 rc = -EAGAIN;
2941                 break;
2942         }
2943
2944         dev_kfree_skb_any(cmd.meta.u.skb);
2945
2946         return rc;
2947 }
2948 #endif
2949
2950 static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
2951                                struct iwl3945_rx_mem_buffer *rxb)
2952 {
2953         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
2954         struct iwl3945_alive_resp *palive;
2955         struct delayed_work *pwork;
2956
2957         palive = &pkt->u.alive_frame;
2958
2959         IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
2960                        "0x%01X 0x%01X\n",
2961                        palive->is_valid, palive->ver_type,
2962                        palive->ver_subtype);
2963
2964         if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
2965                 IWL_DEBUG_INFO("Initialization Alive received.\n");
2966                 memcpy(&priv->card_alive_init,
2967                        &pkt->u.alive_frame,
2968                        sizeof(struct iwl3945_init_alive_resp));
2969                 pwork = &priv->init_alive_start;
2970         } else {
2971                 IWL_DEBUG_INFO("Runtime Alive received.\n");
2972                 memcpy(&priv->card_alive, &pkt->u.alive_frame,
2973                        sizeof(struct iwl3945_alive_resp));
2974                 pwork = &priv->alive_start;
2975                 iwl3945_disable_events(priv);
2976         }
2977
2978         /* We delay the ALIVE response by 5ms to
2979          * give the HW RF Kill time to activate... */
2980         if (palive->is_valid == UCODE_VALID_OK)
2981                 queue_delayed_work(priv->workqueue, pwork,
2982                                    msecs_to_jiffies(5));
2983         else
2984                 IWL_WARNING("uCode did not respond OK.\n");
2985 }
2986
2987 static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
2988                                  struct iwl3945_rx_mem_buffer *rxb)
2989 {
2990         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
2991
2992         IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
2993         return;
2994 }
2995
2996 static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
2997                                struct iwl3945_rx_mem_buffer *rxb)
2998 {
2999         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3000
3001         IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
3002                 "seq 0x%04X ser 0x%08X\n",
3003                 le32_to_cpu(pkt->u.err_resp.error_type),
3004                 get_cmd_string(pkt->u.err_resp.cmd_id),
3005                 pkt->u.err_resp.cmd_id,
3006                 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
3007                 le32_to_cpu(pkt->u.err_resp.error_info));
3008 }
3009
3010 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
3011
3012 static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
3013 {
3014         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3015         struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
3016         struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
3017         IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
3018                       le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
3019         rxon->channel = csa->channel;
3020         priv->staging_rxon.channel = csa->channel;
3021 }
3022
3023 static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
3024                                           struct iwl3945_rx_mem_buffer *rxb)
3025 {
3026 #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
3027         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3028         struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
3029
3030         if (!report->state) {
3031                 IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
3032                           "Spectrum Measure Notification: Start\n");
3033                 return;
3034         }
3035
3036         memcpy(&priv->measure_report, report, sizeof(*report));
3037         priv->measurement_status |= MEASUREMENT_READY;
3038 #endif
3039 }
3040
3041 static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
3042                                   struct iwl3945_rx_mem_buffer *rxb)
3043 {
3044 #ifdef CONFIG_IWL3945_DEBUG
3045         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3046         struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
3047         IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
3048                      sleep->pm_sleep_mode, sleep->pm_wakeup_src);
3049 #endif
3050 }
3051
3052 static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
3053                                              struct iwl3945_rx_mem_buffer *rxb)
3054 {
3055         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3056         IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
3057                         "notification for %s:\n",
3058                         le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
3059         iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
3060 }
3061
3062 static void iwl3945_bg_beacon_update(struct work_struct *work)
3063 {
3064         struct iwl3945_priv *priv =
3065                 container_of(work, struct iwl3945_priv, beacon_update);
3066         struct sk_buff *beacon;
3067
3068         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
3069         beacon = ieee80211_beacon_get(priv->hw, priv->vif);
3070
3071         if (!beacon) {
3072                 IWL_ERROR("update beacon failed\n");
3073                 return;
3074         }
3075
3076         mutex_lock(&priv->mutex);
3077         /* new beacon skb is allocated every time; dispose previous.*/
3078         if (priv->ibss_beacon)
3079                 dev_kfree_skb(priv->ibss_beacon);
3080
3081         priv->ibss_beacon = beacon;
3082         mutex_unlock(&priv->mutex);
3083
3084         iwl3945_send_beacon_cmd(priv);
3085 }
3086
3087 static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
3088                                 struct iwl3945_rx_mem_buffer *rxb)
3089 {
3090 #ifdef CONFIG_IWL3945_DEBUG
3091         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3092         struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
3093         u8 rate = beacon->beacon_notify_hdr.rate;
3094
3095         IWL_DEBUG_RX("beacon status %x retries %d iss %d "
3096                 "tsf %d %d rate %d\n",
3097                 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
3098                 beacon->beacon_notify_hdr.failure_frame,
3099                 le32_to_cpu(beacon->ibss_mgr_status),
3100                 le32_to_cpu(beacon->high_tsf),
3101                 le32_to_cpu(beacon->low_tsf), rate);
3102 #endif
3103
3104         if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
3105             (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
3106                 queue_work(priv->workqueue, &priv->beacon_update);
3107 }
3108
3109 /* Service response to REPLY_SCAN_CMD (0x80) */
3110 static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
3111                               struct iwl3945_rx_mem_buffer *rxb)
3112 {
3113 #ifdef CONFIG_IWL3945_DEBUG
3114         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3115         struct iwl3945_scanreq_notification *notif =
3116             (struct iwl3945_scanreq_notification *)pkt->u.raw;
3117
3118         IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
3119 #endif
3120 }
3121
3122 /* Service SCAN_START_NOTIFICATION (0x82) */
3123 static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
3124                                     struct iwl3945_rx_mem_buffer *rxb)
3125 {
3126         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3127         struct iwl3945_scanstart_notification *notif =
3128             (struct iwl3945_scanstart_notification *)pkt->u.raw;
3129         priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
3130         IWL_DEBUG_SCAN("Scan start: "
3131                        "%d [802.11%s] "
3132                        "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
3133                        notif->channel,
3134                        notif->band ? "bg" : "a",
3135                        notif->tsf_high,
3136                        notif->tsf_low, notif->status, notif->beacon_timer);
3137 }
3138
3139 /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
3140 static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
3141                                       struct iwl3945_rx_mem_buffer *rxb)
3142 {
3143         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3144         struct iwl3945_scanresults_notification *notif =
3145             (struct iwl3945_scanresults_notification *)pkt->u.raw;
3146
3147         IWL_DEBUG_SCAN("Scan ch.res: "
3148                        "%d [802.11%s] "
3149                        "(TSF: 0x%08X:%08X) - %d "
3150                        "elapsed=%lu usec (%dms since last)\n",
3151                        notif->channel,
3152                        notif->band ? "bg" : "a",
3153                        le32_to_cpu(notif->tsf_high),
3154                        le32_to_cpu(notif->tsf_low),
3155                        le32_to_cpu(notif->statistics[0]),
3156                        le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
3157                        jiffies_to_msecs(elapsed_jiffies
3158                                         (priv->last_scan_jiffies, jiffies)));
3159
3160         priv->last_scan_jiffies = jiffies;
3161         priv->next_scan_jiffies = 0;
3162 }
3163
3164 /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
3165 static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
3166                                        struct iwl3945_rx_mem_buffer *rxb)
3167 {
3168         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3169         struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
3170
3171         IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
3172                        scan_notif->scanned_channels,
3173                        scan_notif->tsf_low,
3174                        scan_notif->tsf_high, scan_notif->status);
3175
3176         /* The HW is no longer scanning */
3177         clear_bit(STATUS_SCAN_HW, &priv->status);
3178
3179         /* The scan completion notification came in, so kill that timer... */
3180         cancel_delayed_work(&priv->scan_check);
3181
3182         IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
3183                        (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
3184                                                         "2.4" : "5.2",
3185                        jiffies_to_msecs(elapsed_jiffies
3186                                         (priv->scan_pass_start, jiffies)));
3187
3188         /* Remove this scanned band from the list of pending
3189          * bands to scan, band G precedes A in order of scanning
3190          * as seen in iwl3945_bg_request_scan */
3191         if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
3192                 priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
3193         else if (priv->scan_bands &  BIT(IEEE80211_BAND_5GHZ))
3194                 priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
3195
3196         /* If a request to abort was given, or the scan did not succeed
3197          * then we reset the scan state machine and terminate,
3198          * re-queuing another scan if one has been requested */
3199         if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
3200                 IWL_DEBUG_INFO("Aborted scan completed.\n");
3201                 clear_bit(STATUS_SCAN_ABORTING, &priv->status);
3202         } else {
3203                 /* If there are more bands on this scan pass reschedule */
3204                 if (priv->scan_bands > 0)
3205                         goto reschedule;
3206         }
3207
3208         priv->last_scan_jiffies = jiffies;
3209         priv->next_scan_jiffies = 0;
3210         IWL_DEBUG_INFO("Setting scan to off\n");
3211
3212         clear_bit(STATUS_SCANNING, &priv->status);
3213
3214         IWL_DEBUG_INFO("Scan took %dms\n",
3215                 jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
3216
3217         queue_work(priv->workqueue, &priv->scan_completed);
3218
3219         return;
3220
3221 reschedule:
3222         priv->scan_pass_start = jiffies;
3223         queue_work(priv->workqueue, &priv->request_scan);
3224 }
3225
3226 /* Handle notification from uCode that card's power state is changing
3227  * due to software, hardware, or critical temperature RFKILL */
3228 static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
3229                                     struct iwl3945_rx_mem_buffer *rxb)
3230 {
3231         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
3232         u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3233         unsigned long status = priv->status;
3234
3235         IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
3236                           (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3237                           (flags & SW_CARD_DISABLED) ? "Kill" : "On");
3238
3239         iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
3240                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3241
3242         if (flags & HW_CARD_DISABLED)
3243                 set_bit(STATUS_RF_KILL_HW, &priv->status);
3244         else
3245                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3246
3247
3248         if (flags & SW_CARD_DISABLED)
3249                 set_bit(STATUS_RF_KILL_SW, &priv->status);
3250         else
3251                 clear_bit(STATUS_RF_KILL_SW, &priv->status);
3252
3253         iwl3945_scan_cancel(priv);
3254
3255         if ((test_bit(STATUS_RF_KILL_HW, &status) !=
3256              test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
3257             (test_bit(STATUS_RF_KILL_SW, &status) !=
3258              test_bit(STATUS_RF_KILL_SW, &priv->status)))
3259                 queue_work(priv->workqueue, &priv->rf_kill);
3260         else
3261                 wake_up_interruptible(&priv->wait_command_queue);
3262 }
3263
3264 /**
3265  * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
3266  *
3267  * Setup the RX handlers for each of the reply types sent from the uCode
3268  * to the host.
3269  *
3270  * This function chains into the hardware specific files for them to setup
3271  * any hardware specific handlers as well.
3272  */
3273 static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
3274 {
3275         priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
3276         priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
3277         priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
3278         priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
3279         priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
3280             iwl3945_rx_spectrum_measure_notif;
3281         priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
3282         priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
3283             iwl3945_rx_pm_debug_statistics_notif;
3284         priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
3285
3286         /*
3287          * The same handler is used for both the REPLY to a discrete
3288          * statistics request from the host as well as for the periodic
3289          * statistics notifications (after received beacons) from the uCode.
3290          */
3291         priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
3292         priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
3293
3294         priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
3295         priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
3296         priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
3297             iwl3945_rx_scan_results_notif;
3298         priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
3299             iwl3945_rx_scan_complete_notif;
3300         priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
3301
3302         /* Set up hardware specific Rx handlers */
3303         iwl3945_hw_rx_handler_setup(priv);
3304 }
3305
3306 /**
3307  * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
3308  * When FW advances 'R' index, all entries between old and new 'R' index
3309  * need to be reclaimed.
3310  */
3311 static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
3312                                       int txq_id, int index)
3313 {
3314         struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
3315         struct iwl3945_queue *q = &txq->q;
3316         int nfreed = 0;
3317
3318         if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
3319                 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
3320                           "is out of range [0-%d] %d %d.\n", txq_id,
3321                           index, q->n_bd, q->write_ptr, q->read_ptr);
3322                 return;
3323         }
3324
3325         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
3326                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3327                 if (nfreed > 1) {
3328                         IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
3329                                         q->write_ptr, q->read_ptr);
3330                         queue_work(priv->workqueue, &priv->restart);
3331                         break;
3332                 }
3333                 nfreed++;
3334         }
3335 }
3336
3337
3338 /**
3339  * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
3340  * @rxb: Rx buffer to reclaim
3341  *
3342  * If an Rx buffer has an async callback associated with it the callback
3343  * will be executed.  The attached skb (if present) will only be freed
3344  * if the callback returns 1
3345  */
3346 static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
3347                                 struct iwl3945_rx_mem_buffer *rxb)
3348 {
3349         struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
3350         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3351         int txq_id = SEQ_TO_QUEUE(sequence);
3352         int index = SEQ_TO_INDEX(sequence);
3353         int huge = sequence & SEQ_HUGE_FRAME;
3354         int cmd_index;
3355         struct iwl3945_cmd *cmd;
3356
3357         BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
3358
3359         cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
3360         cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
3361
3362         /* Input error checking is done when commands are added to queue. */
3363         if (cmd->meta.flags & CMD_WANT_SKB) {
3364                 cmd->meta.source->u.skb = rxb->skb;
3365                 rxb->skb = NULL;
3366         } else if (cmd->meta.u.callback &&
3367                    !cmd->meta.u.callback(priv, cmd, rxb->skb))
3368                 rxb->skb = NULL;
3369
3370         iwl3945_cmd_queue_reclaim(priv, txq_id, index);
3371
3372         if (!(cmd->meta.flags & CMD_ASYNC)) {
3373                 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
3374                 wake_up_interruptible(&priv->wait_command_queue);
3375         }
3376 }
3377
3378 /************************** RX-FUNCTIONS ****************************/
3379 /*
3380  * Rx theory of operation
3381  *
3382  * The host allocates 32 DMA target addresses and passes the host address
3383  * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
3384  * 0 to 31
3385  *
3386  * Rx Queue Indexes
3387  * The host/firmware share two index registers for managing the Rx buffers.
3388  *
3389  * The READ index maps to the first position that the firmware may be writing
3390  * to -- the driver can read up to (but not including) this position and get
3391  * good data.
3392  * The READ index is managed by the firmware once the card is enabled.
3393  *
3394  * The WRITE index maps to the last position the driver has read from -- the
3395  * position preceding WRITE is the last slot the firmware can place a packet.
3396  *
3397  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
3398  * WRITE = READ.
3399  *
3400  * During initialization, the host sets up the READ queue position to the first
3401  * INDEX position, and WRITE to the last (READ - 1 wrapped)
3402  *
3403  * When the firmware places a packet in a buffer, it will advance the READ index
3404  * and fire the RX interrupt.  The driver can then query the READ index and
3405  * process as many packets as possible, moving the WRITE index forward as it
3406  * resets the Rx queue buffers with new memory.
3407  *
3408  * The management in the driver is as follows:
3409  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
3410  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
3411  *   to replenish the iwl->rxq->rx_free.
3412  * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
3413  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
3414  *   'processed' and 'read' driver indexes as well)
3415  * + A received packet is processed and handed to the kernel network stack,
3416  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
3417  * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
3418  *   list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
3419  *   INDEX is not incremented and iwl->status(RX_STALLED) is set.  If there
3420  *   were enough free buffers and RX_STALLED is set it is cleared.
3421  *
3422  *
3423  * Driver sequence:
3424  *
3425  * iwl3945_rx_queue_alloc()   Allocates rx_free
3426  * iwl3945_rx_replenish()     Replenishes rx_free list from rx_used, and calls
3427  *                            iwl3945_rx_queue_restock
3428  * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
3429  *                            queue, updates firmware pointers, and updates
3430  *                            the WRITE index.  If insufficient rx_free buffers
3431  *                            are available, schedules iwl3945_rx_replenish
3432  *
3433  * -- enable interrupts --
3434  * ISR - iwl3945_rx()         Detach iwl3945_rx_mem_buffers from pool up to the
3435  *                            READ INDEX, detaching the SKB from the pool.
3436  *                            Moves the packet buffer from queue to rx_used.
3437  *                            Calls iwl3945_rx_queue_restock to refill any empty
3438  *                            slots.
3439  * ...
3440  *
3441  */
3442
3443 /**
3444  * iwl3945_rx_queue_space - Return number of free slots available in queue.
3445  */
3446 static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
3447 {
3448         int s = q->read - q->write;
3449         if (s <= 0)
3450                 s += RX_QUEUE_SIZE;
3451         /* keep some buffer to not confuse full and empty queue */
3452         s -= 2;
3453         if (s < 0)
3454                 s = 0;
3455         return s;
3456 }
3457
3458 /**
3459  * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
3460  */
3461 int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
3462 {
3463         u32 reg = 0;
3464         int rc = 0;
3465         unsigned long flags;
3466
3467         spin_lock_irqsave(&q->lock, flags);
3468
3469         if (q->need_update == 0)
3470                 goto exit_unlock;
3471
3472         /* If power-saving is in use, make sure device is awake */
3473         if (test_bit(STATUS_POWER_PMI, &priv->status)) {
3474                 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
3475
3476                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
3477                         iwl3945_set_bit(priv, CSR_GP_CNTRL,
3478                                     CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3479                         goto exit_unlock;
3480                 }
3481
3482                 rc = iwl3945_grab_nic_access(priv);
3483                 if (rc)
3484                         goto exit_unlock;
3485
3486                 /* Device expects a multiple of 8 */
3487                 iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
3488                                      q->write & ~0x7);
3489                 iwl3945_release_nic_access(priv);
3490
3491         /* Else device is assumed to be awake */
3492         } else
3493                 /* Device expects a multiple of 8 */
3494                 iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
3495
3496
3497         q->need_update = 0;
3498
3499  exit_unlock:
3500         spin_unlock_irqrestore(&q->lock, flags);
3501         return rc;
3502 }
3503
3504 /**
3505  * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
3506  */
3507 static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
3508                                           dma_addr_t dma_addr)
3509 {
3510         return cpu_to_le32((u32)dma_addr);
3511 }
3512
3513 /**
3514  * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
3515  *
3516  * If there are slots in the RX queue that need to be restocked,
3517  * and we have free pre-allocated buffers, fill the ranks as much
3518  * as we can, pulling from rx_free.
3519  *
3520  * This moves the 'write' index forward to catch up with 'processed', and
3521  * also updates the memory address in the firmware to reference the new
3522  * target buffer.
3523  */
3524 static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
3525 {
3526         struct iwl3945_rx_queue *rxq = &priv->rxq;
3527         struct list_head *element;
3528         struct iwl3945_rx_mem_buffer *rxb;
3529         unsigned long flags;
3530         int write, rc;
3531
3532         spin_lock_irqsave(&rxq->lock, flags);
3533         write = rxq->write & ~0x7;
3534         while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
3535                 /* Get next free Rx buffer, remove from free list */
3536                 element = rxq->rx_free.next;
3537                 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
3538                 list_del(element);
3539
3540                 /* Point to Rx buffer via next RBD in circular buffer */
3541                 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
3542                 rxq->queue[rxq->write] = rxb;
3543                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
3544                 rxq->free_count--;
3545         }
3546         spin_unlock_irqrestore(&rxq->lock, flags);
3547         /* If the pre-allocated buffer pool is dropping low, schedule to
3548          * refill it */
3549         if (rxq->free_count <= RX_LOW_WATERMARK)
3550                 queue_work(priv->workqueue, &priv->rx_replenish);
3551
3552
3553         /* If we've added more space for the firmware to place data, tell it.
3554          * Increment device's write pointer in multiples of 8. */
3555         if ((write != (rxq->write & ~0x7))
3556             || (abs(rxq->write - rxq->read) > 7)) {
3557                 spin_lock_irqsave(&rxq->lock, flags);
3558                 rxq->need_update = 1;
3559                 spin_unlock_irqrestore(&rxq->lock, flags);
3560                 rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
3561                 if (rc)
3562                         return rc;
3563         }
3564
3565         return 0;
3566 }
3567
3568 /**
3569  * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
3570  *
3571  * When moving to rx_free an SKB is allocated for the slot.
3572  *
3573  * Also restock the Rx queue via iwl3945_rx_queue_restock.
3574  * This is called as a scheduled work item (except for during initialization)
3575  */
3576 static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
3577 {
3578         struct iwl3945_rx_queue *rxq = &priv->rxq;
3579         struct list_head *element;
3580         struct iwl3945_rx_mem_buffer *rxb;
3581         unsigned long flags;
3582         spin_lock_irqsave(&rxq->lock, flags);
3583         while (!list_empty(&rxq->rx_used)) {
3584                 element = rxq->rx_used.next;
3585                 rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
3586
3587                 /* Alloc a new receive buffer */
3588                 rxb->skb =
3589                     alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
3590                 if (!rxb->skb) {
3591                         if (net_ratelimit())
3592                                 printk(KERN_CRIT DRV_NAME
3593                                        ": Can not allocate SKB buffers\n");
3594                         /* We don't reschedule replenish work here -- we will
3595                          * call the restock method and if it still needs
3596                          * more buffers it will schedule replenish */
3597                         break;
3598                 }
3599
3600                 /* If radiotap head is required, reserve some headroom here.
3601                  * The physical head count is a variable rx_stats->phy_count.
3602                  * We reserve 4 bytes here. Plus these extra bytes, the
3603                  * headroom of the physical head should be enough for the
3604                  * radiotap head that iwl3945 supported. See iwl3945_rt.
3605                  */
3606                 skb_reserve(rxb->skb, 4);
3607
3608                 priv->alloc_rxb_skb++;
3609                 list_del(element);
3610
3611                 /* Get physical address of RB/SKB */
3612                 rxb->dma_addr =
3613                     pci_map_single(priv->pci_dev, rxb->skb->data,
3614                                    IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3615                 list_add_tail(&rxb->list, &rxq->rx_free);
3616                 rxq->free_count++;
3617         }
3618         spin_unlock_irqrestore(&rxq->lock, flags);
3619 }
3620
3621 /*
3622  * this should be called while priv->lock is locked
3623  */
3624 static void __iwl3945_rx_replenish(void *data)
3625 {
3626         struct iwl3945_priv *priv = data;
3627
3628         iwl3945_rx_allocate(priv);
3629         iwl3945_rx_queue_restock(priv);
3630 }
3631
3632
3633 void iwl3945_rx_replenish(void *data)
3634 {
3635         struct iwl3945_priv *priv = data;
3636         unsigned long flags;
3637
3638         iwl3945_rx_allocate(priv);
3639
3640         spin_lock_irqsave(&priv->lock, flags);
3641         iwl3945_rx_queue_restock(priv);
3642         spin_unlock_irqrestore(&priv->lock, flags);
3643 }
3644
3645 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
3646  * If an SKB has been detached, the POOL needs to have its SKB set to NULL
3647  * This free routine walks the list of POOL entries and if SKB is set to
3648  * non NULL it is unmapped and freed
3649  */
3650 static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
3651 {
3652         int i;
3653         for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
3654                 if (rxq->pool[i].skb != NULL) {
3655                         pci_unmap_single(priv->pci_dev,
3656                                          rxq->pool[i].dma_addr,
3657                                          IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3658                         dev_kfree_skb(rxq->pool[i].skb);
3659                 }
3660         }
3661
3662         pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
3663                             rxq->dma_addr);
3664         rxq->bd = NULL;
3665 }
3666
3667 int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
3668 {
3669         struct iwl3945_rx_queue *rxq = &priv->rxq;
3670         struct pci_dev *dev = priv->pci_dev;
3671         int i;
3672
3673         spin_lock_init(&rxq->lock);
3674         INIT_LIST_HEAD(&rxq->rx_free);
3675         INIT_LIST_HEAD(&rxq->rx_used);
3676
3677         /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
3678         rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
3679         if (!rxq->bd)
3680                 return -ENOMEM;
3681
3682         /* Fill the rx_used queue with _all_ of the Rx buffers */
3683         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
3684                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3685
3686         /* Set us so that we have processed and used all buffers, but have
3687          * not restocked the Rx queue with fresh buffers */
3688         rxq->read = rxq->write = 0;
3689         rxq->free_count = 0;
3690         rxq->need_update = 0;
3691         return 0;
3692 }
3693
3694 void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
3695 {
3696         unsigned long flags;
3697         int i;
3698         spin_lock_irqsave(&rxq->lock, flags);
3699         INIT_LIST_HEAD(&rxq->rx_free);
3700         INIT_LIST_HEAD(&rxq->rx_used);
3701         /* Fill the rx_used queue with _all_ of the Rx buffers */
3702         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3703                 /* In the reset function, these buffers may have been allocated
3704                  * to an SKB, so we need to unmap and free potential storage */
3705                 if (rxq->pool[i].skb != NULL) {
3706                         pci_unmap_single(priv->pci_dev,
3707                                          rxq->pool[i].dma_addr,
3708                                          IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3709                         priv->alloc_rxb_skb--;
3710                         dev_kfree_skb(rxq->pool[i].skb);
3711                         rxq->pool[i].skb = NULL;
3712                 }
3713                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3714         }
3715
3716         /* Set us so that we have processed and used all buffers, but have
3717          * not restocked the Rx queue with fresh buffers */
3718         rxq->read = rxq->write = 0;
3719         rxq->free_count = 0;
3720         spin_unlock_irqrestore(&rxq->lock, flags);
3721 }
3722
3723 /* Convert linear signal-to-noise ratio into dB */
3724 static u8 ratio2dB[100] = {
3725 /*       0   1   2   3   4   5   6   7   8   9 */
3726          0,  0,  6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
3727         20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
3728         26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
3729         29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
3730         32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
3731         34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
3732         36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
3733         37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
3734         38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
3735         39, 39, 39, 39, 39, 40, 40, 40, 40, 40  /* 90 - 99 */
3736 };
3737
3738 /* Calculates a relative dB value from a ratio of linear
3739  *   (i.e. not dB) signal levels.
3740  * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
3741 int iwl3945_calc_db_from_ratio(int sig_ratio)
3742 {
3743         /* 1000:1 or higher just report as 60 dB */
3744         if (sig_ratio >= 1000)
3745                 return 60;
3746
3747         /* 100:1 or higher, divide by 10 and use table,
3748          *   add 20 dB to make up for divide by 10 */
3749         if (sig_ratio >= 100)
3750                 return 20 + (int)ratio2dB[sig_ratio/10];
3751
3752         /* We shouldn't see this */
3753         if (sig_ratio < 1)
3754                 return 0;
3755
3756         /* Use table for ratios 1:1 - 99:1 */
3757         return (int)ratio2dB[sig_ratio];
3758 }
3759
3760 #define PERFECT_RSSI (-20) /* dBm */
3761 #define WORST_RSSI (-95)   /* dBm */
3762 #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
3763
3764 /* Calculate an indication of rx signal quality (a percentage, not dBm!).
3765  * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
3766  *   about formulas used below. */
3767 int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
3768 {
3769         int sig_qual;
3770         int degradation = PERFECT_RSSI - rssi_dbm;
3771
3772         /* If we get a noise measurement, use signal-to-noise ratio (SNR)
3773          * as indicator; formula is (signal dbm - noise dbm).
3774          * SNR at or above 40 is a great signal (100%).
3775          * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
3776          * Weakest usable signal is usually 10 - 15 dB SNR. */
3777         if (noise_dbm) {
3778                 if (rssi_dbm - noise_dbm >= 40)
3779                         return 100;
3780                 else if (rssi_dbm < noise_dbm)
3781                         return 0;
3782                 sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
3783
3784         /* Else use just the signal level.
3785          * This formula is a least squares fit of data points collected and
3786          *   compared with a reference system that had a percentage (%) display
3787          *   for signal quality. */
3788         } else
3789                 sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
3790                             (15 * RSSI_RANGE + 62 * degradation)) /
3791                            (RSSI_RANGE * RSSI_RANGE);
3792
3793         if (sig_qual > 100)
3794                 sig_qual = 100;
3795         else if (sig_qual < 1)
3796                 sig_qual = 0;
3797
3798         return sig_qual;
3799 }
3800
3801 /**
3802  * iwl3945_rx_handle - Main entry function for receiving responses from uCode
3803  *
3804  * Uses the priv->rx_handlers callback function array to invoke
3805  * the appropriate handlers, including command responses,
3806  * frame-received notifications, and other notifications.
3807  */
3808 static void iwl3945_rx_handle(struct iwl3945_priv *priv)
3809 {
3810         struct iwl3945_rx_mem_buffer *rxb;
3811         struct iwl3945_rx_packet *pkt;
3812         struct iwl3945_rx_queue *rxq = &priv->rxq;
3813         u32 r, i;
3814         int reclaim;
3815         unsigned long flags;
3816         u8 fill_rx = 0;
3817         u32 count = 8;
3818
3819         /* uCode's read index (stored in shared DRAM) indicates the last Rx
3820          * buffer that the driver may process (last buffer filled by ucode). */
3821         r = iwl3945_hw_get_rx_read(priv);
3822         i = rxq->read;
3823
3824         if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
3825                 fill_rx = 1;
3826         /* Rx interrupt, but nothing sent from uCode */
3827         if (i == r)
3828                 IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
3829
3830         while (i != r) {
3831                 rxb = rxq->queue[i];
3832
3833                 /* If an RXB doesn't have a Rx queue slot associated with it,
3834                  * then a bug has been introduced in the queue refilling
3835                  * routines -- catch it here */
3836                 BUG_ON(rxb == NULL);
3837
3838                 rxq->queue[i] = NULL;
3839
3840                 pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
3841                                             IWL_RX_BUF_SIZE,
3842                                             PCI_DMA_FROMDEVICE);
3843                 pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
3844
3845                 /* Reclaim a command buffer only if this packet is a response
3846                  *   to a (driver-originated) command.
3847                  * If the packet (e.g. Rx frame) originated from uCode,
3848                  *   there is no command buffer to reclaim.
3849                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
3850                  *   but apparently a few don't get set; catch them here. */
3851                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
3852                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
3853                         (pkt->hdr.cmd != REPLY_TX);
3854
3855                 /* Based on type of command response or notification,
3856                  *   handle those that need handling via function in
3857                  *   rx_handlers table.  See iwl3945_setup_rx_handlers() */
3858                 if (priv->rx_handlers[pkt->hdr.cmd]) {
3859                         IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
3860                                 "r = %d, i = %d, %s, 0x%02x\n", r, i,
3861                                 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
3862                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
3863                 } else {
3864                         /* No handling needed */
3865                         IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
3866                                 "r %d i %d No handler needed for %s, 0x%02x\n",
3867                                 r, i, get_cmd_string(pkt->hdr.cmd),
3868                                 pkt->hdr.cmd);
3869                 }
3870
3871                 if (reclaim) {
3872                         /* Invoke any callbacks, transfer the skb to caller, and
3873                          * fire off the (possibly) blocking iwl3945_send_cmd()
3874                          * as we reclaim the driver command queue */
3875                         if (rxb && rxb->skb)
3876                                 iwl3945_tx_cmd_complete(priv, rxb);
3877                         else
3878                                 IWL_WARNING("Claim null rxb?\n");
3879                 }
3880
3881                 /* For now we just don't re-use anything.  We can tweak this
3882                  * later to try and re-use notification packets and SKBs that
3883                  * fail to Rx correctly */
3884                 if (rxb->skb != NULL) {
3885                         priv->alloc_rxb_skb--;
3886                         dev_kfree_skb_any(rxb->skb);
3887                         rxb->skb = NULL;
3888                 }
3889
3890                 pci_unmap_single(priv->pci_dev, rxb->dma_addr,
3891                                  IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3892                 spin_lock_irqsave(&rxq->lock, flags);
3893                 list_add_tail(&rxb->list, &priv->rxq.rx_used);
3894                 spin_unlock_irqrestore(&rxq->lock, flags);
3895                 i = (i + 1) & RX_QUEUE_MASK;
3896                 /* If there are a lot of unused frames,
3897                  * restock the Rx queue so ucode won't assert. */
3898                 if (fill_rx) {
3899                         count++;
3900                         if (count >= 8) {
3901                                 priv->rxq.read = i;
3902                                 __iwl3945_rx_replenish(priv);
3903                                 count = 0;
3904                         }
3905                 }
3906         }
3907
3908         /* Backtrack one entry */
3909         priv->rxq.read = i;
3910         iwl3945_rx_queue_restock(priv);
3911 }
3912
3913 /**
3914  * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
3915  */
3916 static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
3917                                   struct iwl3945_tx_queue *txq)
3918 {
3919         u32 reg = 0;
3920         int rc = 0;
3921         int txq_id = txq->q.id;
3922
3923         if (txq->need_update == 0)
3924                 return rc;
3925
3926         /* if we're trying to save power */
3927         if (test_bit(STATUS_POWER_PMI, &priv->status)) {
3928                 /* wake up nic if it's powered down ...
3929                  * uCode will wake up, and interrupt us again, so next
3930                  * time we'll skip this part. */
3931                 reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
3932
3933                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
3934                         IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
3935                         iwl3945_set_bit(priv, CSR_GP_CNTRL,
3936                                     CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3937                         return rc;
3938                 }
3939
3940                 /* restore this queue's parameters in nic hardware. */
3941                 rc = iwl3945_grab_nic_access(priv);
3942                 if (rc)
3943                         return rc;
3944                 iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
3945                                      txq->q.write_ptr | (txq_id << 8));
3946                 iwl3945_release_nic_access(priv);
3947
3948         /* else not in power-save mode, uCode will never sleep when we're
3949          * trying to tx (during RFKILL, we're not trying to tx). */
3950         } else
3951                 iwl3945_write32(priv, HBUS_TARG_WRPTR,
3952                             txq->q.write_ptr | (txq_id << 8));
3953
3954         txq->need_update = 0;
3955
3956         return rc;
3957 }
3958
3959 #ifdef CONFIG_IWL3945_DEBUG
3960 static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
3961 {
3962         IWL_DEBUG_RADIO("RX CONFIG:\n");
3963         iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
3964         IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
3965         IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
3966         IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
3967                         le32_to_cpu(rxon->filter_flags));
3968         IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
3969         IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
3970                         rxon->ofdm_basic_rates);
3971         IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
3972         IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
3973         IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
3974         IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
3975 }
3976 #endif
3977
3978 static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
3979 {
3980         IWL_DEBUG_ISR("Enabling interrupts\n");
3981         set_bit(STATUS_INT_ENABLED, &priv->status);
3982         iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
3983 }
3984
3985
3986 /* call this function to flush any scheduled tasklet */
3987 static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
3988 {
3989         /* wait to make sure we flush pending tasklet*/
3990         synchronize_irq(priv->pci_dev->irq);
3991         tasklet_kill(&priv->irq_tasklet);
3992 }
3993
3994
3995 static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
3996 {
3997         clear_bit(STATUS_INT_ENABLED, &priv->status);
3998
3999         /* disable interrupts from uCode/NIC to host */
4000         iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
4001
4002         /* acknowledge/clear/reset any interrupts still pending
4003          * from uCode or flow handler (Rx/Tx DMA) */
4004         iwl3945_write32(priv, CSR_INT, 0xffffffff);
4005         iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
4006         IWL_DEBUG_ISR("Disabled interrupts\n");
4007 }
4008
4009 static const char *desc_lookup(int i)
4010 {
4011         switch (i) {
4012         case 1:
4013                 return "FAIL";
4014         case 2:
4015                 return "BAD_PARAM";
4016         case 3:
4017                 return "BAD_CHECKSUM";
4018         case 4:
4019                 return "NMI_INTERRUPT";
4020         case 5:
4021                 return "SYSASSERT";
4022         case 6:
4023                 return "FATAL_ERROR";
4024         }
4025
4026         return "UNKNOWN";
4027 }
4028
4029 #define ERROR_START_OFFSET  (1 * sizeof(u32))
4030 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
4031
4032 static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
4033 {
4034         u32 i;
4035         u32 desc, time, count, base, data1;
4036         u32 blink1, blink2, ilink1, ilink2;
4037         int rc;
4038
4039         base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
4040
4041         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
4042                 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
4043                 return;
4044         }
4045
4046         rc = iwl3945_grab_nic_access(priv);
4047         if (rc) {
4048                 IWL_WARNING("Can not read from adapter at this time.\n");
4049                 return;
4050         }
4051
4052         count = iwl3945_read_targ_mem(priv, base);
4053
4054         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4055                 IWL_ERROR("Start IWL Error Log Dump:\n");
4056                 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
4057         }
4058
4059         IWL_ERROR("Desc       Time       asrtPC  blink2 "
4060                   "ilink1  nmiPC   Line\n");
4061         for (i = ERROR_START_OFFSET;
4062              i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
4063              i += ERROR_ELEM_SIZE) {
4064                 desc = iwl3945_read_targ_mem(priv, base + i);
4065                 time =
4066                     iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
4067                 blink1 =
4068                     iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
4069                 blink2 =
4070                     iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
4071                 ilink1 =
4072                     iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
4073                 ilink2 =
4074                     iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
4075                 data1 =
4076                     iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
4077
4078                 IWL_ERROR
4079                     ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
4080                      desc_lookup(desc), desc, time, blink1, blink2,
4081                      ilink1, ilink2, data1);
4082         }
4083
4084         iwl3945_release_nic_access(priv);
4085
4086 }
4087
4088 #define EVENT_START_OFFSET  (6 * sizeof(u32))
4089
4090 /**
4091  * iwl3945_print_event_log - Dump error event log to syslog
4092  *
4093  * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
4094  */
4095 static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
4096                                 u32 num_events, u32 mode)
4097 {
4098         u32 i;
4099         u32 base;       /* SRAM byte address of event log header */
4100         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
4101         u32 ptr;        /* SRAM byte address of log data */
4102         u32 ev, time, data; /* event log data */
4103
4104         if (num_events == 0)
4105                 return;
4106
4107         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4108
4109         if (mode == 0)
4110                 event_size = 2 * sizeof(u32);
4111         else
4112                 event_size = 3 * sizeof(u32);
4113
4114         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
4115
4116         /* "time" is actually "data" for mode 0 (no timestamp).
4117          * place event id # at far right for easier visual parsing. */
4118         for (i = 0; i < num_events; i++) {
4119                 ev = iwl3945_read_targ_mem(priv, ptr);
4120                 ptr += sizeof(u32);
4121                 time = iwl3945_read_targ_mem(priv, ptr);
4122                 ptr += sizeof(u32);
4123                 if (mode == 0)
4124                         IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
4125                 else {
4126                         data = iwl3945_read_targ_mem(priv, ptr);
4127                         ptr += sizeof(u32);
4128                         IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
4129                 }
4130         }
4131 }
4132
4133 static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
4134 {
4135         int rc;
4136         u32 base;       /* SRAM byte address of event log header */
4137         u32 capacity;   /* event log capacity in # entries */
4138         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
4139         u32 num_wraps;  /* # times uCode wrapped to top of log */
4140         u32 next_entry; /* index of next entry to be written by uCode */
4141         u32 size;       /* # entries that we'll print */
4142
4143         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
4144         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
4145                 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
4146                 return;
4147         }
4148
4149         rc = iwl3945_grab_nic_access(priv);
4150         if (rc) {
4151                 IWL_WARNING("Can not read from adapter at this time.\n");
4152                 return;
4153         }
4154
4155         /* event log header */
4156         capacity = iwl3945_read_targ_mem(priv, base);
4157         mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
4158         num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
4159         next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
4160
4161         size = num_wraps ? capacity : next_entry;
4162
4163         /* bail out if nothing in log */
4164         if (size == 0) {
4165                 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
4166                 iwl3945_release_nic_access(priv);
4167                 return;
4168         }
4169
4170         IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
4171                   size, num_wraps);
4172
4173         /* if uCode has wrapped back to top of log, start at the oldest entry,
4174          * i.e the next one that uCode would fill. */
4175         if (num_wraps)
4176                 iwl3945_print_event_log(priv, next_entry,
4177                                     capacity - next_entry, mode);
4178
4179         /* (then/else) start at top of log */
4180         iwl3945_print_event_log(priv, 0, next_entry, mode);
4181
4182         iwl3945_release_nic_access(priv);
4183 }
4184
4185 /**
4186  * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
4187  */
4188 static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
4189 {
4190         /* Set the FW error flag -- cleared on iwl3945_down */
4191         set_bit(STATUS_FW_ERROR, &priv->status);
4192
4193         /* Cancel currently queued command. */
4194         clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
4195
4196 #ifdef CONFIG_IWL3945_DEBUG
4197         if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
4198                 iwl3945_dump_nic_error_log(priv);
4199                 iwl3945_dump_nic_event_log(priv);
4200                 iwl3945_print_rx_config_cmd(&priv->staging_rxon);
4201         }
4202 #endif
4203
4204         wake_up_interruptible(&priv->wait_command_queue);
4205
4206         /* Keep the restart process from trying to send host
4207          * commands by clearing the INIT status bit */
4208         clear_bit(STATUS_READY, &priv->status);
4209
4210         if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4211                 IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
4212                           "Restarting adapter due to uCode error.\n");
4213
4214                 if (iwl3945_is_associated(priv)) {
4215                         memcpy(&priv->recovery_rxon, &priv->active_rxon,
4216                                sizeof(priv->recovery_rxon));
4217                         priv->error_recovering = 1;
4218                 }
4219                 queue_work(priv->workqueue, &priv->restart);
4220         }
4221 }
4222
4223 static void iwl3945_error_recovery(struct iwl3945_priv *priv)
4224 {
4225         unsigned long flags;
4226
4227         memcpy(&priv->staging_rxon, &priv->recovery_rxon,
4228                sizeof(priv->staging_rxon));
4229         priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
4230         iwl3945_commit_rxon(priv);
4231
4232         iwl3945_add_station(priv, priv->bssid, 1, 0);
4233
4234         spin_lock_irqsave(&priv->lock, flags);
4235         priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
4236         priv->error_recovering = 0;
4237         spin_unlock_irqrestore(&priv->lock, flags);
4238 }
4239
4240 static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
4241 {
4242         u32 inta, handled = 0;
4243         u32 inta_fh;
4244         unsigned long flags;
4245 #ifdef CONFIG_IWL3945_DEBUG
4246         u32 inta_mask;
4247 #endif
4248
4249         spin_lock_irqsave(&priv->lock, flags);
4250
4251         /* Ack/clear/reset pending uCode interrupts.
4252          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4253          *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
4254         inta = iwl3945_read32(priv, CSR_INT);
4255         iwl3945_write32(priv, CSR_INT, inta);
4256
4257         /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4258          * Any new interrupts that happen after this, either while we're
4259          * in this tasklet, or later, will show up in next ISR/tasklet. */
4260         inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4261         iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
4262
4263 #ifdef CONFIG_IWL3945_DEBUG
4264         if (iwl3945_debug_level & IWL_DL_ISR) {
4265                 /* just for debug */
4266                 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4267                 IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4268                               inta, inta_mask, inta_fh);
4269         }
4270 #endif
4271
4272         /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4273          * atomic, make sure that inta covers all the interrupts that
4274          * we've discovered, even if FH interrupt came in just after
4275          * reading CSR_INT. */
4276         if (inta_fh & CSR39_FH_INT_RX_MASK)
4277                 inta |= CSR_INT_BIT_FH_RX;
4278         if (inta_fh & CSR39_FH_INT_TX_MASK)
4279                 inta |= CSR_INT_BIT_FH_TX;
4280
4281         /* Now service all interrupt bits discovered above. */
4282         if (inta & CSR_INT_BIT_HW_ERR) {
4283                 IWL_ERROR("Microcode HW error detected.  Restarting.\n");
4284
4285                 /* Tell the device to stop sending interrupts */
4286                 iwl3945_disable_interrupts(priv);
4287
4288                 iwl3945_irq_handle_error(priv);
4289
4290                 handled |= CSR_INT_BIT_HW_ERR;
4291
4292                 spin_unlock_irqrestore(&priv->lock, flags);
4293
4294                 return;
4295         }
4296
4297 #ifdef CONFIG_IWL3945_DEBUG
4298         if (iwl3945_debug_level & (IWL_DL_ISR)) {
4299                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
4300                 if (inta & CSR_INT_BIT_SCD)
4301                         IWL_DEBUG_ISR("Scheduler finished to transmit "
4302                                       "the frame/frames.\n");
4303
4304                 /* Alive notification via Rx interrupt will do the real work */
4305                 if (inta & CSR_INT_BIT_ALIVE)
4306                         IWL_DEBUG_ISR("Alive interrupt\n");
4307         }
4308 #endif
4309         /* Safely ignore these bits for debug checks below */
4310         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
4311
4312         /* HW RF KILL switch toggled (4965 only) */
4313         if (inta & CSR_INT_BIT_RF_KILL) {
4314                 int hw_rf_kill = 0;
4315                 if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
4316                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4317                         hw_rf_kill = 1;
4318
4319                 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
4320                                 "RF_KILL bit toggled to %s.\n",
4321                                 hw_rf_kill ? "disable radio":"enable radio");
4322
4323                 /* Queue restart only if RF_KILL switch was set to "kill"
4324                  *   when we loaded driver, and is now set to "enable".
4325                  * After we're Alive, RF_KILL gets handled by
4326                  *   iwl3945_rx_card_state_notif() */
4327                 if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
4328                         clear_bit(STATUS_RF_KILL_HW, &priv->status);
4329                         queue_work(priv->workqueue, &priv->restart);
4330                 }
4331
4332                 handled |= CSR_INT_BIT_RF_KILL;
4333         }
4334
4335         /* Chip got too hot and stopped itself (4965 only) */
4336         if (inta & CSR_INT_BIT_CT_KILL) {
4337                 IWL_ERROR("Microcode CT kill error detected.\n");
4338                 handled |= CSR_INT_BIT_CT_KILL;
4339         }
4340
4341         /* Error detected by uCode */
4342         if (inta & CSR_INT_BIT_SW_ERR) {
4343                 IWL_ERROR("Microcode SW error detected.  Restarting 0x%X.\n",
4344                           inta);
4345                 iwl3945_irq_handle_error(priv);
4346                 handled |= CSR_INT_BIT_SW_ERR;
4347         }
4348
4349         /* uCode wakes up after power-down sleep */
4350         if (inta & CSR_INT_BIT_WAKEUP) {
4351                 IWL_DEBUG_ISR("Wakeup interrupt\n");
4352                 iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
4353                 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
4354                 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
4355                 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
4356                 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
4357                 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
4358                 iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
4359
4360                 handled |= CSR_INT_BIT_WAKEUP;
4361         }
4362
4363         /* All uCode command responses, including Tx command responses,
4364          * Rx "responses" (frame-received notification), and other
4365          * notifications from uCode come through here*/
4366         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
4367                 iwl3945_rx_handle(priv);
4368                 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4369         }
4370
4371         if (inta & CSR_INT_BIT_FH_TX) {
4372                 IWL_DEBUG_ISR("Tx interrupt\n");
4373
4374                 iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
4375                 if (!iwl3945_grab_nic_access(priv)) {
4376                         iwl3945_write_direct32(priv,
4377                                              FH_TCSR_CREDIT
4378                                              (ALM_FH_SRVC_CHNL), 0x0);
4379                         iwl3945_release_nic_access(priv);
4380                 }
4381                 handled |= CSR_INT_BIT_FH_TX;
4382         }
4383
4384         if (inta & ~handled)
4385                 IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4386
4387         if (inta & ~CSR_INI_SET_MASK) {
4388                 IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
4389                          inta & ~CSR_INI_SET_MASK);
4390                 IWL_WARNING("   with FH_INT = 0x%08x\n", inta_fh);
4391         }
4392
4393         /* Re-enable all interrupts */
4394         /* only Re-enable if disabled by irq */
4395         if (test_bit(STATUS_INT_ENABLED, &priv->status))
4396                 iwl3945_enable_interrupts(priv);
4397
4398 #ifdef CONFIG_IWL3945_DEBUG
4399         if (iwl3945_debug_level & (IWL_DL_ISR)) {
4400                 inta = iwl3945_read32(priv, CSR_INT);
4401                 inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
4402                 inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4403                 IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4404                         "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4405         }
4406 #endif
4407         spin_unlock_irqrestore(&priv->lock, flags);
4408 }
4409
4410 static irqreturn_t iwl3945_isr(int irq, void *data)
4411 {
4412         struct iwl3945_priv *priv = data;
4413         u32 inta, inta_mask;
4414         u32 inta_fh;
4415         if (!priv)
4416                 return IRQ_NONE;
4417
4418         spin_lock(&priv->lock);
4419
4420         /* Disable (but don't clear!) interrupts here to avoid
4421          *    back-to-back ISRs and sporadic interrupts from our NIC.
4422          * If we have something to service, the tasklet will re-enable ints.
4423          * If we *don't* have something, we'll re-enable before leaving here. */
4424         inta_mask = iwl3945_read32(priv, CSR_INT_MASK);  /* just for debug */
4425         iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
4426
4427         /* Discover which interrupts are active/pending */
4428         inta = iwl3945_read32(priv, CSR_INT);
4429         inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
4430
4431         /* Ignore interrupt if there's nothing in NIC to service.
4432          * This may be due to IRQ shared with another device,
4433          * or due to sporadic interrupts thrown from our NIC. */
4434         if (!inta && !inta_fh) {
4435                 IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
4436                 goto none;
4437         }
4438
4439         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
4440                 /* Hardware disappeared */
4441                 IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
4442                 goto unplugged;
4443         }
4444
4445         IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
4446                       inta, inta_mask, inta_fh);
4447
4448         inta &= ~CSR_INT_BIT_SCD;
4449
4450         /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
4451         if (likely(inta || inta_fh))
4452                 tasklet_schedule(&priv->irq_tasklet);
4453 unplugged:
4454         spin_unlock(&priv->lock);
4455
4456         return IRQ_HANDLED;
4457
4458  none:
4459         /* re-enable interrupts here since we don't have anything to service. */
4460         /* only Re-enable if disabled by irq */
4461         if (test_bit(STATUS_INT_ENABLED, &priv->status))
4462                 iwl3945_enable_interrupts(priv);
4463         spin_unlock(&priv->lock);
4464         return IRQ_NONE;
4465 }
4466
4467 /************************** EEPROM BANDS ****************************
4468  *
4469  * The iwl3945_eeprom_band definitions below provide the mapping from the
4470  * EEPROM contents to the specific channel number supported for each
4471  * band.
4472  *
4473  * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
4474  * definition below maps to physical channel 42 in the 5.2GHz spectrum.
4475  * The specific geography and calibration information for that channel
4476  * is contained in the eeprom map itself.
4477  *
4478  * During init, we copy the eeprom information and channel map
4479  * information into priv->channel_info_24/52 and priv->channel_map_24/52
4480  *
4481  * channel_map_24/52 provides the index in the channel_info array for a
4482  * given channel.  We have to have two separate maps as there is channel
4483  * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
4484  * band_2
4485  *
4486  * A value of 0xff stored in the channel_map indicates that the channel
4487  * is not supported by the hardware at all.
4488  *
4489  * A value of 0xfe in the channel_map indicates that the channel is not
4490  * valid for Tx with the current hardware.  This means that
4491  * while the system can tune and receive on a given channel, it may not
4492  * be able to associate or transmit any frames on that
4493  * channel.  There is no corresponding channel information for that
4494  * entry.
4495  *
4496  *********************************************************************/
4497
4498 /* 2.4 GHz */
4499 static const u8 iwl3945_eeprom_band_1[14] = {
4500         1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4501 };
4502
4503 /* 5.2 GHz bands */
4504 static const u8 iwl3945_eeprom_band_2[] = {     /* 4915-5080MHz */
4505         183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4506 };
4507
4508 static const u8 iwl3945_eeprom_band_3[] = {     /* 5170-5320MHz */
4509         34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4510 };
4511
4512 static const u8 iwl3945_eeprom_band_4[] = {     /* 5500-5700MHz */
4513         100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4514 };
4515
4516 static const u8 iwl3945_eeprom_band_5[] = {     /* 5725-5825MHz */
4517         145, 149, 153, 157, 161, 165
4518 };
4519
4520 static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
4521                                     int *eeprom_ch_count,
4522                                     const struct iwl3945_eeprom_channel
4523                                     **eeprom_ch_info,
4524                                     const u8 **eeprom_ch_index)
4525 {
4526         switch (band) {
4527         case 1:         /* 2.4GHz band */
4528                 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
4529                 *eeprom_ch_info = priv->eeprom.band_1_channels;
4530                 *eeprom_ch_index = iwl3945_eeprom_band_1;
4531                 break;
4532         case 2:         /* 4.9GHz band */
4533                 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
4534                 *eeprom_ch_info = priv->eeprom.band_2_channels;
4535                 *eeprom_ch_index = iwl3945_eeprom_band_2;
4536                 break;
4537         case 3:         /* 5.2GHz band */
4538                 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
4539                 *eeprom_ch_info = priv->eeprom.band_3_channels;
4540                 *eeprom_ch_index = iwl3945_eeprom_band_3;
4541                 break;
4542         case 4:         /* 5.5GHz band */
4543                 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
4544                 *eeprom_ch_info = priv->eeprom.band_4_channels;
4545                 *eeprom_ch_index = iwl3945_eeprom_band_4;
4546                 break;
4547         case 5:         /* 5.7GHz band */
4548                 *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
4549                 *eeprom_ch_info = priv->eeprom.band_5_channels;
4550                 *eeprom_ch_index = iwl3945_eeprom_band_5;
4551                 break;
4552         default:
4553                 BUG();
4554                 return;
4555         }
4556 }
4557
4558 /**
4559  * iwl3945_get_channel_info - Find driver's private channel info
4560  *
4561  * Based on band and channel number.
4562  */
4563 const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
4564                                                     enum ieee80211_band band, u16 channel)
4565 {
4566         int i;
4567
4568         switch (band) {
4569         case IEEE80211_BAND_5GHZ:
4570                 for (i = 14; i < priv->channel_count; i++) {
4571                         if (priv->channel_info[i].channel == channel)
4572                                 return &priv->channel_info[i];
4573                 }
4574                 break;
4575
4576         case IEEE80211_BAND_2GHZ:
4577                 if (channel >= 1 && channel <= 14)
4578                         return &priv->channel_info[channel - 1];
4579                 break;
4580         case IEEE80211_NUM_BANDS:
4581                 WARN_ON(1);
4582         }
4583
4584         return NULL;
4585 }
4586
4587 #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
4588                             ? # x " " : "")
4589
4590 /**
4591  * iwl3945_init_channel_map - Set up driver's info for all possible channels
4592  */
4593 static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
4594 {
4595         int eeprom_ch_count = 0;
4596         const u8 *eeprom_ch_index = NULL;
4597         const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
4598         int band, ch;
4599         struct iwl3945_channel_info *ch_info;
4600
4601         if (priv->channel_count) {
4602                 IWL_DEBUG_INFO("Channel map already initialized.\n");
4603                 return 0;
4604         }
4605
4606         if (priv->eeprom.version < 0x2f) {
4607                 IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
4608                             priv->eeprom.version);
4609                 return -EINVAL;
4610         }
4611
4612         IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
4613
4614         priv->channel_count =
4615             ARRAY_SIZE(iwl3945_eeprom_band_1) +
4616             ARRAY_SIZE(iwl3945_eeprom_band_2) +
4617             ARRAY_SIZE(iwl3945_eeprom_band_3) +
4618             ARRAY_SIZE(iwl3945_eeprom_band_4) +
4619             ARRAY_SIZE(iwl3945_eeprom_band_5);
4620
4621         IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
4622
4623         priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
4624                                      priv->channel_count, GFP_KERNEL);
4625         if (!priv->channel_info) {
4626                 IWL_ERROR("Could not allocate channel_info\n");
4627                 priv->channel_count = 0;
4628                 return -ENOMEM;
4629         }
4630
4631         ch_info = priv->channel_info;
4632
4633         /* Loop through the 5 EEPROM bands adding them in order to the
4634          * channel map we maintain (that contains additional information than
4635          * what just in the EEPROM) */
4636         for (band = 1; band <= 5; band++) {
4637
4638                 iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
4639                                         &eeprom_ch_info, &eeprom_ch_index);
4640
4641                 /* Loop through each band adding each of the channels */
4642                 for (ch = 0; ch < eeprom_ch_count; ch++) {
4643                         ch_info->channel = eeprom_ch_index[ch];
4644                         ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
4645                             IEEE80211_BAND_5GHZ;
4646
4647                         /* permanently store EEPROM's channel regulatory flags
4648                          *   and max power in channel info database. */
4649                         ch_info->eeprom = eeprom_ch_info[ch];
4650
4651                         /* Copy the run-time flags so they are there even on
4652                          * invalid channels */
4653                         ch_info->flags = eeprom_ch_info[ch].flags;
4654
4655                         if (!(is_channel_valid(ch_info))) {
4656                                 IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
4657                                                "No traffic\n",
4658                                                ch_info->channel,
4659                                                ch_info->flags,
4660                                                is_channel_a_band(ch_info) ?
4661                                                "5.2" : "2.4");
4662                                 ch_info++;
4663                                 continue;
4664                         }
4665
4666                         /* Initialize regulatory-based run-time data */
4667                         ch_info->max_power_avg = ch_info->curr_txpow =
4668                             eeprom_ch_info[ch].max_power_avg;
4669                         ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
4670                         ch_info->min_power = 0;
4671
4672                         IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
4673                                        " %ddBm): Ad-Hoc %ssupported\n",
4674                                        ch_info->channel,
4675                                        is_channel_a_band(ch_info) ?
4676                                        "5.2" : "2.4",
4677                                        CHECK_AND_PRINT(VALID),
4678                                        CHECK_AND_PRINT(IBSS),
4679                                        CHECK_AND_PRINT(ACTIVE),
4680                                        CHECK_AND_PRINT(RADAR),
4681                                        CHECK_AND_PRINT(WIDE),
4682                                        CHECK_AND_PRINT(DFS),
4683                                        eeprom_ch_info[ch].flags,
4684                                        eeprom_ch_info[ch].max_power_avg,
4685                                        ((eeprom_ch_info[ch].
4686                                          flags & EEPROM_CHANNEL_IBSS)
4687                                         && !(eeprom_ch_info[ch].
4688                                              flags & EEPROM_CHANNEL_RADAR))
4689                                        ? "" : "not ");
4690
4691                         /* Set the user_txpower_limit to the highest power
4692                          * supported by any channel */
4693                         if (eeprom_ch_info[ch].max_power_avg >
4694                             priv->user_txpower_limit)
4695                                 priv->user_txpower_limit =
4696                                     eeprom_ch_info[ch].max_power_avg;
4697
4698                         ch_info++;
4699                 }
4700         }
4701
4702         /* Set up txpower settings in driver for all channels */
4703         if (iwl3945_txpower_set_from_eeprom(priv))
4704                 return -EIO;
4705
4706         return 0;
4707 }
4708
4709 /*
4710  * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
4711  */
4712 static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
4713 {
4714         kfree(priv->channel_info);
4715         priv->channel_count = 0;
4716 }
4717
4718 /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
4719  * sending probe req.  This should be set long enough to hear probe responses
4720  * from more than one AP.  */
4721 #define IWL_ACTIVE_DWELL_TIME_24    (30)        /* all times in msec */
4722 #define IWL_ACTIVE_DWELL_TIME_52    (20)
4723
4724 #define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
4725 #define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
4726
4727 /* For faster active scanning, scan will move to the next channel if fewer than
4728  * PLCP_QUIET_THRESH packets are heard on this channel within
4729  * ACTIVE_QUIET_TIME after sending probe request.  This shortens the dwell
4730  * time if it's a quiet channel (nothing responded to our probe, and there's
4731  * no other traffic).
4732  * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
4733 #define IWL_PLCP_QUIET_THRESH       __constant_cpu_to_le16(1)   /* packets */
4734 #define IWL_ACTIVE_QUIET_TIME       __constant_cpu_to_le16(10)  /* msec */
4735
4736 /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
4737  * Must be set longer than active dwell time.
4738  * For the most reliable scan, set > AP beacon interval (typically 100msec). */
4739 #define IWL_PASSIVE_DWELL_TIME_24   (20)        /* all times in msec */
4740 #define IWL_PASSIVE_DWELL_TIME_52   (10)
4741 #define IWL_PASSIVE_DWELL_BASE      (100)
4742 #define IWL_CHANNEL_TUNE_TIME       5
4743
4744 #define IWL_SCAN_PROBE_MASK(n)   cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
4745
4746 static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
4747                                                 enum ieee80211_band band,
4748                                                 u8 n_probes)
4749 {
4750         if (band == IEEE80211_BAND_5GHZ)
4751                 return IWL_ACTIVE_DWELL_TIME_52 +
4752                         IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
4753         else
4754                 return IWL_ACTIVE_DWELL_TIME_24 +
4755                         IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
4756 }
4757
4758 static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
4759                                           enum ieee80211_band band)
4760 {
4761         u16 passive = (band == IEEE80211_BAND_2GHZ) ?
4762             IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
4763             IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
4764
4765         if (iwl3945_is_associated(priv)) {
4766                 /* If we're associated, we clamp the maximum passive
4767                  * dwell time to be 98% of the beacon interval (minus
4768                  * 2 * channel tune time) */
4769                 passive = priv->beacon_int;
4770                 if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
4771                         passive = IWL_PASSIVE_DWELL_BASE;
4772                 passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
4773         }
4774
4775         return passive;
4776 }
4777
4778 static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
4779                                          enum ieee80211_band band,
4780                                      u8 is_active, u8 n_probes,
4781                                      struct iwl3945_scan_channel *scan_ch)
4782 {
4783         const struct ieee80211_channel *channels = NULL;
4784         const struct ieee80211_supported_band *sband;
4785         const struct iwl3945_channel_info *ch_info;
4786         u16 passive_dwell = 0;
4787         u16 active_dwell = 0;
4788         int added, i;
4789
4790         sband = iwl3945_get_band(priv, band);
4791         if (!sband)
4792                 return 0;
4793
4794         channels = sband->channels;
4795
4796         active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
4797         passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
4798
4799         if (passive_dwell <= active_dwell)
4800                 passive_dwell = active_dwell + 1;
4801
4802         for (i = 0, added = 0; i < sband->n_channels; i++) {
4803                 if (channels[i].flags & IEEE80211_CHAN_DISABLED)
4804                         continue;
4805
4806                 scan_ch->channel = channels[i].hw_value;
4807
4808                 ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
4809                 if (!is_channel_valid(ch_info)) {
4810                         IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
4811                                        scan_ch->channel);
4812                         continue;
4813                 }
4814
4815                 if (!is_active || is_channel_passive(ch_info) ||
4816                     (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
4817                         scan_ch->type = 0;      /* passive */
4818                 else
4819                         scan_ch->type = 1;      /* active */
4820
4821                 if ((scan_ch->type & 1) && n_probes)
4822                         scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
4823
4824                 scan_ch->active_dwell = cpu_to_le16(active_dwell);
4825                 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
4826
4827                 /* Set txpower levels to defaults */
4828                 scan_ch->tpc.dsp_atten = 110;
4829                 /* scan_pwr_info->tpc.dsp_atten; */
4830
4831                 /*scan_pwr_info->tpc.tx_gain; */
4832                 if (band == IEEE80211_BAND_5GHZ)
4833                         scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
4834                 else {
4835                         scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
4836                         /* NOTE: if we were doing 6Mb OFDM for scans we'd use
4837                          * power level:
4838                          * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
4839                          */
4840                 }
4841
4842                 IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
4843                                scan_ch->channel,
4844                                (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
4845                                (scan_ch->type & 1) ?
4846                                active_dwell : passive_dwell);
4847
4848                 scan_ch++;
4849                 added++;
4850         }
4851
4852         IWL_DEBUG_SCAN("total channels to scan %d \n", added);
4853         return added;
4854 }
4855
4856 static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
4857                               struct ieee80211_rate *rates)
4858 {
4859         int i;
4860
4861         for (i = 0; i < IWL_RATE_COUNT; i++) {
4862                 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
4863                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4864                 rates[i].hw_value_short = i;
4865                 rates[i].flags = 0;
4866                 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
4867                         /*
4868                          * If CCK != 1M then set short preamble rate flag.
4869                          */
4870                         rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
4871                                 0 : IEEE80211_RATE_SHORT_PREAMBLE;
4872                 }
4873         }
4874 }
4875
4876 /**
4877  * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
4878  */
4879 static int iwl3945_init_geos(struct iwl3945_priv *priv)
4880 {
4881         struct iwl3945_channel_info *ch;
4882         struct ieee80211_supported_band *sband;
4883         struct ieee80211_channel *channels;
4884         struct ieee80211_channel *geo_ch;
4885         struct ieee80211_rate *rates;
4886         int i = 0;
4887
4888         if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
4889             priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
4890                 IWL_DEBUG_INFO("Geography modes already initialized.\n");
4891                 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4892                 return 0;
4893         }
4894
4895         channels = kzalloc(sizeof(struct ieee80211_channel) *
4896                            priv->channel_count, GFP_KERNEL);
4897         if (!channels)
4898                 return -ENOMEM;
4899
4900         rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
4901                         GFP_KERNEL);
4902         if (!rates) {
4903                 kfree(channels);
4904                 return -ENOMEM;
4905         }
4906
4907         /* 5.2GHz channels start after the 2.4GHz channels */
4908         sband = &priv->bands[IEEE80211_BAND_5GHZ];
4909         sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
4910         /* just OFDM */
4911         sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
4912         sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
4913
4914         sband = &priv->bands[IEEE80211_BAND_2GHZ];
4915         sband->channels = channels;
4916         /* OFDM & CCK */
4917         sband->bitrates = rates;
4918         sband->n_bitrates = IWL_RATE_COUNT;
4919
4920         priv->ieee_channels = channels;
4921         priv->ieee_rates = rates;
4922
4923         iwl3945_init_hw_rates(priv, rates);
4924
4925         for (i = 0;  i < priv->channel_count; i++) {
4926                 ch = &priv->channel_info[i];
4927
4928                 /* FIXME: might be removed if scan is OK*/
4929                 if (!is_channel_valid(ch))
4930                         continue;
4931
4932                 if (is_channel_a_band(ch))
4933                         sband =  &priv->bands[IEEE80211_BAND_5GHZ];
4934                 else
4935                         sband =  &priv->bands[IEEE80211_BAND_2GHZ];
4936
4937                 geo_ch = &sband->channels[sband->n_channels++];
4938
4939                 geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
4940                 geo_ch->max_power = ch->max_power_avg;
4941                 geo_ch->max_antenna_gain = 0xff;
4942                 geo_ch->hw_value = ch->channel;
4943
4944                 if (is_channel_valid(ch)) {
4945                         if (!(ch->flags & EEPROM_CHANNEL_IBSS))
4946                                 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
4947
4948                         if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
4949                                 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
4950
4951                         if (ch->flags & EEPROM_CHANNEL_RADAR)
4952                                 geo_ch->flags |= IEEE80211_CHAN_RADAR;
4953
4954                         if (ch->max_power_avg > priv->max_channel_txpower_limit)
4955                                 priv->max_channel_txpower_limit =
4956                                     ch->max_power_avg;
4957                 } else {
4958                         geo_ch->flags |= IEEE80211_CHAN_DISABLED;
4959                 }
4960
4961                 /* Save flags for reg domain usage */
4962                 geo_ch->orig_flags = geo_ch->flags;
4963
4964                 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
4965                                 ch->channel, geo_ch->center_freq,
4966                                 is_channel_a_band(ch) ?  "5.2" : "2.4",
4967                                 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
4968                                 "restricted" : "valid",
4969                                  geo_ch->flags);
4970         }
4971
4972         if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
4973              priv->cfg->sku & IWL_SKU_A) {
4974                 printk(KERN_INFO DRV_NAME
4975                        ": Incorrectly detected BG card as ABG.  Please send "
4976                        "your PCI ID 0x%04X:0x%04X to maintainer.\n",
4977                        priv->pci_dev->device, priv->pci_dev->subsystem_device);
4978                  priv->cfg->sku &= ~IWL_SKU_A;
4979         }
4980
4981         printk(KERN_INFO DRV_NAME
4982                ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
4983                priv->bands[IEEE80211_BAND_2GHZ].n_channels,
4984                priv->bands[IEEE80211_BAND_5GHZ].n_channels);
4985
4986         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
4987                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
4988                         &priv->bands[IEEE80211_BAND_2GHZ];
4989         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
4990                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
4991                         &priv->bands[IEEE80211_BAND_5GHZ];
4992
4993         set_bit(STATUS_GEO_CONFIGURED, &priv->status);
4994
4995         return 0;
4996 }
4997
4998 /*
4999  * iwl3945_free_geos - undo allocations in iwl3945_init_geos
5000  */
5001 static void iwl3945_free_geos(struct iwl3945_priv *priv)
5002 {
5003         kfree(priv->ieee_channels);
5004         kfree(priv->ieee_rates);
5005         clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
5006 }
5007
5008 /******************************************************************************
5009  *
5010  * uCode download functions
5011  *
5012  ******************************************************************************/
5013
5014 static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
5015 {
5016         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
5017         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
5018         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
5019         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
5020         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5021         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
5022 }
5023
5024 /**
5025  * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
5026  *     looking at all data.
5027  */
5028 static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 *image, u32 len)
5029 {
5030         u32 val;
5031         u32 save_len = len;
5032         int rc = 0;
5033         u32 errcnt;
5034
5035         IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5036
5037         rc = iwl3945_grab_nic_access(priv);
5038         if (rc)
5039                 return rc;
5040
5041         iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
5042
5043         errcnt = 0;
5044         for (; len > 0; len -= sizeof(u32), image++) {
5045                 /* read data comes through single port, auto-incr addr */
5046                 /* NOTE: Use the debugless read so we don't flood kernel log
5047                  * if IWL_DL_IO is set */
5048                 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
5049                 if (val != le32_to_cpu(*image)) {
5050                         IWL_ERROR("uCode INST section is invalid at "
5051                                   "offset 0x%x, is 0x%x, s/b 0x%x\n",
5052                                   save_len - len, val, le32_to_cpu(*image));
5053                         rc = -EIO;
5054                         errcnt++;
5055                         if (errcnt >= 20)
5056                                 break;
5057                 }
5058         }
5059
5060         iwl3945_release_nic_access(priv);
5061
5062         if (!errcnt)
5063                 IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
5064
5065         return rc;
5066 }
5067
5068
5069 /**
5070  * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
5071  *   using sample data 100 bytes apart.  If these sample points are good,
5072  *   it's a pretty good bet that everything between them is good, too.
5073  */
5074 static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
5075 {
5076         u32 val;
5077         int rc = 0;
5078         u32 errcnt = 0;
5079         u32 i;
5080
5081         IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
5082
5083         rc = iwl3945_grab_nic_access(priv);
5084         if (rc)
5085                 return rc;
5086
5087         for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
5088                 /* read data comes through single port, auto-incr addr */
5089                 /* NOTE: Use the debugless read so we don't flood kernel log
5090                  * if IWL_DL_IO is set */
5091                 iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
5092                         i + RTC_INST_LOWER_BOUND);
5093                 val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
5094                 if (val != le32_to_cpu(*image)) {
5095 #if 0 /* Enable this if you want to see details */
5096                         IWL_ERROR("uCode INST section is invalid at "
5097                                   "offset 0x%x, is 0x%x, s/b 0x%x\n",
5098                                   i, val, *image);
5099 #endif
5100                         rc = -EIO;
5101                         errcnt++;
5102                         if (errcnt >= 3)
5103                                 break;
5104                 }
5105         }
5106
5107         iwl3945_release_nic_access(priv);
5108
5109         return rc;
5110 }
5111
5112
5113 /**
5114  * iwl3945_verify_ucode - determine which instruction image is in SRAM,
5115  *    and verify its contents
5116  */
5117 static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
5118 {
5119         __le32 *image;
5120         u32 len;
5121         int rc = 0;
5122
5123         /* Try bootstrap */
5124         image = (__le32 *)priv->ucode_boot.v_addr;
5125         len = priv->ucode_boot.len;
5126         rc = iwl3945_verify_inst_sparse(priv, image, len);
5127         if (rc == 0) {
5128                 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
5129                 return 0;
5130         }
5131
5132         /* Try initialize */
5133         image = (__le32 *)priv->ucode_init.v_addr;
5134         len = priv->ucode_init.len;
5135         rc = iwl3945_verify_inst_sparse(priv, image, len);
5136         if (rc == 0) {
5137                 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
5138                 return 0;
5139         }
5140
5141         /* Try runtime/protocol */
5142         image = (__le32 *)priv->ucode_code.v_addr;
5143         len = priv->ucode_code.len;
5144         rc = iwl3945_verify_inst_sparse(priv, image, len);
5145         if (rc == 0) {
5146                 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
5147                 return 0;
5148         }
5149
5150         IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
5151
5152         /* Since nothing seems to match, show first several data entries in
5153          * instruction SRAM, so maybe visual inspection will give a clue.
5154          * Selection of bootstrap image (vs. other images) is arbitrary. */
5155         image = (__le32 *)priv->ucode_boot.v_addr;
5156         len = priv->ucode_boot.len;
5157         rc = iwl3945_verify_inst_full(priv, image, len);
5158
5159         return rc;
5160 }
5161
5162
5163 /* check contents of special bootstrap uCode SRAM */
5164 static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
5165 {
5166         __le32 *image = priv->ucode_boot.v_addr;
5167         u32 len = priv->ucode_boot.len;
5168         u32 reg;
5169         u32 val;
5170
5171         IWL_DEBUG_INFO("Begin verify bsm\n");
5172
5173         /* verify BSM SRAM contents */
5174         val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
5175         for (reg = BSM_SRAM_LOWER_BOUND;
5176              reg < BSM_SRAM_LOWER_BOUND + len;
5177              reg += sizeof(u32), image++) {
5178                 val = iwl3945_read_prph(priv, reg);
5179                 if (val != le32_to_cpu(*image)) {
5180                         IWL_ERROR("BSM uCode verification failed at "
5181                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
5182                                   BSM_SRAM_LOWER_BOUND,
5183                                   reg - BSM_SRAM_LOWER_BOUND, len,
5184                                   val, le32_to_cpu(*image));
5185                         return -EIO;
5186                 }
5187         }
5188
5189         IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
5190
5191         return 0;
5192 }
5193
5194 /**
5195  * iwl3945_load_bsm - Load bootstrap instructions
5196  *
5197  * BSM operation:
5198  *
5199  * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
5200  * in special SRAM that does not power down during RFKILL.  When powering back
5201  * up after power-saving sleeps (or during initial uCode load), the BSM loads
5202  * the bootstrap program into the on-board processor, and starts it.
5203  *
5204  * The bootstrap program loads (via DMA) instructions and data for a new
5205  * program from host DRAM locations indicated by the host driver in the
5206  * BSM_DRAM_* registers.  Once the new program is loaded, it starts
5207  * automatically.
5208  *
5209  * When initializing the NIC, the host driver points the BSM to the
5210  * "initialize" uCode image.  This uCode sets up some internal data, then
5211  * notifies host via "initialize alive" that it is complete.
5212  *
5213  * The host then replaces the BSM_DRAM_* pointer values to point to the
5214  * normal runtime uCode instructions and a backup uCode data cache buffer
5215  * (filled initially with starting data values for the on-board processor),
5216  * then triggers the "initialize" uCode to load and launch the runtime uCode,
5217  * which begins normal operation.
5218  *
5219  * When doing a power-save shutdown, runtime uCode saves data SRAM into
5220  * the backup data cache in DRAM before SRAM is powered down.
5221  *
5222  * When powering back up, the BSM loads the bootstrap program.  This reloads
5223  * the runtime uCode instructions and the backup data cache into SRAM,
5224  * and re-launches the runtime uCode from where it left off.
5225  */
5226 static int iwl3945_load_bsm(struct iwl3945_priv *priv)
5227 {
5228         __le32 *image = priv->ucode_boot.v_addr;
5229         u32 len = priv->ucode_boot.len;
5230         dma_addr_t pinst;
5231         dma_addr_t pdata;
5232         u32 inst_len;
5233         u32 data_len;
5234         int rc;
5235         int i;
5236         u32 done;
5237         u32 reg_offset;
5238
5239         IWL_DEBUG_INFO("Begin load bsm\n");
5240
5241         /* make sure bootstrap program is no larger than BSM's SRAM size */
5242         if (len > IWL_MAX_BSM_SIZE)
5243                 return -EINVAL;
5244
5245         /* Tell bootstrap uCode where to find the "Initialize" uCode
5246          *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
5247          * NOTE:  iwl3945_initialize_alive_start() will replace these values,
5248          *        after the "initialize" uCode has run, to point to
5249          *        runtime/protocol instructions and backup data cache. */
5250         pinst = priv->ucode_init.p_addr;
5251         pdata = priv->ucode_init_data.p_addr;
5252         inst_len = priv->ucode_init.len;
5253         data_len = priv->ucode_init_data.len;
5254
5255         rc = iwl3945_grab_nic_access(priv);
5256         if (rc)
5257                 return rc;
5258
5259         iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5260         iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5261         iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5262         iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
5263
5264         /* Fill BSM memory with bootstrap instructions */
5265         for (reg_offset = BSM_SRAM_LOWER_BOUND;
5266              reg_offset < BSM_SRAM_LOWER_BOUND + len;
5267              reg_offset += sizeof(u32), image++)
5268                 _iwl3945_write_prph(priv, reg_offset,
5269                                           le32_to_cpu(*image));
5270
5271         rc = iwl3945_verify_bsm(priv);
5272         if (rc) {
5273                 iwl3945_release_nic_access(priv);
5274                 return rc;
5275         }
5276
5277         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
5278         iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5279         iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
5280                                  RTC_INST_LOWER_BOUND);
5281         iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
5282
5283         /* Load bootstrap code into instruction SRAM now,
5284          *   to prepare to load "initialize" uCode */
5285         iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
5286                 BSM_WR_CTRL_REG_BIT_START);
5287
5288         /* Wait for load of bootstrap uCode to finish */
5289         for (i = 0; i < 100; i++) {
5290                 done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
5291                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5292                         break;
5293                 udelay(10);
5294         }
5295         if (i < 100)
5296                 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
5297         else {
5298                 IWL_ERROR("BSM write did not complete!\n");
5299                 return -EIO;
5300         }
5301
5302         /* Enable future boot loads whenever power management unit triggers it
5303          *   (e.g. when powering back up after power-save shutdown) */
5304         iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
5305                 BSM_WR_CTRL_REG_BIT_START_EN);
5306
5307         iwl3945_release_nic_access(priv);
5308
5309         return 0;
5310 }
5311
5312 static void iwl3945_nic_start(struct iwl3945_priv *priv)
5313 {
5314         /* Remove all resets to allow NIC to operate */
5315         iwl3945_write32(priv, CSR_RESET, 0);
5316 }
5317
5318 /**
5319  * iwl3945_read_ucode - Read uCode images from disk file.
5320  *
5321  * Copy into buffers for card to fetch via bus-mastering
5322  */
5323 static int iwl3945_read_ucode(struct iwl3945_priv *priv)
5324 {
5325         struct iwl3945_ucode *ucode;
5326         int ret = 0;
5327         const struct firmware *ucode_raw;
5328         /* firmware file name contains uCode/driver compatibility version */
5329         const char *name = priv->cfg->fw_name;
5330         u8 *src;
5331         size_t len;
5332         u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
5333
5334         /* Ask kernel firmware_class module to get the boot firmware off disk.
5335          * request_firmware() is synchronous, file is in memory on return. */
5336         ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
5337         if (ret < 0) {
5338                 IWL_ERROR("%s firmware file req failed: Reason %d\n",
5339                                 name, ret);
5340                 goto error;
5341         }
5342
5343         IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
5344                        name, ucode_raw->size);
5345
5346         /* Make sure that we got at least our header! */
5347         if (ucode_raw->size < sizeof(*ucode)) {
5348                 IWL_ERROR("File size way too small!\n");
5349                 ret = -EINVAL;
5350                 goto err_release;
5351         }
5352
5353         /* Data from ucode file:  header followed by uCode images */
5354         ucode = (void *)ucode_raw->data;
5355
5356         ver = le32_to_cpu(ucode->ver);
5357         inst_size = le32_to_cpu(ucode->inst_size);
5358         data_size = le32_to_cpu(ucode->data_size);
5359         init_size = le32_to_cpu(ucode->init_size);
5360         init_data_size = le32_to_cpu(ucode->init_data_size);
5361         boot_size = le32_to_cpu(ucode->boot_size);
5362
5363         IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
5364         IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
5365         IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
5366         IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
5367         IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
5368         IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
5369
5370         /* Verify size of file vs. image size info in file's header */
5371         if (ucode_raw->size < sizeof(*ucode) +
5372                 inst_size + data_size + init_size +
5373                 init_data_size + boot_size) {
5374
5375                 IWL_DEBUG_INFO("uCode file size %d too small\n",
5376                                (int)ucode_raw->size);
5377                 ret = -EINVAL;
5378                 goto err_release;
5379         }
5380
5381         /* Verify that uCode images will fit in card's SRAM */
5382         if (inst_size > IWL_MAX_INST_SIZE) {
5383                 IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
5384                                inst_size);
5385                 ret = -EINVAL;
5386                 goto err_release;
5387         }
5388
5389         if (data_size > IWL_MAX_DATA_SIZE) {
5390                 IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
5391                                data_size);
5392                 ret = -EINVAL;
5393                 goto err_release;
5394         }
5395         if (init_size > IWL_MAX_INST_SIZE) {
5396                 IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
5397                                 init_size);
5398                 ret = -EINVAL;
5399                 goto err_release;
5400         }
5401         if (init_data_size > IWL_MAX_DATA_SIZE) {
5402                 IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
5403                                 init_data_size);
5404                 ret = -EINVAL;
5405                 goto err_release;
5406         }
5407         if (boot_size > IWL_MAX_BSM_SIZE) {
5408                 IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
5409                                 boot_size);
5410                 ret = -EINVAL;
5411                 goto err_release;
5412         }
5413
5414         /* Allocate ucode buffers for card's bus-master loading ... */
5415
5416         /* Runtime instructions and 2 copies of data:
5417          * 1) unmodified from disk
5418          * 2) backup cache for save/restore during power-downs */
5419         priv->ucode_code.len = inst_size;
5420         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
5421
5422         priv->ucode_data.len = data_size;
5423         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
5424
5425         priv->ucode_data_backup.len = data_size;
5426         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
5427
5428         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
5429             !priv->ucode_data_backup.v_addr)
5430                 goto err_pci_alloc;
5431
5432         /* Initialization instructions and data */
5433         if (init_size && init_data_size) {
5434                 priv->ucode_init.len = init_size;
5435                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
5436
5437                 priv->ucode_init_data.len = init_data_size;
5438                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
5439
5440                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
5441                         goto err_pci_alloc;
5442         }
5443
5444         /* Bootstrap (instructions only, no data) */
5445         if (boot_size) {
5446                 priv->ucode_boot.len = boot_size;
5447                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
5448
5449                 if (!priv->ucode_boot.v_addr)
5450                         goto err_pci_alloc;
5451         }
5452
5453         /* Copy images into buffers for card's bus-master reads ... */
5454
5455         /* Runtime instructions (first block of data in file) */
5456         src = &ucode->data[0];
5457         len = priv->ucode_code.len;
5458         IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
5459         memcpy(priv->ucode_code.v_addr, src, len);
5460         IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
5461                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
5462
5463         /* Runtime data (2nd block)
5464          * NOTE:  Copy into backup buffer will be done in iwl3945_up()  */
5465         src = &ucode->data[inst_size];
5466         len = priv->ucode_data.len;
5467         IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
5468         memcpy(priv->ucode_data.v_addr, src, len);
5469         memcpy(priv->ucode_data_backup.v_addr, src, len);
5470
5471         /* Initialization instructions (3rd block) */
5472         if (init_size) {
5473                 src = &ucode->data[inst_size + data_size];
5474                 len = priv->ucode_init.len;
5475                 IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
5476                                len);
5477                 memcpy(priv->ucode_init.v_addr, src, len);
5478         }
5479
5480         /* Initialization data (4th block) */
5481         if (init_data_size) {
5482                 src = &ucode->data[inst_size + data_size + init_size];
5483                 len = priv->ucode_init_data.len;
5484                 IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
5485                                (int)len);
5486                 memcpy(priv->ucode_init_data.v_addr, src, len);
5487         }
5488
5489         /* Bootstrap instructions (5th block) */
5490         src = &ucode->data[inst_size + data_size + init_size + init_data_size];
5491         len = priv->ucode_boot.len;
5492         IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
5493                        (int)len);
5494         memcpy(priv->ucode_boot.v_addr, src, len);
5495
5496         /* We have our copies now, allow OS release its copies */
5497         release_firmware(ucode_raw);
5498         return 0;
5499
5500  err_pci_alloc:
5501         IWL_ERROR("failed to allocate pci memory\n");
5502         ret = -ENOMEM;
5503         iwl3945_dealloc_ucode_pci(priv);
5504
5505  err_release:
5506         release_firmware(ucode_raw);
5507
5508  error:
5509         return ret;
5510 }
5511
5512
5513 /**
5514  * iwl3945_set_ucode_ptrs - Set uCode address location
5515  *
5516  * Tell initialization uCode where to find runtime uCode.
5517  *
5518  * BSM registers initially contain pointers to initialization uCode.
5519  * We need to replace them to load runtime uCode inst and data,
5520  * and to save runtime data when powering down.
5521  */
5522 static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
5523 {
5524         dma_addr_t pinst;
5525         dma_addr_t pdata;
5526         int rc = 0;
5527         unsigned long flags;
5528
5529         /* bits 31:0 for 3945 */
5530         pinst = priv->ucode_code.p_addr;
5531         pdata = priv->ucode_data_backup.p_addr;
5532
5533         spin_lock_irqsave(&priv->lock, flags);
5534         rc = iwl3945_grab_nic_access(priv);
5535         if (rc) {
5536                 spin_unlock_irqrestore(&priv->lock, flags);
5537                 return rc;
5538         }
5539
5540         /* Tell bootstrap uCode where to find image to load */
5541         iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5542         iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5543         iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
5544                                  priv->ucode_data.len);
5545
5546         /* Inst byte count must be last to set up, bit 31 signals uCode
5547          *   that all new ptr/size info is in place */
5548         iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
5549                                  priv->ucode_code.len | BSM_DRAM_INST_LOAD);
5550
5551         iwl3945_release_nic_access(priv);
5552
5553         spin_unlock_irqrestore(&priv->lock, flags);
5554
5555         IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
5556
5557         return rc;
5558 }
5559
5560 /**
5561  * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
5562  *
5563  * Called after REPLY_ALIVE notification received from "initialize" uCode.
5564  *
5565  * Tell "initialize" uCode to go ahead and load the runtime uCode.
5566  */
5567 static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
5568 {
5569         /* Check alive response for "valid" sign from uCode */
5570         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
5571                 /* We had an error bringing up the hardware, so take it
5572                  * all the way back down so we can try again */
5573                 IWL_DEBUG_INFO("Initialize Alive failed.\n");
5574                 goto restart;
5575         }
5576
5577         /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
5578          * This is a paranoid check, because we would not have gotten the
5579          * "initialize" alive if code weren't properly loaded.  */
5580         if (iwl3945_verify_ucode(priv)) {
5581                 /* Runtime instruction load was bad;
5582                  * take it all the way back down so we can try again */
5583                 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
5584                 goto restart;
5585         }
5586
5587         /* Send pointers to protocol/runtime uCode image ... init code will
5588          * load and launch runtime uCode, which will send us another "Alive"
5589          * notification. */
5590         IWL_DEBUG_INFO("Initialization Alive received.\n");
5591         if (iwl3945_set_ucode_ptrs(priv)) {
5592                 /* Runtime instruction load won't happen;
5593                  * take it all the way back down so we can try again */
5594                 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
5595                 goto restart;
5596         }
5597         return;
5598
5599  restart:
5600         queue_work(priv->workqueue, &priv->restart);
5601 }
5602
5603
5604 /**
5605  * iwl3945_alive_start - called after REPLY_ALIVE notification received
5606  *                   from protocol/runtime uCode (initialization uCode's
5607  *                   Alive gets handled by iwl3945_init_alive_start()).
5608  */
5609 static void iwl3945_alive_start(struct iwl3945_priv *priv)
5610 {
5611         int rc = 0;
5612         int thermal_spin = 0;
5613         u32 rfkill;
5614
5615         IWL_DEBUG_INFO("Runtime Alive received.\n");
5616
5617         if (priv->card_alive.is_valid != UCODE_VALID_OK) {
5618                 /* We had an error bringing up the hardware, so take it
5619                  * all the way back down so we can try again */
5620                 IWL_DEBUG_INFO("Alive failed.\n");
5621                 goto restart;
5622         }
5623
5624         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5625          * This is a paranoid check, because we would not have gotten the
5626          * "runtime" alive if code weren't properly loaded.  */
5627         if (iwl3945_verify_ucode(priv)) {
5628                 /* Runtime instruction load was bad;
5629                  * take it all the way back down so we can try again */
5630                 IWL_DEBUG_INFO("Bad runtime uCode load.\n");
5631                 goto restart;
5632         }
5633
5634         iwl3945_clear_stations_table(priv);
5635
5636         rc = iwl3945_grab_nic_access(priv);
5637         if (rc) {
5638                 IWL_WARNING("Can not read RFKILL status from adapter\n");
5639                 return;
5640         }
5641
5642         rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
5643         IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
5644         iwl3945_release_nic_access(priv);
5645
5646         if (rfkill & 0x1) {
5647                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5648                 /* if RFKILL is not on, then wait for thermal
5649                  * sensor in adapter to kick in */
5650                 while (iwl3945_hw_get_temperature(priv) == 0) {
5651                         thermal_spin++;
5652                         udelay(10);
5653                 }
5654
5655                 if (thermal_spin)
5656                         IWL_DEBUG_INFO("Thermal calibration took %dus\n",
5657                                        thermal_spin * 10);
5658         } else
5659                 set_bit(STATUS_RF_KILL_HW, &priv->status);
5660
5661         /* After the ALIVE response, we can send commands to 3945 uCode */
5662         set_bit(STATUS_ALIVE, &priv->status);
5663
5664         /* Clear out the uCode error bit if it is set */
5665         clear_bit(STATUS_FW_ERROR, &priv->status);
5666
5667         if (iwl3945_is_rfkill(priv))
5668                 return;
5669
5670         ieee80211_wake_queues(priv->hw);
5671
5672         priv->active_rate = priv->rates_mask;
5673         priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
5674
5675         iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
5676
5677         if (iwl3945_is_associated(priv)) {
5678                 struct iwl3945_rxon_cmd *active_rxon =
5679                                 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
5680
5681                 memcpy(&priv->staging_rxon, &priv->active_rxon,
5682                        sizeof(priv->staging_rxon));
5683                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5684         } else {
5685                 /* Initialize our rx_config data */
5686                 iwl3945_connection_init_rx_config(priv, priv->iw_mode);
5687                 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
5688         }
5689
5690         /* Configure Bluetooth device coexistence support */
5691         iwl3945_send_bt_config(priv);
5692
5693         /* Configure the adapter for unassociated operation */
5694         iwl3945_commit_rxon(priv);
5695
5696         iwl3945_reg_txpower_periodic(priv);
5697
5698         iwl3945_led_register(priv);
5699
5700         IWL_DEBUG_INFO("ALIVE processing complete.\n");
5701         set_bit(STATUS_READY, &priv->status);
5702         wake_up_interruptible(&priv->wait_command_queue);
5703
5704         if (priv->error_recovering)
5705                 iwl3945_error_recovery(priv);
5706
5707         return;
5708
5709  restart:
5710         queue_work(priv->workqueue, &priv->restart);
5711 }
5712
5713 static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
5714
5715 static void __iwl3945_down(struct iwl3945_priv *priv)
5716 {
5717         unsigned long flags;
5718         int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
5719         struct ieee80211_conf *conf = NULL;
5720
5721         IWL_DEBUG_INFO(DRV_NAME " is going down\n");
5722
5723         conf = ieee80211_get_hw_conf(priv->hw);
5724
5725         if (!exit_pending)
5726                 set_bit(STATUS_EXIT_PENDING, &priv->status);
5727
5728         iwl3945_led_unregister(priv);
5729         iwl3945_clear_stations_table(priv);
5730
5731         /* Unblock any waiting calls */
5732         wake_up_interruptible_all(&priv->wait_command_queue);
5733
5734         /* Wipe out the EXIT_PENDING status bit if we are not actually
5735          * exiting the module */
5736         if (!exit_pending)
5737                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
5738
5739         /* stop and reset the on-board processor */
5740         iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
5741
5742         /* tell the device to stop sending interrupts */
5743         spin_lock_irqsave(&priv->lock, flags);
5744         iwl3945_disable_interrupts(priv);
5745         spin_unlock_irqrestore(&priv->lock, flags);
5746         iwl_synchronize_irq(priv);
5747
5748         if (priv->mac80211_registered)
5749                 ieee80211_stop_queues(priv->hw);
5750
5751         /* If we have not previously called iwl3945_init() then
5752          * clear all bits but the RF Kill and SUSPEND bits and return */
5753         if (!iwl3945_is_init(priv)) {
5754                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5755                                         STATUS_RF_KILL_HW |
5756                                test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5757                                         STATUS_RF_KILL_SW |
5758                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5759                                         STATUS_GEO_CONFIGURED |
5760                                test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5761                                         STATUS_IN_SUSPEND |
5762                                 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5763                                         STATUS_EXIT_PENDING;
5764                 goto exit;
5765         }
5766
5767         /* ...otherwise clear out all the status bits but the RF Kill and
5768          * SUSPEND bits and continue taking the NIC down. */
5769         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
5770                                 STATUS_RF_KILL_HW |
5771                         test_bit(STATUS_RF_KILL_SW, &priv->status) <<
5772                                 STATUS_RF_KILL_SW |
5773                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
5774                                 STATUS_GEO_CONFIGURED |
5775                         test_bit(STATUS_IN_SUSPEND, &priv->status) <<
5776                                 STATUS_IN_SUSPEND |
5777                         test_bit(STATUS_FW_ERROR, &priv->status) <<
5778                                 STATUS_FW_ERROR |
5779                         test_bit(STATUS_EXIT_PENDING, &priv->status) <<
5780                                 STATUS_EXIT_PENDING;
5781
5782         spin_lock_irqsave(&priv->lock, flags);
5783         iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
5784         spin_unlock_irqrestore(&priv->lock, flags);
5785
5786         iwl3945_hw_txq_ctx_stop(priv);
5787         iwl3945_hw_rxq_stop(priv);
5788
5789         spin_lock_irqsave(&priv->lock, flags);
5790         if (!iwl3945_grab_nic_access(priv)) {
5791                 iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
5792                                          APMG_CLK_VAL_DMA_CLK_RQT);
5793                 iwl3945_release_nic_access(priv);
5794         }
5795         spin_unlock_irqrestore(&priv->lock, flags);
5796
5797         udelay(5);
5798
5799         iwl3945_hw_nic_stop_master(priv);
5800         iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
5801         iwl3945_hw_nic_reset(priv);
5802
5803  exit:
5804         memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
5805
5806         if (priv->ibss_beacon)
5807                 dev_kfree_skb(priv->ibss_beacon);
5808         priv->ibss_beacon = NULL;
5809
5810         /* clear out any free frames */
5811         iwl3945_clear_free_frames(priv);
5812 }
5813
5814 static void iwl3945_down(struct iwl3945_priv *priv)
5815 {
5816         mutex_lock(&priv->mutex);
5817         __iwl3945_down(priv);
5818         mutex_unlock(&priv->mutex);
5819
5820         iwl3945_cancel_deferred_work(priv);
5821 }
5822
5823 #define MAX_HW_RESTARTS 5
5824
5825 static int __iwl3945_up(struct iwl3945_priv *priv)
5826 {
5827         int rc, i;
5828
5829         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
5830                 IWL_WARNING("Exit pending; will not bring the NIC up\n");
5831                 return -EIO;
5832         }
5833
5834         if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
5835                 IWL_WARNING("Radio disabled by SW RF kill (module "
5836                             "parameter)\n");
5837                 return -ENODEV;
5838         }
5839
5840         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
5841                 IWL_ERROR("ucode not available for device bring up\n");
5842                 return -EIO;
5843         }
5844
5845         /* If platform's RF_KILL switch is NOT set to KILL */
5846         if (iwl3945_read32(priv, CSR_GP_CNTRL) &
5847                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5848                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
5849         else {
5850                 set_bit(STATUS_RF_KILL_HW, &priv->status);
5851                 if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
5852                         IWL_WARNING("Radio disabled by HW RF Kill switch\n");
5853                         return -ENODEV;
5854                 }
5855         }
5856
5857         iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
5858
5859         rc = iwl3945_hw_nic_init(priv);
5860         if (rc) {
5861                 IWL_ERROR("Unable to int nic\n");
5862                 return rc;
5863         }
5864
5865         /* make sure rfkill handshake bits are cleared */
5866         iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5867         iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
5868                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5869
5870         /* clear (again), then enable host interrupts */
5871         iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
5872         iwl3945_enable_interrupts(priv);
5873
5874         /* really make sure rfkill handshake bits are cleared */
5875         iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5876         iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5877
5878         /* Copy original ucode data image from disk into backup cache.
5879          * This will be used to initialize the on-board processor's
5880          * data SRAM for a clean start when the runtime program first loads. */
5881         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5882                priv->ucode_data.len);
5883
5884         /* We return success when we resume from suspend and rf_kill is on. */
5885         if (test_bit(STATUS_RF_KILL_HW, &priv->status))
5886                 return 0;
5887
5888         for (i = 0; i < MAX_HW_RESTARTS; i++) {
5889
5890                 iwl3945_clear_stations_table(priv);
5891
5892                 /* load bootstrap state machine,
5893                  * load bootstrap program into processor's memory,
5894                  * prepare to load the "initialize" uCode */
5895                 rc = iwl3945_load_bsm(priv);
5896
5897                 if (rc) {
5898                         IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
5899                         continue;
5900                 }
5901
5902                 /* start card; "initialize" will load runtime ucode */
5903                 iwl3945_nic_start(priv);
5904
5905                 IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
5906
5907                 return 0;
5908         }
5909
5910         set_bit(STATUS_EXIT_PENDING, &priv->status);
5911         __iwl3945_down(priv);
5912         clear_bit(STATUS_EXIT_PENDING, &priv->status);
5913
5914         /* tried to restart and config the device for as long as our
5915          * patience could withstand */
5916         IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
5917         return -EIO;
5918 }
5919
5920
5921 /*****************************************************************************
5922  *
5923  * Workqueue callbacks
5924  *
5925  *****************************************************************************/
5926
5927 static void iwl3945_bg_init_alive_start(struct work_struct *data)
5928 {
5929         struct iwl3945_priv *priv =
5930             container_of(data, struct iwl3945_priv, init_alive_start.work);
5931
5932         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5933                 return;
5934
5935         mutex_lock(&priv->mutex);
5936         iwl3945_init_alive_start(priv);
5937         mutex_unlock(&priv->mutex);
5938 }
5939
5940 static void iwl3945_bg_alive_start(struct work_struct *data)
5941 {
5942         struct iwl3945_priv *priv =
5943             container_of(data, struct iwl3945_priv, alive_start.work);
5944
5945         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5946                 return;
5947
5948         mutex_lock(&priv->mutex);
5949         iwl3945_alive_start(priv);
5950         mutex_unlock(&priv->mutex);
5951 }
5952
5953 static void iwl3945_bg_rf_kill(struct work_struct *work)
5954 {
5955         struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
5956
5957         wake_up_interruptible(&priv->wait_command_queue);
5958
5959         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
5960                 return;
5961
5962         mutex_lock(&priv->mutex);
5963
5964         if (!iwl3945_is_rfkill(priv)) {
5965                 IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
5966                           "HW and/or SW RF Kill no longer active, restarting "
5967                           "device\n");
5968                 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
5969                         queue_work(priv->workqueue, &priv->restart);
5970         } else {
5971
5972                 if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
5973                         IWL_DEBUG_RF_KILL("Can not turn radio back on - "
5974                                           "disabled by SW switch\n");
5975                 else
5976                         IWL_WARNING("Radio Frequency Kill Switch is On:\n"
5977                                     "Kill switch must be turned off for "
5978                                     "wireless networking to work.\n");
5979         }
5980
5981         mutex_unlock(&priv->mutex);
5982         iwl3945_rfkill_set_hw_state(priv);
5983 }
5984
5985 static void iwl3945_bg_set_monitor(struct work_struct *work)
5986 {
5987         struct iwl3945_priv *priv = container_of(work,
5988                                 struct iwl3945_priv, set_monitor);
5989
5990         IWL_DEBUG(IWL_DL_STATE, "setting monitor mode\n");
5991
5992         mutex_lock(&priv->mutex);
5993
5994         if (!iwl3945_is_ready(priv))
5995                 IWL_DEBUG(IWL_DL_STATE, "leave - not ready\n");
5996         else
5997                 if (iwl3945_set_mode(priv, NL80211_IFTYPE_MONITOR) != 0)
5998                         IWL_ERROR("iwl3945_set_mode() failed\n");
5999
6000         mutex_unlock(&priv->mutex);
6001 }
6002
6003 #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
6004
6005 static void iwl3945_bg_scan_check(struct work_struct *data)
6006 {
6007         struct iwl3945_priv *priv =
6008             container_of(data, struct iwl3945_priv, scan_check.work);
6009
6010         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
6011                 return;
6012
6013         mutex_lock(&priv->mutex);
6014         if (test_bit(STATUS_SCANNING, &priv->status) ||
6015             test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6016                 IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
6017                           "Scan completion watchdog resetting adapter (%dms)\n",
6018                           jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
6019
6020                 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
6021                         iwl3945_send_scan_abort(priv);
6022         }
6023         mutex_unlock(&priv->mutex);
6024 }
6025
6026 static void iwl3945_bg_request_scan(struct work_struct *data)
6027 {
6028         struct iwl3945_priv *priv =
6029             container_of(data, struct iwl3945_priv, request_scan);
6030         struct iwl3945_host_cmd cmd = {
6031                 .id = REPLY_SCAN_CMD,
6032                 .len = sizeof(struct iwl3945_scan_cmd),
6033                 .meta.flags = CMD_SIZE_HUGE,
6034         };
6035         int rc = 0;
6036         struct iwl3945_scan_cmd *scan;
6037         struct ieee80211_conf *conf = NULL;
6038         u8 n_probes = 2;
6039         enum ieee80211_band band;
6040         DECLARE_SSID_BUF(ssid);
6041
6042         conf = ieee80211_get_hw_conf(priv->hw);
6043
6044         mutex_lock(&priv->mutex);
6045
6046         if (!iwl3945_is_ready(priv)) {
6047                 IWL_WARNING("request scan called when driver not ready.\n");
6048                 goto done;
6049         }
6050
6051         /* Make sure the scan wasn't canceled before this queued work
6052          * was given the chance to run... */
6053         if (!test_bit(STATUS_SCANNING, &priv->status))
6054                 goto done;
6055
6056         /* This should never be called or scheduled if there is currently
6057          * a scan active in the hardware. */
6058         if (test_bit(STATUS_SCAN_HW, &priv->status)) {
6059                 IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
6060                                "Ignoring second request.\n");
6061                 rc = -EIO;
6062                 goto done;
6063         }
6064
6065         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
6066                 IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
6067                 goto done;
6068         }
6069
6070         if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
6071  &nbs