brcmsmac: implement ieee80211_ops get_tsf and set_tsf
[linux-3.10.git] / drivers / net / wireless / brcm80211 / brcmsmac / main.c
1 /*
2  * Copyright (c) 2010 Broadcom Corporation
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/pci_ids.h>
20 #include <linux/if_ether.h>
21 #include <net/cfg80211.h>
22 #include <net/mac80211.h>
23 #include <brcm_hw_ids.h>
24 #include <aiutils.h>
25 #include <chipcommon.h>
26 #include "rate.h"
27 #include "scb.h"
28 #include "phy/phy_hal.h"
29 #include "channel.h"
30 #include "antsel.h"
31 #include "stf.h"
32 #include "ampdu.h"
33 #include "mac80211_if.h"
34 #include "ucode_loader.h"
35 #include "main.h"
36 #include "soc.h"
37 #include "dma.h"
38 #include "debug.h"
39 #include "brcms_trace_events.h"
40
41 /* watchdog timer, in unit of ms */
42 #define TIMER_INTERVAL_WATCHDOG         1000
43 /* radio monitor timer, in unit of ms */
44 #define TIMER_INTERVAL_RADIOCHK         800
45
46 /* beacon interval, in unit of 1024TU */
47 #define BEACON_INTERVAL_DEFAULT         100
48
49 /* n-mode support capability */
50 /* 2x2 includes both 1x1 & 2x2 devices
51  * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
52  * control it independently
53  */
54 #define WL_11N_2x2                      1
55 #define WL_11N_3x3                      3
56 #define WL_11N_4x4                      4
57
58 #define EDCF_ACI_MASK                   0x60
59 #define EDCF_ACI_SHIFT                  5
60 #define EDCF_ECWMIN_MASK                0x0f
61 #define EDCF_ECWMAX_SHIFT               4
62 #define EDCF_AIFSN_MASK                 0x0f
63 #define EDCF_AIFSN_MAX                  15
64 #define EDCF_ECWMAX_MASK                0xf0
65
66 #define EDCF_AC_BE_TXOP_STA             0x0000
67 #define EDCF_AC_BK_TXOP_STA             0x0000
68 #define EDCF_AC_VO_ACI_STA              0x62
69 #define EDCF_AC_VO_ECW_STA              0x32
70 #define EDCF_AC_VI_ACI_STA              0x42
71 #define EDCF_AC_VI_ECW_STA              0x43
72 #define EDCF_AC_BK_ECW_STA              0xA4
73 #define EDCF_AC_VI_TXOP_STA             0x005e
74 #define EDCF_AC_VO_TXOP_STA             0x002f
75 #define EDCF_AC_BE_ACI_STA              0x03
76 #define EDCF_AC_BE_ECW_STA              0xA4
77 #define EDCF_AC_BK_ACI_STA              0x27
78 #define EDCF_AC_VO_TXOP_AP              0x002f
79
80 #define EDCF_TXOP2USEC(txop)            ((txop) << 5)
81 #define EDCF_ECW2CW(exp)                ((1 << (exp)) - 1)
82
83 #define APHY_SYMBOL_TIME                4
84 #define APHY_PREAMBLE_TIME              16
85 #define APHY_SIGNAL_TIME                4
86 #define APHY_SIFS_TIME                  16
87 #define APHY_SERVICE_NBITS              16
88 #define APHY_TAIL_NBITS                 6
89 #define BPHY_SIFS_TIME                  10
90 #define BPHY_PLCP_SHORT_TIME            96
91
92 #define PREN_PREAMBLE                   24
93 #define PREN_MM_EXT                     12
94 #define PREN_PREAMBLE_EXT               4
95
96 #define DOT11_MAC_HDR_LEN               24
97 #define DOT11_ACK_LEN                   10
98 #define DOT11_BA_LEN                    4
99 #define DOT11_OFDM_SIGNAL_EXTENSION     6
100 #define DOT11_MIN_FRAG_LEN              256
101 #define DOT11_RTS_LEN                   16
102 #define DOT11_CTS_LEN                   10
103 #define DOT11_BA_BITMAP_LEN             128
104 #define DOT11_MAXNUMFRAGS               16
105 #define DOT11_MAX_FRAG_LEN              2346
106
107 #define BPHY_PLCP_TIME                  192
108 #define RIFS_11N_TIME                   2
109
110 /* length of the BCN template area */
111 #define BCN_TMPL_LEN                    512
112
113 /* brcms_bss_info flag bit values */
114 #define BRCMS_BSS_HT                    0x0020  /* BSS is HT (MIMO) capable */
115
116 /* chip rx buffer offset */
117 #define BRCMS_HWRXOFF                   38
118
119 /* rfdisable delay timer 500 ms, runs of ALP clock */
120 #define RFDISABLE_DEFAULT               10000000
121
122 #define BRCMS_TEMPSENSE_PERIOD          10      /* 10 second timeout */
123
124 /* synthpu_dly times in us */
125 #define SYNTHPU_DLY_APHY_US             3700
126 #define SYNTHPU_DLY_BPHY_US             1050
127 #define SYNTHPU_DLY_NPHY_US             2048
128 #define SYNTHPU_DLY_LPPHY_US            300
129
130 #define ANTCNT                          10      /* vanilla M_MAX_ANTCNT val */
131
132 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
133 #define EDCF_SHORT_S                    0
134 #define EDCF_SFB_S                      4
135 #define EDCF_LONG_S                     8
136 #define EDCF_LFB_S                      12
137 #define EDCF_SHORT_M                    BITFIELD_MASK(4)
138 #define EDCF_SFB_M                      BITFIELD_MASK(4)
139 #define EDCF_LONG_M                     BITFIELD_MASK(4)
140 #define EDCF_LFB_M                      BITFIELD_MASK(4)
141
142 #define RETRY_SHORT_DEF                 7       /* Default Short retry Limit */
143 #define RETRY_SHORT_MAX                 255     /* Maximum Short retry Limit */
144 #define RETRY_LONG_DEF                  4       /* Default Long retry count */
145 #define RETRY_SHORT_FB                  3       /* Short count for fb rate */
146 #define RETRY_LONG_FB                   2       /* Long count for fb rate */
147
148 #define APHY_CWMIN                      15
149 #define PHY_CWMAX                       1023
150
151 #define EDCF_AIFSN_MIN                  1
152
153 #define FRAGNUM_MASK                    0xF
154
155 #define APHY_SLOT_TIME                  9
156 #define BPHY_SLOT_TIME                  20
157
158 #define WL_SPURAVOID_OFF                0
159 #define WL_SPURAVOID_ON1                1
160 #define WL_SPURAVOID_ON2                2
161
162 /* invalid core flags, use the saved coreflags */
163 #define BRCMS_USE_COREFLAGS             0xffffffff
164
165 /* values for PLCPHdr_override */
166 #define BRCMS_PLCP_AUTO                 -1
167 #define BRCMS_PLCP_SHORT                0
168 #define BRCMS_PLCP_LONG                 1
169
170 /* values for g_protection_override and n_protection_override */
171 #define BRCMS_PROTECTION_AUTO           -1
172 #define BRCMS_PROTECTION_OFF            0
173 #define BRCMS_PROTECTION_ON             1
174 #define BRCMS_PROTECTION_MMHDR_ONLY     2
175 #define BRCMS_PROTECTION_CTS_ONLY       3
176
177 /* values for g_protection_control and n_protection_control */
178 #define BRCMS_PROTECTION_CTL_OFF        0
179 #define BRCMS_PROTECTION_CTL_LOCAL      1
180 #define BRCMS_PROTECTION_CTL_OVERLAP    2
181
182 /* values for n_protection */
183 #define BRCMS_N_PROTECTION_OFF          0
184 #define BRCMS_N_PROTECTION_OPTIONAL     1
185 #define BRCMS_N_PROTECTION_20IN40       2
186 #define BRCMS_N_PROTECTION_MIXEDMODE    3
187
188 /* values for band specific 40MHz capabilities */
189 #define BRCMS_N_BW_20ALL                0
190 #define BRCMS_N_BW_40ALL                1
191 #define BRCMS_N_BW_20IN2G_40IN5G        2
192
193 /* bitflags for SGI support (sgi_rx iovar) */
194 #define BRCMS_N_SGI_20                  0x01
195 #define BRCMS_N_SGI_40                  0x02
196
197 /* defines used by the nrate iovar */
198 /* MSC in use,indicates b0-6 holds an mcs */
199 #define NRATE_MCS_INUSE                 0x00000080
200 /* rate/mcs value */
201 #define NRATE_RATE_MASK                 0x0000007f
202 /* stf mode mask: siso, cdd, stbc, sdm */
203 #define NRATE_STF_MASK                  0x0000ff00
204 /* stf mode shift */
205 #define NRATE_STF_SHIFT                 8
206 /* bit indicate to override mcs only */
207 #define NRATE_OVERRIDE_MCS_ONLY         0x40000000
208 #define NRATE_SGI_MASK                  0x00800000      /* sgi mode */
209 #define NRATE_SGI_SHIFT                 23              /* sgi mode */
210 #define NRATE_LDPC_CODING               0x00400000      /* adv coding in use */
211 #define NRATE_LDPC_SHIFT                22              /* ldpc shift */
212
213 #define NRATE_STF_SISO                  0               /* stf mode SISO */
214 #define NRATE_STF_CDD                   1               /* stf mode CDD */
215 #define NRATE_STF_STBC                  2               /* stf mode STBC */
216 #define NRATE_STF_SDM                   3               /* stf mode SDM */
217
218 #define MAX_DMA_SEGS                    4
219
220 /* # of entries in Tx FIFO */
221 #define NTXD                            64
222 /* Max # of entries in Rx FIFO based on 4kb page size */
223 #define NRXD                            256
224
225 /* Amount of headroom to leave in Tx FIFO */
226 #define TX_HEADROOM                     4
227
228 /* try to keep this # rbufs posted to the chip */
229 #define NRXBUFPOST                      32
230
231 /* max # frames to process in brcms_c_recv() */
232 #define RXBND                           8
233 /* max # tx status to process in wlc_txstatus() */
234 #define TXSBND                          8
235
236 /* brcmu_format_flags() bit description structure */
237 struct brcms_c_bit_desc {
238         u32 bit;
239         const char *name;
240 };
241
242 /*
243  * The following table lists the buffer memory allocated to xmt fifos in HW.
244  * the size is in units of 256bytes(one block), total size is HW dependent
245  * ucode has default fifo partition, sw can overwrite if necessary
246  *
247  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
248  * the twiki is updated before making changes.
249  */
250
251 /* Starting corerev for the fifo size table */
252 #define XMTFIFOTBL_STARTREV     17
253
254 struct d11init {
255         __le16 addr;
256         __le16 size;
257         __le32 value;
258 };
259
260 struct edcf_acparam {
261         u8 ACI;
262         u8 ECW;
263         u16 TXOP;
264 } __packed;
265
266 /* debug/trace */
267 uint brcm_msg_level;
268
269 /* TX FIFO number to WME/802.1E Access Category */
270 static const u8 wme_fifo2ac[] = {
271         IEEE80211_AC_BK,
272         IEEE80211_AC_BE,
273         IEEE80211_AC_VI,
274         IEEE80211_AC_VO,
275         IEEE80211_AC_BE,
276         IEEE80211_AC_BE
277 };
278
279 /* ieee80211 Access Category to TX FIFO number */
280 static const u8 wme_ac2fifo[] = {
281         TX_AC_VO_FIFO,
282         TX_AC_VI_FIFO,
283         TX_AC_BE_FIFO,
284         TX_AC_BK_FIFO
285 };
286
287 static const u16 xmtfifo_sz[][NFIFO] = {
288         /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
289         {20, 192, 192, 21, 17, 5},
290         /* corerev 18: */
291         {0, 0, 0, 0, 0, 0},
292         /* corerev 19: */
293         {0, 0, 0, 0, 0, 0},
294         /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
295         {20, 192, 192, 21, 17, 5},
296         /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
297         {9, 58, 22, 14, 14, 5},
298         /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
299         {20, 192, 192, 21, 17, 5},
300         /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
301         {20, 192, 192, 21, 17, 5},
302         /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
303         {9, 58, 22, 14, 14, 5},
304         /* corerev 25: */
305         {0, 0, 0, 0, 0, 0},
306         /* corerev 26: */
307         {0, 0, 0, 0, 0, 0},
308         /* corerev 27: */
309         {0, 0, 0, 0, 0, 0},
310         /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
311         {9, 58, 22, 14, 14, 5},
312 };
313
314 #ifdef DEBUG
315 static const char * const fifo_names[] = {
316         "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
317 #else
318 static const char fifo_names[6][0];
319 #endif
320
321 #ifdef DEBUG
322 /* pointer to most recently allocated wl/wlc */
323 static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
324 #endif
325
326 /* Mapping of ieee80211 AC numbers to tx fifos */
327 static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = {
328         [IEEE80211_AC_VO]       = TX_AC_VO_FIFO,
329         [IEEE80211_AC_VI]       = TX_AC_VI_FIFO,
330         [IEEE80211_AC_BE]       = TX_AC_BE_FIFO,
331         [IEEE80211_AC_BK]       = TX_AC_BK_FIFO,
332 };
333
334 /* Mapping of tx fifos to ieee80211 AC numbers */
335 static const u8 fifo_to_ac_mapping[IEEE80211_NUM_ACS] = {
336         [TX_AC_BK_FIFO] = IEEE80211_AC_BK,
337         [TX_AC_BE_FIFO] = IEEE80211_AC_BE,
338         [TX_AC_VI_FIFO] = IEEE80211_AC_VI,
339         [TX_AC_VO_FIFO] = IEEE80211_AC_VO,
340 };
341
342 static u8 brcms_ac_to_fifo(u8 ac)
343 {
344         if (ac >= ARRAY_SIZE(ac_to_fifo_mapping))
345                 return TX_AC_BE_FIFO;
346         return ac_to_fifo_mapping[ac];
347 }
348
349 static u8 brcms_fifo_to_ac(u8 fifo)
350 {
351         if (fifo >= ARRAY_SIZE(fifo_to_ac_mapping))
352                 return IEEE80211_AC_BE;
353         return fifo_to_ac_mapping[fifo];
354 }
355
356 /* Find basic rate for a given rate */
357 static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
358 {
359         if (is_mcs_rate(rspec))
360                 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
361                        .leg_ofdm];
362         return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
363 }
364
365 static u16 frametype(u32 rspec, u8 mimoframe)
366 {
367         if (is_mcs_rate(rspec))
368                 return mimoframe;
369         return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
370 }
371
372 /* currently the best mechanism for determining SIFS is the band in use */
373 static u16 get_sifs(struct brcms_band *band)
374 {
375         return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
376                                  BPHY_SIFS_TIME;
377 }
378
379 /*
380  * Detect Card removed.
381  * Even checking an sbconfig register read will not false trigger when the core
382  * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
383  * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
384  * reg with fixed 0/1 pattern (some platforms return all 0).
385  * If clocks are present, call the sb routine which will figure out if the
386  * device is removed.
387  */
388 static bool brcms_deviceremoved(struct brcms_c_info *wlc)
389 {
390         u32 macctrl;
391
392         if (!wlc->hw->clk)
393                 return ai_deviceremoved(wlc->hw->sih);
394         macctrl = bcma_read32(wlc->hw->d11core,
395                               D11REGOFFS(maccontrol));
396         return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
397 }
398
399 /* sum the individual fifo tx pending packet counts */
400 static int brcms_txpktpendtot(struct brcms_c_info *wlc)
401 {
402         int i;
403         int pending = 0;
404
405         for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
406                 if (wlc->hw->di[i])
407                         pending += dma_txpending(wlc->hw->di[i]);
408         return pending;
409 }
410
411 static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
412 {
413         return wlc->pub->_nbands > 1 && !wlc->bandlocked;
414 }
415
416 static int brcms_chspec_bw(u16 chanspec)
417 {
418         if (CHSPEC_IS40(chanspec))
419                 return BRCMS_40_MHZ;
420         if (CHSPEC_IS20(chanspec))
421                 return BRCMS_20_MHZ;
422
423         return BRCMS_10_MHZ;
424 }
425
426 static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
427 {
428         if (cfg == NULL)
429                 return;
430
431         kfree(cfg->current_bss);
432         kfree(cfg);
433 }
434
435 static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
436 {
437         if (wlc == NULL)
438                 return;
439
440         brcms_c_bsscfg_mfree(wlc->bsscfg);
441         kfree(wlc->pub);
442         kfree(wlc->modulecb);
443         kfree(wlc->default_bss);
444         kfree(wlc->protection);
445         kfree(wlc->stf);
446         kfree(wlc->bandstate[0]);
447         kfree(wlc->corestate->macstat_snapshot);
448         kfree(wlc->corestate);
449         kfree(wlc->hw->bandstate[0]);
450         kfree(wlc->hw);
451
452         /* free the wlc */
453         kfree(wlc);
454         wlc = NULL;
455 }
456
457 static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
458 {
459         struct brcms_bss_cfg *cfg;
460
461         cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
462         if (cfg == NULL)
463                 goto fail;
464
465         cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
466         if (cfg->current_bss == NULL)
467                 goto fail;
468
469         return cfg;
470
471  fail:
472         brcms_c_bsscfg_mfree(cfg);
473         return NULL;
474 }
475
476 static struct brcms_c_info *
477 brcms_c_attach_malloc(uint unit, uint *err, uint devid)
478 {
479         struct brcms_c_info *wlc;
480
481         wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
482         if (wlc == NULL) {
483                 *err = 1002;
484                 goto fail;
485         }
486
487         /* allocate struct brcms_c_pub state structure */
488         wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
489         if (wlc->pub == NULL) {
490                 *err = 1003;
491                 goto fail;
492         }
493         wlc->pub->wlc = wlc;
494
495         /* allocate struct brcms_hardware state structure */
496
497         wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
498         if (wlc->hw == NULL) {
499                 *err = 1005;
500                 goto fail;
501         }
502         wlc->hw->wlc = wlc;
503
504         wlc->hw->bandstate[0] =
505                 kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
506         if (wlc->hw->bandstate[0] == NULL) {
507                 *err = 1006;
508                 goto fail;
509         } else {
510                 int i;
511
512                 for (i = 1; i < MAXBANDS; i++)
513                         wlc->hw->bandstate[i] = (struct brcms_hw_band *)
514                             ((unsigned long)wlc->hw->bandstate[0] +
515                              (sizeof(struct brcms_hw_band) * i));
516         }
517
518         wlc->modulecb =
519                 kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
520         if (wlc->modulecb == NULL) {
521                 *err = 1009;
522                 goto fail;
523         }
524
525         wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
526         if (wlc->default_bss == NULL) {
527                 *err = 1010;
528                 goto fail;
529         }
530
531         wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
532         if (wlc->bsscfg == NULL) {
533                 *err = 1011;
534                 goto fail;
535         }
536
537         wlc->protection = kzalloc(sizeof(struct brcms_protection),
538                                   GFP_ATOMIC);
539         if (wlc->protection == NULL) {
540                 *err = 1016;
541                 goto fail;
542         }
543
544         wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
545         if (wlc->stf == NULL) {
546                 *err = 1017;
547                 goto fail;
548         }
549
550         wlc->bandstate[0] =
551                 kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
552         if (wlc->bandstate[0] == NULL) {
553                 *err = 1025;
554                 goto fail;
555         } else {
556                 int i;
557
558                 for (i = 1; i < MAXBANDS; i++)
559                         wlc->bandstate[i] = (struct brcms_band *)
560                                 ((unsigned long)wlc->bandstate[0]
561                                 + (sizeof(struct brcms_band)*i));
562         }
563
564         wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
565         if (wlc->corestate == NULL) {
566                 *err = 1026;
567                 goto fail;
568         }
569
570         wlc->corestate->macstat_snapshot =
571                 kzalloc(sizeof(struct macstat), GFP_ATOMIC);
572         if (wlc->corestate->macstat_snapshot == NULL) {
573                 *err = 1027;
574                 goto fail;
575         }
576
577         return wlc;
578
579  fail:
580         brcms_c_detach_mfree(wlc);
581         return NULL;
582 }
583
584 /*
585  * Update the slot timing for standard 11b/g (20us slots)
586  * or shortslot 11g (9us slots)
587  * The PSM needs to be suspended for this call.
588  */
589 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
590                                         bool shortslot)
591 {
592         struct bcma_device *core = wlc_hw->d11core;
593
594         if (shortslot) {
595                 /* 11g short slot: 11a timing */
596                 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
597                 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
598         } else {
599                 /* 11g long slot: 11b timing */
600                 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
601                 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
602         }
603 }
604
605 /*
606  * calculate frame duration of a given rate and length, return
607  * time in usec unit
608  */
609 static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
610                                     u8 preamble_type, uint mac_len)
611 {
612         uint nsyms, dur = 0, Ndps, kNdps;
613         uint rate = rspec2rate(ratespec);
614
615         if (rate == 0) {
616                 brcms_err(wlc->hw->d11core, "wl%d: WAR: using rate of 1 mbps\n",
617                           wlc->pub->unit);
618                 rate = BRCM_RATE_1M;
619         }
620
621         if (is_mcs_rate(ratespec)) {
622                 uint mcs = ratespec & RSPEC_RATE_MASK;
623                 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
624
625                 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
626                 if (preamble_type == BRCMS_MM_PREAMBLE)
627                         dur += PREN_MM_EXT;
628                 /* 1000Ndbps = kbps * 4 */
629                 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
630                                    rspec_issgi(ratespec)) * 4;
631
632                 if (rspec_stc(ratespec) == 0)
633                         nsyms =
634                             CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
635                                   APHY_TAIL_NBITS) * 1000, kNdps);
636                 else
637                         /* STBC needs to have even number of symbols */
638                         nsyms =
639                             2 *
640                             CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
641                                   APHY_TAIL_NBITS) * 1000, 2 * kNdps);
642
643                 dur += APHY_SYMBOL_TIME * nsyms;
644                 if (wlc->band->bandtype == BRCM_BAND_2G)
645                         dur += DOT11_OFDM_SIGNAL_EXTENSION;
646         } else if (is_ofdm_rate(rate)) {
647                 dur = APHY_PREAMBLE_TIME;
648                 dur += APHY_SIGNAL_TIME;
649                 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
650                 Ndps = rate * 2;
651                 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
652                 nsyms =
653                     CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
654                          Ndps);
655                 dur += APHY_SYMBOL_TIME * nsyms;
656                 if (wlc->band->bandtype == BRCM_BAND_2G)
657                         dur += DOT11_OFDM_SIGNAL_EXTENSION;
658         } else {
659                 /*
660                  * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
661                  * will divide out
662                  */
663                 mac_len = mac_len * 8 * 2;
664                 /* calc ceiling of bits/rate = microseconds of air time */
665                 dur = (mac_len + rate - 1) / rate;
666                 if (preamble_type & BRCMS_SHORT_PREAMBLE)
667                         dur += BPHY_PLCP_SHORT_TIME;
668                 else
669                         dur += BPHY_PLCP_TIME;
670         }
671         return dur;
672 }
673
674 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
675                                 const struct d11init *inits)
676 {
677         struct bcma_device *core = wlc_hw->d11core;
678         int i;
679         uint offset;
680         u16 size;
681         u32 value;
682
683         brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
684
685         for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
686                 size = le16_to_cpu(inits[i].size);
687                 offset = le16_to_cpu(inits[i].addr);
688                 value = le32_to_cpu(inits[i].value);
689                 if (size == 2)
690                         bcma_write16(core, offset, value);
691                 else if (size == 4)
692                         bcma_write32(core, offset, value);
693                 else
694                         break;
695         }
696 }
697
698 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
699 {
700         u8 idx;
701         u16 addr[] = {
702                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
703                 M_HOST_FLAGS5
704         };
705
706         for (idx = 0; idx < MHFMAX; idx++)
707                 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
708 }
709
710 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
711 {
712         struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
713
714         /* init microcode host flags */
715         brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
716
717         /* do band-specific ucode IHR, SHM, and SCR inits */
718         if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
719                 if (BRCMS_ISNPHY(wlc_hw->band))
720                         brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
721                 else
722                         brcms_err(wlc_hw->d11core,
723                                   "%s: wl%d: unsupported phy in corerev %d\n",
724                                   __func__, wlc_hw->unit,
725                                   wlc_hw->corerev);
726         } else {
727                 if (D11REV_IS(wlc_hw->corerev, 24)) {
728                         if (BRCMS_ISLCNPHY(wlc_hw->band))
729                                 brcms_c_write_inits(wlc_hw,
730                                                     ucode->d11lcn0bsinitvals24);
731                         else
732                                 brcms_err(wlc_hw->d11core,
733                                           "%s: wl%d: unsupported phy in core rev %d\n",
734                                           __func__, wlc_hw->unit,
735                                           wlc_hw->corerev);
736                 } else {
737                         brcms_err(wlc_hw->d11core,
738                                   "%s: wl%d: unsupported corerev %d\n",
739                                   __func__, wlc_hw->unit, wlc_hw->corerev);
740                 }
741         }
742 }
743
744 static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
745 {
746         struct bcma_device *core = wlc_hw->d11core;
747         u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
748
749         bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
750 }
751
752 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
753 {
754         brcms_dbg_info(wlc_hw->d11core, "wl%d: clk %d\n", wlc_hw->unit, clk);
755
756         wlc_hw->phyclk = clk;
757
758         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
759
760                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
761                                    (SICF_PRST | SICF_FGC));
762                 udelay(1);
763                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
764                 udelay(1);
765
766         } else {                /* take phy out of reset */
767
768                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
769                 udelay(1);
770                 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
771                 udelay(1);
772
773         }
774 }
775
776 /* low-level band switch utility routine */
777 static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
778 {
779         brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
780                            bandunit);
781
782         wlc_hw->band = wlc_hw->bandstate[bandunit];
783
784         /*
785          * BMAC_NOTE:
786          *   until we eliminate need for wlc->band refs in low level code
787          */
788         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
789
790         /* set gmode core flag */
791         if (wlc_hw->sbclk && !wlc_hw->noreset) {
792                 u32 gmode = 0;
793
794                 if (bandunit == 0)
795                         gmode = SICF_GMODE;
796
797                 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
798         }
799 }
800
801 /* switch to new band but leave it inactive */
802 static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
803 {
804         struct brcms_hardware *wlc_hw = wlc->hw;
805         u32 macintmask;
806         u32 macctrl;
807
808         brcms_dbg_mac80211(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
809         macctrl = bcma_read32(wlc_hw->d11core,
810                               D11REGOFFS(maccontrol));
811         WARN_ON((macctrl & MCTL_EN_MAC) != 0);
812
813         /* disable interrupts */
814         macintmask = brcms_intrsoff(wlc->wl);
815
816         /* radio off */
817         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
818
819         brcms_b_core_phy_clk(wlc_hw, OFF);
820
821         brcms_c_setxband(wlc_hw, bandunit);
822
823         return macintmask;
824 }
825
826 /* process an individual struct tx_status */
827 static bool
828 brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
829 {
830         struct sk_buff *p = NULL;
831         uint queue = NFIFO;
832         struct dma_pub *dma = NULL;
833         struct d11txh *txh = NULL;
834         struct scb *scb = NULL;
835         bool free_pdu;
836         int tx_rts, tx_frame_count, tx_rts_count;
837         uint totlen, supr_status;
838         bool lastframe;
839         struct ieee80211_hdr *h;
840         u16 mcl;
841         struct ieee80211_tx_info *tx_info;
842         struct ieee80211_tx_rate *txrate;
843         int i;
844         bool fatal = true;
845
846         trace_brcms_txstatus(&wlc->hw->d11core->dev, txs->framelen,
847                              txs->frameid, txs->status, txs->lasttxtime,
848                              txs->sequence, txs->phyerr, txs->ackphyrxsh);
849
850         /* discard intermediate indications for ucode with one legitimate case:
851          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
852          *   but the subsequent tx of DATA failed. so it will start rts/cts
853          *   from the beginning (resetting the rts transmission count)
854          */
855         if (!(txs->status & TX_STATUS_AMPDU)
856             && (txs->status & TX_STATUS_INTERMEDIATE)) {
857                 brcms_dbg_tx(wlc->hw->d11core, "INTERMEDIATE but not AMPDU\n");
858                 fatal = false;
859                 goto out;
860         }
861
862         queue = txs->frameid & TXFID_QUEUE_MASK;
863         if (queue >= NFIFO) {
864                 brcms_err(wlc->hw->d11core, "queue %u >= NFIFO\n", queue);
865                 goto out;
866         }
867
868         dma = wlc->hw->di[queue];
869
870         p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
871         if (p == NULL) {
872                 brcms_err(wlc->hw->d11core, "dma_getnexttxp returned null!\n");
873                 goto out;
874         }
875
876         txh = (struct d11txh *) (p->data);
877         mcl = le16_to_cpu(txh->MacTxControlLow);
878
879         if (txs->phyerr)
880                 brcms_err(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n",
881                           txs->phyerr, txh->MainRates);
882
883         if (txs->frameid != le16_to_cpu(txh->TxFrameID)) {
884                 brcms_err(wlc->hw->d11core, "frameid != txh->TxFrameID\n");
885                 goto out;
886         }
887         tx_info = IEEE80211_SKB_CB(p);
888         h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
889
890         if (tx_info->rate_driver_data[0])
891                 scb = &wlc->pri_scb;
892
893         if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
894                 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
895                 fatal = false;
896                 goto out;
897         }
898
899         /*
900          * brcms_c_ampdu_dotxstatus() will trace tx descriptors for AMPDU
901          * frames; this traces them for the rest.
902          */
903         trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, sizeof(*txh));
904
905         supr_status = txs->status & TX_STATUS_SUPR_MASK;
906         if (supr_status == TX_STATUS_SUPR_BADCH) {
907                 unsigned xfts = le16_to_cpu(txh->XtraFrameTypes);
908                 brcms_dbg_tx(wlc->hw->d11core,
909                              "Pkt tx suppressed, dest chan %u, current %d\n",
910                              (xfts >> XFTS_CHANNEL_SHIFT) & 0xff,
911                              CHSPEC_CHANNEL(wlc->default_bss->chanspec));
912         }
913
914         tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
915         tx_frame_count =
916             (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
917         tx_rts_count =
918             (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
919
920         lastframe = !ieee80211_has_morefrags(h->frame_control);
921
922         if (!lastframe) {
923                 brcms_err(wlc->hw->d11core, "Not last frame!\n");
924         } else {
925                 /*
926                  * Set information to be consumed by Minstrel ht.
927                  *
928                  * The "fallback limit" is the number of tx attempts a given
929                  * MPDU is sent at the "primary" rate. Tx attempts beyond that
930                  * limit are sent at the "secondary" rate.
931                  * A 'short frame' does not exceed RTS treshold.
932                  */
933                 u16 sfbl,       /* Short Frame Rate Fallback Limit */
934                     lfbl,       /* Long Frame Rate Fallback Limit */
935                     fbl;
936
937                 if (queue < IEEE80211_NUM_ACS) {
938                         sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
939                                       EDCF_SFB);
940                         lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
941                                       EDCF_LFB);
942                 } else {
943                         sfbl = wlc->SFBL;
944                         lfbl = wlc->LFBL;
945                 }
946
947                 txrate = tx_info->status.rates;
948                 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
949                         fbl = lfbl;
950                 else
951                         fbl = sfbl;
952
953                 ieee80211_tx_info_clear_status(tx_info);
954
955                 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
956                         /*
957                          * rate selection requested a fallback rate
958                          * and we used it
959                          */
960                         txrate[0].count = fbl;
961                         txrate[1].count = tx_frame_count - fbl;
962                 } else {
963                         /*
964                          * rate selection did not request fallback rate, or
965                          * we didn't need it
966                          */
967                         txrate[0].count = tx_frame_count;
968                         /*
969                          * rc80211_minstrel.c:minstrel_tx_status() expects
970                          * unused rates to be marked with idx = -1
971                          */
972                         txrate[1].idx = -1;
973                         txrate[1].count = 0;
974                 }
975
976                 /* clear the rest of the rates */
977                 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
978                         txrate[i].idx = -1;
979                         txrate[i].count = 0;
980                 }
981
982                 if (txs->status & TX_STATUS_ACK_RCV)
983                         tx_info->flags |= IEEE80211_TX_STAT_ACK;
984         }
985
986         totlen = p->len;
987         free_pdu = true;
988
989         if (lastframe) {
990                 /* remove PLCP & Broadcom tx descriptor header */
991                 skb_pull(p, D11_PHY_HDR_LEN);
992                 skb_pull(p, D11_TXH_LEN);
993                 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
994         } else {
995                 brcms_err(wlc->hw->d11core,
996                           "%s: Not last frame => not calling tx_status\n",
997                           __func__);
998         }
999
1000         fatal = false;
1001
1002  out:
1003         if (fatal) {
1004                 if (txh)
1005                         trace_brcms_txdesc(&wlc->hw->d11core->dev, txh,
1006                                            sizeof(*txh));
1007                 if (p)
1008                         brcmu_pkt_buf_free_skb(p);
1009         }
1010
1011         if (dma && queue < NFIFO) {
1012                 u16 ac_queue = brcms_fifo_to_ac(queue);
1013                 if (dma->txavail > TX_HEADROOM && queue < TX_BCMC_FIFO &&
1014                     ieee80211_queue_stopped(wlc->pub->ieee_hw, ac_queue))
1015                         ieee80211_wake_queue(wlc->pub->ieee_hw, ac_queue);
1016                 dma_kick_tx(dma);
1017         }
1018
1019         return fatal;
1020 }
1021
1022 /* process tx completion events in BMAC
1023  * Return true if more tx status need to be processed. false otherwise.
1024  */
1025 static bool
1026 brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
1027 {
1028         struct bcma_device *core;
1029         struct tx_status txstatus, *txs;
1030         u32 s1, s2;
1031         uint n = 0;
1032         /*
1033          * Param 'max_tx_num' indicates max. # tx status to process before
1034          * break out.
1035          */
1036         uint max_tx_num = bound ? TXSBND : -1;
1037
1038         txs = &txstatus;
1039         core = wlc_hw->d11core;
1040         *fatal = false;
1041
1042         while (n < max_tx_num) {
1043                 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1044                 if (s1 == 0xffffffff) {
1045                         brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
1046                                   __func__);
1047                         *fatal = true;
1048                         return false;
1049                 }
1050                 /* only process when valid */
1051                 if (!(s1 & TXS_V))
1052                         break;
1053
1054                 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
1055                 txs->status = s1 & TXS_STATUS_MASK;
1056                 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
1057                 txs->sequence = s2 & TXS_SEQ_MASK;
1058                 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
1059                 txs->lasttxtime = 0;
1060
1061                 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1062                 if (*fatal == true)
1063                         return false;
1064                 n++;
1065         }
1066
1067         return n >= max_tx_num;
1068 }
1069
1070 static void brcms_c_tbtt(struct brcms_c_info *wlc)
1071 {
1072         if (!wlc->bsscfg->BSS)
1073                 /*
1074                  * DirFrmQ is now valid...defer setting until end
1075                  * of ATIM window
1076                  */
1077                 wlc->qvalid |= MCMD_DIRFRMQVAL;
1078 }
1079
1080 /* set initial host flags value */
1081 static void
1082 brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1083 {
1084         struct brcms_hardware *wlc_hw = wlc->hw;
1085
1086         memset(mhfs, 0, MHFMAX * sizeof(u16));
1087
1088         mhfs[MHF2] |= mhf2_init;
1089
1090         /* prohibit use of slowclock on multifunction boards */
1091         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1092                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1093
1094         if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1095                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1096                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1097         }
1098 }
1099
1100 static uint
1101 dmareg(uint direction, uint fifonum)
1102 {
1103         if (direction == DMA_TX)
1104                 return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
1105         return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
1106 }
1107
1108 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
1109 {
1110         uint i;
1111         char name[8];
1112         /*
1113          * ucode host flag 2 needed for pio mode, independent of band and fifo
1114          */
1115         u16 pio_mhf2 = 0;
1116         struct brcms_hardware *wlc_hw = wlc->hw;
1117         uint unit = wlc_hw->unit;
1118
1119         /* name and offsets for dma_attach */
1120         snprintf(name, sizeof(name), "wl%d", unit);
1121
1122         if (wlc_hw->di[0] == NULL) {    /* Init FIFOs */
1123                 int dma_attach_err = 0;
1124
1125                 /*
1126                  * FIFO 0
1127                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1128                  * RX: RX_FIFO (RX data packets)
1129                  */
1130                 wlc_hw->di[0] = dma_attach(name, wlc,
1131                                            (wme ? dmareg(DMA_TX, 0) : 0),
1132                                            dmareg(DMA_RX, 0),
1133                                            (wme ? NTXD : 0), NRXD,
1134                                            RXBUFSZ, -1, NRXBUFPOST,
1135                                            BRCMS_HWRXOFF);
1136                 dma_attach_err |= (NULL == wlc_hw->di[0]);
1137
1138                 /*
1139                  * FIFO 1
1140                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1141                  *   (legacy) TX_DATA_FIFO (TX data packets)
1142                  * RX: UNUSED
1143                  */
1144                 wlc_hw->di[1] = dma_attach(name, wlc,
1145                                            dmareg(DMA_TX, 1), 0,
1146                                            NTXD, 0, 0, -1, 0, 0);
1147                 dma_attach_err |= (NULL == wlc_hw->di[1]);
1148
1149                 /*
1150                  * FIFO 2
1151                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1152                  * RX: UNUSED
1153                  */
1154                 wlc_hw->di[2] = dma_attach(name, wlc,
1155                                            dmareg(DMA_TX, 2), 0,
1156                                            NTXD, 0, 0, -1, 0, 0);
1157                 dma_attach_err |= (NULL == wlc_hw->di[2]);
1158                 /*
1159                  * FIFO 3
1160                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1161                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1162                  */
1163                 wlc_hw->di[3] = dma_attach(name, wlc,
1164                                            dmareg(DMA_TX, 3),
1165                                            0, NTXD, 0, 0, -1,
1166                                            0, 0);
1167                 dma_attach_err |= (NULL == wlc_hw->di[3]);
1168 /* Cleaner to leave this as if with AP defined */
1169
1170                 if (dma_attach_err) {
1171                         brcms_err(wlc_hw->d11core,
1172                                   "wl%d: wlc_attach: dma_attach failed\n",
1173                                   unit);
1174                         return false;
1175                 }
1176
1177                 /* get pointer to dma engine tx flow control variable */
1178                 for (i = 0; i < NFIFO; i++)
1179                         if (wlc_hw->di[i])
1180                                 wlc_hw->txavail[i] =
1181                                     (uint *) dma_getvar(wlc_hw->di[i],
1182                                                         "&txavail");
1183         }
1184
1185         /* initial ucode host flags */
1186         brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1187
1188         return true;
1189 }
1190
1191 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1192 {
1193         uint j;
1194
1195         for (j = 0; j < NFIFO; j++) {
1196                 if (wlc_hw->di[j]) {
1197                         dma_detach(wlc_hw->di[j]);
1198                         wlc_hw->di[j] = NULL;
1199                 }
1200         }
1201 }
1202
1203 /*
1204  * Initialize brcms_c_info default values ...
1205  * may get overrides later in this function
1206  *  BMAC_NOTES, move low out and resolve the dangling ones
1207  */
1208 static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1209 {
1210         struct brcms_c_info *wlc = wlc_hw->wlc;
1211
1212         /* set default sw macintmask value */
1213         wlc->defmacintmask = DEF_MACINTMASK;
1214
1215         /* various 802.11g modes */
1216         wlc_hw->shortslot = false;
1217
1218         wlc_hw->SFBL = RETRY_SHORT_FB;
1219         wlc_hw->LFBL = RETRY_LONG_FB;
1220
1221         /* default mac retry limits */
1222         wlc_hw->SRL = RETRY_SHORT_DEF;
1223         wlc_hw->LRL = RETRY_LONG_DEF;
1224         wlc_hw->chanspec = ch20mhz_chspec(1);
1225 }
1226
1227 static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1228 {
1229         /* delay before first read of ucode state */
1230         udelay(40);
1231
1232         /* wait until ucode is no longer asleep */
1233         SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1234                   DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1235 }
1236
1237 /* control chip clock to save power, enable dynamic clock or force fast clock */
1238 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
1239 {
1240         if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1241                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1242                  * on backplane, but mac core will still run on ALP(not HT) when
1243                  * it enters powersave mode, which means the FCA bit may not be
1244                  * set. Should wakeup mac if driver wants it to run on HT.
1245                  */
1246
1247                 if (wlc_hw->clk) {
1248                         if (mode == BCMA_CLKMODE_FAST) {
1249                                 bcma_set32(wlc_hw->d11core,
1250                                            D11REGOFFS(clk_ctl_st),
1251                                            CCS_FORCEHT);
1252
1253                                 udelay(64);
1254
1255                                 SPINWAIT(
1256                                     ((bcma_read32(wlc_hw->d11core,
1257                                       D11REGOFFS(clk_ctl_st)) &
1258                                       CCS_HTAVAIL) == 0),
1259                                       PMU_MAX_TRANSITION_DLY);
1260                                 WARN_ON(!(bcma_read32(wlc_hw->d11core,
1261                                         D11REGOFFS(clk_ctl_st)) &
1262                                         CCS_HTAVAIL));
1263                         } else {
1264                                 if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1265                                     (bcma_read32(wlc_hw->d11core,
1266                                         D11REGOFFS(clk_ctl_st)) &
1267                                         (CCS_FORCEHT | CCS_HTAREQ)))
1268                                         SPINWAIT(
1269                                             ((bcma_read32(wlc_hw->d11core,
1270                                               offsetof(struct d11regs,
1271                                                        clk_ctl_st)) &
1272                                               CCS_HTAVAIL) == 0),
1273                                               PMU_MAX_TRANSITION_DLY);
1274                                 bcma_mask32(wlc_hw->d11core,
1275                                         D11REGOFFS(clk_ctl_st),
1276                                         ~CCS_FORCEHT);
1277                         }
1278                 }
1279                 wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
1280         } else {
1281
1282                 /* old chips w/o PMU, force HT through cc,
1283                  * then use FCA to verify mac is running fast clock
1284                  */
1285
1286                 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1287
1288                 /* check fast clock is available (if core is not in reset) */
1289                 if (wlc_hw->forcefastclk && wlc_hw->clk)
1290                         WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
1291                                   SISF_FCLKA));
1292
1293                 /*
1294                  * keep the ucode wake bit on if forcefastclk is on since we
1295                  * do not want ucode to put us back to slow clock when it dozes
1296                  * for PM mode. Code below matches the wake override bit with
1297                  * current forcefastclk state. Only setting bit in wake_override
1298                  * instead of waking ucode immediately since old code had this
1299                  * behavior. Older code set wlc->forcefastclk but only had the
1300                  * wake happen if the wakup_ucode work (protected by an up
1301                  * check) was executed just below.
1302                  */
1303                 if (wlc_hw->forcefastclk)
1304                         mboolset(wlc_hw->wake_override,
1305                                  BRCMS_WAKE_OVERRIDE_FORCEFAST);
1306                 else
1307                         mboolclr(wlc_hw->wake_override,
1308                                  BRCMS_WAKE_OVERRIDE_FORCEFAST);
1309         }
1310 }
1311
1312 /* set or clear ucode host flag bits
1313  * it has an optimization for no-change write
1314  * it only writes through shared memory when the core has clock;
1315  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1316  *
1317  *
1318  * bands values are: BRCM_BAND_AUTO <--- Current band only
1319  *                   BRCM_BAND_5G   <--- 5G band only
1320  *                   BRCM_BAND_2G   <--- 2G band only
1321  *                   BRCM_BAND_ALL  <--- All bands
1322  */
1323 void
1324 brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1325              int bands)
1326 {
1327         u16 save;
1328         u16 addr[MHFMAX] = {
1329                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1330                 M_HOST_FLAGS5
1331         };
1332         struct brcms_hw_band *band;
1333
1334         if ((val & ~mask) || idx >= MHFMAX)
1335                 return; /* error condition */
1336
1337         switch (bands) {
1338                 /* Current band only or all bands,
1339                  * then set the band to current band
1340                  */
1341         case BRCM_BAND_AUTO:
1342         case BRCM_BAND_ALL:
1343                 band = wlc_hw->band;
1344                 break;
1345         case BRCM_BAND_5G:
1346                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1347                 break;
1348         case BRCM_BAND_2G:
1349                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1350                 break;
1351         default:
1352                 band = NULL;    /* error condition */
1353         }
1354
1355         if (band) {
1356                 save = band->mhfs[idx];
1357                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1358
1359                 /* optimization: only write through if changed, and
1360                  * changed band is the current band
1361                  */
1362                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1363                     && (band == wlc_hw->band))
1364                         brcms_b_write_shm(wlc_hw, addr[idx],
1365                                            (u16) band->mhfs[idx]);
1366         }
1367
1368         if (bands == BRCM_BAND_ALL) {
1369                 wlc_hw->bandstate[0]->mhfs[idx] =
1370                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1371                 wlc_hw->bandstate[1]->mhfs[idx] =
1372                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1373         }
1374 }
1375
1376 /* set the maccontrol register to desired reset state and
1377  * initialize the sw cache of the register
1378  */
1379 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1380 {
1381         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1382         wlc_hw->maccontrol = 0;
1383         wlc_hw->suspended_fifos = 0;
1384         wlc_hw->wake_override = 0;
1385         wlc_hw->mute_override = 0;
1386         brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1387 }
1388
1389 /*
1390  * write the software state of maccontrol and
1391  * overrides to the maccontrol register
1392  */
1393 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1394 {
1395         u32 maccontrol = wlc_hw->maccontrol;
1396
1397         /* OR in the wake bit if overridden */
1398         if (wlc_hw->wake_override)
1399                 maccontrol |= MCTL_WAKE;
1400
1401         /* set AP and INFRA bits for mute if needed */
1402         if (wlc_hw->mute_override) {
1403                 maccontrol &= ~(MCTL_AP);
1404                 maccontrol |= MCTL_INFRA;
1405         }
1406
1407         bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1408                      maccontrol);
1409 }
1410
1411 /* set or clear maccontrol bits */
1412 void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1413 {
1414         u32 maccontrol;
1415         u32 new_maccontrol;
1416
1417         if (val & ~mask)
1418                 return; /* error condition */
1419         maccontrol = wlc_hw->maccontrol;
1420         new_maccontrol = (maccontrol & ~mask) | val;
1421
1422         /* if the new maccontrol value is the same as the old, nothing to do */
1423         if (new_maccontrol == maccontrol)
1424                 return;
1425
1426         /* something changed, cache the new value */
1427         wlc_hw->maccontrol = new_maccontrol;
1428
1429         /* write the new values with overrides applied */
1430         brcms_c_mctrl_write(wlc_hw);
1431 }
1432
1433 void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1434                                  u32 override_bit)
1435 {
1436         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1437                 mboolset(wlc_hw->wake_override, override_bit);
1438                 return;
1439         }
1440
1441         mboolset(wlc_hw->wake_override, override_bit);
1442
1443         brcms_c_mctrl_write(wlc_hw);
1444         brcms_b_wait_for_wake(wlc_hw);
1445 }
1446
1447 void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1448                                    u32 override_bit)
1449 {
1450         mboolclr(wlc_hw->wake_override, override_bit);
1451
1452         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1453                 return;
1454
1455         brcms_c_mctrl_write(wlc_hw);
1456 }
1457
1458 /* When driver needs ucode to stop beaconing, it has to make sure that
1459  * MCTL_AP is clear and MCTL_INFRA is set
1460  * Mode           MCTL_AP        MCTL_INFRA
1461  * AP                1              1
1462  * STA               0              1 <--- This will ensure no beacons
1463  * IBSS              0              0
1464  */
1465 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1466 {
1467         wlc_hw->mute_override = 1;
1468
1469         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1470          * override, then there is no change to write
1471          */
1472         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1473                 return;
1474
1475         brcms_c_mctrl_write(wlc_hw);
1476 }
1477
1478 /* Clear the override on AP and INFRA bits */
1479 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1480 {
1481         if (wlc_hw->mute_override == 0)
1482                 return;
1483
1484         wlc_hw->mute_override = 0;
1485
1486         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1487          * override, then there is no change to write
1488          */
1489         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1490                 return;
1491
1492         brcms_c_mctrl_write(wlc_hw);
1493 }
1494
1495 /*
1496  * Write a MAC address to the given match reg offset in the RXE match engine.
1497  */
1498 static void
1499 brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1500                        const u8 *addr)
1501 {
1502         struct bcma_device *core = wlc_hw->d11core;
1503         u16 mac_l;
1504         u16 mac_m;
1505         u16 mac_h;
1506
1507         brcms_dbg_rx(core, "wl%d: brcms_b_set_addrmatch\n", wlc_hw->unit);
1508
1509         mac_l = addr[0] | (addr[1] << 8);
1510         mac_m = addr[2] | (addr[3] << 8);
1511         mac_h = addr[4] | (addr[5] << 8);
1512
1513         /* enter the MAC addr into the RXE match registers */
1514         bcma_write16(core, D11REGOFFS(rcm_ctl),
1515                      RCM_INC_DATA | match_reg_offset);
1516         bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
1517         bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
1518         bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
1519 }
1520
1521 void
1522 brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1523                             void *buf)
1524 {
1525         struct bcma_device *core = wlc_hw->d11core;
1526         u32 word;
1527         __le32 word_le;
1528         __be32 word_be;
1529         bool be_bit;
1530         brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
1531
1532         bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
1533
1534         /* if MCTL_BIGEND bit set in mac control register,
1535          * the chip swaps data in fifo, as well as data in
1536          * template ram
1537          */
1538         be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
1539
1540         while (len > 0) {
1541                 memcpy(&word, buf, sizeof(u32));
1542
1543                 if (be_bit) {
1544                         word_be = cpu_to_be32(word);
1545                         word = *(u32 *)&word_be;
1546                 } else {
1547                         word_le = cpu_to_le32(word);
1548                         word = *(u32 *)&word_le;
1549                 }
1550
1551                 bcma_write32(core, D11REGOFFS(tplatewrdata), word);
1552
1553                 buf = (u8 *) buf + sizeof(u32);
1554                 len -= sizeof(u32);
1555         }
1556 }
1557
1558 static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1559 {
1560         wlc_hw->band->CWmin = newmin;
1561
1562         bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1563                      OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1564         (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1565         bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1566 }
1567
1568 static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1569 {
1570         wlc_hw->band->CWmax = newmax;
1571
1572         bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1573                      OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1574         (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1575         bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1576 }
1577
1578 void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1579 {
1580         bool fastclk;
1581
1582         /* request FAST clock if not on */
1583         fastclk = wlc_hw->forcefastclk;
1584         if (!fastclk)
1585                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1586
1587         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1588
1589         brcms_b_phy_reset(wlc_hw);
1590         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1591
1592         /* restore the clk */
1593         if (!fastclk)
1594                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1595 }
1596
1597 static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1598 {
1599         u16 v;
1600         struct brcms_c_info *wlc = wlc_hw->wlc;
1601         /* update SYNTHPU_DLY */
1602
1603         if (BRCMS_ISLCNPHY(wlc->band))
1604                 v = SYNTHPU_DLY_LPPHY_US;
1605         else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
1606                 v = SYNTHPU_DLY_NPHY_US;
1607         else
1608                 v = SYNTHPU_DLY_BPHY_US;
1609
1610         brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1611 }
1612
1613 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1614 {
1615         u16 phyctl;
1616         u16 phytxant = wlc_hw->bmac_phytxant;
1617         u16 mask = PHY_TXC_ANT_MASK;
1618
1619         /* set the Probe Response frame phy control word */
1620         phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1621         phyctl = (phyctl & ~mask) | phytxant;
1622         brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1623
1624         /* set the Response (ACK/CTS) frame phy control word */
1625         phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1626         phyctl = (phyctl & ~mask) | phytxant;
1627         brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1628 }
1629
1630 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1631                                          u8 rate)
1632 {
1633         uint i;
1634         u8 plcp_rate = 0;
1635         struct plcp_signal_rate_lookup {
1636                 u8 rate;
1637                 u8 signal_rate;
1638         };
1639         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1640         const struct plcp_signal_rate_lookup rate_lookup[] = {
1641                 {BRCM_RATE_6M, 0xB},
1642                 {BRCM_RATE_9M, 0xF},
1643                 {BRCM_RATE_12M, 0xA},
1644                 {BRCM_RATE_18M, 0xE},
1645                 {BRCM_RATE_24M, 0x9},
1646                 {BRCM_RATE_36M, 0xD},
1647                 {BRCM_RATE_48M, 0x8},
1648                 {BRCM_RATE_54M, 0xC}
1649         };
1650
1651         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
1652                 if (rate == rate_lookup[i].rate) {
1653                         plcp_rate = rate_lookup[i].signal_rate;
1654                         break;
1655                 }
1656         }
1657
1658         /* Find the SHM pointer to the rate table entry by looking in the
1659          * Direct-map Table
1660          */
1661         return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1662 }
1663
1664 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1665 {
1666         u8 rate;
1667         u8 rates[8] = {
1668                 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
1669                 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
1670         };
1671         u16 entry_ptr;
1672         u16 pctl1;
1673         uint i;
1674
1675         if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1676                 return;
1677
1678         /* walk the phy rate table and update the entries */
1679         for (i = 0; i < ARRAY_SIZE(rates); i++) {
1680                 rate = rates[i];
1681
1682                 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1683
1684                 /* read the SHM Rate Table entry OFDM PCTL1 values */
1685                 pctl1 =
1686                     brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1687
1688                 /* modify the value */
1689                 pctl1 &= ~PHY_TXC1_MODE_MASK;
1690                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1691
1692                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
1693                 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1694                                    pctl1);
1695         }
1696 }
1697
1698 /* band-specific init */
1699 static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
1700 {
1701         struct brcms_hardware *wlc_hw = wlc->hw;
1702
1703         brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
1704                            wlc_hw->band->bandunit);
1705
1706         brcms_c_ucode_bsinit(wlc_hw);
1707
1708         wlc_phy_init(wlc_hw->band->pi, chanspec);
1709
1710         brcms_c_ucode_txant_set(wlc_hw);
1711
1712         /*
1713          * cwmin is band-specific, update hardware
1714          * with value for current band
1715          */
1716         brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1717         brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1718
1719         brcms_b_update_slot_timing(wlc_hw,
1720                                    wlc_hw->band->bandtype == BRCM_BAND_5G ?
1721                                    true : wlc_hw->shortslot);
1722
1723         /* write phytype and phyvers */
1724         brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1725         brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1726
1727         /*
1728          * initialize the txphyctl1 rate table since
1729          * shmem is shared between bands
1730          */
1731         brcms_upd_ofdm_pctl1_table(wlc_hw);
1732
1733         brcms_b_upd_synthpu(wlc_hw);
1734 }
1735
1736 /* Perform a soft reset of the PHY PLL */
1737 void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1738 {
1739         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
1740                   ~0, 0);
1741         udelay(1);
1742         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1743                   0x4, 0);
1744         udelay(1);
1745         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1746                   0x4, 4);
1747         udelay(1);
1748         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1749                   0x4, 0);
1750         udelay(1);
1751 }
1752
1753 /* light way to turn on phy clock without reset for NPHY only
1754  *  refer to brcms_b_core_phy_clk for full version
1755  */
1756 void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1757 {
1758         /* support(necessary for NPHY and HYPHY) only */
1759         if (!BRCMS_ISNPHY(wlc_hw->band))
1760                 return;
1761
1762         if (ON == clk)
1763                 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
1764         else
1765                 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
1766
1767 }
1768
1769 void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1770 {
1771         if (ON == clk)
1772                 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
1773         else
1774                 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
1775 }
1776
1777 void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1778 {
1779         struct brcms_phy_pub *pih = wlc_hw->band->pi;
1780         u32 phy_bw_clkbits;
1781         bool phy_in_reset = false;
1782
1783         brcms_dbg_info(wlc_hw->d11core, "wl%d: reset phy\n", wlc_hw->unit);
1784
1785         if (pih == NULL)
1786                 return;
1787
1788         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1789
1790         /* Specific reset sequence required for NPHY rev 3 and 4 */
1791         if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1792             NREV_LE(wlc_hw->band->phyrev, 4)) {
1793                 /* Set the PHY bandwidth */
1794                 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
1795
1796                 udelay(1);
1797
1798                 /* Perform a soft reset of the PHY PLL */
1799                 brcms_b_core_phypll_reset(wlc_hw);
1800
1801                 /* reset the PHY */
1802                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
1803                                    (SICF_PRST | SICF_PCLKE));
1804                 phy_in_reset = true;
1805         } else {
1806                 brcms_b_core_ioctl(wlc_hw,
1807                                    (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1808                                    (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1809         }
1810
1811         udelay(2);
1812         brcms_b_core_phy_clk(wlc_hw, ON);
1813
1814         if (pih)
1815                 wlc_phy_anacore(pih, ON);
1816 }
1817
1818 /* switch to and initialize new band */
1819 static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1820                             u16 chanspec) {
1821         struct brcms_c_info *wlc = wlc_hw->wlc;
1822         u32 macintmask;
1823
1824         /* Enable the d11 core before accessing it */
1825         if (!bcma_core_is_enabled(wlc_hw->d11core)) {
1826                 bcma_core_enable(wlc_hw->d11core, 0);
1827                 brcms_c_mctrl_reset(wlc_hw);
1828         }
1829
1830         macintmask = brcms_c_setband_inact(wlc, bandunit);
1831
1832         if (!wlc_hw->up)
1833                 return;
1834
1835         brcms_b_core_phy_clk(wlc_hw, ON);
1836
1837         /* band-specific initializations */
1838         brcms_b_bsinit(wlc, chanspec);
1839
1840         /*
1841          * If there are any pending software interrupt bits,
1842          * then replace these with a harmless nonzero value
1843          * so brcms_c_dpc() will re-enable interrupts when done.
1844          */
1845         if (wlc->macintstatus)
1846                 wlc->macintstatus = MI_DMAINT;
1847
1848         /* restore macintmask */
1849         brcms_intrsrestore(wlc->wl, macintmask);
1850
1851         /* ucode should still be suspended.. */
1852         WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1853                  MCTL_EN_MAC) != 0);
1854 }
1855
1856 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1857 {
1858
1859         /* reject unsupported corerev */
1860         if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1861                 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1862                           wlc_hw->corerev);
1863                 return false;
1864         }
1865
1866         return true;
1867 }
1868
1869 /* Validate some board info parameters */
1870 static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1871 {
1872         uint boardrev = wlc_hw->boardrev;
1873
1874         /* 4 bits each for board type, major, minor, and tiny version */
1875         uint brt = (boardrev & 0xf000) >> 12;
1876         uint b0 = (boardrev & 0xf00) >> 8;
1877         uint b1 = (boardrev & 0xf0) >> 4;
1878         uint b2 = boardrev & 0xf;
1879
1880         /* voards from other vendors are always considered valid */
1881         if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1882                 return true;
1883
1884         /* do some boardrev sanity checks when boardvendor is Broadcom */
1885         if (boardrev == 0)
1886                 return false;
1887
1888         if (boardrev <= 0xff)
1889                 return true;
1890
1891         if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1892                 || (b2 > 9))
1893                 return false;
1894
1895         return true;
1896 }
1897
1898 static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1899 {
1900         struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1901
1902         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1903         if (!is_zero_ether_addr(sprom->il0mac)) {
1904                 memcpy(etheraddr, sprom->il0mac, 6);
1905                 return;
1906         }
1907
1908         if (wlc_hw->_nbands > 1)
1909                 memcpy(etheraddr, sprom->et1mac, 6);
1910         else
1911                 memcpy(etheraddr, sprom->il0mac, 6);
1912 }
1913
1914 /* power both the pll and external oscillator on/off */
1915 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1916 {
1917         brcms_dbg_info(wlc_hw->d11core, "wl%d: want %d\n", wlc_hw->unit, want);
1918
1919         /*
1920          * dont power down if plldown is false or
1921          * we must poll hw radio disable
1922          */
1923         if (!want && wlc_hw->pllreq)
1924                 return;
1925
1926         wlc_hw->sbclk = want;
1927         if (!wlc_hw->sbclk) {
1928                 wlc_hw->clk = false;
1929                 if (wlc_hw->band && wlc_hw->band->pi)
1930                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1931         }
1932 }
1933
1934 /*
1935  * Return true if radio is disabled, otherwise false.
1936  * hw radio disable signal is an external pin, users activate it asynchronously
1937  * this function could be called when driver is down and w/o clock
1938  * it operates on different registers depending on corerev and boardflag.
1939  */
1940 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1941 {
1942         bool v, clk, xtal;
1943         u32 flags = 0;
1944
1945         xtal = wlc_hw->sbclk;
1946         if (!xtal)
1947                 brcms_b_xtal(wlc_hw, ON);
1948
1949         /* may need to take core out of reset first */
1950         clk = wlc_hw->clk;
1951         if (!clk) {
1952                 /*
1953                  * mac no longer enables phyclk automatically when driver
1954                  * accesses phyreg throughput mac. This can be skipped since
1955                  * only mac reg is accessed below
1956                  */
1957                 if (D11REV_GE(wlc_hw->corerev, 18))
1958                         flags |= SICF_PCLKE;
1959
1960                 /*
1961                  * TODO: test suspend/resume
1962                  *
1963                  * AI chip doesn't restore bar0win2 on
1964                  * hibernation/resume, need sw fixup
1965                  */
1966
1967                 bcma_core_enable(wlc_hw->d11core, flags);
1968                 brcms_c_mctrl_reset(wlc_hw);
1969         }
1970
1971         v = ((bcma_read32(wlc_hw->d11core,
1972                           D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
1973
1974         /* put core back into reset */
1975         if (!clk)
1976                 bcma_core_disable(wlc_hw->d11core, 0);
1977
1978         if (!xtal)
1979                 brcms_b_xtal(wlc_hw, OFF);
1980
1981         return v;
1982 }
1983
1984 static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
1985 {
1986         struct dma_pub *di = wlc_hw->di[fifo];
1987         return dma_rxreset(di);
1988 }
1989
1990 /* d11 core reset
1991  *   ensure fask clock during reset
1992  *   reset dma
1993  *   reset d11(out of reset)
1994  *   reset phy(out of reset)
1995  *   clear software macintstatus for fresh new start
1996  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
1997  */
1998 void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
1999 {
2000         uint i;
2001         bool fastclk;
2002
2003         if (flags == BRCMS_USE_COREFLAGS)
2004                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2005
2006         brcms_dbg_info(wlc_hw->d11core, "wl%d: core reset\n", wlc_hw->unit);
2007
2008         /* request FAST clock if not on  */
2009         fastclk = wlc_hw->forcefastclk;
2010         if (!fastclk)
2011                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2012
2013         /* reset the dma engines except first time thru */
2014         if (bcma_core_is_enabled(wlc_hw->d11core)) {
2015                 for (i = 0; i < NFIFO; i++)
2016                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2017                                 brcms_err(wlc_hw->d11core, "wl%d: %s: "
2018                                           "dma_txreset[%d]: cannot stop dma\n",
2019                                            wlc_hw->unit, __func__, i);
2020
2021                 if ((wlc_hw->di[RX_FIFO])
2022                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2023                         brcms_err(wlc_hw->d11core, "wl%d: %s: dma_rxreset"
2024                                   "[%d]: cannot stop dma\n",
2025                                   wlc_hw->unit, __func__, RX_FIFO);
2026         }
2027         /* if noreset, just stop the psm and return */
2028         if (wlc_hw->noreset) {
2029                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2030                 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2031                 return;
2032         }
2033
2034         /*
2035          * mac no longer enables phyclk automatically when driver accesses
2036          * phyreg throughput mac, AND phy_reset is skipped at early stage when
2037          * band->pi is invalid. need to enable PHY CLK
2038          */
2039         if (D11REV_GE(wlc_hw->corerev, 18))
2040                 flags |= SICF_PCLKE;
2041
2042         /*
2043          * reset the core
2044          * In chips with PMU, the fastclk request goes through d11 core
2045          * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2046          *
2047          * This adds some delay and we can optimize it by also requesting
2048          * fastclk through chipcommon during this period if necessary. But
2049          * that has to work coordinate with other driver like mips/arm since
2050          * they may touch chipcommon as well.
2051          */
2052         wlc_hw->clk = false;
2053         bcma_core_enable(wlc_hw->d11core, flags);
2054         wlc_hw->clk = true;
2055         if (wlc_hw->band && wlc_hw->band->pi)
2056                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2057
2058         brcms_c_mctrl_reset(wlc_hw);
2059
2060         if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2061                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2062
2063         brcms_b_phy_reset(wlc_hw);
2064
2065         /* turn on PHY_PLL */
2066         brcms_b_core_phypll_ctl(wlc_hw, true);
2067
2068         /* clear sw intstatus */
2069         wlc_hw->wlc->macintstatus = 0;
2070
2071         /* restore the clk setting */
2072         if (!fastclk)
2073                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
2074 }
2075
2076 /* txfifo sizes needs to be modified(increased) since the newer cores
2077  * have more memory.
2078  */
2079 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2080 {
2081         struct bcma_device *core = wlc_hw->d11core;
2082         u16 fifo_nu;
2083         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2084         u16 txfifo_def, txfifo_def1;
2085         u16 txfifo_cmd;
2086
2087         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2088         txfifo_startblk = TXFIFO_START_BLK;
2089
2090         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2091         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2092
2093                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2094                 txfifo_def = (txfifo_startblk & 0xff) |
2095                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2096                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2097                     ((((txfifo_endblk -
2098                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2099                 txfifo_cmd =
2100                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2101
2102                 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2103                 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
2104                 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
2105
2106                 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2107
2108                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2109         }
2110         /*
2111          * need to propagate to shm location to be in sync since ucode/hw won't
2112          * do this
2113          */
2114         brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2115                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2116         brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2117                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2118         brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2119                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2120                             xmtfifo_sz[TX_AC_BK_FIFO]));
2121         brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2122                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2123                             xmtfifo_sz[TX_BCMC_FIFO]));
2124 }
2125
2126 /* This function is used for changing the tsf frac register
2127  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2128  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2129  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2130  * HTPHY Formula is 2^26/freq(MHz) e.g.
2131  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2132  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2133  * For spuron: 123MHz -> 2^26/123    = 545600.5
2134  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2135  * For spur off: 120MHz -> 2^26/120    = 559240.5
2136  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2137  */
2138
2139 void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2140 {
2141         struct bcma_device *core = wlc_hw->d11core;
2142
2143         if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
2144             (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
2145                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2146                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
2147                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2148                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2149                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
2150                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2151                 } else {        /* 120Mhz */
2152                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
2153                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2154                 }
2155         } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2156                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2157                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
2158                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2159                 } else {        /* 80Mhz */
2160                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
2161                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2162                 }
2163         }
2164 }
2165
2166 /* Initialize GPIOs that are controlled by D11 core */
2167 static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2168 {
2169         struct brcms_hardware *wlc_hw = wlc->hw;
2170         u32 gc, gm;
2171
2172         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2173         brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2174
2175         /*
2176          * Common GPIO setup:
2177          *      G0 = LED 0 = WLAN Activity
2178          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2179          *      G2 = LED 2 = WLAN 5 GHz Radio State
2180          *      G4 = radio disable input (HI enabled, LO disabled)
2181          */
2182
2183         gc = gm = 0;
2184
2185         /* Allocate GPIOs for mimo antenna diversity feature */
2186         if (wlc_hw->antsel_type == ANTSEL_2x3) {
2187                 /* Enable antenna diversity, use 2x3 mode */
2188                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2189                              MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2190                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2191                              MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2192
2193                 /* init superswitch control */
2194                 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2195
2196         } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2197                 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2198                 /*
2199                  * The board itself is powered by these GPIOs
2200                  * (when not sending pattern) so set them high
2201                  */
2202                 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2203                            (BOARD_GPIO_12 | BOARD_GPIO_13));
2204                 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2205                            (BOARD_GPIO_12 | BOARD_GPIO_13));
2206
2207                 /* Enable antenna diversity, use 2x4 mode */
2208                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2209                              MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2210                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2211                              BRCM_BAND_ALL);
2212
2213                 /* Configure the desired clock to be 4Mhz */
2214                 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2215                                    ANTSEL_CLKDIV_4MHZ);
2216         }
2217
2218         /*
2219          * gpio 9 controls the PA. ucode is responsible
2220          * for wiggling out and oe
2221          */
2222         if (wlc_hw->boardflags & BFL_PACTRL)
2223                 gm |= gc |= BOARD_GPIO_PACTRL;
2224
2225         /* apply to gpiocontrol register */
2226         bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
2227 }
2228
2229 static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2230                               const __le32 ucode[], const size_t nbytes)
2231 {
2232         struct bcma_device *core = wlc_hw->d11core;
2233         uint i;
2234         uint count;
2235
2236         brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
2237
2238         count = (nbytes / sizeof(u32));
2239
2240         bcma_write32(core, D11REGOFFS(objaddr),
2241                      OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
2242         (void)bcma_read32(core, D11REGOFFS(objaddr));
2243         for (i = 0; i < count; i++)
2244                 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
2245
2246 }
2247
2248 static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2249 {
2250         struct brcms_c_info *wlc;
2251         struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2252
2253         wlc = wlc_hw->wlc;
2254
2255         if (wlc_hw->ucode_loaded)
2256                 return;
2257
2258         if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
2259                 if (BRCMS_ISNPHY(wlc_hw->band)) {
2260                         brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2261                                           ucode->bcm43xx_16_mimosz);
2262                         wlc_hw->ucode_loaded = true;
2263                 } else
2264                         brcms_err(wlc_hw->d11core,
2265                                   "%s: wl%d: unsupported phy in corerev %d\n",
2266                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2267         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2268                 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2269                         brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2270                                           ucode->bcm43xx_24_lcnsz);
2271                         wlc_hw->ucode_loaded = true;
2272                 } else {
2273                         brcms_err(wlc_hw->d11core,
2274                                   "%s: wl%d: unsupported phy in corerev %d\n",
2275                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2276                 }
2277         }
2278 }
2279
2280 void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2281 {
2282         /* update sw state */
2283         wlc_hw->bmac_phytxant = phytxant;
2284
2285         /* push to ucode if up */
2286         if (!wlc_hw->up)
2287                 return;
2288         brcms_c_ucode_txant_set(wlc_hw);
2289
2290 }
2291
2292 u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2293 {
2294         return (u16) wlc_hw->wlc->stf->txant;
2295 }
2296
2297 void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2298 {
2299         wlc_hw->antsel_type = antsel_type;
2300
2301         /* Update the antsel type for phy module to use */
2302         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2303 }
2304
2305 static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2306 {
2307         bool fatal = false;
2308         uint unit;
2309         uint intstatus, idx;
2310         struct bcma_device *core = wlc_hw->d11core;
2311
2312         unit = wlc_hw->unit;
2313
2314         for (idx = 0; idx < NFIFO; idx++) {
2315                 /* read intstatus register and ignore any non-error bits */
2316                 intstatus =
2317                         bcma_read32(core,
2318                                     D11REGOFFS(intctrlregs[idx].intstatus)) &
2319                         I_ERRORS;
2320                 if (!intstatus)
2321                         continue;
2322
2323                 brcms_dbg_int(core, "wl%d: intstatus%d 0x%x\n",
2324                               unit, idx, intstatus);
2325
2326                 if (intstatus & I_RO) {
2327                         brcms_err(core, "wl%d: fifo %d: receive fifo "
2328                                   "overflow\n", unit, idx);
2329                         fatal = true;
2330                 }
2331
2332                 if (intstatus & I_PC) {
2333                         brcms_err(core, "wl%d: fifo %d: descriptor error\n",
2334                                   unit, idx);
2335                         fatal = true;
2336                 }
2337
2338                 if (intstatus & I_PD) {
2339                         brcms_err(core, "wl%d: fifo %d: data error\n", unit,
2340                                   idx);
2341                         fatal = true;
2342                 }
2343
2344                 if (intstatus & I_DE) {
2345                         brcms_err(core, "wl%d: fifo %d: descriptor protocol "
2346                                   "error\n", unit, idx);
2347                         fatal = true;
2348                 }
2349
2350                 if (intstatus & I_RU)
2351                         brcms_err(core, "wl%d: fifo %d: receive descriptor "
2352                                   "underflow\n", idx, unit);
2353
2354                 if (intstatus & I_XU) {
2355                         brcms_err(core, "wl%d: fifo %d: transmit fifo "
2356                                   "underflow\n", idx, unit);
2357                         fatal = true;
2358                 }
2359
2360                 if (fatal) {
2361                         brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2362                         break;
2363                 } else
2364                         bcma_write32(core,
2365                                      D11REGOFFS(intctrlregs[idx].intstatus),
2366                                      intstatus);
2367         }
2368 }
2369
2370 void brcms_c_intrson(struct brcms_c_info *wlc)
2371 {
2372         struct brcms_hardware *wlc_hw = wlc->hw;
2373         wlc->macintmask = wlc->defmacintmask;
2374         bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2375 }
2376
2377 u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2378 {
2379         struct brcms_hardware *wlc_hw = wlc->hw;
2380         u32 macintmask;
2381
2382         if (!wlc_hw->clk)
2383                 return 0;
2384
2385         macintmask = wlc->macintmask;   /* isr can still happen */
2386
2387         bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2388         (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2389         udelay(1);              /* ensure int line is no longer driven */
2390         wlc->macintmask = 0;
2391
2392         /* return previous macintmask; resolve race between us and our isr */
2393         return wlc->macintstatus ? 0 : macintmask;
2394 }
2395
2396 void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2397 {
2398         struct brcms_hardware *wlc_hw = wlc->hw;
2399         if (!wlc_hw->clk)
2400                 return;
2401
2402         wlc->macintmask = macintmask;
2403         bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2404 }
2405
2406 /* assumes that the d11 MAC is enabled */
2407 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2408                                     uint tx_fifo)
2409 {
2410         u8 fifo = 1 << tx_fifo;
2411
2412         /* Two clients of this code, 11h Quiet period and scanning. */
2413
2414         /* only suspend if not already suspended */
2415         if ((wlc_hw->suspended_fifos & fifo) == fifo)
2416                 return;
2417
2418         /* force the core awake only if not already */
2419         if (wlc_hw->suspended_fifos == 0)
2420                 brcms_c_ucode_wake_override_set(wlc_hw,
2421                                                 BRCMS_WAKE_OVERRIDE_TXFIFO);
2422
2423         wlc_hw->suspended_fifos |= fifo;
2424
2425         if (wlc_hw->di[tx_fifo]) {
2426                 /*
2427                  * Suspending AMPDU transmissions in the middle can cause
2428                  * underflow which may result in mismatch between ucode and
2429                  * driver so suspend the mac before suspending the FIFO
2430                  */
2431                 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2432                         brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2433
2434                 dma_txsuspend(wlc_hw->di[tx_fifo]);
2435
2436                 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2437                         brcms_c_enable_mac(wlc_hw->wlc);
2438         }
2439 }
2440
2441 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2442                                    uint tx_fifo)
2443 {
2444         /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2445          * but need to be done here for PIO otherwise the watchdog will catch
2446          * the inconsistency and fire
2447          */
2448         /* Two clients of this code, 11h Quiet period and scanning. */
2449         if (wlc_hw->di[tx_fifo])
2450                 dma_txresume(wlc_hw->di[tx_fifo]);
2451
2452         /* allow core to sleep again */
2453         if (wlc_hw->suspended_fifos == 0)
2454                 return;
2455         else {
2456                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2457                 if (wlc_hw->suspended_fifos == 0)
2458                         brcms_c_ucode_wake_override_clear(wlc_hw,
2459                                                 BRCMS_WAKE_OVERRIDE_TXFIFO);
2460         }
2461 }
2462
2463 /* precondition: requires the mac core to be enabled */
2464 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2465 {
2466         static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2467         u8 *ethaddr = wlc_hw->wlc->pub->cur_etheraddr;
2468
2469         if (mute_tx) {
2470                 /* suspend tx fifos */
2471                 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2472                 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2473                 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2474                 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2475
2476                 /* zero the address match register so we do not send ACKs */
2477                 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, null_ether_addr);
2478         } else {
2479                 /* resume tx fifos */
2480                 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2481                 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2482                 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2483                 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2484
2485                 /* Restore address */
2486                 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, ethaddr);
2487         }
2488
2489         wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2490
2491         if (mute_tx)
2492                 brcms_c_ucode_mute_override_set(wlc_hw);
2493         else
2494                 brcms_c_ucode_mute_override_clear(wlc_hw);
2495 }
2496
2497 void
2498 brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2499 {
2500         brcms_b_mute(wlc->hw, mute_tx);
2501 }
2502
2503 /*
2504  * Read and clear macintmask and macintstatus and intstatus registers.
2505  * This routine should be called with interrupts off
2506  * Return:
2507  *   -1 if brcms_deviceremoved(wlc) evaluates to true;
2508  *   0 if the interrupt is not for us, or we are in some special cases;
2509  *   device interrupt status bits otherwise.
2510  */
2511 static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2512 {
2513         struct brcms_hardware *wlc_hw = wlc->hw;
2514         struct bcma_device *core = wlc_hw->d11core;
2515         u32 macintstatus, mask;
2516
2517         /* macintstatus includes a DMA interrupt summary bit */
2518         macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
2519         mask = in_isr ? wlc->macintmask : wlc->defmacintmask;
2520
2521         trace_brcms_macintstatus(&core->dev, in_isr, macintstatus, mask);
2522
2523         /* detect cardbus removed, in power down(suspend) and in reset */
2524         if (brcms_deviceremoved(wlc))
2525                 return -1;
2526
2527         /* brcms_deviceremoved() succeeds even when the core is still resetting,
2528          * handle that case here.
2529          */
2530         if (macintstatus == 0xffffffff)
2531                 return 0;
2532
2533         /* defer unsolicited interrupts */
2534         macintstatus &= mask;
2535
2536         /* if not for us */
2537         if (macintstatus == 0)
2538                 return 0;
2539
2540         /* turn off the interrupts */
2541         bcma_write32(core, D11REGOFFS(macintmask), 0);
2542         (void)bcma_read32(core, D11REGOFFS(macintmask));
2543         wlc->macintmask = 0;
2544
2545         /* clear device interrupts */
2546         bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
2547
2548         /* MI_DMAINT is indication of non-zero intstatus */
2549         if (macintstatus & MI_DMAINT)
2550                 /*
2551                  * only fifo interrupt enabled is I_RI in
2552                  * RX_FIFO. If MI_DMAINT is set, assume it
2553                  * is set and clear the interrupt.
2554                  */
2555                 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
2556                              DEF_RXINTMASK);
2557
2558         return macintstatus;
2559 }
2560
2561 /* Update wlc->macintstatus and wlc->intstatus[]. */
2562 /* Return true if they are updated successfully. false otherwise */
2563 bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2564 {
2565         u32 macintstatus;
2566
2567         /* read and clear macintstatus and intstatus registers */
2568         macintstatus = wlc_intstatus(wlc, false);
2569
2570         /* device is removed */
2571         if (macintstatus == 0xffffffff)
2572                 return false;
2573
2574         /* update interrupt status in software */
2575         wlc->macintstatus |= macintstatus;
2576
2577         return true;
2578 }
2579
2580 /*
2581  * First-level interrupt processing.
2582  * Return true if this was our interrupt
2583  * and if further brcms_c_dpc() processing is required,
2584  * false otherwise.
2585  */
2586 bool brcms_c_isr(struct brcms_c_info *wlc)
2587 {
2588         struct brcms_hardware *wlc_hw = wlc->hw;
2589         u32 macintstatus;
2590
2591         if (!wlc_hw->up || !wlc->macintmask)
2592                 return false;
2593
2594         /* read and clear macintstatus and intstatus registers */
2595         macintstatus = wlc_intstatus(wlc, true);
2596
2597         if (macintstatus == 0xffffffff) {
2598                 brcms_err(wlc_hw->d11core,
2599                           "DEVICEREMOVED detected in the ISR code path\n");
2600                 return false;
2601         }
2602
2603         /* it is not for us */
2604         if (macintstatus == 0)
2605                 return false;
2606
2607         /* save interrupt status bits */
2608         wlc->macintstatus = macintstatus;
2609
2610         return true;
2611
2612 }
2613
2614 void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2615 {
2616         struct brcms_hardware *wlc_hw = wlc->hw;
2617         struct bcma_device *core = wlc_hw->d11core;
2618         u32 mc, mi;
2619
2620         brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2621                            wlc_hw->band->bandunit);
2622
2623         /*
2624          * Track overlapping suspend requests
2625          */
2626         wlc_hw->mac_suspend_depth++;
2627         if (wlc_hw->mac_suspend_depth > 1)
2628                 return;
2629
2630         /* force the core awake */
2631         brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2632
2633         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2634
2635         if (mc == 0xffffffff) {
2636                 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2637                           __func__);
2638                 brcms_down(wlc->wl);
2639                 return;
2640         }
2641         WARN_ON(mc & MCTL_PSM_JMP_0);
2642         WARN_ON(!(mc & MCTL_PSM_RUN));
2643         WARN_ON(!(mc & MCTL_EN_MAC));
2644
2645         mi = bcma_read32(core, D11REGOFFS(macintstatus));
2646         if (mi == 0xffffffff) {
2647                 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2648                           __func__);
2649                 brcms_down(wlc->wl);
2650                 return;
2651         }
2652         WARN_ON(mi & MI_MACSSPNDD);
2653
2654         brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2655
2656         SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
2657                  BRCMS_MAX_MAC_SUSPEND);
2658
2659         if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
2660                 brcms_err(core, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2661                           " and MI_MACSSPNDD is still not on.\n",
2662                           wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2663                 brcms_err(core, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2664                           "psm_brc 0x%04x\n", wlc_hw->unit,
2665                           bcma_read32(core, D11REGOFFS(psmdebug)),
2666                           bcma_read32(core, D11REGOFFS(phydebug)),
2667                           bcma_read16(core, D11REGOFFS(psm_brc)));
2668         }
2669
2670         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2671         if (mc == 0xffffffff) {
2672                 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2673                           __func__);
2674                 brcms_down(wlc->wl);
2675                 return;
2676         }
2677         WARN_ON(mc & MCTL_PSM_JMP_0);
2678         WARN_ON(!(mc & MCTL_PSM_RUN));
2679         WARN_ON(mc & MCTL_EN_MAC);
2680 }
2681
2682 void brcms_c_enable_mac(struct brcms_c_info *wlc)
2683 {
2684         struct brcms_hardware *wlc_hw = wlc->hw;
2685         struct bcma_device *core = wlc_hw->d11core;
2686         u32 mc, mi;
2687
2688         brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2689                            wlc->band->bandunit);
2690
2691         /*
2692          * Track overlapping suspend requests
2693          */
2694         wlc_hw->mac_suspend_depth--;
2695         if (wlc_hw->mac_suspend_depth > 0)
2696                 return;
2697
2698         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2699         WARN_ON(mc & MCTL_PSM_JMP_0);
2700         WARN_ON(mc & MCTL_EN_MAC);
2701         WARN_ON(!(mc & MCTL_PSM_RUN));
2702
2703         brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2704         bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
2705
2706         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2707         WARN_ON(mc & MCTL_PSM_JMP_0);
2708         WARN_ON(!(mc & MCTL_EN_MAC));
2709         WARN_ON(!(mc & MCTL_PSM_RUN));
2710
2711         mi = bcma_read32(core, D11REGOFFS(macintstatus));
2712         WARN_ON(mi & MI_MACSSPNDD);
2713
2714         brcms_c_ucode_wake_override_clear(wlc_hw,
2715                                           BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2716 }
2717
2718 void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2719 {
2720         wlc_hw->hw_stf_ss_opmode = stf_mode;
2721
2722         if (wlc_hw->clk)
2723                 brcms_upd_ofdm_pctl1_table(wlc_hw);
2724 }
2725
2726 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2727 {
2728         struct bcma_device *core = wlc_hw->d11core;
2729         u32 w, val;
2730         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2731
2732         /* Validate dchip register access */
2733
2734         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2735         (void)bcma_read32(core, D11REGOFFS(objaddr));
2736         w = bcma_read32(core, D11REGOFFS(objdata));
2737
2738         /* Can we write and read back a 32bit register? */
2739         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2740         (void)bcma_read32(core, D11REGOFFS(objaddr));
2741         bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
2742
2743         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2744         (void)bcma_read32(core, D11REGOFFS(objaddr));
2745         val = bcma_read32(core, D11REGOFFS(objdata));
2746         if (val != (u32) 0xaa5555aa) {
2747                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2748                           "expected 0xaa5555aa\n", wlc_hw->unit, val);
2749                 return false;
2750         }
2751
2752         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2753         (void)bcma_read32(core, D11REGOFFS(objaddr));
2754         bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
2755
2756         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2757         (void)bcma_read32(core, D11REGOFFS(objaddr));
2758         val = bcma_read32(core, D11REGOFFS(objdata));
2759         if (val != (u32) 0x55aaaa55) {
2760                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2761                           "expected 0x55aaaa55\n", wlc_hw->unit, val);
2762                 return false;
2763         }
2764
2765         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2766         (void)bcma_read32(core, D11REGOFFS(objaddr));
2767         bcma_write32(core, D11REGOFFS(objdata), w);
2768
2769         /* clear CFPStart */
2770         bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
2771
2772         w = bcma_read32(core, D11REGOFFS(maccontrol));
2773         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2774             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2775                 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
2776                           "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2777                           (MCTL_IHR_EN | MCTL_WAKE),
2778                           (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
2779                 return false;
2780         }
2781
2782         return true;
2783 }
2784
2785 #define PHYPLL_WAIT_US  100000
2786
2787 void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2788 {
2789         struct bcma_device *core = wlc_hw->d11core;
2790         u32 tmp;
2791
2792         brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
2793
2794         tmp = 0;
2795
2796         if (on) {
2797                 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
2798                         bcma_set32(core, D11REGOFFS(clk_ctl_st),
2799                                    CCS_ERSRC_REQ_HT |
2800                                    CCS_ERSRC_REQ_D11PLL |
2801                                    CCS_ERSRC_REQ_PHYPLL);
2802                         SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2803                                   CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
2804                                  PHYPLL_WAIT_US);
2805
2806                         tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2807                         if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
2808                                 brcms_err(core, "%s: turn on PHY PLL failed\n",
2809                                           __func__);
2810                 } else {
2811                         bcma_set32(core, D11REGOFFS(clk_ctl_st),
2812                                    tmp | CCS_ERSRC_REQ_D11PLL |
2813                                    CCS_ERSRC_REQ_PHYPLL);
2814                         SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2815                                   (CCS_ERSRC_AVAIL_D11PLL |
2816                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
2817                                  (CCS_ERSRC_AVAIL_D11PLL |
2818                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2819
2820                         tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2821                         if ((tmp &
2822                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2823                             !=
2824                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2825                                 brcms_err(core, "%s: turn on PHY PLL failed\n",
2826                                           __func__);
2827                 }
2828         } else {
2829                 /*
2830                  * Since the PLL may be shared, other cores can still
2831                  * be requesting it; so we'll deassert the request but
2832                  * not wait for status to comply.
2833                  */
2834                 bcma_mask32(core, D11REGOFFS(clk_ctl_st),
2835                             ~CCS_ERSRC_REQ_PHYPLL);
2836                 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
2837         }
2838 }
2839
2840 static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2841 {
2842         bool dev_gone;
2843
2844         brcms_dbg_info(wlc_hw->d11core, "wl%d: disable core\n", wlc_hw->unit);
2845
2846         dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2847
2848         if (dev_gone)
2849                 return;
2850
2851         if (wlc_hw->noreset)
2852                 return;
2853
2854         /* radio off */
2855         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2856
2857         /* turn off analog core */
2858         wlc_phy_anacore(wlc_hw->band->pi, OFF);
2859
2860         /* turn off PHYPLL to save power */
2861         brcms_b_core_phypll_ctl(wlc_hw, false);
2862
2863         wlc_hw->clk = false;
2864         bcma_core_disable(wlc_hw->d11core, 0);
2865         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2866 }
2867
2868 static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2869 {
2870         struct brcms_hardware *wlc_hw = wlc->hw;
2871         uint i;
2872
2873         /* free any posted tx packets */
2874         for (i = 0; i < NFIFO; i++) {
2875                 if (wlc_hw->di[i]) {
2876                         dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
2877                         if (i < TX_BCMC_FIFO)
2878                                 ieee80211_wake_queue(wlc->pub->ieee_hw,
2879                                                      brcms_fifo_to_ac(i));
2880                 }
2881         }
2882
2883         /* free any posted rx packets */
2884         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
2885 }
2886
2887 static u16
2888 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2889 {
2890         struct bcma_device *core = wlc_hw->d11core;
2891         u16 objoff = D11REGOFFS(objdata);
2892
2893         bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2894         (void)bcma_read32(core, D11REGOFFS(objaddr));
2895         if (offset & 2)
2896                 objoff += 2;
2897
2898         return bcma_read16(core, objoff);
2899 }
2900
2901 static void
2902 brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2903                      u32 sel)
2904 {
2905         struct bcma_device *core = wlc_hw->d11core;
2906         u16 objoff = D11REGOFFS(objdata);
2907
2908         bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2909         (void)bcma_read32(core, D11REGOFFS(objaddr));
2910         if (offset & 2)
2911                 objoff += 2;
2912
2913         bcma_wflush16(core, objoff, v);
2914 }
2915
2916 /*
2917  * Read a single u16 from shared memory.
2918  * SHM 'offset' needs to be an even address
2919  */
2920 u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
2921 {
2922         return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
2923 }
2924
2925 /*
2926  * Write a single u16 to shared memory.
2927  * SHM 'offset' needs to be an even address
2928  */
2929 void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
2930 {
2931         brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
2932 }
2933
2934 /*
2935  * Copy a buffer to shared memory of specified type .
2936  * SHM 'offset' needs to be an even address and
2937  * Buffer length 'len' must be an even number of bytes
2938  * 'sel' selects the type of memory
2939  */
2940 void
2941 brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
2942                       const void *buf, int len, u32 sel)
2943 {
2944         u16 v;
2945         const u8 *p = (const u8 *)buf;
2946         int i;
2947
2948         if (len <= 0 || (offset & 1) || (len & 1))
2949                 return;
2950
2951         for (i = 0; i < len; i += 2) {
2952                 v = p[i] | (p[i + 1] << 8);
2953                 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
2954         }
2955 }
2956
2957 /*
2958  * Copy a piece of shared memory of specified type to a buffer .
2959  * SHM 'offset' needs to be an even address and
2960  * Buffer length 'len' must be an even number of bytes
2961  * 'sel' selects the type of memory
2962  */
2963 void
2964 brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
2965                          int len, u32 sel)
2966 {
2967         u16 v;
2968         u8 *p = (u8 *) buf;
2969         int i;
2970
2971         if (len <= 0 || (offset & 1) || (len & 1))
2972                 return;
2973
2974         for (i = 0; i < len; i += 2) {
2975                 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
2976                 p[i] = v & 0xFF;
2977                 p[i + 1] = (v >> 8) & 0xFF;
2978         }
2979 }
2980
2981 /* Copy a buffer to shared memory.
2982  * SHM 'offset' needs to be an even address and
2983  * Buffer length 'len' must be an even number of bytes
2984  */
2985 static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
2986                         const void *buf, int len)
2987 {
2988         brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
2989 }
2990
2991 static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
2992                                    u16 SRL, u16 LRL)
2993 {
2994         wlc_hw->SRL = SRL;
2995         wlc_hw->LRL = LRL;
2996
2997         /* write retry limit to SCR, shouldn't need to suspend */
2998         if (wlc_hw->up) {
2999                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3000                              OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3001                 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3002                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
3003                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3004                              OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3005                 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3006                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3007         }
3008 }
3009
3010 static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3011 {
3012         if (set) {
3013                 if (mboolisset(wlc_hw->pllreq, req_bit))
3014                         return;
3015
3016                 mboolset(wlc_hw->pllreq, req_bit);
3017
3018                 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3019                         if (!wlc_hw->sbclk)
3020                                 brcms_b_xtal(wlc_hw, ON);
3021                 }
3022         } else {
3023                 if (!mboolisset(wlc_hw->pllreq, req_bit))
3024                         return;
3025
3026                 mboolclr(wlc_hw->pllreq, req_bit);
3027
3028                 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3029                         if (wlc_hw->sbclk)
3030                                 brcms_b_xtal(wlc_hw, OFF);
3031                 }
3032         }
3033 }
3034
3035 static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3036 {
3037         wlc_hw->antsel_avail = antsel_avail;
3038 }
3039
3040 /*
3041  * conditions under which the PM bit should be set in outgoing frames
3042  * and STAY_AWAKE is meaningful
3043  */
3044 static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
3045 {
3046         struct brcms_bss_cfg *cfg = wlc->bsscfg;
3047
3048         /* disallow PS when one of the following global conditions meets */
3049         if (!wlc->pub->associated)
3050                 return false;
3051
3052         /* disallow PS when one of these meets when not scanning */
3053         if (wlc->filter_flags & FIF_PROMISC_IN_BSS)
3054                 return false;
3055
3056         if (cfg->associated) {
3057                 /*
3058                  * disallow PS when one of the following
3059                  * bsscfg specific conditions meets
3060                  */
3061                 if (!cfg->BSS)
3062                         return false;
3063
3064                 return false;
3065         }
3066
3067         return true;
3068 }
3069
3070 static void brcms_c_statsupd(struct brcms_c_info *wlc)
3071 {
3072         int i;
3073         struct macstat macstats;
3074 #ifdef DEBUG
3075         u16 delta;
3076         u16 rxf0ovfl;
3077         u16 txfunfl[NFIFO];
3078 #endif                          /* DEBUG */
3079
3080         /* if driver down, make no sense to update stats */
3081         if (!wlc->pub->up)
3082                 return;
3083
3084 #ifdef DEBUG
3085         /* save last rx fifo 0 overflow count */
3086         rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
3087
3088         /* save last tx fifo  underflow count */
3089         for (i = 0; i < NFIFO; i++)
3090                 txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
3091 #endif                          /* DEBUG */
3092
3093         /* Read mac stats from contiguous shared memory */
3094         brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
3095                                 sizeof(struct macstat), OBJADDR_SHM_SEL);
3096
3097 #ifdef DEBUG
3098         /* check for rx fifo 0 overflow */
3099         delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
3100         if (delta)
3101                 brcms_err(wlc->hw->d11core, "wl%d: %u rx fifo 0 overflows!\n",
3102                           wlc->pub->unit, delta);
3103
3104         /* check for tx fifo underflows */
3105         for (i = 0; i < NFIFO; i++) {
3106                 delta =
3107                     (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
3108                               txfunfl[i]);
3109                 if (delta)
3110                         brcms_err(wlc->hw->d11core,
3111                                   "wl%d: %u tx fifo %d underflows!\n",
3112                                   wlc->pub->unit, delta, i);
3113         }
3114 #endif                          /* DEBUG */
3115
3116         /* merge counters from dma module */
3117         for (i = 0; i < NFIFO; i++) {
3118                 if (wlc->hw->di[i])
3119                         dma_counterreset(wlc->hw->di[i]);
3120         }
3121 }
3122
3123 static void brcms_b_reset(struct brcms_hardware *wlc_hw)
3124 {
3125         /* reset the core */
3126         if (!brcms_deviceremoved(wlc_hw->wlc))
3127                 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
3128
3129         /* purge the dma rings */
3130         brcms_c_flushqueues(wlc_hw->wlc);
3131 }
3132
3133 void brcms_c_reset(struct brcms_c_info *wlc)
3134 {
3135         brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
3136
3137         /* slurp up hw mac counters before core reset */
3138         brcms_c_statsupd(wlc);
3139
3140         /* reset our snapshot of macstat counters */
3141         memset(wlc->core->macstat_snapshot, 0, sizeof(struct macstat));
3142
3143         brcms_b_reset(wlc->hw);
3144 }
3145
3146 void brcms_c_init_scb(struct scb *scb)
3147 {
3148         int i;
3149
3150         memset(scb, 0, sizeof(struct scb));
3151         scb->flags = SCB_WMECAP | SCB_HTCAP;
3152         for (i = 0; i < NUMPRIO; i++) {
3153                 scb->seqnum[i] = 0;
3154                 scb->seqctl[i] = 0xFFFF;
3155         }
3156
3157         scb->seqctl_nonqos = 0xFFFF;
3158         scb->magic = SCB_MAGIC;
3159 }
3160
3161 /* d11 core init
3162  *   reset PSM
3163  *   download ucode/PCM
3164  *   let ucode run to suspended
3165  *   download ucode inits
3166  *   config other core registers
3167  *   init dma
3168  */
3169 static void brcms_b_coreinit(struct brcms_c_info *wlc)
3170 {
3171         struct brcms_hardware *wlc_hw = wlc->hw;
3172         struct bcma_device *core = wlc_hw->d11core;
3173         u32 sflags;
3174         u32 bcnint_us;
3175         uint i = 0;
3176         bool fifosz_fixup = false;
3177         int err = 0;
3178         u16 buf[NFIFO];
3179         struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
3180
3181         brcms_dbg_info(core, "wl%d: core init\n", wlc_hw->unit);
3182
3183         /* reset PSM */
3184         brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
3185
3186         brcms_ucode_download(wlc_hw);
3187         /*
3188          * FIFOSZ fixup. driver wants to controls the fifo allocation.
3189          */
3190         fifosz_fixup = true;
3191
3192         /* let the PSM run to the suspended state, set mode to BSS STA */
3193         bcma_write32(core, D11REGOFFS(macintstatus), -1);
3194         brcms_b_mctrl(wlc_hw, ~0,
3195                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
3196
3197         /* wait for ucode to self-suspend after auto-init */
3198         SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
3199                    MI_MACSSPNDD) == 0), 1000 * 1000);
3200         if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
3201                 brcms_err(core, "wl%d: wlc_coreinit: ucode did not self-"
3202                           "suspend!\n", wlc_hw->unit);
3203
3204         brcms_c_gpio_init(wlc);
3205
3206         sflags = bcma_aread32(core, BCMA_IOST);
3207
3208         if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
3209                 if (BRCMS_ISNPHY(wlc_hw->band))
3210                         brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
3211                 else
3212                         brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3213                                   " %d\n", __func__, wlc_hw->unit,
3214                                   wlc_hw->corerev);
3215         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
3216                 if (BRCMS_ISLCNPHY(wlc_hw->band))
3217                         brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
3218                 else
3219                         brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3220                                   " %d\n", __func__, wlc_hw->unit,
3221                                   wlc_hw->corerev);
3222         } else {
3223                 brcms_err(core, "%s: wl%d: unsupported corerev %d\n",
3224                           __func__, wlc_hw->unit, wlc_hw->corerev);
3225         }
3226
3227         /* For old ucode, txfifo sizes needs to be modified(increased) */
3228         if (fifosz_fixup)
3229                 brcms_b_corerev_fifofixup(wlc_hw);
3230
3231         /* check txfifo allocations match between ucode and driver */
3232         buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
3233         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
3234                 i = TX_AC_BE_FIFO;
3235                 err = -1;
3236         }
3237         buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
3238         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
3239                 i = TX_AC_VI_FIFO;
3240                 err = -1;
3241         }
3242         buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
3243         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
3244         buf[TX_AC_BK_FIFO] &= 0xff;
3245         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
3246                 i = TX_AC_BK_FIFO;
3247                 err = -1;
3248         }
3249         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
3250                 i = TX_AC_VO_FIFO;
3251                 err = -1;
3252         }
3253         buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
3254         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
3255         buf[TX_BCMC_FIFO] &= 0xff;
3256         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
3257                 i = TX_BCMC_FIFO;
3258                 err = -1;
3259         }
3260         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
3261                 i = TX_ATIM_FIFO;
3262                 err = -1;
3263         }
3264         if (err != 0)
3265                 brcms_err(core, "wlc_coreinit: txfifo mismatch: ucode size %d"
3266                           " driver size %d index %d\n", buf[i],
3267                           wlc_hw->xmtfifo_sz[i], i);
3268
3269         /* make sure we can still talk to the mac */
3270         WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
3271
3272         /* band-specific inits done by wlc_bsinit() */
3273
3274         /* Set up frame burst size and antenna swap threshold init values */
3275         brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
3276         brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
3277
3278         /* enable one rx interrupt per received frame */
3279         bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
3280
3281         /* set the station mode (BSS STA) */
3282         brcms_b_mctrl(wlc_hw,
3283                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
3284                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
3285
3286         /* set up Beacon interval */
3287         bcnint_us = 0x8000 << 10;
3288         bcma_write32(core, D11REGOFFS(tsf_cfprep),
3289                      (bcnint_us << CFPREP_CBI_SHIFT));
3290         bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
3291         bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
3292
3293         /* write interrupt mask */
3294         bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
3295                      DEF_RXINTMASK);
3296
3297         /* allow the MAC to control the PHY clock (dynamic on/off) */
3298         brcms_b_macphyclk_set(wlc_hw, ON);
3299
3300         /* program dynamic clock control fast powerup delay register */
3301         wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
3302         bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
3303
3304         /* tell the ucode the corerev */
3305         brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
3306
3307         /* tell the ucode MAC capabilities */
3308         brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
3309                            (u16) (wlc_hw->machwcap & 0xffff));
3310         brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
3311                            (u16) ((wlc_hw->
3312                                       machwcap >> 16) & 0xffff));
3313
3314         /* write retry limits to SCR, this done after PSM init */
3315         bcma_write32(core, D11REGOFFS(objaddr),
3316                      OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3317         (void)bcma_read32(core, D11REGOFFS(objaddr));
3318         bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
3319         bcma_write32(core, D11REGOFFS(objaddr),
3320                      OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3321         (void)bcma_read32(core, D11REGOFFS(objaddr));
3322         bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
3323
3324         /* write rate fallback retry limits */
3325         brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
3326         brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
3327
3328         bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
3329         bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
3330
3331         /* init the tx dma engines */
3332         for (i = 0; i < NFIFO; i++) {
3333                 if (wlc_hw->di[i])
3334                         dma_txinit(wlc_hw->di[i]);
3335         }
3336
3337         /* init the rx dma engine(s) and post receive buffers */
3338         dma_rxinit(wlc_hw->di[RX_FIFO]);
3339         dma_rxfill(wlc_hw->di[RX_FIFO]);
3340 }
3341
3342 void
3343 static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
3344         u32 macintmask;
3345         bool fastclk;
3346         struct brcms_c_info *wlc = wlc_hw->wlc;
3347
3348         /* request FAST clock if not on */
3349         fastclk = wlc_hw->forcefastclk;
3350         if (!fastclk)
3351                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
3352
3353         /* disable interrupts */
3354         macintmask = brcms_intrsoff(wlc->wl);
3355
3356         /* set up the specified band and chanspec */
3357         brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
3358         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3359
3360         /* do one-time phy inits and calibration */
3361         wlc_phy_cal_init(wlc_hw->band->pi);
3362
3363         /* core-specific initialization */
3364         brcms_b_coreinit(wlc);
3365
3366         /* band-specific inits */
3367         brcms_b_bsinit(wlc, chanspec);
3368
3369         /* restore macintmask */
3370         brcms_intrsrestore(wlc->wl, macintmask);
3371
3372         /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
3373          * is suspended and brcms_c_enable_mac() will clear this override bit.
3374          */
3375         mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3376
3377         /*
3378          * initialize mac_suspend_depth to 1 to match ucode
3379          * initial suspended state
3380          */
3381         wlc_hw->mac_suspend_depth = 1;
3382
3383         /* restore the clk */
3384         if (!fastclk)
3385                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
3386 }
3387
3388 static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
3389                                      u16 chanspec)
3390 {
3391         /* Save our copy of the chanspec */
3392         wlc->chanspec = chanspec;
3393
3394         /* Set the chanspec and power limits for this locale */
3395         brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
3396
3397         if (wlc->stf->ss_algosel_auto)
3398                 brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
3399                                             chanspec);
3400
3401         brcms_c_stf_ss_update(wlc, wlc->band);
3402 }
3403
3404 static void
3405 brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
3406 {
3407         brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
3408                 wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
3409                 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
3410                 brcms_chspec_bw(wlc->default_bss->chanspec),
3411                 wlc->stf->txstreams);
3412 }
3413
3414 /* derive wlc->band->basic_rate[] table from 'rateset' */
3415 static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
3416                               struct brcms_c_rateset *rateset)
3417 {
3418         u8 rate;
3419         u8 mandatory;
3420         u8 cck_basic = 0;
3421         u8 ofdm_basic = 0;
3422         u8 *br = wlc->band->basic_rate;
3423         uint i;
3424
3425         /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
3426         memset(br, 0, BRCM_MAXRATE + 1);
3427
3428         /* For each basic rate in the rates list, make an entry in the
3429          * best basic lookup.
3430          */
3431         for (i = 0; i < rateset->count; i++) {
3432                 /* only make an entry for a basic rate */
3433                 if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
3434                         continue;
3435
3436                 /* mask off basic bit */
3437                 rate = (rateset->rates[i] & BRCMS_RATE_MASK);
3438
3439                 if (rate > BRCM_MAXRATE) {
3440                         brcms_err(wlc->hw->d11core, "brcms_c_rate_lookup_init: "
3441                                   "invalid rate 0x%X in rate set\n",
3442                                   rateset->rates[i]);
3443                         continue;
3444                 }
3445
3446                 br[rate] = rate;
3447         }
3448
3449         /* The rate lookup table now has non-zero entries for each
3450          * basic rate, equal to the basic rate: br[basicN] = basicN
3451          *
3452          * To look up the best basic rate corresponding to any
3453          * particular rate, code can use the basic_rate table
3454          * like this
3455          *
3456          * basic_rate = wlc->band->basic_rate[tx_rate]
3457          *
3458          * Make sure there is a best basic rate entry for
3459          * every rate by walking up the table from low rates
3460          * to high, filling in holes in the lookup table
3461          */
3462
3463         for (i = 0; i < wlc->band->hw_rateset.count; i++) {
3464                 rate = wlc->band->hw_rateset.rates[i];
3465
3466                 if (br[rate] != 0) {
3467                         /* This rate is a basic rate.
3468                          * Keep track of the best basic rate so far by
3469                          * modulation type.
3470                          */
3471                         if (is_ofdm_rate(rate))
3472                                 ofdm_basic = rate;
3473                         else
3474                                 cck_basic = rate;
3475
3476                         continue;
3477                 }
3478
3479                 /* This rate is not a basic rate so figure out the
3480                  * best basic rate less than this rate and fill in
3481                  * the hole in the table
3482                  */
3483
3484                 br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
3485
3486                 if (br[rate] != 0)
3487                         continue;
3488
3489                 if (is_ofdm_rate(rate)) {
3490                         /*
3491                          * In 11g and 11a, the OFDM mandatory rates
3492                          * are 6, 12, and 24 Mbps
3493                          */
3494                         if (rate >= BRCM_RATE_24M)
3495                                 mandatory = BRCM_RATE_24M;
3496                         else if (rate >= BRCM_RATE_12M)
3497                                 mandatory = BRCM_RATE_12M;
3498                         else
3499                                 mandatory = BRCM_RATE_6M;
3500                 } else {
3501                         /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
3502                         mandatory = rate;
3503                 }
3504
3505                 br[rate] = mandatory;
3506         }
3507 }
3508
3509 static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
3510                                      u16 chanspec)
3511 {
3512         struct brcms_c_rateset default_rateset;
3513         uint parkband;
3514         uint i, band_order[2];
3515
3516         /*
3517          * We might have been bandlocked during down and the chip
3518          * power-cycled (hibernate). Figure out the right band to park on
3519          */
3520         if (wlc->bandlocked || wlc->pub->_nbands == 1) {
3521                 /* updated in brcms_c_bandlock() */
3522                 parkband = wlc->band->bandunit;
3523                 band_order[0] = band_order[1] = parkband;
3524         } else {
3525                 /* park on the band of the specified chanspec */
3526                 parkband = chspec_bandunit(chanspec);
3527
3528                 /* order so that parkband initialize last */
3529                 band_order[0] = parkband ^ 1;
3530                 band_order[1] = parkband;
3531         }
3532
3533         /* make each band operational, software state init */
3534         for (i = 0; i < wlc->pub->_nbands; i++) {
3535                 uint j = band_order[i];
3536
3537                 wlc->band = wlc->bandstate[j];
3538
3539                 brcms_default_rateset(wlc, &default_rateset);
3540
3541                 /* fill in hw_rate */
3542                 brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
3543                                    false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
3544                                    (bool) (wlc->pub->_n_enab & SUPPORT_11N));
3545
3546                 /* init basic rate lookup */
3547                 brcms_c_rate_lookup_init(wlc, &default_rateset);
3548         }
3549
3550         /* sync up phy/radio chanspec */
3551         brcms_c_set_phy_chanspec(wlc, chanspec);
3552 }
3553
3554 /*
3555  * Set or clear filtering related maccontrol bits based on
3556  * specified filter flags
3557  */
3558 void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags)
3559 {
3560         u32 promisc_bits = 0;
3561
3562         wlc->filter_flags = filter_flags;
3563
3564         if (filter_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS))
3565                 promisc_bits |= MCTL_PROMISC;
3566
3567         if (filter_flags & FIF_BCN_PRBRESP_PROMISC)
3568                 promisc_bits |= MCTL_BCNS_PROMISC;
3569
3570         if (filter_flags & FIF_FCSFAIL)
3571                 promisc_bits |= MCTL_KEEPBADFCS;
3572
3573         if (filter_flags & (FIF_CONTROL | FIF_PSPOLL))
3574                 promisc_bits |= MCTL_KEEPCONTROL;
3575
3576         brcms_b_mctrl(wlc->hw,
3577                 MCTL_PROMISC | MCTL_BCNS_PROMISC |
3578                 MCTL_KEEPCONTROL | MCTL_KEEPBADFCS,
3579                 promisc_bits);
3580 }
3581
3582 /*
3583  * ucode, hwmac update
3584  *    Channel dependent updates for ucode and hw
3585  */
3586 static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
3587 {
3588         /* enable or disable any active IBSSs depending on whether or not
3589          * we are on the home channel
3590          */
3591         if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
3592                 if (wlc->pub->associated) {
3593                         /*
3594                          * BMAC_NOTE: This is something that should be fixed
3595                          * in ucode inits. I think that the ucode inits set
3596                          * up the bcn templates and shm values with a bogus
3597                          * beacon. This should not be done in the inits. If
3598                          * ucode needs to set up a beacon for testing, the
3599                          * test routines should write it down, not expect the
3600                          * inits to populate a bogus beacon.
3601                          */
3602                         if (BRCMS_PHY_11N_CAP(wlc->band))
3603                                 brcms_b_write_shm(wlc->hw,
3604                                                 M_BCN_TXTSF_OFFSET, 0);
3605                 }
3606         } else {
3607                 /* disable an active IBSS if we are not on the home channel */
3608         }
3609 }
3610
3611 static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
3612                                    u8 basic_rate)
3613 {
3614         u8 phy_rate, index;
3615         u8 basic_phy_rate, basic_index;
3616         u16 dir_table, basic_table;
3617         u16 basic_ptr;
3618
3619         /* Shared memory address for the table we are reading */
3620         dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
3621
3622         /* Shared memory address for the table we are writing */
3623         basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
3624
3625         /*
3626          * for a given rate, the LS-nibble of the PLCP SIGNAL field is
3627          * the index into the rate table.
3628          */
3629         phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
3630         basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
3631         index = phy_rate & 0xf;
3632         basic_index = basic_phy_rate & 0xf;
3633
3634         /* Find the SHM pointer to the ACK rate entry by looking in the
3635          * Direct-map Table
3636          */
3637         basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
3638
3639         /* Update the SHM BSS-basic-rate-set mapping table with the pointer
3640          * to the correct basic rate for the given incoming rate
3641          */
3642         brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
3643 }
3644
3645 static const struct brcms_c_rateset *
3646 brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
3647 {
3648         const struct brcms_c_rateset *rs_dflt;
3649
3650         if (BRCMS_PHY_11N_CAP(wlc->band)) {
3651                 if (wlc->band->bandtype == BRCM_BAND_5G)
3652                         rs_dflt = &ofdm_mimo_rates;
3653                 else
3654                         rs_dflt = &cck_ofdm_mimo_rates;
3655         } else if (wlc->band->gmode)
3656                 rs_dflt = &cck_ofdm_rates;
3657         else
3658                 rs_dflt = &cck_rates;
3659
3660         return rs_dflt;
3661 }
3662
3663 static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
3664 {
3665         const struct brcms_c_rateset *rs_dflt;
3666         struct brcms_c_rateset rs;
3667         u8 rate, basic_rate;
3668         uint i;
3669
3670         rs_dflt = brcms_c_rateset_get_hwrs(wlc);
3671
3672         brcms_c_rateset_copy(rs_dflt, &rs);
3673         brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
3674
3675         /* walk the phy rate table and update SHM basic rate lookup table */
3676         for (i = 0; i < rs.count; i++) {
3677                 rate = rs.rates[i] & BRCMS_RATE_MASK;
3678
3679                 /* for a given rate brcms_basic_rate returns the rate at
3680                  * which a response ACK/CTS should be sent.
3681                  */
3682                 basic_rate = brcms_basic_rate(wlc, rate);
3683                 if (basic_rate == 0)
3684                         /* This should only happen if we are using a
3685                          * restricted rateset.
3686                          */
3687                         basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
3688
3689                 brcms_c_write_rate_shm(wlc, rate, basic_rate);
3690         }
3691 }
3692
3693 /* band-specific init */
3694 static void brcms_c_bsinit(struct brcms_c_info *wlc)
3695 {
3696         brcms_dbg_info(wlc->hw->d11core, "wl%d: bandunit %d\n",
3697                        wlc->pub->unit, wlc->band->bandunit);
3698
3699         /* write ucode ACK/CTS rate table */
3700         brcms_c_set_ratetable(wlc);
3701
3702         /* update some band specific mac configuration */
3703         brcms_c_ucode_mac_upd(wlc);
3704
3705         /* init antenna selection */
3706         brcms_c_antsel_init(wlc->asi);
3707
3708 }
3709
3710 /* formula:  IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
3711 static int
3712 brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
3713                    bool writeToShm)
3714 {
3715         int idle_busy_ratio_x_16 = 0;
3716         uint offset =
3717             isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
3718             M_TX_IDLE_BUSY_RATIO_X_16_CCK;
3719         if (duty_cycle > 100 || duty_cycle < 0) {
3720                 brcms_err(wlc->hw->d11core,
3721                           "wl%d:  duty cycle value off limit\n",
3722                           wlc->pub->unit);
3723                 return -EINVAL;
3724         }
3725         if (duty_cycle)
3726                 idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
3727         /* Only write to shared memory  when wl is up */
3728         if (writeToShm)
3729                 brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
3730
3731         if (isOFDM)
3732                 wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
3733         else
3734                 wlc->tx_duty_cycle_cck = (u16) duty_cycle;
3735
3736         return 0;
3737 }
3738
3739 /* push sw hps and wake state through hardware */
3740 static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
3741 {
3742         u32 v1, v2;
3743         bool hps;
3744         bool awake_before;
3745
3746         hps = brcms_c_ps_allowed(wlc);
3747
3748         brcms_dbg_mac80211(wlc->hw->d11core, "wl%d: hps %d\n", wlc->pub->unit,
3749                            hps);
3750
3751         v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
3752         v2 = MCTL_WAKE;
3753         if (hps)
3754                 v2 |= MCTL_HPS;
3755
3756         brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
3757
3758         awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
3759
3760         if (!awake_before)
3761                 brcms_b_wait_for_wake(wlc->hw);
3762 }
3763
3764 /*
3765  * Write this BSS config's MAC address to core.
3766  * Updates RXE match engine.
3767  */
3768 static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
3769 {
3770         int err = 0;
3771         struct brcms_c_info *wlc = bsscfg->wlc;
3772
3773         /* enter the MAC addr into the RXE match registers */
3774         brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, bsscfg->cur_etheraddr);
3775
3776         brcms_c_ampdu_macaddr_upd(wlc);
3777
3778         return err;
3779 }
3780
3781 /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
3782  * Updates RXE match engine.
3783  */
3784 static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
3785 {
3786         /* we need to update BSSID in RXE match registers */
3787         brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
3788 }
3789
3790 static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
3791 {
3792         wlc_hw->shortslot = shortslot;
3793
3794         if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
3795                 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
3796                 brcms_b_update_slot_timing(wlc_hw, shortslot);
3797                 brcms_c_enable_mac(wlc_hw->wlc);
3798         }
3799 }
3800
3801 /*
3802  * Suspend the the MAC and update the slot timing
3803  * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
3804  */
3805 static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
3806 {
3807         /* use the override if it is set */
3808         if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
3809                 shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
3810
3811         if (wlc->shortslot == shortslot)
3812                 return;
3813
3814         wlc->shortslot = shortslot;
3815
3816         brcms_b_set_shortslot(wlc->hw, shortslot);
3817 }
3818
3819 static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3820 {
3821         if (wlc->home_chanspec != chanspec) {
3822                 wlc->home_chanspec = chanspec;
3823
3824                 if (wlc->bsscfg->associated)
3825                         wlc->bsscfg->current_bss->chanspec = chanspec;
3826         }
3827 }
3828
3829 void
3830 brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
3831                       bool mute_tx, struct txpwr_limits *txpwr)
3832 {
3833         uint bandunit;
3834
3835         brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: 0x%x\n", wlc_hw->unit,
3836                            chanspec);
3837
3838         wlc_hw->chanspec = chanspec;
3839
3840         /* Switch bands if necessary */
3841         if (wlc_hw->_nbands > 1) {
3842                 bandunit = chspec_bandunit(chanspec);
3843                 if (wlc_hw->band->bandunit != bandunit) {
3844                         /* brcms_b_setband disables other bandunit,
3845                          *  use light band switch if not up yet
3846                          */
3847                         if (wlc_hw->up) {
3848                                 wlc_phy_chanspec_radio_set(wlc_hw->
3849                                                            bandstate[bandunit]->
3850                                                            pi, chanspec);
3851                                 brcms_b_setband(wlc_hw, bandunit, chanspec);
3852                         } else {
3853                                 brcms_c_setxband(wlc_hw, bandunit);
3854                         }
3855                 }
3856         }
3857
3858         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
3859
3860         if (!wlc_hw->up) {
3861                 if (wlc_hw->clk)
3862                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
3863                                                   chanspec);
3864                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3865         } else {
3866                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
3867                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
3868
3869                 /* Update muting of the channel */
3870                 brcms_b_mute(wlc_hw, mute_tx);
3871         }
3872 }
3873
3874 /* switch to and initialize new band */
3875 static void brcms_c_setband(struct brcms_c_info *wlc,
3876                                            uint bandunit)
3877 {
3878         wlc->band = wlc->bandstate[bandunit];
3879
3880         if (!wlc->pub->up)
3881                 return;
3882
3883         /* wait for at least one beacon before entering sleeping state */
3884         brcms_c_set_ps_ctrl(wlc);
3885
3886         /* band-specific initializations */
3887         brcms_c_bsinit(wlc);
3888 }
3889
3890 static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3891 {
3892         uint bandunit;
3893         bool switchband = false;
3894         u16 old_chanspec = wlc->chanspec;
3895
3896         if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
3897                 brcms_err(wlc->hw->d11core, "wl%d: %s: Bad channel %d\n",
3898                           wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
3899                 return;
3900         }
3901
3902         /* Switch bands if necessary */
3903         if (wlc->pub->_nbands > 1) {
3904                 bandunit = chspec_bandunit(chanspec);
3905                 if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
3906                         switchband = true;
3907                         if (wlc->bandlocked) {
3908                                 brcms_err(wlc->hw->d11core,
3909                                           "wl%d: %s: chspec %d band is locked!\n",
3910                                           wlc->pub->unit, __func__,
3911                                           CHSPEC_CHANNEL(chanspec));
3912                                 return;
3913                         }
3914                         /*
3915                          * should the setband call come after the
3916                          * brcms_b_chanspec() ? if the setband updates
3917                          * (brcms_c_bsinit) use low level calls to inspect and
3918                          * set state, the state inspected may be from the wrong
3919                          * band, or the following brcms_b_set_chanspec() may
3920                          * undo the work.
3921                          */
3922                         brcms_c_setband(wlc, bandunit);
3923                 }
3924         }
3925
3926         /* sync up phy/radio chanspec */
3927         brcms_c_set_phy_chanspec(wlc, chanspec);
3928
3929         /* init antenna selection */
3930         if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
3931                 brcms_c_antsel_init(wlc->asi);
3932
3933                 /* Fix the hardware rateset based on bw.
3934                  * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
3935                  */
3936                 brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
3937                         wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
3938         }
3939
3940         /* update some mac configuration since chanspec changed */
3941         brcms_c_ucode_mac_upd(wlc);
3942 }
3943
3944 /*
3945  * This function changes the phytxctl for beacon based on current
3946  * beacon ratespec AND txant setting as per this table:
3947  *  ratespec     CCK            ant = wlc->stf->txant
3948  *              OFDM            ant = 3
3949  */
3950 void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
3951                                        u32 bcn_rspec)
3952 {
3953         u16 phyctl;
3954         u16 phytxant = wlc->stf->phytxant;
3955         u16 mask = PHY_TXC_ANT_MASK;
3956
3957         /* for non-siso rates or default setting, use the available chains */
3958         if (BRCMS_PHY_11N_CAP(wlc->band))
3959                 phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
3960
3961         phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
3962         phyctl = (phyctl & ~mask) | phytxant;
3963         brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
3964 }
3965
3966 /*
3967  * centralized protection config change function to simplify debugging, no
3968  * consistency checking this should be called only on changes to avoid overhead
3969  * in periodic function
3970  */
3971 void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
3972 {
3973         /*
3974          * Cannot use brcms_dbg_* here because this function is called
3975          * before wlc is sufficiently initialized.
3976          */
3977         BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
3978
3979         switch (idx) {
3980         case BRCMS_PROT_G_SPEC:
3981                 wlc->protection->_g = (bool) val;
3982                 break;
3983         case BRCMS_PROT_G_OVR:
3984                 wlc->protection->g_override = (s8) val;
3985                 break;
3986         case BRCMS_PROT_G_USER:
3987                 wlc->protection->gmode_user = (u8) val;
3988                 break;
3989         case BRCMS_PROT_OVERLAP:
3990                 wlc->protection->overlap = (s8) val;
3991                 break;
3992         case BRCMS_PROT_N_USER:
3993                 wlc->protection->nmode_user = (s8) val;
3994                 break;
3995         case BRCMS_PROT_N_CFG:
3996                 wlc->protection->n_cfg = (s8) val;
3997                 break;
3998         case BRCMS_PROT_N_CFG_OVR:
3999                 wlc->protection->n_cfg_override = (s8) val;
4000                 break;
4001         case BRCMS_PROT_N_NONGF:
4002                 wlc->protection->nongf = (bool) val;
4003                 break;
4004         case BRCMS_PROT_N_NONGF_OVR:
4005                 wlc->protection->nongf_override = (s8) val;
4006                 break;
4007         case BRCMS_PROT_N_PAM_OVR:
4008                 wlc->protection->n_pam_override = (s8) val;
4009                 break;
4010         case BRCMS_PROT_N_OBSS:
4011                 wlc->protection->n_obss = (bool) val;
4012                 break;
4013
4014         default:
4015                 break;
4016         }
4017
4018 }
4019
4020 static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
4021 {
4022         if (wlc->pub->up) {
4023                 brcms_c_update_beacon(wlc);
4024                 brcms_c_update_probe_resp(wlc, true);
4025         }
4026 }
4027
4028 static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
4029 {
4030         wlc->stf->ldpc = val;
4031
4032         if (wlc->pub->up) {
4033                 brcms_c_update_beacon(wlc);
4034                 brcms_c_update_probe_resp(wlc, true);
4035                 wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
4036         }
4037 }
4038
4039 void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
4040                        const struct ieee80211_tx_queue_params *params,
4041                        bool suspend)
4042 {
4043         int i;
4044         struct shm_acparams acp_shm;
4045         u16 *shm_entry;
4046
4047         /* Only apply params if the core is out of reset and has clocks */
4048         if (!wlc->clk) {
4049                 brcms_err(wlc->hw->d11core, "wl%d: %s : no-clock\n",
4050                           wlc->pub->unit, __func__);
4051                 return;
4052         }
4053
4054         memset(&acp_shm, 0, sizeof(struct shm_acparams));
4055         /* fill in shm ac params struct */
4056         acp_shm.txop = params->txop;
4057         /* convert from units of 32us to us for ucode */
4058         wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
4059             EDCF_TXOP2USEC(acp_shm.txop);
4060         acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
4061
4062         if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
4063             && acp_shm.aifs < EDCF_AIFSN_MAX)
4064                 acp_shm.aifs++;
4065
4066         if (acp_shm.aifs < EDCF_AIFSN_MIN
4067             || acp_shm.aifs > EDCF_AIFSN_MAX) {
4068                 brcms_err(wlc->hw->d11core, "wl%d: edcf_setparams: bad "
4069                           "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
4070         } else {
4071                 acp_shm.cwmin = params->cw_min;
4072                 acp_shm.cwmax = params->cw_max;
4073                 acp_shm.cwcur = acp_shm.cwmin;
4074                 acp_shm.bslots =
4075                         bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) &
4076                         acp_shm.cwcur;
4077                 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
4078                 /* Indicate the new params to the ucode */
4079                 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
4080                                                   wme_ac2fifo[aci] *
4081                                                   M_EDCF_QLEN +
4082                                                   M_EDCF_STATUS_OFF));
4083                 acp_shm.status |= WME_STATUS_NEWAC;
4084
4085                 /* Fill in shm acparam table */
4086                 shm_entry = (u16 *) &acp_shm;
4087                 for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
4088                         brcms_b_write_shm(wlc->hw,
4089                                           M_EDCF_QINFO +
4090                                           wme_ac2fifo[aci] * M_EDCF_QLEN + i,
4091                                           *shm_entry++);
4092         }
4093
4094         if (suspend) {
4095                 brcms_c_suspend_mac_and_wait(wlc);
4096                 brcms_c_enable_mac(wlc);
4097         }
4098 }
4099
4100 static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
4101 {
4102         u16 aci;
4103         int i_ac;
4104         struct ieee80211_tx_queue_params txq_pars;
4105         static const struct edcf_acparam default_edcf_acparams[] = {
4106                  {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
4107                  {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
4108                  {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
4109                  {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
4110         }; /* ucode needs these parameters during its initialization */
4111         const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
4112
4113         for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) {
4114                 /* find out which ac this set of params applies to */
4115                 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
4116
4117                 /* fill in shm ac params struct */
4118                 txq_pars.txop = edcf_acp->TXOP;
4119                 txq_pars.aifs = edcf_acp->ACI;
4120
4121                 /* CWmin = 2^(ECWmin) - 1 */
4122                 txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
4123                 /* CWmax = 2^(ECWmax) - 1 */
4124                 txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
4125                                             >> EDCF_ECWMAX_SHIFT);
4126                 brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
4127         }
4128
4129         if (suspend) {
4130                 brcms_c_suspend_mac_and_wait(wlc);
4131                 brcms_c_enable_mac(wlc);
4132         }
4133 }
4134
4135 static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
4136 {
4137         /* Don't start the timer if HWRADIO feature is disabled */
4138         if (wlc->radio_monitor)
4139                 return;
4140
4141         wlc->radio_monitor = true;
4142         brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
4143         brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
4144 }
4145
4146 static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
4147 {
4148         if (!wlc->radio_monitor)
4149                 return true;
4150
4151         wlc->radio_monitor = false;
4152         brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
4153         return brcms_del_timer(wlc->radio_timer);
4154 }
4155
4156 /* read hwdisable state and propagate to wlc flag */
4157 static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
4158 {
4159         if (wlc->pub->hw_off)
4160                 return;
4161
4162         if (brcms_b_radio_read_hwdisabled(wlc->hw))
4163                 mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4164         else
4165                 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4166 }
4167
4168 /* update hwradio status and return it */
4169 bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
4170 {
4171         brcms_c_radio_hwdisable_upd(wlc);
4172
4173         return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
4174                         true : false;
4175 }
4176
4177 /* periodical query hw radio button while driver is "down" */
4178 static void brcms_c_radio_timer(void *arg)
4179 {
4180         struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4181
4182         if (brcms_deviceremoved(wlc)) {
4183                 brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
4184                           wlc->pub->unit, __func__);
4185                 brcms_down(wlc->wl);
4186                 return;
4187         }
4188
4189         brcms_c_radio_hwdisable_upd(wlc);
4190 }
4191
4192 /* common low-level watchdog code */
4193 static void brcms_b_watchdog(struct brcms_c_info *wlc)
4194 {
4195         struct brcms_hardware *wlc_hw = wlc->hw;
4196
4197         if (!wlc_hw->up)
4198                 return;
4199
4200         /* increment second count */
4201         wlc_hw->now++;
4202
4203         /* Check for FIFO error interrupts */
4204         brcms_b_fifoerrors(wlc_hw);
4205
4206         /* make sure RX dma has buffers */
4207         dma_rxfill(wlc->hw->di[RX_FIFO]);
4208
4209         wlc_phy_watchdog(wlc_hw->band->pi);
4210 }
4211
4212 /* common watchdog code */
4213 static void brcms_c_watchdog(struct brcms_c_info *wlc)
4214 {
4215         brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
4216
4217         if (!wlc->pub->up)
4218                 return;
4219
4220         if (brcms_deviceremoved(wlc)) {
4221                 brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
4222                           wlc->pub->unit, __func__);
4223                 brcms_down(wlc->wl);
4224                 return;
4225         }
4226
4227         /* increment second count */
4228         wlc->pub->now++;
4229
4230         brcms_c_radio_hwdisable_upd(wlc);
4231         /* if radio is disable, driver may be down, quit here */
4232         if (wlc->pub->radio_disabled)
4233                 return;
4234
4235         brcms_b_watchdog(wlc);
4236
4237         /*
4238          * occasionally sample mac stat counters to
4239          * detect 16-bit counter wrap
4240          */
4241         if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
4242                 brcms_c_statsupd(wlc);
4243
4244         if (BRCMS_ISNPHY(wlc->band) &&
4245             ((wlc->pub->now - wlc->tempsense_lasttime) >=
4246              BRCMS_TEMPSENSE_PERIOD)) {
4247                 wlc->tempsense_lasttime = wlc->pub->now;
4248                 brcms_c_tempsense_upd(wlc);
4249         }
4250 }
4251
4252 static void brcms_c_watchdog_by_timer(void *arg)
4253 {
4254         struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4255
4256         brcms_c_watchdog(wlc);
4257 }
4258
4259 static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
4260 {
4261         wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
4262                 wlc, "watchdog");
4263         if (!wlc->wdtimer) {
4264                 wiphy_err(wlc->wiphy, "wl%d:  wl_init_timer for wdtimer "
4265                           "failed\n", unit);
4266                 goto fail;
4267         }
4268
4269         wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
4270                 wlc, "radio");
4271         if (!wlc->radio_timer) {
4272                 wiphy_err(wlc->wiphy, "wl%d:  wl_init_timer for radio_timer "
4273                           "failed\n", unit);
4274                 goto fail;
4275         }
4276
4277         return true;
4278
4279  fail:
4280         return false;
4281 }
4282
4283 /*
4284  * Initialize brcms_c_info default values ...
4285  * may get overrides later in this function
4286  */
4287 static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
4288 {
4289         int i;
4290
4291         /* Save our copy of the chanspec */
4292         wlc->chanspec = ch20mhz_chspec(1);
4293
4294         /* various 802.11g modes */
4295         wlc->shortslot = false;
4296         wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
4297
4298         brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
4299         brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
4300
4301         brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
4302                                BRCMS_PROTECTION_AUTO);
4303         brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
4304         brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
4305                                BRCMS_PROTECTION_AUTO);
4306         brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
4307         brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
4308
4309         brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
4310                                BRCMS_PROTECTION_CTL_OVERLAP);
4311
4312         /* 802.11g draft 4.0 NonERP elt advertisement */
4313         wlc->include_legacy_erp = true;
4314
4315         wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
4316         wlc->stf->txant = ANT_TX_DEF;
4317
4318         wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
4319
4320         wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
4321         for (i = 0; i < NFIFO; i++)
4322                 wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
4323         wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
4324
4325         /* default rate fallback retry limits */
4326         wlc->SFBL = RETRY_SHORT_FB;
4327         wlc->LFBL = RETRY_LONG_FB;
4328
4329         /* default mac retry limits */
4330         wlc->SRL = RETRY_SHORT_DEF;
4331         wlc->LRL = RETRY_LONG_DEF;
4332
4333         /* WME QoS mode is Auto by default */
4334         wlc->pub->_ampdu = AMPDU_AGG_HOST;
4335         wlc->pub->bcmerror = 0;
4336 }
4337
4338 static uint brcms_c_attach_module(struct brcms_c_info *wlc)
4339 {
4340         uint err = 0;
4341         uint unit;
4342         unit = wlc->pub->unit;
4343
4344         wlc->asi = brcms_c_antsel_attach(wlc);
4345         if (wlc->asi == NULL) {
4346                 wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
4347                           "failed\n", unit);
4348                 err = 44;
4349                 goto fail;
4350         }
4351
4352         wlc->ampdu = brcms_c_ampdu_attach(wlc);
4353         if (wlc->ampdu == NULL) {
4354                 wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
4355                           "failed\n", unit);
4356                 err = 50;
4357                 goto fail;
4358         }
4359
4360         if ((brcms_c_stf_attach(wlc) != 0)) {
4361                 wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
4362                           "failed\n", unit);
4363                 err = 68;
4364                 goto fail;
4365         }
4366  fail:
4367         return err;
4368 }
4369
4370 struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
4371 {
4372         return wlc->pub;
4373 }
4374
4375 /* low level attach
4376  *    run backplane attach, init nvram
4377  *    run phy attach
4378  *    initialize software state for each core and band
4379  *    put the whole chip in reset(driver down state), no clock
4380  */
4381 static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4382                           uint unit, bool piomode)
4383 {
4384         struct brcms_hardware *wlc_hw;
4385         uint err = 0;
4386         uint j;
4387         bool wme = false;
4388         struct shared_phy_params sha_params;
4389         struct wiphy *wiphy = wlc->wiphy;
4390         struct pci_dev *pcidev = core->bus->host_pci;
4391         struct ssb_sprom *sprom = &core->bus->sprom;
4392
4393         if (core->bus->hosttype == BCMA_HOSTTYPE_PCI)
4394                 brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
4395                                pcidev->vendor,
4396                                pcidev->device);
4397         else
4398                 brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
4399                                core->bus->boardinfo.vendor,
4400                                core->bus->boardinfo.type);
4401
4402         wme = true;
4403
4404         wlc_hw = wlc->hw;
4405         wlc_hw->wlc = wlc;
4406         wlc_hw->unit = unit;
4407         wlc_hw->band = wlc_hw->bandstate[0];
4408         wlc_hw->_piomode = piomode;
4409
4410         /* populate struct brcms_hardware with default values  */
4411         brcms_b_info_init(wlc_hw);
4412
4413         /*
4414          * Do the hardware portion of the attach. Also initialize software
4415          * state that depends on the particular hardware we are running.
4416          */
4417         wlc_hw->sih = ai_attach(core->bus);
4418         if (wlc_hw->sih == NULL) {
4419                 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
4420                           unit);
4421                 err = 11;
4422                 goto fail;
4423         }
4424
4425         /* verify again the device is supported */
4426         if (!brcms_c_chipmatch(core)) {
4427                 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported device\n",
4428                          unit);
4429                 err = 12;
4430                 goto fail;
4431         }
4432
4433         if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
4434                 wlc_hw->vendorid = pcidev->vendor;
4435                 wlc_hw->deviceid = pcidev->device;
4436         } else {
4437                 wlc_hw->vendorid = core->bus->boardinfo.vendor;
4438                 wlc_hw->deviceid = core->bus->boardinfo.type;
4439         }
4440
4441         wlc_hw->d11core = core;
4442         wlc_hw->corerev = core->id.rev;
4443
4444         /* validate chip, chiprev and corerev */
4445         if (!brcms_c_isgoodchip(wlc_hw)) {
4446                 err = 13;
4447                 goto fail;
4448         }
4449
4450         /* initialize power control registers */
4451         ai_clkctl_init(wlc_hw->sih);
4452
4453         /* request fastclock and force fastclock for the rest of attach
4454          * bring the d11 core out of reset.
4455          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
4456          *   is still false; But it will be called again inside wlc_corereset,
4457          *   after d11 is out of reset.
4458          */
4459         brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4460         brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4461
4462         if (!brcms_b_validate_chip_access(wlc_hw)) {
4463                 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
4464                         "failed\n", unit);
4465                 err = 14;
4466                 goto fail;
4467         }
4468
4469         /* get the board rev, used just below */
4470         j = sprom->board_rev;
4471         /* promote srom boardrev of 0xFF to 1 */
4472         if (j == BOARDREV_PROMOTABLE)
4473                 j = BOARDREV_PROMOTED;
4474         wlc_hw->boardrev = (u16) j;
4475         if (!brcms_c_validboardtype(wlc_hw)) {
4476                 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
4477                           "board type (0x%x)" " or revision level (0x%x)\n",
4478                           unit, ai_get_boardtype(wlc_hw->sih),
4479                           wlc_hw->boardrev);
4480                 err = 15;
4481                 goto fail;
4482         }
4483         wlc_hw->sromrev = sprom->revision;
4484         wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
4485         wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
4486
4487         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
4488                 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
4489
4490         /* check device id(srom, nvram etc.) to set bands */
4491         if (wlc_hw->deviceid == BCM43224_D11N_ID ||
4492             wlc_hw->deviceid == BCM43224_D11N_ID_VEN1 ||
4493             wlc_hw->deviceid == BCM43224_CHIP_ID)
4494                 /* Dualband boards */
4495                 wlc_hw->_nbands = 2;
4496         else
4497                 wlc_hw->_nbands = 1;
4498
4499         if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225))
4500                 wlc_hw->_nbands = 1;
4501
4502         /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
4503          * unconditionally does the init of these values
4504          */
4505         wlc->vendorid = wlc_hw->vendorid;
4506         wlc->deviceid = wlc_hw->deviceid;
4507         wlc->pub->sih = wlc_hw->sih;
4508         wlc->pub->corerev = wlc_hw->corerev;
4509         wlc->pub->sromrev = wlc_hw->sromrev;
4510         wlc->pub->boardrev = wlc_hw->boardrev;
4511         wlc->pub->boardflags = wlc_hw->boardflags;
4512         wlc->pub->boardflags2 = wlc_hw->boardflags2;
4513         wlc->pub->_nbands = wlc_hw->_nbands;
4514
4515         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
4516
4517         if (wlc_hw->physhim == NULL) {
4518                 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
4519                         "failed\n", unit);
4520                 err = 25;
4521                 goto fail;
4522         }
4523
4524         /* pass all the parameters to wlc_phy_shared_attach in one struct */
4525         sha_params.sih = wlc_hw->sih;
4526         sha_params.physhim = wlc_hw->physhim;
4527         sha_params.unit = unit;
4528         sha_params.corerev = wlc_hw->corerev;
4529         sha_params.vid = wlc_hw->vendorid;
4530         sha_params.did = wlc_hw->deviceid;
4531         sha_params.chip = ai_get_chip_id(wlc_hw->sih);
4532         sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
4533         sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
4534         sha_params.sromrev = wlc_hw->sromrev;
4535         sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
4536         sha_params.boardrev = wlc_hw->boardrev;
4537         sha_params.boardflags = wlc_hw->boardflags;
4538         sha_params.boardflags2 = wlc_hw->boardflags2;
4539
4540         /* alloc and save pointer to shared phy state area */
4541         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
4542         if (!wlc_hw->phy_sh) {
4543                 err = 16;
4544                 goto fail;
4545         }
4546
4547         /* initialize software state for each core and band */
4548         for (j = 0; j < wlc_hw->_nbands; j++) {
4549                 /*
4550                  * band0 is always 2.4Ghz
4551                  * band1, if present, is 5Ghz
4552                  */
4553
4554                 brcms_c_setxband(wlc_hw, j);
4555
4556                 wlc_hw->band->bandunit = j;
4557                 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4558                 wlc->band->bandunit = j;
4559                 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4560                 wlc->core->coreidx = core->core_index;
4561
4562                 wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
4563                 wlc_hw->machwcap_backup = wlc_hw->machwcap;
4564
4565                 /* init tx fifo size */
4566                 WARN_ON((wlc_hw->corerev - XMTFIFOTBL_STARTREV) < 0 ||
4567                         (wlc_hw->corerev - XMTFIFOTBL_STARTREV) >
4568                                 ARRAY_SIZE(xmtfifo_sz));
4569                 wlc_hw->xmtfifo_sz =
4570                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
4571                 WARN_ON(!wlc_hw->xmtfifo_sz[0]);
4572
4573                 /* Get a phy for this band */
4574                 wlc_hw->band->pi =
4575                         wlc_phy_attach(wlc_hw->phy_sh, core,
4576                                        wlc_hw->band->bandtype,
4577                                        wlc->wiphy);
4578                 if (wlc_hw->band->pi == NULL) {
4579                         wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
4580                                   "attach failed\n", unit);
4581                         err = 17;
4582                         goto fail;
4583                 }
4584
4585                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
4586
4587                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
4588                                        &wlc_hw->band->phyrev,
4589                                        &wlc_hw->band->radioid,
4590                                        &wlc_hw->band->radiorev);
4591                 wlc_hw->band->abgphy_encore =
4592                     wlc_phy_get_encore(wlc_hw->band->pi);
4593                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
4594                 wlc_hw->band->core_flags =
4595                     wlc_phy_get_coreflags(wlc_hw->band->pi);
4596
4597                 /* verify good phy_type & supported phy revision */
4598                 if (BRCMS_ISNPHY(wlc_hw->band)) {
4599                         if (NCONF_HAS(wlc_hw->band->phyrev))
4600                                 goto good_phy;
4601                         else
4602                                 goto bad_phy;
4603                 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
4604                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
4605                                 goto good_phy;
4606                         else
4607                                 goto bad_phy;
4608                 } else {
4609  bad_phy:
4610                         wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
4611                                   "phy type/rev (%d/%d)\n", unit,
4612                                   wlc_hw->band->phytype, wlc_hw->band->phyrev);
4613                         err = 18;
4614                         goto fail;
4615                 }
4616
4617  good_phy:
4618                 /*
4619                  * BMAC_NOTE: wlc->band->pi should not be set below and should
4620                  * be done in the high level attach. However we can not make
4621                  * that change until all low level access is changed to
4622                  * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
4623                  * keeping wlc_hw->band->pi as well for incremental update of
4624                  * low level fns, and cut over low only init when all fns
4625                  * updated.
4626                  */
4627                 wlc->band->pi = wlc_hw->band->pi;
4628                 wlc->band->phytype = wlc_hw->band->phytype;
4629                 wlc->band->phyrev = wlc_hw->band->phyrev;
4630                 wlc->band->radioid = wlc_hw->band->radioid;
4631                 wlc->band->radiorev = wlc_hw->band->radiorev;
4632
4633                 /* default contention windows size limits */
4634                 wlc_hw->band->CWmin = APHY_CWMIN;
4635                 wlc_hw->band->CWmax = PHY_CWMAX;
4636
4637                 if (!brcms_b_attach_dmapio(wlc, j, wme)) {
4638                         err = 19;
4639                         goto fail;
4640                 }
4641         }
4642
4643         /* disable core to match driver "down" state */
4644         brcms_c_coredisable(wlc_hw);
4645
4646         /* Match driver "down" state */
4647         ai_pci_down(wlc_hw->sih);
4648
4649         /* turn off pll and xtal to match driver "down" state */
4650         brcms_b_xtal(wlc_hw, OFF);
4651
4652         /* *******************************************************************
4653          * The hardware is in the DOWN state at this point. D11 core
4654          * or cores are in reset with clocks off, and the board PLLs
4655          * are off if possible.
4656          *
4657          * Beyond this point, wlc->sbclk == false and chip registers
4658          * should not be touched.
4659          *********************************************************************
4660          */
4661
4662         /* init etheraddr state variables */
4663         brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
4664
4665         if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
4666             is_zero_ether_addr(wlc_hw->etheraddr)) {
4667                 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
4668                           unit);
4669                 err = 22;
4670                 goto fail;
4671         }
4672
4673         brcms_dbg_info(wlc_hw->d11core, "deviceid 0x%x nbands %d board 0x%x\n",
4674                        wlc_hw->deviceid, wlc_hw->_nbands,
4675                        ai_get_boardtype(wlc_hw->sih));
4676
4677         return err;
4678
4679  fail:
4680         wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
4681                   err);
4682         return err;
4683 }
4684
4685 static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc)
4686 {
4687         uint unit;
4688         unit = wlc->pub->unit;
4689
4690         if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
4691                 /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
4692                 wlc->band->antgain = 8;
4693         } else if (wlc->band->antgain == -1) {
4694                 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4695                           " srom, using 2dB\n", unit, __func__);
4696                 wlc->band->antgain = 8;
4697         } else {
4698                 s8 gain, fract;
4699                 /* Older sroms specified gain in whole dbm only.  In order
4700                  * be able to specify qdbm granularity and remain backward
4701                  * compatible the whole dbms are now encoded in only
4702                  * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
4703                  * 6 bit signed number ranges from -32 - 31.
4704                  *
4705                  * Examples:
4706                  * 0x1 = 1 db,
4707                  * 0xc1 = 1.75 db (1 + 3 quarters),
4708                  * 0x3f = -1 (-1 + 0 quarters),
4709                  * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
4710                  * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
4711                  */
4712                 gain = wlc->band->antgain & 0x3f;
4713                 gain <<= 2;     /* Sign extend */
4714                 gain >>= 2;
4715                 fract = (wlc->band->antgain & 0xc0) >> 6;
4716                 wlc->band->antgain = 4 * gain + fract;
4717         }
4718 }
4719
4720 static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
4721 {
4722         int aa;
4723         uint unit;
4724         int bandtype;
4725         struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
4726
4727         unit = wlc->pub->unit;
4728         bandtype = wlc->band->bandtype;
4729
4730         /* get antennas available */
4731         if (bandtype == BRCM_BAND_5G)
4732                 aa = sprom->ant_available_a;
4733         else
4734                 aa = sprom->ant_available_bg;
4735
4736         if ((aa < 1) || (aa > 15)) {
4737                 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4738                           " srom (0x%x), using 3\n", unit, __func__, aa);
4739                 aa = 3;
4740         }
4741
4742         /* reset the defaults if we have a single antenna */
4743         if (aa == 1) {
4744                 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
4745                 wlc->stf->txant = ANT_TX_FORCE_0;
4746         } else if (aa == 2) {
4747                 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
4748                 wlc->stf->txant = ANT_TX_FORCE_1;
4749         } else {
4750         }
4751
4752         /* Compute Antenna Gain */
4753         if (bandtype == BRCM_BAND_5G)
4754                 wlc->band->antgain = sprom->antenna_gain.a1;
4755         else
4756                 wlc->band->antgain = sprom->antenna_gain.a0;
4757
4758         brcms_c_attach_antgain_init(wlc);
4759
4760         return true;
4761 }
4762
4763 static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
4764 {
4765         u16 chanspec;
4766         struct brcms_band *band;
4767         struct brcms_bss_info *bi = wlc->default_bss;
4768
4769         /* init default and target BSS with some sane initial values */
4770         memset(bi, 0, sizeof(*bi));
4771         bi->beacon_period = BEACON_INTERVAL_DEFAULT;
4772
4773         /* fill the default channel as the first valid channel
4774          * starting from the 2G channels
4775          */
4776         chanspec = ch20mhz_chspec(1);
4777         wlc->home_chanspec = bi->chanspec = chanspec;
4778
4779         /* find the band of our default channel */
4780         band = wlc->band;
4781         if (wlc->pub->_nbands > 1 &&
4782             band->bandunit != chspec_bandunit(chanspec))
4783                 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
4784
4785         /* init bss rates to the band specific default rate set */
4786         brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
4787                 band->bandtype, false, BRCMS_RATE_MASK_FULL,
4788                 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
4789                 brcms_chspec_bw(chanspec), wlc->stf->txstreams);
4790
4791         if (wlc->pub->_n_enab & SUPPORT_11N)
4792                 bi->flags |= BRCMS_BSS_HT;
4793 }
4794
4795 static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
4796 {
4797         uint i;
4798         struct brcms_band *band;
4799
4800         for (i = 0; i < wlc->pub->_nbands; i++) {
4801                 band = wlc->bandstate[i];
4802                 if (band->bandtype == BRCM_BAND_5G) {
4803                         if ((bwcap == BRCMS_N_BW_40ALL)
4804                             || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
4805                                 band->mimo_cap_40 = true;
4806                         else
4807                                 band->mimo_cap_40 = false;
4808                 } else {
4809                         if (bwcap == BRCMS_N_BW_40ALL)
4810                                 band->mimo_cap_40 = true;
4811                         else
4812                                 band->mimo_cap_40 = false;
4813                 }
4814         }
4815 }
4816
4817 static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
4818 {
4819         /* free timer state */
4820         if (wlc->wdtimer) {
4821                 brcms_free_timer(wlc->wdtimer);
4822                 wlc->wdtimer = NULL;
4823         }
4824         if (wlc->radio_timer) {
4825                 brcms_free_timer(wlc->radio_timer);
4826                 wlc->radio_timer = NULL;
4827         }
4828 }
4829
4830 static void brcms_c_detach_module(struct brcms_c_info *wlc)
4831 {
4832         if (wlc->asi) {
4833                 brcms_c_antsel_detach(wlc->asi);
4834                 wlc->asi = NULL;
4835         }
4836
4837         if (wlc->ampdu) {
4838                 brcms_c_ampdu_detach(wlc->ampdu);
4839                 wlc->ampdu = NULL;
4840         }
4841
4842         brcms_c_stf_detach(wlc);
4843 }
4844
4845 /*
4846  * low level detach
4847  */
4848 static int brcms_b_detach(struct brcms_c_info *wlc)
4849 {
4850         uint i;
4851         struct brcms_hw_band *band;
4852         struct brcms_hardware *wlc_hw = wlc->hw;
4853         int callbacks;
4854
4855         callbacks = 0;
4856
4857         brcms_b_detach_dmapio(wlc_hw);
4858
4859         band = wlc_hw->band;
4860         for (i = 0; i < wlc_hw->_nbands; i++) {
4861                 if (band->pi) {
4862                         /* Detach this band's phy */
4863                         wlc_phy_detach(band->pi);
4864                         band->pi = NULL;
4865                 }
4866                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
4867         }
4868
4869         /* Free shared phy state */
4870         kfree(wlc_hw->phy_sh);
4871
4872         wlc_phy_shim_detach(wlc_hw->physhim);
4873
4874         if (wlc_hw->sih) {
4875                 ai_detach(wlc_hw->sih);
4876                 wlc_hw->sih = NULL;
4877         }
4878
4879         return callbacks;
4880
4881 }
4882
4883 /*
4884  * Return a count of the number of driver callbacks still pending.
4885  *
4886  * General policy is that brcms_c_detach can only dealloc/free software states.
4887  * It can NOT touch hardware registers since the d11core may be in reset and
4888  * clock may not be available.
4889  * One exception is sb register access, which is possible if crystal is turned
4890  * on after "down" state, driver should avoid software timer with the exception
4891  * of radio_monitor.
4892  */
4893 uint brcms_c_detach(struct brcms_c_info *wlc)
4894 {
4895         uint callbacks = 0;
4896
4897         if (wlc == NULL)
4898                 return 0;
4899
4900         callbacks += brcms_b_detach(wlc);
4901
4902         /* delete software timers */
4903         if (!brcms_c_radio_monitor_stop(wlc))
4904                 callbacks++;
4905
4906         brcms_c_channel_mgr_detach(wlc->cmi);
4907
4908         brcms_c_timers_deinit(wlc);
4909
4910         brcms_c_detach_module(wlc);
4911
4912         brcms_c_detach_mfree(wlc);
4913         return callbacks;
4914 }
4915
4916 /* update state that depends on the current value of "ap" */
4917 static void brcms_c_ap_upd(struct brcms_c_info *wlc)
4918 {
4919         /* STA-BSS; short capable */
4920         wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
4921 }
4922
4923 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
4924 static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
4925 {
4926         if (wlc_hw->wlc->pub->hw_up)
4927                 return;
4928
4929         brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4930
4931         /*
4932          * Enable pll and xtal, initialize the power control registers,
4933          * and force fastclock for the remainder of brcms_c_up().
4934          */
4935         brcms_b_xtal(wlc_hw, ON);
4936         ai_clkctl_init(wlc_hw->sih);
4937         brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4938
4939         /*
4940          * TODO: test suspend/resume
4941          *
4942          * AI chip doesn't restore bar0win2 on
4943          * hibernation/resume, need sw fixup
4944          */
4945
4946         /*
4947          * Inform phy that a POR reset has occurred so
4948          * it does a complete phy init
4949          */
4950         wlc_phy_por_inform(wlc_hw->band->pi);
4951
4952         wlc_hw->ucode_loaded = false;
4953         wlc_hw->wlc->pub->hw_up = true;
4954
4955         if ((wlc_hw->boardflags & BFL_FEM)
4956             && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
4957                 if (!
4958                     (wlc_hw->boardrev >= 0x1250
4959                      && (wlc_hw->boardflags & BFL_FEM_BT)))
4960                         ai_epa_4313war(wlc_hw->sih);
4961         }
4962 }
4963
4964 static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
4965 {
4966         brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4967
4968         /*
4969          * Enable pll and xtal, initialize the power control registers,
4970          * and force fastclock for the remainder of brcms_c_up().
4971          */
4972         brcms_b_xtal(wlc_hw, ON);
4973         ai_clkctl_init(wlc_hw->sih);
4974         brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4975
4976         /*
4977          * Configure pci/pcmcia here instead of in brcms_c_attach()
4978          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
4979          */
4980         bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
4981                               true);
4982
4983         /*
4984          * Need to read the hwradio status here to cover the case where the
4985          * system is loaded with the hw radio disabled. We do not want to
4986          * bring the driver up in this case.
4987          */
4988         if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
4989                 /* put SB PCI in down state again */
4990                 ai_pci_down(wlc_hw->sih);
4991                 brcms_b_xtal(wlc_hw, OFF);
4992                 return -ENOMEDIUM;
4993         }
4994
4995         ai_pci_up(wlc_hw->sih);
4996
4997         /* reset the d11 core */
4998         brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4999
5000         return 0;
5001 }
5002
5003 static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
5004 {
5005         wlc_hw->up = true;
5006         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
5007
5008         /* FULLY enable dynamic power control and d11 core interrupt */
5009         brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
5010         brcms_intrson(wlc_hw->wlc->wl);
5011         return 0;
5012 }
5013
5014 /*
5015  * Write WME tunable parameters for retransmit/max rate
5016  * from wlc struct to ucode
5017  */
5018 static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
5019 {
5020         int ac;
5021
5022         /* Need clock to do this */
5023         if (!wlc->clk)
5024                 return;
5025
5026         for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
5027                 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
5028                                   wlc->wme_retries[ac]);
5029 }
5030
5031 /* make interface operational */
5032 int brcms_c_up(struct brcms_c_info *wlc)
5033 {
5034         struct ieee80211_channel *ch;
5035
5036         brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
5037
5038         /* HW is turned off so don't try to access it */
5039         if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
5040                 return -ENOMEDIUM;
5041
5042         if (!wlc->pub->hw_up) {
5043                 brcms_b_hw_up(wlc->hw);
5044                 wlc->pub->hw_up = true;
5045         }
5046
5047         if ((wlc->pub->boardflags & BFL_FEM)
5048             && (ai_get_chip_id(wlc->hw->sih) == BCMA_CHIP_ID_BCM4313)) {
5049                 if (wlc->pub->boardrev >= 0x1250
5050                     && (wlc->pub->boardflags & BFL_FEM_BT))
5051                         brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
5052                                 MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
5053                 else
5054                         brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
5055                                     MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
5056         }
5057
5058         /*
5059          * Need to read the hwradio status here to cover the case where the
5060          * system is loaded with the hw radio disabled. We do not want to bring
5061          * the driver up in this case. If radio is disabled, abort up, lower
5062          * power, start radio timer and return 0(for NDIS) don't call
5063          * radio_update to avoid looping brcms_c_up.
5064          *
5065          * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
5066          */
5067         if (!wlc->pub->radio_disabled) {
5068                 int status = brcms_b_up_prep(wlc->hw);
5069                 if (status == -ENOMEDIUM) {
5070                         if (!mboolisset
5071                             (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
5072                                 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
5073                                 mboolset(wlc->pub->radio_disabled,
5074                                          WL_RADIO_HW_DISABLE);
5075
5076                                 if (bsscfg->enable && bsscfg->BSS)
5077                                         brcms_err(wlc->hw->d11core,
5078                                                   "wl%d: up: rfdisable -> "
5079                                                   "bsscfg_disable()\n",
5080                                                    wlc->pub->unit);
5081                         }
5082                 }
5083         }
5084
5085         if (wlc->pub->radio_disabled) {
5086                 brcms_c_radio_monitor_start(wlc);
5087                 return 0;
5088         }
5089
5090         /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
5091         wlc->clk = true;
5092
5093         brcms_c_radio_monitor_stop(wlc);
5094
5095         /* Set EDCF hostflags */
5096         brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
5097
5098         brcms_init(wlc->wl);
5099         wlc->pub->up = true;
5100
5101         if (wlc->bandinit_pending) {
5102                 ch = wlc->pub->ieee_hw->conf.channel;
5103                 brcms_c_suspend_mac_and_wait(wlc);
5104                 brcms_c_set_chanspec(wlc, ch20mhz_chspec(ch->hw_value));
5105                 wlc->bandinit_pending = false;
5106                 brcms_c_enable_mac(wlc);
5107         }
5108
5109         brcms_b_up_finish(wlc->hw);
5110
5111         /* Program the TX wme params with the current settings */
5112         brcms_c_wme_retries_write(wlc);
5113
5114         /* start one second watchdog timer */
5115         brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
5116         wlc->WDarmed = true;
5117
5118         /* ensure antenna config is up to date */
5119         brcms_c_stf_phy_txant_upd(wlc);
5120         /* ensure LDPC config is in sync */
5121         brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
5122
5123         return 0;
5124 }
5125
5126 static uint brcms_c_down_del_timer(struct brcms_c_info *wlc)
5127 {
5128         uint callbacks = 0;
5129
5130         return callbacks;
5131 }
5132
5133 static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
5134 {
5135         bool dev_gone;
5136         uint callbacks = 0;
5137
5138         if (!wlc_hw->up)
5139                 return callbacks;
5140
5141         dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5142
5143         /* disable interrupts */
5144         if (dev_gone)
5145                 wlc_hw->wlc->macintmask = 0;
5146         else {
5147                 /* now disable interrupts */
5148                 brcms_intrsoff(wlc_hw->wlc->wl);
5149
5150                 /* ensure we're running on the pll clock again */
5151                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5152         }
5153         /* down phy at the last of this stage */
5154         callbacks += wlc_phy_down(wlc_hw->band->pi);
5155
5156         return callbacks;
5157 }
5158
5159 static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
5160 {
5161         uint callbacks = 0;
5162         bool dev_gone;
5163
5164         if (!wlc_hw->up)
5165                 return callbacks;
5166
5167         wlc_hw->up = false;
5168         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
5169
5170         dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5171
5172         if (dev_gone) {
5173                 wlc_hw->sbclk = false;
5174                 wlc_hw->clk = false;
5175                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
5176
5177                 /* reclaim any posted packets */
5178                 brcms_c_flushqueues(wlc_hw->wlc);
5179         } else {
5180
5181                 /* Reset and disable the core */
5182                 if (bcma_core_is_enabled(wlc_hw->d11core)) {
5183                         if (bcma_read32(wlc_hw->d11core,
5184                                         D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
5185                                 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
5186                         callbacks += brcms_reset(wlc_hw->wlc->wl);
5187                         brcms_c_coredisable(wlc_hw);
5188                 }
5189
5190                 /* turn off primary xtal and pll */
5191                 if (!wlc_hw->noreset) {
5192                         ai_pci_down(wlc_hw->sih);
5193                         brcms_b_xtal(wlc_hw, OFF);
5194                 }
5195         }
5196
5197         return callbacks;
5198 }
5199
5200 /*
5201  * Mark the interface nonoperational, stop the software mechanisms,
5202  * disable the hardware, free any transient buffer state.
5203  * Return a count of the number of driver callbacks still pending.
5204  */
5205 uint brcms_c_down(struct brcms_c_info *wlc)
5206 {
5207
5208         uint callbacks = 0;
5209         int i;
5210         bool dev_gone = false;
5211
5212         brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
5213
5214         /* check if we are already in the going down path */
5215         if (wlc->going_down) {
5216                 brcms_err(wlc->hw->d11core,
5217                           "wl%d: %s: Driver going down so return\n",
5218                           wlc->pub->unit, __func__);
5219                 return 0;
5220         }
5221         if (!wlc->pub->up)
5222                 return callbacks;
5223
5224         wlc->going_down = true;
5225
5226         callbacks += brcms_b_bmac_down_prep(wlc->hw);
5227
5228         dev_gone = brcms_deviceremoved(wlc);
5229
5230         /* Call any registered down handlers */
5231         for (i = 0; i < BRCMS_MAXMODULES; i++) {
5232                 if (wlc->modulecb[i].down_fn)
5233                         callbacks +=
5234                             wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
5235         }
5236
5237         /* cancel the watchdog timer */
5238         if (wlc->WDarmed) {
5239                 if (!brcms_del_timer(wlc->wdtimer))
5240                         callbacks++;
5241                 wlc->WDarmed = false;
5242         }
5243         /* cancel all other timers */
5244         callbacks += brcms_c_down_del_timer(wlc);
5245
5246         wlc->pub->up = false;
5247
5248         wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
5249
5250         callbacks += brcms_b_down_finish(wlc->hw);
5251
5252         /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
5253         wlc->clk = false;
5254
5255         wlc->going_down = false;
5256         return callbacks;
5257 }
5258
5259 /* Set the current gmode configuration */
5260 int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
5261 {
5262         int ret = 0;
5263         uint i;
5264         struct brcms_c_rateset rs;
5265         /* Default to 54g Auto */
5266         /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
5267         s8 shortslot = BRCMS_SHORTSLOT_AUTO;
5268         bool shortslot_restrict = false; /* Restrict association to stations
5269                                           * that support shortslot
5270                                           */
5271         bool ofdm_basic = false;        /* Make 6, 12, and 24 basic rates */
5272         /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
5273         int preamble = BRCMS_PLCP_LONG;
5274         bool preamble_restrict = false; /* Restrict association to stations
5275                                          * that support short preambles
5276                                          */
5277         struct brcms_band *band;
5278
5279         /* if N-support is enabled, allow Gmode set as long as requested
5280          * Gmode is not GMODE_LEGACY_B
5281          */
5282         if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
5283                 return -ENOTSUPP;
5284
5285         /* verify that we are dealing with 2G band and grab the band pointer */
5286         if (wlc->band->bandtype == BRCM_BAND_2G)
5287                 band = wlc->band;
5288         else if ((wlc->pub->_nbands > 1) &&
5289                  (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
5290                 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
5291         else
5292                 return -EINVAL;
5293
5294         /* update configuration value */
5295         if (config)
5296                 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
5297
5298         /* Clear rateset override */
5299         memset(&rs, 0, sizeof(rs));
5300
5301         switch (gmode) {
5302         case GMODE_LEGACY_B:
5303                 shortslot = BRCMS_SHORTSLOT_OFF;
5304                 brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
5305
5306                 break;
5307
5308         case GMODE_LRS:
5309                 break;
5310
5311         case GMODE_AUTO:
5312                 /* Accept defaults */
5313                 break;
5314
5315         case GMODE_ONLY:
5316                 ofdm_basic = true;
5317                 preamble = BRCMS_PLCP_SHORT;
5318                 preamble_restrict = true;
5319                 break;
5320
5321         case GMODE_PERFORMANCE:
5322                 shortslot = BRCMS_SHORTSLOT_ON;
5323                 shortslot_restrict = true;
5324                 ofdm_basic = true;
5325                 preamble = BRCMS_PLCP_SHORT;
5326                 preamble_restrict = true;
5327                 break;
5328
5329         default:
5330                 /* Error */
5331                 brcms_err(wlc->hw->d11core, "wl%d: %s: invalid gmode %d\n",
5332                           wlc->pub->unit, __func__, gmode);
5333                 return -ENOTSUPP;
5334         }
5335
5336         band->gmode = gmode;
5337
5338         wlc->shortslot_override = shortslot;
5339
5340         /* Use the default 11g rateset */
5341         if (!rs.count)
5342                 brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
5343
5344         if (ofdm_basic) {
5345                 for (i = 0; i < rs.count; i++) {
5346                         if (rs.rates[i] == BRCM_RATE_6M
5347                             || rs.rates[i] == BRCM_RATE_12M
5348                             || rs.rates[i] == BRCM_RATE_24M)
5349                                 rs.rates[i] |= BRCMS_RATE_FLAG;
5350                 }
5351         }
5352
5353         /* Set default bss rateset */
5354         wlc->default_bss->rateset.count = rs.count;
5355         memcpy(wlc->default_bss->rateset.rates, rs.rates,
5356                sizeof(wlc->default_bss->rateset.rates));
5357
5358         return ret;
5359 }
5360
5361 int brcms_c_set_nmode(struct brcms_c_info *wlc)
5362 {
5363         uint i;
5364         s32 nmode = AUTO;
5365
5366         if (wlc->stf->txstreams == WL_11N_3x3)
5367                 nmode = WL_11N_3x3;
5368         else
5369                 nmode = WL_11N_2x2;
5370
5371         /* force GMODE_AUTO if NMODE is ON */
5372         brcms_c_set_gmode(wlc, GMODE_AUTO, true);
5373         if (nmode == WL_11N_3x3)
5374                 wlc->pub->_n_enab = SUPPORT_HT;
5375         else
5376                 wlc->pub->_n_enab = SUPPORT_11N;
5377         wlc->default_bss->flags |= BRCMS_BSS_HT;
5378         /* add the mcs rates to the default and hw ratesets */
5379         brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
5380                               wlc->stf->txstreams);
5381         for (i = 0; i < wlc->pub->_nbands; i++)
5382                 memcpy(wlc->bandstate[i]->hw_rateset.mcs,
5383                        wlc->default_bss->rateset.mcs, MCSSET_LEN);
5384
5385         return 0;
5386 }
5387
5388 static int
5389 brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
5390                              struct brcms_c_rateset *rs_arg)
5391 {
5392         struct brcms_c_rateset rs, new;
5393         uint bandunit;
5394
5395         memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
5396
5397         /* check for bad count value */
5398         if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
5399                 return -EINVAL;
5400
5401         /* try the current band */
5402         bandunit = wlc->band->bandunit;
5403         memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5404         if (brcms_c_rate_hwrs_filter_sort_validate
5405             (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
5406              wlc->stf->txstreams))
5407                 goto good;
5408
5409         /* try the other band */
5410         if (brcms_is_mband_unlocked(wlc)) {
5411                 bandunit = OTHERBANDUNIT(wlc);
5412                 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5413                 if (brcms_c_rate_hwrs_filter_sort_validate(&new,
5414                                                        &wlc->
5415                                                        bandstate[bandunit]->
5416                                                        hw_rateset, true,
5417                                                        wlc->stf->txstreams))
5418                         goto good;
5419         }
5420
5421         return -EBADE;
5422
5423  good:
5424         /* apply new rateset */
5425         memcpy(&wlc->default_bss->rateset, &new,
5426                sizeof(struct brcms_c_rateset));
5427         memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
5428                sizeof(struct brcms_c_rateset));
5429         return 0;
5430 }
5431
5432 static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
5433 {
5434         u8 r;
5435         bool war = false;
5436
5437         if (wlc->bsscfg->associated)
5438                 r = wlc->bsscfg->current_bss->rateset.rates[0];
5439         else
5440                 r = wlc->default_bss->rateset.rates[0];
5441
5442         wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
5443 }
5444
5445 int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
5446 {
5447         u16 chspec = ch20mhz_chspec(channel);
5448
5449         if (channel < 0 || channel > MAXCHANNEL)
5450                 return -EINVAL;
5451
5452         if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
5453                 return -EINVAL;
5454
5455
5456         if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
5457                 if (wlc->band->bandunit != chspec_bandunit(chspec))
5458                         wlc->bandinit_pending = true;
5459                 else
5460                         wlc->bandinit_pending = false;
5461         }
5462
5463         wlc->default_bss->chanspec = chspec;
5464         /* brcms_c_BSSinit() will sanitize the rateset before
5465          * using it.. */
5466         if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
5467                 brcms_c_set_home_chanspec(wlc, chspec);
5468                 brcms_c_suspend_mac_and_wait(wlc);
5469                 brcms_c_set_chanspec(wlc, chspec);
5470                 brcms_c_enable_mac(wlc);
5471         }
5472         return 0;
5473 }
5474
5475 int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
5476 {
5477         int ac;
5478
5479         if (srl < 1 || srl > RETRY_SHORT_MAX ||
5480             lrl < 1 || lrl > RETRY_SHORT_MAX)
5481                 return -EINVAL;
5482
5483         wlc->SRL = srl;
5484         wlc->LRL = lrl;
5485
5486         brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
5487
5488         for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
5489                 wlc->wme_retries[ac] =  SFIELD(wlc->wme_retries[ac],
5490                                                EDCF_SHORT,  wlc->SRL);
5491                 wlc->wme_retries[ac] =  SFIELD(wlc->wme_retries[ac],
5492                                                EDCF_LONG, wlc->LRL);
5493         }
5494         brcms_c_wme_retries_write(wlc);
5495
5496         return 0;
5497 }
5498
5499 void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
5500                                  struct brcm_rateset *currs)
5501 {
5502         struct brcms_c_rateset *rs;
5503
5504         if (wlc->pub->associated)
5505                 rs = &wlc->bsscfg->current_bss->rateset;
5506         else
5507                 rs = &wlc->default_bss->rateset;
5508
5509         /* Copy only legacy rateset section */
5510         currs->count = rs->count;
5511         memcpy(&currs->rates, &rs->rates, rs->count);
5512 }
5513
5514 int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
5515 {
5516         struct brcms_c_rateset internal_rs;
5517         int bcmerror;
5518
5519         if (rs->count > BRCMS_NUMRATES)
5520                 return -ENOBUFS;
5521
5522         memset(&internal_rs, 0, sizeof(internal_rs));
5523
5524         /* Copy only legacy rateset section */
5525         internal_rs.count = rs->count;
5526         memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
5527
5528         /* merge rateset coming in with the current mcsset */
5529         if (wlc->pub->_n_enab & SUPPORT_11N) {
5530                 struct brcms_bss_info *mcsset_bss;
5531                 if (wlc->bsscfg->associated)
5532                         mcsset_bss = wlc->bsscfg->current_bss;
5533                 else
5534                         mcsset_bss = wlc->default_bss;
5535                 memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
5536                        MCSSET_LEN);
5537         }
5538
5539         bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
5540         if (!bcmerror)
5541                 brcms_c_ofdm_rateset_war(wlc);
5542
5543         return bcmerror;
5544 }
5545
5546 static void brcms_c_time_lock(struct brcms_c_info *wlc)
5547 {
5548         bcma_set32(wlc->hw->d11core, D11REGOFFS(maccontrol), MCTL_TBTTHOLD);
5549         /* Commit the write */
5550         bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
5551 }
5552
5553 static void brcms_c_time_unlock(struct brcms_c_info *wlc)
5554 {
5555         bcma_mask32(wlc->hw->d11core, D11REGOFFS(maccontrol), ~MCTL_TBTTHOLD);
5556         /* Commit the write */
5557         bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
5558 }
5559
5560 int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
5561 {
5562         if (period == 0)
5563                 return -EINVAL;
5564
5565         wlc->default_bss->beacon_period = period;
5566         return 0;
5567 }
5568
5569 u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
5570 {
5571         return wlc->band->phytype;
5572 }
5573
5574 void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
5575 {
5576         wlc->shortslot_override = sslot_override;
5577
5578         /*
5579          * shortslot is an 11g feature, so no more work if we are
5580          * currently on the 5G band
5581          */
5582         if (wlc->band->bandtype == BRCM_BAND_5G)
5583                 return;
5584
5585         if (wlc->pub->up && wlc->pub->associated) {
5586                 /* let watchdog or beacon processing update shortslot */
5587         } else if (wlc->pub->up) {
5588                 /* unassociated shortslot is off */
5589                 brcms_c_switch_shortslot(wlc, false);
5590         } else {
5591                 /* driver is down, so just update the brcms_c_info
5592                  * value */
5593                 if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
5594                         wlc->shortslot = false;
5595                 else
5596                         wlc->shortslot =
5597                             (wlc->shortslot_override ==
5598                              BRCMS_SHORTSLOT_ON);
5599         }
5600 }
5601
5602 /*
5603  * register watchdog and down handlers.
5604  */
5605 int brcms_c_module_register(struct brcms_pub *pub,
5606                             const char *name, struct brcms_info *hdl,
5607                             int (*d_fn)(void *handle))
5608 {
5609         struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5610         int i;
5611
5612         /* find an empty entry and just add, no duplication check! */
5613         for (i = 0; i < BRCMS_MAXMODULES; i++) {
5614                 if (wlc->modulecb[i].name[0] == '\0') {
5615                         strncpy(wlc->modulecb[i].name, name,
5616                                 sizeof(wlc->modulecb[i].name) - 1);
5617                         wlc->modulecb[i].hdl = hdl;
5618                         wlc->modulecb[i].down_fn = d_fn;
5619                         return 0;
5620                 }
5621         }
5622
5623         return -ENOSR;
5624 }
5625
5626 /* unregister module callbacks */
5627 int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
5628                               struct brcms_info *hdl)
5629 {
5630         struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5631         int i;
5632
5633         if (wlc == NULL)
5634                 return -ENODATA;
5635
5636         for (i = 0; i < BRCMS_MAXMODULES; i++) {
5637                 if (!strcmp(wlc->modulecb[i].name, name) &&
5638                     (wlc->modulecb[i].hdl == hdl)) {
5639                         memset(&wlc->modulecb[i], 0, sizeof(wlc->modulecb[i]));
5640                         return 0;
5641                 }
5642         }
5643
5644         /* table not found! */
5645         return -ENODATA;
5646 }
5647
5648 static bool brcms_c_chipmatch_pci(struct bcma_device *core)
5649 {
5650         struct pci_dev *pcidev = core->bus->host_pci;
5651         u16 vendor = pcidev->vendor;
5652         u16 device = pcidev->device;
5653
5654         if (vendor != PCI_VENDOR_ID_BROADCOM) {
5655                 pr_err("unknown vendor id %04x\n", vendor);
5656                 return false;
5657         }
5658
5659         if (device == BCM43224_D11N_ID_VEN1 || device == BCM43224_CHIP_ID)
5660                 return true;
5661         if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
5662                 return true;
5663         if (device == BCM4313_D11N2G_ID)
5664                 return true;
5665         if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
5666                 return true;
5667
5668         pr_err("unknown device id %04x\n", device);
5669         return false;
5670 }
5671
5672 static bool brcms_c_chipmatch_soc(struct bcma_device *core)
5673 {
5674         struct bcma_chipinfo *chipinfo = &core->bus->chipinfo;
5675
5676         if (chipinfo->id == BCMA_CHIP_ID_BCM4716)
5677                 return true;
5678
5679         pr_err("unknown chip id %04x\n", chipinfo->id);
5680         return false;
5681 }
5682
5683 bool brcms_c_chipmatch(struct bcma_device *core)
5684 {
5685         switch (core->bus->hosttype) {
5686         case BCMA_HOSTTYPE_PCI:
5687                 return brcms_c_chipmatch_pci(core);
5688         case BCMA_HOSTTYPE_SOC:
5689                 return brcms_c_chipmatch_soc(core);
5690         default:
5691                 pr_err("unknown host type: %i\n", core->bus->hosttype);
5692                 return false;
5693         }
5694 }
5695
5696 u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
5697 {
5698         u16 table_ptr;
5699         u8 phy_rate, index;
5700
5701         /* get the phy specific rate encoding for the PLCP SIGNAL field */
5702         if (is_ofdm_rate(rate))
5703                 table_ptr = M_RT_DIRMAP_A;
5704         else
5705                 table_ptr = M_RT_DIRMAP_B;
5706
5707         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
5708          * the index into the rate table.
5709          */
5710         phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
5711         index = phy_rate & 0xf;
5712
5713         /* Find the SHM pointer to the rate table entry by looking in the
5714          * Direct-map Table
5715          */
5716         return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
5717 }
5718
5719 /*
5720  * bcmc_fid_generate:
5721  * Generate frame ID for a BCMC packet.  The frag field is not used
5722  * for MC frames so is used as part of the sequence number.
5723  */
5724 static inline u16
5725 bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
5726                   struct d11txh *txh)
5727 {
5728         u16 frameid;
5729
5730         frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
5731                                                   TXFID_QUEUE_MASK);
5732         frameid |=
5733             (((wlc->
5734                mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
5735             TX_BCMC_FIFO;
5736
5737         return frameid;
5738 }
5739
5740 static uint
5741 brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
5742                       u8 preamble_type)
5743 {
5744         uint dur = 0;
5745
5746         /*
5747          * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5748          * is less than or equal to the rate of the immediately previous
5749          * frame in the FES
5750          */
5751         rspec = brcms_basic_rate(wlc, rspec);
5752         /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
5753         dur =
5754             brcms_c_calc_frame_time(wlc, rspec, preamble_type,
5755                                 (DOT11_ACK_LEN + FCS_LEN));
5756         return dur;
5757 }
5758
5759 static uint
5760 brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec,
5761                       u8 preamble_type)
5762 {
5763         return brcms_c_calc_ack_time(wlc, rspec, preamble_type);
5764 }
5765
5766 static uint
5767 brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec,
5768                      u8 preamble_type)
5769 {
5770         /*
5771          * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5772          * is less than or equal to the rate of the immediately previous
5773          * frame in the FES
5774          */
5775         rspec = brcms_basic_rate(wlc, rspec);
5776         /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
5777         return brcms_c_calc_frame_time(wlc, rspec, preamble_type,
5778                                    (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
5779                                     FCS_LEN));
5780 }
5781
5782 /* brcms_c_compute_frame_dur()
5783  *
5784  * Calculate the 802.11 MAC header DUR field for MPDU
5785  * DUR for a single frame = 1 SIFS + 1 ACK
5786  * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
5787  *
5788  * rate                 MPDU rate in unit of 500kbps
5789  * next_frag_len        next MPDU length in bytes
5790  * preamble_type        use short/GF or long/MM PLCP header
5791  */
5792 static u16
5793 brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate,
5794                       u8 preamble_type, uint next_frag_len)
5795 {
5796         u16 dur, sifs;
5797
5798         sifs = get_sifs(wlc->band);
5799
5800         dur = sifs;
5801         dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type);
5802
5803         if (next_frag_len) {
5804                 /* Double the current DUR to get 2 SIFS + 2 ACKs */
5805                 dur *= 2;
5806                 /* add another SIFS and the frag time */
5807                 dur += sifs;
5808                 dur +=
5809                     (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type,
5810                                                  next_frag_len);
5811         }
5812         return dur;
5813 }
5814
5815 /* The opposite of brcms_c_calc_frame_time */
5816 static uint
5817 brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec,
5818                    u8 preamble_type, uint dur)
5819 {
5820         uint nsyms, mac_len, Ndps, kNdps;
5821         uint rate = rspec2rate(ratespec);
5822
5823         if (is_mcs_rate(ratespec)) {
5824                 uint mcs = ratespec & RSPEC_RATE_MASK;
5825                 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
5826                 dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
5827                 /* payload calculation matches that of regular ofdm */
5828                 if (wlc->band->bandtype == BRCM_BAND_2G)
5829                         dur -= DOT11_OFDM_SIGNAL_EXTENSION;
5830                 /* kNdbps = kbps * 4 */
5831                 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
5832                                    rspec_issgi(ratespec)) * 4;
5833                 nsyms = dur / APHY_SYMBOL_TIME;
5834                 mac_len =
5835                     ((nsyms * kNdps) -
5836                      ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
5837         } else if (is_ofdm_rate(ratespec)) {
5838                 dur -= APHY_PREAMBLE_TIME;
5839                 dur -= APHY_SIGNAL_TIME;
5840                 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
5841                 Ndps = rate * 2;
5842                 nsyms = dur / APHY_SYMBOL_TIME;
5843                 mac_len =
5844                     ((nsyms * Ndps) -
5845                      (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
5846         } else {
5847                 if (preamble_type & BRCMS_SHORT_PREAMBLE)
5848                         dur -= BPHY_PLCP_SHORT_TIME;
5849                 else
5850                         dur -= BPHY_PLCP_TIME;
5851                 mac_len = dur * rate;
5852                 /* divide out factor of 2 in rate (1/2 mbps) */
5853                 mac_len = mac_len / 8 / 2;
5854         }
5855         return mac_len;
5856 }
5857
5858 /*
5859  * Return true if the specified rate is supported by the specified band.
5860  * BRCM_BAND_AUTO indicates the current band.
5861  */
5862 static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band,
5863                     bool verbose)
5864 {
5865         struct brcms_c_rateset *hw_rateset;
5866         uint i;
5867
5868         if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype))
5869                 hw_rateset = &wlc->band->hw_rateset;
5870         else if (wlc->pub->_nbands > 1)
5871                 hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
5872         else
5873                 /* other band specified and we are a single band device */
5874                 return false;
5875
5876         /* check if this is a mimo rate */
5877         if (is_mcs_rate(rspec)) {
5878                 if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE)
5879                         goto error;
5880
5881                 return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
5882         }
5883
5884         for (i = 0; i < hw_rateset->count; i++)
5885                 if (hw_rateset->rates[i] == rspec2rate(rspec))
5886                         return true;
5887  error:
5888         if (verbose)
5889                 brcms_err(wlc->hw->d11core, "wl%d: valid_rate: rate spec 0x%x "
5890                           "not in hw_rateset\n", wlc->pub->unit, rspec);
5891
5892         return false;
5893 }
5894
5895 static u32
5896 mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band,
5897                        u32 int_val)
5898 {
5899         struct bcma_device *core = wlc->hw->d11core;
5900         u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
5901         u8 rate = int_val & NRATE_RATE_MASK;
5902         u32 rspec;
5903         bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
5904         bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
5905         bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
5906                                   == NRATE_OVERRIDE_MCS_ONLY);
5907         int bcmerror = 0;
5908
5909         if (!ismcs)
5910                 return (u32) rate;
5911
5912         /* validate the combination of rate/mcs/stf is allowed */
5913         if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) {
5914                 /* mcs only allowed when nmode */
5915                 if (stf > PHY_TXC1_MODE_SDM) {
5916                         brcms_err(core, "wl%d: %s: Invalid stf\n",
5917                                   wlc->pub->unit, __func__);
5918                         bcmerror = -EINVAL;
5919                         goto done;
5920                 }
5921
5922                 /* mcs 32 is a special case, DUP mode 40 only */
5923                 if (rate == 32) {
5924                         if (!CHSPEC_IS40(wlc->home_chanspec) ||
5925                             ((stf != PHY_TXC1_MODE_SISO)
5926                              && (stf != PHY_TXC1_MODE_CDD))) {
5927                                 brcms_err(core, "wl%d: %s: Invalid mcs 32\n",
5928                                           wlc->pub->unit, __func__);
5929                                 bcmerror = -EINVAL;
5930                                 goto done;
5931                         }
5932                         /* mcs > 7 must use stf SDM */
5933                 } else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
5934                         /* mcs > 7 must use stf SDM */
5935                         if (stf != PHY_TXC1_MODE_SDM) {
5936                                 brcms_dbg_mac80211(core, "wl%d: enabling "
5937                                                    "SDM mode for mcs %d\n",
5938                                                    wlc->pub->unit, rate);
5939                                 stf = PHY_TXC1_MODE_SDM;
5940                         }
5941                 } else {
5942                         /*
5943                          * MCS 0-7 may use SISO, CDD, and for
5944                          * phy_rev >= 3 STBC
5945                          */
5946                         if ((stf > PHY_TXC1_MODE_STBC) ||
5947                             (!BRCMS_STBC_CAP_PHY(wlc)
5948                              && (stf == PHY_TXC1_MODE_STBC))) {
5949                                 brcms_err(core, "wl%d: %s: Invalid STBC\n",
5950                                           wlc->pub->unit, __func__);
5951                                 bcmerror = -EINVAL;
5952                                 goto done;
5953                         }
5954                 }
5955         } else if (is_ofdm_rate(rate)) {
5956                 if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
5957                         brcms_err(core, "wl%d: %s: Invalid OFDM\n",
5958                                   wlc->pub->unit, __func__);
5959                         bcmerror = -EINVAL;
5960                         goto done;
5961                 }
5962         } else if (is_cck_rate(rate)) {
5963                 if ((cur_band->bandtype != BRCM_BAND_2G)
5964                     || (stf != PHY_TXC1_MODE_SISO)) {
5965                         brcms_err(core, "wl%d: %s: Invalid CCK\n",
5966                                   wlc->pub->unit, __func__);
5967                         bcmerror = -EINVAL;
5968                         goto done;
5969                 }
5970         } else {
5971                 brcms_err(core, "wl%d: %s: Unknown rate type\n",
5972                           wlc->pub->unit, __func__);
5973                 bcmerror = -EINVAL;
5974                 goto done;
5975         }
5976         /* make sure multiple antennae are available for non-siso rates */
5977         if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
5978                 brcms_err(core, "wl%d: %s: SISO antenna but !SISO "
5979                           "request\n", wlc->pub->unit, __func__);
5980                 bcmerror = -EINVAL;
5981                 goto done;
5982         }
5983
5984         rspec = rate;
5985         if (ismcs) {
5986                 rspec |= RSPEC_MIMORATE;
5987                 /* For STBC populate the STC field of the ratespec */
5988                 if (stf == PHY_TXC1_MODE_STBC) {
5989                         u8 stc;
5990                         stc = 1;        /* Nss for single stream is always 1 */
5991                         rspec |= (stc << RSPEC_STC_SHIFT);
5992                 }
5993         }
5994
5995         rspec |= (stf << RSPEC_STF_SHIFT);
5996
5997         if (override_mcs_only)
5998                 rspec |= RSPEC_OVERRIDE_MCS_ONLY;
5999
6000         if (issgi)
6001                 rspec |= RSPEC_SHORT_GI;
6002
6003         if ((rate != 0)
6004             && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true))
6005                 return rate;
6006
6007         return rspec;
6008 done:
6009         return rate;
6010 }
6011
6012 /*
6013  * Compute PLCP, but only requires actual rate and length of pkt.
6014  * Rate is given in the driver standard multiple of 500 kbps.
6015  * le is set for 11 Mbps rate if necessary.
6016  * Broken out for PRQ.
6017  */
6018
6019 static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500,
6020                              uint length, u8 *plcp)
6021 {
6022         u16 usec = 0;
6023         u8 le = 0;
6024
6025         switch (rate_500) {
6026         case BRCM_RATE_1M:
6027                 usec = length << 3;
6028                 break;
6029         case BRCM_RATE_2M:
6030                 usec = length << 2;
6031                 break;
6032         case BRCM_RATE_5M5:
6033                 usec = (length << 4) / 11;
6034                 if ((length << 4) - (usec * 11) > 0)
6035                         usec++;
6036                 break;
6037         case BRCM_RATE_11M:
6038                 usec = (length << 3) / 11;
6039                 if ((length << 3) - (usec * 11) > 0) {
6040                         usec++;
6041                         if ((usec * 11) - (length << 3) >= 8)
6042                                 le = D11B_PLCP_SIGNAL_LE;
6043                 }
6044                 break;
6045
6046         default:
6047                 brcms_err(wlc->hw->d11core,
6048                           "brcms_c_cck_plcp_set: unsupported rate %d\n",
6049                           rate_500);
6050                 rate_500 = BRCM_RATE_1M;
6051                 usec = length << 3;
6052                 break;
6053         }
6054         /* PLCP signal byte */
6055         plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */
6056         /* PLCP service byte */
6057         plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
6058         /* PLCP length u16, little endian */
6059         plcp[2] = usec & 0xff;
6060         plcp[3] = (usec >> 8) & 0xff;
6061         /* PLCP CRC16 */
6062         plcp[4] = 0;
6063         plcp[5] = 0;
6064 }
6065
6066 /* Rate: 802.11 rate code, length: PSDU length in octets */
6067 static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp)
6068 {
6069         u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
6070         plcp[0] = mcs;
6071         if (rspec_is40mhz(rspec) || (mcs == 32))
6072                 plcp[0] |= MIMO_PLCP_40MHZ;
6073         BRCMS_SET_MIMO_PLCP_LEN(plcp, length);
6074         plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */
6075         plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
6076         plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
6077         plcp[5] = 0;
6078 }
6079
6080 /* Rate: 802.11 rate code, length: PSDU length in octets */
6081 static void
6082 brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp)
6083 {
6084         u8 rate_signal;
6085         u32 tmp = 0;
6086         int rate = rspec2rate(rspec);
6087
6088         /*
6089          * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
6090          * transmitted first
6091          */
6092         rate_signal = rate_info[rate] & BRCMS_RATE_MASK;
6093         memset(plcp, 0, D11_PHY_HDR_LEN);
6094         D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal);
6095
6096         tmp = (length & 0xfff) << 5;
6097         plcp[2] |= (tmp >> 16) & 0xff;
6098         plcp[1] |= (tmp >> 8) & 0xff;
6099         plcp[0] |= tmp & 0xff;
6100 }
6101
6102 /* Rate: 802.11 rate code, length: PSDU length in octets */
6103 static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec,
6104                                  uint length, u8 *plcp)
6105 {
6106         int rate = rspec2rate(rspec);
6107
6108         brcms_c_cck_plcp_set(wlc, rate, length, plcp);
6109 }
6110
6111 static void
6112 brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec,
6113                      uint length, u8 *plcp)
6114 {
6115         if (is_mcs_rate(rspec))
6116                 brcms_c_compute_mimo_plcp(rspec, length, plcp);
6117         else if (is_ofdm_rate(rspec))