Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-3.10.git] / drivers / net / wireless / brcm80211 / brcmsmac / main.c
1 /*
2  * Copyright (c) 2010 Broadcom Corporation
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/pci_ids.h>
20 #include <linux/if_ether.h>
21 #include <net/cfg80211.h>
22 #include <net/mac80211.h>
23 #include <brcm_hw_ids.h>
24 #include <aiutils.h>
25 #include <chipcommon.h>
26 #include "rate.h"
27 #include "scb.h"
28 #include "phy/phy_hal.h"
29 #include "channel.h"
30 #include "antsel.h"
31 #include "stf.h"
32 #include "ampdu.h"
33 #include "mac80211_if.h"
34 #include "ucode_loader.h"
35 #include "main.h"
36 #include "soc.h"
37
38 /*
39  * Indication for txflowcontrol that all priority bits in
40  * TXQ_STOP_FOR_PRIOFC_MASK are to be considered.
41  */
42 #define ALLPRIO                         -1
43
44 /* watchdog timer, in unit of ms */
45 #define TIMER_INTERVAL_WATCHDOG         1000
46 /* radio monitor timer, in unit of ms */
47 #define TIMER_INTERVAL_RADIOCHK         800
48
49 /* beacon interval, in unit of 1024TU */
50 #define BEACON_INTERVAL_DEFAULT         100
51
52 /* n-mode support capability */
53 /* 2x2 includes both 1x1 & 2x2 devices
54  * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
55  * control it independently
56  */
57 #define WL_11N_2x2                      1
58 #define WL_11N_3x3                      3
59 #define WL_11N_4x4                      4
60
61 #define EDCF_ACI_MASK                   0x60
62 #define EDCF_ACI_SHIFT                  5
63 #define EDCF_ECWMIN_MASK                0x0f
64 #define EDCF_ECWMAX_SHIFT               4
65 #define EDCF_AIFSN_MASK                 0x0f
66 #define EDCF_AIFSN_MAX                  15
67 #define EDCF_ECWMAX_MASK                0xf0
68
69 #define EDCF_AC_BE_TXOP_STA             0x0000
70 #define EDCF_AC_BK_TXOP_STA             0x0000
71 #define EDCF_AC_VO_ACI_STA              0x62
72 #define EDCF_AC_VO_ECW_STA              0x32
73 #define EDCF_AC_VI_ACI_STA              0x42
74 #define EDCF_AC_VI_ECW_STA              0x43
75 #define EDCF_AC_BK_ECW_STA              0xA4
76 #define EDCF_AC_VI_TXOP_STA             0x005e
77 #define EDCF_AC_VO_TXOP_STA             0x002f
78 #define EDCF_AC_BE_ACI_STA              0x03
79 #define EDCF_AC_BE_ECW_STA              0xA4
80 #define EDCF_AC_BK_ACI_STA              0x27
81 #define EDCF_AC_VO_TXOP_AP              0x002f
82
83 #define EDCF_TXOP2USEC(txop)            ((txop) << 5)
84 #define EDCF_ECW2CW(exp)                ((1 << (exp)) - 1)
85
86 #define APHY_SYMBOL_TIME                4
87 #define APHY_PREAMBLE_TIME              16
88 #define APHY_SIGNAL_TIME                4
89 #define APHY_SIFS_TIME                  16
90 #define APHY_SERVICE_NBITS              16
91 #define APHY_TAIL_NBITS                 6
92 #define BPHY_SIFS_TIME                  10
93 #define BPHY_PLCP_SHORT_TIME            96
94
95 #define PREN_PREAMBLE                   24
96 #define PREN_MM_EXT                     12
97 #define PREN_PREAMBLE_EXT               4
98
99 #define DOT11_MAC_HDR_LEN               24
100 #define DOT11_ACK_LEN                   10
101 #define DOT11_BA_LEN                    4
102 #define DOT11_OFDM_SIGNAL_EXTENSION     6
103 #define DOT11_MIN_FRAG_LEN              256
104 #define DOT11_RTS_LEN                   16
105 #define DOT11_CTS_LEN                   10
106 #define DOT11_BA_BITMAP_LEN             128
107 #define DOT11_MIN_BEACON_PERIOD         1
108 #define DOT11_MAX_BEACON_PERIOD         0xFFFF
109 #define DOT11_MAXNUMFRAGS               16
110 #define DOT11_MAX_FRAG_LEN              2346
111
112 #define BPHY_PLCP_TIME                  192
113 #define RIFS_11N_TIME                   2
114
115 /* length of the BCN template area */
116 #define BCN_TMPL_LEN                    512
117
118 /* brcms_bss_info flag bit values */
119 #define BRCMS_BSS_HT                    0x0020  /* BSS is HT (MIMO) capable */
120
121 /* chip rx buffer offset */
122 #define BRCMS_HWRXOFF                   38
123
124 /* rfdisable delay timer 500 ms, runs of ALP clock */
125 #define RFDISABLE_DEFAULT               10000000
126
127 #define BRCMS_TEMPSENSE_PERIOD          10      /* 10 second timeout */
128
129 /* precedences numbers for wlc queues. These are twice as may levels as
130  * 802.1D priorities.
131  * Odd numbers are used for HI priority traffic at same precedence levels
132  * These constants are used ONLY by wlc_prio2prec_map.  Do not use them
133  * elsewhere.
134  */
135 #define _BRCMS_PREC_NONE                0       /* None = - */
136 #define _BRCMS_PREC_BK                  2       /* BK - Background */
137 #define _BRCMS_PREC_BE                  4       /* BE - Best-effort */
138 #define _BRCMS_PREC_EE                  6       /* EE - Excellent-effort */
139 #define _BRCMS_PREC_CL                  8       /* CL - Controlled Load */
140 #define _BRCMS_PREC_VI                  10      /* Vi - Video */
141 #define _BRCMS_PREC_VO                  12      /* Vo - Voice */
142 #define _BRCMS_PREC_NC                  14      /* NC - Network Control */
143
144 /* synthpu_dly times in us */
145 #define SYNTHPU_DLY_APHY_US             3700
146 #define SYNTHPU_DLY_BPHY_US             1050
147 #define SYNTHPU_DLY_NPHY_US             2048
148 #define SYNTHPU_DLY_LPPHY_US            300
149
150 #define ANTCNT                          10      /* vanilla M_MAX_ANTCNT val */
151
152 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
153 #define EDCF_SHORT_S                    0
154 #define EDCF_SFB_S                      4
155 #define EDCF_LONG_S                     8
156 #define EDCF_LFB_S                      12
157 #define EDCF_SHORT_M                    BITFIELD_MASK(4)
158 #define EDCF_SFB_M                      BITFIELD_MASK(4)
159 #define EDCF_LONG_M                     BITFIELD_MASK(4)
160 #define EDCF_LFB_M                      BITFIELD_MASK(4)
161
162 #define RETRY_SHORT_DEF                 7       /* Default Short retry Limit */
163 #define RETRY_SHORT_MAX                 255     /* Maximum Short retry Limit */
164 #define RETRY_LONG_DEF                  4       /* Default Long retry count */
165 #define RETRY_SHORT_FB                  3       /* Short count for fb rate */
166 #define RETRY_LONG_FB                   2       /* Long count for fb rate */
167
168 #define APHY_CWMIN                      15
169 #define PHY_CWMAX                       1023
170
171 #define EDCF_AIFSN_MIN                  1
172
173 #define FRAGNUM_MASK                    0xF
174
175 #define APHY_SLOT_TIME                  9
176 #define BPHY_SLOT_TIME                  20
177
178 #define WL_SPURAVOID_OFF                0
179 #define WL_SPURAVOID_ON1                1
180 #define WL_SPURAVOID_ON2                2
181
182 /* invalid core flags, use the saved coreflags */
183 #define BRCMS_USE_COREFLAGS             0xffffffff
184
185 /* values for PLCPHdr_override */
186 #define BRCMS_PLCP_AUTO                 -1
187 #define BRCMS_PLCP_SHORT                0
188 #define BRCMS_PLCP_LONG                 1
189
190 /* values for g_protection_override and n_protection_override */
191 #define BRCMS_PROTECTION_AUTO           -1
192 #define BRCMS_PROTECTION_OFF            0
193 #define BRCMS_PROTECTION_ON             1
194 #define BRCMS_PROTECTION_MMHDR_ONLY     2
195 #define BRCMS_PROTECTION_CTS_ONLY       3
196
197 /* values for g_protection_control and n_protection_control */
198 #define BRCMS_PROTECTION_CTL_OFF        0
199 #define BRCMS_PROTECTION_CTL_LOCAL      1
200 #define BRCMS_PROTECTION_CTL_OVERLAP    2
201
202 /* values for n_protection */
203 #define BRCMS_N_PROTECTION_OFF          0
204 #define BRCMS_N_PROTECTION_OPTIONAL     1
205 #define BRCMS_N_PROTECTION_20IN40       2
206 #define BRCMS_N_PROTECTION_MIXEDMODE    3
207
208 /* values for band specific 40MHz capabilities */
209 #define BRCMS_N_BW_20ALL                0
210 #define BRCMS_N_BW_40ALL                1
211 #define BRCMS_N_BW_20IN2G_40IN5G        2
212
213 /* bitflags for SGI support (sgi_rx iovar) */
214 #define BRCMS_N_SGI_20                  0x01
215 #define BRCMS_N_SGI_40                  0x02
216
217 /* defines used by the nrate iovar */
218 /* MSC in use,indicates b0-6 holds an mcs */
219 #define NRATE_MCS_INUSE                 0x00000080
220 /* rate/mcs value */
221 #define NRATE_RATE_MASK                 0x0000007f
222 /* stf mode mask: siso, cdd, stbc, sdm */
223 #define NRATE_STF_MASK                  0x0000ff00
224 /* stf mode shift */
225 #define NRATE_STF_SHIFT                 8
226 /* bit indicate to override mcs only */
227 #define NRATE_OVERRIDE_MCS_ONLY         0x40000000
228 #define NRATE_SGI_MASK                  0x00800000      /* sgi mode */
229 #define NRATE_SGI_SHIFT                 23              /* sgi mode */
230 #define NRATE_LDPC_CODING               0x00400000      /* adv coding in use */
231 #define NRATE_LDPC_SHIFT                22              /* ldpc shift */
232
233 #define NRATE_STF_SISO                  0               /* stf mode SISO */
234 #define NRATE_STF_CDD                   1               /* stf mode CDD */
235 #define NRATE_STF_STBC                  2               /* stf mode STBC */
236 #define NRATE_STF_SDM                   3               /* stf mode SDM */
237
238 #define MAX_DMA_SEGS                    4
239
240 /* Max # of entries in Tx FIFO based on 4kb page size */
241 #define NTXD                            256
242 /* Max # of entries in Rx FIFO based on 4kb page size */
243 #define NRXD                            256
244
245 /* try to keep this # rbufs posted to the chip */
246 #define NRXBUFPOST                      32
247
248 /* data msg txq hiwat mark */
249 #define BRCMS_DATAHIWAT                 50
250
251 /* max # frames to process in brcms_c_recv() */
252 #define RXBND                           8
253 /* max # tx status to process in wlc_txstatus() */
254 #define TXSBND                          8
255
256 /* brcmu_format_flags() bit description structure */
257 struct brcms_c_bit_desc {
258         u32 bit;
259         const char *name;
260 };
261
262 /*
263  * The following table lists the buffer memory allocated to xmt fifos in HW.
264  * the size is in units of 256bytes(one block), total size is HW dependent
265  * ucode has default fifo partition, sw can overwrite if necessary
266  *
267  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
268  * the twiki is updated before making changes.
269  */
270
271 /* Starting corerev for the fifo size table */
272 #define XMTFIFOTBL_STARTREV     17
273
274 struct d11init {
275         __le16 addr;
276         __le16 size;
277         __le32 value;
278 };
279
280 struct edcf_acparam {
281         u8 ACI;
282         u8 ECW;
283         u16 TXOP;
284 } __packed;
285
286 const u8 prio2fifo[NUMPRIO] = {
287         TX_AC_BE_FIFO,          /* 0    BE      AC_BE   Best Effort */
288         TX_AC_BK_FIFO,          /* 1    BK      AC_BK   Background */
289         TX_AC_BK_FIFO,          /* 2    --      AC_BK   Background */
290         TX_AC_BE_FIFO,          /* 3    EE      AC_BE   Best Effort */
291         TX_AC_VI_FIFO,          /* 4    CL      AC_VI   Video */
292         TX_AC_VI_FIFO,          /* 5    VI      AC_VI   Video */
293         TX_AC_VO_FIFO,          /* 6    VO      AC_VO   Voice */
294         TX_AC_VO_FIFO           /* 7    NC      AC_VO   Voice */
295 };
296
297 /* debug/trace */
298 uint brcm_msg_level =
299 #if defined(DEBUG)
300         LOG_ERROR_VAL;
301 #else
302         0;
303 #endif                          /* DEBUG */
304
305 /* TX FIFO number to WME/802.1E Access Category */
306 static const u8 wme_fifo2ac[] = {
307         IEEE80211_AC_BK,
308         IEEE80211_AC_BE,
309         IEEE80211_AC_VI,
310         IEEE80211_AC_VO,
311         IEEE80211_AC_BE,
312         IEEE80211_AC_BE
313 };
314
315 /* ieee80211 Access Category to TX FIFO number */
316 static const u8 wme_ac2fifo[] = {
317         TX_AC_VO_FIFO,
318         TX_AC_VI_FIFO,
319         TX_AC_BE_FIFO,
320         TX_AC_BK_FIFO
321 };
322
323 /* 802.1D Priority to precedence queue mapping */
324 const u8 wlc_prio2prec_map[] = {
325         _BRCMS_PREC_BE,         /* 0 BE - Best-effort */
326         _BRCMS_PREC_BK,         /* 1 BK - Background */
327         _BRCMS_PREC_NONE,               /* 2 None = - */
328         _BRCMS_PREC_EE,         /* 3 EE - Excellent-effort */
329         _BRCMS_PREC_CL,         /* 4 CL - Controlled Load */
330         _BRCMS_PREC_VI,         /* 5 Vi - Video */
331         _BRCMS_PREC_VO,         /* 6 Vo - Voice */
332         _BRCMS_PREC_NC,         /* 7 NC - Network Control */
333 };
334
335 static const u16 xmtfifo_sz[][NFIFO] = {
336         /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
337         {20, 192, 192, 21, 17, 5},
338         /* corerev 18: */
339         {0, 0, 0, 0, 0, 0},
340         /* corerev 19: */
341         {0, 0, 0, 0, 0, 0},
342         /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
343         {20, 192, 192, 21, 17, 5},
344         /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
345         {9, 58, 22, 14, 14, 5},
346         /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
347         {20, 192, 192, 21, 17, 5},
348         /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
349         {20, 192, 192, 21, 17, 5},
350         /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
351         {9, 58, 22, 14, 14, 5},
352         /* corerev 25: */
353         {0, 0, 0, 0, 0, 0},
354         /* corerev 26: */
355         {0, 0, 0, 0, 0, 0},
356         /* corerev 27: */
357         {0, 0, 0, 0, 0, 0},
358         /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
359         {9, 58, 22, 14, 14, 5},
360 };
361
362 #ifdef DEBUG
363 static const char * const fifo_names[] = {
364         "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
365 #else
366 static const char fifo_names[6][0];
367 #endif
368
369 #ifdef DEBUG
370 /* pointer to most recently allocated wl/wlc */
371 static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
372 #endif
373
374 /* Find basic rate for a given rate */
375 static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
376 {
377         if (is_mcs_rate(rspec))
378                 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
379                        .leg_ofdm];
380         return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
381 }
382
383 static u16 frametype(u32 rspec, u8 mimoframe)
384 {
385         if (is_mcs_rate(rspec))
386                 return mimoframe;
387         return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
388 }
389
390 /* currently the best mechanism for determining SIFS is the band in use */
391 static u16 get_sifs(struct brcms_band *band)
392 {
393         return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
394                                  BPHY_SIFS_TIME;
395 }
396
397 /*
398  * Detect Card removed.
399  * Even checking an sbconfig register read will not false trigger when the core
400  * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
401  * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
402  * reg with fixed 0/1 pattern (some platforms return all 0).
403  * If clocks are present, call the sb routine which will figure out if the
404  * device is removed.
405  */
406 static bool brcms_deviceremoved(struct brcms_c_info *wlc)
407 {
408         u32 macctrl;
409
410         if (!wlc->hw->clk)
411                 return ai_deviceremoved(wlc->hw->sih);
412         macctrl = bcma_read32(wlc->hw->d11core,
413                               D11REGOFFS(maccontrol));
414         return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
415 }
416
417 /* sum the individual fifo tx pending packet counts */
418 static s16 brcms_txpktpendtot(struct brcms_c_info *wlc)
419 {
420         return wlc->core->txpktpend[0] + wlc->core->txpktpend[1] +
421                wlc->core->txpktpend[2] + wlc->core->txpktpend[3];
422 }
423
424 static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
425 {
426         return wlc->pub->_nbands > 1 && !wlc->bandlocked;
427 }
428
429 static int brcms_chspec_bw(u16 chanspec)
430 {
431         if (CHSPEC_IS40(chanspec))
432                 return BRCMS_40_MHZ;
433         if (CHSPEC_IS20(chanspec))
434                 return BRCMS_20_MHZ;
435
436         return BRCMS_10_MHZ;
437 }
438
439 static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
440 {
441         if (cfg == NULL)
442                 return;
443
444         kfree(cfg->current_bss);
445         kfree(cfg);
446 }
447
448 static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
449 {
450         if (wlc == NULL)
451                 return;
452
453         brcms_c_bsscfg_mfree(wlc->bsscfg);
454         kfree(wlc->pub);
455         kfree(wlc->modulecb);
456         kfree(wlc->default_bss);
457         kfree(wlc->protection);
458         kfree(wlc->stf);
459         kfree(wlc->bandstate[0]);
460         kfree(wlc->corestate->macstat_snapshot);
461         kfree(wlc->corestate);
462         kfree(wlc->hw->bandstate[0]);
463         kfree(wlc->hw);
464
465         /* free the wlc */
466         kfree(wlc);
467         wlc = NULL;
468 }
469
470 static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
471 {
472         struct brcms_bss_cfg *cfg;
473
474         cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
475         if (cfg == NULL)
476                 goto fail;
477
478         cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
479         if (cfg->current_bss == NULL)
480                 goto fail;
481
482         return cfg;
483
484  fail:
485         brcms_c_bsscfg_mfree(cfg);
486         return NULL;
487 }
488
489 static struct brcms_c_info *
490 brcms_c_attach_malloc(uint unit, uint *err, uint devid)
491 {
492         struct brcms_c_info *wlc;
493
494         wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
495         if (wlc == NULL) {
496                 *err = 1002;
497                 goto fail;
498         }
499
500         /* allocate struct brcms_c_pub state structure */
501         wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
502         if (wlc->pub == NULL) {
503                 *err = 1003;
504                 goto fail;
505         }
506         wlc->pub->wlc = wlc;
507
508         /* allocate struct brcms_hardware state structure */
509
510         wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
511         if (wlc->hw == NULL) {
512                 *err = 1005;
513                 goto fail;
514         }
515         wlc->hw->wlc = wlc;
516
517         wlc->hw->bandstate[0] =
518                 kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
519         if (wlc->hw->bandstate[0] == NULL) {
520                 *err = 1006;
521                 goto fail;
522         } else {
523                 int i;
524
525                 for (i = 1; i < MAXBANDS; i++)
526                         wlc->hw->bandstate[i] = (struct brcms_hw_band *)
527                             ((unsigned long)wlc->hw->bandstate[0] +
528                              (sizeof(struct brcms_hw_band) * i));
529         }
530
531         wlc->modulecb =
532                 kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
533         if (wlc->modulecb == NULL) {
534                 *err = 1009;
535                 goto fail;
536         }
537
538         wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
539         if (wlc->default_bss == NULL) {
540                 *err = 1010;
541                 goto fail;
542         }
543
544         wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
545         if (wlc->bsscfg == NULL) {
546                 *err = 1011;
547                 goto fail;
548         }
549
550         wlc->protection = kzalloc(sizeof(struct brcms_protection),
551                                   GFP_ATOMIC);
552         if (wlc->protection == NULL) {
553                 *err = 1016;
554                 goto fail;
555         }
556
557         wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
558         if (wlc->stf == NULL) {
559                 *err = 1017;
560                 goto fail;
561         }
562
563         wlc->bandstate[0] =
564                 kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
565         if (wlc->bandstate[0] == NULL) {
566                 *err = 1025;
567                 goto fail;
568         } else {
569                 int i;
570
571                 for (i = 1; i < MAXBANDS; i++)
572                         wlc->bandstate[i] = (struct brcms_band *)
573                                 ((unsigned long)wlc->bandstate[0]
574                                 + (sizeof(struct brcms_band)*i));
575         }
576
577         wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
578         if (wlc->corestate == NULL) {
579                 *err = 1026;
580                 goto fail;
581         }
582
583         wlc->corestate->macstat_snapshot =
584                 kzalloc(sizeof(struct macstat), GFP_ATOMIC);
585         if (wlc->corestate->macstat_snapshot == NULL) {
586                 *err = 1027;
587                 goto fail;
588         }
589
590         return wlc;
591
592  fail:
593         brcms_c_detach_mfree(wlc);
594         return NULL;
595 }
596
597 /*
598  * Update the slot timing for standard 11b/g (20us slots)
599  * or shortslot 11g (9us slots)
600  * The PSM needs to be suspended for this call.
601  */
602 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
603                                         bool shortslot)
604 {
605         struct bcma_device *core = wlc_hw->d11core;
606
607         if (shortslot) {
608                 /* 11g short slot: 11a timing */
609                 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
610                 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
611         } else {
612                 /* 11g long slot: 11b timing */
613                 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
614                 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
615         }
616 }
617
618 /*
619  * calculate frame duration of a given rate and length, return
620  * time in usec unit
621  */
622 static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
623                                     u8 preamble_type, uint mac_len)
624 {
625         uint nsyms, dur = 0, Ndps, kNdps;
626         uint rate = rspec2rate(ratespec);
627
628         if (rate == 0) {
629                 wiphy_err(wlc->wiphy, "wl%d: WAR: using rate of 1 mbps\n",
630                           wlc->pub->unit);
631                 rate = BRCM_RATE_1M;
632         }
633
634         BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, len%d\n",
635                  wlc->pub->unit, ratespec, preamble_type, mac_len);
636
637         if (is_mcs_rate(ratespec)) {
638                 uint mcs = ratespec & RSPEC_RATE_MASK;
639                 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
640
641                 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
642                 if (preamble_type == BRCMS_MM_PREAMBLE)
643                         dur += PREN_MM_EXT;
644                 /* 1000Ndbps = kbps * 4 */
645                 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
646                                    rspec_issgi(ratespec)) * 4;
647
648                 if (rspec_stc(ratespec) == 0)
649                         nsyms =
650                             CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
651                                   APHY_TAIL_NBITS) * 1000, kNdps);
652                 else
653                         /* STBC needs to have even number of symbols */
654                         nsyms =
655                             2 *
656                             CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
657                                   APHY_TAIL_NBITS) * 1000, 2 * kNdps);
658
659                 dur += APHY_SYMBOL_TIME * nsyms;
660                 if (wlc->band->bandtype == BRCM_BAND_2G)
661                         dur += DOT11_OFDM_SIGNAL_EXTENSION;
662         } else if (is_ofdm_rate(rate)) {
663                 dur = APHY_PREAMBLE_TIME;
664                 dur += APHY_SIGNAL_TIME;
665                 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
666                 Ndps = rate * 2;
667                 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
668                 nsyms =
669                     CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
670                          Ndps);
671                 dur += APHY_SYMBOL_TIME * nsyms;
672                 if (wlc->band->bandtype == BRCM_BAND_2G)
673                         dur += DOT11_OFDM_SIGNAL_EXTENSION;
674         } else {
675                 /*
676                  * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
677                  * will divide out
678                  */
679                 mac_len = mac_len * 8 * 2;
680                 /* calc ceiling of bits/rate = microseconds of air time */
681                 dur = (mac_len + rate - 1) / rate;
682                 if (preamble_type & BRCMS_SHORT_PREAMBLE)
683                         dur += BPHY_PLCP_SHORT_TIME;
684                 else
685                         dur += BPHY_PLCP_TIME;
686         }
687         return dur;
688 }
689
690 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
691                                 const struct d11init *inits)
692 {
693         struct bcma_device *core = wlc_hw->d11core;
694         int i;
695         uint offset;
696         u16 size;
697         u32 value;
698
699         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
700
701         for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
702                 size = le16_to_cpu(inits[i].size);
703                 offset = le16_to_cpu(inits[i].addr);
704                 value = le32_to_cpu(inits[i].value);
705                 if (size == 2)
706                         bcma_write16(core, offset, value);
707                 else if (size == 4)
708                         bcma_write32(core, offset, value);
709                 else
710                         break;
711         }
712 }
713
714 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
715 {
716         u8 idx;
717         u16 addr[] = {
718                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
719                 M_HOST_FLAGS5
720         };
721
722         for (idx = 0; idx < MHFMAX; idx++)
723                 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
724 }
725
726 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
727 {
728         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
729         struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
730
731         /* init microcode host flags */
732         brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
733
734         /* do band-specific ucode IHR, SHM, and SCR inits */
735         if (D11REV_IS(wlc_hw->corerev, 23)) {
736                 if (BRCMS_ISNPHY(wlc_hw->band))
737                         brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
738                 else
739                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
740                                   " %d\n", __func__, wlc_hw->unit,
741                                   wlc_hw->corerev);
742         } else {
743                 if (D11REV_IS(wlc_hw->corerev, 24)) {
744                         if (BRCMS_ISLCNPHY(wlc_hw->band))
745                                 brcms_c_write_inits(wlc_hw,
746                                                     ucode->d11lcn0bsinitvals24);
747                         else
748                                 wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
749                                           " core rev %d\n", __func__,
750                                           wlc_hw->unit, wlc_hw->corerev);
751                 } else {
752                         wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
753                                 __func__, wlc_hw->unit, wlc_hw->corerev);
754                 }
755         }
756 }
757
758 static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
759 {
760         struct bcma_device *core = wlc_hw->d11core;
761         u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
762
763         bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
764 }
765
766 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
767 {
768         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
769
770         wlc_hw->phyclk = clk;
771
772         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
773
774                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
775                                    (SICF_PRST | SICF_FGC));
776                 udelay(1);
777                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
778                 udelay(1);
779
780         } else {                /* take phy out of reset */
781
782                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
783                 udelay(1);
784                 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
785                 udelay(1);
786
787         }
788 }
789
790 /* low-level band switch utility routine */
791 static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
792 {
793         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
794                 bandunit);
795
796         wlc_hw->band = wlc_hw->bandstate[bandunit];
797
798         /*
799          * BMAC_NOTE:
800          *   until we eliminate need for wlc->band refs in low level code
801          */
802         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
803
804         /* set gmode core flag */
805         if (wlc_hw->sbclk && !wlc_hw->noreset) {
806                 u32 gmode = 0;
807
808                 if (bandunit == 0)
809                         gmode = SICF_GMODE;
810
811                 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
812         }
813 }
814
815 /* switch to new band but leave it inactive */
816 static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
817 {
818         struct brcms_hardware *wlc_hw = wlc->hw;
819         u32 macintmask;
820         u32 macctrl;
821
822         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
823         macctrl = bcma_read32(wlc_hw->d11core,
824                               D11REGOFFS(maccontrol));
825         WARN_ON((macctrl & MCTL_EN_MAC) != 0);
826
827         /* disable interrupts */
828         macintmask = brcms_intrsoff(wlc->wl);
829
830         /* radio off */
831         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
832
833         brcms_b_core_phy_clk(wlc_hw, OFF);
834
835         brcms_c_setxband(wlc_hw, bandunit);
836
837         return macintmask;
838 }
839
840 /* process an individual struct tx_status */
841 static bool
842 brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
843 {
844         struct sk_buff *p;
845         uint queue;
846         struct d11txh *txh;
847         struct scb *scb = NULL;
848         bool free_pdu;
849         int tx_rts, tx_frame_count, tx_rts_count;
850         uint totlen, supr_status;
851         bool lastframe;
852         struct ieee80211_hdr *h;
853         u16 mcl;
854         struct ieee80211_tx_info *tx_info;
855         struct ieee80211_tx_rate *txrate;
856         int i;
857
858         /* discard intermediate indications for ucode with one legitimate case:
859          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
860          *   but the subsequent tx of DATA failed. so it will start rts/cts
861          *   from the beginning (resetting the rts transmission count)
862          */
863         if (!(txs->status & TX_STATUS_AMPDU)
864             && (txs->status & TX_STATUS_INTERMEDIATE)) {
865                 BCMMSG(wlc->wiphy, "INTERMEDIATE but not AMPDU\n");
866                 return false;
867         }
868
869         queue = txs->frameid & TXFID_QUEUE_MASK;
870         if (queue >= NFIFO) {
871                 p = NULL;
872                 goto fatal;
873         }
874
875         p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
876         if (p == NULL)
877                 goto fatal;
878
879         txh = (struct d11txh *) (p->data);
880         mcl = le16_to_cpu(txh->MacTxControlLow);
881
882         if (txs->phyerr) {
883                 if (brcm_msg_level & LOG_ERROR_VAL) {
884                         wiphy_err(wlc->wiphy, "phyerr 0x%x, rate 0x%x\n",
885                                   txs->phyerr, txh->MainRates);
886                         brcms_c_print_txdesc(txh);
887                 }
888                 brcms_c_print_txstatus(txs);
889         }
890
891         if (txs->frameid != le16_to_cpu(txh->TxFrameID))
892                 goto fatal;
893         tx_info = IEEE80211_SKB_CB(p);
894         h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
895
896         if (tx_info->rate_driver_data[0])
897                 scb = &wlc->pri_scb;
898
899         if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
900                 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
901                 return false;
902         }
903
904         supr_status = txs->status & TX_STATUS_SUPR_MASK;
905         if (supr_status == TX_STATUS_SUPR_BADCH)
906                 BCMMSG(wlc->wiphy,
907                        "%s: Pkt tx suppressed, possibly channel %d\n",
908                        __func__, CHSPEC_CHANNEL(wlc->default_bss->chanspec));
909
910         tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
911         tx_frame_count =
912             (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
913         tx_rts_count =
914             (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
915
916         lastframe = !ieee80211_has_morefrags(h->frame_control);
917
918         if (!lastframe) {
919                 wiphy_err(wlc->wiphy, "Not last frame!\n");
920         } else {
921                 /*
922                  * Set information to be consumed by Minstrel ht.
923                  *
924                  * The "fallback limit" is the number of tx attempts a given
925                  * MPDU is sent at the "primary" rate. Tx attempts beyond that
926                  * limit are sent at the "secondary" rate.
927                  * A 'short frame' does not exceed RTS treshold.
928                  */
929                 u16 sfbl,       /* Short Frame Rate Fallback Limit */
930                     lfbl,       /* Long Frame Rate Fallback Limit */
931                     fbl;
932
933                 if (queue < IEEE80211_NUM_ACS) {
934                         sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
935                                       EDCF_SFB);
936                         lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
937                                       EDCF_LFB);
938                 } else {
939                         sfbl = wlc->SFBL;
940                         lfbl = wlc->LFBL;
941                 }
942
943                 txrate = tx_info->status.rates;
944                 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
945                         fbl = lfbl;
946                 else
947                         fbl = sfbl;
948
949                 ieee80211_tx_info_clear_status(tx_info);
950
951                 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
952                         /*
953                          * rate selection requested a fallback rate
954                          * and we used it
955                          */
956                         txrate[0].count = fbl;
957                         txrate[1].count = tx_frame_count - fbl;
958                 } else {
959                         /*
960                          * rate selection did not request fallback rate, or
961                          * we didn't need it
962                          */
963                         txrate[0].count = tx_frame_count;
964                         /*
965                          * rc80211_minstrel.c:minstrel_tx_status() expects
966                          * unused rates to be marked with idx = -1
967                          */
968                         txrate[1].idx = -1;
969                         txrate[1].count = 0;
970                 }
971
972                 /* clear the rest of the rates */
973                 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
974                         txrate[i].idx = -1;
975                         txrate[i].count = 0;
976                 }
977
978                 if (txs->status & TX_STATUS_ACK_RCV)
979                         tx_info->flags |= IEEE80211_TX_STAT_ACK;
980         }
981
982         totlen = p->len;
983         free_pdu = true;
984
985         brcms_c_txfifo_complete(wlc, queue, 1);
986
987         if (lastframe) {
988                 /* remove PLCP & Broadcom tx descriptor header */
989                 skb_pull(p, D11_PHY_HDR_LEN);
990                 skb_pull(p, D11_TXH_LEN);
991                 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
992         } else {
993                 wiphy_err(wlc->wiphy, "%s: Not last frame => not calling "
994                           "tx_status\n", __func__);
995         }
996
997         return false;
998
999  fatal:
1000         if (p)
1001                 brcmu_pkt_buf_free_skb(p);
1002
1003         return true;
1004
1005 }
1006
1007 /* process tx completion events in BMAC
1008  * Return true if more tx status need to be processed. false otherwise.
1009  */
1010 static bool
1011 brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
1012 {
1013         bool morepending = false;
1014         struct brcms_c_info *wlc = wlc_hw->wlc;
1015         struct bcma_device *core;
1016         struct tx_status txstatus, *txs;
1017         u32 s1, s2;
1018         uint n = 0;
1019         /*
1020          * Param 'max_tx_num' indicates max. # tx status to process before
1021          * break out.
1022          */
1023         uint max_tx_num = bound ? TXSBND : -1;
1024
1025         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
1026
1027         txs = &txstatus;
1028         core = wlc_hw->d11core;
1029         *fatal = false;
1030         s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1031         while (!(*fatal)
1032                && (s1 & TXS_V)) {
1033
1034                 if (s1 == 0xffffffff) {
1035                         wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
1036                                 wlc_hw->unit, __func__);
1037                         return morepending;
1038                 }
1039                 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
1040
1041                 txs->status = s1 & TXS_STATUS_MASK;
1042                 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
1043                 txs->sequence = s2 & TXS_SEQ_MASK;
1044                 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
1045                 txs->lasttxtime = 0;
1046
1047                 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1048
1049                 /* !give others some time to run! */
1050                 if (++n >= max_tx_num)
1051                         break;
1052                 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1053         }
1054
1055         if (*fatal)
1056                 return 0;
1057
1058         if (n >= max_tx_num)
1059                 morepending = true;
1060
1061         if (!pktq_empty(&wlc->pkt_queue->q))
1062                 brcms_c_send_q(wlc);
1063
1064         return morepending;
1065 }
1066
1067 static void brcms_c_tbtt(struct brcms_c_info *wlc)
1068 {
1069         if (!wlc->bsscfg->BSS)
1070                 /*
1071                  * DirFrmQ is now valid...defer setting until end
1072                  * of ATIM window
1073                  */
1074                 wlc->qvalid |= MCMD_DIRFRMQVAL;
1075 }
1076
1077 /* set initial host flags value */
1078 static void
1079 brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1080 {
1081         struct brcms_hardware *wlc_hw = wlc->hw;
1082
1083         memset(mhfs, 0, MHFMAX * sizeof(u16));
1084
1085         mhfs[MHF2] |= mhf2_init;
1086
1087         /* prohibit use of slowclock on multifunction boards */
1088         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1089                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1090
1091         if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1092                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1093                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1094         }
1095 }
1096
1097 static uint
1098 dmareg(uint direction, uint fifonum)
1099 {
1100         if (direction == DMA_TX)
1101                 return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
1102         return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
1103 }
1104
1105 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
1106 {
1107         uint i;
1108         char name[8];
1109         /*
1110          * ucode host flag 2 needed for pio mode, independent of band and fifo
1111          */
1112         u16 pio_mhf2 = 0;
1113         struct brcms_hardware *wlc_hw = wlc->hw;
1114         uint unit = wlc_hw->unit;
1115         struct wiphy *wiphy = wlc->wiphy;
1116
1117         /* name and offsets for dma_attach */
1118         snprintf(name, sizeof(name), "wl%d", unit);
1119
1120         if (wlc_hw->di[0] == NULL) {    /* Init FIFOs */
1121                 int dma_attach_err = 0;
1122
1123                 /*
1124                  * FIFO 0
1125                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1126                  * RX: RX_FIFO (RX data packets)
1127                  */
1128                 wlc_hw->di[0] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
1129                                            (wme ? dmareg(DMA_TX, 0) : 0),
1130                                            dmareg(DMA_RX, 0),
1131                                            (wme ? NTXD : 0), NRXD,
1132                                            RXBUFSZ, -1, NRXBUFPOST,
1133                                            BRCMS_HWRXOFF, &brcm_msg_level);
1134                 dma_attach_err |= (NULL == wlc_hw->di[0]);
1135
1136                 /*
1137                  * FIFO 1
1138                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1139                  *   (legacy) TX_DATA_FIFO (TX data packets)
1140                  * RX: UNUSED
1141                  */
1142                 wlc_hw->di[1] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
1143                                            dmareg(DMA_TX, 1), 0,
1144                                            NTXD, 0, 0, -1, 0, 0,
1145                                            &brcm_msg_level);
1146                 dma_attach_err |= (NULL == wlc_hw->di[1]);
1147
1148                 /*
1149                  * FIFO 2
1150                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1151                  * RX: UNUSED
1152                  */
1153                 wlc_hw->di[2] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
1154                                            dmareg(DMA_TX, 2), 0,
1155                                            NTXD, 0, 0, -1, 0, 0,
1156                                            &brcm_msg_level);
1157                 dma_attach_err |= (NULL == wlc_hw->di[2]);
1158                 /*
1159                  * FIFO 3
1160                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1161                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1162                  */
1163                 wlc_hw->di[3] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
1164                                            dmareg(DMA_TX, 3),
1165                                            0, NTXD, 0, 0, -1,
1166                                            0, 0, &brcm_msg_level);
1167                 dma_attach_err |= (NULL == wlc_hw->di[3]);
1168 /* Cleaner to leave this as if with AP defined */
1169
1170                 if (dma_attach_err) {
1171                         wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
1172                                   "\n", unit);
1173                         return false;
1174                 }
1175
1176                 /* get pointer to dma engine tx flow control variable */
1177                 for (i = 0; i < NFIFO; i++)
1178                         if (wlc_hw->di[i])
1179                                 wlc_hw->txavail[i] =
1180                                     (uint *) dma_getvar(wlc_hw->di[i],
1181                                                         "&txavail");
1182         }
1183
1184         /* initial ucode host flags */
1185         brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1186
1187         return true;
1188 }
1189
1190 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1191 {
1192         uint j;
1193
1194         for (j = 0; j < NFIFO; j++) {
1195                 if (wlc_hw->di[j]) {
1196                         dma_detach(wlc_hw->di[j]);
1197                         wlc_hw->di[j] = NULL;
1198                 }
1199         }
1200 }
1201
1202 /*
1203  * Initialize brcms_c_info default values ...
1204  * may get overrides later in this function
1205  *  BMAC_NOTES, move low out and resolve the dangling ones
1206  */
1207 static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1208 {
1209         struct brcms_c_info *wlc = wlc_hw->wlc;
1210
1211         /* set default sw macintmask value */
1212         wlc->defmacintmask = DEF_MACINTMASK;
1213
1214         /* various 802.11g modes */
1215         wlc_hw->shortslot = false;
1216
1217         wlc_hw->SFBL = RETRY_SHORT_FB;
1218         wlc_hw->LFBL = RETRY_LONG_FB;
1219
1220         /* default mac retry limits */
1221         wlc_hw->SRL = RETRY_SHORT_DEF;
1222         wlc_hw->LRL = RETRY_LONG_DEF;
1223         wlc_hw->chanspec = ch20mhz_chspec(1);
1224 }
1225
1226 static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1227 {
1228         /* delay before first read of ucode state */
1229         udelay(40);
1230
1231         /* wait until ucode is no longer asleep */
1232         SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1233                   DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1234 }
1235
1236 /* control chip clock to save power, enable dynamic clock or force fast clock */
1237 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
1238 {
1239         if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1240                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1241                  * on backplane, but mac core will still run on ALP(not HT) when
1242                  * it enters powersave mode, which means the FCA bit may not be
1243                  * set. Should wakeup mac if driver wants it to run on HT.
1244                  */
1245
1246                 if (wlc_hw->clk) {
1247                         if (mode == BCMA_CLKMODE_FAST) {
1248                                 bcma_set32(wlc_hw->d11core,
1249                                            D11REGOFFS(clk_ctl_st),
1250                                            CCS_FORCEHT);
1251
1252                                 udelay(64);
1253
1254                                 SPINWAIT(
1255                                     ((bcma_read32(wlc_hw->d11core,
1256                                       D11REGOFFS(clk_ctl_st)) &
1257                                       CCS_HTAVAIL) == 0),
1258                                       PMU_MAX_TRANSITION_DLY);
1259                                 WARN_ON(!(bcma_read32(wlc_hw->d11core,
1260                                         D11REGOFFS(clk_ctl_st)) &
1261                                         CCS_HTAVAIL));
1262                         } else {
1263                                 if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1264                                     (bcma_read32(wlc_hw->d11core,
1265                                         D11REGOFFS(clk_ctl_st)) &
1266                                         (CCS_FORCEHT | CCS_HTAREQ)))
1267                                         SPINWAIT(
1268                                             ((bcma_read32(wlc_hw->d11core,
1269                                               offsetof(struct d11regs,
1270                                                        clk_ctl_st)) &
1271                                               CCS_HTAVAIL) == 0),
1272                                               PMU_MAX_TRANSITION_DLY);
1273                                 bcma_mask32(wlc_hw->d11core,
1274                                         D11REGOFFS(clk_ctl_st),
1275                                         ~CCS_FORCEHT);
1276                         }
1277                 }
1278                 wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
1279         } else {
1280
1281                 /* old chips w/o PMU, force HT through cc,
1282                  * then use FCA to verify mac is running fast clock
1283                  */
1284
1285                 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1286
1287                 /* check fast clock is available (if core is not in reset) */
1288                 if (wlc_hw->forcefastclk && wlc_hw->clk)
1289                         WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
1290                                   SISF_FCLKA));
1291
1292                 /*
1293                  * keep the ucode wake bit on if forcefastclk is on since we
1294                  * do not want ucode to put us back to slow clock when it dozes
1295                  * for PM mode. Code below matches the wake override bit with
1296                  * current forcefastclk state. Only setting bit in wake_override
1297                  * instead of waking ucode immediately since old code had this
1298                  * behavior. Older code set wlc->forcefastclk but only had the
1299                  * wake happen if the wakup_ucode work (protected by an up
1300                  * check) was executed just below.
1301                  */
1302                 if (wlc_hw->forcefastclk)
1303                         mboolset(wlc_hw->wake_override,
1304                                  BRCMS_WAKE_OVERRIDE_FORCEFAST);
1305                 else
1306                         mboolclr(wlc_hw->wake_override,
1307                                  BRCMS_WAKE_OVERRIDE_FORCEFAST);
1308         }
1309 }
1310
1311 /* set or clear ucode host flag bits
1312  * it has an optimization for no-change write
1313  * it only writes through shared memory when the core has clock;
1314  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1315  *
1316  *
1317  * bands values are: BRCM_BAND_AUTO <--- Current band only
1318  *                   BRCM_BAND_5G   <--- 5G band only
1319  *                   BRCM_BAND_2G   <--- 2G band only
1320  *                   BRCM_BAND_ALL  <--- All bands
1321  */
1322 void
1323 brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1324              int bands)
1325 {
1326         u16 save;
1327         u16 addr[MHFMAX] = {
1328                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1329                 M_HOST_FLAGS5
1330         };
1331         struct brcms_hw_band *band;
1332
1333         if ((val & ~mask) || idx >= MHFMAX)
1334                 return; /* error condition */
1335
1336         switch (bands) {
1337                 /* Current band only or all bands,
1338                  * then set the band to current band
1339                  */
1340         case BRCM_BAND_AUTO:
1341         case BRCM_BAND_ALL:
1342                 band = wlc_hw->band;
1343                 break;
1344         case BRCM_BAND_5G:
1345                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1346                 break;
1347         case BRCM_BAND_2G:
1348                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1349                 break;
1350         default:
1351                 band = NULL;    /* error condition */
1352         }
1353
1354         if (band) {
1355                 save = band->mhfs[idx];
1356                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1357
1358                 /* optimization: only write through if changed, and
1359                  * changed band is the current band
1360                  */
1361                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1362                     && (band == wlc_hw->band))
1363                         brcms_b_write_shm(wlc_hw, addr[idx],
1364                                            (u16) band->mhfs[idx]);
1365         }
1366
1367         if (bands == BRCM_BAND_ALL) {
1368                 wlc_hw->bandstate[0]->mhfs[idx] =
1369                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1370                 wlc_hw->bandstate[1]->mhfs[idx] =
1371                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1372         }
1373 }
1374
1375 /* set the maccontrol register to desired reset state and
1376  * initialize the sw cache of the register
1377  */
1378 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1379 {
1380         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1381         wlc_hw->maccontrol = 0;
1382         wlc_hw->suspended_fifos = 0;
1383         wlc_hw->wake_override = 0;
1384         wlc_hw->mute_override = 0;
1385         brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1386 }
1387
1388 /*
1389  * write the software state of maccontrol and
1390  * overrides to the maccontrol register
1391  */
1392 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1393 {
1394         u32 maccontrol = wlc_hw->maccontrol;
1395
1396         /* OR in the wake bit if overridden */
1397         if (wlc_hw->wake_override)
1398                 maccontrol |= MCTL_WAKE;
1399
1400         /* set AP and INFRA bits for mute if needed */
1401         if (wlc_hw->mute_override) {
1402                 maccontrol &= ~(MCTL_AP);
1403                 maccontrol |= MCTL_INFRA;
1404         }
1405
1406         bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1407                      maccontrol);
1408 }
1409
1410 /* set or clear maccontrol bits */
1411 void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1412 {
1413         u32 maccontrol;
1414         u32 new_maccontrol;
1415
1416         if (val & ~mask)
1417                 return; /* error condition */
1418         maccontrol = wlc_hw->maccontrol;
1419         new_maccontrol = (maccontrol & ~mask) | val;
1420
1421         /* if the new maccontrol value is the same as the old, nothing to do */
1422         if (new_maccontrol == maccontrol)
1423                 return;
1424
1425         /* something changed, cache the new value */
1426         wlc_hw->maccontrol = new_maccontrol;
1427
1428         /* write the new values with overrides applied */
1429         brcms_c_mctrl_write(wlc_hw);
1430 }
1431
1432 void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1433                                  u32 override_bit)
1434 {
1435         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1436                 mboolset(wlc_hw->wake_override, override_bit);
1437                 return;
1438         }
1439
1440         mboolset(wlc_hw->wake_override, override_bit);
1441
1442         brcms_c_mctrl_write(wlc_hw);
1443         brcms_b_wait_for_wake(wlc_hw);
1444 }
1445
1446 void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1447                                    u32 override_bit)
1448 {
1449         mboolclr(wlc_hw->wake_override, override_bit);
1450
1451         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1452                 return;
1453
1454         brcms_c_mctrl_write(wlc_hw);
1455 }
1456
1457 /* When driver needs ucode to stop beaconing, it has to make sure that
1458  * MCTL_AP is clear and MCTL_INFRA is set
1459  * Mode           MCTL_AP        MCTL_INFRA
1460  * AP                1              1
1461  * STA               0              1 <--- This will ensure no beacons
1462  * IBSS              0              0
1463  */
1464 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1465 {
1466         wlc_hw->mute_override = 1;
1467
1468         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1469          * override, then there is no change to write
1470          */
1471         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1472                 return;
1473
1474         brcms_c_mctrl_write(wlc_hw);
1475 }
1476
1477 /* Clear the override on AP and INFRA bits */
1478 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1479 {
1480         if (wlc_hw->mute_override == 0)
1481                 return;
1482
1483         wlc_hw->mute_override = 0;
1484
1485         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1486          * override, then there is no change to write
1487          */
1488         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1489                 return;
1490
1491         brcms_c_mctrl_write(wlc_hw);
1492 }
1493
1494 /*
1495  * Write a MAC address to the given match reg offset in the RXE match engine.
1496  */
1497 static void
1498 brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1499                        const u8 *addr)
1500 {
1501         struct bcma_device *core = wlc_hw->d11core;
1502         u16 mac_l;
1503         u16 mac_m;
1504         u16 mac_h;
1505
1506         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: brcms_b_set_addrmatch\n",
1507                  wlc_hw->unit);
1508
1509         mac_l = addr[0] | (addr[1] << 8);
1510         mac_m = addr[2] | (addr[3] << 8);
1511         mac_h = addr[4] | (addr[5] << 8);
1512
1513         /* enter the MAC addr into the RXE match registers */
1514         bcma_write16(core, D11REGOFFS(rcm_ctl),
1515                      RCM_INC_DATA | match_reg_offset);
1516         bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
1517         bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
1518         bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
1519 }
1520
1521 void
1522 brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1523                             void *buf)
1524 {
1525         struct bcma_device *core = wlc_hw->d11core;
1526         u32 word;
1527         __le32 word_le;
1528         __be32 word_be;
1529         bool be_bit;
1530         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1531
1532         bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
1533
1534         /* if MCTL_BIGEND bit set in mac control register,
1535          * the chip swaps data in fifo, as well as data in
1536          * template ram
1537          */
1538         be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
1539
1540         while (len > 0) {
1541                 memcpy(&word, buf, sizeof(u32));
1542
1543                 if (be_bit) {
1544                         word_be = cpu_to_be32(word);
1545                         word = *(u32 *)&word_be;
1546                 } else {
1547                         word_le = cpu_to_le32(word);
1548                         word = *(u32 *)&word_le;
1549                 }
1550
1551                 bcma_write32(core, D11REGOFFS(tplatewrdata), word);
1552
1553                 buf = (u8 *) buf + sizeof(u32);
1554                 len -= sizeof(u32);
1555         }
1556 }
1557
1558 static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1559 {
1560         wlc_hw->band->CWmin = newmin;
1561
1562         bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1563                      OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1564         (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1565         bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1566 }
1567
1568 static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1569 {
1570         wlc_hw->band->CWmax = newmax;
1571
1572         bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1573                      OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1574         (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1575         bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1576 }
1577
1578 void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1579 {
1580         bool fastclk;
1581
1582         /* request FAST clock if not on */
1583         fastclk = wlc_hw->forcefastclk;
1584         if (!fastclk)
1585                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1586
1587         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1588
1589         brcms_b_phy_reset(wlc_hw);
1590         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1591
1592         /* restore the clk */
1593         if (!fastclk)
1594                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1595 }
1596
1597 static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1598 {
1599         u16 v;
1600         struct brcms_c_info *wlc = wlc_hw->wlc;
1601         /* update SYNTHPU_DLY */
1602
1603         if (BRCMS_ISLCNPHY(wlc->band))
1604                 v = SYNTHPU_DLY_LPPHY_US;
1605         else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
1606                 v = SYNTHPU_DLY_NPHY_US;
1607         else
1608                 v = SYNTHPU_DLY_BPHY_US;
1609
1610         brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1611 }
1612
1613 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1614 {
1615         u16 phyctl;
1616         u16 phytxant = wlc_hw->bmac_phytxant;
1617         u16 mask = PHY_TXC_ANT_MASK;
1618
1619         /* set the Probe Response frame phy control word */
1620         phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1621         phyctl = (phyctl & ~mask) | phytxant;
1622         brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1623
1624         /* set the Response (ACK/CTS) frame phy control word */
1625         phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1626         phyctl = (phyctl & ~mask) | phytxant;
1627         brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1628 }
1629
1630 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1631                                          u8 rate)
1632 {
1633         uint i;
1634         u8 plcp_rate = 0;
1635         struct plcp_signal_rate_lookup {
1636                 u8 rate;
1637                 u8 signal_rate;
1638         };
1639         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1640         const struct plcp_signal_rate_lookup rate_lookup[] = {
1641                 {BRCM_RATE_6M, 0xB},
1642                 {BRCM_RATE_9M, 0xF},
1643                 {BRCM_RATE_12M, 0xA},
1644                 {BRCM_RATE_18M, 0xE},
1645                 {BRCM_RATE_24M, 0x9},
1646                 {BRCM_RATE_36M, 0xD},
1647                 {BRCM_RATE_48M, 0x8},
1648                 {BRCM_RATE_54M, 0xC}
1649         };
1650
1651         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
1652                 if (rate == rate_lookup[i].rate) {
1653                         plcp_rate = rate_lookup[i].signal_rate;
1654                         break;
1655                 }
1656         }
1657
1658         /* Find the SHM pointer to the rate table entry by looking in the
1659          * Direct-map Table
1660          */
1661         return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1662 }
1663
1664 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1665 {
1666         u8 rate;
1667         u8 rates[8] = {
1668                 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
1669                 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
1670         };
1671         u16 entry_ptr;
1672         u16 pctl1;
1673         uint i;
1674
1675         if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1676                 return;
1677
1678         /* walk the phy rate table and update the entries */
1679         for (i = 0; i < ARRAY_SIZE(rates); i++) {
1680                 rate = rates[i];
1681
1682                 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1683
1684                 /* read the SHM Rate Table entry OFDM PCTL1 values */
1685                 pctl1 =
1686                     brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1687
1688                 /* modify the value */
1689                 pctl1 &= ~PHY_TXC1_MODE_MASK;
1690                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1691
1692                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
1693                 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1694                                    pctl1);
1695         }
1696 }
1697
1698 /* band-specific init */
1699 static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
1700 {
1701         struct brcms_hardware *wlc_hw = wlc->hw;
1702
1703         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1704                 wlc_hw->band->bandunit);
1705
1706         brcms_c_ucode_bsinit(wlc_hw);
1707
1708         wlc_phy_init(wlc_hw->band->pi, chanspec);
1709
1710         brcms_c_ucode_txant_set(wlc_hw);
1711
1712         /*
1713          * cwmin is band-specific, update hardware
1714          * with value for current band
1715          */
1716         brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1717         brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1718
1719         brcms_b_update_slot_timing(wlc_hw,
1720                                    wlc_hw->band->bandtype == BRCM_BAND_5G ?
1721                                    true : wlc_hw->shortslot);
1722
1723         /* write phytype and phyvers */
1724         brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1725         brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1726
1727         /*
1728          * initialize the txphyctl1 rate table since
1729          * shmem is shared between bands
1730          */
1731         brcms_upd_ofdm_pctl1_table(wlc_hw);
1732
1733         brcms_b_upd_synthpu(wlc_hw);
1734 }
1735
1736 /* Perform a soft reset of the PHY PLL */
1737 void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1738 {
1739         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1740
1741         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
1742                   ~0, 0);
1743         udelay(1);
1744         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1745                   0x4, 0);
1746         udelay(1);
1747         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1748                   0x4, 4);
1749         udelay(1);
1750         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1751                   0x4, 0);
1752         udelay(1);
1753 }
1754
1755 /* light way to turn on phy clock without reset for NPHY only
1756  *  refer to brcms_b_core_phy_clk for full version
1757  */
1758 void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1759 {
1760         /* support(necessary for NPHY and HYPHY) only */
1761         if (!BRCMS_ISNPHY(wlc_hw->band))
1762                 return;
1763
1764         if (ON == clk)
1765                 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
1766         else
1767                 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
1768
1769 }
1770
1771 void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1772 {
1773         if (ON == clk)
1774                 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
1775         else
1776                 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
1777 }
1778
1779 void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1780 {
1781         struct brcms_phy_pub *pih = wlc_hw->band->pi;
1782         u32 phy_bw_clkbits;
1783         bool phy_in_reset = false;
1784
1785         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1786
1787         if (pih == NULL)
1788                 return;
1789
1790         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1791
1792         /* Specific reset sequence required for NPHY rev 3 and 4 */
1793         if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1794             NREV_LE(wlc_hw->band->phyrev, 4)) {
1795                 /* Set the PHY bandwidth */
1796                 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
1797
1798                 udelay(1);
1799
1800                 /* Perform a soft reset of the PHY PLL */
1801                 brcms_b_core_phypll_reset(wlc_hw);
1802
1803                 /* reset the PHY */
1804                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
1805                                    (SICF_PRST | SICF_PCLKE));
1806                 phy_in_reset = true;
1807         } else {
1808                 brcms_b_core_ioctl(wlc_hw,
1809                                    (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1810                                    (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1811         }
1812
1813         udelay(2);
1814         brcms_b_core_phy_clk(wlc_hw, ON);
1815
1816         if (pih)
1817                 wlc_phy_anacore(pih, ON);
1818 }
1819
1820 /* switch to and initialize new band */
1821 static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1822                             u16 chanspec) {
1823         struct brcms_c_info *wlc = wlc_hw->wlc;
1824         u32 macintmask;
1825
1826         /* Enable the d11 core before accessing it */
1827         if (!bcma_core_is_enabled(wlc_hw->d11core)) {
1828                 bcma_core_enable(wlc_hw->d11core, 0);
1829                 brcms_c_mctrl_reset(wlc_hw);
1830         }
1831
1832         macintmask = brcms_c_setband_inact(wlc, bandunit);
1833
1834         if (!wlc_hw->up)
1835                 return;
1836
1837         brcms_b_core_phy_clk(wlc_hw, ON);
1838
1839         /* band-specific initializations */
1840         brcms_b_bsinit(wlc, chanspec);
1841
1842         /*
1843          * If there are any pending software interrupt bits,
1844          * then replace these with a harmless nonzero value
1845          * so brcms_c_dpc() will re-enable interrupts when done.
1846          */
1847         if (wlc->macintstatus)
1848                 wlc->macintstatus = MI_DMAINT;
1849
1850         /* restore macintmask */
1851         brcms_intrsrestore(wlc->wl, macintmask);
1852
1853         /* ucode should still be suspended.. */
1854         WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1855                  MCTL_EN_MAC) != 0);
1856 }
1857
1858 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1859 {
1860
1861         /* reject unsupported corerev */
1862         if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1863                 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1864                           wlc_hw->corerev);
1865                 return false;
1866         }
1867
1868         return true;
1869 }
1870
1871 /* Validate some board info parameters */
1872 static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1873 {
1874         uint boardrev = wlc_hw->boardrev;
1875
1876         /* 4 bits each for board type, major, minor, and tiny version */
1877         uint brt = (boardrev & 0xf000) >> 12;
1878         uint b0 = (boardrev & 0xf00) >> 8;
1879         uint b1 = (boardrev & 0xf0) >> 4;
1880         uint b2 = boardrev & 0xf;
1881
1882         /* voards from other vendors are always considered valid */
1883         if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1884                 return true;
1885
1886         /* do some boardrev sanity checks when boardvendor is Broadcom */
1887         if (boardrev == 0)
1888                 return false;
1889
1890         if (boardrev <= 0xff)
1891                 return true;
1892
1893         if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1894                 || (b2 > 9))
1895                 return false;
1896
1897         return true;
1898 }
1899
1900 static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1901 {
1902         struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1903
1904         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1905         if (!is_zero_ether_addr(sprom->il0mac)) {
1906                 memcpy(etheraddr, sprom->il0mac, 6);
1907                 return;
1908         }
1909
1910         if (wlc_hw->_nbands > 1)
1911                 memcpy(etheraddr, sprom->et1mac, 6);
1912         else
1913                 memcpy(etheraddr, sprom->il0mac, 6);
1914 }
1915
1916 /* power both the pll and external oscillator on/off */
1917 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1918 {
1919         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
1920
1921         /*
1922          * dont power down if plldown is false or
1923          * we must poll hw radio disable
1924          */
1925         if (!want && wlc_hw->pllreq)
1926                 return;
1927
1928         wlc_hw->sbclk = want;
1929         if (!wlc_hw->sbclk) {
1930                 wlc_hw->clk = false;
1931                 if (wlc_hw->band && wlc_hw->band->pi)
1932                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1933         }
1934 }
1935
1936 /*
1937  * Return true if radio is disabled, otherwise false.
1938  * hw radio disable signal is an external pin, users activate it asynchronously
1939  * this function could be called when driver is down and w/o clock
1940  * it operates on different registers depending on corerev and boardflag.
1941  */
1942 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1943 {
1944         bool v, clk, xtal;
1945         u32 flags = 0;
1946
1947         xtal = wlc_hw->sbclk;
1948         if (!xtal)
1949                 brcms_b_xtal(wlc_hw, ON);
1950
1951         /* may need to take core out of reset first */
1952         clk = wlc_hw->clk;
1953         if (!clk) {
1954                 /*
1955                  * mac no longer enables phyclk automatically when driver
1956                  * accesses phyreg throughput mac. This can be skipped since
1957                  * only mac reg is accessed below
1958                  */
1959                 if (D11REV_GE(wlc_hw->corerev, 18))
1960                         flags |= SICF_PCLKE;
1961
1962                 /*
1963                  * TODO: test suspend/resume
1964                  *
1965                  * AI chip doesn't restore bar0win2 on
1966                  * hibernation/resume, need sw fixup
1967                  */
1968
1969                 bcma_core_enable(wlc_hw->d11core, flags);
1970                 brcms_c_mctrl_reset(wlc_hw);
1971         }
1972
1973         v = ((bcma_read32(wlc_hw->d11core,
1974                           D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
1975
1976         /* put core back into reset */
1977         if (!clk)
1978                 bcma_core_disable(wlc_hw->d11core, 0);
1979
1980         if (!xtal)
1981                 brcms_b_xtal(wlc_hw, OFF);
1982
1983         return v;
1984 }
1985
1986 static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
1987 {
1988         struct dma_pub *di = wlc_hw->di[fifo];
1989         return dma_rxreset(di);
1990 }
1991
1992 /* d11 core reset
1993  *   ensure fask clock during reset
1994  *   reset dma
1995  *   reset d11(out of reset)
1996  *   reset phy(out of reset)
1997  *   clear software macintstatus for fresh new start
1998  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
1999  */
2000 void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
2001 {
2002         uint i;
2003         bool fastclk;
2004
2005         if (flags == BRCMS_USE_COREFLAGS)
2006                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2007
2008         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2009
2010         /* request FAST clock if not on  */
2011         fastclk = wlc_hw->forcefastclk;
2012         if (!fastclk)
2013                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2014
2015         /* reset the dma engines except first time thru */
2016         if (bcma_core_is_enabled(wlc_hw->d11core)) {
2017                 for (i = 0; i < NFIFO; i++)
2018                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2019                                 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
2020                                           "dma_txreset[%d]: cannot stop dma\n",
2021                                            wlc_hw->unit, __func__, i);
2022
2023                 if ((wlc_hw->di[RX_FIFO])
2024                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2025                         wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
2026                                   "[%d]: cannot stop dma\n",
2027                                   wlc_hw->unit, __func__, RX_FIFO);
2028         }
2029         /* if noreset, just stop the psm and return */
2030         if (wlc_hw->noreset) {
2031                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2032                 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2033                 return;
2034         }
2035
2036         /*
2037          * mac no longer enables phyclk automatically when driver accesses
2038          * phyreg throughput mac, AND phy_reset is skipped at early stage when
2039          * band->pi is invalid. need to enable PHY CLK
2040          */
2041         if (D11REV_GE(wlc_hw->corerev, 18))
2042                 flags |= SICF_PCLKE;
2043
2044         /*
2045          * reset the core
2046          * In chips with PMU, the fastclk request goes through d11 core
2047          * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2048          *
2049          * This adds some delay and we can optimize it by also requesting
2050          * fastclk through chipcommon during this period if necessary. But
2051          * that has to work coordinate with other driver like mips/arm since
2052          * they may touch chipcommon as well.
2053          */
2054         wlc_hw->clk = false;
2055         bcma_core_enable(wlc_hw->d11core, flags);
2056         wlc_hw->clk = true;
2057         if (wlc_hw->band && wlc_hw->band->pi)
2058                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2059
2060         brcms_c_mctrl_reset(wlc_hw);
2061
2062         if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2063                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2064
2065         brcms_b_phy_reset(wlc_hw);
2066
2067         /* turn on PHY_PLL */
2068         brcms_b_core_phypll_ctl(wlc_hw, true);
2069
2070         /* clear sw intstatus */
2071         wlc_hw->wlc->macintstatus = 0;
2072
2073         /* restore the clk setting */
2074         if (!fastclk)
2075                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
2076 }
2077
2078 /* txfifo sizes needs to be modified(increased) since the newer cores
2079  * have more memory.
2080  */
2081 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2082 {
2083         struct bcma_device *core = wlc_hw->d11core;
2084         u16 fifo_nu;
2085         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2086         u16 txfifo_def, txfifo_def1;
2087         u16 txfifo_cmd;
2088
2089         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2090         txfifo_startblk = TXFIFO_START_BLK;
2091
2092         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2093         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2094
2095                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2096                 txfifo_def = (txfifo_startblk & 0xff) |
2097                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2098                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2099                     ((((txfifo_endblk -
2100                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2101                 txfifo_cmd =
2102                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2103
2104                 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2105                 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
2106                 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
2107
2108                 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2109
2110                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2111         }
2112         /*
2113          * need to propagate to shm location to be in sync since ucode/hw won't
2114          * do this
2115          */
2116         brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2117                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2118         brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2119                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2120         brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2121                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2122                             xmtfifo_sz[TX_AC_BK_FIFO]));
2123         brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2124                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2125                             xmtfifo_sz[TX_BCMC_FIFO]));
2126 }
2127
2128 /* This function is used for changing the tsf frac register
2129  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2130  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2131  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2132  * HTPHY Formula is 2^26/freq(MHz) e.g.
2133  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2134  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2135  * For spuron: 123MHz -> 2^26/123    = 545600.5
2136  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2137  * For spur off: 120MHz -> 2^26/120    = 559240.5
2138  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2139  */
2140
2141 void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2142 {
2143         struct bcma_device *core = wlc_hw->d11core;
2144
2145         if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
2146             (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
2147                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2148                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
2149                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2150                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2151                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
2152                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2153                 } else {        /* 120Mhz */
2154                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
2155                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2156                 }
2157         } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2158                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2159                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
2160                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2161                 } else {        /* 80Mhz */
2162                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
2163                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2164                 }
2165         }
2166 }
2167
2168 /* Initialize GPIOs that are controlled by D11 core */
2169 static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2170 {
2171         struct brcms_hardware *wlc_hw = wlc->hw;
2172         u32 gc, gm;
2173
2174         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2175         brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2176
2177         /*
2178          * Common GPIO setup:
2179          *      G0 = LED 0 = WLAN Activity
2180          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2181          *      G2 = LED 2 = WLAN 5 GHz Radio State
2182          *      G4 = radio disable input (HI enabled, LO disabled)
2183          */
2184
2185         gc = gm = 0;
2186
2187         /* Allocate GPIOs for mimo antenna diversity feature */
2188         if (wlc_hw->antsel_type == ANTSEL_2x3) {
2189                 /* Enable antenna diversity, use 2x3 mode */
2190                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2191                              MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2192                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2193                              MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2194
2195                 /* init superswitch control */
2196                 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2197
2198         } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2199                 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2200                 /*
2201                  * The board itself is powered by these GPIOs
2202                  * (when not sending pattern) so set them high
2203                  */
2204                 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2205                            (BOARD_GPIO_12 | BOARD_GPIO_13));
2206                 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2207                            (BOARD_GPIO_12 | BOARD_GPIO_13));
2208
2209                 /* Enable antenna diversity, use 2x4 mode */
2210                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2211                              MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2212                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2213                              BRCM_BAND_ALL);
2214
2215                 /* Configure the desired clock to be 4Mhz */
2216                 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2217                                    ANTSEL_CLKDIV_4MHZ);
2218         }
2219
2220         /*
2221          * gpio 9 controls the PA. ucode is responsible
2222          * for wiggling out and oe
2223          */
2224         if (wlc_hw->boardflags & BFL_PACTRL)
2225                 gm |= gc |= BOARD_GPIO_PACTRL;
2226
2227         /* apply to gpiocontrol register */
2228         bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
2229 }
2230
2231 static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2232                               const __le32 ucode[], const size_t nbytes)
2233 {
2234         struct bcma_device *core = wlc_hw->d11core;
2235         uint i;
2236         uint count;
2237
2238         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2239
2240         count = (nbytes / sizeof(u32));
2241
2242         bcma_write32(core, D11REGOFFS(objaddr),
2243                      OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
2244         (void)bcma_read32(core, D11REGOFFS(objaddr));
2245         for (i = 0; i < count; i++)
2246                 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
2247
2248 }
2249
2250 static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2251 {
2252         struct brcms_c_info *wlc;
2253         struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2254
2255         wlc = wlc_hw->wlc;
2256
2257         if (wlc_hw->ucode_loaded)
2258                 return;
2259
2260         if (D11REV_IS(wlc_hw->corerev, 23)) {
2261                 if (BRCMS_ISNPHY(wlc_hw->band)) {
2262                         brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2263                                           ucode->bcm43xx_16_mimosz);
2264                         wlc_hw->ucode_loaded = true;
2265                 } else
2266                         wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2267                                   "corerev %d\n",
2268                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2269         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2270                 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2271                         brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2272                                           ucode->bcm43xx_24_lcnsz);
2273                         wlc_hw->ucode_loaded = true;
2274                 } else {
2275                         wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2276                                   "corerev %d\n",
2277                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2278                 }
2279         }
2280 }
2281
2282 void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2283 {
2284         /* update sw state */
2285         wlc_hw->bmac_phytxant = phytxant;
2286
2287         /* push to ucode if up */
2288         if (!wlc_hw->up)
2289                 return;
2290         brcms_c_ucode_txant_set(wlc_hw);
2291
2292 }
2293
2294 u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2295 {
2296         return (u16) wlc_hw->wlc->stf->txant;
2297 }
2298
2299 void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2300 {
2301         wlc_hw->antsel_type = antsel_type;
2302
2303         /* Update the antsel type for phy module to use */
2304         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2305 }
2306
2307 static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2308 {
2309         bool fatal = false;
2310         uint unit;
2311         uint intstatus, idx;
2312         struct bcma_device *core = wlc_hw->d11core;
2313         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2314
2315         unit = wlc_hw->unit;
2316
2317         for (idx = 0; idx < NFIFO; idx++) {
2318                 /* read intstatus register and ignore any non-error bits */
2319                 intstatus =
2320                         bcma_read32(core,
2321                                     D11REGOFFS(intctrlregs[idx].intstatus)) &
2322                         I_ERRORS;
2323                 if (!intstatus)
2324                         continue;
2325
2326                 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
2327                         unit, idx, intstatus);
2328
2329                 if (intstatus & I_RO) {
2330                         wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
2331                                   "overflow\n", unit, idx);
2332                         fatal = true;
2333                 }
2334
2335                 if (intstatus & I_PC) {
2336                         wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
2337                                  unit, idx);
2338                         fatal = true;
2339                 }
2340
2341                 if (intstatus & I_PD) {
2342                         wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
2343                                   idx);
2344                         fatal = true;
2345                 }
2346
2347                 if (intstatus & I_DE) {
2348                         wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
2349                                   "error\n", unit, idx);
2350                         fatal = true;
2351                 }
2352
2353                 if (intstatus & I_RU)
2354                         wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
2355                                   "underflow\n", idx, unit);
2356
2357                 if (intstatus & I_XU) {
2358                         wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
2359                                   "underflow\n", idx, unit);
2360                         fatal = true;
2361                 }
2362
2363                 if (fatal) {
2364                         brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2365                         break;
2366                 } else
2367                         bcma_write32(core,
2368                                      D11REGOFFS(intctrlregs[idx].intstatus),
2369                                      intstatus);
2370         }
2371 }
2372
2373 void brcms_c_intrson(struct brcms_c_info *wlc)
2374 {
2375         struct brcms_hardware *wlc_hw = wlc->hw;
2376         wlc->macintmask = wlc->defmacintmask;
2377         bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2378 }
2379
2380 u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2381 {
2382         struct brcms_hardware *wlc_hw = wlc->hw;
2383         u32 macintmask;
2384
2385         if (!wlc_hw->clk)
2386                 return 0;
2387
2388         macintmask = wlc->macintmask;   /* isr can still happen */
2389
2390         bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2391         (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2392         udelay(1);              /* ensure int line is no longer driven */
2393         wlc->macintmask = 0;
2394
2395         /* return previous macintmask; resolve race between us and our isr */
2396         return wlc->macintstatus ? 0 : macintmask;
2397 }
2398
2399 void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2400 {
2401         struct brcms_hardware *wlc_hw = wlc->hw;
2402         if (!wlc_hw->clk)
2403                 return;
2404
2405         wlc->macintmask = macintmask;
2406         bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2407 }
2408
2409 /* assumes that the d11 MAC is enabled */
2410 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2411                                     uint tx_fifo)
2412 {
2413         u8 fifo = 1 << tx_fifo;
2414
2415         /* Two clients of this code, 11h Quiet period and scanning. */
2416
2417         /* only suspend if not already suspended */
2418         if ((wlc_hw->suspended_fifos & fifo) == fifo)
2419                 return;
2420
2421         /* force the core awake only if not already */
2422         if (wlc_hw->suspended_fifos == 0)
2423                 brcms_c_ucode_wake_override_set(wlc_hw,
2424                                                 BRCMS_WAKE_OVERRIDE_TXFIFO);
2425
2426         wlc_hw->suspended_fifos |= fifo;
2427
2428         if (wlc_hw->di[tx_fifo]) {
2429                 /*
2430                  * Suspending AMPDU transmissions in the middle can cause
2431                  * underflow which may result in mismatch between ucode and
2432                  * driver so suspend the mac before suspending the FIFO
2433                  */
2434                 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2435                         brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2436
2437                 dma_txsuspend(wlc_hw->di[tx_fifo]);
2438
2439                 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2440                         brcms_c_enable_mac(wlc_hw->wlc);
2441         }
2442 }
2443
2444 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2445                                    uint tx_fifo)
2446 {
2447         /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2448          * but need to be done here for PIO otherwise the watchdog will catch
2449          * the inconsistency and fire
2450          */
2451         /* Two clients of this code, 11h Quiet period and scanning. */
2452         if (wlc_hw->di[tx_fifo])
2453                 dma_txresume(wlc_hw->di[tx_fifo]);
2454
2455         /* allow core to sleep again */
2456         if (wlc_hw->suspended_fifos == 0)
2457                 return;
2458         else {
2459                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2460                 if (wlc_hw->suspended_fifos == 0)
2461                         brcms_c_ucode_wake_override_clear(wlc_hw,
2462                                                 BRCMS_WAKE_OVERRIDE_TXFIFO);
2463         }
2464 }
2465
2466 /* precondition: requires the mac core to be enabled */
2467 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2468 {
2469         static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2470
2471         if (mute_tx) {
2472                 /* suspend tx fifos */
2473                 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2474                 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2475                 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2476                 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2477
2478                 /* zero the address match register so we do not send ACKs */
2479                 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2480                                        null_ether_addr);
2481         } else {
2482                 /* resume tx fifos */
2483                 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2484                 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2485                 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2486                 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2487
2488                 /* Restore address */
2489                 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2490                                        wlc_hw->etheraddr);
2491         }
2492
2493         wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2494
2495         if (mute_tx)
2496                 brcms_c_ucode_mute_override_set(wlc_hw);
2497         else
2498                 brcms_c_ucode_mute_override_clear(wlc_hw);
2499 }
2500
2501 void
2502 brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2503 {
2504         brcms_b_mute(wlc->hw, mute_tx);
2505 }
2506
2507 /*
2508  * Read and clear macintmask and macintstatus and intstatus registers.
2509  * This routine should be called with interrupts off
2510  * Return:
2511  *   -1 if brcms_deviceremoved(wlc) evaluates to true;
2512  *   0 if the interrupt is not for us, or we are in some special cases;
2513  *   device interrupt status bits otherwise.
2514  */
2515 static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2516 {
2517         struct brcms_hardware *wlc_hw = wlc->hw;
2518         struct bcma_device *core = wlc_hw->d11core;
2519         u32 macintstatus;
2520
2521         /* macintstatus includes a DMA interrupt summary bit */
2522         macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
2523
2524         BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
2525                  macintstatus);
2526
2527         /* detect cardbus removed, in power down(suspend) and in reset */
2528         if (brcms_deviceremoved(wlc))
2529                 return -1;
2530
2531         /* brcms_deviceremoved() succeeds even when the core is still resetting,
2532          * handle that case here.
2533          */
2534         if (macintstatus == 0xffffffff)
2535                 return 0;
2536
2537         /* defer unsolicited interrupts */
2538         macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2539
2540         /* if not for us */
2541         if (macintstatus == 0)
2542                 return 0;
2543
2544         /* interrupts are already turned off for CFE build
2545          * Caution: For CFE Turning off the interrupts again has some undesired
2546          * consequences
2547          */
2548         /* turn off the interrupts */
2549         bcma_write32(core, D11REGOFFS(macintmask), 0);
2550         (void)bcma_read32(core, D11REGOFFS(macintmask));
2551         wlc->macintmask = 0;
2552
2553         /* clear device interrupts */
2554         bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
2555
2556         /* MI_DMAINT is indication of non-zero intstatus */
2557         if (macintstatus & MI_DMAINT)
2558                 /*
2559                  * only fifo interrupt enabled is I_RI in
2560                  * RX_FIFO. If MI_DMAINT is set, assume it
2561                  * is set and clear the interrupt.
2562                  */
2563                 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
2564                              DEF_RXINTMASK);
2565
2566         return macintstatus;
2567 }
2568
2569 /* Update wlc->macintstatus and wlc->intstatus[]. */
2570 /* Return true if they are updated successfully. false otherwise */
2571 bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2572 {
2573         u32 macintstatus;
2574
2575         /* read and clear macintstatus and intstatus registers */
2576         macintstatus = wlc_intstatus(wlc, false);
2577
2578         /* device is removed */
2579         if (macintstatus == 0xffffffff)
2580                 return false;
2581
2582         /* update interrupt status in software */
2583         wlc->macintstatus |= macintstatus;
2584
2585         return true;
2586 }
2587
2588 /*
2589  * First-level interrupt processing.
2590  * Return true if this was our interrupt, false otherwise.
2591  * *wantdpc will be set to true if further brcms_c_dpc() processing is required,
2592  * false otherwise.
2593  */
2594 bool brcms_c_isr(struct brcms_c_info *wlc, bool *wantdpc)
2595 {
2596         struct brcms_hardware *wlc_hw = wlc->hw;
2597         u32 macintstatus;
2598
2599         *wantdpc = false;
2600
2601         if (!wlc_hw->up || !wlc->macintmask)
2602                 return false;
2603
2604         /* read and clear macintstatus and intstatus registers */
2605         macintstatus = wlc_intstatus(wlc, true);
2606
2607         if (macintstatus == 0xffffffff)
2608                 wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
2609                           " path\n");
2610
2611         /* it is not for us */
2612         if (macintstatus == 0)
2613                 return false;
2614
2615         *wantdpc = true;
2616
2617         /* save interrupt status bits */
2618         wlc->macintstatus = macintstatus;
2619
2620         return true;
2621
2622 }
2623
2624 void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2625 {
2626         struct brcms_hardware *wlc_hw = wlc->hw;
2627         struct bcma_device *core = wlc_hw->d11core;
2628         u32 mc, mi;
2629         struct wiphy *wiphy = wlc->wiphy;
2630
2631         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
2632                 wlc_hw->band->bandunit);
2633
2634         /*
2635          * Track overlapping suspend requests
2636          */
2637         wlc_hw->mac_suspend_depth++;
2638         if (wlc_hw->mac_suspend_depth > 1)
2639                 return;
2640
2641         /* force the core awake */
2642         brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2643
2644         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2645
2646         if (mc == 0xffffffff) {
2647                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2648                           __func__);
2649                 brcms_down(wlc->wl);
2650                 return;
2651         }
2652         WARN_ON(mc & MCTL_PSM_JMP_0);
2653         WARN_ON(!(mc & MCTL_PSM_RUN));
2654         WARN_ON(!(mc & MCTL_EN_MAC));
2655
2656         mi = bcma_read32(core, D11REGOFFS(macintstatus));
2657         if (mi == 0xffffffff) {
2658                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2659                           __func__);
2660                 brcms_down(wlc->wl);
2661                 return;
2662         }
2663         WARN_ON(mi & MI_MACSSPNDD);
2664
2665         brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2666
2667         SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
2668                  BRCMS_MAX_MAC_SUSPEND);
2669
2670         if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
2671                 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2672                           " and MI_MACSSPNDD is still not on.\n",
2673                           wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2674                 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2675                           "psm_brc 0x%04x\n", wlc_hw->unit,
2676                           bcma_read32(core, D11REGOFFS(psmdebug)),
2677                           bcma_read32(core, D11REGOFFS(phydebug)),
2678                           bcma_read16(core, D11REGOFFS(psm_brc)));
2679         }
2680
2681         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2682         if (mc == 0xffffffff) {
2683                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2684                           __func__);
2685                 brcms_down(wlc->wl);
2686                 return;
2687         }
2688         WARN_ON(mc & MCTL_PSM_JMP_0);
2689         WARN_ON(!(mc & MCTL_PSM_RUN));
2690         WARN_ON(mc & MCTL_EN_MAC);
2691 }
2692
2693 void brcms_c_enable_mac(struct brcms_c_info *wlc)
2694 {
2695         struct brcms_hardware *wlc_hw = wlc->hw;
2696         struct bcma_device *core = wlc_hw->d11core;
2697         u32 mc, mi;
2698
2699         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
2700                 wlc->band->bandunit);
2701
2702         /*
2703          * Track overlapping suspend requests
2704          */
2705         wlc_hw->mac_suspend_depth--;
2706         if (wlc_hw->mac_suspend_depth > 0)
2707                 return;
2708
2709         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2710         WARN_ON(mc & MCTL_PSM_JMP_0);
2711         WARN_ON(mc & MCTL_EN_MAC);
2712         WARN_ON(!(mc & MCTL_PSM_RUN));
2713
2714         brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2715         bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
2716
2717         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2718         WARN_ON(mc & MCTL_PSM_JMP_0);
2719         WARN_ON(!(mc & MCTL_EN_MAC));
2720         WARN_ON(!(mc & MCTL_PSM_RUN));
2721
2722         mi = bcma_read32(core, D11REGOFFS(macintstatus));
2723         WARN_ON(mi & MI_MACSSPNDD);
2724
2725         brcms_c_ucode_wake_override_clear(wlc_hw,
2726                                           BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2727 }
2728
2729 void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2730 {
2731         wlc_hw->hw_stf_ss_opmode = stf_mode;
2732
2733         if (wlc_hw->clk)
2734                 brcms_upd_ofdm_pctl1_table(wlc_hw);
2735 }
2736
2737 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2738 {
2739         struct bcma_device *core = wlc_hw->d11core;
2740         u32 w, val;
2741         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2742
2743         BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
2744
2745         /* Validate dchip register access */
2746
2747         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2748         (void)bcma_read32(core, D11REGOFFS(objaddr));
2749         w = bcma_read32(core, D11REGOFFS(objdata));
2750
2751         /* Can we write and read back a 32bit register? */
2752         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2753         (void)bcma_read32(core, D11REGOFFS(objaddr));
2754         bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
2755
2756         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2757         (void)bcma_read32(core, D11REGOFFS(objaddr));
2758         val = bcma_read32(core, D11REGOFFS(objdata));
2759         if (val != (u32) 0xaa5555aa) {
2760                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2761                           "expected 0xaa5555aa\n", wlc_hw->unit, val);
2762                 return false;
2763         }
2764
2765         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2766         (void)bcma_read32(core, D11REGOFFS(objaddr));
2767         bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
2768
2769         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2770         (void)bcma_read32(core, D11REGOFFS(objaddr));
2771         val = bcma_read32(core, D11REGOFFS(objdata));
2772         if (val != (u32) 0x55aaaa55) {
2773                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2774                           "expected 0x55aaaa55\n", wlc_hw->unit, val);
2775                 return false;
2776         }
2777
2778         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2779         (void)bcma_read32(core, D11REGOFFS(objaddr));
2780         bcma_write32(core, D11REGOFFS(objdata), w);
2781
2782         /* clear CFPStart */
2783         bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
2784
2785         w = bcma_read32(core, D11REGOFFS(maccontrol));
2786         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2787             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2788                 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
2789                           "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2790                           (MCTL_IHR_EN | MCTL_WAKE),
2791                           (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
2792                 return false;
2793         }
2794
2795         return true;
2796 }
2797
2798 #define PHYPLL_WAIT_US  100000
2799
2800 void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2801 {
2802         struct bcma_device *core = wlc_hw->d11core;
2803         u32 tmp;
2804
2805         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2806
2807         tmp = 0;
2808
2809         if (on) {
2810                 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
2811                         bcma_set32(core, D11REGOFFS(clk_ctl_st),
2812                                    CCS_ERSRC_REQ_HT |
2813                                    CCS_ERSRC_REQ_D11PLL |
2814                                    CCS_ERSRC_REQ_PHYPLL);
2815                         SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2816                                   CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
2817                                  PHYPLL_WAIT_US);
2818
2819                         tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2820                         if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
2821                                 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
2822                                           " PLL failed\n", __func__);
2823                 } else {
2824                         bcma_set32(core, D11REGOFFS(clk_ctl_st),
2825                                    tmp | CCS_ERSRC_REQ_D11PLL |
2826                                    CCS_ERSRC_REQ_PHYPLL);
2827                         SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2828                                   (CCS_ERSRC_AVAIL_D11PLL |
2829                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
2830                                  (CCS_ERSRC_AVAIL_D11PLL |
2831                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2832
2833                         tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2834                         if ((tmp &
2835                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2836                             !=
2837                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2838                                 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
2839                                           "PHY PLL failed\n", __func__);
2840                 }
2841         } else {
2842                 /*
2843                  * Since the PLL may be shared, other cores can still
2844                  * be requesting it; so we'll deassert the request but
2845                  * not wait for status to comply.
2846                  */
2847                 bcma_mask32(core, D11REGOFFS(clk_ctl_st),
2848                             ~CCS_ERSRC_REQ_PHYPLL);
2849                 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
2850         }
2851 }
2852
2853 static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2854 {
2855         bool dev_gone;
2856
2857         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2858
2859         dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2860
2861         if (dev_gone)
2862                 return;
2863
2864         if (wlc_hw->noreset)
2865                 return;
2866
2867         /* radio off */
2868         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2869
2870         /* turn off analog core */
2871         wlc_phy_anacore(wlc_hw->band->pi, OFF);
2872
2873         /* turn off PHYPLL to save power */
2874         brcms_b_core_phypll_ctl(wlc_hw, false);
2875
2876         wlc_hw->clk = false;
2877         bcma_core_disable(wlc_hw->d11core, 0);
2878         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2879 }
2880
2881 static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2882 {
2883         struct brcms_hardware *wlc_hw = wlc->hw;
2884         uint i;
2885
2886         /* free any posted tx packets */
2887         for (i = 0; i < NFIFO; i++)
2888                 if (wlc_hw->di[i]) {
2889                         dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
2890                         wlc->core->txpktpend[i] = 0;
2891                         BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
2892                 }
2893
2894         /* free any posted rx packets */
2895         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
2896 }
2897
2898 static u16
2899 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2900 {
2901         struct bcma_device *core = wlc_hw->d11core;
2902         u16 objoff = D11REGOFFS(objdata);
2903
2904         bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2905         (void)bcma_read32(core, D11REGOFFS(objaddr));
2906         if (offset & 2)
2907                 objoff += 2;
2908
2909         return bcma_read16(core, objoff);
2910 }
2911
2912 static void
2913 brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2914                      u32 sel)
2915 {
2916         struct bcma_device *core = wlc_hw->d11core;
2917         u16 objoff = D11REGOFFS(objdata);
2918
2919         bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2920         (void)bcma_read32(core, D11REGOFFS(objaddr));
2921         if (offset & 2)
2922                 objoff += 2;
2923
2924         bcma_write16(core, objoff, v);
2925 }
2926
2927 /*
2928  * Read a single u16 from shared memory.
2929  * SHM 'offset' needs to be an even address
2930  */
2931 u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
2932 {
2933         return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
2934 }
2935
2936 /*
2937  * Write a single u16 to shared memory.
2938  * SHM 'offset' needs to be an even address
2939  */
2940 void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
2941 {
2942         brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
2943 }
2944
2945 /*
2946  * Copy a buffer to shared memory of specified type .
2947  * SHM 'offset' needs to be an even address and
2948  * Buffer length 'len' must be an even number of bytes
2949  * 'sel' selects the type of memory
2950  */
2951 void
2952 brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
2953                       const void *buf, int len, u32 sel)
2954 {
2955         u16 v;
2956         const u8 *p = (const u8 *)buf;
2957         int i;
2958
2959         if (len <= 0 || (offset & 1) || (len & 1))
2960                 return;
2961
2962         for (i = 0; i < len; i += 2) {
2963                 v = p[i] | (p[i + 1] << 8);
2964                 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
2965         }
2966 }
2967
2968 /*
2969  * Copy a piece of shared memory of specified type to a buffer .
2970  * SHM 'offset' needs to be an even address and
2971  * Buffer length 'len' must be an even number of bytes
2972  * 'sel' selects the type of memory
2973  */
2974 void
2975 brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
2976                          int len, u32 sel)
2977 {
2978         u16 v;
2979         u8 *p = (u8 *) buf;
2980         int i;
2981
2982         if (len <= 0 || (offset & 1) || (len & 1))
2983                 return;
2984
2985         for (i = 0; i < len; i += 2) {
2986                 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
2987                 p[i] = v & 0xFF;
2988                 p[i + 1] = (v >> 8) & 0xFF;
2989         }
2990 }
2991
2992 /* Copy a buffer to shared memory.
2993  * SHM 'offset' needs to be an even address and
2994  * Buffer length 'len' must be an even number of bytes
2995  */
2996 static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
2997                         const void *buf, int len)
2998 {
2999         brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
3000 }
3001
3002 static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
3003                                    u16 SRL, u16 LRL)
3004 {
3005         wlc_hw->SRL = SRL;
3006         wlc_hw->LRL = LRL;
3007
3008         /* write retry limit to SCR, shouldn't need to suspend */
3009         if (wlc_hw->up) {
3010                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3011                              OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3012                 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3013                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
3014                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3015                              OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3016                 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3017                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3018         }
3019 }
3020
3021 static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3022 {
3023         if (set) {
3024                 if (mboolisset(wlc_hw->pllreq, req_bit))
3025                         return;
3026
3027                 mboolset(wlc_hw->pllreq, req_bit);
3028
3029                 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3030                         if (!wlc_hw->sbclk)
3031                                 brcms_b_xtal(wlc_hw, ON);
3032                 }
3033         } else {
3034                 if (!mboolisset(wlc_hw->pllreq, req_bit))
3035                         return;
3036
3037                 mboolclr(wlc_hw->pllreq, req_bit);
3038
3039                 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3040                         if (wlc_hw->sbclk)
3041                                 brcms_b_xtal(wlc_hw, OFF);
3042                 }
3043         }
3044 }
3045
3046 static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3047 {
3048         wlc_hw->antsel_avail = antsel_avail;
3049 }
3050
3051 /*
3052  * conditions under which the PM bit should be set in outgoing frames
3053  * and STAY_AWAKE is meaningful
3054  */
3055 static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
3056 {
3057         struct brcms_bss_cfg *cfg = wlc->bsscfg;
3058
3059         /* disallow PS when one of the following global conditions meets */
3060         if (!wlc->pub->associated)
3061                 return false;
3062
3063         /* disallow PS when one of these meets when not scanning */
3064         if (wlc->filter_flags & FIF_PROMISC_IN_BSS)
3065                 return false;
3066
3067         if (cfg->associated) {
3068                 /*
3069                  * disallow PS when one of the following
3070                  * bsscfg specific conditions meets
3071                  */
3072                 if (!cfg->BSS)
3073                         return false;
3074
3075                 return false;
3076         }
3077
3078         return true;
3079 }
3080
3081 static void brcms_c_statsupd(struct brcms_c_info *wlc)
3082 {
3083         int i;
3084         struct macstat macstats;
3085 #ifdef DEBUG
3086         u16 delta;
3087         u16 rxf0ovfl;
3088         u16 txfunfl[NFIFO];
3089 #endif                          /* DEBUG */
3090
3091         /* if driver down, make no sense to update stats */
3092         if (!wlc->pub->up)
3093                 return;
3094
3095 #ifdef DEBUG
3096         /* save last rx fifo 0 overflow count */
3097         rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
3098
3099         /* save last tx fifo  underflow count */
3100         for (i = 0; i < NFIFO; i++)
3101                 txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
3102 #endif                          /* DEBUG */
3103
3104         /* Read mac stats from contiguous shared memory */
3105         brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
3106                                 sizeof(struct macstat), OBJADDR_SHM_SEL);
3107
3108 #ifdef DEBUG
3109         /* check for rx fifo 0 overflow */
3110         delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
3111         if (delta)
3112                 wiphy_err(wlc->wiphy, "wl%d: %u rx fifo 0 overflows!\n",
3113                           wlc->pub->unit, delta);
3114
3115         /* check for tx fifo underflows */
3116         for (i = 0; i < NFIFO; i++) {
3117                 delta =
3118                     (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
3119                               txfunfl[i]);
3120                 if (delta)
3121                         wiphy_err(wlc->wiphy, "wl%d: %u tx fifo %d underflows!"
3122                                   "\n", wlc->pub->unit, delta, i);
3123         }
3124 #endif                          /* DEBUG */
3125
3126         /* merge counters from dma module */
3127         for (i = 0; i < NFIFO; i++) {
3128                 if (wlc->hw->di[i])
3129                         dma_counterreset(wlc->hw->di[i]);
3130         }
3131 }
3132
3133 static void brcms_b_reset(struct brcms_hardware *wlc_hw)
3134 {
3135         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3136
3137         /* reset the core */
3138         if (!brcms_deviceremoved(wlc_hw->wlc))
3139                 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
3140
3141         /* purge the dma rings */
3142         brcms_c_flushqueues(wlc_hw->wlc);
3143 }
3144
3145 void brcms_c_reset(struct brcms_c_info *wlc)
3146 {
3147         BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
3148
3149         /* slurp up hw mac counters before core reset */
3150         brcms_c_statsupd(wlc);
3151
3152         /* reset our snapshot of macstat counters */
3153         memset((char *)wlc->core->macstat_snapshot, 0,
3154                 sizeof(struct macstat));
3155
3156         brcms_b_reset(wlc->hw);
3157 }
3158
3159 void brcms_c_init_scb(struct scb *scb)
3160 {
3161         int i;
3162
3163         memset(scb, 0, sizeof(struct scb));
3164         scb->flags = SCB_WMECAP | SCB_HTCAP;
3165         for (i = 0; i < NUMPRIO; i++) {
3166                 scb->seqnum[i] = 0;
3167                 scb->seqctl[i] = 0xFFFF;
3168         }
3169
3170         scb->seqctl_nonqos = 0xFFFF;
3171         scb->magic = SCB_MAGIC;
3172 }
3173
3174 /* d11 core init
3175  *   reset PSM
3176  *   download ucode/PCM
3177  *   let ucode run to suspended
3178  *   download ucode inits
3179  *   config other core registers
3180  *   init dma
3181  */
3182 static void brcms_b_coreinit(struct brcms_c_info *wlc)
3183 {
3184         struct brcms_hardware *wlc_hw = wlc->hw;
3185         struct bcma_device *core = wlc_hw->d11core;
3186         u32 sflags;
3187         u32 bcnint_us;
3188         uint i = 0;
3189         bool fifosz_fixup = false;
3190         int err = 0;
3191         u16 buf[NFIFO];
3192         struct wiphy *wiphy = wlc->wiphy;
3193         struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
3194
3195         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
3196
3197         /* reset PSM */
3198         brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
3199
3200         brcms_ucode_download(wlc_hw);
3201         /*
3202          * FIFOSZ fixup. driver wants to controls the fifo allocation.
3203          */
3204         fifosz_fixup = true;
3205
3206         /* let the PSM run to the suspended state, set mode to BSS STA */
3207         bcma_write32(core, D11REGOFFS(macintstatus), -1);
3208         brcms_b_mctrl(wlc_hw, ~0,
3209                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
3210
3211         /* wait for ucode to self-suspend after auto-init */
3212         SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
3213                    MI_MACSSPNDD) == 0), 1000 * 1000);
3214         if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
3215                 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
3216                           "suspend!\n", wlc_hw->unit);
3217
3218         brcms_c_gpio_init(wlc);
3219
3220         sflags = bcma_aread32(core, BCMA_IOST);
3221
3222         if (D11REV_IS(wlc_hw->corerev, 23)) {
3223                 if (BRCMS_ISNPHY(wlc_hw->band))
3224                         brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
3225                 else
3226                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
3227                                   " %d\n", __func__, wlc_hw->unit,
3228                                   wlc_hw->corerev);
3229         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
3230                 if (BRCMS_ISLCNPHY(wlc_hw->band))
3231                         brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
3232                 else
3233                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
3234                                   " %d\n", __func__, wlc_hw->unit,
3235                                   wlc_hw->corerev);
3236         } else {
3237                 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
3238                           __func__, wlc_hw->unit, wlc_hw->corerev);
3239         }
3240
3241         /* For old ucode, txfifo sizes needs to be modified(increased) */
3242         if (fifosz_fixup)
3243                 brcms_b_corerev_fifofixup(wlc_hw);
3244
3245         /* check txfifo allocations match between ucode and driver */
3246         buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
3247         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
3248                 i = TX_AC_BE_FIFO;
3249                 err = -1;
3250         }
3251         buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
3252         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
3253                 i = TX_AC_VI_FIFO;
3254                 err = -1;
3255         }
3256         buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
3257         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
3258         buf[TX_AC_BK_FIFO] &= 0xff;
3259         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
3260                 i = TX_AC_BK_FIFO;
3261                 err = -1;
3262         }
3263         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
3264                 i = TX_AC_VO_FIFO;
3265                 err = -1;
3266         }
3267         buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
3268         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
3269         buf[TX_BCMC_FIFO] &= 0xff;
3270         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
3271                 i = TX_BCMC_FIFO;
3272                 err = -1;
3273         }
3274         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
3275                 i = TX_ATIM_FIFO;
3276                 err = -1;
3277         }
3278         if (err != 0)
3279                 wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
3280                           " driver size %d index %d\n", buf[i],
3281                           wlc_hw->xmtfifo_sz[i], i);
3282
3283         /* make sure we can still talk to the mac */
3284         WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
3285
3286         /* band-specific inits done by wlc_bsinit() */
3287
3288         /* Set up frame burst size and antenna swap threshold init values */
3289         brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
3290         brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
3291
3292         /* enable one rx interrupt per received frame */
3293         bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
3294
3295         /* set the station mode (BSS STA) */
3296         brcms_b_mctrl(wlc_hw,
3297                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
3298                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
3299
3300         /* set up Beacon interval */
3301         bcnint_us = 0x8000 << 10;
3302         bcma_write32(core, D11REGOFFS(tsf_cfprep),
3303                      (bcnint_us << CFPREP_CBI_SHIFT));
3304         bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
3305         bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
3306
3307         /* write interrupt mask */
3308         bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
3309                      DEF_RXINTMASK);
3310
3311         /* allow the MAC to control the PHY clock (dynamic on/off) */
3312         brcms_b_macphyclk_set(wlc_hw, ON);
3313
3314         /* program dynamic clock control fast powerup delay register */
3315         wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
3316         bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
3317
3318         /* tell the ucode the corerev */
3319         brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
3320
3321         /* tell the ucode MAC capabilities */
3322         brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
3323                            (u16) (wlc_hw->machwcap & 0xffff));
3324         brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
3325                            (u16) ((wlc_hw->
3326                                       machwcap >> 16) & 0xffff));
3327
3328         /* write retry limits to SCR, this done after PSM init */
3329         bcma_write32(core, D11REGOFFS(objaddr),
3330                      OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3331         (void)bcma_read32(core, D11REGOFFS(objaddr));
3332         bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
3333         bcma_write32(core, D11REGOFFS(objaddr),
3334                      OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3335         (void)bcma_read32(core, D11REGOFFS(objaddr));
3336         bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
3337
3338         /* write rate fallback retry limits */
3339         brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
3340         brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
3341
3342         bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
3343         bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
3344
3345         /* init the tx dma engines */
3346         for (i = 0; i < NFIFO; i++) {
3347                 if (wlc_hw->di[i])
3348                         dma_txinit(wlc_hw->di[i]);
3349         }
3350
3351         /* init the rx dma engine(s) and post receive buffers */
3352         dma_rxinit(wlc_hw->di[RX_FIFO]);
3353         dma_rxfill(wlc_hw->di[RX_FIFO]);
3354 }
3355
3356 void
3357 static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
3358         u32 macintmask;
3359         bool fastclk;
3360         struct brcms_c_info *wlc = wlc_hw->wlc;
3361
3362         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3363
3364         /* request FAST clock if not on */
3365         fastclk = wlc_hw->forcefastclk;
3366         if (!fastclk)
3367                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
3368
3369         /* disable interrupts */
3370         macintmask = brcms_intrsoff(wlc->wl);
3371
3372         /* set up the specified band and chanspec */
3373         brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
3374         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3375
3376         /* do one-time phy inits and calibration */
3377         wlc_phy_cal_init(wlc_hw->band->pi);
3378
3379         /* core-specific initialization */
3380         brcms_b_coreinit(wlc);
3381
3382         /* band-specific inits */
3383         brcms_b_bsinit(wlc, chanspec);
3384
3385         /* restore macintmask */
3386         brcms_intrsrestore(wlc->wl, macintmask);
3387
3388         /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
3389          * is suspended and brcms_c_enable_mac() will clear this override bit.
3390          */
3391         mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3392
3393         /*
3394          * initialize mac_suspend_depth to 1 to match ucode
3395          * initial suspended state
3396          */
3397         wlc_hw->mac_suspend_depth = 1;
3398
3399         /* restore the clk */
3400         if (!fastclk)
3401                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
3402 }
3403
3404 static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
3405                                      u16 chanspec)
3406 {
3407         /* Save our copy of the chanspec */
3408         wlc->chanspec = chanspec;
3409
3410         /* Set the chanspec and power limits for this locale */
3411         brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
3412
3413         if (wlc->stf->ss_algosel_auto)
3414                 brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
3415                                             chanspec);
3416
3417         brcms_c_stf_ss_update(wlc, wlc->band);
3418 }
3419
3420 static void
3421 brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
3422 {
3423         brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
3424                 wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
3425                 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
3426                 brcms_chspec_bw(wlc->default_bss->chanspec),
3427                 wlc->stf->txstreams);
3428 }
3429
3430 /* derive wlc->band->basic_rate[] table from 'rateset' */
3431 static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
3432                               struct brcms_c_rateset *rateset)
3433 {
3434         u8 rate;
3435         u8 mandatory;
3436         u8 cck_basic = 0;
3437         u8 ofdm_basic = 0;
3438         u8 *br = wlc->band->basic_rate;
3439         uint i;
3440
3441         /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
3442         memset(br, 0, BRCM_MAXRATE + 1);
3443
3444         /* For each basic rate in the rates list, make an entry in the
3445          * best basic lookup.
3446          */
3447         for (i = 0; i < rateset->count; i++) {
3448                 /* only make an entry for a basic rate */
3449                 if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
3450                         continue;
3451
3452                 /* mask off basic bit */
3453                 rate = (rateset->rates[i] & BRCMS_RATE_MASK);
3454
3455                 if (rate > BRCM_MAXRATE) {
3456                         wiphy_err(wlc->wiphy, "brcms_c_rate_lookup_init: "
3457                                   "invalid rate 0x%X in rate set\n",
3458                                   rateset->rates[i]);
3459                         continue;
3460                 }
3461
3462                 br[rate] = rate;
3463         }
3464
3465         /* The rate lookup table now has non-zero entries for each
3466          * basic rate, equal to the basic rate: br[basicN] = basicN
3467          *
3468          * To look up the best basic rate corresponding to any
3469          * particular rate, code can use the basic_rate table
3470          * like this
3471          *
3472          * basic_rate = wlc->band->basic_rate[tx_rate]
3473          *
3474          * Make sure there is a best basic rate entry for
3475          * every rate by walking up the table from low rates
3476          * to high, filling in holes in the lookup table
3477          */
3478
3479         for (i = 0; i < wlc->band->hw_rateset.count; i++) {
3480                 rate = wlc->band->hw_rateset.rates[i];
3481
3482                 if (br[rate] != 0) {
3483                         /* This rate is a basic rate.
3484                          * Keep track of the best basic rate so far by
3485                          * modulation type.
3486                          */
3487                         if (is_ofdm_rate(rate))
3488                                 ofdm_basic = rate;
3489                         else
3490                                 cck_basic = rate;
3491
3492                         continue;
3493                 }
3494
3495                 /* This rate is not a basic rate so figure out the
3496                  * best basic rate less than this rate and fill in
3497                  * the hole in the table
3498                  */
3499
3500                 br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
3501
3502                 if (br[rate] != 0)
3503                         continue;
3504
3505                 if (is_ofdm_rate(rate)) {
3506                         /*
3507                          * In 11g and 11a, the OFDM mandatory rates
3508                          * are 6, 12, and 24 Mbps
3509                          */
3510                         if (rate >= BRCM_RATE_24M)
3511                                 mandatory = BRCM_RATE_24M;
3512                         else if (rate >= BRCM_RATE_12M)
3513                                 mandatory = BRCM_RATE_12M;
3514                         else
3515                                 mandatory = BRCM_RATE_6M;
3516                 } else {
3517                         /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
3518                         mandatory = rate;
3519                 }
3520
3521                 br[rate] = mandatory;
3522         }
3523 }
3524
3525 static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
3526                                      u16 chanspec)
3527 {
3528         struct brcms_c_rateset default_rateset;
3529         uint parkband;
3530         uint i, band_order[2];
3531
3532         BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
3533         /*
3534          * We might have been bandlocked during down and the chip
3535          * power-cycled (hibernate). Figure out the right band to park on
3536          */
3537         if (wlc->bandlocked || wlc->pub->_nbands == 1) {
3538                 /* updated in brcms_c_bandlock() */
3539                 parkband = wlc->band->bandunit;
3540                 band_order[0] = band_order[1] = parkband;
3541         } else {
3542                 /* park on the band of the specified chanspec */
3543                 parkband = chspec_bandunit(chanspec);
3544
3545                 /* order so that parkband initialize last */
3546                 band_order[0] = parkband ^ 1;
3547                 band_order[1] = parkband;
3548         }
3549
3550         /* make each band operational, software state init */
3551         for (i = 0; i < wlc->pub->_nbands; i++) {
3552                 uint j = band_order[i];
3553
3554                 wlc->band = wlc->bandstate[j];
3555
3556                 brcms_default_rateset(wlc, &default_rateset);
3557
3558                 /* fill in hw_rate */
3559                 brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
3560                                    false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
3561                                    (bool) (wlc->pub->_n_enab & SUPPORT_11N));
3562
3563                 /* init basic rate lookup */
3564                 brcms_c_rate_lookup_init(wlc, &default_rateset);
3565         }
3566
3567         /* sync up phy/radio chanspec */
3568         brcms_c_set_phy_chanspec(wlc, chanspec);
3569 }
3570
3571 /*
3572  * Set or clear filtering related maccontrol bits based on
3573  * specified filter flags
3574  */
3575 void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags)
3576 {
3577         u32 promisc_bits = 0;
3578
3579         wlc->filter_flags = filter_flags;
3580
3581         if (filter_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS))
3582                 promisc_bits |= MCTL_PROMISC;
3583
3584         if (filter_flags & FIF_BCN_PRBRESP_PROMISC)
3585                 promisc_bits |= MCTL_BCNS_PROMISC;
3586
3587         if (filter_flags & FIF_FCSFAIL)
3588                 promisc_bits |= MCTL_KEEPBADFCS;
3589
3590         if (filter_flags & (FIF_CONTROL | FIF_PSPOLL))
3591                 promisc_bits |= MCTL_KEEPCONTROL;
3592
3593         brcms_b_mctrl(wlc->hw,
3594                 MCTL_PROMISC | MCTL_BCNS_PROMISC |
3595                 MCTL_KEEPCONTROL | MCTL_KEEPBADFCS,
3596                 promisc_bits);
3597 }
3598
3599 /*
3600  * ucode, hwmac update
3601  *    Channel dependent updates for ucode and hw
3602  */
3603 static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
3604 {
3605         /* enable or disable any active IBSSs depending on whether or not
3606          * we are on the home channel
3607          */
3608         if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
3609                 if (wlc->pub->associated) {
3610                         /*
3611                          * BMAC_NOTE: This is something that should be fixed
3612                          * in ucode inits. I think that the ucode inits set
3613                          * up the bcn templates and shm values with a bogus
3614                          * beacon. This should not be done in the inits. If
3615                          * ucode needs to set up a beacon for testing, the
3616                          * test routines should write it down, not expect the
3617                          * inits to populate a bogus beacon.
3618                          */
3619                         if (BRCMS_PHY_11N_CAP(wlc->band))
3620                                 brcms_b_write_shm(wlc->hw,
3621                                                 M_BCN_TXTSF_OFFSET, 0);
3622                 }
3623         } else {
3624                 /* disable an active IBSS if we are not on the home channel */
3625         }
3626 }
3627
3628 static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
3629                                    u8 basic_rate)
3630 {
3631         u8 phy_rate, index;
3632         u8 basic_phy_rate, basic_index;
3633         u16 dir_table, basic_table;
3634         u16 basic_ptr;
3635
3636         /* Shared memory address for the table we are reading */
3637         dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
3638
3639         /* Shared memory address for the table we are writing */
3640         basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
3641
3642         /*
3643          * for a given rate, the LS-nibble of the PLCP SIGNAL field is
3644          * the index into the rate table.
3645          */
3646         phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
3647         basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
3648         index = phy_rate & 0xf;
3649         basic_index = basic_phy_rate & 0xf;
3650
3651         /* Find the SHM pointer to the ACK rate entry by looking in the
3652          * Direct-map Table
3653          */
3654         basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
3655
3656         /* Update the SHM BSS-basic-rate-set mapping table with the pointer
3657          * to the correct basic rate for the given incoming rate
3658          */
3659         brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
3660 }
3661
3662 static const struct brcms_c_rateset *
3663 brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
3664 {
3665         const struct brcms_c_rateset *rs_dflt;
3666
3667         if (BRCMS_PHY_11N_CAP(wlc->band)) {
3668                 if (wlc->band->bandtype == BRCM_BAND_5G)
3669                         rs_dflt = &ofdm_mimo_rates;
3670                 else
3671                         rs_dflt = &cck_ofdm_mimo_rates;
3672         } else if (wlc->band->gmode)
3673                 rs_dflt = &cck_ofdm_rates;
3674         else
3675                 rs_dflt = &cck_rates;
3676
3677         return rs_dflt;
3678 }
3679
3680 static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
3681 {
3682         const struct brcms_c_rateset *rs_dflt;
3683         struct brcms_c_rateset rs;
3684         u8 rate, basic_rate;
3685         uint i;
3686
3687         rs_dflt = brcms_c_rateset_get_hwrs(wlc);
3688
3689         brcms_c_rateset_copy(rs_dflt, &rs);
3690         brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
3691
3692         /* walk the phy rate table and update SHM basic rate lookup table */
3693         for (i = 0; i < rs.count; i++) {
3694                 rate = rs.rates[i] & BRCMS_RATE_MASK;
3695
3696                 /* for a given rate brcms_basic_rate returns the rate at
3697                  * which a response ACK/CTS should be sent.
3698                  */
3699                 basic_rate = brcms_basic_rate(wlc, rate);
3700                 if (basic_rate == 0)
3701                         /* This should only happen if we are using a
3702                          * restricted rateset.
3703                          */
3704                         basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
3705
3706                 brcms_c_write_rate_shm(wlc, rate, basic_rate);
3707         }
3708 }
3709
3710 /* band-specific init */
3711 static void brcms_c_bsinit(struct brcms_c_info *wlc)
3712 {
3713         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n",
3714                  wlc->pub->unit, wlc->band->bandunit);
3715
3716         /* write ucode ACK/CTS rate table */
3717         brcms_c_set_ratetable(wlc);
3718
3719         /* update some band specific mac configuration */
3720         brcms_c_ucode_mac_upd(wlc);
3721
3722         /* init antenna selection */
3723         brcms_c_antsel_init(wlc->asi);
3724
3725 }
3726
3727 /* formula:  IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
3728 static int
3729 brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
3730                    bool writeToShm)
3731 {
3732         int idle_busy_ratio_x_16 = 0;
3733         uint offset =
3734             isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
3735             M_TX_IDLE_BUSY_RATIO_X_16_CCK;
3736         if (duty_cycle > 100 || duty_cycle < 0) {
3737                 wiphy_err(wlc->wiphy, "wl%d:  duty cycle value off limit\n",
3738                           wlc->pub->unit);
3739                 return -EINVAL;
3740         }
3741         if (duty_cycle)
3742                 idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
3743         /* Only write to shared memory  when wl is up */
3744         if (writeToShm)
3745                 brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
3746
3747         if (isOFDM)
3748                 wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
3749         else
3750                 wlc->tx_duty_cycle_cck = (u16) duty_cycle;
3751
3752         return 0;
3753 }
3754
3755 /*
3756  * Initialize the base precedence map for dequeueing
3757  * from txq based on WME settings
3758  */
3759 static void brcms_c_tx_prec_map_init(struct brcms_c_info *wlc)
3760 {
3761         wlc->tx_prec_map = BRCMS_PREC_BMP_ALL;
3762         memset(wlc->fifo2prec_map, 0, NFIFO * sizeof(u16));
3763
3764         wlc->fifo2prec_map[TX_AC_BK_FIFO] = BRCMS_PREC_BMP_AC_BK;
3765         wlc->fifo2prec_map[TX_AC_BE_FIFO] = BRCMS_PREC_BMP_AC_BE;
3766         wlc->fifo2prec_map[TX_AC_VI_FIFO] = BRCMS_PREC_BMP_AC_VI;
3767         wlc->fifo2prec_map[TX_AC_VO_FIFO] = BRCMS_PREC_BMP_AC_VO;
3768 }
3769
3770 static void
3771 brcms_c_txflowcontrol_signal(struct brcms_c_info *wlc,
3772                              struct brcms_txq_info *qi, bool on, int prio)
3773 {
3774         /* transmit flowcontrol is not yet implemented */
3775 }
3776
3777 static void brcms_c_txflowcontrol_reset(struct brcms_c_info *wlc)
3778 {
3779         struct brcms_txq_info *qi;
3780
3781         for (qi = wlc->tx_queues; qi != NULL; qi = qi->next) {
3782                 if (qi->stopped) {
3783                         brcms_c_txflowcontrol_signal(wlc, qi, OFF, ALLPRIO);
3784                         qi->stopped = 0;
3785                 }
3786         }
3787 }
3788
3789 /* push sw hps and wake state through hardware */
3790 static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
3791 {
3792         u32 v1, v2;
3793         bool hps;
3794         bool awake_before;
3795
3796         hps = brcms_c_ps_allowed(wlc);
3797
3798         BCMMSG(wlc->wiphy, "wl%d: hps %d\n", wlc->pub->unit, hps);
3799
3800         v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
3801         v2 = MCTL_WAKE;
3802         if (hps)
3803                 v2 |= MCTL_HPS;
3804
3805         brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
3806
3807         awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
3808
3809         if (!awake_before)
3810                 brcms_b_wait_for_wake(wlc->hw);
3811 }
3812
3813 /*
3814  * Write this BSS config's MAC address to core.
3815  * Updates RXE match engine.
3816  */
3817 static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
3818 {
3819         int err = 0;
3820         struct brcms_c_info *wlc = bsscfg->wlc;
3821
3822         /* enter the MAC addr into the RXE match registers */
3823         brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, bsscfg->cur_etheraddr);
3824
3825         brcms_c_ampdu_macaddr_upd(wlc);
3826
3827         return err;
3828 }
3829
3830 /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
3831  * Updates RXE match engine.
3832  */
3833 static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
3834 {
3835         /* we need to update BSSID in RXE match registers */
3836         brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
3837 }
3838
3839 static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
3840 {
3841         wlc_hw->shortslot = shortslot;
3842
3843         if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
3844                 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
3845                 brcms_b_update_slot_timing(wlc_hw, shortslot);
3846                 brcms_c_enable_mac(wlc_hw->wlc);
3847         }
3848 }
3849
3850 /*
3851  * Suspend the the MAC and update the slot timing
3852  * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
3853  */
3854 static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
3855 {
3856         /* use the override if it is set */
3857         if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
3858                 shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
3859
3860         if (wlc->shortslot == shortslot)
3861                 return;
3862
3863         wlc->shortslot = shortslot;
3864
3865         brcms_b_set_shortslot(wlc->hw, shortslot);
3866 }
3867
3868 static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3869 {
3870         if (wlc->home_chanspec != chanspec) {
3871                 wlc->home_chanspec = chanspec;
3872
3873                 if (wlc->bsscfg->associated)
3874                         wlc->bsscfg->current_bss->chanspec = chanspec;
3875         }
3876 }
3877
3878 void
3879 brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
3880                       bool mute_tx, struct txpwr_limits *txpwr)
3881 {
3882         uint bandunit;
3883
3884         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
3885
3886         wlc_hw->chanspec = chanspec;
3887
3888         /* Switch bands if necessary */
3889         if (wlc_hw->_nbands > 1) {
3890                 bandunit = chspec_bandunit(chanspec);
3891                 if (wlc_hw->band->bandunit != bandunit) {
3892                         /* brcms_b_setband disables other bandunit,
3893                          *  use light band switch if not up yet
3894                          */
3895                         if (wlc_hw->up) {
3896                                 wlc_phy_chanspec_radio_set(wlc_hw->
3897                                                            bandstate[bandunit]->
3898                                                            pi, chanspec);
3899                                 brcms_b_setband(wlc_hw, bandunit, chanspec);
3900                         } else {
3901                                 brcms_c_setxband(wlc_hw, bandunit);
3902                         }
3903                 }
3904         }
3905
3906         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
3907
3908         if (!wlc_hw->up) {
3909                 if (wlc_hw->clk)
3910                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
3911                                                   chanspec);
3912                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3913         } else {
3914                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
3915                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
3916
3917                 /* Update muting of the channel */
3918                 brcms_b_mute(wlc_hw, mute_tx);
3919         }
3920 }
3921
3922 /* switch to and initialize new band */
3923 static void brcms_c_setband(struct brcms_c_info *wlc,
3924                                            uint bandunit)
3925 {
3926         wlc->band = wlc->bandstate[bandunit];
3927
3928         if (!wlc->pub->up)
3929                 return;
3930
3931         /* wait for at least one beacon before entering sleeping state */
3932         brcms_c_set_ps_ctrl(wlc);
3933
3934         /* band-specific initializations */
3935         brcms_c_bsinit(wlc);
3936 }
3937
3938 static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3939 {
3940         uint bandunit;
3941         bool switchband = false;
3942         u16 old_chanspec = wlc->chanspec;
3943
3944         if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
3945                 wiphy_err(wlc->wiphy, "wl%d: %s: Bad channel %d\n",
3946                           wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
3947                 return;
3948         }
3949
3950         /* Switch bands if necessary */
3951         if (wlc->pub->_nbands > 1) {
3952                 bandunit = chspec_bandunit(chanspec);
3953                 if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
3954                         switchband = true;
3955                         if (wlc->bandlocked) {
3956                                 wiphy_err(wlc->wiphy, "wl%d: %s: chspec %d "
3957                                           "band is locked!\n",
3958                                           wlc->pub->unit, __func__,
3959                                           CHSPEC_CHANNEL(chanspec));
3960                                 return;
3961                         }
3962                         /*
3963                          * should the setband call come after the
3964                          * brcms_b_chanspec() ? if the setband updates
3965                          * (brcms_c_bsinit) use low level calls to inspect and
3966                          * set state, the state inspected may be from the wrong
3967                          * band, or the following brcms_b_set_chanspec() may
3968                          * undo the work.
3969                          */
3970                         brcms_c_setband(wlc, bandunit);
3971                 }
3972         }
3973
3974         /* sync up phy/radio chanspec */
3975         brcms_c_set_phy_chanspec(wlc, chanspec);
3976
3977         /* init antenna selection */
3978         if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
3979                 brcms_c_antsel_init(wlc->asi);
3980
3981                 /* Fix the hardware rateset based on bw.
3982                  * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
3983                  */
3984                 brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
3985                         wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
3986         }
3987
3988         /* update some mac configuration since chanspec changed */
3989         brcms_c_ucode_mac_upd(wlc);
3990 }
3991
3992 /*
3993  * This function changes the phytxctl for beacon based on current
3994  * beacon ratespec AND txant setting as per this table:
3995  *  ratespec     CCK            ant = wlc->stf->txant
3996  *              OFDM            ant = 3
3997  */
3998 void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
3999                                        u32 bcn_rspec)
4000 {
4001         u16 phyctl;
4002         u16 phytxant = wlc->stf->phytxant;
4003         u16 mask = PHY_TXC_ANT_MASK;
4004
4005         /* for non-siso rates or default setting, use the available chains */
4006         if (BRCMS_PHY_11N_CAP(wlc->band))
4007                 phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
4008
4009         phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
4010         phyctl = (phyctl & ~mask) | phytxant;
4011         brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
4012 }
4013
4014 /*
4015  * centralized protection config change function to simplify debugging, no
4016  * consistency checking this should be called only on changes to avoid overhead
4017  * in periodic function
4018  */
4019 void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
4020 {
4021         BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
4022
4023         switch (idx) {
4024         case BRCMS_PROT_G_SPEC:
4025                 wlc->protection->_g = (bool) val;
4026                 break;
4027         case BRCMS_PROT_G_OVR:
4028                 wlc->protection->g_override = (s8) val;
4029                 break;
4030         case BRCMS_PROT_G_USER:
4031                 wlc->protection->gmode_user = (u8) val;
4032                 break;
4033         case BRCMS_PROT_OVERLAP:
4034                 wlc->protection->overlap = (s8) val;
4035                 break;
4036         case BRCMS_PROT_N_USER:
4037                 wlc->protection->nmode_user = (s8) val;
4038                 break;
4039         case BRCMS_PROT_N_CFG:
4040                 wlc->protection->n_cfg = (s8) val;
4041                 break;
4042         case BRCMS_PROT_N_CFG_OVR:
4043                 wlc->protection->n_cfg_override = (s8) val;
4044                 break;
4045         case BRCMS_PROT_N_NONGF:
4046                 wlc->protection->nongf = (bool) val;
4047                 break;
4048         case BRCMS_PROT_N_NONGF_OVR:
4049                 wlc->protection->nongf_override = (s8) val;
4050                 break;
4051         case BRCMS_PROT_N_PAM_OVR:
4052                 wlc->protection->n_pam_override = (s8) val;
4053                 break;
4054         case BRCMS_PROT_N_OBSS:
4055                 wlc->protection->n_obss = (bool) val;
4056                 break;
4057
4058         default:
4059                 break;
4060         }
4061
4062 }
4063
4064 static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
4065 {
4066         if (wlc->pub->up) {
4067                 brcms_c_update_beacon(wlc);
4068                 brcms_c_update_probe_resp(wlc, true);
4069         }
4070 }
4071
4072 static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
4073 {
4074         wlc->stf->ldpc = val;
4075
4076         if (wlc->pub->up) {
4077                 brcms_c_update_beacon(wlc);
4078                 brcms_c_update_probe_resp(wlc, true);
4079                 wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
4080         }
4081 }
4082
4083 void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
4084                        const struct ieee80211_tx_queue_params *params,
4085                        bool suspend)
4086 {
4087         int i;
4088         struct shm_acparams acp_shm;
4089         u16 *shm_entry;
4090
4091         /* Only apply params if the core is out of reset and has clocks */
4092         if (!wlc->clk) {
4093                 wiphy_err(wlc->wiphy, "wl%d: %s : no-clock\n", wlc->pub->unit,
4094                           __func__);
4095                 return;
4096         }
4097
4098         memset((char *)&acp_shm, 0, sizeof(struct shm_acparams));
4099         /* fill in shm ac params struct */
4100         acp_shm.txop = params->txop;
4101         /* convert from units of 32us to us for ucode */
4102         wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
4103             EDCF_TXOP2USEC(acp_shm.txop);
4104         acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
4105
4106         if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
4107             && acp_shm.aifs < EDCF_AIFSN_MAX)
4108                 acp_shm.aifs++;
4109
4110         if (acp_shm.aifs < EDCF_AIFSN_MIN
4111             || acp_shm.aifs > EDCF_AIFSN_MAX) {
4112                 wiphy_err(wlc->wiphy, "wl%d: edcf_setparams: bad "
4113                           "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
4114         } else {
4115                 acp_shm.cwmin = params->cw_min;
4116                 acp_shm.cwmax = params->cw_max;
4117                 acp_shm.cwcur = acp_shm.cwmin;
4118                 acp_shm.bslots =
4119                         bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) &
4120                         acp_shm.cwcur;
4121                 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
4122                 /* Indicate the new params to the ucode */
4123                 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
4124                                                   wme_ac2fifo[aci] *
4125                                                   M_EDCF_QLEN +
4126                                                   M_EDCF_STATUS_OFF));
4127                 acp_shm.status |= WME_STATUS_NEWAC;
4128
4129                 /* Fill in shm acparam table */
4130                 shm_entry = (u16 *) &acp_shm;
4131                 for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
4132                         brcms_b_write_shm(wlc->hw,
4133                                           M_EDCF_QINFO +
4134                                           wme_ac2fifo[aci] * M_EDCF_QLEN + i,
4135                                           *shm_entry++);
4136         }
4137
4138         if (suspend) {
4139                 brcms_c_suspend_mac_and_wait(wlc);
4140                 brcms_c_enable_mac(wlc);
4141         }
4142 }
4143
4144 static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
4145 {
4146         u16 aci;
4147         int i_ac;
4148         struct ieee80211_tx_queue_params txq_pars;
4149         static const struct edcf_acparam default_edcf_acparams[] = {
4150                  {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
4151                  {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
4152                  {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
4153                  {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
4154         }; /* ucode needs these parameters during its initialization */
4155         const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
4156
4157         for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) {
4158                 /* find out which ac this set of params applies to */
4159                 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
4160
4161                 /* fill in shm ac params struct */
4162                 txq_pars.txop = edcf_acp->TXOP;
4163                 txq_pars.aifs = edcf_acp->ACI;
4164
4165                 /* CWmin = 2^(ECWmin) - 1 */
4166                 txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
4167                 /* CWmax = 2^(ECWmax) - 1 */
4168                 txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
4169                                             >> EDCF_ECWMAX_SHIFT);
4170                 brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
4171         }
4172
4173         if (suspend) {
4174                 brcms_c_suspend_mac_and_wait(wlc);
4175                 brcms_c_enable_mac(wlc);
4176         }
4177 }
4178
4179 static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
4180 {
4181         /* Don't start the timer if HWRADIO feature is disabled */
4182         if (wlc->radio_monitor)
4183                 return;
4184
4185         wlc->radio_monitor = true;
4186         brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
4187         brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
4188 }
4189
4190 static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
4191 {
4192         if (!wlc->radio_monitor)
4193                 return true;
4194
4195         wlc->radio_monitor = false;
4196         brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
4197         return brcms_del_timer(wlc->radio_timer);
4198 }
4199
4200 /* read hwdisable state and propagate to wlc flag */
4201 static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
4202 {
4203         if (wlc->pub->hw_off)
4204                 return;
4205
4206         if (brcms_b_radio_read_hwdisabled(wlc->hw))
4207                 mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4208         else
4209                 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4210 }
4211
4212 /* update hwradio status and return it */
4213 bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
4214 {
4215         brcms_c_radio_hwdisable_upd(wlc);
4216
4217         return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
4218                         true : false;
4219 }
4220
4221 /* periodical query hw radio button while driver is "down" */
4222 static void brcms_c_radio_timer(void *arg)
4223 {
4224         struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4225
4226         if (brcms_deviceremoved(wlc)) {
4227                 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
4228                         __func__);
4229                 brcms_down(wlc->wl);
4230                 return;
4231         }
4232
4233         brcms_c_radio_hwdisable_upd(wlc);
4234 }
4235
4236 /* common low-level watchdog code */
4237 static void brcms_b_watchdog(struct brcms_c_info *wlc)
4238 {
4239         struct brcms_hardware *wlc_hw = wlc->hw;
4240
4241         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
4242
4243         if (!wlc_hw->up)
4244                 return;
4245
4246         /* increment second count */
4247         wlc_hw->now++;
4248
4249         /* Check for FIFO error interrupts */
4250         brcms_b_fifoerrors(wlc_hw);
4251
4252         /* make sure RX dma has buffers */
4253         dma_rxfill(wlc->hw->di[RX_FIFO]);
4254
4255         wlc_phy_watchdog(wlc_hw->band->pi);
4256 }
4257
4258 /* common watchdog code */
4259 static void brcms_c_watchdog(struct brcms_c_info *wlc)
4260 {
4261         BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
4262
4263         if (!wlc->pub->up)
4264                 return;
4265
4266         if (brcms_deviceremoved(wlc)) {
4267                 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
4268                           __func__);
4269                 brcms_down(wlc->wl);
4270                 return;
4271         }
4272
4273         /* increment second count */
4274         wlc->pub->now++;
4275
4276         brcms_c_radio_hwdisable_upd(wlc);
4277         /* if radio is disable, driver may be down, quit here */
4278         if (wlc->pub->radio_disabled)
4279                 return;
4280
4281         brcms_b_watchdog(wlc);
4282
4283         /*
4284          * occasionally sample mac stat counters to
4285          * detect 16-bit counter wrap
4286          */
4287         if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
4288                 brcms_c_statsupd(wlc);
4289
4290         if (BRCMS_ISNPHY(wlc->band) &&
4291             ((wlc->pub->now - wlc->tempsense_lasttime) >=
4292              BRCMS_TEMPSENSE_PERIOD)) {
4293                 wlc->tempsense_lasttime = wlc->pub->now;
4294                 brcms_c_tempsense_upd(wlc);
4295         }
4296 }
4297
4298 static void brcms_c_watchdog_by_timer(void *arg)
4299 {
4300         struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4301
4302         brcms_c_watchdog(wlc);
4303 }
4304
4305 static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
4306 {
4307         wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
4308                 wlc, "watchdog");
4309         if (!wlc->wdtimer) {
4310                 wiphy_err(wlc->wiphy, "wl%d:  wl_init_timer for wdtimer "
4311                           "failed\n", unit);
4312                 goto fail;
4313         }
4314
4315         wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
4316                 wlc, "radio");
4317         if (!wlc->radio_timer) {
4318                 wiphy_err(wlc->wiphy, "wl%d:  wl_init_timer for radio_timer "
4319                           "failed\n", unit);
4320                 goto fail;
4321         }
4322
4323         return true;
4324
4325  fail:
4326         return false;
4327 }
4328
4329 /*
4330  * Initialize brcms_c_info default values ...
4331  * may get overrides later in this function
4332  */
4333 static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
4334 {
4335         int i;
4336
4337         /* Save our copy of the chanspec */
4338         wlc->chanspec = ch20mhz_chspec(1);
4339
4340         /* various 802.11g modes */
4341         wlc->shortslot = false;
4342         wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
4343
4344         brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
4345         brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
4346
4347         brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
4348                                BRCMS_PROTECTION_AUTO);
4349         brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
4350         brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
4351                                BRCMS_PROTECTION_AUTO);
4352         brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
4353         brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
4354
4355         brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
4356                                BRCMS_PROTECTION_CTL_OVERLAP);
4357
4358         /* 802.11g draft 4.0 NonERP elt advertisement */
4359         wlc->include_legacy_erp = true;
4360
4361         wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
4362         wlc->stf->txant = ANT_TX_DEF;
4363
4364         wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
4365
4366         wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
4367         for (i = 0; i < NFIFO; i++)
4368                 wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
4369         wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
4370
4371         /* default rate fallback retry limits */
4372         wlc->SFBL = RETRY_SHORT_FB;
4373         wlc->LFBL = RETRY_LONG_FB;
4374
4375         /* default mac retry limits */
4376         wlc->SRL = RETRY_SHORT_DEF;
4377         wlc->LRL = RETRY_LONG_DEF;
4378
4379         /* WME QoS mode is Auto by default */
4380         wlc->pub->_ampdu = AMPDU_AGG_HOST;
4381         wlc->pub->bcmerror = 0;
4382 }
4383
4384 static uint brcms_c_attach_module(struct brcms_c_info *wlc)
4385 {
4386         uint err = 0;
4387         uint unit;
4388         unit = wlc->pub->unit;
4389
4390         wlc->asi = brcms_c_antsel_attach(wlc);
4391         if (wlc->asi == NULL) {
4392                 wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
4393                           "failed\n", unit);
4394                 err = 44;
4395                 goto fail;
4396         }
4397
4398         wlc->ampdu = brcms_c_ampdu_attach(wlc);
4399         if (wlc->ampdu == NULL) {
4400                 wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
4401                           "failed\n", unit);
4402                 err = 50;
4403                 goto fail;
4404         }
4405
4406         if ((brcms_c_stf_attach(wlc) != 0)) {
4407                 wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
4408                           "failed\n", unit);
4409                 err = 68;
4410                 goto fail;
4411         }
4412  fail:
4413         return err;
4414 }
4415
4416 struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
4417 {
4418         return wlc->pub;
4419 }
4420
4421 /* low level attach
4422  *    run backplane attach, init nvram
4423  *    run phy attach
4424  *    initialize software state for each core and band
4425  *    put the whole chip in reset(driver down state), no clock
4426  */
4427 static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4428                           uint unit, bool piomode)
4429 {
4430         struct brcms_hardware *wlc_hw;
4431         uint err = 0;
4432         uint j;
4433         bool wme = false;
4434         struct shared_phy_params sha_params;
4435         struct wiphy *wiphy = wlc->wiphy;
4436         struct pci_dev *pcidev = core->bus->host_pci;
4437         struct ssb_sprom *sprom = &core->bus->sprom;
4438
4439         if (core->bus->hosttype == BCMA_HOSTTYPE_PCI)
4440                 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit,
4441                        pcidev->vendor,
4442                        pcidev->device);
4443         else
4444                 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit,
4445                        core->bus->boardinfo.vendor,
4446                        core->bus->boardinfo.type);
4447
4448         wme = true;
4449
4450         wlc_hw = wlc->hw;
4451         wlc_hw->wlc = wlc;
4452         wlc_hw->unit = unit;
4453         wlc_hw->band = wlc_hw->bandstate[0];
4454         wlc_hw->_piomode = piomode;
4455
4456         /* populate struct brcms_hardware with default values  */
4457         brcms_b_info_init(wlc_hw);
4458
4459         /*
4460          * Do the hardware portion of the attach. Also initialize software
4461          * state that depends on the particular hardware we are running.
4462          */
4463         wlc_hw->sih = ai_attach(core->bus);
4464         if (wlc_hw->sih == NULL) {
4465                 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
4466                           unit);
4467                 err = 11;
4468                 goto fail;
4469         }
4470
4471         /* verify again the device is supported */
4472         if (!brcms_c_chipmatch(core)) {
4473                 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported device\n",
4474                          unit);
4475                 err = 12;
4476                 goto fail;
4477         }
4478
4479         if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
4480                 wlc_hw->vendorid = pcidev->vendor;
4481                 wlc_hw->deviceid = pcidev->device;
4482         } else {
4483                 wlc_hw->vendorid = core->bus->boardinfo.vendor;
4484                 wlc_hw->deviceid = core->bus->boardinfo.type;
4485         }
4486
4487         wlc_hw->d11core = core;
4488         wlc_hw->corerev = core->id.rev;
4489
4490         /* validate chip, chiprev and corerev */
4491         if (!brcms_c_isgoodchip(wlc_hw)) {
4492                 err = 13;
4493                 goto fail;
4494         }
4495
4496         /* initialize power control registers */
4497         ai_clkctl_init(wlc_hw->sih);
4498
4499         /* request fastclock and force fastclock for the rest of attach
4500          * bring the d11 core out of reset.
4501          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
4502          *   is still false; But it will be called again inside wlc_corereset,
4503          *   after d11 is out of reset.
4504          */
4505         brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4506         brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4507
4508         if (!brcms_b_validate_chip_access(wlc_hw)) {
4509                 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
4510                         "failed\n", unit);
4511                 err = 14;
4512                 goto fail;
4513         }
4514
4515         /* get the board rev, used just below */
4516         j = sprom->board_rev;
4517         /* promote srom boardrev of 0xFF to 1 */
4518         if (j == BOARDREV_PROMOTABLE)
4519                 j = BOARDREV_PROMOTED;
4520         wlc_hw->boardrev = (u16) j;
4521         if (!brcms_c_validboardtype(wlc_hw)) {
4522                 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
4523                           "board type (0x%x)" " or revision level (0x%x)\n",
4524                           unit, ai_get_boardtype(wlc_hw->sih),
4525                           wlc_hw->boardrev);
4526                 err = 15;
4527                 goto fail;
4528         }
4529         wlc_hw->sromrev = sprom->revision;
4530         wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
4531         wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
4532
4533         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
4534                 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
4535
4536         /* check device id(srom, nvram etc.) to set bands */
4537         if (wlc_hw->deviceid == BCM43224_D11N_ID ||
4538             wlc_hw->deviceid == BCM43224_D11N_ID_VEN1)
4539                 /* Dualband boards */
4540                 wlc_hw->_nbands = 2;
4541         else
4542                 wlc_hw->_nbands = 1;
4543
4544         if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225))
4545                 wlc_hw->_nbands = 1;
4546
4547         /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
4548          * unconditionally does the init of these values
4549          */
4550         wlc->vendorid = wlc_hw->vendorid;
4551         wlc->deviceid = wlc_hw->deviceid;
4552         wlc->pub->sih = wlc_hw->sih;
4553         wlc->pub->corerev = wlc_hw->corerev;
4554         wlc->pub->sromrev = wlc_hw->sromrev;
4555         wlc->pub->boardrev = wlc_hw->boardrev;
4556         wlc->pub->boardflags = wlc_hw->boardflags;
4557         wlc->pub->boardflags2 = wlc_hw->boardflags2;
4558         wlc->pub->_nbands = wlc_hw->_nbands;
4559
4560         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
4561
4562         if (wlc_hw->physhim == NULL) {
4563                 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
4564                         "failed\n", unit);
4565                 err = 25;
4566                 goto fail;
4567         }
4568
4569         /* pass all the parameters to wlc_phy_shared_attach in one struct */
4570         sha_params.sih = wlc_hw->sih;
4571         sha_params.physhim = wlc_hw->physhim;
4572         sha_params.unit = unit;
4573         sha_params.corerev = wlc_hw->corerev;
4574         sha_params.vid = wlc_hw->vendorid;
4575         sha_params.did = wlc_hw->deviceid;
4576         sha_params.chip = ai_get_chip_id(wlc_hw->sih);
4577         sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
4578         sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
4579         sha_params.sromrev = wlc_hw->sromrev;
4580         sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
4581         sha_params.boardrev = wlc_hw->boardrev;
4582         sha_params.boardflags = wlc_hw->boardflags;
4583         sha_params.boardflags2 = wlc_hw->boardflags2;
4584
4585         /* alloc and save pointer to shared phy state area */
4586         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
4587         if (!wlc_hw->phy_sh) {
4588                 err = 16;
4589                 goto fail;
4590         }
4591
4592         /* initialize software state for each core and band */
4593         for (j = 0; j < wlc_hw->_nbands; j++) {
4594                 /*
4595                  * band0 is always 2.4Ghz
4596                  * band1, if present, is 5Ghz
4597                  */
4598
4599                 brcms_c_setxband(wlc_hw, j);
4600
4601                 wlc_hw->band->bandunit = j;
4602                 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4603                 wlc->band->bandunit = j;
4604                 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4605                 wlc->core->coreidx = core->core_index;
4606
4607                 wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
4608                 wlc_hw->machwcap_backup = wlc_hw->machwcap;
4609
4610                 /* init tx fifo size */
4611                 WARN_ON((wlc_hw->corerev - XMTFIFOTBL_STARTREV) < 0 ||
4612                         (wlc_hw->corerev - XMTFIFOTBL_STARTREV) >
4613                                 ARRAY_SIZE(xmtfifo_sz));
4614                 wlc_hw->xmtfifo_sz =
4615                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
4616                 WARN_ON(!wlc_hw->xmtfifo_sz[0]);
4617
4618                 /* Get a phy for this band */
4619                 wlc_hw->band->pi =
4620                         wlc_phy_attach(wlc_hw->phy_sh, core,
4621                                        wlc_hw->band->bandtype,
4622                                        wlc->wiphy);
4623                 if (wlc_hw->band->pi == NULL) {
4624                         wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
4625                                   "attach failed\n", unit);
4626                         err = 17;
4627                         goto fail;
4628                 }
4629
4630                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
4631
4632                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
4633                                        &wlc_hw->band->phyrev,
4634                                        &wlc_hw->band->radioid,
4635                                        &wlc_hw->band->radiorev);
4636                 wlc_hw->band->abgphy_encore =
4637                     wlc_phy_get_encore(wlc_hw->band->pi);
4638                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
4639                 wlc_hw->band->core_flags =
4640                     wlc_phy_get_coreflags(wlc_hw->band->pi);
4641
4642                 /* verify good phy_type & supported phy revision */
4643                 if (BRCMS_ISNPHY(wlc_hw->band)) {
4644                         if (NCONF_HAS(wlc_hw->band->phyrev))
4645                                 goto good_phy;
4646                         else
4647                                 goto bad_phy;
4648                 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
4649                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
4650                                 goto good_phy;
4651                         else
4652                                 goto bad_phy;
4653                 } else {
4654  bad_phy:
4655                         wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
4656                                   "phy type/rev (%d/%d)\n", unit,
4657                                   wlc_hw->band->phytype, wlc_hw->band->phyrev);
4658                         err = 18;
4659                         goto fail;
4660                 }
4661
4662  good_phy:
4663                 /*
4664                  * BMAC_NOTE: wlc->band->pi should not be set below and should
4665                  * be done in the high level attach. However we can not make
4666                  * that change until all low level access is changed to
4667                  * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
4668                  * keeping wlc_hw->band->pi as well for incremental update of
4669                  * low level fns, and cut over low only init when all fns
4670                  * updated.
4671                  */
4672                 wlc->band->pi = wlc_hw->band->pi;
4673                 wlc->band->phytype = wlc_hw->band->phytype;
4674                 wlc->band->phyrev = wlc_hw->band->phyrev;
4675                 wlc->band->radioid = wlc_hw->band->radioid;
4676                 wlc->band->radiorev = wlc_hw->band->radiorev;
4677
4678                 /* default contention windows size limits */
4679                 wlc_hw->band->CWmin = APHY_CWMIN;
4680                 wlc_hw->band->CWmax = PHY_CWMAX;
4681
4682                 if (!brcms_b_attach_dmapio(wlc, j, wme)) {
4683                         err = 19;
4684                         goto fail;
4685                 }
4686         }
4687
4688         /* disable core to match driver "down" state */
4689         brcms_c_coredisable(wlc_hw);
4690
4691         /* Match driver "down" state */
4692         ai_pci_down(wlc_hw->sih);
4693
4694         /* turn off pll and xtal to match driver "down" state */
4695         brcms_b_xtal(wlc_hw, OFF);
4696
4697         /* *******************************************************************
4698          * The hardware is in the DOWN state at this point. D11 core
4699          * or cores are in reset with clocks off, and the board PLLs
4700          * are off if possible.
4701          *
4702          * Beyond this point, wlc->sbclk == false and chip registers
4703          * should not be touched.
4704          *********************************************************************
4705          */
4706
4707         /* init etheraddr state variables */
4708         brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
4709
4710         if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
4711             is_zero_ether_addr(wlc_hw->etheraddr)) {
4712                 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
4713                           unit);
4714                 err = 22;
4715                 goto fail;
4716         }
4717
4718         BCMMSG(wlc->wiphy, "deviceid 0x%x nbands %d board 0x%x\n",
4719                wlc_hw->deviceid, wlc_hw->_nbands, ai_get_boardtype(wlc_hw->sih));
4720
4721         return err;
4722
4723  fail:
4724         wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
4725                   err);
4726         return err;
4727 }
4728
4729 static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc)
4730 {
4731         uint unit;
4732         unit = wlc->pub->unit;
4733
4734         if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
4735                 /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
4736                 wlc->band->antgain = 8;
4737         } else if (wlc->band->antgain == -1) {
4738                 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4739                           " srom, using 2dB\n", unit, __func__);
4740                 wlc->band->antgain = 8;
4741         } else {
4742                 s8 gain, fract;
4743                 /* Older sroms specified gain in whole dbm only.  In order
4744                  * be able to specify qdbm granularity and remain backward
4745                  * compatible the whole dbms are now encoded in only
4746                  * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
4747                  * 6 bit signed number ranges from -32 - 31.
4748                  *
4749                  * Examples:
4750                  * 0x1 = 1 db,
4751                  * 0xc1 = 1.75 db (1 + 3 quarters),
4752                  * 0x3f = -1 (-1 + 0 quarters),
4753                  * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
4754                  * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
4755                  */
4756                 gain = wlc->band->antgain & 0x3f;
4757                 gain <<= 2;     /* Sign extend */
4758                 gain >>= 2;
4759                 fract = (wlc->band->antgain & 0xc0) >> 6;
4760                 wlc->band->antgain = 4 * gain + fract;
4761         }
4762 }
4763
4764 static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
4765 {
4766         int aa;
4767         uint unit;
4768         int bandtype;
4769         struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
4770
4771         unit = wlc->pub->unit;
4772         bandtype = wlc->band->bandtype;
4773
4774         /* get antennas available */
4775         if (bandtype == BRCM_BAND_5G)
4776                 aa = sprom->ant_available_a;
4777         else
4778                 aa = sprom->ant_available_bg;
4779
4780         if ((aa < 1) || (aa > 15)) {
4781                 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4782                           " srom (0x%x), using 3\n", unit, __func__, aa);
4783                 aa = 3;
4784         }
4785
4786         /* reset the defaults if we have a single antenna */
4787         if (aa == 1) {
4788                 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
4789                 wlc->stf->txant = ANT_TX_FORCE_0;
4790         } else if (aa == 2) {
4791                 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
4792                 wlc->stf->txant = ANT_TX_FORCE_1;
4793         } else {
4794         }
4795
4796         /* Compute Antenna Gain */
4797         if (bandtype == BRCM_BAND_5G)
4798                 wlc->band->antgain = sprom->antenna_gain.a1;
4799         else
4800                 wlc->band->antgain = sprom->antenna_gain.a0;
4801
4802         brcms_c_attach_antgain_init(wlc);
4803
4804         return true;
4805 }
4806
4807 static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
4808 {
4809         u16 chanspec;
4810         struct brcms_band *band;
4811         struct brcms_bss_info *bi = wlc->default_bss;
4812
4813         /* init default and target BSS with some sane initial values */
4814         memset((char *)(bi), 0, sizeof(struct brcms_bss_info));
4815         bi->beacon_period = BEACON_INTERVAL_DEFAULT;
4816
4817         /* fill the default channel as the first valid channel
4818          * starting from the 2G channels
4819          */
4820         chanspec = ch20mhz_chspec(1);
4821         wlc->home_chanspec = bi->chanspec = chanspec;
4822
4823         /* find the band of our default channel */
4824         band = wlc->band;
4825         if (wlc->pub->_nbands > 1 &&
4826             band->bandunit != chspec_bandunit(chanspec))
4827                 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
4828
4829         /* init bss rates to the band specific default rate set */
4830         brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
4831                 band->bandtype, false, BRCMS_RATE_MASK_FULL,
4832                 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
4833                 brcms_chspec_bw(chanspec), wlc->stf->txstreams);
4834
4835         if (wlc->pub->_n_enab & SUPPORT_11N)
4836                 bi->flags |= BRCMS_BSS_HT;
4837 }
4838
4839 static struct brcms_txq_info *brcms_c_txq_alloc(struct brcms_c_info *wlc)
4840 {
4841         struct brcms_txq_info *qi, *p;
4842
4843         qi = kzalloc(sizeof(struct brcms_txq_info), GFP_ATOMIC);
4844         if (qi != NULL) {
4845                 /*
4846                  * Have enough room for control packets along with HI watermark
4847                  * Also, add room to txq for total psq packets if all the SCBs
4848                  * leave PS mode. The watermark for flowcontrol to OS packets
4849                  * will remain the same
4850                  */
4851                 brcmu_pktq_init(&qi->q, BRCMS_PREC_COUNT,
4852                           2 * BRCMS_DATAHIWAT + PKTQ_LEN_DEFAULT);
4853
4854                 /* add this queue to the the global list */
4855                 p = wlc->tx_queues;
4856                 if (p == NULL) {
4857                         wlc->tx_queues = qi;
4858                 } else {
4859                         while (p->next != NULL)
4860                                 p = p->next;
4861                         p->next = qi;
4862                 }
4863         }
4864         return qi;
4865 }
4866
4867 static void brcms_c_txq_free(struct brcms_c_info *wlc,
4868                              struct brcms_txq_info *qi)
4869 {
4870         struct brcms_txq_info *p;
4871
4872         if (qi == NULL)
4873                 return;
4874
4875         /* remove the queue from the linked list */
4876         p = wlc->tx_queues;
4877         if (p == qi)
4878                 wlc->tx_queues = p->next;
4879         else {
4880                 while (p != NULL && p->next != qi)
4881                         p = p->next;
4882                 if (p != NULL)
4883                         p->next = p->next->next;
4884         }
4885
4886         kfree(qi);
4887 }
4888
4889 static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
4890 {
4891         uint i;
4892         struct brcms_band *band;
4893
4894         for (i = 0; i < wlc->pub->_nbands; i++) {
4895                 band = wlc->bandstate[i];
4896                 if (band->bandtype == BRCM_BAND_5G) {
4897                         if ((bwcap == BRCMS_N_BW_40ALL)
4898                             || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
4899                                 band->mimo_cap_40 = true;
4900                         else
4901                                 band->mimo_cap_40 = false;
4902                 } else {
4903                         if (bwcap == BRCMS_N_BW_40ALL)
4904                                 band->mimo_cap_40 = true;
4905                         else
4906                                 band->mimo_cap_40 = false;
4907                 }
4908         }
4909 }
4910
4911 static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
4912 {
4913         /* free timer state */
4914         if (wlc->wdtimer) {
4915                 brcms_free_timer(wlc->wdtimer);
4916                 wlc->wdtimer = NULL;
4917         }
4918         if (wlc->radio_timer) {
4919                 brcms_free_timer(wlc->radio_timer);
4920                 wlc->radio_timer = NULL;
4921         }
4922 }
4923
4924 static void brcms_c_detach_module(struct brcms_c_info *wlc)
4925 {
4926         if (wlc->asi) {
4927                 brcms_c_antsel_detach(wlc->asi);
4928                 wlc->asi = NULL;
4929         }
4930
4931         if (wlc->ampdu) {
4932                 brcms_c_ampdu_detach(wlc->ampdu);
4933                 wlc->ampdu = NULL;
4934         }
4935
4936         brcms_c_stf_detach(wlc);
4937 }
4938
4939 /*
4940  * low level detach
4941  */
4942 static int brcms_b_detach(struct brcms_c_info *wlc)
4943 {
4944         uint i;
4945         struct brcms_hw_band *band;
4946         struct brcms_hardware *wlc_hw = wlc->hw;
4947         int callbacks;
4948
4949         callbacks = 0;
4950
4951         brcms_b_detach_dmapio(wlc_hw);
4952
4953         band = wlc_hw->band;
4954         for (i = 0; i < wlc_hw->_nbands; i++) {
4955                 if (band->pi) {
4956                         /* Detach this band's phy */
4957                         wlc_phy_detach(band->pi);
4958                         band->pi = NULL;
4959                 }
4960                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
4961         }
4962
4963         /* Free shared phy state */
4964         kfree(wlc_hw->phy_sh);
4965
4966         wlc_phy_shim_detach(wlc_hw->physhim);
4967
4968         if (wlc_hw->sih) {
4969                 ai_detach(wlc_hw->sih);
4970                 wlc_hw->sih = NULL;
4971         }
4972
4973         return callbacks;
4974
4975 }
4976
4977 /*
4978  * Return a count of the number of driver callbacks still pending.
4979  *
4980  * General policy is that brcms_c_detach can only dealloc/free software states.
4981  * It can NOT touch hardware registers since the d11core may be in reset and
4982  * clock may not be available.
4983  * One exception is sb register access, which is possible if crystal is turned
4984  * on after "down" state, driver should avoid software timer with the exception
4985  * of radio_monitor.
4986  */
4987 uint brcms_c_detach(struct brcms_c_info *wlc)
4988 {
4989         uint callbacks = 0;
4990
4991         if (wlc == NULL)
4992                 return 0;
4993
4994         BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
4995
4996         callbacks += brcms_b_detach(wlc);
4997
4998         /* delete software timers */
4999         if (!brcms_c_radio_monitor_stop(wlc))
5000                 callbacks++;
5001
5002         brcms_c_channel_mgr_detach(wlc->cmi);
5003
5004         brcms_c_timers_deinit(wlc);
5005
5006         brcms_c_detach_module(wlc);
5007
5008
5009         while (wlc->tx_queues != NULL)
5010                 brcms_c_txq_free(wlc, wlc->tx_queues);
5011
5012         brcms_c_detach_mfree(wlc);
5013         return callbacks;
5014 }
5015
5016 /* update state that depends on the current value of "ap" */
5017 static void brcms_c_ap_upd(struct brcms_c_info *wlc)
5018 {
5019         /* STA-BSS; short capable */
5020         wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
5021 }
5022
5023 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
5024 static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
5025 {
5026         if (wlc_hw->wlc->pub->hw_up)
5027                 return;
5028
5029         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5030
5031         /*
5032          * Enable pll and xtal, initialize the power control registers,
5033          * and force fastclock for the remainder of brcms_c_up().
5034          */
5035         brcms_b_xtal(wlc_hw, ON);
5036         ai_clkctl_init(wlc_hw->sih);
5037         brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5038
5039         /*
5040          * TODO: test suspend/resume
5041          *
5042          * AI chip doesn't restore bar0win2 on
5043          * hibernation/resume, need sw fixup
5044          */
5045
5046         /*
5047          * Inform phy that a POR reset has occurred so
5048          * it does a complete phy init
5049          */
5050         wlc_phy_por_inform(wlc_hw->band->pi);
5051
5052         wlc_hw->ucode_loaded = false;
5053         wlc_hw->wlc->pub->hw_up = true;
5054
5055         if ((wlc_hw->boardflags & BFL_FEM)
5056             && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
5057                 if (!
5058                     (wlc_hw->boardrev >= 0x1250
5059                      && (wlc_hw->boardflags & BFL_FEM_BT)))
5060                         ai_epa_4313war(wlc_hw->sih);
5061         }
5062 }
5063
5064 static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
5065 {
5066         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5067
5068         /*
5069          * Enable pll and xtal, initialize the power control registers,
5070          * and force fastclock for the remainder of brcms_c_up().
5071          */
5072         brcms_b_xtal(wlc_hw, ON);
5073         ai_clkctl_init(wlc_hw->sih);
5074         brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5075
5076         /*
5077          * Configure pci/pcmcia here instead of in brcms_c_attach()
5078          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
5079          */
5080         bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
5081                               true);
5082
5083         /*
5084          * Need to read the hwradio status here to cover the case where the
5085          * system is loaded with the hw radio disabled. We do not want to
5086          * bring the driver up in this case.
5087          */
5088         if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
5089                 /* put SB PCI in down state again */
5090                 ai_pci_down(wlc_hw->sih);
5091                 brcms_b_xtal(wlc_hw, OFF);
5092                 return -ENOMEDIUM;
5093         }
5094
5095         ai_pci_up(wlc_hw->sih);
5096
5097         /* reset the d11 core */
5098         brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
5099
5100         return 0;
5101 }
5102
5103 static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
5104 {
5105         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5106
5107         wlc_hw->up = true;
5108         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
5109
5110         /* FULLY enable dynamic power control and d11 core interrupt */
5111         brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
5112         brcms_intrson(wlc_hw->wlc->wl);
5113         return 0;
5114 }
5115
5116 /*
5117  * Write WME tunable parameters for retransmit/max rate
5118  * from wlc struct to ucode
5119  */
5120 static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
5121 {
5122         int ac;
5123
5124         /* Need clock to do this */
5125         if (!wlc->clk)
5126                 return;
5127
5128         for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
5129                 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
5130                                   wlc->wme_retries[ac]);
5131 }
5132
5133 /* make interface operational */
5134 int brcms_c_up(struct brcms_c_info *wlc)
5135 {
5136         struct ieee80211_channel *ch;
5137
5138         BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
5139
5140         /* HW is turned off so don't try to access it */
5141         if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
5142                 return -ENOMEDIUM;
5143
5144         if (!wlc->pub->hw_up) {
5145                 brcms_b_hw_up(wlc->hw);
5146                 wlc->pub->hw_up = true;
5147         }
5148
5149         if ((wlc->pub->boardflags & BFL_FEM)
5150             && (ai_get_chip_id(wlc->hw->sih) == BCMA_CHIP_ID_BCM4313)) {
5151                 if (wlc->pub->boardrev >= 0x1250
5152                     && (wlc->pub->boardflags & BFL_FEM_BT))
5153                         brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
5154                                 MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
5155                 else
5156                         brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
5157                                     MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
5158         }
5159
5160         /*
5161          * Need to read the hwradio status here to cover the case where the
5162          * system is loaded with the hw radio disabled. We do not want to bring
5163          * the driver up in this case. If radio is disabled, abort up, lower
5164          * power, start radio timer and return 0(for NDIS) don't call
5165          * radio_update to avoid looping brcms_c_up.
5166          *
5167          * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
5168          */
5169         if (!wlc->pub->radio_disabled) {
5170                 int status = brcms_b_up_prep(wlc->hw);
5171                 if (status == -ENOMEDIUM) {
5172                         if (!mboolisset
5173                             (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
5174                                 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
5175                                 mboolset(wlc->pub->radio_disabled,
5176                                          WL_RADIO_HW_DISABLE);
5177
5178                                 if (bsscfg->enable && bsscfg->BSS)
5179                                         wiphy_err(wlc->wiphy, "wl%d: up"
5180                                                   ": rfdisable -> "
5181                                                   "bsscfg_disable()\n",
5182                                                    wlc->pub->unit);
5183                         }
5184                 }
5185         }
5186
5187         if (wlc->pub->radio_disabled) {
5188                 brcms_c_radio_monitor_start(wlc);
5189                 return 0;
5190         }
5191
5192         /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
5193         wlc->clk = true;
5194
5195         brcms_c_radio_monitor_stop(wlc);
5196
5197         /* Set EDCF hostflags */
5198         brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
5199
5200         brcms_init(wlc->wl);
5201         wlc->pub->up = true;
5202
5203         if (wlc->bandinit_pending) {
5204                 ch = wlc->pub->ieee_hw->conf.channel;
5205                 brcms_c_suspend_mac_and_wait(wlc);
5206                 brcms_c_set_chanspec(wlc, ch20mhz_chspec(ch->hw_value));
5207                 wlc->bandinit_pending = false;
5208                 brcms_c_enable_mac(wlc);
5209         }
5210
5211         brcms_b_up_finish(wlc->hw);
5212
5213         /* Program the TX wme params with the current settings */
5214         brcms_c_wme_retries_write(wlc);
5215
5216         /* start one second watchdog timer */
5217         brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
5218         wlc->WDarmed = true;
5219
5220         /* ensure antenna config is up to date */
5221         brcms_c_stf_phy_txant_upd(wlc);
5222         /* ensure LDPC config is in sync */
5223         brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
5224
5225         return 0;
5226 }
5227
5228 static uint brcms_c_down_del_timer(struct brcms_c_info *wlc)
5229 {
5230         uint callbacks = 0;
5231
5232         return callbacks;
5233 }
5234
5235 static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
5236 {
5237         bool dev_gone;
5238         uint callbacks = 0;
5239
5240         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5241
5242         if (!wlc_hw->up)
5243                 return callbacks;
5244
5245         dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5246
5247         /* disable interrupts */
5248         if (dev_gone)
5249                 wlc_hw->wlc->macintmask = 0;
5250         else {
5251                 /* now disable interrupts */
5252                 brcms_intrsoff(wlc_hw->wlc->wl);
5253
5254                 /* ensure we're running on the pll clock again */
5255                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5256         }
5257         /* down phy at the last of this stage */
5258         callbacks += wlc_phy_down(wlc_hw->band->pi);
5259
5260         return callbacks;
5261 }
5262
5263 static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
5264 {
5265         uint callbacks = 0;
5266         bool dev_gone;
5267
5268         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5269
5270         if (!wlc_hw->up)
5271                 return callbacks;
5272
5273         wlc_hw->up = false;
5274         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
5275
5276         dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5277
5278         if (dev_gone) {
5279                 wlc_hw->sbclk = false;
5280                 wlc_hw->clk = false;
5281                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
5282
5283                 /* reclaim any posted packets */
5284                 brcms_c_flushqueues(wlc_hw->wlc);
5285         } else {
5286
5287                 /* Reset and disable the core */
5288                 if (bcma_core_is_enabled(wlc_hw->d11core)) {
5289                         if (bcma_read32(wlc_hw->d11core,
5290                                         D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
5291                                 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
5292                         callbacks += brcms_reset(wlc_hw->wlc->wl);
5293                         brcms_c_coredisable(wlc_hw);
5294                 }
5295
5296                 /* turn off primary xtal and pll */
5297                 if (!wlc_hw->noreset) {
5298                         ai_pci_down(wlc_hw->sih);
5299                         brcms_b_xtal(wlc_hw, OFF);
5300                 }
5301         }
5302
5303         return callbacks;
5304 }
5305
5306 /*
5307  * Mark the interface nonoperational, stop the software mechanisms,
5308  * disable the hardware, free any transient buffer state.
5309  * Return a count of the number of driver callbacks still pending.
5310  */
5311 uint brcms_c_down(struct brcms_c_info *wlc)
5312 {
5313
5314         uint callbacks = 0;
5315         int i;
5316         bool dev_gone = false;
5317         struct brcms_txq_info *qi;
5318
5319         BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
5320
5321         /* check if we are already in the going down path */
5322         if (wlc->going_down) {
5323                 wiphy_err(wlc->wiphy, "wl%d: %s: Driver going down so return"
5324                           "\n", wlc->pub->unit, __func__);
5325                 return 0;
5326         }
5327         if (!wlc->pub->up)
5328                 return callbacks;
5329
5330         wlc->going_down = true;
5331
5332         callbacks += brcms_b_bmac_down_prep(wlc->hw);
5333
5334         dev_gone = brcms_deviceremoved(wlc);
5335
5336         /* Call any registered down handlers */
5337         for (i = 0; i < BRCMS_MAXMODULES; i++) {
5338                 if (wlc->modulecb[i].down_fn)
5339                         callbacks +=
5340                             wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
5341         }
5342
5343         /* cancel the watchdog timer */
5344         if (wlc->WDarmed) {
5345                 if (!brcms_del_timer(wlc->wdtimer))
5346                         callbacks++;
5347                 wlc->WDarmed = false;
5348         }
5349         /* cancel all other timers */
5350         callbacks += brcms_c_down_del_timer(wlc);
5351
5352         wlc->pub->up = false;
5353
5354         wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
5355
5356         /* clear txq flow control */
5357         brcms_c_txflowcontrol_reset(wlc);
5358
5359         /* flush tx queues */
5360         for (qi = wlc->tx_queues; qi != NULL; qi = qi->next)
5361                 brcmu_pktq_flush(&qi->q, true, NULL, NULL);
5362
5363         callbacks += brcms_b_down_finish(wlc->hw);
5364
5365         /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
5366         wlc->clk = false;
5367
5368         wlc->going_down = false;
5369         return callbacks;
5370 }
5371
5372 /* Set the current gmode configuration */
5373 int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
5374 {
5375         int ret = 0;
5376         uint i;
5377         struct brcms_c_rateset rs;
5378         /* Default to 54g Auto */
5379         /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
5380         s8 shortslot = BRCMS_SHORTSLOT_AUTO;
5381         bool shortslot_restrict = false; /* Restrict association to stations
5382                                           * that support shortslot
5383                                           */
5384         bool ofdm_basic = false;        /* Make 6, 12, and 24 basic rates */
5385         /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
5386         int preamble = BRCMS_PLCP_LONG;
5387         bool preamble_restrict = false; /* Restrict association to stations
5388                                          * that support short preambles
5389                                          */
5390         struct brcms_band *band;
5391
5392         /* if N-support is enabled, allow Gmode set as long as requested
5393          * Gmode is not GMODE_LEGACY_B
5394          */
5395         if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
5396                 return -ENOTSUPP;
5397
5398         /* verify that we are dealing with 2G band and grab the band pointer */
5399         if (wlc->band->bandtype == BRCM_BAND_2G)
5400                 band = wlc->band;
5401         else if ((wlc->pub->_nbands > 1) &&
5402                  (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
5403                 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
5404         else
5405                 return -EINVAL;
5406
5407         /* update configuration value */
5408         if (config)
5409                 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
5410
5411         /* Clear rateset override */
5412         memset(&rs, 0, sizeof(struct brcms_c_rateset));
5413
5414         switch (gmode) {
5415         case GMODE_LEGACY_B:
5416                 shortslot = BRCMS_SHORTSLOT_OFF;
5417                 brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
5418
5419                 break;
5420
5421         case GMODE_LRS:
5422                 break;
5423
5424         case GMODE_AUTO:
5425                 /* Accept defaults */
5426                 break;
5427
5428         case GMODE_ONLY:
5429                 ofdm_basic = true;
5430                 preamble = BRCMS_PLCP_SHORT;
5431                 preamble_restrict = true;
5432                 break;
5433
5434         case GMODE_PERFORMANCE:
5435                 shortslot = BRCMS_SHORTSLOT_ON;
5436                 shortslot_restrict = true;
5437                 ofdm_basic = true;
5438                 preamble = BRCMS_PLCP_SHORT;
5439                 preamble_restrict = true;
5440                 break;
5441
5442         default:
5443                 /* Error */
5444                 wiphy_err(wlc->wiphy, "wl%d: %s: invalid gmode %d\n",
5445                           wlc->pub->unit, __func__, gmode);
5446                 return -ENOTSUPP;
5447         }
5448
5449         band->gmode = gmode;
5450
5451         wlc->shortslot_override = shortslot;
5452
5453         /* Use the default 11g rateset */
5454         if (!rs.count)
5455                 brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
5456
5457         if (ofdm_basic) {
5458                 for (i = 0; i < rs.count; i++) {
5459                         if (rs.rates[i] == BRCM_RATE_6M
5460                             || rs.rates[i] == BRCM_RATE_12M
5461                             || rs.rates[i] == BRCM_RATE_24M)
5462                                 rs.rates[i] |= BRCMS_RATE_FLAG;
5463                 }
5464         }
5465
5466         /* Set default bss rateset */
5467         wlc->default_bss->rateset.count = rs.count;
5468         memcpy(wlc->default_bss->rateset.rates, rs.rates,
5469                sizeof(wlc->default_bss->rateset.rates));
5470
5471         return ret;
5472 }
5473
5474 int brcms_c_set_nmode(struct brcms_c_info *wlc)
5475 {
5476         uint i;
5477         s32 nmode = AUTO;
5478
5479         if (wlc->stf->txstreams == WL_11N_3x3)
5480                 nmode = WL_11N_3x3;
5481         else
5482                 nmode = WL_11N_2x2;
5483
5484         /* force GMODE_AUTO if NMODE is ON */
5485         brcms_c_set_gmode(wlc, GMODE_AUTO, true);
5486         if (nmode == WL_11N_3x3)
5487                 wlc->pub->_n_enab = SUPPORT_HT;
5488         else
5489                 wlc->pub->_n_enab = SUPPORT_11N;
5490         wlc->default_bss->flags |= BRCMS_BSS_HT;
5491         /* add the mcs rates to the default and hw ratesets */
5492         brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
5493                               wlc->stf->txstreams);
5494         for (i = 0; i < wlc->pub->_nbands; i++)
5495                 memcpy(wlc->bandstate[i]->hw_rateset.mcs,
5496                        wlc->default_bss->rateset.mcs, MCSSET_LEN);
5497
5498         return 0;
5499 }
5500
5501 static int
5502 brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
5503                              struct brcms_c_rateset *rs_arg)
5504 {
5505         struct brcms_c_rateset rs, new;
5506         uint bandunit;
5507
5508         memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
5509
5510         /* check for bad count value */
5511         if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
5512                 return -EINVAL;
5513
5514         /* try the current band */
5515         bandunit = wlc->band->bandunit;
5516         memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5517         if (brcms_c_rate_hwrs_filter_sort_validate
5518             (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
5519              wlc->stf->txstreams))
5520                 goto good;
5521
5522         /* try the other band */
5523         if (brcms_is_mband_unlocked(wlc)) {
5524                 bandunit = OTHERBANDUNIT(wlc);
5525                 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5526                 if (brcms_c_rate_hwrs_filter_sort_validate(&new,
5527                                                        &wlc->
5528                                                        bandstate[bandunit]->
5529                                                        hw_rateset, true,
5530                                                        wlc->stf->txstreams))
5531                         goto good;
5532         }
5533
5534         return -EBADE;
5535
5536  good:
5537         /* apply new rateset */
5538         memcpy(&wlc->default_bss->rateset, &new,
5539                sizeof(struct brcms_c_rateset));
5540         memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
5541                sizeof(struct brcms_c_rateset));
5542         return 0;
5543 }
5544
5545 static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
5546 {
5547         u8 r;
5548         bool war = false;
5549
5550         if (wlc->bsscfg->associated)
5551                 r = wlc->bsscfg->current_bss->rateset.rates[0];
5552         else
5553                 r = wlc->default_bss->rateset.rates[0];
5554
5555         wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
5556 }
5557
5558 int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
5559 {
5560         u16 chspec = ch20mhz_chspec(channel);
5561
5562         if (channel < 0 || channel > MAXCHANNEL)
5563                 return -EINVAL;
5564
5565         if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
5566                 return -EINVAL;
5567
5568
5569         if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
5570                 if (wlc->band->bandunit != chspec_bandunit(chspec))
5571                         wlc->bandinit_pending = true;
5572                 else
5573                         wlc->bandinit_pending = false;
5574         }
5575
5576         wlc->default_bss->chanspec = chspec;
5577         /* brcms_c_BSSinit() will sanitize the rateset before
5578          * using it.. */
5579         if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
5580                 brcms_c_set_home_chanspec(wlc, chspec);
5581                 brcms_c_suspend_mac_and_wait(wlc);
5582                 brcms_c_set_chanspec(wlc, chspec);
5583                 brcms_c_enable_mac(wlc);
5584         }
5585         return 0;
5586 }
5587
5588 int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
5589 {
5590         int ac;
5591
5592         if (srl < 1 || srl > RETRY_SHORT_MAX ||
5593             lrl < 1 || lrl > RETRY_SHORT_MAX)
5594                 return -EINVAL;
5595
5596         wlc->SRL = srl;
5597         wlc->LRL = lrl;
5598
5599         brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
5600
5601         for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
5602                 wlc->wme_retries[ac] =  SFIELD(wlc->wme_retries[ac],
5603                                                EDCF_SHORT,  wlc->SRL);
5604                 wlc->wme_retries[ac] =  SFIELD(wlc->wme_retries[ac],
5605                                                EDCF_LONG, wlc->LRL);
5606         }
5607         brcms_c_wme_retries_write(wlc);
5608
5609         return 0;
5610 }
5611
5612 void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
5613                                  struct brcm_rateset *currs)
5614 {
5615         struct brcms_c_rateset *rs;
5616
5617         if (wlc->pub->associated)
5618                 rs = &wlc->bsscfg->current_bss->rateset;
5619         else
5620                 rs = &wlc->default_bss->rateset;
5621
5622         /* Copy only legacy rateset section */
5623         currs->count = rs->count;
5624         memcpy(&currs->rates, &rs->rates, rs->count);
5625 }
5626
5627 int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
5628 {
5629         struct brcms_c_rateset internal_rs;
5630         int bcmerror;
5631
5632         if (rs->count > BRCMS_NUMRATES)
5633                 return -ENOBUFS;
5634
5635         memset(&internal_rs, 0, sizeof(struct brcms_c_rateset));
5636
5637         /* Copy only legacy rateset section */
5638         internal_rs.count = rs->count;
5639         memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
5640
5641         /* merge rateset coming in with the current mcsset */
5642         if (wlc->pub->_n_enab & SUPPORT_11N) {
5643                 struct brcms_bss_info *mcsset_bss;
5644                 if (wlc->bsscfg->associated)
5645                         mcsset_bss = wlc->bsscfg->current_bss;
5646                 else
5647                         mcsset_bss = wlc->default_bss;
5648                 memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
5649                        MCSSET_LEN);
5650         }
5651
5652         bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
5653         if (!bcmerror)
5654                 brcms_c_ofdm_rateset_war(wlc);
5655
5656         return bcmerror;
5657 }
5658
5659 int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
5660 {
5661         if (period < DOT11_MIN_BEACON_PERIOD ||
5662             period > DOT11_MAX_BEACON_PERIOD)
5663                 return -EINVAL;
5664
5665         wlc->default_bss->beacon_period = period;
5666         return 0;
5667 }
5668
5669 u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
5670 {
5671         return wlc->band->phytype;
5672 }
5673
5674 void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
5675 {
5676         wlc->shortslot_override = sslot_override;
5677
5678         /*
5679          * shortslot is an 11g feature, so no more work if we are
5680          * currently on the 5G band
5681          */
5682         if (wlc->band->bandtype == BRCM_BAND_5G)
5683                 return;
5684
5685         if (wlc->pub->up && wlc->pub->associated) {
5686                 /* let watchdog or beacon processing update shortslot */
5687         } else if (wlc->pub->up) {
5688                 /* unassociated shortslot is off */
5689                 brcms_c_switch_shortslot(wlc, false);
5690         } else {
5691                 /* driver is down, so just update the brcms_c_info
5692                  * value */
5693                 if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
5694                         wlc->shortslot = false;
5695                 else
5696                         wlc->shortslot =
5697                             (wlc->shortslot_override ==
5698                              BRCMS_SHORTSLOT_ON);
5699         }
5700 }
5701
5702 /*
5703  * register watchdog and down handlers.
5704  */
5705 int brcms_c_module_register(struct brcms_pub *pub,
5706                             const char *name, struct brcms_info *hdl,
5707                             int (*d_fn)(void *handle))
5708 {
5709         struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5710         int i;
5711
5712         /* find an empty entry and just add, no duplication check! */
5713         for (i = 0; i < BRCMS_MAXMODULES; i++) {
5714                 if (wlc->modulecb[i].name[0] == '\0') {
5715                         strncpy(wlc->modulecb[i].name, name,
5716                                 sizeof(wlc->modulecb[i].name) - 1);
5717                         wlc->modulecb[i].hdl = hdl;
5718                         wlc->modulecb[i].down_fn = d_fn;
5719                         return 0;
5720                 }
5721         }
5722
5723         return -ENOSR;
5724 }
5725
5726 /* unregister module callbacks */
5727 int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
5728                               struct brcms_info *hdl)
5729 {
5730         struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5731         int i;
5732
5733         if (wlc == NULL)
5734                 return -ENODATA;
5735
5736         for (i = 0; i < BRCMS_MAXMODULES; i++) {
5737                 if (!strcmp(wlc->modulecb[i].name, name) &&
5738                     (wlc->modulecb[i].hdl == hdl)) {
5739                         memset(&wlc->modulecb[i], 0, sizeof(struct modulecb));
5740                         return 0;
5741                 }
5742         }
5743
5744         /* table not found! */
5745         return -ENODATA;
5746 }
5747
5748 void brcms_c_print_txstatus(struct tx_status *txs)
5749 {
5750         pr_debug("\ntxpkt (MPDU) Complete\n");
5751
5752         pr_debug("FrameID: %04x   TxStatus: %04x\n", txs->frameid, txs->status);
5753
5754         pr_debug("[15:12]  %d  frame attempts\n",
5755                   (txs->status & TX_STATUS_FRM_RTX_MASK) >>
5756                  TX_STATUS_FRM_RTX_SHIFT);
5757         pr_debug(" [11:8]  %d  rts attempts\n",
5758                  (txs->status & TX_STATUS_RTS_RTX_MASK) >>
5759                  TX_STATUS_RTS_RTX_SHIFT);
5760         pr_debug("    [7]  %d  PM mode indicated\n",
5761                  txs->status & TX_STATUS_PMINDCTD ? 1 : 0);
5762         pr_debug("    [6]  %d  intermediate status\n",
5763                  txs->status & TX_STATUS_INTERMEDIATE ? 1 : 0);
5764         pr_debug("    [5]  %d  AMPDU\n",
5765                  txs->status & TX_STATUS_AMPDU ? 1 : 0);
5766         pr_debug("  [4:2]  %d  Frame Suppressed Reason (%s)\n",
5767                  (txs->status & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT,
5768                  (const char *[]) {
5769                         "None",
5770                         "PMQ Entry",
5771                         "Flush request",
5772                         "Previous frag failure",
5773                         "Channel mismatch",
5774                         "Lifetime Expiry",
5775                         "Underflow"
5776                  } [(txs->status & TX_STATUS_SUPR_MASK) >>
5777                     TX_STATUS_SUPR_SHIFT]);
5778         pr_debug("    [1]  %d  acked\n",
5779                  txs->status & TX_STATUS_ACK_RCV ? 1 : 0);
5780
5781         pr_debug("LastTxTime: %04x Seq: %04x PHYTxStatus: %04x RxAckRSSI: %04x RxAckSQ: %04x\n",
5782                  txs->lasttxtime, txs->sequence, txs->phyerr,
5783                  (txs->ackphyrxsh & PRXS1_JSSI_MASK) >> PRXS1_JSSI_SHIFT,
5784                  (txs->ackphyrxsh & PRXS1_SQ_MASK) >> PRXS1_SQ_SHIFT);
5785 }
5786
5787 static bool brcms_c_chipmatch_pci(struct bcma_device *core)
5788 {
5789         struct pci_dev *pcidev = core->bus->host_pci;
5790         u16 vendor = pcidev->vendor;
5791         u16 device = pcidev->device;
5792
5793         if (vendor != PCI_VENDOR_ID_BROADCOM) {
5794                 pr_err("unknown vendor id %04x\n", vendor);
5795                 return false;
5796         }
5797
5798         if (device == BCM43224_D11N_ID_VEN1)
5799                 return true;
5800         if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
5801                 return true;
5802         if (device == BCM4313_D11N2G_ID)
5803                 return true;
5804         if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
5805                 return true;
5806
5807         pr_err("unknown device id %04x\n", device);
5808         return false;
5809 }
5810
5811 static bool brcms_c_chipmatch_soc(struct bcma_device *core)
5812 {
5813         struct bcma_chipinfo *chipinfo = &core->bus->chipinfo;
5814
5815         if (chipinfo->id == BCMA_CHIP_ID_BCM4716)
5816                 return true;
5817
5818         pr_err("unknown chip id %04x\n", chipinfo->id);
5819         return false;
5820 }
5821
5822 bool brcms_c_chipmatch(struct bcma_device *core)
5823 {
5824         switch (core->bus->hosttype) {
5825         case BCMA_HOSTTYPE_PCI:
5826                 return brcms_c_chipmatch_pci(core);
5827         case BCMA_HOSTTYPE_SOC:
5828                 return brcms_c_chipmatch_soc(core);
5829         default:
5830                 pr_err("unknown host type: %i\n", core->bus->hosttype);
5831                 return false;
5832         }
5833 }
5834
5835 #if defined(DEBUG)
5836 void brcms_c_print_txdesc(struct d11txh *txh)
5837 {
5838         u16 mtcl = le16_to_cpu(txh->MacTxControlLow);
5839         u16 mtch = le16_to_cpu(txh->MacTxControlHigh);
5840         u16 mfc = le16_to_cpu(txh->MacFrameControl);
5841         u16 tfest = le16_to_cpu(txh->TxFesTimeNormal);
5842         u16 ptcw = le16_to_cpu(txh->PhyTxControlWord);
5843         u16 ptcw_1 = le16_to_cpu(txh->PhyTxControlWord_1);
5844         u16 ptcw_1_Fbr = le16_to_cpu(txh->PhyTxControlWord_1_Fbr);
5845         u16 ptcw_1_Rts = le16_to_cpu(txh->PhyTxControlWord_1_Rts);
5846         u16 ptcw_1_FbrRts = le16_to_cpu(txh->PhyTxControlWord_1_FbrRts);
5847         u16 mainrates = le16_to_cpu(txh->MainRates);
5848         u16 xtraft = le16_to_cpu(txh->XtraFrameTypes);
5849         u8 *iv = txh->IV;
5850         u8 *ra = txh->TxFrameRA;
5851         u16 tfestfb = le16_to_cpu(txh->TxFesTimeFallback);
5852         u8 *rtspfb = txh->RTSPLCPFallback;
5853         u16 rtsdfb = le16_to_cpu(txh->RTSDurFallback);
5854         u8 *fragpfb = txh->FragPLCPFallback;
5855         u16 fragdfb = le16_to_cpu(txh->FragDurFallback);
5856         u16 mmodelen = le16_to_cpu(txh->MModeLen);
5857         u16 mmodefbrlen = le16_to_cpu(txh->MModeFbrLen);
5858         u16 tfid = le16_to_cpu(txh->TxFrameID);
5859         u16 txs = le16_to_cpu(txh->TxStatus);
5860         u16 mnmpdu = le16_to_cpu(txh->MaxNMpdus);
5861         u16 mabyte = le16_to_cpu(txh->MaxABytes_MRT);
5862         u16 mabyte_f = le16_to_cpu(txh->MaxABytes_FBR);
5863         u16 mmbyte = le16_to_cpu(txh->MinMBytes);
5864
5865         u8 *rtsph = txh->RTSPhyHeader;
5866         struct ieee80211_rts rts = txh->rts_frame;
5867
5868         /* add plcp header along with txh descriptor */
5869         brcmu_dbg_hex_dump(txh, sizeof(struct d11txh) + 48,
5870                            "Raw TxDesc + plcp header:\n");
5871
5872         pr_debug("TxCtlLow: %04x ", mtcl);
5873         pr_debug("TxCtlHigh: %04x ", mtch);
5874         pr_debug("FC: %04x ", mfc);
5875         pr_debug("FES Time: %04x\n", tfest);
5876         pr_debug("PhyCtl: %04x%s ", ptcw,
5877                (ptcw & PHY_TXC_SHORT_HDR) ? " short" : "");
5878         pr_debug("PhyCtl_1: %04x ", ptcw_1);
5879         pr_debug("PhyCtl_1_Fbr: %04x\n", ptcw_1_Fbr);
5880         pr_debug("PhyCtl_1_Rts: %04x ", ptcw_1_Rts);
5881         pr_debug("PhyCtl_1_Fbr_Rts: %04x\n", ptcw_1_FbrRts);
5882         pr_debug("MainRates: %04x ", mainrates);
5883         pr_debug("XtraFrameTypes: %04x ", xtraft);
5884         pr_debug("\n");
5885
5886         print_hex_dump_bytes("SecIV:", DUMP_PREFIX_OFFSET, iv, sizeof(txh->IV));
5887         print_hex_dump_bytes("RA:", DUMP_PREFIX_OFFSET,
5888                              ra, sizeof(txh->TxFrameRA));
5889
5890         pr_debug("Fb FES Time: %04x ", tfestfb);
5891         print_hex_dump_bytes("Fb RTS PLCP:", DUMP_PREFIX_OFFSET,
5892                              rtspfb, sizeof(txh->RTSPLCPFallback));
5893         pr_debug("RTS DUR: %04x ", rtsdfb);
5894         print_hex_dump_bytes("PLCP:", DUMP_PREFIX_OFFSET,
5895                              fragpfb, sizeof(txh->FragPLCPFallback));
5896         pr_debug("DUR: %04x", fragdfb);
5897         pr_debug("\n");
5898
5899         pr_debug("MModeLen: %04x ", mmodelen);
5900         pr_debug("MModeFbrLen: %04x\n", mmodefbrlen);
5901
5902         pr_debug("FrameID:     %04x\n", tfid);
5903         pr_debug("TxStatus:    %04x\n", txs);
5904
5905         pr_debug("MaxNumMpdu:  %04x\n", mnmpdu);
5906         pr_debug("MaxAggbyte:  %04x\n", mabyte);
5907         pr_debug("MaxAggbyte_fb:  %04x\n", mabyte_f);
5908         pr_debug("MinByte:     %04x\n", mmbyte);
5909
5910         print_hex_dump_bytes("RTS PLCP:", DUMP_PREFIX_OFFSET,
5911                              rtsph, sizeof(txh->RTSPhyHeader));
5912         print_hex_dump_bytes("RTS Frame:", DUMP_PREFIX_OFFSET,
5913                              (u8 *)&rts, sizeof(txh->rts_frame));
5914         pr_debug("\n");
5915 }
5916 #endif                          /* defined(DEBUG) */
5917
5918 #if defined(DEBUG)
5919 static int
5920 brcms_c_format_flags(const struct brcms_c_bit_desc *bd, u32 flags, char *buf,
5921                      int len)
5922 {
5923         int i;
5924         char *p = buf;
5925         char hexstr[16];
5926         int slen = 0, nlen = 0;
5927         u32 bit;
5928         const char *name;
5929
5930         if (len < 2 || !buf)
5931                 return 0;
5932
5933         buf[0] = '\0';
5934
5935         for (i = 0; flags != 0; i++) {
5936                 bit = bd[i].bit;
5937                 name = bd[i].name;
5938                 if (bit == 0 && flags != 0) {
5939                         /* print any unnamed bits */
5940                         snprintf(hexstr, 16, "0x%X", flags);
5941                         name = hexstr;
5942                         flags = 0;      /* exit loop */
5943                 } else if ((flags & bit) == 0)
5944                         continue;
5945                 flags &= ~bit;
5946                 nlen = strlen(name);
5947                 slen += nlen;
5948                 /* count btwn flag space */
5949                 if (flags != 0)
5950                         slen += 1;
5951                 /* need NULL char as well */
5952                 if (len <= slen)
5953                         break;
5954                 /* copy NULL char but don't count it */
5955                 strncpy(p, name, nlen + 1);
5956                 p += nlen;
5957                 /* copy btwn flag space and NULL char */
5958                 if (flags != 0)
5959                         p += snprintf(p, 2, " ");
5960                 len -= slen;
5961         }
5962
5963         /* indicate the str was too short */
5964         if (flags != 0) {
5965                 if (len < 2)
5966                         p -= 2 - len;   /* overwrite last char */
5967                 p += snprintf(p, 2, ">");
5968         }
5969
5970         return (int)(p - buf);
5971 }
5972 #endif                          /* defined(DEBUG) */
5973
5974 #if defined(DEBUG)
5975 void brcms_c_print_rxh(struct d11rxhdr *rxh)
5976 {
5977         u16 len = rxh->RxFrameSize;
5978         u16 phystatus_0 = rxh->PhyRxStatus_0;
5979         u16 phystatus_1 = rxh->PhyRxStatus_1;
5980         u16 phystatus_2 = rxh->PhyRxStatus_2;
5981         u16 phystatus_3 = rxh->PhyRxStatus_3;
5982         u16 macstatus1 = rxh->RxStatus1;
5983         u16 macstatus2 = rxh->RxStatus2;
5984         char flagstr[64];
5985         char lenbuf[20];
5986         static const struct brcms_c_bit_desc macstat_flags[] = {
5987                 {RXS_FCSERR, "FCSErr"},
5988                 {RXS_RESPFRAMETX, "Reply"},
5989                 {RXS_PBPRES, "PADDING"},
5990                 {RXS_DECATMPT, "DeCr"},
5991                 {RXS_DECERR, "DeCrErr"},
5992                 {RXS_BCNSENT, "Bcn"},
5993                 {0, NULL}
5994         };
5995
5996         brcmu_dbg_hex_dump(rxh, sizeof(struct d11rxhdr), "Raw RxDesc:\n");
5997
5998         brcms_c_format_flags(macstat_flags, macstatus1, flagstr, 64);
5999
6000         snprintf(lenbuf, sizeof(lenbuf), "0x%x", len);
6001
6002         pr_debug("RxFrameSize:     %6s (%d)%s\n", lenbuf, len,
6003                (rxh->PhyRxStatus_0 & PRXS0_SHORTH) ? " short preamble" : "");
6004         pr_debug("RxPHYStatus:     %04x %04x %04x %04x\n",
6005                phystatus_0, phystatus_1, phystatus_2, phystatus_3);
6006         pr_debug("RxMACStatus:     %x %s\n", macstatus1, flagstr);
6007         pr_debug("RXMACaggtype:    %x\n",
6008                (macstatus2 & RXS_AGGTYPE_MASK));
6009         pr_debug("RxTSFTime:       %04x\n", rxh->RxTSFTime);
6010 }
6011 #endif                          /* defined(DEBUG) */
6012
6013 u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
6014 {
6015         u16 table_ptr;
6016         u8 phy_rate, index;
6017
6018         /* get the phy specific rate encoding for the PLCP SIGNAL field */
6019         if (is_ofdm_rate(rate))
6020                 table_ptr = M_RT_DIRMAP_A;
6021         else
6022                 table_ptr = M_RT_DIRMAP_B;
6023
6024         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
6025          * the index into the rate table.
6026          */
6027         phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
6028         index = phy_rate & 0xf;
6029
6030         /* Find the SHM pointer to the rate table entry by looking in the
6031          * Direct-map Table
6032          */
6033         return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
6034 }
6035
6036 static bool
6037 brcms_c_prec_enq_head(struct brcms_c_info *wlc, struct pktq *q,
6038                       struct sk_buff *pkt, int prec, bool head)
6039 {
6040         struct sk_buff *p;
6041         int eprec = -1;         /* precedence to evict from */
6042
6043         /* Determine precedence from which to evict packet, if any */
6044         if (pktq_pfull(q, prec))
6045                 eprec = prec;
6046         else if (pktq_full(q)) {
6047                 p = brcmu_pktq_peek_tail(q, &eprec);
6048                 if (eprec > prec) {
6049                         wiphy_err(wlc->wiphy, "%s: Failing: eprec %d > prec %d"
6050                                   "\n", __func__, eprec, prec);
6051                         return false;
6052                 }
6053         }
6054
6055         /* Evict if needed */
6056         if (eprec >= 0) {
6057                 bool discard_oldest;
6058
6059                 discard_oldest = ac_bitmap_tst(0, eprec);
6060
6061                 /* Refuse newer packet unless configured to discard oldest */
6062                 if (eprec == prec && !discard_oldest) {
6063                         wiphy_err(wlc->wiphy, "%s: No where to go, prec == %d"
6064                                   "\n", __func__, prec);
6065                         return false;
6066                 }
6067
6068                 /* Evict packet according to discard policy */
6069                 p = discard_oldest ? brcmu_pktq_pdeq(q, eprec) :
6070                         brcmu_pktq_pdeq_tail(q, eprec);
6071                 brcmu_pkt_buf_free_skb(p);
6072         }
6073
6074         /* Enqueue */
6075         if (head)
6076                 p = brcmu_pktq_penq_head(q, prec, pkt);
6077         else
6078                 p = brcmu_pktq_penq(q, prec, pkt);
6079
6080         return true;
6081 }
6082
6083 /*
6084  * Attempts to queue a packet onto a multiple-precedence queue,
6085  * if necessary evicting a lower precedence packet from the queue.
6086  *
6087  * 'prec' is the precedence number that has already been mapped
6088  * from the packet priority.
6089  *
6090  * Returns true if packet consumed (queued), false if not.
6091  */
6092 static bool brcms_c_prec_enq(struct brcms_c_info *wlc, struct pktq *q,
6093                       struct sk_buff *pkt, int prec)
6094 {
6095         return brcms_c_prec_enq_head(wlc, q, pkt, prec, false);
6096 }
6097
6098 void brcms_c_txq_enq(struct brcms_c_info *wlc, struct scb *scb,
6099                      struct sk_buff *sdu, uint prec)
6100 {
6101         struct brcms_txq_info *qi = wlc->pkt_queue;     /* Check me */
6102         struct pktq *q = &qi->q;
6103         int prio;
6104
6105         prio = sdu->priority;
6106
6107         if (!brcms_c_prec_enq(wlc, q, sdu, prec)) {
6108                 /*
6109                  * we might hit this condtion in case
6110                  * packet flooding from mac80211 stack
6111                  */
6112                 brcmu_pkt_buf_free_skb(sdu);
6113         }
6114 }
6115
6116 /*
6117  * bcmc_fid_generate:
6118  * Generate frame ID for a BCMC packet.  The frag field is not used
6119  * for MC frames so is used as part of the sequence number.
6120  */
6121 static inline u16
6122 bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
6123                   struct d11txh *txh)
6124 {
6125         u16 frameid;
6126
6127         frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
6128                                                   TXFID_QUEUE_MASK);
6129         frameid |=
6130             (((wlc->
6131                mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
6132             TX_BCMC_FIFO;
6133
6134         return frameid;
6135 }
6136
6137 static uint
6138 brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
6139           &n