Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
[linux-3.10.git] / drivers / net / wireless / b43 / phy_n.c
1 /*
2
3   Broadcom B43 wireless driver
4   IEEE 802.11n PHY support
5
6   Copyright (c) 2008 Michael Buesch <m@bues.ch>
7
8   This program is free software; you can redistribute it and/or modify
9   it under the terms of the GNU General Public License as published by
10   the Free Software Foundation; either version 2 of the License, or
11   (at your option) any later version.
12
13   This program is distributed in the hope that it will be useful,
14   but WITHOUT ANY WARRANTY; without even the implied warranty of
15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16   GNU General Public License for more details.
17
18   You should have received a copy of the GNU General Public License
19   along with this program; see the file COPYING.  If not, write to
20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21   Boston, MA 02110-1301, USA.
22
23 */
24
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/types.h>
28
29 #include "b43.h"
30 #include "phy_n.h"
31 #include "tables_nphy.h"
32 #include "radio_2055.h"
33 #include "radio_2056.h"
34 #include "main.h"
35
36 struct nphy_txgains {
37         u16 txgm[2];
38         u16 pga[2];
39         u16 pad[2];
40         u16 ipa[2];
41 };
42
43 struct nphy_iqcal_params {
44         u16 txgm;
45         u16 pga;
46         u16 pad;
47         u16 ipa;
48         u16 cal_gain;
49         u16 ncorr[5];
50 };
51
52 struct nphy_iq_est {
53         s32 iq0_prod;
54         u32 i0_pwr;
55         u32 q0_pwr;
56         s32 iq1_prod;
57         u32 i1_pwr;
58         u32 q1_pwr;
59 };
60
61 enum b43_nphy_rf_sequence {
62         B43_RFSEQ_RX2TX,
63         B43_RFSEQ_TX2RX,
64         B43_RFSEQ_RESET2RX,
65         B43_RFSEQ_UPDATE_GAINH,
66         B43_RFSEQ_UPDATE_GAINL,
67         B43_RFSEQ_UPDATE_GAINU,
68 };
69
70 enum b43_nphy_rssi_type {
71         B43_NPHY_RSSI_X = 0,
72         B43_NPHY_RSSI_Y,
73         B43_NPHY_RSSI_Z,
74         B43_NPHY_RSSI_PWRDET,
75         B43_NPHY_RSSI_TSSI_I,
76         B43_NPHY_RSSI_TSSI_Q,
77         B43_NPHY_RSSI_TBD,
78 };
79
80 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
81                                                 bool enable);
82 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
83                                         u8 *events, u8 *delays, u8 length);
84 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
85                                        enum b43_nphy_rf_sequence seq);
86 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
87                                                 u16 value, u8 core, bool off);
88 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
89                                                 u16 value, u8 core);
90
91 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
92 {//TODO
93 }
94
95 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
96 {//TODO
97 }
98
99 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
100                                                         bool ignore_tssi)
101 {//TODO
102         return B43_TXPWR_RES_DONE;
103 }
104
105 static void b43_chantab_radio_upload(struct b43_wldev *dev,
106                                 const struct b43_nphy_channeltab_entry_rev2 *e)
107 {
108         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
109         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
110         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
111         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
112         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
113
114         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
115         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
116         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
117         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
118         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
119
120         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
121         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
122         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
123         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
124         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
125
126         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
127         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
128         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
129         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
130         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
131
132         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
133         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
134         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
135         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
136         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
137
138         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
139         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
140 }
141
142 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
143                                 const struct b43_nphy_channeltab_entry_rev3 *e)
144 {
145         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
146         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
147         b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
148         b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
149         b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
150         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
151                                         e->radio_syn_pll_loopfilter1);
152         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
153                                         e->radio_syn_pll_loopfilter2);
154         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
155                                         e->radio_syn_pll_loopfilter3);
156         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
157                                         e->radio_syn_pll_loopfilter4);
158         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
159                                         e->radio_syn_pll_loopfilter5);
160         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
161                                         e->radio_syn_reserved_addr27);
162         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
163                                         e->radio_syn_reserved_addr28);
164         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
165                                         e->radio_syn_reserved_addr29);
166         b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
167                                         e->radio_syn_logen_vcobuf1);
168         b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
169         b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
170         b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
171
172         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
173                                         e->radio_rx0_lnaa_tune);
174         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
175                                         e->radio_rx0_lnag_tune);
176
177         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
178                                         e->radio_tx0_intpaa_boost_tune);
179         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
180                                         e->radio_tx0_intpag_boost_tune);
181         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
182                                         e->radio_tx0_pada_boost_tune);
183         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
184                                         e->radio_tx0_padg_boost_tune);
185         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
186                                         e->radio_tx0_pgaa_boost_tune);
187         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
188                                         e->radio_tx0_pgag_boost_tune);
189         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
190                                         e->radio_tx0_mixa_boost_tune);
191         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
192                                         e->radio_tx0_mixg_boost_tune);
193
194         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
195                                         e->radio_rx1_lnaa_tune);
196         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
197                                         e->radio_rx1_lnag_tune);
198
199         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
200                                         e->radio_tx1_intpaa_boost_tune);
201         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
202                                         e->radio_tx1_intpag_boost_tune);
203         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
204                                         e->radio_tx1_pada_boost_tune);
205         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
206                                         e->radio_tx1_padg_boost_tune);
207         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
208                                         e->radio_tx1_pgaa_boost_tune);
209         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
210                                         e->radio_tx1_pgag_boost_tune);
211         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
212                                         e->radio_tx1_mixa_boost_tune);
213         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
214                                         e->radio_tx1_mixg_boost_tune);
215 }
216
217 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
218 static void b43_radio_2056_setup(struct b43_wldev *dev,
219                                 const struct b43_nphy_channeltab_entry_rev3 *e)
220 {
221         B43_WARN_ON(dev->phy.rev < 3);
222
223         b43_chantab_radio_2056_upload(dev, e);
224         /* TODO */
225         udelay(50);
226         /* VCO calibration */
227         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
228         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
229         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
230         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
231         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
232         udelay(300);
233 }
234
235 static void b43_chantab_phy_upload(struct b43_wldev *dev,
236                                    const struct b43_phy_n_sfo_cfg *e)
237 {
238         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
239         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
240         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
241         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
242         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
243         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
244 }
245
246 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
247 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
248 {
249         struct b43_phy_n *nphy = dev->phy.n;
250         u8 i;
251         u16 tmp;
252
253         if (nphy->hang_avoid)
254                 b43_nphy_stay_in_carrier_search(dev, 1);
255
256         nphy->txpwrctrl = enable;
257         if (!enable) {
258                 if (dev->phy.rev >= 3)
259                         ; /* TODO */
260
261                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
262                 for (i = 0; i < 84; i++)
263                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
264
265                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
266                 for (i = 0; i < 84; i++)
267                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
268
269                 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
270                 if (dev->phy.rev >= 3)
271                         tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
272                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
273
274                 if (dev->phy.rev >= 3) {
275                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
276                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
277                 } else {
278                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
279                 }
280
281                 if (dev->phy.rev == 2)
282                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
283                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
284                 else if (dev->phy.rev < 2)
285                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
286                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
287
288                 if (dev->phy.rev < 2 && 0)
289                         ; /* TODO */
290         } else {
291                 b43err(dev->wl, "enabling tx pwr ctrl not implemented yet\n");
292         }
293
294         if (nphy->hang_avoid)
295                 b43_nphy_stay_in_carrier_search(dev, 0);
296 }
297
298 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
299 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
300 {
301         struct b43_phy_n *nphy = dev->phy.n;
302         struct ssb_sprom *sprom = dev->dev->bus_sprom;
303
304         u8 txpi[2], bbmult, i;
305         u16 tmp, radio_gain, dac_gain;
306         u16 freq = dev->phy.channel_freq;
307         u32 txgain;
308         /* u32 gaintbl; rev3+ */
309
310         if (nphy->hang_avoid)
311                 b43_nphy_stay_in_carrier_search(dev, 1);
312
313         if (dev->phy.rev >= 3) {
314                 txpi[0] = 40;
315                 txpi[1] = 40;
316         } else if (sprom->revision < 4) {
317                 txpi[0] = 72;
318                 txpi[1] = 72;
319         } else {
320                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
321                         txpi[0] = sprom->txpid2g[0];
322                         txpi[1] = sprom->txpid2g[1];
323                 } else if (freq >= 4900 && freq < 5100) {
324                         txpi[0] = sprom->txpid5gl[0];
325                         txpi[1] = sprom->txpid5gl[1];
326                 } else if (freq >= 5100 && freq < 5500) {
327                         txpi[0] = sprom->txpid5g[0];
328                         txpi[1] = sprom->txpid5g[1];
329                 } else if (freq >= 5500) {
330                         txpi[0] = sprom->txpid5gh[0];
331                         txpi[1] = sprom->txpid5gh[1];
332                 } else {
333                         txpi[0] = 91;
334                         txpi[1] = 91;
335                 }
336         }
337
338         /*
339         for (i = 0; i < 2; i++) {
340                 nphy->txpwrindex[i].index_internal = txpi[i];
341                 nphy->txpwrindex[i].index_internal_save = txpi[i];
342         }
343         */
344
345         for (i = 0; i < 2; i++) {
346                 if (dev->phy.rev >= 3) {
347                         /* FIXME: support 5GHz */
348                         txgain = b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
349                         radio_gain = (txgain >> 16) & 0x1FFFF;
350                 } else {
351                         txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
352                         radio_gain = (txgain >> 16) & 0x1FFF;
353                 }
354
355                 dac_gain = (txgain >> 8) & 0x3F;
356                 bbmult = txgain & 0xFF;
357
358                 if (dev->phy.rev >= 3) {
359                         if (i == 0)
360                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
361                         else
362                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
363                 } else {
364                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
365                 }
366
367                 if (i == 0)
368                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
369                 else
370                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
371
372                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D10 + i);
373                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, radio_gain);
374
375                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
376                 tmp = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
377
378                 if (i == 0)
379                         tmp = (tmp & 0x00FF) | (bbmult << 8);
380                 else
381                         tmp = (tmp & 0xFF00) | bbmult;
382
383                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
384                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, tmp);
385
386                 if (0)
387                         ; /* TODO */
388         }
389
390         b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
391
392         if (nphy->hang_avoid)
393                 b43_nphy_stay_in_carrier_search(dev, 0);
394 }
395
396
397 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
398 static void b43_radio_2055_setup(struct b43_wldev *dev,
399                                 const struct b43_nphy_channeltab_entry_rev2 *e)
400 {
401         B43_WARN_ON(dev->phy.rev >= 3);
402
403         b43_chantab_radio_upload(dev, e);
404         udelay(50);
405         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
406         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
407         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
408         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
409         udelay(300);
410 }
411
412 static void b43_radio_init2055_pre(struct b43_wldev *dev)
413 {
414         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
415                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
416         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
417                     B43_NPHY_RFCTL_CMD_CHIP0PU |
418                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
419         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
420                     B43_NPHY_RFCTL_CMD_PORFORCE);
421 }
422
423 static void b43_radio_init2055_post(struct b43_wldev *dev)
424 {
425         struct b43_phy_n *nphy = dev->phy.n;
426         struct ssb_sprom *sprom = dev->dev->bus_sprom;
427         int i;
428         u16 val;
429         bool workaround = false;
430
431         if (sprom->revision < 4)
432                 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
433                               && dev->dev->board_type == 0x46D
434                               && dev->dev->board_rev >= 0x41);
435         else
436                 workaround =
437                         !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
438
439         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
440         if (workaround) {
441                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
442                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
443         }
444         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
445         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
446         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
447         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
448         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
449         msleep(1);
450         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
451         for (i = 0; i < 200; i++) {
452                 val = b43_radio_read(dev, B2055_CAL_COUT2);
453                 if (val & 0x80) {
454                         i = 0;
455                         break;
456                 }
457                 udelay(10);
458         }
459         if (i)
460                 b43err(dev->wl, "radio post init timeout\n");
461         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
462         b43_switch_channel(dev, dev->phy.channel);
463         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
464         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
465         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
466         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
467         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
468         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
469         if (!nphy->gain_boost) {
470                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
471                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
472         } else {
473                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
474                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
475         }
476         udelay(2);
477 }
478
479 /*
480  * Initialize a Broadcom 2055 N-radio
481  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
482  */
483 static void b43_radio_init2055(struct b43_wldev *dev)
484 {
485         b43_radio_init2055_pre(dev);
486         if (b43_status(dev) < B43_STAT_INITIALIZED) {
487                 /* Follow wl, not specs. Do not force uploading all regs */
488                 b2055_upload_inittab(dev, 0, 0);
489         } else {
490                 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
491                 b2055_upload_inittab(dev, ghz5, 0);
492         }
493         b43_radio_init2055_post(dev);
494 }
495
496 static void b43_radio_init2056_pre(struct b43_wldev *dev)
497 {
498         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
499                      ~B43_NPHY_RFCTL_CMD_CHIP0PU);
500         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
501         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
502                      B43_NPHY_RFCTL_CMD_OEPORFORCE);
503         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
504                     ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
505         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
506                     B43_NPHY_RFCTL_CMD_CHIP0PU);
507 }
508
509 static void b43_radio_init2056_post(struct b43_wldev *dev)
510 {
511         b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
512         b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
513         b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
514         msleep(1);
515         b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
516         b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
517         b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
518         /*
519         if (nphy->init_por)
520                 Call Radio 2056 Recalibrate
521         */
522 }
523
524 /*
525  * Initialize a Broadcom 2056 N-radio
526  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
527  */
528 static void b43_radio_init2056(struct b43_wldev *dev)
529 {
530         b43_radio_init2056_pre(dev);
531         b2056_upload_inittabs(dev, 0, 0);
532         b43_radio_init2056_post(dev);
533 }
534
535 /*
536  * Upload the N-PHY tables.
537  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
538  */
539 static void b43_nphy_tables_init(struct b43_wldev *dev)
540 {
541         if (dev->phy.rev < 3)
542                 b43_nphy_rev0_1_2_tables_init(dev);
543         else
544                 b43_nphy_rev3plus_tables_init(dev);
545 }
546
547 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
548 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
549 {
550         struct b43_phy_n *nphy = dev->phy.n;
551         enum ieee80211_band band;
552         u16 tmp;
553
554         if (!enable) {
555                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
556                                                        B43_NPHY_RFCTL_INTC1);
557                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
558                                                        B43_NPHY_RFCTL_INTC2);
559                 band = b43_current_band(dev->wl);
560                 if (dev->phy.rev >= 3) {
561                         if (band == IEEE80211_BAND_5GHZ)
562                                 tmp = 0x600;
563                         else
564                                 tmp = 0x480;
565                 } else {
566                         if (band == IEEE80211_BAND_5GHZ)
567                                 tmp = 0x180;
568                         else
569                                 tmp = 0x120;
570                 }
571                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
572                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
573         } else {
574                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
575                                 nphy->rfctrl_intc1_save);
576                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
577                                 nphy->rfctrl_intc2_save);
578         }
579 }
580
581 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
582 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
583 {
584         struct b43_phy_n *nphy = dev->phy.n;
585         u16 tmp;
586         enum ieee80211_band band = b43_current_band(dev->wl);
587         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
588                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
589
590         if (dev->phy.rev >= 3) {
591                 if (ipa) {
592                         tmp = 4;
593                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
594                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
595                 }
596
597                 tmp = 1;
598                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
599                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
600         }
601 }
602
603 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
604 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
605 {
606         u32 tmp;
607
608         if (dev->phy.type != B43_PHYTYPE_N)
609                 return;
610
611         switch (dev->dev->bus_type) {
612 #ifdef CONFIG_B43_BCMA
613         case B43_BUS_BCMA:
614                 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
615                 if (force)
616                         tmp |= BCMA_IOCTL_FGC;
617                 else
618                         tmp &= ~BCMA_IOCTL_FGC;
619                 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
620                 break;
621 #endif
622 #ifdef CONFIG_B43_SSB
623         case B43_BUS_SSB:
624                 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
625                 if (force)
626                         tmp |= SSB_TMSLOW_FGC;
627                 else
628                         tmp &= ~SSB_TMSLOW_FGC;
629                 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
630                 break;
631 #endif
632         }
633 }
634
635 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
636 static void b43_nphy_reset_cca(struct b43_wldev *dev)
637 {
638         u16 bbcfg;
639
640         b43_nphy_bmac_clock_fgc(dev, 1);
641         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
642         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
643         udelay(1);
644         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
645         b43_nphy_bmac_clock_fgc(dev, 0);
646         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
647 }
648
649 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
650 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
651 {
652         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
653
654         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
655         if (preamble == 1)
656                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
657         else
658                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
659
660         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
661 }
662
663 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
664 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
665 {
666         struct b43_phy_n *nphy = dev->phy.n;
667
668         bool override = false;
669         u16 chain = 0x33;
670
671         if (nphy->txrx_chain == 0) {
672                 chain = 0x11;
673                 override = true;
674         } else if (nphy->txrx_chain == 1) {
675                 chain = 0x22;
676                 override = true;
677         }
678
679         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
680                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
681                         chain);
682
683         if (override)
684                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
685                                 B43_NPHY_RFSEQMODE_CAOVER);
686         else
687                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
688                                 ~B43_NPHY_RFSEQMODE_CAOVER);
689 }
690
691 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
692 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
693                                 u16 samps, u8 time, bool wait)
694 {
695         int i;
696         u16 tmp;
697
698         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
699         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
700         if (wait)
701                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
702         else
703                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
704
705         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
706
707         for (i = 1000; i; i--) {
708                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
709                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
710                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
711                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
712                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
713                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
714                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
715                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
716
717                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
718                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
719                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
720                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
721                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
722                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
723                         return;
724                 }
725                 udelay(10);
726         }
727         memset(est, 0, sizeof(*est));
728 }
729
730 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
731 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
732                                         struct b43_phy_n_iq_comp *pcomp)
733 {
734         if (write) {
735                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
736                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
737                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
738                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
739         } else {
740                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
741                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
742                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
743                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
744         }
745 }
746
747 #if 0
748 /* Ready but not used anywhere */
749 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
750 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
751 {
752         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
753
754         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
755         if (core == 0) {
756                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
757                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
758         } else {
759                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
760                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
761         }
762         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
763         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
764         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
765         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
766         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
767         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
768         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
769         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
770 }
771
772 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
773 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
774 {
775         u8 rxval, txval;
776         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
777
778         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
779         if (core == 0) {
780                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
781                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
782         } else {
783                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
784                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
785         }
786         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
787         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
788         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
789         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
790         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
791         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
792         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
793         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
794
795         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
796         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
797
798         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
799                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
800                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
801         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
802                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
803         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
804                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
805         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
806                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
807
808         if (core == 0) {
809                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
810                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
811         } else {
812                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
813                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
814         }
815
816         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
817         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
818         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
819
820         if (core == 0) {
821                 rxval = 1;
822                 txval = 8;
823         } else {
824                 rxval = 4;
825                 txval = 2;
826         }
827         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
828         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
829 }
830 #endif
831
832 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
833 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
834 {
835         int i;
836         s32 iq;
837         u32 ii;
838         u32 qq;
839         int iq_nbits, qq_nbits;
840         int arsh, brsh;
841         u16 tmp, a, b;
842
843         struct nphy_iq_est est;
844         struct b43_phy_n_iq_comp old;
845         struct b43_phy_n_iq_comp new = { };
846         bool error = false;
847
848         if (mask == 0)
849                 return;
850
851         b43_nphy_rx_iq_coeffs(dev, false, &old);
852         b43_nphy_rx_iq_coeffs(dev, true, &new);
853         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
854         new = old;
855
856         for (i = 0; i < 2; i++) {
857                 if (i == 0 && (mask & 1)) {
858                         iq = est.iq0_prod;
859                         ii = est.i0_pwr;
860                         qq = est.q0_pwr;
861                 } else if (i == 1 && (mask & 2)) {
862                         iq = est.iq1_prod;
863                         ii = est.i1_pwr;
864                         qq = est.q1_pwr;
865                 } else {
866                         continue;
867                 }
868
869                 if (ii + qq < 2) {
870                         error = true;
871                         break;
872                 }
873
874                 iq_nbits = fls(abs(iq));
875                 qq_nbits = fls(qq);
876
877                 arsh = iq_nbits - 20;
878                 if (arsh >= 0) {
879                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
880                         tmp = ii >> arsh;
881                 } else {
882                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
883                         tmp = ii << -arsh;
884                 }
885                 if (tmp == 0) {
886                         error = true;
887                         break;
888                 }
889                 a /= tmp;
890
891                 brsh = qq_nbits - 11;
892                 if (brsh >= 0) {
893                         b = (qq << (31 - qq_nbits));
894                         tmp = ii >> brsh;
895                 } else {
896                         b = (qq << (31 - qq_nbits));
897                         tmp = ii << -brsh;
898                 }
899                 if (tmp == 0) {
900                         error = true;
901                         break;
902                 }
903                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
904
905                 if (i == 0 && (mask & 0x1)) {
906                         if (dev->phy.rev >= 3) {
907                                 new.a0 = a & 0x3FF;
908                                 new.b0 = b & 0x3FF;
909                         } else {
910                                 new.a0 = b & 0x3FF;
911                                 new.b0 = a & 0x3FF;
912                         }
913                 } else if (i == 1 && (mask & 0x2)) {
914                         if (dev->phy.rev >= 3) {
915                                 new.a1 = a & 0x3FF;
916                                 new.b1 = b & 0x3FF;
917                         } else {
918                                 new.a1 = b & 0x3FF;
919                                 new.b1 = a & 0x3FF;
920                         }
921                 }
922         }
923
924         if (error)
925                 new = old;
926
927         b43_nphy_rx_iq_coeffs(dev, true, &new);
928 }
929
930 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
931 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
932 {
933         u16 array[4];
934         int i;
935
936         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
937         for (i = 0; i < 4; i++)
938                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
939
940         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
941         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
942         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
943         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
944 }
945
946 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
947 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
948                                           const u16 *clip_st)
949 {
950         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
951         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
952 }
953
954 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
955 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
956 {
957         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
958         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
959 }
960
961 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
962 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
963 {
964         if (dev->phy.rev >= 3) {
965                 if (!init)
966                         return;
967                 if (0 /* FIXME */) {
968                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
969                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
970                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
971                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
972                 }
973         } else {
974                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
975                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
976
977                 switch (dev->dev->bus_type) {
978 #ifdef CONFIG_B43_BCMA
979                 case B43_BUS_BCMA:
980                         bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
981                                                  0xFC00, 0xFC00);
982                         break;
983 #endif
984 #ifdef CONFIG_B43_SSB
985                 case B43_BUS_SSB:
986                         ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
987                                                 0xFC00, 0xFC00);
988                         break;
989 #endif
990                 }
991
992                 b43_write32(dev, B43_MMIO_MACCTL,
993                         b43_read32(dev, B43_MMIO_MACCTL) &
994                         ~B43_MACCTL_GPOUTSMSK);
995                 b43_write16(dev, B43_MMIO_GPIO_MASK,
996                         b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
997                 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
998                         b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
999
1000                 if (init) {
1001                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1002                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1003                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1004                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1005                 }
1006         }
1007 }
1008
1009 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
1010 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
1011 {
1012         u16 tmp;
1013
1014         if (dev->dev->core_rev == 16)
1015                 b43_mac_suspend(dev);
1016
1017         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
1018         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
1019                 B43_NPHY_CLASSCTL_WAITEDEN);
1020         tmp &= ~mask;
1021         tmp |= (val & mask);
1022         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
1023
1024         if (dev->dev->core_rev == 16)
1025                 b43_mac_enable(dev);
1026
1027         return tmp;
1028 }
1029
1030 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
1031 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
1032 {
1033         struct b43_phy *phy = &dev->phy;
1034         struct b43_phy_n *nphy = phy->n;
1035
1036         if (enable) {
1037                 static const u16 clip[] = { 0xFFFF, 0xFFFF };
1038                 if (nphy->deaf_count++ == 0) {
1039                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
1040                         b43_nphy_classifier(dev, 0x7, 0);
1041                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
1042                         b43_nphy_write_clip_detection(dev, clip);
1043                 }
1044                 b43_nphy_reset_cca(dev);
1045         } else {
1046                 if (--nphy->deaf_count == 0) {
1047                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
1048                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
1049                 }
1050         }
1051 }
1052
1053 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
1054 static void b43_nphy_stop_playback(struct b43_wldev *dev)
1055 {
1056         struct b43_phy_n *nphy = dev->phy.n;
1057         u16 tmp;
1058
1059         if (nphy->hang_avoid)
1060                 b43_nphy_stay_in_carrier_search(dev, 1);
1061
1062         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
1063         if (tmp & 0x1)
1064                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
1065         else if (tmp & 0x2)
1066                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1067
1068         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
1069
1070         if (nphy->bb_mult_save & 0x80000000) {
1071                 tmp = nphy->bb_mult_save & 0xFFFF;
1072                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1073                 nphy->bb_mult_save = 0;
1074         }
1075
1076         if (nphy->hang_avoid)
1077                 b43_nphy_stay_in_carrier_search(dev, 0);
1078 }
1079
1080 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
1081 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
1082 {
1083         struct b43_phy_n *nphy = dev->phy.n;
1084
1085         u8 channel = dev->phy.channel;
1086         int tone[2] = { 57, 58 };
1087         u32 noise[2] = { 0x3FF, 0x3FF };
1088
1089         B43_WARN_ON(dev->phy.rev < 3);
1090
1091         if (nphy->hang_avoid)
1092                 b43_nphy_stay_in_carrier_search(dev, 1);
1093
1094         if (nphy->gband_spurwar_en) {
1095                 /* TODO: N PHY Adjust Analog Pfbw (7) */
1096                 if (channel == 11 && dev->phy.is_40mhz)
1097                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
1098                 else
1099                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1100                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
1101         }
1102
1103         if (nphy->aband_spurwar_en) {
1104                 if (channel == 54) {
1105                         tone[0] = 0x20;
1106                         noise[0] = 0x25F;
1107                 } else if (channel == 38 || channel == 102 || channel == 118) {
1108                         if (0 /* FIXME */) {
1109                                 tone[0] = 0x20;
1110                                 noise[0] = 0x21F;
1111                         } else {
1112                                 tone[0] = 0;
1113                                 noise[0] = 0;
1114                         }
1115                 } else if (channel == 134) {
1116                         tone[0] = 0x20;
1117                         noise[0] = 0x21F;
1118                 } else if (channel == 151) {
1119                         tone[0] = 0x10;
1120                         noise[0] = 0x23F;
1121                 } else if (channel == 153 || channel == 161) {
1122                         tone[0] = 0x30;
1123                         noise[0] = 0x23F;
1124                 } else {
1125                         tone[0] = 0;
1126                         noise[0] = 0;
1127                 }
1128
1129                 if (!tone[0] && !noise[0])
1130                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
1131                 else
1132                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1133         }
1134
1135         if (nphy->hang_avoid)
1136                 b43_nphy_stay_in_carrier_search(dev, 0);
1137 }
1138
1139 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
1140 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
1141 {
1142         struct b43_phy_n *nphy = dev->phy.n;
1143
1144         u8 i;
1145         s16 tmp;
1146         u16 data[4];
1147         s16 gain[2];
1148         u16 minmax[2];
1149         static const u16 lna_gain[4] = { -2, 10, 19, 25 };
1150
1151         if (nphy->hang_avoid)
1152                 b43_nphy_stay_in_carrier_search(dev, 1);
1153
1154         if (nphy->gain_boost) {
1155                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1156                         gain[0] = 6;
1157                         gain[1] = 6;
1158                 } else {
1159                         tmp = 40370 - 315 * dev->phy.channel;
1160                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
1161                         tmp = 23242 - 224 * dev->phy.channel;
1162                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
1163                 }
1164         } else {
1165                 gain[0] = 0;
1166                 gain[1] = 0;
1167         }
1168
1169         for (i = 0; i < 2; i++) {
1170                 if (nphy->elna_gain_config) {
1171                         data[0] = 19 + gain[i];
1172                         data[1] = 25 + gain[i];
1173                         data[2] = 25 + gain[i];
1174                         data[3] = 25 + gain[i];
1175                 } else {
1176                         data[0] = lna_gain[0] + gain[i];
1177                         data[1] = lna_gain[1] + gain[i];
1178                         data[2] = lna_gain[2] + gain[i];
1179                         data[3] = lna_gain[3] + gain[i];
1180                 }
1181                 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
1182
1183                 minmax[i] = 23 + gain[i];
1184         }
1185
1186         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
1187                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
1188         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
1189                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
1190
1191         if (nphy->hang_avoid)
1192                 b43_nphy_stay_in_carrier_search(dev, 0);
1193 }
1194
1195 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
1196 static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
1197 {
1198         struct b43_phy_n *nphy = dev->phy.n;
1199         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1200
1201         /* PHY rev 0, 1, 2 */
1202         u8 i, j;
1203         u8 code;
1204         u16 tmp;
1205         u8 rfseq_events[3] = { 6, 8, 7 };
1206         u8 rfseq_delays[3] = { 10, 30, 1 };
1207
1208         /* PHY rev >= 3 */
1209         bool ghz5;
1210         bool ext_lna;
1211         u16 rssi_gain;
1212         struct nphy_gain_ctl_workaround_entry *e;
1213         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1214         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1215
1216         if (dev->phy.rev >= 3) {
1217                 /* Prepare values */
1218                 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1219                         & B43_NPHY_BANDCTL_5GHZ;
1220                 ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
1221                 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1222                 if (ghz5 && dev->phy.rev >= 5)
1223                         rssi_gain = 0x90;
1224                 else
1225                         rssi_gain = 0x50;
1226
1227                 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1228
1229                 /* Set Clip 2 detect */
1230                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1231                                 B43_NPHY_C1_CGAINI_CL2DETECT);
1232                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1233                                 B43_NPHY_C2_CGAINI_CL2DETECT);
1234
1235                 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1236                                 0x17);
1237                 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1238                                 0x17);
1239                 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1240                 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1241                 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1242                 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1243                 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1244                                 rssi_gain);
1245                 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1246                                 rssi_gain);
1247                 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1248                                 0x17);
1249                 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1250                                 0x17);
1251                 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1252                 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1253
1254                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1255                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1256                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1257                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1258                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1259                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1260                 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1261                 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1262                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1263                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1264                 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1265                 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1266
1267                 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1268                 b43_phy_write(dev, 0x2A7, e->init_gain);
1269                 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1270                                         e->rfseq_init);
1271                 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1272
1273                 /* TODO: check defines. Do not match variables names */
1274                 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1275                 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1276                 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1277                 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1278                 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1279                 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1280
1281                 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1282                 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1283                 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1284                 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1285                 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1286                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1287                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1288                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1289                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1290                 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1291         } else {
1292                 /* Set Clip 2 detect */
1293                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1294                                 B43_NPHY_C1_CGAINI_CL2DETECT);
1295                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1296                                 B43_NPHY_C2_CGAINI_CL2DETECT);
1297
1298                 /* Set narrowband clip threshold */
1299                 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1300                 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
1301
1302                 if (!dev->phy.is_40mhz) {
1303                         /* Set dwell lengths */
1304                         b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1305                         b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1306                         b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1307                         b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
1308                 }
1309
1310                 /* Set wideband clip 2 threshold */
1311                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1312                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
1313                                 21);
1314                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1315                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
1316                                 21);
1317
1318                 if (!dev->phy.is_40mhz) {
1319                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1320                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1321                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1322                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1323                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1324                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1325                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1326                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1327                 }
1328
1329                 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1330
1331                 if (nphy->gain_boost) {
1332                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1333                             dev->phy.is_40mhz)
1334                                 code = 4;
1335                         else
1336                                 code = 5;
1337                 } else {
1338                         code = dev->phy.is_40mhz ? 6 : 7;
1339                 }
1340
1341                 /* Set HPVGA2 index */
1342                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
1343                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
1344                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1345                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
1346                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
1347                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1348
1349                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1350                 /* specs say about 2 loops, but wl does 4 */
1351                 for (i = 0; i < 4; i++)
1352                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1353                                                         (code << 8 | 0x7C));
1354
1355                 b43_nphy_adjust_lna_gain_table(dev);
1356
1357                 if (nphy->elna_gain_config) {
1358                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1359                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1360                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1361                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1362                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1363
1364                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1365                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1366                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1367                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1368                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1369
1370                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1371                         /* specs say about 2 loops, but wl does 4 */
1372                         for (i = 0; i < 4; i++)
1373                                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1374                                                         (code << 8 | 0x74));
1375                 }
1376
1377                 if (dev->phy.rev == 2) {
1378                         for (i = 0; i < 4; i++) {
1379                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1380                                                 (0x0400 * i) + 0x0020);
1381                                 for (j = 0; j < 21; j++) {
1382                                         tmp = j * (i < 2 ? 3 : 1);
1383                                         b43_phy_write(dev,
1384                                                 B43_NPHY_TABLE_DATALO, tmp);
1385                                 }
1386                         }
1387                 }
1388
1389                 b43_nphy_set_rf_sequence(dev, 5,
1390                                 rfseq_events, rfseq_delays, 3);
1391                 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1392                         ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1393                         0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1394
1395                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1396                         b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1397                                         0xFF80, 4);
1398         }
1399 }
1400
1401 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1402 static void b43_nphy_workarounds(struct b43_wldev *dev)
1403 {
1404         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1405         struct b43_phy *phy = &dev->phy;
1406         struct b43_phy_n *nphy = phy->n;
1407
1408         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1409         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1410
1411         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1412         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1413
1414         u16 tmp16;
1415         u32 tmp32;
1416
1417         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1418                 b43_nphy_classifier(dev, 1, 0);
1419         else
1420                 b43_nphy_classifier(dev, 1, 1);
1421
1422         if (nphy->hang_avoid)
1423                 b43_nphy_stay_in_carrier_search(dev, 1);
1424
1425         b43_phy_set(dev, B43_NPHY_IQFLIP,
1426                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1427
1428         if (dev->phy.rev >= 3) {
1429                 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1430                 tmp32 &= 0xffffff;
1431                 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
1432
1433                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
1434                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
1435                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
1436                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
1437                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
1438                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
1439
1440                 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
1441                 b43_phy_write(dev, 0x2AE, 0x000C);
1442
1443                 /* TODO */
1444
1445                 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
1446                         0x2 : 0x9C40;
1447                 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
1448
1449                 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
1450
1451                 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
1452                 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
1453
1454                 b43_nphy_gain_ctrl_workarounds(dev);
1455
1456                 b43_ntab_write(dev, B43_NTAB32(8, 0), 2);
1457                 b43_ntab_write(dev, B43_NTAB32(8, 16), 2);
1458
1459                 /* TODO */
1460
1461                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1462                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1463                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1464                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1465                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1466                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1467                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1468                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1469                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1470                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1471
1472                 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
1473
1474                 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1475                     b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
1476                     (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1477                     b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1478                         tmp32 = 0x00088888;
1479                 else
1480                         tmp32 = 0x88888888;
1481                 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
1482                 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
1483                 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1484
1485                 if (dev->phy.rev == 4 &&
1486                     b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1487                         b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
1488                                         0x70);
1489                         b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
1490                                         0x70);
1491                 }
1492
1493                 b43_phy_write(dev, 0x224, 0x039C);
1494                 b43_phy_write(dev, 0x225, 0x0357);
1495                 b43_phy_write(dev, 0x226, 0x0317);
1496                 b43_phy_write(dev, 0x227, 0x02D7);
1497                 b43_phy_write(dev, 0x228, 0x039C);
1498                 b43_phy_write(dev, 0x229, 0x0357);
1499                 b43_phy_write(dev, 0x22A, 0x0317);
1500                 b43_phy_write(dev, 0x22B, 0x02D7);
1501                 b43_phy_write(dev, 0x22C, 0x039C);
1502                 b43_phy_write(dev, 0x22D, 0x0357);
1503                 b43_phy_write(dev, 0x22E, 0x0317);
1504                 b43_phy_write(dev, 0x22F, 0x02D7);
1505         } else {
1506                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1507                     nphy->band5g_pwrgain) {
1508                         b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1509                         b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1510                 } else {
1511                         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1512                         b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1513                 }
1514
1515                 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
1516                 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
1517                 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
1518                 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
1519
1520                 if (dev->phy.rev < 2) {
1521                         b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
1522                         b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
1523                         b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
1524                         b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
1525                         b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
1526                         b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
1527                 }
1528
1529                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1530                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1531                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1532                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1533
1534                 if (sprom->boardflags2_lo & 0x100 &&
1535                     dev->dev->board_type == 0x8B) {
1536                         delays1[0] = 0x1;
1537                         delays1[5] = 0x14;
1538                 }
1539                 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1540                 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1541
1542                 b43_nphy_gain_ctrl_workarounds(dev);
1543
1544                 if (dev->phy.rev < 2) {
1545                         if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1546                                 b43_hf_write(dev, b43_hf_read(dev) |
1547                                                 B43_HF_MLADVW);
1548                 } else if (dev->phy.rev == 2) {
1549                         b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1550                         b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1551                 }
1552
1553                 if (dev->phy.rev < 2)
1554                         b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1555                                         ~B43_NPHY_SCRAM_SIGCTL_SCM);
1556
1557                 /* Set phase track alpha and beta */
1558                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1559                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1560                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1561                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1562                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1563                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1564
1565                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1566                                 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1567                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1568                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1569                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1570
1571                 if (dev->phy.rev == 2)
1572                         b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1573                                         B43_NPHY_FINERX2_CGC_DECGC);
1574         }
1575
1576         if (nphy->hang_avoid)
1577                 b43_nphy_stay_in_carrier_search(dev, 0);
1578 }
1579
1580 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1581 static int b43_nphy_load_samples(struct b43_wldev *dev,
1582                                         struct b43_c32 *samples, u16 len) {
1583         struct b43_phy_n *nphy = dev->phy.n;
1584         u16 i;
1585         u32 *data;
1586
1587         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1588         if (!data) {
1589                 b43err(dev->wl, "allocation for samples loading failed\n");
1590                 return -ENOMEM;
1591         }
1592         if (nphy->hang_avoid)
1593                 b43_nphy_stay_in_carrier_search(dev, 1);
1594
1595         for (i = 0; i < len; i++) {
1596                 data[i] = (samples[i].i & 0x3FF << 10);
1597                 data[i] |= samples[i].q & 0x3FF;
1598         }
1599         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1600
1601         kfree(data);
1602         if (nphy->hang_avoid)
1603                 b43_nphy_stay_in_carrier_search(dev, 0);
1604         return 0;
1605 }
1606
1607 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1608 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1609                                         bool test)
1610 {
1611         int i;
1612         u16 bw, len, rot, angle;
1613         struct b43_c32 *samples;
1614
1615
1616         bw = (dev->phy.is_40mhz) ? 40 : 20;
1617         len = bw << 3;
1618
1619         if (test) {
1620                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1621                         bw = 82;
1622                 else
1623                         bw = 80;
1624
1625                 if (dev->phy.is_40mhz)
1626                         bw <<= 1;
1627
1628                 len = bw << 1;
1629         }
1630
1631         samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1632         if (!samples) {
1633                 b43err(dev->wl, "allocation for samples generation failed\n");
1634                 return 0;
1635         }
1636         rot = (((freq * 36) / bw) << 16) / 100;
1637         angle = 0;
1638
1639         for (i = 0; i < len; i++) {
1640                 samples[i] = b43_cordic(angle);
1641                 angle += rot;
1642                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1643                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1644         }
1645
1646         i = b43_nphy_load_samples(dev, samples, len);
1647         kfree(samples);
1648         return (i < 0) ? 0 : len;
1649 }
1650
1651 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1652 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1653                                         u16 wait, bool iqmode, bool dac_test)
1654 {
1655         struct b43_phy_n *nphy = dev->phy.n;
1656         int i;
1657         u16 seq_mode;
1658         u32 tmp;
1659
1660         if (nphy->hang_avoid)
1661                 b43_nphy_stay_in_carrier_search(dev, true);
1662
1663         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1664                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1665                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1666         }
1667
1668         if (!dev->phy.is_40mhz)
1669                 tmp = 0x6464;
1670         else
1671                 tmp = 0x4747;
1672         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1673
1674         if (nphy->hang_avoid)
1675                 b43_nphy_stay_in_carrier_search(dev, false);
1676
1677         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1678
1679         if (loops != 0xFFFF)
1680                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1681         else
1682                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1683
1684         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1685
1686         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1687
1688         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1689         if (iqmode) {
1690                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1691                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1692         } else {
1693                 if (dac_test)
1694                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1695                 else
1696                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1697         }
1698         for (i = 0; i < 100; i++) {
1699                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1700                         i = 0;
1701                         break;
1702                 }
1703                 udelay(10);
1704         }
1705         if (i)
1706                 b43err(dev->wl, "run samples timeout\n");
1707
1708         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1709 }
1710
1711 /*
1712  * Transmits a known value for LO calibration
1713  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1714  */
1715 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1716                                 bool iqmode, bool dac_test)
1717 {
1718         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1719         if (samp == 0)
1720                 return -1;
1721         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1722         return 0;
1723 }
1724
1725 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1726 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1727 {
1728         struct b43_phy_n *nphy = dev->phy.n;
1729         int i, j;
1730         u32 tmp;
1731         u32 cur_real, cur_imag, real_part, imag_part;
1732
1733         u16 buffer[7];
1734
1735         if (nphy->hang_avoid)
1736                 b43_nphy_stay_in_carrier_search(dev, true);
1737
1738         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1739
1740         for (i = 0; i < 2; i++) {
1741                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1742                         (buffer[i * 2 + 1] & 0x3FF);
1743                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1744                                 (((i + 26) << 10) | 320));
1745                 for (j = 0; j < 128; j++) {
1746                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1747                                         ((tmp >> 16) & 0xFFFF));
1748                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1749                                         (tmp & 0xFFFF));
1750                 }
1751         }
1752
1753         for (i = 0; i < 2; i++) {
1754                 tmp = buffer[5 + i];
1755                 real_part = (tmp >> 8) & 0xFF;
1756                 imag_part = (tmp & 0xFF);
1757                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1758                                 (((i + 26) << 10) | 448));
1759
1760                 if (dev->phy.rev >= 3) {
1761                         cur_real = real_part;
1762                         cur_imag = imag_part;
1763                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1764                 }
1765
1766                 for (j = 0; j < 128; j++) {
1767                         if (dev->phy.rev < 3) {
1768                                 cur_real = (real_part * loscale[j] + 128) >> 8;
1769                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1770                                 tmp = ((cur_real & 0xFF) << 8) |
1771                                         (cur_imag & 0xFF);
1772                         }
1773                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1774                                         ((tmp >> 16) & 0xFFFF));
1775                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1776                                         (tmp & 0xFFFF));
1777                 }
1778         }
1779
1780         if (dev->phy.rev >= 3) {
1781                 b43_shm_write16(dev, B43_SHM_SHARED,
1782                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1783                 b43_shm_write16(dev, B43_SHM_SHARED,
1784                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1785         }
1786
1787         if (nphy->hang_avoid)
1788                 b43_nphy_stay_in_carrier_search(dev, false);
1789 }
1790
1791 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1792 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1793                                         u8 *events, u8 *delays, u8 length)
1794 {
1795         struct b43_phy_n *nphy = dev->phy.n;
1796         u8 i;
1797         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1798         u16 offset1 = cmd << 4;
1799         u16 offset2 = offset1 + 0x80;
1800
1801         if (nphy->hang_avoid)
1802                 b43_nphy_stay_in_carrier_search(dev, true);
1803
1804         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1805         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1806
1807         for (i = length; i < 16; i++) {
1808                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1809                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1810         }
1811
1812         if (nphy->hang_avoid)
1813                 b43_nphy_stay_in_carrier_search(dev, false);
1814 }
1815
1816 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1817 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1818                                        enum b43_nphy_rf_sequence seq)
1819 {
1820         static const u16 trigger[] = {
1821                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1822                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1823                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1824                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1825                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1826                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1827         };
1828         int i;
1829         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1830
1831         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1832
1833         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1834                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1835         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1836         for (i = 0; i < 200; i++) {
1837                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1838                         goto ok;
1839                 msleep(1);
1840         }
1841         b43err(dev->wl, "RF sequence status timeout\n");
1842 ok:
1843         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1844 }
1845
1846 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1847 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1848                                                 u16 value, u8 core, bool off)
1849 {
1850         int i;
1851         u8 index = fls(field);
1852         u8 addr, en_addr, val_addr;
1853         /* we expect only one bit set */
1854         B43_WARN_ON(field & (~(1 << (index - 1))));
1855
1856         if (dev->phy.rev >= 3) {
1857                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1858                 for (i = 0; i < 2; i++) {
1859                         if (index == 0 || index == 16) {
1860                                 b43err(dev->wl,
1861                                         "Unsupported RF Ctrl Override call\n");
1862                                 return;
1863                         }
1864
1865                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1866                         en_addr = B43_PHY_N((i == 0) ?
1867                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1868                         val_addr = B43_PHY_N((i == 0) ?
1869                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1870
1871                         if (off) {
1872                                 b43_phy_mask(dev, en_addr, ~(field));
1873                                 b43_phy_mask(dev, val_addr,
1874                                                 ~(rf_ctrl->val_mask));
1875                         } else {
1876                                 if (core == 0 || ((1 << core) & i) != 0) {
1877                                         b43_phy_set(dev, en_addr, field);
1878                                         b43_phy_maskset(dev, val_addr,
1879                                                 ~(rf_ctrl->val_mask),
1880                                                 (value << rf_ctrl->val_shift));
1881                                 }
1882                         }
1883                 }
1884         } else {
1885                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1886                 if (off) {
1887                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1888                         value = 0;
1889                 } else {
1890                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1891                 }
1892
1893                 for (i = 0; i < 2; i++) {
1894                         if (index <= 1 || index == 16) {
1895                                 b43err(dev->wl,
1896                                         "Unsupported RF Ctrl Override call\n");
1897                                 return;
1898                         }
1899
1900                         if (index == 2 || index == 10 ||
1901                             (index >= 13 && index <= 15)) {
1902                                 core = 1;
1903                         }
1904
1905                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1906                         addr = B43_PHY_N((i == 0) ?
1907                                 rf_ctrl->addr0 : rf_ctrl->addr1);
1908
1909                         if ((core & (1 << i)) != 0)
1910                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1911                                                 (value << rf_ctrl->shift));
1912
1913                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1914                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1915                                         B43_NPHY_RFCTL_CMD_START);
1916                         udelay(1);
1917                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1918                 }
1919         }
1920 }
1921
1922 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1923 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1924                                                 u16 value, u8 core)
1925 {
1926         u8 i, j;
1927         u16 reg, tmp, val;
1928
1929         B43_WARN_ON(dev->phy.rev < 3);
1930         B43_WARN_ON(field > 4);
1931
1932         for (i = 0; i < 2; i++) {
1933                 if ((core == 1 && i == 1) || (core == 2 && !i))
1934                         continue;
1935
1936                 reg = (i == 0) ?
1937                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1938                 b43_phy_mask(dev, reg, 0xFBFF);
1939
1940                 switch (field) {
1941                 case 0:
1942                         b43_phy_write(dev, reg, 0);
1943                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1944                         break;
1945                 case 1:
1946                         if (!i) {
1947                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1948                                                 0xFC3F, (value << 6));
1949                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1950                                                 0xFFFE, 1);
1951                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1952                                                 B43_NPHY_RFCTL_CMD_START);
1953                                 for (j = 0; j < 100; j++) {
1954                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1955                                                 j = 0;
1956                                                 break;
1957                                         }
1958                                         udelay(10);
1959                                 }
1960                                 if (j)
1961                                         b43err(dev->wl,
1962                                                 "intc override timeout\n");
1963                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1964                                                 0xFFFE);
1965                         } else {
1966                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1967                                                 0xFC3F, (value << 6));
1968                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1969                                                 0xFFFE, 1);
1970                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1971                                                 B43_NPHY_RFCTL_CMD_RXTX);
1972                                 for (j = 0; j < 100; j++) {
1973                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1974                                                 j = 0;
1975                                                 break;
1976                                         }
1977                                         udelay(10);
1978                                 }
1979                                 if (j)
1980                                         b43err(dev->wl,
1981                                                 "intc override timeout\n");
1982                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1983                                                 0xFFFE);
1984                         }
1985                         break;
1986                 case 2:
1987                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1988                                 tmp = 0x0020;
1989                                 val = value << 5;
1990                         } else {
1991                                 tmp = 0x0010;
1992                                 val = value << 4;
1993                         }
1994                         b43_phy_maskset(dev, reg, ~tmp, val);
1995                         break;
1996                 case 3:
1997                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1998                                 tmp = 0x0001;
1999                                 val = value;
2000                         } else {
2001                                 tmp = 0x0004;
2002                                 val = value << 2;
2003                         }
2004                         b43_phy_maskset(dev, reg, ~tmp, val);
2005                         break;
2006                 case 4:
2007                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2008                                 tmp = 0x0002;
2009                                 val = value << 1;
2010                         } else {
2011                                 tmp = 0x0008;
2012                                 val = value << 3;
2013                         }
2014                         b43_phy_maskset(dev, reg, ~tmp, val);
2015                         break;
2016                 }
2017         }
2018 }
2019
2020 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
2021 static void b43_nphy_bphy_init(struct b43_wldev *dev)
2022 {
2023         unsigned int i;
2024         u16 val;
2025
2026         val = 0x1E1F;
2027         for (i = 0; i < 16; i++) {
2028                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
2029                 val -= 0x202;
2030         }
2031         val = 0x3E3F;
2032         for (i = 0; i < 16; i++) {
2033                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
2034                 val -= 0x202;
2035         }
2036         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
2037 }
2038
2039 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
2040 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
2041                                         s8 offset, u8 core, u8 rail,
2042                                         enum b43_nphy_rssi_type type)
2043 {
2044         u16 tmp;
2045         bool core1or5 = (core == 1) || (core == 5);
2046         bool core2or5 = (core == 2) || (core == 5);
2047
2048         offset = clamp_val(offset, -32, 31);
2049         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
2050
2051         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2052                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
2053         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2054                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
2055         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2056                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
2057         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2058                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
2059
2060         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2061                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
2062         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2063                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
2064         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2065                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
2066         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2067                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
2068
2069         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2070                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
2071         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2072                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
2073         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2074                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
2075         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2076                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
2077
2078         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2079                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
2080         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2081                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
2082         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2083                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
2084         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2085                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
2086
2087         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2088                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
2089         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2090                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
2091         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2092                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
2093         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2094                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
2095
2096         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
2097                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
2098         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
2099                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
2100
2101         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2102                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
2103         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2104                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
2105 }
2106
2107 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2108 {
2109         u16 val;
2110
2111         if (type < 3)
2112                 val = 0;
2113         else if (type == 6)
2114                 val = 1;
2115         else if (type == 3)
2116                 val = 2;
2117         else
2118                 val = 3;
2119
2120         val = (val << 12) | (val << 14);
2121         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
2122         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
2123
2124         if (type < 3) {
2125                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
2126                                 (type + 1) << 4);
2127                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
2128                                 (type + 1) << 4);
2129         }
2130
2131         if (code == 0) {
2132                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
2133                 if (type < 3) {
2134                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2135                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
2136                                   B43_NPHY_RFCTL_CMD_CORESEL));
2137                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2138                                 ~(0x1 << 12 |
2139                                   0x1 << 5 |
2140                                   0x1 << 1 |
2141                                   0x1));
2142                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2143                                 ~B43_NPHY_RFCTL_CMD_START);
2144                         udelay(20);
2145                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2146                 }
2147         } else {
2148                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
2149                 if (type < 3) {
2150                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
2151                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
2152                                   B43_NPHY_RFCTL_CMD_CORESEL),
2153                                 (B43_NPHY_RFCTL_CMD_RXEN |
2154                                  code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
2155                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
2156                                 (0x1 << 12 |
2157                                   0x1 << 5 |
2158                                   0x1 << 1 |
2159                                   0x1));
2160                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2161                                 B43_NPHY_RFCTL_CMD_START);
2162                         udelay(20);
2163                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2164                 }
2165         }
2166 }
2167
2168 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2169 {
2170         struct b43_phy_n *nphy = dev->phy.n;
2171         u8 i;
2172         u16 reg, val;
2173
2174         if (code == 0) {
2175                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
2176                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
2177                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
2178                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
2179                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
2180                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
2181                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
2182                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
2183         } else {
2184                 for (i = 0; i < 2; i++) {
2185                         if ((code == 1 && i == 1) || (code == 2 && !i))
2186                                 continue;
2187
2188                         reg = (i == 0) ?
2189                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
2190                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
2191
2192                         if (type < 3) {
2193                                 reg = (i == 0) ?
2194                                         B43_NPHY_AFECTL_C1 :
2195                                         B43_NPHY_AFECTL_C2;
2196                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
2197
2198                                 reg = (i == 0) ?
2199                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
2200                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
2201                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
2202
2203                                 if (type == 0)
2204                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
2205                                 else if (type == 1)
2206                                         val = 16;
2207                                 else
2208                                         val = 32;
2209                                 b43_phy_set(dev, reg, val);
2210
2211                                 reg = (i == 0) ?
2212                                         B43_NPHY_TXF_40CO_B1S0 :
2213                                         B43_NPHY_TXF_40CO_B32S1;
2214                                 b43_phy_set(dev, reg, 0x0020);
2215                         } else {
2216                                 if (type == 6)
2217                                         val = 0x0100;
2218                                 else if (type == 3)
2219                                         val = 0x0200;
2220                                 else
2221                                         val = 0x0300;
2222
2223                                 reg = (i == 0) ?
2224                                         B43_NPHY_AFECTL_C1 :
2225                                         B43_NPHY_AFECTL_C2;
2226
2227                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
2228                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
2229
2230                                 if (type != 3 && type != 6) {
2231                                         enum ieee80211_band band =
2232                                                 b43_current_band(dev->wl);
2233
2234                                         if ((nphy->ipa2g_on &&
2235                                                 band == IEEE80211_BAND_2GHZ) ||
2236                                                 (nphy->ipa5g_on &&
2237                                                 band == IEEE80211_BAND_5GHZ))
2238                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
2239                                         else
2240                                                 val = 0x11;
2241                                         reg = (i == 0) ? 0x2000 : 0x3000;
2242                                         reg |= B2055_PADDRV;
2243                                         b43_radio_write16(dev, reg, val);
2244
2245                                         reg = (i == 0) ?
2246                                                 B43_NPHY_AFECTL_OVER1 :
2247                                                 B43_NPHY_AFECTL_OVER;
2248                                         b43_phy_set(dev, reg, 0x0200);
2249                                 }
2250                         }
2251                 }
2252         }
2253 }
2254
2255 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
2256 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2257 {
2258         if (dev->phy.rev >= 3)
2259                 b43_nphy_rev3_rssi_select(dev, code, type);
2260         else
2261                 b43_nphy_rev2_rssi_select(dev, code, type);
2262 }
2263
2264 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
2265 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
2266 {
2267         int i;
2268         for (i = 0; i < 2; i++) {
2269                 if (type == 2) {
2270                         if (i == 0) {
2271                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
2272                                                   0xFC, buf[0]);
2273                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2274                                                   0xFC, buf[1]);
2275                         } else {
2276                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
2277                                                   0xFC, buf[2 * i]);
2278                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2279                                                   0xFC, buf[2 * i + 1]);
2280                         }
2281                 } else {
2282                         if (i == 0)
2283                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2284                                                   0xF3, buf[0] << 2);
2285                         else
2286                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2287                                                   0xF3, buf[2 * i + 1] << 2);
2288                 }
2289         }
2290 }
2291
2292 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
2293 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
2294                                 u8 nsamp)
2295 {
2296         int i;
2297         int out;
2298         u16 save_regs_phy[9];
2299         u16 s[2];
2300
2301         if (dev->phy.rev >= 3) {
2302                 save_regs_phy[0] = b43_phy_read(dev,
2303                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
2304                 save_regs_phy[1] = b43_phy_read(dev,
2305                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
2306                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2307                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2308                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2309                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2310                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
2311                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
2312                 save_regs_phy[8] = 0;
2313         } else {
2314                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2315                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2316                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2317                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
2318                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2319                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2320                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2321                 save_regs_phy[7] = 0;
2322                 save_regs_phy[8] = 0;
2323         }
2324
2325         b43_nphy_rssi_select(dev, 5, type);
2326
2327         if (dev->phy.rev < 2) {
2328                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
2329                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
2330         }
2331
2332         for (i = 0; i < 4; i++)
2333                 buf[i] = 0;
2334
2335         for (i = 0; i < nsamp; i++) {
2336                 if (dev->phy.rev < 2) {
2337                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
2338                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
2339                 } else {
2340                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2341                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2342                 }
2343
2344                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2345                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2346                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2347                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2348         }
2349         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2350                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2351
2352         if (dev->phy.rev < 2)
2353                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2354
2355         if (dev->phy.rev >= 3) {
2356                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2357                                 save_regs_phy[0]);
2358                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2359                                 save_regs_phy[1]);
2360                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
2361                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
2362                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2363                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2364                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2365                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2366         } else {
2367                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2368                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2369                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2370                 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2371                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2372                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2373                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2374         }
2375
2376         return out;
2377 }
2378
2379 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2380 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
2381 {
2382         int i, j;
2383         u8 state[4];
2384         u8 code, val;
2385         u16 class, override;
2386         u8 regs_save_radio[2];
2387         u16 regs_save_phy[2];
2388
2389         s8 offset[4];
2390         u8 core;
2391         u8 rail;
2392
2393         u16 clip_state[2];
2394         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2395         s32 results_min[4] = { };
2396         u8 vcm_final[4] = { };
2397         s32 results[4][4] = { };
2398         s32 miniq[4][2] = { };
2399
2400         if (type == 2) {
2401                 code = 0;
2402                 val = 6;
2403         } else if (type < 2) {
2404                 code = 25;
2405                 val = 4;
2406         } else {
2407                 B43_WARN_ON(1);
2408                 return;
2409         }
2410
2411         class = b43_nphy_classifier(dev, 0, 0);
2412         b43_nphy_classifier(dev, 7, 4);
2413         b43_nphy_read_clip_detection(dev, clip_state);
2414         b43_nphy_write_clip_detection(dev, clip_off);
2415
2416         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2417                 override = 0x140;
2418         else
2419                 override = 0x110;
2420
2421         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2422         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
2423         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2424         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
2425
2426         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2427         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
2428         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2429         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
2430
2431         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2432         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2433         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2434         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2435         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
2436         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
2437
2438         b43_nphy_rssi_select(dev, 5, type);
2439         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
2440         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
2441
2442         for (i = 0; i < 4; i++) {
2443                 u8 tmp[4];
2444                 for (j = 0; j < 4; j++)
2445                         tmp[j] = i;
2446                 if (type != 1)
2447                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2448                 b43_nphy_poll_rssi(dev, type, results[i], 8);
2449                 if (type < 2)
2450                         for (j = 0; j < 2; j++)
2451                                 miniq[i][j] = min(results[i][2 * j],
2452                                                 results[i][2 * j + 1]);
2453         }
2454
2455         for (i = 0; i < 4; i++) {
2456                 s32 mind = 40;
2457                 u8 minvcm = 0;
2458                 s32 minpoll = 249;
2459                 s32 curr;
2460                 for (j = 0; j < 4; j++) {
2461                         if (type == 2)
2462                                 curr = abs(results[j][i]);
2463                         else
2464                                 curr = abs(miniq[j][i / 2] - code * 8);
2465
2466                         if (curr < mind) {
2467                                 mind = curr;
2468                                 minvcm = j;
2469                         }
2470
2471                         if (results[j][i] < minpoll)
2472                                 minpoll = results[j][i];
2473                 }
2474                 results_min[i] = minpoll;
2475                 vcm_final[i] = minvcm;
2476         }
2477
2478         if (type != 1)
2479                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2480
2481         for (i = 0; i < 4; i++) {
2482                 offset[i] = (code * 8) - results[vcm_final[i]][i];
2483
2484                 if (offset[i] < 0)
2485                         offset[i] = -((abs(offset[i]) + 4) / 8);
2486                 else
2487                         offset[i] = (offset[i] + 4) / 8;
2488
2489                 if (results_min[i] == 248)
2490                         offset[i] = code - 32;
2491
2492                 core = (i / 2) ? 2 : 1;
2493                 rail = (i % 2) ? 1 : 0;
2494
2495                 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2496                                                 type);
2497         }
2498
2499         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2500         b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2501
2502         switch (state[2]) {
2503         case 1:
2504                 b43_nphy_rssi_select(dev, 1, 2);
2505                 break;
2506         case 4:
2507                 b43_nphy_rssi_select(dev, 1, 0);
2508                 break;
2509         case 2:
2510                 b43_nphy_rssi_select(dev, 1, 1);
2511                 break;
2512         default:
2513                 b43_nphy_rssi_select(dev, 1, 1);
2514                 break;
2515         }
2516
2517         switch (state[3]) {
2518         case 1:
2519                 b43_nphy_rssi_select(dev, 2, 2);
2520                 break;
2521         case 4:
2522                 b43_nphy_rssi_select(dev, 2, 0);
2523                 break;
2524         default:
2525                 b43_nphy_rssi_select(dev, 2, 1);
2526                 break;
2527         }
2528
2529         b43_nphy_rssi_select(dev, 0, type);
2530
2531         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2532         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2533         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2534         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2535
2536         b43_nphy_classifier(dev, 7, class);
2537         b43_nphy_write_clip_detection(dev, clip_state);
2538         /* Specs don't say about reset here, but it makes wl and b43 dumps
2539            identical, it really seems wl performs this */
2540         b43_nphy_reset_cca(dev);
2541 }
2542
2543 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2544 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2545 {
2546         /* TODO */
2547 }
2548
2549 /*
2550  * RSSI Calibration
2551  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2552  */
2553 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2554 {
2555         if (dev->phy.rev >= 3) {
2556                 b43_nphy_rev3_rssi_cal(dev);
2557         } else {
2558                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
2559                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
2560                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
2561         }
2562 }
2563
2564 /*
2565  * Restore RSSI Calibration
2566  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2567  */
2568 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2569 {
2570         struct b43_phy_n *nphy = dev->phy.n;
2571
2572         u16 *rssical_radio_regs = NULL;
2573         u16 *rssical_phy_regs = NULL;
2574
2575         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2576                 if (!nphy->rssical_chanspec_2G.center_freq)
2577                         return;
2578                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2579                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2580         } else {
2581                 if (!nphy->rssical_chanspec_5G.center_freq)
2582                         return;
2583                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2584                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2585         }
2586
2587         /* TODO use some definitions */
2588         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2589         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2590
2591         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2592         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2593         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2594         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2595
2596         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2597         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2598         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2599         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2600
2601         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2602         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2603         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2604         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2605 }
2606
2607 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2608 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2609 {
2610         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2611                 if (dev->phy.rev >= 6) {
2612                         /* TODO If the chip is 47162
2613                                 return txpwrctrl_tx_gain_ipa_rev5 */
2614                         return txpwrctrl_tx_gain_ipa_rev6;
2615                 } else if (dev->phy.rev >= 5) {
2616                         return txpwrctrl_tx_gain_ipa_rev5;
2617                 } else {
2618                         return txpwrctrl_tx_gain_ipa;
2619                 }
2620         } else {
2621                 return txpwrctrl_tx_gain_ipa_5g;
2622         }
2623 }
2624
2625 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2626 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2627 {
2628         struct b43_phy_n *nphy = dev->phy.n;
2629         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2630         u16 tmp;
2631         u8 offset, i;
2632
2633         if (dev->phy.rev >= 3) {
2634             for (i = 0; i < 2; i++) {
2635                 tmp = (i == 0) ? 0x2000 : 0x3000;
2636                 offset = i * 11;
2637
2638                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2639                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2640                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2641                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2642                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2643                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2644                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2645                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2646                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2647                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2648                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2649
2650                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2651                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2652                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2653                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2654                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2655                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2656                         if (nphy->ipa5g_on) {
2657                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2658                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2659                         } else {
2660                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2661                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2662                         }
2663                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2664                 } else {
2665                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2666                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2667                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2668                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2669                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2670                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2671                         if (nphy->ipa2g_on) {
2672                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2673                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2674                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2675                         } else {
2676                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2677                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2678                         }
2679                 }
2680                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2681                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2682                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2683             }
2684         } else {
2685                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2686                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2687
2688                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2689                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2690
2691                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2692                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2693
2694                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2695                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2696
2697                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2698                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2699
2700                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2701                     B43_NPHY_BANDCTL_5GHZ)) {
2702                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2703                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2704                 } else {
2705                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2706                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2707                 }
2708
2709                 if (dev->phy.rev < 2) {
2710                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2711                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2712                 } else {
2713                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2714                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2715                 }
2716         }
2717 }
2718
2719 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2720 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2721                                         struct nphy_txgains target,
2722                                         struct nphy_iqcal_params *params)
2723 {
2724         int i, j, indx;
2725         u16 gain;
2726
2727         if (dev->phy.rev >= 3) {
2728                 params->txgm = target.txgm[core];
2729                 params->pga = target.pga[core];
2730                 params->pad = target.pad[core];
2731                 params->ipa = target.ipa[core];
2732                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2733                                         (params->pad << 4) | (params->ipa);
2734                 for (j = 0; j < 5; j++)
2735                         params->ncorr[j] = 0x79;
2736         } else {
2737                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2738                         (target.txgm[core] << 8);
2739
2740                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2741                         1 : 0;
2742                 for (i = 0; i < 9; i++)
2743                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2744                                 break;
2745                 i = min(i, 8);
2746
2747                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2748                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2749                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2750                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2751                                         (params->pad << 2);
2752                 for (j = 0; j < 4; j++)
2753                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2754         }
2755 }
2756
2757 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2758 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2759 {
2760         struct b43_phy_n *nphy = dev->phy.n;
2761         int i;
2762         u16 scale, entry;
2763
2764         u16 tmp = nphy->txcal_bbmult;
2765         if (core == 0)
2766                 tmp >>= 8;
2767         tmp &= 0xff;
2768
2769         for (i = 0; i < 18; i++) {
2770                 scale = (ladder_lo[i].percent * tmp) / 100;
2771                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2772                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2773
2774                 scale = (ladder_iq[i].percent * tmp) / 100;
2775                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2776                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2777         }
2778 }
2779
2780 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2781 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2782 {
2783         int i;
2784         for (i = 0; i < 15; i++)
2785                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2786                                 tbl_tx_filter_coef_rev4[2][i]);
2787 }
2788
2789 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2790 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2791 {
2792         int i, j;
2793         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2794         static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
2795
2796         for (i = 0; i < 3; i++)
2797                 for (j = 0; j < 15; j++)
2798                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2799                                         tbl_tx_filter_coef_rev4[i][j]);
2800
2801         if (dev->phy.is_40mhz) {
2802                 for (j = 0; j < 15; j++)
2803                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2804                                         tbl_tx_filter_coef_rev4[3][j]);
2805         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2806                 for (j = 0; j < 15; j++)
2807                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2808                                         tbl_tx_filter_coef_rev4[5][j]);
2809         }
2810
2811         if (dev->phy.channel == 14)
2812                 for (j = 0; j < 15; j++)
2813                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2814                                         tbl_tx_filter_coef_rev4[6][j]);
2815 }
2816
2817 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2818 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2819 {
2820         struct b43_phy_n *nphy = dev->phy.n;
2821
2822         u16 curr_gain[2];
2823         struct nphy_txgains target;
2824         const u32 *table = NULL;
2825
2826         if (!nphy->txpwrctrl) {
2827                 int i;
2828
2829                 if (nphy->hang_avoid)
2830                         b43_nphy_stay_in_carrier_search(dev, true);
2831                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2832                 if (nphy->hang_avoid)
2833                         b43_nphy_stay_in_carrier_search(dev, false);
2834
2835                 for (i = 0; i < 2; ++i) {
2836                         if (dev->phy.rev >= 3) {
2837                                 target.ipa[i] = curr_gain[i] & 0x000F;
2838                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2839                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2840                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2841                         } else {
2842                                 target.ipa[i] = curr_gain[i] & 0x0003;
2843                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2844                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2845                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2846                         }
2847                 }
2848         } else {
2849                 int i;
2850                 u16 index[2];
2851                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2852                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2853                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2854                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2855                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2856                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2857
2858                 for (i = 0; i < 2; ++i) {
2859                         if (dev->phy.rev >= 3) {
2860                                 enum ieee80211_band band =
2861                                         b43_current_band(dev->wl);
2862
2863                                 if ((nphy->ipa2g_on &&
2864                                      band == IEEE80211_BAND_2GHZ) ||
2865                                     (nphy->ipa5g_on &&
2866                                      band == IEEE80211_BAND_5GHZ)) {
2867                                         table = b43_nphy_get_ipa_gain_table(dev);
2868                                 } else {
2869                                         if (band == IEEE80211_BAND_5GHZ) {
2870                                                 if (dev->phy.rev == 3)
2871                                                         table = b43_ntab_tx_gain_rev3_5ghz;
2872                                                 else if (dev->phy.rev == 4)
2873                                                         table = b43_ntab_tx_gain_rev4_5ghz;
2874                                                 else
2875                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
2876                                         } else {
2877                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
2878                                         }
2879                                 }
2880
2881                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2882                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2883                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2884                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2885                         } else {
2886                                 table = b43_ntab_tx_gain_rev0_1_2;
2887
2888                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2889                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2890                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2891                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2892                         }
2893                 }
2894         }
2895
2896         return target;
2897 }
2898
2899 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2900 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2901 {
2902         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2903
2904         if (dev->phy.rev >= 3) {
2905                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2906                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2907                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2908                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2909                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2910                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2911                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2912                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2913                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2914                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2915                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2916                 b43_nphy_reset_cca(dev);
2917         } else {
2918                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2919                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2920                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2921                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2922                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2923                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2924                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2925         }
2926 }
2927
2928 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2929 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2930 {
2931         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2932         u16 tmp;
2933
2934         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2935         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2936         if (dev->phy.rev >= 3) {
2937                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2938                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2939
2940                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2941                 regs[2] = tmp;
2942                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2943
2944                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2945                 regs[3] = tmp;
2946                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2947
2948                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2949                 b43_phy_mask(dev, B43_NPHY_BBCFG,
2950                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
2951
2952                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2953                 regs[5] = tmp;
2954                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2955
2956                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2957                 regs[6] = tmp;
2958                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2959                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2960                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2961
2962                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2963                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2964                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2965
2966                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2967                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2968                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2969                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2970         } else {
2971                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2972                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2973                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2974                 regs[2] = tmp;
2975                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2976                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2977                 regs[3] = tmp;
2978                 tmp |= 0x2000;
2979                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2980                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2981                 regs[4] = tmp;
2982                 tmp |= 0x2000;
2983                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2984                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2985                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2986                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2987                         tmp = 0x0180;
2988                 else
2989                         tmp = 0x0120;
2990                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2991                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2992         }
2993 }
2994
2995 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2996 static void b43_nphy_save_cal(struct b43_wldev *dev)
2997 {
2998         struct b43_phy_n *nphy = dev->phy.n;
2999
3000         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3001         u16 *txcal_radio_regs = NULL;
3002         struct b43_chanspec *iqcal_chanspec;
3003         u16 *table = NULL;
3004
3005         if (nphy->hang_avoid)
3006                 b43_nphy_stay_in_carrier_search(dev, 1);
3007
3008         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3009                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3010                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3011                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
3012                 table = nphy->cal_cache.txcal_coeffs_2G;
3013         } else {
3014                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3015                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3016                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
3017                 table = nphy->cal_cache.txcal_coeffs_5G;
3018         }
3019
3020         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
3021         /* TODO use some definitions */
3022         if (dev->phy.rev >= 3) {
3023                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
3024                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
3025                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
3026                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
3027                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
3028                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
3029                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
3030                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
3031         } else {
3032                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3033                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3034                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3035                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3036         }
3037         iqcal_chanspec->center_freq = dev->phy.channel_freq;
3038         iqcal_chanspec->channel_type = dev->phy.channel_type;
3039         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
3040
3041         if (nphy->hang_avoid)
3042                 b43_nphy_stay_in_carrier_search(dev, 0);
3043 }
3044
3045 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
3046 static void b43_nphy_restore_cal(struct b43_wldev *dev)
3047 {
3048         struct b43_phy_n *nphy = dev->phy.n;
3049
3050         u16 coef[4];
3051         u16 *loft = NULL;
3052         u16 *table = NULL;
3053
3054         int i;
3055         u16 *txcal_radio_regs = NULL;
3056         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3057
3058         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3059                 if (!nphy->iqcal_chanspec_2G.center_freq)
3060                         return;
3061                 table = nphy->cal_cache.txcal_coeffs_2G;
3062                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3063         } else {
3064                 if (!nphy->iqcal_chanspec_5G.center_freq)
3065                         return;
3066                 table = nphy->cal_cache.txcal_coeffs_5G;
3067                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3068         }
3069
3070         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
3071
3072         for (i = 0; i < 4; i++) {
3073                 if (dev->phy.rev >= 3)
3074                         table[i] = coef[i];
3075                 else
3076                         coef[i] = 0;
3077         }
3078
3079         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3080         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3081         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
3082
3083         if (dev->phy.rev < 2)
3084                 b43_nphy_tx_iq_workaround(dev);
3085
3086         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3087                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3088                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3089         } else {
3090                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3091                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3092         }
3093
3094         /* TODO use some definitions */
3095         if (dev->phy.rev >= 3) {
3096                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3097                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3098                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3099                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3100                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3101                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3102                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3103                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3104         } else {
3105                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3106                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3107                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3108                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3109         }
3110         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3111 }
3112
3113 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
3114 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3115                                 struct nphy_txgains target,
3116                                 bool full, bool mphase)
3117 {
3118         struct b43_phy_n *nphy = dev->phy.n;
3119         int i;
3120         int error = 0;
3121         int freq;
3122         bool avoid = false;
3123         u8 length;
3124         u16 tmp, core, type, count, max, numb, last = 0, cmd;
3125         const u16 *table;
3126         bool phy6or5x;
3127
3128         u16 buffer[11];
3129         u16 diq_start = 0;
3130         u16 save[2];
3131         u16 gain[2];
3132         struct nphy_iqcal_params params[2];
3133         bool updated[2] = { };
3134
3135         b43_nphy_stay_in_carrier_search(dev, true);
3136
3137         if (dev->phy.rev >= 4) {
3138                 avoid = nphy->hang_avoid;
3139                 nphy->hang_avoid = 0;
3140         }
3141
3142         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3143
3144         for (i = 0; i < 2; i++) {
3145                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
3146                 gain[i] = params[i].cal_gain;
3147         }
3148
3149         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
3150
3151         b43_nphy_tx_cal_radio_setup(dev);
3152         b43_nphy_tx_cal_phy_setup(dev);
3153
3154         phy6or5x = dev->phy.rev >= 6 ||
3155                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
3156                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3157         if (phy6or5x) {
3158                 if (dev->phy.is_40mhz) {
3159                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3160                                         tbl_tx_iqlo_cal_loft_ladder_40);
3161                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3162                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
3163                 } else {
3164                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3165                                         tbl_tx_iqlo_cal_loft_ladder_20);
3166                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3167                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
3168                 }
3169         }
3170
3171         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3172
3173         if (!dev->phy.is_40mhz)
3174                 freq = 2500;
3175         else
3176                 freq = 5000;
3177
3178         if (nphy->mphase_cal_phase_id > 2)
3179                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3180                                         0xFFFF, 0, true, false);
3181         else
3182                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
3183
3184         if (error == 0) {
3185                 if (nphy->mphase_cal_phase_id > 2) {
3186                         table = nphy->mphase_txcal_bestcoeffs;
3187                         length = 11;
3188                         if (dev->phy.rev < 3)
3189                                 length -= 2;
3190                 } else {
3191                         if (!full && nphy->txiqlocal_coeffsvalid) {
3192                                 table = nphy->txiqlocal_bestc;
3193                                 length = 11;
3194                                 if (dev->phy.rev < 3)
3195                                         length -= 2;
3196                         } else {
3197                                 full = true;
3198                                 if (dev->phy.rev >= 3) {
3199                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3200                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3201                                 } else {
3202                                         table = tbl_tx_iqlo_cal_startcoefs;
3203                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3204                                 }
3205                         }
3206                 }
3207
3208                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
3209
3210                 if (full) {
3211                         if (dev->phy.rev >= 3)
3212                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3213                         else
3214                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3215                 } else {
3216                         if (dev->phy.rev >= 3)
3217                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3218                         else
3219                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3220                 }
3221
3222                 if (mphase) {
3223                         count = nphy->mphase_txcal_cmdidx;
3224                         numb = min(max,
3225                                 (u16)(count + nphy->mphase_txcal_numcmds));
3226                 } else {
3227                         count = 0;
3228                         numb = max;
3229                 }
3230
3231                 for (; count < numb; count++) {
3232                         if (full) {
3233                                 if (dev->phy.rev >= 3)
3234                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3235                                 else
3236                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3237                         } else {
3238                                 if (dev->phy.rev >= 3)
3239                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3240                                 else
3241                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3242                         }
3243
3244                         core = (cmd & 0x3000) >> 12;
3245                         type = (cmd & 0x0F00) >> 8;
3246
3247                         if (phy6or5x && updated[core] == 0) {
3248                                 b43_nphy_update_tx_cal_ladder(dev, core);
3249                                 updated[core] = 1;
3250                         }
3251
3252                         tmp = (params[core].ncorr[type] << 8) | 0x66;
3253                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3254
3255                         if (type == 1 || type == 3 || type == 4) {
3256                                 buffer[0] = b43_ntab_read(dev,
3257                                                 B43_NTAB16(15, 69 + core));
3258                                 diq_start = buffer[0];
3259                                 buffer[0] = 0;
3260                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3261                                                 0);
3262                         }
3263
3264                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3265                         for (i = 0; i < 2000; i++) {
3266                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3267                                 if (tmp & 0xC000)
3268                                         break;
3269                                 udelay(10);
3270                         }
3271
3272                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3273                                                 buffer);
3274                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3275                                                 buffer);
3276
3277                         if (type == 1 || type == 3 || type == 4)
3278                                 buffer[0] = diq_start;
3279                 }
3280
3281                 if (mphase)
3282                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3283
3284                 last = (dev->phy.rev < 3) ? 6 : 7;
3285
3286                 if (!mphase || nphy->mphase_cal_phase_id == last) {
3287                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
3288                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
3289                         if (dev->phy.rev < 3) {
3290                                 buffer[0] = 0;
3291                                 buffer[1] = 0;
3292                                 buffer[2] = 0;
3293                                 buffer[3] = 0;
3294                         }
3295                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3296                                                 buffer);
3297                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
3298                                                 buffer);
3299                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3300                                                 buffer);
3301                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3302                                                 buffer);
3303                         length = 11;
3304                         if (dev->phy.rev < 3)
3305                                 length -= 2;
3306                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3307                                                 nphy->txiqlocal_bestc);
3308                         nphy->txiqlocal_coeffsvalid = true;
3309                         nphy->txiqlocal_chanspec.center_freq =
3310                                                         dev->phy.channel_freq;
3311                         nphy->txiqlocal_chanspec.channel_type =
3312                                                         dev->phy.channel_type;
3313                 } else {
3314                         length = 11;
3315                         if (dev->phy.rev < 3)
3316                                 length -= 2;
3317                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3318                                                 nphy->mphase_txcal_bestcoeffs);
3319                 }
3320
3321                 b43_nphy_stop_playback(dev);
3322                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3323         }
3324
3325         b43_nphy_tx_cal_phy_cleanup(dev);
3326         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3327
3328         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3329                 b43_nphy_tx_iq_workaround(dev);
3330
3331         if (dev->phy.rev >= 4)
3332                 nphy->hang_avoid = avoid;
3333
3334         b43_nphy_stay_in_carrier_search(dev, false);
3335
3336         return error;
3337 }
3338
3339 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3340 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3341 {
3342         struct b43_phy_n *nphy = dev->phy.n;
3343         u8 i;
3344         u16 buffer[7];
3345         bool equal = true;
3346
3347         if (!nphy->txiqlocal_coeffsvalid ||
3348             nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3349             nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
3350                 return;
3351
3352         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3353         for (i = 0; i < 4; i++) {
3354                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3355                         equal = false;
3356                         break;
3357                 }
3358         }
3359
3360         if (!equal) {
3361                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3362                                         nphy->txiqlocal_bestc);
3363                 for (i = 0; i < 4; i++)
3364                         buffer[i] = 0;
3365                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3366                                         buffer);
3367                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3368                                         &nphy->txiqlocal_bestc[5]);
3369                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3370                                         &nphy->txiqlocal_bestc[5]);
3371         }
3372 }
3373
3374 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3375 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3376                         struct nphy_txgains target, u8 type, bool debug)
3377 {
3378         struct b43_phy_n *nphy = dev->phy.n;
3379         int i, j, index;
3380         u8 rfctl[2];
3381         u8 afectl_core;
3382         u16 tmp[6];
3383         u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
3384         u32 real, imag;
3385         enum ieee80211_band band;
3386
3387         u8 use;
3388         u16 cur_hpf;
3389         u16 lna[3] = { 3, 3, 1 };
3390         u16 hpf1[3] = { 7, 2, 0 };
3391         u16 hpf2[3] = { 2, 0, 0 };
3392         u32 power[3] = { };
3393         u16 gain_save[2];
3394         u16 cal_gain[2];
3395         struct nphy_iqcal_params cal_params[2];
3396         struct nphy_iq_est est;
3397         int ret = 0;
3398         bool playtone = true;
3399         int desired = 13;
3400
3401         b43_nphy_stay_in_carrier_search(dev, 1);
3402
3403         if (dev->phy.rev < 2)
3404                 b43_nphy_reapply_tx_cal_coeffs(dev);
3405         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3406         for (i = 0; i < 2; i++) {
3407                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3408                 cal_gain[i] = cal_params[i].cal_gain;
3409         }
3410         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
3411
3412         for (i = 0; i < 2; i++) {
3413                 if (i == 0) {
3414                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
3415                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
3416                         afectl_core = B43_NPHY_AFECTL_C1;
3417                 } else {
3418                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
3419                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
3420                         afectl_core = B43_NPHY_AFECTL_C2;
3421                 }
3422
3423                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3424                 tmp[2] = b43_phy_read(dev, afectl_core);
3425                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3426                 tmp[4] = b43_phy_read(dev, rfctl[0]);
3427                 tmp[5] = b43_phy_read(dev, rfctl[1]);
3428
3429                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3430                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3431                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3432                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3433                                 (1 - i));
3434                 b43_phy_set(dev, afectl_core, 0x0006);
3435                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3436
3437                 band = b43_current_band(dev->wl);
3438
3439                 if (nphy->rxcalparams & 0xFF000000) {
3440                         if (band == IEEE80211_BAND_5GHZ)
3441                                 b43_phy_write(dev, rfctl[0], 0x140);
3442                         else
3443                                 b43_phy_write(dev, rfctl[0], 0x110);
3444                 } else {
3445                         if (band == IEEE80211_BAND_5GHZ)
3446                                 b43_phy_write(dev, rfctl[0], 0x180);
3447                         else
3448                                 b43_phy_write(dev, rfctl[0], 0x120);
3449                 }
3450
3451                 if (band == IEEE80211_BAND_5GHZ)
3452                         b43_phy_write(dev, rfctl[1], 0x148);
3453                 else
3454                         b43_phy_write(dev, rfctl[1], 0x114);
3455
3456                 if (nphy->rxcalparams & 0x10000) {
3457                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3458                                         (i + 1));
3459                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3460                                         (2 - i));
3461                 }
3462
3463                 for (j = 0; j < 4; j++) {
3464                         if (j < 3) {
3465                                 cur_lna = lna[j];
3466                                 cur_hpf1 = hpf1[j];
3467                                 cur_hpf2 = hpf2[j];
3468                         } else {
3469                                 if (power[1] > 10000) {
3470                                         use = 1;
3471                                         cur_hpf = cur_hpf1;
3472                                         index = 2;
3473                                 } else {
3474                                         if (power[0] > 10000) {
3475                                                 use = 1;
3476                                                 cur_hpf = cur_hpf1;
3477                                                 index = 1;
3478                                         } else {
3479                                                 index = 0;
3480                                                 use = 2;
3481                                                 cur_hpf = cur_hpf2;
3482                                         }
3483                                 }
3484                                 cur_lna = lna[index];
3485                                 cur_hpf1 = hpf1[index];
3486                                 cur_hpf2 = hpf2[index];
3487                                 cur_hpf += desired - hweight32(power[index]);
3488                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
3489                                 if (use == 1)
3490                                         cur_hpf1 = cur_hpf;
3491                                 else
3492                                         cur_hpf2 = cur_hpf;
3493                         }
3494
3495                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3496                                         (cur_lna << 2));
3497                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3498                                                                         false);
3499                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3500                         b43_nphy_stop_playback(dev);
3501
3502                         if (playtone) {
3503                                 ret = b43_nphy_tx_tone(dev, 4000,
3504                                                 (nphy->rxcalparams & 0xFFFF),
3505                                                 false, false);
3506                                 playtone = false;
3507                         } else {
3508                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3509                                                         false, false);
3510                         }
3511
3512                         if (ret == 0) {
3513                                 if (j < 3) {
3514                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3515                                                                         false);
3516                                         if (i == 0) {
3517                                                 real = est.i0_pwr;
3518                                                 imag = est.q0_pwr;
3519                                         } else {
3520                                                 real = est.i1_pwr;
3521                                                 imag = est.q1_pwr;
3522                                         }
3523                                         power[i] = ((real + imag) / 1024) + 1;
3524                                 } else {
3525                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3526                                 }
3527                                 b43_nphy_stop_playback(dev);
3528                         }
3529
3530                         if (ret != 0)
3531                                 break;
3532                 }
3533
3534                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3535                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3536                 b43_phy_write(dev, rfctl[1], tmp[5]);
3537                 b43_phy_write(dev, rfctl[0], tmp[4]);
3538                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3539                 b43_phy_write(dev, afectl_core, tmp[2]);
3540                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3541
3542                 if (ret != 0)
3543                         break;
3544         }
3545
3546         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3547         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3548         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3549
3550         b43_nphy_stay_in_carrier_search(dev, 0);
3551
3552         return ret;
3553 }
3554
3555 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3556                         struct nphy_txgains target, u8 type, bool debug)
3557 {
3558         return -1;
3559 }
3560
3561 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3562 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3563                         struct nphy_txgains target, u8 type, bool debug)
3564 {
3565         if (dev->phy.rev >= 3)
3566                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3567         else
3568                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3569 }
3570
3571 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3572 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3573 {
3574         struct b43_phy *phy = &dev->phy;
3575         struct b43_phy_n *nphy = phy->n;
3576         /* u16 buf[16]; it's rev3+ */
3577
3578         nphy->phyrxchain = mask;
3579
3580         if (0 /* FIXME clk */)
3581                 return;
3582
3583         b43_mac_suspend(dev);
3584
3585         if (nphy->hang_avoid)
3586                 b43_nphy_stay_in_carrier_search(dev, true);
3587
3588         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3589                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3590
3591         if ((mask & 0x3) != 0x3) {
3592                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3593                 if (dev->phy.rev >= 3) {
3594                         /* TODO */
3595                 }
3596         } else {
3597                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3598                 if (dev->phy.rev >= 3) {
3599                         /* TODO */
3600                 }
3601         }
3602
3603         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3604
3605         if (nphy->hang_avoid)
3606                 b43_nphy_stay_in_carrier_search(dev, false);
3607
3608         b43_mac_enable(dev);
3609 }
3610
3611 /*
3612  * Init N-PHY
3613  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3614  */
3615 int b43_phy_initn(struct b43_wldev *dev)
3616 {
3617         struct ssb_sprom *sprom = dev->dev->bus_sprom;
3618         struct b43_phy *phy = &dev->phy;
3619         struct b43_phy_n *nphy = phy->n;
3620         u8 tx_pwr_state;
3621         struct nphy_txgains target;
3622         u16 tmp;
3623         enum ieee80211_band tmp2;
3624         bool do_rssi_cal;
3625
3626         u16 clip[2];
3627         bool do_cal = false;
3628
3629         if ((dev->phy.rev >= 3) &&
3630            (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
3631            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3632                 switch (dev->dev->bus_type) {
3633 #ifdef CONFIG_B43_BCMA
3634                 case B43_BUS_BCMA:
3635                         bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
3636                                       BCMA_CC_CHIPCTL, 0x40);
3637                         break;
3638 #endif
3639 #ifdef CONFIG_B43_SSB
3640                 case B43_BUS_SSB:
3641                         chipco_set32(&dev->dev->sdev->bus->chipco,
3642                                      SSB_CHIPCO_CHIPCTL, 0x40);
3643                         break;
3644 #endif
3645                 }
3646         }
3647         nphy->deaf_count = 0;
3648         b43_nphy_tables_init(dev);
3649         nphy->crsminpwr_adjusted = false;
3650         nphy->noisevars_adjusted = false;
3651
3652         /* Clear all overrides */
3653         if (dev->phy.rev >= 3) {
3654                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3655                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3656                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3657                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3658         } else {
3659                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3660         }
3661         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3662         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3663         if (dev->phy.rev < 6) {
3664                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3665                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3666         }
3667         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3668                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3669                        B43_NPHY_RFSEQMODE_TROVER));
3670         if (dev->phy.rev >= 3)
3671                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3672         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3673
3674         if (dev->phy.rev <= 2) {
3675                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3676                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3677                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3678                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3679         }
3680         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3681         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3682
3683         if (sprom->boardflags2_lo & 0x100 ||
3684             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
3685              dev->dev->board_type == 0x8B))
3686                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3687         else
3688                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3689         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3690         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3691         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3692
3693         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3694         b43_nphy_update_txrx_chain(dev);
3695
3696         if (phy->rev < 2) {
3697                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3698                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3699         }
3700
3701         tmp2 = b43_current_band(dev->wl);
3702         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3703             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3704                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3705                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3706                                 nphy->papd_epsilon_offset[0] << 7);
3707                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3708                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3709                                 nphy->papd_epsilon_offset[1] << 7);
3710                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3711         } else if (phy->rev >= 5) {
3712                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3713         }
3714
3715         b43_nphy_workarounds(dev);
3716
3717         /* Reset CCA, in init code it differs a little from standard way */
3718         b43_nphy_bmac_clock_fgc(dev, 1);
3719         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3720         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3721         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3722         b43_nphy_bmac_clock_fgc(dev, 0);
3723
3724         b43_mac_phy_clock_set(dev, true);
3725
3726         b43_nphy_pa_override(dev, false);
3727         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3728         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3729         b43_nphy_pa_override(dev, true);
3730
3731         b43_nphy_classifier(dev, 0, 0);
3732         b43_nphy_read_clip_detection(dev, clip);
3733         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3734                 b43_nphy_bphy_init(dev);
3735
3736         tx_pwr_state = nphy->txpwrctrl;
3737         b43_nphy_tx_power_ctrl(dev, false);
3738         b43_nphy_tx_power_fix(dev);
3739         /* TODO N PHY TX Power Control Idle TSSI */
3740         /* TODO N PHY TX Power Control Setup */
3741
3742         if (phy->rev >= 3) {
3743                 /* TODO */
3744         } else {
3745                 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3746                                         b43_ntab_tx_gain_rev0_1_2);
3747                 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3748                                         b43_ntab_tx_gain_rev0_1_2);
3749         }
3750
3751         if (nphy->phyrxchain != 3)
3752                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3753         if (nphy->mphase_cal_phase_id > 0)
3754                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3755
3756         do_rssi_cal = false;
3757         if (phy->rev >= 3) {
3758                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3759                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
3760                 else
3761                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
3762
3763                 if (do_rssi_cal)
3764                         b43_nphy_rssi_cal(dev);
3765                 else
3766                         b43_nphy_restore_rssi_cal(dev);
3767         } else {
3768                 b43_nphy_rssi_cal(dev);
3769         }
3770
3771         if (!((nphy->measure_hold & 0x6) != 0)) {
3772                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3773                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
3774                 else
3775                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
3776
3777                 if (nphy->mute)
3778                         do_cal = false;
3779
3780                 if (do_cal) {
3781                         target = b43_nphy_get_tx_gains(dev);
3782
3783                         if (nphy->antsel_type == 2)
3784                                 b43_nphy_superswitch_init(dev, true);
3785                         if (nphy->perical != 2) {
3786                                 b43_nphy_rssi_cal(dev);
3787                                 if (phy->rev >= 3) {
3788                                         nphy->cal_orig_pwr_idx[0] =
3789                                             nphy->txpwrindex[0].index_internal;
3790                                         nphy->cal_orig_pwr_idx[1] =
3791                                             nphy->txpwrindex[1].index_internal;
3792                                         /* TODO N PHY Pre Calibrate TX Gain */
3793                                         target = b43_nphy_get_tx_gains(dev);
3794                                 }
3795                                 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
3796                                         if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3797                                                 b43_nphy_save_cal(dev);
3798                         } else if (nphy->mphase_cal_phase_id == 0)
3799                                 ;/* N PHY Periodic Calibration with arg 3 */
3800                 } else {
3801                         b43_nphy_restore_cal(dev);
3802                 }
3803         }
3804
3805         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3806         b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
3807         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3808         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3809         if (phy->rev >= 3 && phy->rev <= 6)
3810                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3811         b43_nphy_tx_lp_fbw(dev);
3812         if (phy->rev >= 3)
3813                 b43_nphy_spur_workaround(dev);
3814
3815         return 0;
3816 }
3817
3818 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
3819 static void b43_nphy_channel_setup(struct b43_wldev *dev,
3820                                 const struct b43_phy_n_sfo_cfg *e,
3821                                 struct ieee80211_channel *new_channel)
3822 {
3823         struct b43_phy *phy = &dev->phy;
3824         struct b43_phy_n *nphy = dev->phy.n;
3825
3826         u16 old_band_5ghz;
3827         u32 tmp32;
3828
3829         old_band_5ghz =
3830                 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3831         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
3832                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3833                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3834                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3835                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3836                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3837         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
3838                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3839                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3840                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3841                 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
3842                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3843         }
3844
3845         b43_chantab_phy_upload(dev, e);
3846
3847         if (new_channel->hw_value == 14) {
3848                 b43_nphy_classifier(dev, 2, 0);
3849                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3850         } else {
3851                 b43_nphy_classifier(dev, 2, 2);
3852                 if (new_channel->band == IEEE80211_BAND_2GHZ)
3853                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3854         }
3855
3856         if (!nphy->txpwrctrl)
3857                 b43_nphy_tx_power_fix(dev);
3858
3859         if (dev->phy.rev < 3)
3860                 b43_nphy_adjust_lna_gain_table(dev);
3861
3862         b43_nphy_tx_lp_fbw(dev);
3863
3864         if (dev->phy.rev >= 3 && 0) {
3865                 /* TODO */
3866         }
3867
3868         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3869
3870         if (phy->rev >= 3)
3871                 b43_nphy_spur_workaround(dev);
3872 }
3873
3874 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
3875 static int b43_nphy_set_channel(struct b43_wldev *dev,
3876                                 struct ieee80211_channel *channel,
3877                                 enum nl80211_channel_type channel_type)
3878 {
3879         struct b43_phy *phy = &dev->phy;
3880
3881         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
3882         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
3883
3884         u8 tmp;
3885
3886         if (dev->phy.rev >= 3) {
3887                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
3888                                                         channel->center_freq);
3889                 if (!tabent_r3)
3890                         return -ESRCH;
3891         } else {
3892                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
3893                                                         channel->hw_value);
3894                 if (!tabent_r2)
3895                         return -ESRCH;
3896         }
3897
3898         /* Channel is set later in common code, but we need to set it on our
3899            own to let this function's subcalls work properly. */
3900         phy->channel = channel->hw_value;
3901         phy->channel_freq = channel->center_freq;
3902
3903         if (b43_channel_type_is_40mhz(phy->channel_type) !=
3904                 b43_channel_type_is_40mhz(channel_type))
3905                 ; /* TODO: BMAC BW Set (channel_type) */
3906
3907         if (channel_type == NL80211_CHAN_HT40PLUS)
3908                 b43_phy_set(dev, B43_NPHY_RXCTL,
3909                                 B43_NPHY_RXCTL_BSELU20);
3910         else if (channel_type == NL80211_CHAN_HT40MINUS)
3911                 b43_phy_mask(dev, B43_NPHY_RXCTL,
3912                                 ~B43_NPHY_RXCTL_BSELU20);
3913
3914         if (dev->phy.rev >= 3) {
3915                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
3916                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
3917                 b43_radio_2056_setup(dev, tabent_r3);
3918                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
3919         } else {
3920                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
3921                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
3922                 b43_radio_2055_setup(dev, tabent_r2);
3923                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
3924         }
3925
3926         return 0;
3927 }
3928
3929 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3930 {
3931         struct b43_phy_n *nphy;
3932
3933         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3934         if (!nphy)
3935                 return -ENOMEM;
3936         dev->phy.n = nphy;
3937
3938         return 0;
3939 }
3940
3941 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3942 {
3943         struct b43_phy *phy = &dev->phy;
3944         struct b43_phy_n *nphy = phy->n;
3945
3946         memset(nphy, 0, sizeof(*nphy));
3947
3948         nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
3949         nphy->gain_boost = true; /* this way we follow wl, assume it is true */
3950         nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
3951         nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
3952         nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
3953 }
3954
3955 static void b43_nphy_op_free(struct b43_wldev *dev)
3956 {
3957         struct b43_phy *phy = &dev->phy;
3958         struct b43_phy_n *nphy = phy->n;
3959
3960         kfree(nphy);
3961         phy->n = NULL;
3962 }
3963
3964 static int b43_nphy_op_init(struct b43_wldev *dev)
3965 {
3966         return b43_phy_initn(dev);
3967 }
3968
3969 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3970 {
3971 #if B43_DEBUG
3972         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3973                 /* OFDM registers are onnly available on A/G-PHYs */
3974                 b43err(dev->wl, "Invalid OFDM PHY access at "
3975                        "0x%04X on N-PHY\n", offset);
3976                 dump_stack();
3977         }
3978         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3979                 /* Ext-G registers are only available on G-PHYs */
3980                 b43err(dev->wl, "Invalid EXT-G PHY access at "
3981                        "0x%04X on N-PHY\n", offset);
3982                 dump_stack();
3983         }
3984 #endif /* B43_DEBUG */
3985 }
3986
3987 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3988 {
3989         check_phyreg(dev, reg);
3990         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3991         return b43_read16(dev, B43_MMIO_PHY_DATA);
3992 }
3993
3994 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3995 {
3996         check_phyreg(dev, reg);
3997         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3998         b43_write16(dev, B43_MMIO_PHY_DATA, value);
3999 }
4000
4001 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
4002                                  u16 set)
4003 {
4004         check_phyreg(dev, reg);
4005         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4006         b43_write16(dev, B43_MMIO_PHY_DATA,
4007                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
4008 }
4009
4010 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
4011 {
4012         /* Register 1 is a 32-bit register. */
4013         B43_WARN_ON(reg == 1);
4014         /* N-PHY needs 0x100 for read access */
4015         reg |= 0x100;
4016
4017         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4018         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4019 }
4020
4021 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
4022 {
4023         /* Register 1 is a 32-bit register. */
4024         B43_WARN_ON(reg == 1);
4025
4026         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4027         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
4028 }
4029
4030 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
4031 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
4032                                         bool blocked)
4033 {
4034         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
4035                 b43err(dev->wl, "MAC not suspended\n");
4036
4037         if (blocked) {
4038                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
4039                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
4040                 if (dev->phy.rev >= 3) {
4041                         b43_radio_mask(dev, 0x09, ~0x2);
4042
4043                         b43_radio_write(dev, 0x204D, 0);
4044                         b43_radio_write(dev, 0x2053, 0);
4045                         b43_radio_write(dev, 0x2058, 0);
4046                         b43_radio_write(dev, 0x205E, 0);
4047                         b43_radio_mask(dev, 0x2062, ~0xF0);
4048                         b43_radio_write(dev, 0x2064, 0);
4049
4050                         b43_radio_write(dev, 0x304D, 0);
4051                         b43_radio_write(dev, 0x3053, 0);
4052                         b43_radio_write(dev, 0x3058, 0);
4053                         b43_radio_write(dev, 0x305E, 0);
4054                         b43_radio_mask(dev, 0x3062, ~0xF0);
4055                         b43_radio_write(dev, 0x3064, 0);
4056                 }
4057         } else {
4058                 if (dev->phy.rev >= 3) {
4059                         b43_radio_init2056(dev);
4060                         b43_switch_channel(dev, dev->phy.channel);
4061                 } else {
4062                         b43_radio_init2055(dev);
4063                 }
4064         }
4065 }
4066
4067 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
4068 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4069 {
4070         u16 override = on ? 0x0 : 0x7FFF;
4071         u16 core = on ? 0xD : 0x00FD;
4072
4073         if (dev->phy.rev >= 3) {
4074                 if (on) {
4075                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4076                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4077                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4078                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4079                 } else {
4080                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4081                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4082                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4083                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4084                 }
4085         } else {
4086                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4087         }
4088 }
4089
4090 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4091                                       unsigned int new_channel)
4092 {
4093         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4094         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
4095
4096         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4097                 if ((new_channel < 1) || (new_channel > 14))
4098                         return -EINVAL;
4099         } else {
4100                 if (new_channel > 200)
4101                         return -EINVAL;
4102         }
4103
4104         return b43_nphy_set_channel(dev, channel, channel_type);
4105 }
4106
4107 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4108 {
4109         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4110                 return 1;
4111         return 36;
4112 }
4113
4114 const struct b43_phy_operations b43_phyops_n = {
4115         .allocate               = b43_nphy_op_allocate,
4116         .free                   = b43_nphy_op_free,
4117         .prepare_structs        = b43_nphy_op_prepare_structs,
4118         .init                   = b43_nphy_op_init,
4119         .phy_read               = b43_nphy_op_read,
4120         .phy_write              = b43_nphy_op_write,
4121         .phy_maskset            = b43_nphy_op_maskset,
4122         .radio_read             = b43_nphy_op_radio_read,
4123         .radio_write            = b43_nphy_op_radio_write,
4124         .software_rfkill        = b43_nphy_op_software_rfkill,
4125         .switch_analog          = b43_nphy_op_switch_analog,
4126         .switch_channel         = b43_nphy_op_switch_channel,
4127         .get_default_chan       = b43_nphy_op_get_default_chan,
4128         .recalc_txpower         = b43_nphy_op_recalc_txpower,
4129         .adjust_txpower         = b43_nphy_op_adjust_txpower,
4130 };