0cc804d0a214fcad833c7dcdbd2afd6e7451aee3
[linux-3.10.git] / drivers / net / wireless / b43 / dma.c
1 /*
2
3   Broadcom B43 wireless driver
4
5   DMA ringbuffer and descriptor allocation/management
6
7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8
9   Some code in this file is derived from the b44.c driver
10   Copyright (C) 2002 David S. Miller
11   Copyright (C) Pekka Pietikainen
12
13   This program is free software; you can redistribute it and/or modify
14   it under the terms of the GNU General Public License as published by
15   the Free Software Foundation; either version 2 of the License, or
16   (at your option) any later version.
17
18   This program is distributed in the hope that it will be useful,
19   but WITHOUT ANY WARRANTY; without even the implied warranty of
20   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21   GNU General Public License for more details.
22
23   You should have received a copy of the GNU General Public License
24   along with this program; see the file COPYING.  If not, write to
25   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26   Boston, MA 02110-1301, USA.
27
28 */
29
30 #include "b43.h"
31 #include "dma.h"
32 #include "main.h"
33 #include "debugfs.h"
34 #include "xmit.h"
35
36 #include <linux/dma-mapping.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/skbuff.h>
40 #include <linux/etherdevice.h>
41 #include <asm/div64.h>
42
43
44 /* Required number of TX DMA slots per TX frame.
45  * This currently is 2, because we put the header and the ieee80211 frame
46  * into separate slots. */
47 #define TX_SLOTS_PER_FRAME      2
48
49
50 /* 32bit DMA ops. */
51 static
52 struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
53                                           int slot,
54                                           struct b43_dmadesc_meta **meta)
55 {
56         struct b43_dmadesc32 *desc;
57
58         *meta = &(ring->meta[slot]);
59         desc = ring->descbase;
60         desc = &(desc[slot]);
61
62         return (struct b43_dmadesc_generic *)desc;
63 }
64
65 static void op32_fill_descriptor(struct b43_dmaring *ring,
66                                  struct b43_dmadesc_generic *desc,
67                                  dma_addr_t dmaaddr, u16 bufsize,
68                                  int start, int end, int irq)
69 {
70         struct b43_dmadesc32 *descbase = ring->descbase;
71         int slot;
72         u32 ctl;
73         u32 addr;
74         u32 addrext;
75
76         slot = (int)(&(desc->dma32) - descbase);
77         B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
78
79         addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
80         addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK)
81             >> SSB_DMA_TRANSLATION_SHIFT;
82         addr |= ssb_dma_translation(ring->dev->dev);
83         ctl = bufsize & B43_DMA32_DCTL_BYTECNT;
84         if (slot == ring->nr_slots - 1)
85                 ctl |= B43_DMA32_DCTL_DTABLEEND;
86         if (start)
87                 ctl |= B43_DMA32_DCTL_FRAMESTART;
88         if (end)
89                 ctl |= B43_DMA32_DCTL_FRAMEEND;
90         if (irq)
91                 ctl |= B43_DMA32_DCTL_IRQ;
92         ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
93             & B43_DMA32_DCTL_ADDREXT_MASK;
94
95         desc->dma32.control = cpu_to_le32(ctl);
96         desc->dma32.address = cpu_to_le32(addr);
97 }
98
99 static void op32_poke_tx(struct b43_dmaring *ring, int slot)
100 {
101         b43_dma_write(ring, B43_DMA32_TXINDEX,
102                       (u32) (slot * sizeof(struct b43_dmadesc32)));
103 }
104
105 static void op32_tx_suspend(struct b43_dmaring *ring)
106 {
107         b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
108                       | B43_DMA32_TXSUSPEND);
109 }
110
111 static void op32_tx_resume(struct b43_dmaring *ring)
112 {
113         b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
114                       & ~B43_DMA32_TXSUSPEND);
115 }
116
117 static int op32_get_current_rxslot(struct b43_dmaring *ring)
118 {
119         u32 val;
120
121         val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
122         val &= B43_DMA32_RXDPTR;
123
124         return (val / sizeof(struct b43_dmadesc32));
125 }
126
127 static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
128 {
129         b43_dma_write(ring, B43_DMA32_RXINDEX,
130                       (u32) (slot * sizeof(struct b43_dmadesc32)));
131 }
132
133 static const struct b43_dma_ops dma32_ops = {
134         .idx2desc = op32_idx2desc,
135         .fill_descriptor = op32_fill_descriptor,
136         .poke_tx = op32_poke_tx,
137         .tx_suspend = op32_tx_suspend,
138         .tx_resume = op32_tx_resume,
139         .get_current_rxslot = op32_get_current_rxslot,
140         .set_current_rxslot = op32_set_current_rxslot,
141 };
142
143 /* 64bit DMA ops. */
144 static
145 struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
146                                           int slot,
147                                           struct b43_dmadesc_meta **meta)
148 {
149         struct b43_dmadesc64 *desc;
150
151         *meta = &(ring->meta[slot]);
152         desc = ring->descbase;
153         desc = &(desc[slot]);
154
155         return (struct b43_dmadesc_generic *)desc;
156 }
157
158 static void op64_fill_descriptor(struct b43_dmaring *ring,
159                                  struct b43_dmadesc_generic *desc,
160                                  dma_addr_t dmaaddr, u16 bufsize,
161                                  int start, int end, int irq)
162 {
163         struct b43_dmadesc64 *descbase = ring->descbase;
164         int slot;
165         u32 ctl0 = 0, ctl1 = 0;
166         u32 addrlo, addrhi;
167         u32 addrext;
168
169         slot = (int)(&(desc->dma64) - descbase);
170         B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
171
172         addrlo = (u32) (dmaaddr & 0xFFFFFFFF);
173         addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
174         addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
175             >> SSB_DMA_TRANSLATION_SHIFT;
176         addrhi |= (ssb_dma_translation(ring->dev->dev) << 1);
177         if (slot == ring->nr_slots - 1)
178                 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
179         if (start)
180                 ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
181         if (end)
182                 ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
183         if (irq)
184                 ctl0 |= B43_DMA64_DCTL0_IRQ;
185         ctl1 |= bufsize & B43_DMA64_DCTL1_BYTECNT;
186         ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
187             & B43_DMA64_DCTL1_ADDREXT_MASK;
188
189         desc->dma64.control0 = cpu_to_le32(ctl0);
190         desc->dma64.control1 = cpu_to_le32(ctl1);
191         desc->dma64.address_low = cpu_to_le32(addrlo);
192         desc->dma64.address_high = cpu_to_le32(addrhi);
193 }
194
195 static void op64_poke_tx(struct b43_dmaring *ring, int slot)
196 {
197         b43_dma_write(ring, B43_DMA64_TXINDEX,
198                       (u32) (slot * sizeof(struct b43_dmadesc64)));
199 }
200
201 static void op64_tx_suspend(struct b43_dmaring *ring)
202 {
203         b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
204                       | B43_DMA64_TXSUSPEND);
205 }
206
207 static void op64_tx_resume(struct b43_dmaring *ring)
208 {
209         b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
210                       & ~B43_DMA64_TXSUSPEND);
211 }
212
213 static int op64_get_current_rxslot(struct b43_dmaring *ring)
214 {
215         u32 val;
216
217         val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
218         val &= B43_DMA64_RXSTATDPTR;
219
220         return (val / sizeof(struct b43_dmadesc64));
221 }
222
223 static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
224 {
225         b43_dma_write(ring, B43_DMA64_RXINDEX,
226                       (u32) (slot * sizeof(struct b43_dmadesc64)));
227 }
228
229 static const struct b43_dma_ops dma64_ops = {
230         .idx2desc = op64_idx2desc,
231         .fill_descriptor = op64_fill_descriptor,
232         .poke_tx = op64_poke_tx,
233         .tx_suspend = op64_tx_suspend,
234         .tx_resume = op64_tx_resume,
235         .get_current_rxslot = op64_get_current_rxslot,
236         .set_current_rxslot = op64_set_current_rxslot,
237 };
238
239 static inline int free_slots(struct b43_dmaring *ring)
240 {
241         return (ring->nr_slots - ring->used_slots);
242 }
243
244 static inline int next_slot(struct b43_dmaring *ring, int slot)
245 {
246         B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
247         if (slot == ring->nr_slots - 1)
248                 return 0;
249         return slot + 1;
250 }
251
252 static inline int prev_slot(struct b43_dmaring *ring, int slot)
253 {
254         B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
255         if (slot == 0)
256                 return ring->nr_slots - 1;
257         return slot - 1;
258 }
259
260 #ifdef CONFIG_B43_DEBUG
261 static void update_max_used_slots(struct b43_dmaring *ring,
262                                   int current_used_slots)
263 {
264         if (current_used_slots <= ring->max_used_slots)
265                 return;
266         ring->max_used_slots = current_used_slots;
267         if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
268                 b43dbg(ring->dev->wl,
269                        "max_used_slots increased to %d on %s ring %d\n",
270                        ring->max_used_slots,
271                        ring->tx ? "TX" : "RX", ring->index);
272         }
273 }
274 #else
275 static inline
276     void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
277 {
278 }
279 #endif /* DEBUG */
280
281 /* Request a slot for usage. */
282 static inline int request_slot(struct b43_dmaring *ring)
283 {
284         int slot;
285
286         B43_WARN_ON(!ring->tx);
287         B43_WARN_ON(ring->stopped);
288         B43_WARN_ON(free_slots(ring) == 0);
289
290         slot = next_slot(ring, ring->current_slot);
291         ring->current_slot = slot;
292         ring->used_slots++;
293
294         update_max_used_slots(ring, ring->used_slots);
295
296         return slot;
297 }
298
299 static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx)
300 {
301         static const u16 map64[] = {
302                 B43_MMIO_DMA64_BASE0,
303                 B43_MMIO_DMA64_BASE1,
304                 B43_MMIO_DMA64_BASE2,
305                 B43_MMIO_DMA64_BASE3,
306                 B43_MMIO_DMA64_BASE4,
307                 B43_MMIO_DMA64_BASE5,
308         };
309         static const u16 map32[] = {
310                 B43_MMIO_DMA32_BASE0,
311                 B43_MMIO_DMA32_BASE1,
312                 B43_MMIO_DMA32_BASE2,
313                 B43_MMIO_DMA32_BASE3,
314                 B43_MMIO_DMA32_BASE4,
315                 B43_MMIO_DMA32_BASE5,
316         };
317
318         if (type == B43_DMA_64BIT) {
319                 B43_WARN_ON(!(controller_idx >= 0 &&
320                               controller_idx < ARRAY_SIZE(map64)));
321                 return map64[controller_idx];
322         }
323         B43_WARN_ON(!(controller_idx >= 0 &&
324                       controller_idx < ARRAY_SIZE(map32)));
325         return map32[controller_idx];
326 }
327
328 static inline
329     dma_addr_t map_descbuffer(struct b43_dmaring *ring,
330                               unsigned char *buf, size_t len, int tx)
331 {
332         dma_addr_t dmaaddr;
333
334         if (tx) {
335                 dmaaddr = ssb_dma_map_single(ring->dev->dev,
336                                              buf, len, DMA_TO_DEVICE);
337         } else {
338                 dmaaddr = ssb_dma_map_single(ring->dev->dev,
339                                              buf, len, DMA_FROM_DEVICE);
340         }
341
342         return dmaaddr;
343 }
344
345 static inline
346     void unmap_descbuffer(struct b43_dmaring *ring,
347                           dma_addr_t addr, size_t len, int tx)
348 {
349         if (tx) {
350                 ssb_dma_unmap_single(ring->dev->dev,
351                                      addr, len, DMA_TO_DEVICE);
352         } else {
353                 ssb_dma_unmap_single(ring->dev->dev,
354                                      addr, len, DMA_FROM_DEVICE);
355         }
356 }
357
358 static inline
359     void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
360                                  dma_addr_t addr, size_t len)
361 {
362         B43_WARN_ON(ring->tx);
363         ssb_dma_sync_single_for_cpu(ring->dev->dev,
364                                     addr, len, DMA_FROM_DEVICE);
365 }
366
367 static inline
368     void sync_descbuffer_for_device(struct b43_dmaring *ring,
369                                     dma_addr_t addr, size_t len)
370 {
371         B43_WARN_ON(ring->tx);
372         ssb_dma_sync_single_for_device(ring->dev->dev,
373                                        addr, len, DMA_FROM_DEVICE);
374 }
375
376 static inline
377     void free_descriptor_buffer(struct b43_dmaring *ring,
378                                 struct b43_dmadesc_meta *meta)
379 {
380         if (meta->skb) {
381                 dev_kfree_skb_any(meta->skb);
382                 meta->skb = NULL;
383         }
384 }
385
386 static int alloc_ringmemory(struct b43_dmaring *ring)
387 {
388         gfp_t flags = GFP_KERNEL;
389
390         /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
391          * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
392          * has shown that 4K is sufficient for the latter as long as the buffer
393          * does not cross an 8K boundary.
394          *
395          * For unknown reasons - possibly a hardware error - the BCM4311 rev
396          * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
397          * which accounts for the GFP_DMA flag below.
398          *
399          * The flags here must match the flags in free_ringmemory below!
400          */
401         if (ring->type == B43_DMA_64BIT)
402                 flags |= GFP_DMA;
403         ring->descbase = ssb_dma_alloc_consistent(ring->dev->dev,
404                                                   B43_DMA_RINGMEMSIZE,
405                                                   &(ring->dmabase), flags);
406         if (!ring->descbase) {
407                 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
408                 return -ENOMEM;
409         }
410         memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
411
412         return 0;
413 }
414
415 static void free_ringmemory(struct b43_dmaring *ring)
416 {
417         gfp_t flags = GFP_KERNEL;
418
419         if (ring->type == B43_DMA_64BIT)
420                 flags |= GFP_DMA;
421
422         ssb_dma_free_consistent(ring->dev->dev, B43_DMA_RINGMEMSIZE,
423                                 ring->descbase, ring->dmabase, flags);
424 }
425
426 /* Reset the RX DMA channel */
427 static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,
428                                       enum b43_dmatype type)
429 {
430         int i;
431         u32 value;
432         u16 offset;
433
434         might_sleep();
435
436         offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
437         b43_write32(dev, mmio_base + offset, 0);
438         for (i = 0; i < 10; i++) {
439                 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS :
440                                                    B43_DMA32_RXSTATUS;
441                 value = b43_read32(dev, mmio_base + offset);
442                 if (type == B43_DMA_64BIT) {
443                         value &= B43_DMA64_RXSTAT;
444                         if (value == B43_DMA64_RXSTAT_DISABLED) {
445                                 i = -1;
446                                 break;
447                         }
448                 } else {
449                         value &= B43_DMA32_RXSTATE;
450                         if (value == B43_DMA32_RXSTAT_DISABLED) {
451                                 i = -1;
452                                 break;
453                         }
454                 }
455                 msleep(1);
456         }
457         if (i != -1) {
458                 b43err(dev->wl, "DMA RX reset timed out\n");
459                 return -ENODEV;
460         }
461
462         return 0;
463 }
464
465 /* Reset the TX DMA channel */
466 static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,
467                                       enum b43_dmatype type)
468 {
469         int i;
470         u32 value;
471         u16 offset;
472
473         might_sleep();
474
475         for (i = 0; i < 10; i++) {
476                 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
477                                                    B43_DMA32_TXSTATUS;
478                 value = b43_read32(dev, mmio_base + offset);
479                 if (type == B43_DMA_64BIT) {
480                         value &= B43_DMA64_TXSTAT;
481                         if (value == B43_DMA64_TXSTAT_DISABLED ||
482                             value == B43_DMA64_TXSTAT_IDLEWAIT ||
483                             value == B43_DMA64_TXSTAT_STOPPED)
484                                 break;
485                 } else {
486                         value &= B43_DMA32_TXSTATE;
487                         if (value == B43_DMA32_TXSTAT_DISABLED ||
488                             value == B43_DMA32_TXSTAT_IDLEWAIT ||
489                             value == B43_DMA32_TXSTAT_STOPPED)
490                                 break;
491                 }
492                 msleep(1);
493         }
494         offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
495         b43_write32(dev, mmio_base + offset, 0);
496         for (i = 0; i < 10; i++) {
497                 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
498                                                    B43_DMA32_TXSTATUS;
499                 value = b43_read32(dev, mmio_base + offset);
500                 if (type == B43_DMA_64BIT) {
501                         value &= B43_DMA64_TXSTAT;
502                         if (value == B43_DMA64_TXSTAT_DISABLED) {
503                                 i = -1;
504                                 break;
505                         }
506                 } else {
507                         value &= B43_DMA32_TXSTATE;
508                         if (value == B43_DMA32_TXSTAT_DISABLED) {
509                                 i = -1;
510                                 break;
511                         }
512                 }
513                 msleep(1);
514         }
515         if (i != -1) {
516                 b43err(dev->wl, "DMA TX reset timed out\n");
517                 return -ENODEV;
518         }
519         /* ensure the reset is completed. */
520         msleep(1);
521
522         return 0;
523 }
524
525 /* Check if a DMA mapping address is invalid. */
526 static bool b43_dma_mapping_error(struct b43_dmaring *ring,
527                                   dma_addr_t addr,
528                                   size_t buffersize, bool dma_to_device)
529 {
530         if (unlikely(ssb_dma_mapping_error(ring->dev->dev, addr)))
531                 return 1;
532
533         switch (ring->type) {
534         case B43_DMA_30BIT:
535                 if ((u64)addr + buffersize > (1ULL << 30))
536                         goto address_error;
537                 break;
538         case B43_DMA_32BIT:
539                 if ((u64)addr + buffersize > (1ULL << 32))
540                         goto address_error;
541                 break;
542         case B43_DMA_64BIT:
543                 /* Currently we can't have addresses beyond
544                  * 64bit in the kernel. */
545                 break;
546         }
547
548         /* The address is OK. */
549         return 0;
550
551 address_error:
552         /* We can't support this address. Unmap it again. */
553         unmap_descbuffer(ring, addr, buffersize, dma_to_device);
554
555         return 1;
556 }
557
558 static int setup_rx_descbuffer(struct b43_dmaring *ring,
559                                struct b43_dmadesc_generic *desc,
560                                struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
561 {
562         struct b43_rxhdr_fw4 *rxhdr;
563         dma_addr_t dmaaddr;
564         struct sk_buff *skb;
565
566         B43_WARN_ON(ring->tx);
567
568         skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
569         if (unlikely(!skb))
570                 return -ENOMEM;
571         dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
572         if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
573                 /* ugh. try to realloc in zone_dma */
574                 gfp_flags |= GFP_DMA;
575
576                 dev_kfree_skb_any(skb);
577
578                 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
579                 if (unlikely(!skb))
580                         return -ENOMEM;
581                 dmaaddr = map_descbuffer(ring, skb->data,
582                                          ring->rx_buffersize, 0);
583                 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
584                         b43err(ring->dev->wl, "RX DMA buffer allocation failed\n");
585                         dev_kfree_skb_any(skb);
586                         return -EIO;
587                 }
588         }
589
590         meta->skb = skb;
591         meta->dmaaddr = dmaaddr;
592         ring->ops->fill_descriptor(ring, desc, dmaaddr,
593                                    ring->rx_buffersize, 0, 0, 0);
594
595         rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
596         rxhdr->frame_len = 0;
597
598         return 0;
599 }
600
601 /* Allocate the initial descbuffers.
602  * This is used for an RX ring only.
603  */
604 static int alloc_initial_descbuffers(struct b43_dmaring *ring)
605 {
606         int i, err = -ENOMEM;
607         struct b43_dmadesc_generic *desc;
608         struct b43_dmadesc_meta *meta;
609
610         for (i = 0; i < ring->nr_slots; i++) {
611                 desc = ring->ops->idx2desc(ring, i, &meta);
612
613                 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
614                 if (err) {
615                         b43err(ring->dev->wl,
616                                "Failed to allocate initial descbuffers\n");
617                         goto err_unwind;
618                 }
619         }
620         mb();
621         ring->used_slots = ring->nr_slots;
622         err = 0;
623       out:
624         return err;
625
626       err_unwind:
627         for (i--; i >= 0; i--) {
628                 desc = ring->ops->idx2desc(ring, i, &meta);
629
630                 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
631                 dev_kfree_skb(meta->skb);
632         }
633         goto out;
634 }
635
636 /* Do initial setup of the DMA controller.
637  * Reset the controller, write the ring busaddress
638  * and switch the "enable" bit on.
639  */
640 static int dmacontroller_setup(struct b43_dmaring *ring)
641 {
642         int err = 0;
643         u32 value;
644         u32 addrext;
645         u32 trans = ssb_dma_translation(ring->dev->dev);
646
647         if (ring->tx) {
648                 if (ring->type == B43_DMA_64BIT) {
649                         u64 ringbase = (u64) (ring->dmabase);
650
651                         addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
652                             >> SSB_DMA_TRANSLATION_SHIFT;
653                         value = B43_DMA64_TXENABLE;
654                         value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
655                             & B43_DMA64_TXADDREXT_MASK;
656                         b43_dma_write(ring, B43_DMA64_TXCTL, value);
657                         b43_dma_write(ring, B43_DMA64_TXRINGLO,
658                                       (ringbase & 0xFFFFFFFF));
659                         b43_dma_write(ring, B43_DMA64_TXRINGHI,
660                                       ((ringbase >> 32) &
661                                        ~SSB_DMA_TRANSLATION_MASK)
662                                       | (trans << 1));
663                 } else {
664                         u32 ringbase = (u32) (ring->dmabase);
665
666                         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
667                             >> SSB_DMA_TRANSLATION_SHIFT;
668                         value = B43_DMA32_TXENABLE;
669                         value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
670                             & B43_DMA32_TXADDREXT_MASK;
671                         b43_dma_write(ring, B43_DMA32_TXCTL, value);
672                         b43_dma_write(ring, B43_DMA32_TXRING,
673                                       (ringbase & ~SSB_DMA_TRANSLATION_MASK)
674                                       | trans);
675                 }
676         } else {
677                 err = alloc_initial_descbuffers(ring);
678                 if (err)
679                         goto out;
680                 if (ring->type == B43_DMA_64BIT) {
681                         u64 ringbase = (u64) (ring->dmabase);
682
683                         addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
684                             >> SSB_DMA_TRANSLATION_SHIFT;
685                         value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
686                         value |= B43_DMA64_RXENABLE;
687                         value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
688                             & B43_DMA64_RXADDREXT_MASK;
689                         b43_dma_write(ring, B43_DMA64_RXCTL, value);
690                         b43_dma_write(ring, B43_DMA64_RXRINGLO,
691                                       (ringbase & 0xFFFFFFFF));
692                         b43_dma_write(ring, B43_DMA64_RXRINGHI,
693                                       ((ringbase >> 32) &
694                                        ~SSB_DMA_TRANSLATION_MASK)
695                                       | (trans << 1));
696                         b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
697                                       sizeof(struct b43_dmadesc64));
698                 } else {
699                         u32 ringbase = (u32) (ring->dmabase);
700
701                         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
702                             >> SSB_DMA_TRANSLATION_SHIFT;
703                         value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
704                         value |= B43_DMA32_RXENABLE;
705                         value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
706                             & B43_DMA32_RXADDREXT_MASK;
707                         b43_dma_write(ring, B43_DMA32_RXCTL, value);
708                         b43_dma_write(ring, B43_DMA32_RXRING,
709                                       (ringbase & ~SSB_DMA_TRANSLATION_MASK)
710                                       | trans);
711                         b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
712                                       sizeof(struct b43_dmadesc32));
713                 }
714         }
715
716 out:
717         return err;
718 }
719
720 /* Shutdown the DMA controller. */
721 static void dmacontroller_cleanup(struct b43_dmaring *ring)
722 {
723         if (ring->tx) {
724                 b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
725                                            ring->type);
726                 if (ring->type == B43_DMA_64BIT) {
727                         b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
728                         b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
729                 } else
730                         b43_dma_write(ring, B43_DMA32_TXRING, 0);
731         } else {
732                 b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
733                                            ring->type);
734                 if (ring->type == B43_DMA_64BIT) {
735                         b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
736                         b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
737                 } else
738                         b43_dma_write(ring, B43_DMA32_RXRING, 0);
739         }
740 }
741
742 static void free_all_descbuffers(struct b43_dmaring *ring)
743 {
744         struct b43_dmadesc_generic *desc;
745         struct b43_dmadesc_meta *meta;
746         int i;
747
748         if (!ring->used_slots)
749                 return;
750         for (i = 0; i < ring->nr_slots; i++) {
751                 desc = ring->ops->idx2desc(ring, i, &meta);
752
753                 if (!meta->skb) {
754                         B43_WARN_ON(!ring->tx);
755                         continue;
756                 }
757                 if (ring->tx) {
758                         unmap_descbuffer(ring, meta->dmaaddr,
759                                          meta->skb->len, 1);
760                 } else {
761                         unmap_descbuffer(ring, meta->dmaaddr,
762                                          ring->rx_buffersize, 0);
763                 }
764                 free_descriptor_buffer(ring, meta);
765         }
766 }
767
768 static u64 supported_dma_mask(struct b43_wldev *dev)
769 {
770         u32 tmp;
771         u16 mmio_base;
772
773         tmp = b43_read32(dev, SSB_TMSHIGH);
774         if (tmp & SSB_TMSHIGH_DMA64)
775                 return DMA_64BIT_MASK;
776         mmio_base = b43_dmacontroller_base(0, 0);
777         b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
778         tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
779         if (tmp & B43_DMA32_TXADDREXT_MASK)
780                 return DMA_32BIT_MASK;
781
782         return DMA_30BIT_MASK;
783 }
784
785 static enum b43_dmatype dma_mask_to_engine_type(u64 dmamask)
786 {
787         if (dmamask == DMA_30BIT_MASK)
788                 return B43_DMA_30BIT;
789         if (dmamask == DMA_32BIT_MASK)
790                 return B43_DMA_32BIT;
791         if (dmamask == DMA_64BIT_MASK)
792                 return B43_DMA_64BIT;
793         B43_WARN_ON(1);
794         return B43_DMA_30BIT;
795 }
796
797 /* Main initialization function. */
798 static
799 struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
800                                       int controller_index,
801                                       int for_tx,
802                                       enum b43_dmatype type)
803 {
804         struct b43_dmaring *ring;
805         int err;
806         dma_addr_t dma_test;
807
808         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
809         if (!ring)
810                 goto out;
811
812         ring->nr_slots = B43_RXRING_SLOTS;
813         if (for_tx)
814                 ring->nr_slots = B43_TXRING_SLOTS;
815
816         ring->meta = kcalloc(ring->nr_slots, sizeof(struct b43_dmadesc_meta),
817                              GFP_KERNEL);
818         if (!ring->meta)
819                 goto err_kfree_ring;
820
821         ring->type = type;
822         ring->dev = dev;
823         ring->mmio_base = b43_dmacontroller_base(type, controller_index);
824         ring->index = controller_index;
825         if (type == B43_DMA_64BIT)
826                 ring->ops = &dma64_ops;
827         else
828                 ring->ops = &dma32_ops;
829         if (for_tx) {
830                 ring->tx = 1;
831                 ring->current_slot = -1;
832         } else {
833                 if (ring->index == 0) {
834                         ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE;
835                         ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET;
836                 } else
837                         B43_WARN_ON(1);
838         }
839         spin_lock_init(&ring->lock);
840 #ifdef CONFIG_B43_DEBUG
841         ring->last_injected_overflow = jiffies;
842 #endif
843
844         if (for_tx) {
845                 /* Assumption: B43_TXRING_SLOTS can be divided by TX_SLOTS_PER_FRAME */
846                 BUILD_BUG_ON(B43_TXRING_SLOTS % TX_SLOTS_PER_FRAME != 0);
847
848                 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
849                                             b43_txhdr_size(dev),
850                                             GFP_KERNEL);
851                 if (!ring->txhdr_cache)
852                         goto err_kfree_meta;
853
854                 /* test for ability to dma to txhdr_cache */
855                 dma_test = ssb_dma_map_single(dev->dev,
856                                               ring->txhdr_cache,
857                                               b43_txhdr_size(dev),
858                                               DMA_TO_DEVICE);
859
860                 if (b43_dma_mapping_error(ring, dma_test,
861                                           b43_txhdr_size(dev), 1)) {
862                         /* ugh realloc */
863                         kfree(ring->txhdr_cache);
864                         ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
865                                                     b43_txhdr_size(dev),
866                                                     GFP_KERNEL | GFP_DMA);
867                         if (!ring->txhdr_cache)
868                                 goto err_kfree_meta;
869
870                         dma_test = ssb_dma_map_single(dev->dev,
871                                                       ring->txhdr_cache,
872                                                       b43_txhdr_size(dev),
873                                                       DMA_TO_DEVICE);
874
875                         if (b43_dma_mapping_error(ring, dma_test,
876                                                   b43_txhdr_size(dev), 1)) {
877
878                                 b43err(dev->wl,
879                                        "TXHDR DMA allocation failed\n");
880                                 goto err_kfree_txhdr_cache;
881                         }
882                 }
883
884                 ssb_dma_unmap_single(dev->dev,
885                                      dma_test, b43_txhdr_size(dev),
886                                      DMA_TO_DEVICE);
887         }
888
889         err = alloc_ringmemory(ring);
890         if (err)
891                 goto err_kfree_txhdr_cache;
892         err = dmacontroller_setup(ring);
893         if (err)
894                 goto err_free_ringmemory;
895
896       out:
897         return ring;
898
899       err_free_ringmemory:
900         free_ringmemory(ring);
901       err_kfree_txhdr_cache:
902         kfree(ring->txhdr_cache);
903       err_kfree_meta:
904         kfree(ring->meta);
905       err_kfree_ring:
906         kfree(ring);
907         ring = NULL;
908         goto out;
909 }
910
911 #define divide(a, b)    ({      \
912         typeof(a) __a = a;      \
913         do_div(__a, b);         \
914         __a;                    \
915   })
916
917 #define modulo(a, b)    ({      \
918         typeof(a) __a = a;      \
919         do_div(__a, b);         \
920   })
921
922 /* Main cleanup function. */
923 static void b43_destroy_dmaring(struct b43_dmaring *ring,
924                                 const char *ringname)
925 {
926         if (!ring)
927                 return;
928
929 #ifdef CONFIG_B43_DEBUG
930         {
931                 /* Print some statistics. */
932                 u64 failed_packets = ring->nr_failed_tx_packets;
933                 u64 succeed_packets = ring->nr_succeed_tx_packets;
934                 u64 nr_packets = failed_packets + succeed_packets;
935                 u64 permille_failed = 0, average_tries = 0;
936
937                 if (nr_packets)
938                         permille_failed = divide(failed_packets * 1000, nr_packets);
939                 if (nr_packets)
940                         average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets);
941
942                 b43dbg(ring->dev->wl, "DMA-%u %s: "
943                        "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
944                        "Average tries %llu.%02llu\n",
945                        (unsigned int)(ring->type), ringname,
946                        ring->max_used_slots,
947                        ring->nr_slots,
948                        (unsigned long long)failed_packets,
949                        (unsigned long long)nr_packets,
950                        (unsigned long long)divide(permille_failed, 10),
951                        (unsigned long long)modulo(permille_failed, 10),
952                        (unsigned long long)divide(average_tries, 100),
953                        (unsigned long long)modulo(average_tries, 100));
954         }
955 #endif /* DEBUG */
956
957         /* Device IRQs are disabled prior entering this function,
958          * so no need to take care of concurrency with rx handler stuff.
959          */
960         dmacontroller_cleanup(ring);
961         free_all_descbuffers(ring);
962         free_ringmemory(ring);
963
964         kfree(ring->txhdr_cache);
965         kfree(ring->meta);
966         kfree(ring);
967 }
968
969 #define destroy_ring(dma, ring) do {                            \
970         b43_destroy_dmaring((dma)->ring, __stringify(ring));    \
971         (dma)->ring = NULL;                                     \
972     } while (0)
973
974 void b43_dma_free(struct b43_wldev *dev)
975 {
976         struct b43_dma *dma;
977
978         if (b43_using_pio_transfers(dev))
979                 return;
980         dma = &dev->dma;
981
982         destroy_ring(dma, rx_ring);
983         destroy_ring(dma, tx_ring_AC_BK);
984         destroy_ring(dma, tx_ring_AC_BE);
985         destroy_ring(dma, tx_ring_AC_VI);
986         destroy_ring(dma, tx_ring_AC_VO);
987         destroy_ring(dma, tx_ring_mcast);
988 }
989
990 static int b43_dma_set_mask(struct b43_wldev *dev, u64 mask)
991 {
992         u64 orig_mask = mask;
993         bool fallback = 0;
994         int err;
995
996         /* Try to set the DMA mask. If it fails, try falling back to a
997          * lower mask, as we can always also support a lower one. */
998         while (1) {
999                 err = ssb_dma_set_mask(dev->dev, mask);
1000                 if (!err)
1001                         break;
1002                 if (mask == DMA_64BIT_MASK) {
1003                         mask = DMA_32BIT_MASK;
1004                         fallback = 1;
1005                         continue;
1006                 }
1007                 if (mask == DMA_32BIT_MASK) {
1008                         mask = DMA_30BIT_MASK;
1009                         fallback = 1;
1010                         continue;
1011                 }
1012                 b43err(dev->wl, "The machine/kernel does not support "
1013                        "the required %u-bit DMA mask\n",
1014                        (unsigned int)dma_mask_to_engine_type(orig_mask));
1015                 return -EOPNOTSUPP;
1016         }
1017         if (fallback) {
1018                 b43info(dev->wl, "DMA mask fallback from %u-bit to %u-bit\n",
1019                         (unsigned int)dma_mask_to_engine_type(orig_mask),
1020                         (unsigned int)dma_mask_to_engine_type(mask));
1021         }
1022
1023         return 0;
1024 }
1025
1026 int b43_dma_init(struct b43_wldev *dev)
1027 {
1028         struct b43_dma *dma = &dev->dma;
1029         int err;
1030         u64 dmamask;
1031         enum b43_dmatype type;
1032
1033         dmamask = supported_dma_mask(dev);
1034         type = dma_mask_to_engine_type(dmamask);
1035         err = b43_dma_set_mask(dev, dmamask);
1036         if (err)
1037                 return err;
1038
1039         err = -ENOMEM;
1040         /* setup TX DMA channels. */
1041         dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type);
1042         if (!dma->tx_ring_AC_BK)
1043                 goto out;
1044
1045         dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type);
1046         if (!dma->tx_ring_AC_BE)
1047                 goto err_destroy_bk;
1048
1049         dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type);
1050         if (!dma->tx_ring_AC_VI)
1051                 goto err_destroy_be;
1052
1053         dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type);
1054         if (!dma->tx_ring_AC_VO)
1055                 goto err_destroy_vi;
1056
1057         dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type);
1058         if (!dma->tx_ring_mcast)
1059                 goto err_destroy_vo;
1060
1061         /* setup RX DMA channel. */
1062         dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type);
1063         if (!dma->rx_ring)
1064                 goto err_destroy_mcast;
1065
1066         /* No support for the TX status DMA ring. */
1067         B43_WARN_ON(dev->dev->id.revision < 5);
1068
1069         b43dbg(dev->wl, "%u-bit DMA initialized\n",
1070                (unsigned int)type);
1071         err = 0;
1072 out:
1073         return err;
1074
1075 err_destroy_mcast:
1076         destroy_ring(dma, tx_ring_mcast);
1077 err_destroy_vo:
1078         destroy_ring(dma, tx_ring_AC_VO);
1079 err_destroy_vi:
1080         destroy_ring(dma, tx_ring_AC_VI);
1081 err_destroy_be:
1082         destroy_ring(dma, tx_ring_AC_BE);
1083 err_destroy_bk:
1084         destroy_ring(dma, tx_ring_AC_BK);
1085         return err;
1086 }
1087
1088 /* Generate a cookie for the TX header. */
1089 static u16 generate_cookie(struct b43_dmaring *ring, int slot)
1090 {
1091         u16 cookie;
1092
1093         /* Use the upper 4 bits of the cookie as
1094          * DMA controller ID and store the slot number
1095          * in the lower 12 bits.
1096          * Note that the cookie must never be 0, as this
1097          * is a special value used in RX path.
1098          * It can also not be 0xFFFF because that is special
1099          * for multicast frames.
1100          */
1101         cookie = (((u16)ring->index + 1) << 12);
1102         B43_WARN_ON(slot & ~0x0FFF);
1103         cookie |= (u16)slot;
1104
1105         return cookie;
1106 }
1107
1108 /* Inspect a cookie and find out to which controller/slot it belongs. */
1109 static
1110 struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1111 {
1112         struct b43_dma *dma = &dev->dma;
1113         struct b43_dmaring *ring = NULL;
1114
1115         switch (cookie & 0xF000) {
1116         case 0x1000:
1117                 ring = dma->tx_ring_AC_BK;
1118                 break;
1119         case 0x2000:
1120                 ring = dma->tx_ring_AC_BE;
1121                 break;
1122         case 0x3000:
1123                 ring = dma->tx_ring_AC_VI;
1124                 break;
1125         case 0x4000:
1126                 ring = dma->tx_ring_AC_VO;
1127                 break;
1128         case 0x5000:
1129                 ring = dma->tx_ring_mcast;
1130                 break;
1131         default:
1132                 B43_WARN_ON(1);
1133         }
1134         *slot = (cookie & 0x0FFF);
1135         B43_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots));
1136
1137         return ring;
1138 }
1139
1140 static int dma_tx_fragment(struct b43_dmaring *ring,
1141                            struct sk_buff *skb)
1142 {
1143         const struct b43_dma_ops *ops = ring->ops;
1144         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1145         u8 *header;
1146         int slot, old_top_slot, old_used_slots;
1147         int err;
1148         struct b43_dmadesc_generic *desc;
1149         struct b43_dmadesc_meta *meta;
1150         struct b43_dmadesc_meta *meta_hdr;
1151         struct sk_buff *bounce_skb;
1152         u16 cookie;
1153         size_t hdrsize = b43_txhdr_size(ring->dev);
1154
1155         /* Important note: If the number of used DMA slots per TX frame
1156          * is changed here, the TX_SLOTS_PER_FRAME definition at the top of
1157          * the file has to be updated, too!
1158          */
1159
1160         old_top_slot = ring->current_slot;
1161         old_used_slots = ring->used_slots;
1162
1163         /* Get a slot for the header. */
1164         slot = request_slot(ring);
1165         desc = ops->idx2desc(ring, slot, &meta_hdr);
1166         memset(meta_hdr, 0, sizeof(*meta_hdr));
1167
1168         header = &(ring->txhdr_cache[(slot / TX_SLOTS_PER_FRAME) * hdrsize]);
1169         cookie = generate_cookie(ring, slot);
1170         err = b43_generate_txhdr(ring->dev, header,
1171                                  skb->data, skb->len, info, cookie);
1172         if (unlikely(err)) {
1173                 ring->current_slot = old_top_slot;
1174                 ring->used_slots = old_used_slots;
1175                 return err;
1176         }
1177
1178         meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1179                                            hdrsize, 1);
1180         if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) {
1181                 ring->current_slot = old_top_slot;
1182                 ring->used_slots = old_used_slots;
1183                 return -EIO;
1184         }
1185         ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1186                              hdrsize, 1, 0, 0);
1187
1188         /* Get a slot for the payload. */
1189         slot = request_slot(ring);
1190         desc = ops->idx2desc(ring, slot, &meta);
1191         memset(meta, 0, sizeof(*meta));
1192
1193         meta->skb = skb;
1194         meta->is_last_fragment = 1;
1195
1196         meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1197         /* create a bounce buffer in zone_dma on mapping failure. */
1198         if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1199                 bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
1200                 if (!bounce_skb) {
1201                         ring->current_slot = old_top_slot;
1202                         ring->used_slots = old_used_slots;
1203                         err = -ENOMEM;
1204                         goto out_unmap_hdr;
1205                 }
1206
1207                 memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
1208                 dev_kfree_skb_any(skb);
1209                 skb = bounce_skb;
1210                 meta->skb = skb;
1211                 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1212                 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1213                         ring->current_slot = old_top_slot;
1214                         ring->used_slots = old_used_slots;
1215                         err = -EIO;
1216                         goto out_free_bounce;
1217                 }
1218         }
1219
1220         ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1221
1222         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1223                 /* Tell the firmware about the cookie of the last
1224                  * mcast frame, so it can clear the more-data bit in it. */
1225                 b43_shm_write16(ring->dev, B43_SHM_SHARED,
1226                                 B43_SHM_SH_MCASTCOOKIE, cookie);
1227         }
1228         /* Now transfer the whole frame. */
1229         wmb();
1230         ops->poke_tx(ring, next_slot(ring, slot));
1231         return 0;
1232
1233 out_free_bounce:
1234         dev_kfree_skb_any(skb);
1235 out_unmap_hdr:
1236         unmap_descbuffer(ring, meta_hdr->dmaaddr,
1237                          hdrsize, 1);
1238         return err;
1239 }
1240
1241 static inline int should_inject_overflow(struct b43_dmaring *ring)
1242 {
1243 #ifdef CONFIG_B43_DEBUG
1244         if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
1245                 /* Check if we should inject another ringbuffer overflow
1246                  * to test handling of this situation in the stack. */
1247                 unsigned long next_overflow;
1248
1249                 next_overflow = ring->last_injected_overflow + HZ;
1250                 if (time_after(jiffies, next_overflow)) {
1251                         ring->last_injected_overflow = jiffies;
1252                         b43dbg(ring->dev->wl,
1253                                "Injecting TX ring overflow on "
1254                                "DMA controller %d\n", ring->index);
1255                         return 1;
1256                 }
1257         }
1258 #endif /* CONFIG_B43_DEBUG */
1259         return 0;
1260 }
1261
1262 /* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
1263 static struct b43_dmaring *select_ring_by_priority(struct b43_wldev *dev,
1264                                                    u8 queue_prio)
1265 {
1266         struct b43_dmaring *ring;
1267
1268         if (b43_modparam_qos) {
1269                 /* 0 = highest priority */
1270                 switch (queue_prio) {
1271                 default:
1272                         B43_WARN_ON(1);
1273                         /* fallthrough */
1274                 case 0:
1275                         ring = dev->dma.tx_ring_AC_VO;
1276                         break;
1277                 case 1:
1278                         ring = dev->dma.tx_ring_AC_VI;
1279                         break;
1280                 case 2:
1281                         ring = dev->dma.tx_ring_AC_BE;
1282                         break;
1283                 case 3:
1284                         ring = dev->dma.tx_ring_AC_BK;
1285                         break;
1286                 }
1287         } else
1288                 ring = dev->dma.tx_ring_AC_BE;
1289
1290         return ring;
1291 }
1292
1293 int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb)
1294 {
1295         struct b43_dmaring *ring;
1296         struct ieee80211_hdr *hdr;
1297         int err = 0;
1298         unsigned long flags;
1299         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1300
1301         hdr = (struct ieee80211_hdr *)skb->data;
1302         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1303                 /* The multicast ring will be sent after the DTIM */
1304                 ring = dev->dma.tx_ring_mcast;
1305                 /* Set the more-data bit. Ucode will clear it on
1306                  * the last frame for us. */
1307                 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1308         } else {
1309                 /* Decide by priority where to put this frame. */
1310                 ring = select_ring_by_priority(
1311                         dev, skb_get_queue_mapping(skb));
1312         }
1313
1314         spin_lock_irqsave(&ring->lock, flags);
1315
1316         B43_WARN_ON(!ring->tx);
1317         /* Check if the queue was stopped in mac80211,
1318          * but we got called nevertheless.
1319          * That would be a mac80211 bug. */
1320         B43_WARN_ON(ring->stopped);
1321
1322         if (unlikely(free_slots(ring) < TX_SLOTS_PER_FRAME)) {
1323                 b43warn(dev->wl, "DMA queue overflow\n");
1324                 err = -ENOSPC;
1325                 goto out_unlock;
1326         }
1327
1328         /* Assign the queue number to the ring (if not already done before)
1329          * so TX status handling can use it. The queue to ring mapping is
1330          * static, so we don't need to store it per frame. */
1331         ring->queue_prio = skb_get_queue_mapping(skb);
1332
1333         err = dma_tx_fragment(ring, skb);
1334         if (unlikely(err == -ENOKEY)) {
1335                 /* Drop this packet, as we don't have the encryption key
1336                  * anymore and must not transmit it unencrypted. */
1337                 dev_kfree_skb_any(skb);
1338                 err = 0;
1339                 goto out_unlock;
1340         }
1341         if (unlikely(err)) {
1342                 b43err(dev->wl, "DMA tx mapping failure\n");
1343                 goto out_unlock;
1344         }
1345         ring->nr_tx_packets++;
1346         if ((free_slots(ring) < TX_SLOTS_PER_FRAME) ||
1347             should_inject_overflow(ring)) {
1348                 /* This TX ring is full. */
1349                 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
1350                 ring->stopped = 1;
1351                 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1352                         b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
1353                 }
1354         }
1355 out_unlock:
1356         spin_unlock_irqrestore(&ring->lock, flags);
1357
1358         return err;
1359 }
1360
1361 /* Called with IRQs disabled. */
1362 void b43_dma_handle_txstatus(struct b43_wldev *dev,
1363                              const struct b43_txstatus *status)
1364 {
1365         const struct b43_dma_ops *ops;
1366         struct b43_dmaring *ring;
1367         struct b43_dmadesc_generic *desc;
1368         struct b43_dmadesc_meta *meta;
1369         int slot;
1370         bool frame_succeed;
1371
1372         ring = parse_cookie(dev, status->cookie, &slot);
1373         if (unlikely(!ring))
1374                 return;
1375
1376         spin_lock(&ring->lock); /* IRQs are already disabled. */
1377
1378         B43_WARN_ON(!ring->tx);
1379         ops = ring->ops;
1380         while (1) {
1381                 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
1382                 desc = ops->idx2desc(ring, slot, &meta);
1383
1384                 if (meta->skb)
1385                         unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len,
1386                                          1);
1387                 else
1388                         unmap_descbuffer(ring, meta->dmaaddr,
1389                                          b43_txhdr_size(dev), 1);
1390
1391                 if (meta->is_last_fragment) {
1392                         struct ieee80211_tx_info *info;
1393
1394                         BUG_ON(!meta->skb);
1395
1396                         info = IEEE80211_SKB_CB(meta->skb);
1397
1398                         /*
1399                          * Call back to inform the ieee80211 subsystem about
1400                          * the status of the transmission.
1401                          */
1402                         frame_succeed = b43_fill_txstatus_report(dev, info, status);
1403 #ifdef CONFIG_B43_DEBUG
1404                         if (frame_succeed)
1405                                 ring->nr_succeed_tx_packets++;
1406                         else
1407                                 ring->nr_failed_tx_packets++;
1408                         ring->nr_total_packet_tries += status->frame_count;
1409 #endif /* DEBUG */
1410                         ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb);
1411
1412                         /* skb is freed by ieee80211_tx_status_irqsafe() */
1413                         meta->skb = NULL;
1414                 } else {
1415                         /* No need to call free_descriptor_buffer here, as
1416                          * this is only the txhdr, which is not allocated.
1417                          */
1418                         B43_WARN_ON(meta->skb);
1419                 }
1420
1421                 /* Everything unmapped and free'd. So it's not used anymore. */
1422                 ring->used_slots--;
1423
1424                 if (meta->is_last_fragment)
1425                         break;
1426                 slot = next_slot(ring, slot);
1427         }
1428         if (ring->stopped) {
1429                 B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME);
1430                 ieee80211_wake_queue(dev->wl->hw, ring->queue_prio);
1431                 ring->stopped = 0;
1432                 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1433                         b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
1434                 }
1435         }
1436
1437         spin_unlock(&ring->lock);
1438 }
1439
1440 void b43_dma_get_tx_stats(struct b43_wldev *dev,
1441                           struct ieee80211_tx_queue_stats *stats)
1442 {
1443         const int nr_queues = dev->wl->hw->queues;
1444         struct b43_dmaring *ring;
1445         unsigned long flags;
1446         int i;
1447
1448         for (i = 0; i < nr_queues; i++) {
1449                 ring = select_ring_by_priority(dev, i);
1450
1451                 spin_lock_irqsave(&ring->lock, flags);
1452                 stats[i].len = ring->used_slots / TX_SLOTS_PER_FRAME;
1453                 stats[i].limit = ring->nr_slots / TX_SLOTS_PER_FRAME;
1454                 stats[i].count = ring->nr_tx_packets;
1455                 spin_unlock_irqrestore(&ring->lock, flags);
1456         }
1457 }
1458
1459 static void dma_rx(struct b43_dmaring *ring, int *slot)
1460 {
1461         const struct b43_dma_ops *ops = ring->ops;
1462         struct b43_dmadesc_generic *desc;
1463         struct b43_dmadesc_meta *meta;
1464         struct b43_rxhdr_fw4 *rxhdr;
1465         struct sk_buff *skb;
1466         u16 len;
1467         int err;
1468         dma_addr_t dmaaddr;
1469
1470         desc = ops->idx2desc(ring, *slot, &meta);
1471
1472         sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1473         skb = meta->skb;
1474
1475         rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
1476         len = le16_to_cpu(rxhdr->frame_len);
1477         if (len == 0) {
1478                 int i = 0;
1479
1480                 do {
1481                         udelay(2);
1482                         barrier();
1483                         len = le16_to_cpu(rxhdr->frame_len);
1484                 } while (len == 0 && i++ < 5);
1485                 if (unlikely(len == 0)) {
1486                         /* recycle the descriptor buffer. */
1487                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1488                                                    ring->rx_buffersize);
1489                         goto drop;
1490                 }
1491         }
1492         if (unlikely(len > ring->rx_buffersize)) {
1493                 /* The data did not fit into one descriptor buffer
1494                  * and is split over multiple buffers.
1495                  * This should never happen, as we try to allocate buffers
1496                  * big enough. So simply ignore this packet.
1497                  */
1498                 int cnt = 0;
1499                 s32 tmp = len;
1500
1501                 while (1) {
1502                         desc = ops->idx2desc(ring, *slot, &meta);
1503                         /* recycle the descriptor buffer. */
1504                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1505                                                    ring->rx_buffersize);
1506                         *slot = next_slot(ring, *slot);
1507                         cnt++;
1508                         tmp -= ring->rx_buffersize;
1509                         if (tmp <= 0)
1510                                 break;
1511                 }
1512                 b43err(ring->dev->wl, "DMA RX buffer too small "
1513                        "(len: %u, buffer: %u, nr-dropped: %d)\n",
1514                        len, ring->rx_buffersize, cnt);
1515                 goto drop;
1516         }
1517
1518         dmaaddr = meta->dmaaddr;
1519         err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1520         if (unlikely(err)) {
1521                 b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
1522                 sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
1523                 goto drop;
1524         }
1525
1526         unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1527         skb_put(skb, len + ring->frameoffset);
1528         skb_pull(skb, ring->frameoffset);
1529
1530         b43_rx(ring->dev, skb, rxhdr);
1531 drop:
1532         return;
1533 }
1534
1535 void b43_dma_rx(struct b43_dmaring *ring)
1536 {
1537         const struct b43_dma_ops *ops = ring->ops;
1538         int slot, current_slot;
1539         int used_slots = 0;
1540
1541         B43_WARN_ON(ring->tx);
1542         current_slot = ops->get_current_rxslot(ring);
1543         B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
1544
1545         slot = ring->current_slot;
1546         for (; slot != current_slot; slot = next_slot(ring, slot)) {
1547                 dma_rx(ring, &slot);
1548                 update_max_used_slots(ring, ++used_slots);
1549         }
1550         ops->set_current_rxslot(ring, slot);
1551         ring->current_slot = slot;
1552 }
1553
1554 static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
1555 {
1556         unsigned long flags;
1557
1558         spin_lock_irqsave(&ring->lock, flags);
1559         B43_WARN_ON(!ring->tx);
1560         ring->ops->tx_suspend(ring);
1561         spin_unlock_irqrestore(&ring->lock, flags);
1562 }
1563
1564 static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
1565 {
1566         unsigned long flags;
1567
1568         spin_lock_irqsave(&ring->lock, flags);
1569         B43_WARN_ON(!ring->tx);
1570         ring->ops->tx_resume(ring);
1571         spin_unlock_irqrestore(&ring->lock, flags);
1572 }
1573
1574 void b43_dma_tx_suspend(struct b43_wldev *dev)
1575 {
1576         b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
1577         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK);
1578         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE);
1579         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI);
1580         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO);
1581         b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast);
1582 }
1583
1584 void b43_dma_tx_resume(struct b43_wldev *dev)
1585 {
1586         b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast);
1587         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO);
1588         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI);
1589         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE);
1590         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK);
1591         b43_power_saving_ctl_bits(dev, 0);
1592 }
1593
1594 #ifdef CONFIG_B43_PIO
1595 static void direct_fifo_rx(struct b43_wldev *dev, enum b43_dmatype type,
1596                            u16 mmio_base, bool enable)
1597 {
1598         u32 ctl;
1599
1600         if (type == B43_DMA_64BIT) {
1601                 ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL);
1602                 ctl &= ~B43_DMA64_RXDIRECTFIFO;
1603                 if (enable)
1604                         ctl |= B43_DMA64_RXDIRECTFIFO;
1605                 b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl);
1606         } else {
1607                 ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL);
1608                 ctl &= ~B43_DMA32_RXDIRECTFIFO;
1609                 if (enable)
1610                         ctl |= B43_DMA32_RXDIRECTFIFO;
1611                 b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl);
1612         }
1613 }
1614
1615 /* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine.
1616  * This is called from PIO code, so DMA structures are not available. */
1617 void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
1618                             unsigned int engine_index, bool enable)
1619 {
1620         enum b43_dmatype type;
1621         u16 mmio_base;
1622
1623         type = dma_mask_to_engine_type(supported_dma_mask(dev));
1624
1625         mmio_base = b43_dmacontroller_base(type, engine_index);
1626         direct_fifo_rx(dev, type, mmio_base, enable);
1627 }
1628 #endif /* CONFIG_B43_PIO */