d8e829f6fcb2b8a5049a257b5b679cb861f64617
[linux-3.10.git] / drivers / net / tg3.h
1 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2  * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  */
8
9 #ifndef _T3_H
10 #define _T3_H
11
12 #define TG3_64BIT_REG_HIGH              0x00UL
13 #define TG3_64BIT_REG_LOW               0x04UL
14
15 /* Descriptor block info. */
16 #define TG3_BDINFO_HOST_ADDR            0x0UL /* 64-bit */
17 #define TG3_BDINFO_MAXLEN_FLAGS         0x8UL /* 32-bit */
18 #define  BDINFO_FLAGS_USE_EXT_RECV       0x00000001 /* ext rx_buffer_desc */
19 #define  BDINFO_FLAGS_DISABLED           0x00000002
20 #define  BDINFO_FLAGS_MAXLEN_MASK        0xffff0000
21 #define  BDINFO_FLAGS_MAXLEN_SHIFT       16
22 #define TG3_BDINFO_NIC_ADDR             0xcUL /* 32-bit */
23 #define TG3_BDINFO_SIZE                 0x10UL
24
25 #define RX_COPY_THRESHOLD               256
26
27 #define TG3_RX_INTERNAL_RING_SZ_5906    32
28
29 #define RX_STD_MAX_SIZE                 1536
30 #define RX_STD_MAX_SIZE_5705            512
31 #define RX_JUMBO_MAX_SIZE               0xdeadbeef /* XXX */
32
33 /* First 256 bytes are a mirror of PCI config space. */
34 #define TG3PCI_VENDOR                   0x00000000
35 #define  TG3PCI_VENDOR_BROADCOM          0x14e4
36 #define TG3PCI_DEVICE                   0x00000002
37 #define  TG3PCI_DEVICE_TIGON3_1          0x1644 /* BCM5700 */
38 #define  TG3PCI_DEVICE_TIGON3_2          0x1645 /* BCM5701 */
39 #define  TG3PCI_DEVICE_TIGON3_3          0x1646 /* BCM5702 */
40 #define  TG3PCI_DEVICE_TIGON3_4          0x1647 /* BCM5703 */
41 #define TG3PCI_COMMAND                  0x00000004
42 #define TG3PCI_STATUS                   0x00000006
43 #define TG3PCI_CCREVID                  0x00000008
44 #define TG3PCI_CACHELINESZ              0x0000000c
45 #define TG3PCI_LATTIMER                 0x0000000d
46 #define TG3PCI_HEADERTYPE               0x0000000e
47 #define TG3PCI_BIST                     0x0000000f
48 #define TG3PCI_BASE0_LOW                0x00000010
49 #define TG3PCI_BASE0_HIGH               0x00000014
50 /* 0x18 --> 0x2c unused */
51 #define TG3PCI_SUBSYSVENID              0x0000002c
52 #define TG3PCI_SUBSYSID                 0x0000002e
53 #define TG3PCI_ROMADDR                  0x00000030
54 #define TG3PCI_CAPLIST                  0x00000034
55 /* 0x35 --> 0x3c unused */
56 #define TG3PCI_IRQ_LINE                 0x0000003c
57 #define TG3PCI_IRQ_PIN                  0x0000003d
58 #define TG3PCI_MIN_GNT                  0x0000003e
59 #define TG3PCI_MAX_LAT                  0x0000003f
60 /* 0x40 --> 0x64 unused */
61 #define TG3PCI_MSI_DATA                 0x00000064
62 /* 0x66 --> 0x68 unused */
63 #define TG3PCI_MISC_HOST_CTRL           0x00000068
64 #define  MISC_HOST_CTRL_CLEAR_INT        0x00000001
65 #define  MISC_HOST_CTRL_MASK_PCI_INT     0x00000002
66 #define  MISC_HOST_CTRL_BYTE_SWAP        0x00000004
67 #define  MISC_HOST_CTRL_WORD_SWAP        0x00000008
68 #define  MISC_HOST_CTRL_PCISTATE_RW      0x00000010
69 #define  MISC_HOST_CTRL_CLKREG_RW        0x00000020
70 #define  MISC_HOST_CTRL_REGWORD_SWAP     0x00000040
71 #define  MISC_HOST_CTRL_INDIR_ACCESS     0x00000080
72 #define  MISC_HOST_CTRL_IRQ_MASK_MODE    0x00000100
73 #define  MISC_HOST_CTRL_TAGGED_STATUS    0x00000200
74 #define  MISC_HOST_CTRL_CHIPREV          0xffff0000
75 #define  MISC_HOST_CTRL_CHIPREV_SHIFT    16
76 #define  GET_CHIP_REV_ID(MISC_HOST_CTRL) \
77          (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
78           MISC_HOST_CTRL_CHIPREV_SHIFT)
79 #define  CHIPREV_ID_5700_A0              0x7000
80 #define  CHIPREV_ID_5700_A1              0x7001
81 #define  CHIPREV_ID_5700_B0              0x7100
82 #define  CHIPREV_ID_5700_B1              0x7101
83 #define  CHIPREV_ID_5700_B3              0x7102
84 #define  CHIPREV_ID_5700_ALTIMA          0x7104
85 #define  CHIPREV_ID_5700_C0              0x7200
86 #define  CHIPREV_ID_5701_A0              0x0000
87 #define  CHIPREV_ID_5701_B0              0x0100
88 #define  CHIPREV_ID_5701_B2              0x0102
89 #define  CHIPREV_ID_5701_B5              0x0105
90 #define  CHIPREV_ID_5703_A0              0x1000
91 #define  CHIPREV_ID_5703_A1              0x1001
92 #define  CHIPREV_ID_5703_A2              0x1002
93 #define  CHIPREV_ID_5703_A3              0x1003
94 #define  CHIPREV_ID_5704_A0              0x2000
95 #define  CHIPREV_ID_5704_A1              0x2001
96 #define  CHIPREV_ID_5704_A2              0x2002
97 #define  CHIPREV_ID_5704_A3              0x2003
98 #define  CHIPREV_ID_5705_A0              0x3000
99 #define  CHIPREV_ID_5705_A1              0x3001
100 #define  CHIPREV_ID_5705_A2              0x3002
101 #define  CHIPREV_ID_5705_A3              0x3003
102 #define  CHIPREV_ID_5750_A0              0x4000
103 #define  CHIPREV_ID_5750_A1              0x4001
104 #define  CHIPREV_ID_5750_A3              0x4003
105 #define  CHIPREV_ID_5750_C2              0x4202
106 #define  CHIPREV_ID_5752_A0_HW           0x5000
107 #define  CHIPREV_ID_5752_A0              0x6000
108 #define  CHIPREV_ID_5752_A1              0x6001
109 #define  CHIPREV_ID_5714_A2              0x9002
110 #define  CHIPREV_ID_5906_A1              0xc001
111 #define  CHIPREV_ID_5784_A0              0x5784000
112 #define  GET_ASIC_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 12)
113 #define   ASIC_REV_5700                  0x07
114 #define   ASIC_REV_5701                  0x00
115 #define   ASIC_REV_5703                  0x01
116 #define   ASIC_REV_5704                  0x02
117 #define   ASIC_REV_5705                  0x03
118 #define   ASIC_REV_5750                  0x04
119 #define   ASIC_REV_5752                  0x06
120 #define   ASIC_REV_5780                  0x08
121 #define   ASIC_REV_5714                  0x09
122 #define   ASIC_REV_5755                  0x0a
123 #define   ASIC_REV_5787                  0x0b
124 #define   ASIC_REV_5906                  0x0c
125 #define   ASIC_REV_USE_PROD_ID_REG       0x0f
126 #define   ASIC_REV_5784                  0x5784
127 #define  GET_CHIP_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 8)
128 #define   CHIPREV_5700_AX                0x70
129 #define   CHIPREV_5700_BX                0x71
130 #define   CHIPREV_5700_CX                0x72
131 #define   CHIPREV_5701_AX                0x00
132 #define   CHIPREV_5703_AX                0x10
133 #define   CHIPREV_5704_AX                0x20
134 #define   CHIPREV_5704_BX                0x21
135 #define   CHIPREV_5750_AX                0x40
136 #define   CHIPREV_5750_BX                0x41
137 #define  GET_METAL_REV(CHIP_REV_ID)     ((CHIP_REV_ID) & 0xff)
138 #define   METAL_REV_A0                   0x00
139 #define   METAL_REV_A1                   0x01
140 #define   METAL_REV_B0                   0x00
141 #define   METAL_REV_B1                   0x01
142 #define   METAL_REV_B2                   0x02
143 #define TG3PCI_DMA_RW_CTRL              0x0000006c
144 #define  DMA_RWCTRL_MIN_DMA              0x000000ff
145 #define  DMA_RWCTRL_MIN_DMA_SHIFT        0
146 #define  DMA_RWCTRL_READ_BNDRY_MASK      0x00000700
147 #define  DMA_RWCTRL_READ_BNDRY_DISAB     0x00000000
148 #define  DMA_RWCTRL_READ_BNDRY_16        0x00000100
149 #define  DMA_RWCTRL_READ_BNDRY_128_PCIX  0x00000100
150 #define  DMA_RWCTRL_READ_BNDRY_32        0x00000200
151 #define  DMA_RWCTRL_READ_BNDRY_256_PCIX  0x00000200
152 #define  DMA_RWCTRL_READ_BNDRY_64        0x00000300
153 #define  DMA_RWCTRL_READ_BNDRY_384_PCIX  0x00000300
154 #define  DMA_RWCTRL_READ_BNDRY_128       0x00000400
155 #define  DMA_RWCTRL_READ_BNDRY_256       0x00000500
156 #define  DMA_RWCTRL_READ_BNDRY_512       0x00000600
157 #define  DMA_RWCTRL_READ_BNDRY_1024      0x00000700
158 #define  DMA_RWCTRL_WRITE_BNDRY_MASK     0x00003800
159 #define  DMA_RWCTRL_WRITE_BNDRY_DISAB    0x00000000
160 #define  DMA_RWCTRL_WRITE_BNDRY_16       0x00000800
161 #define  DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
162 #define  DMA_RWCTRL_WRITE_BNDRY_32       0x00001000
163 #define  DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
164 #define  DMA_RWCTRL_WRITE_BNDRY_64       0x00001800
165 #define  DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
166 #define  DMA_RWCTRL_WRITE_BNDRY_128      0x00002000
167 #define  DMA_RWCTRL_WRITE_BNDRY_256      0x00002800
168 #define  DMA_RWCTRL_WRITE_BNDRY_512      0x00003000
169 #define  DMA_RWCTRL_WRITE_BNDRY_1024     0x00003800
170 #define  DMA_RWCTRL_ONE_DMA              0x00004000
171 #define  DMA_RWCTRL_READ_WATER           0x00070000
172 #define  DMA_RWCTRL_READ_WATER_SHIFT     16
173 #define  DMA_RWCTRL_WRITE_WATER          0x00380000
174 #define  DMA_RWCTRL_WRITE_WATER_SHIFT    19
175 #define  DMA_RWCTRL_USE_MEM_READ_MULT    0x00400000
176 #define  DMA_RWCTRL_ASSERT_ALL_BE        0x00800000
177 #define  DMA_RWCTRL_PCI_READ_CMD         0x0f000000
178 #define  DMA_RWCTRL_PCI_READ_CMD_SHIFT   24
179 #define  DMA_RWCTRL_PCI_WRITE_CMD        0xf0000000
180 #define  DMA_RWCTRL_PCI_WRITE_CMD_SHIFT  28
181 #define  DMA_RWCTRL_WRITE_BNDRY_64_PCIE  0x10000000
182 #define  DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
183 #define  DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
184 #define TG3PCI_PCISTATE                 0x00000070
185 #define  PCISTATE_FORCE_RESET            0x00000001
186 #define  PCISTATE_INT_NOT_ACTIVE         0x00000002
187 #define  PCISTATE_CONV_PCI_MODE          0x00000004
188 #define  PCISTATE_BUS_SPEED_HIGH         0x00000008
189 #define  PCISTATE_BUS_32BIT              0x00000010
190 #define  PCISTATE_ROM_ENABLE             0x00000020
191 #define  PCISTATE_ROM_RETRY_ENABLE       0x00000040
192 #define  PCISTATE_FLAT_VIEW              0x00000100
193 #define  PCISTATE_RETRY_SAME_DMA         0x00002000
194 #define TG3PCI_CLOCK_CTRL               0x00000074
195 #define  CLOCK_CTRL_CORECLK_DISABLE      0x00000200
196 #define  CLOCK_CTRL_RXCLK_DISABLE        0x00000400
197 #define  CLOCK_CTRL_TXCLK_DISABLE        0x00000800
198 #define  CLOCK_CTRL_ALTCLK               0x00001000
199 #define  CLOCK_CTRL_PWRDOWN_PLL133       0x00008000
200 #define  CLOCK_CTRL_44MHZ_CORE           0x00040000
201 #define  CLOCK_CTRL_625_CORE             0x00100000
202 #define  CLOCK_CTRL_FORCE_CLKRUN         0x00200000
203 #define  CLOCK_CTRL_CLKRUN_OENABLE       0x00400000
204 #define  CLOCK_CTRL_DELAY_PCI_GRANT      0x80000000
205 #define TG3PCI_REG_BASE_ADDR            0x00000078
206 #define TG3PCI_MEM_WIN_BASE_ADDR        0x0000007c
207 #define TG3PCI_REG_DATA                 0x00000080
208 #define TG3PCI_MEM_WIN_DATA             0x00000084
209 #define TG3PCI_MODE_CTRL                0x00000088
210 #define TG3PCI_MISC_CFG                 0x0000008c
211 #define TG3PCI_MISC_LOCAL_CTRL          0x00000090
212 /* 0x94 --> 0x98 unused */
213 #define TG3PCI_STD_RING_PROD_IDX        0x00000098 /* 64-bit */
214 #define TG3PCI_RCV_RET_RING_CON_IDX     0x000000a0 /* 64-bit */
215 #define TG3PCI_SND_PROD_IDX             0x000000a8 /* 64-bit */
216 /* 0xb0 --> 0xb8 unused */
217 #define TG3PCI_DUAL_MAC_CTRL            0x000000b8
218 #define  DUAL_MAC_CTRL_CH_MASK           0x00000003
219 #define  DUAL_MAC_CTRL_ID                0x00000004
220 #define TG3PCI_PRODID_ASICREV           0x000000bc
221 #define  PROD_ID_ASIC_REV_MASK           0x0fffffff
222 /* 0xc0 --> 0x100 unused */
223
224 /* 0x100 --> 0x200 unused */
225
226 /* Mailbox registers */
227 #define MAILBOX_INTERRUPT_0             0x00000200 /* 64-bit */
228 #define MAILBOX_INTERRUPT_1             0x00000208 /* 64-bit */
229 #define MAILBOX_INTERRUPT_2             0x00000210 /* 64-bit */
230 #define MAILBOX_INTERRUPT_3             0x00000218 /* 64-bit */
231 #define MAILBOX_GENERAL_0               0x00000220 /* 64-bit */
232 #define MAILBOX_GENERAL_1               0x00000228 /* 64-bit */
233 #define MAILBOX_GENERAL_2               0x00000230 /* 64-bit */
234 #define MAILBOX_GENERAL_3               0x00000238 /* 64-bit */
235 #define MAILBOX_GENERAL_4               0x00000240 /* 64-bit */
236 #define MAILBOX_GENERAL_5               0x00000248 /* 64-bit */
237 #define MAILBOX_GENERAL_6               0x00000250 /* 64-bit */
238 #define MAILBOX_GENERAL_7               0x00000258 /* 64-bit */
239 #define MAILBOX_RELOAD_STAT             0x00000260 /* 64-bit */
240 #define MAILBOX_RCV_STD_PROD_IDX        0x00000268 /* 64-bit */
241 #define MAILBOX_RCV_JUMBO_PROD_IDX      0x00000270 /* 64-bit */
242 #define MAILBOX_RCV_MINI_PROD_IDX       0x00000278 /* 64-bit */
243 #define MAILBOX_RCVRET_CON_IDX_0        0x00000280 /* 64-bit */
244 #define MAILBOX_RCVRET_CON_IDX_1        0x00000288 /* 64-bit */
245 #define MAILBOX_RCVRET_CON_IDX_2        0x00000290 /* 64-bit */
246 #define MAILBOX_RCVRET_CON_IDX_3        0x00000298 /* 64-bit */
247 #define MAILBOX_RCVRET_CON_IDX_4        0x000002a0 /* 64-bit */
248 #define MAILBOX_RCVRET_CON_IDX_5        0x000002a8 /* 64-bit */
249 #define MAILBOX_RCVRET_CON_IDX_6        0x000002b0 /* 64-bit */
250 #define MAILBOX_RCVRET_CON_IDX_7        0x000002b8 /* 64-bit */
251 #define MAILBOX_RCVRET_CON_IDX_8        0x000002c0 /* 64-bit */
252 #define MAILBOX_RCVRET_CON_IDX_9        0x000002c8 /* 64-bit */
253 #define MAILBOX_RCVRET_CON_IDX_10       0x000002d0 /* 64-bit */
254 #define MAILBOX_RCVRET_CON_IDX_11       0x000002d8 /* 64-bit */
255 #define MAILBOX_RCVRET_CON_IDX_12       0x000002e0 /* 64-bit */
256 #define MAILBOX_RCVRET_CON_IDX_13       0x000002e8 /* 64-bit */
257 #define MAILBOX_RCVRET_CON_IDX_14       0x000002f0 /* 64-bit */
258 #define MAILBOX_RCVRET_CON_IDX_15       0x000002f8 /* 64-bit */
259 #define MAILBOX_SNDHOST_PROD_IDX_0      0x00000300 /* 64-bit */
260 #define MAILBOX_SNDHOST_PROD_IDX_1      0x00000308 /* 64-bit */
261 #define MAILBOX_SNDHOST_PROD_IDX_2      0x00000310 /* 64-bit */
262 #define MAILBOX_SNDHOST_PROD_IDX_3      0x00000318 /* 64-bit */
263 #define MAILBOX_SNDHOST_PROD_IDX_4      0x00000320 /* 64-bit */
264 #define MAILBOX_SNDHOST_PROD_IDX_5      0x00000328 /* 64-bit */
265 #define MAILBOX_SNDHOST_PROD_IDX_6      0x00000330 /* 64-bit */
266 #define MAILBOX_SNDHOST_PROD_IDX_7      0x00000338 /* 64-bit */
267 #define MAILBOX_SNDHOST_PROD_IDX_8      0x00000340 /* 64-bit */
268 #define MAILBOX_SNDHOST_PROD_IDX_9      0x00000348 /* 64-bit */
269 #define MAILBOX_SNDHOST_PROD_IDX_10     0x00000350 /* 64-bit */
270 #define MAILBOX_SNDHOST_PROD_IDX_11     0x00000358 /* 64-bit */
271 #define MAILBOX_SNDHOST_PROD_IDX_12     0x00000360 /* 64-bit */
272 #define MAILBOX_SNDHOST_PROD_IDX_13     0x00000368 /* 64-bit */
273 #define MAILBOX_SNDHOST_PROD_IDX_14     0x00000370 /* 64-bit */
274 #define MAILBOX_SNDHOST_PROD_IDX_15     0x00000378 /* 64-bit */
275 #define MAILBOX_SNDNIC_PROD_IDX_0       0x00000380 /* 64-bit */
276 #define MAILBOX_SNDNIC_PROD_IDX_1       0x00000388 /* 64-bit */
277 #define MAILBOX_SNDNIC_PROD_IDX_2       0x00000390 /* 64-bit */
278 #define MAILBOX_SNDNIC_PROD_IDX_3       0x00000398 /* 64-bit */
279 #define MAILBOX_SNDNIC_PROD_IDX_4       0x000003a0 /* 64-bit */
280 #define MAILBOX_SNDNIC_PROD_IDX_5       0x000003a8 /* 64-bit */
281 #define MAILBOX_SNDNIC_PROD_IDX_6       0x000003b0 /* 64-bit */
282 #define MAILBOX_SNDNIC_PROD_IDX_7       0x000003b8 /* 64-bit */
283 #define MAILBOX_SNDNIC_PROD_IDX_8       0x000003c0 /* 64-bit */
284 #define MAILBOX_SNDNIC_PROD_IDX_9       0x000003c8 /* 64-bit */
285 #define MAILBOX_SNDNIC_PROD_IDX_10      0x000003d0 /* 64-bit */
286 #define MAILBOX_SNDNIC_PROD_IDX_11      0x000003d8 /* 64-bit */
287 #define MAILBOX_SNDNIC_PROD_IDX_12      0x000003e0 /* 64-bit */
288 #define MAILBOX_SNDNIC_PROD_IDX_13      0x000003e8 /* 64-bit */
289 #define MAILBOX_SNDNIC_PROD_IDX_14      0x000003f0 /* 64-bit */
290 #define MAILBOX_SNDNIC_PROD_IDX_15      0x000003f8 /* 64-bit */
291
292 /* MAC control registers */
293 #define MAC_MODE                        0x00000400
294 #define  MAC_MODE_RESET                  0x00000001
295 #define  MAC_MODE_HALF_DUPLEX            0x00000002
296 #define  MAC_MODE_PORT_MODE_MASK         0x0000000c
297 #define  MAC_MODE_PORT_MODE_TBI          0x0000000c
298 #define  MAC_MODE_PORT_MODE_GMII         0x00000008
299 #define  MAC_MODE_PORT_MODE_MII          0x00000004
300 #define  MAC_MODE_PORT_MODE_NONE         0x00000000
301 #define  MAC_MODE_PORT_INT_LPBACK        0x00000010
302 #define  MAC_MODE_TAGGED_MAC_CTRL        0x00000080
303 #define  MAC_MODE_TX_BURSTING            0x00000100
304 #define  MAC_MODE_MAX_DEFER              0x00000200
305 #define  MAC_MODE_LINK_POLARITY          0x00000400
306 #define  MAC_MODE_RXSTAT_ENABLE          0x00000800
307 #define  MAC_MODE_RXSTAT_CLEAR           0x00001000
308 #define  MAC_MODE_RXSTAT_FLUSH           0x00002000
309 #define  MAC_MODE_TXSTAT_ENABLE          0x00004000
310 #define  MAC_MODE_TXSTAT_CLEAR           0x00008000
311 #define  MAC_MODE_TXSTAT_FLUSH           0x00010000
312 #define  MAC_MODE_SEND_CONFIGS           0x00020000
313 #define  MAC_MODE_MAGIC_PKT_ENABLE       0x00040000
314 #define  MAC_MODE_ACPI_ENABLE            0x00080000
315 #define  MAC_MODE_MIP_ENABLE             0x00100000
316 #define  MAC_MODE_TDE_ENABLE             0x00200000
317 #define  MAC_MODE_RDE_ENABLE             0x00400000
318 #define  MAC_MODE_FHDE_ENABLE            0x00800000
319 #define MAC_STATUS                      0x00000404
320 #define  MAC_STATUS_PCS_SYNCED           0x00000001
321 #define  MAC_STATUS_SIGNAL_DET           0x00000002
322 #define  MAC_STATUS_RCVD_CFG             0x00000004
323 #define  MAC_STATUS_CFG_CHANGED          0x00000008
324 #define  MAC_STATUS_SYNC_CHANGED         0x00000010
325 #define  MAC_STATUS_PORT_DEC_ERR         0x00000400
326 #define  MAC_STATUS_LNKSTATE_CHANGED     0x00001000
327 #define  MAC_STATUS_MI_COMPLETION        0x00400000
328 #define  MAC_STATUS_MI_INTERRUPT         0x00800000
329 #define  MAC_STATUS_AP_ERROR             0x01000000
330 #define  MAC_STATUS_ODI_ERROR            0x02000000
331 #define  MAC_STATUS_RXSTAT_OVERRUN       0x04000000
332 #define  MAC_STATUS_TXSTAT_OVERRUN       0x08000000
333 #define MAC_EVENT                       0x00000408
334 #define  MAC_EVENT_PORT_DECODE_ERR       0x00000400
335 #define  MAC_EVENT_LNKSTATE_CHANGED      0x00001000
336 #define  MAC_EVENT_MI_COMPLETION         0x00400000
337 #define  MAC_EVENT_MI_INTERRUPT          0x00800000
338 #define  MAC_EVENT_AP_ERROR              0x01000000
339 #define  MAC_EVENT_ODI_ERROR             0x02000000
340 #define  MAC_EVENT_RXSTAT_OVERRUN        0x04000000
341 #define  MAC_EVENT_TXSTAT_OVERRUN        0x08000000
342 #define MAC_LED_CTRL                    0x0000040c
343 #define  LED_CTRL_LNKLED_OVERRIDE        0x00000001
344 #define  LED_CTRL_1000MBPS_ON            0x00000002
345 #define  LED_CTRL_100MBPS_ON             0x00000004
346 #define  LED_CTRL_10MBPS_ON              0x00000008
347 #define  LED_CTRL_TRAFFIC_OVERRIDE       0x00000010
348 #define  LED_CTRL_TRAFFIC_BLINK          0x00000020
349 #define  LED_CTRL_TRAFFIC_LED            0x00000040
350 #define  LED_CTRL_1000MBPS_STATUS        0x00000080
351 #define  LED_CTRL_100MBPS_STATUS         0x00000100
352 #define  LED_CTRL_10MBPS_STATUS          0x00000200
353 #define  LED_CTRL_TRAFFIC_STATUS         0x00000400
354 #define  LED_CTRL_MODE_MAC               0x00000000
355 #define  LED_CTRL_MODE_PHY_1             0x00000800
356 #define  LED_CTRL_MODE_PHY_2             0x00001000
357 #define  LED_CTRL_MODE_SHASTA_MAC        0x00002000
358 #define  LED_CTRL_MODE_SHARED            0x00004000
359 #define  LED_CTRL_MODE_COMBO             0x00008000
360 #define  LED_CTRL_BLINK_RATE_MASK        0x7ff80000
361 #define  LED_CTRL_BLINK_RATE_SHIFT       19
362 #define  LED_CTRL_BLINK_PER_OVERRIDE     0x00080000
363 #define  LED_CTRL_BLINK_RATE_OVERRIDE    0x80000000
364 #define MAC_ADDR_0_HIGH                 0x00000410 /* upper 2 bytes */
365 #define MAC_ADDR_0_LOW                  0x00000414 /* lower 4 bytes */
366 #define MAC_ADDR_1_HIGH                 0x00000418 /* upper 2 bytes */
367 #define MAC_ADDR_1_LOW                  0x0000041c /* lower 4 bytes */
368 #define MAC_ADDR_2_HIGH                 0x00000420 /* upper 2 bytes */
369 #define MAC_ADDR_2_LOW                  0x00000424 /* lower 4 bytes */
370 #define MAC_ADDR_3_HIGH                 0x00000428 /* upper 2 bytes */
371 #define MAC_ADDR_3_LOW                  0x0000042c /* lower 4 bytes */
372 #define MAC_ACPI_MBUF_PTR               0x00000430
373 #define MAC_ACPI_LEN_OFFSET             0x00000434
374 #define  ACPI_LENOFF_LEN_MASK            0x0000ffff
375 #define  ACPI_LENOFF_LEN_SHIFT           0
376 #define  ACPI_LENOFF_OFF_MASK            0x0fff0000
377 #define  ACPI_LENOFF_OFF_SHIFT           16
378 #define MAC_TX_BACKOFF_SEED             0x00000438
379 #define  TX_BACKOFF_SEED_MASK            0x000003ff
380 #define MAC_RX_MTU_SIZE                 0x0000043c
381 #define  RX_MTU_SIZE_MASK                0x0000ffff
382 #define MAC_PCS_TEST                    0x00000440
383 #define  PCS_TEST_PATTERN_MASK           0x000fffff
384 #define  PCS_TEST_PATTERN_SHIFT          0
385 #define  PCS_TEST_ENABLE                 0x00100000
386 #define MAC_TX_AUTO_NEG                 0x00000444
387 #define  TX_AUTO_NEG_MASK                0x0000ffff
388 #define  TX_AUTO_NEG_SHIFT               0
389 #define MAC_RX_AUTO_NEG                 0x00000448
390 #define  RX_AUTO_NEG_MASK                0x0000ffff
391 #define  RX_AUTO_NEG_SHIFT               0
392 #define MAC_MI_COM                      0x0000044c
393 #define  MI_COM_CMD_MASK                 0x0c000000
394 #define  MI_COM_CMD_WRITE                0x04000000
395 #define  MI_COM_CMD_READ                 0x08000000
396 #define  MI_COM_READ_FAILED              0x10000000
397 #define  MI_COM_START                    0x20000000
398 #define  MI_COM_BUSY                     0x20000000
399 #define  MI_COM_PHY_ADDR_MASK            0x03e00000
400 #define  MI_COM_PHY_ADDR_SHIFT           21
401 #define  MI_COM_REG_ADDR_MASK            0x001f0000
402 #define  MI_COM_REG_ADDR_SHIFT           16
403 #define  MI_COM_DATA_MASK                0x0000ffff
404 #define MAC_MI_STAT                     0x00000450
405 #define  MAC_MI_STAT_LNKSTAT_ATTN_ENAB   0x00000001
406 #define MAC_MI_MODE                     0x00000454
407 #define  MAC_MI_MODE_CLK_10MHZ           0x00000001
408 #define  MAC_MI_MODE_SHORT_PREAMBLE      0x00000002
409 #define  MAC_MI_MODE_AUTO_POLL           0x00000010
410 #define  MAC_MI_MODE_CORE_CLK_62MHZ      0x00008000
411 #define  MAC_MI_MODE_BASE                0x000c0000 /* XXX magic values XXX */
412 #define MAC_AUTO_POLL_STATUS            0x00000458
413 #define  MAC_AUTO_POLL_ERROR             0x00000001
414 #define MAC_TX_MODE                     0x0000045c
415 #define  TX_MODE_RESET                   0x00000001
416 #define  TX_MODE_ENABLE                  0x00000002
417 #define  TX_MODE_FLOW_CTRL_ENABLE        0x00000010
418 #define  TX_MODE_BIG_BCKOFF_ENABLE       0x00000020
419 #define  TX_MODE_LONG_PAUSE_ENABLE       0x00000040
420 #define MAC_TX_STATUS                   0x00000460
421 #define  TX_STATUS_XOFFED                0x00000001
422 #define  TX_STATUS_SENT_XOFF             0x00000002
423 #define  TX_STATUS_SENT_XON              0x00000004
424 #define  TX_STATUS_LINK_UP               0x00000008
425 #define  TX_STATUS_ODI_UNDERRUN          0x00000010
426 #define  TX_STATUS_ODI_OVERRUN           0x00000020
427 #define MAC_TX_LENGTHS                  0x00000464
428 #define  TX_LENGTHS_SLOT_TIME_MASK       0x000000ff
429 #define  TX_LENGTHS_SLOT_TIME_SHIFT      0
430 #define  TX_LENGTHS_IPG_MASK             0x00000f00
431 #define  TX_LENGTHS_IPG_SHIFT            8
432 #define  TX_LENGTHS_IPG_CRS_MASK         0x00003000
433 #define  TX_LENGTHS_IPG_CRS_SHIFT        12
434 #define MAC_RX_MODE                     0x00000468
435 #define  RX_MODE_RESET                   0x00000001
436 #define  RX_MODE_ENABLE                  0x00000002
437 #define  RX_MODE_FLOW_CTRL_ENABLE        0x00000004
438 #define  RX_MODE_KEEP_MAC_CTRL           0x00000008
439 #define  RX_MODE_KEEP_PAUSE              0x00000010
440 #define  RX_MODE_ACCEPT_OVERSIZED        0x00000020
441 #define  RX_MODE_ACCEPT_RUNTS            0x00000040
442 #define  RX_MODE_LEN_CHECK               0x00000080
443 #define  RX_MODE_PROMISC                 0x00000100
444 #define  RX_MODE_NO_CRC_CHECK            0x00000200
445 #define  RX_MODE_KEEP_VLAN_TAG           0x00000400
446 #define  RX_MODE_IPV6_CSUM_ENABLE        0x01000000
447 #define MAC_RX_STATUS                   0x0000046c
448 #define  RX_STATUS_REMOTE_TX_XOFFED      0x00000001
449 #define  RX_STATUS_XOFF_RCVD             0x00000002
450 #define  RX_STATUS_XON_RCVD              0x00000004
451 #define MAC_HASH_REG_0                  0x00000470
452 #define MAC_HASH_REG_1                  0x00000474
453 #define MAC_HASH_REG_2                  0x00000478
454 #define MAC_HASH_REG_3                  0x0000047c
455 #define MAC_RCV_RULE_0                  0x00000480
456 #define MAC_RCV_VALUE_0                 0x00000484
457 #define MAC_RCV_RULE_1                  0x00000488
458 #define MAC_RCV_VALUE_1                 0x0000048c
459 #define MAC_RCV_RULE_2                  0x00000490
460 #define MAC_RCV_VALUE_2                 0x00000494
461 #define MAC_RCV_RULE_3                  0x00000498
462 #define MAC_RCV_VALUE_3                 0x0000049c
463 #define MAC_RCV_RULE_4                  0x000004a0
464 #define MAC_RCV_VALUE_4                 0x000004a4
465 #define MAC_RCV_RULE_5                  0x000004a8
466 #define MAC_RCV_VALUE_5                 0x000004ac
467 #define MAC_RCV_RULE_6                  0x000004b0
468 #define MAC_RCV_VALUE_6                 0x000004b4
469 #define MAC_RCV_RULE_7                  0x000004b8
470 #define MAC_RCV_VALUE_7                 0x000004bc
471 #define MAC_RCV_RULE_8                  0x000004c0
472 #define MAC_RCV_VALUE_8                 0x000004c4
473 #define MAC_RCV_RULE_9                  0x000004c8
474 #define MAC_RCV_VALUE_9                 0x000004cc
475 #define MAC_RCV_RULE_10                 0x000004d0
476 #define MAC_RCV_VALUE_10                0x000004d4
477 #define MAC_RCV_RULE_11                 0x000004d8
478 #define MAC_RCV_VALUE_11                0x000004dc
479 #define MAC_RCV_RULE_12                 0x000004e0
480 #define MAC_RCV_VALUE_12                0x000004e4
481 #define MAC_RCV_RULE_13                 0x000004e8
482 #define MAC_RCV_VALUE_13                0x000004ec
483 #define MAC_RCV_RULE_14                 0x000004f0
484 #define MAC_RCV_VALUE_14                0x000004f4
485 #define MAC_RCV_RULE_15                 0x000004f8
486 #define MAC_RCV_VALUE_15                0x000004fc
487 #define  RCV_RULE_DISABLE_MASK           0x7fffffff
488 #define MAC_RCV_RULE_CFG                0x00000500
489 #define  RCV_RULE_CFG_DEFAULT_CLASS     0x00000008
490 #define MAC_LOW_WMARK_MAX_RX_FRAME      0x00000504
491 /* 0x508 --> 0x520 unused */
492 #define MAC_HASHREGU_0                  0x00000520
493 #define MAC_HASHREGU_1                  0x00000524
494 #define MAC_HASHREGU_2                  0x00000528
495 #define MAC_HASHREGU_3                  0x0000052c
496 #define MAC_EXTADDR_0_HIGH              0x00000530
497 #define MAC_EXTADDR_0_LOW               0x00000534
498 #define MAC_EXTADDR_1_HIGH              0x00000538
499 #define MAC_EXTADDR_1_LOW               0x0000053c
500 #define MAC_EXTADDR_2_HIGH              0x00000540
501 #define MAC_EXTADDR_2_LOW               0x00000544
502 #define MAC_EXTADDR_3_HIGH              0x00000548
503 #define MAC_EXTADDR_3_LOW               0x0000054c
504 #define MAC_EXTADDR_4_HIGH              0x00000550
505 #define MAC_EXTADDR_4_LOW               0x00000554
506 #define MAC_EXTADDR_5_HIGH              0x00000558
507 #define MAC_EXTADDR_5_LOW               0x0000055c
508 #define MAC_EXTADDR_6_HIGH              0x00000560
509 #define MAC_EXTADDR_6_LOW               0x00000564
510 #define MAC_EXTADDR_7_HIGH              0x00000568
511 #define MAC_EXTADDR_7_LOW               0x0000056c
512 #define MAC_EXTADDR_8_HIGH              0x00000570
513 #define MAC_EXTADDR_8_LOW               0x00000574
514 #define MAC_EXTADDR_9_HIGH              0x00000578
515 #define MAC_EXTADDR_9_LOW               0x0000057c
516 #define MAC_EXTADDR_10_HIGH             0x00000580
517 #define MAC_EXTADDR_10_LOW              0x00000584
518 #define MAC_EXTADDR_11_HIGH             0x00000588
519 #define MAC_EXTADDR_11_LOW              0x0000058c
520 #define MAC_SERDES_CFG                  0x00000590
521 #define  MAC_SERDES_CFG_EDGE_SELECT      0x00001000
522 #define MAC_SERDES_STAT                 0x00000594
523 /* 0x598 --> 0x5b0 unused */
524 #define SERDES_RX_CTRL                  0x000005b0      /* 5780/5714 only */
525 #define  SERDES_RX_SIG_DETECT            0x00000400
526 #define SG_DIG_CTRL                     0x000005b0
527 #define  SG_DIG_USING_HW_AUTONEG         0x80000000
528 #define  SG_DIG_SOFT_RESET               0x40000000
529 #define  SG_DIG_DISABLE_LINKRDY          0x20000000
530 #define  SG_DIG_CRC16_CLEAR_N            0x01000000
531 #define  SG_DIG_EN10B                    0x00800000
532 #define  SG_DIG_CLEAR_STATUS             0x00400000
533 #define  SG_DIG_LOCAL_DUPLEX_STATUS      0x00200000
534 #define  SG_DIG_LOCAL_LINK_STATUS        0x00100000
535 #define  SG_DIG_SPEED_STATUS_MASK        0x000c0000
536 #define  SG_DIG_SPEED_STATUS_SHIFT       18
537 #define  SG_DIG_JUMBO_PACKET_DISABLE     0x00020000
538 #define  SG_DIG_RESTART_AUTONEG          0x00010000
539 #define  SG_DIG_FIBER_MODE               0x00008000
540 #define  SG_DIG_REMOTE_FAULT_MASK        0x00006000
541 #define  SG_DIG_PAUSE_MASK               0x00001800
542 #define  SG_DIG_GBIC_ENABLE              0x00000400
543 #define  SG_DIG_CHECK_END_ENABLE         0x00000200
544 #define  SG_DIG_SGMII_AUTONEG_TIMER      0x00000100
545 #define  SG_DIG_CLOCK_PHASE_SELECT       0x00000080
546 #define  SG_DIG_GMII_INPUT_SELECT        0x00000040
547 #define  SG_DIG_MRADV_CRC16_SELECT       0x00000020
548 #define  SG_DIG_COMMA_DETECT_ENABLE      0x00000010
549 #define  SG_DIG_AUTONEG_TIMER_REDUCE     0x00000008
550 #define  SG_DIG_AUTONEG_LOW_ENABLE       0x00000004
551 #define  SG_DIG_REMOTE_LOOPBACK          0x00000002
552 #define  SG_DIG_LOOPBACK                 0x00000001
553 #define SG_DIG_STATUS                   0x000005b4
554 #define  SG_DIG_CRC16_BUS_MASK           0xffff0000
555 #define  SG_DIG_PARTNER_FAULT_MASK       0x00600000 /* If !MRADV_CRC16_SELECT */
556 #define  SG_DIG_PARTNER_ASYM_PAUSE       0x00100000 /* If !MRADV_CRC16_SELECT */
557 #define  SG_DIG_PARTNER_PAUSE_CAPABLE    0x00080000 /* If !MRADV_CRC16_SELECT */
558 #define  SG_DIG_PARTNER_HALF_DUPLEX      0x00040000 /* If !MRADV_CRC16_SELECT */
559 #define  SG_DIG_PARTNER_FULL_DUPLEX      0x00020000 /* If !MRADV_CRC16_SELECT */
560 #define  SG_DIG_PARTNER_NEXT_PAGE        0x00010000 /* If !MRADV_CRC16_SELECT */
561 #define  SG_DIG_AUTONEG_STATE_MASK       0x00000ff0
562 #define  SG_DIG_COMMA_DETECTOR           0x00000008
563 #define  SG_DIG_MAC_ACK_STATUS           0x00000004
564 #define  SG_DIG_AUTONEG_COMPLETE         0x00000002
565 #define  SG_DIG_AUTONEG_ERROR            0x00000001
566 /* 0x5b8 --> 0x600 unused */
567 #define MAC_TX_MAC_STATE_BASE           0x00000600 /* 16 bytes */
568 #define MAC_RX_MAC_STATE_BASE           0x00000610 /* 20 bytes */
569 /* 0x624 --> 0x800 unused */
570 #define MAC_TX_STATS_OCTETS             0x00000800
571 #define MAC_TX_STATS_RESV1              0x00000804
572 #define MAC_TX_STATS_COLLISIONS         0x00000808
573 #define MAC_TX_STATS_XON_SENT           0x0000080c
574 #define MAC_TX_STATS_XOFF_SENT          0x00000810
575 #define MAC_TX_STATS_RESV2              0x00000814
576 #define MAC_TX_STATS_MAC_ERRORS         0x00000818
577 #define MAC_TX_STATS_SINGLE_COLLISIONS  0x0000081c
578 #define MAC_TX_STATS_MULT_COLLISIONS    0x00000820
579 #define MAC_TX_STATS_DEFERRED           0x00000824
580 #define MAC_TX_STATS_RESV3              0x00000828
581 #define MAC_TX_STATS_EXCESSIVE_COL      0x0000082c
582 #define MAC_TX_STATS_LATE_COL           0x00000830
583 #define MAC_TX_STATS_RESV4_1            0x00000834
584 #define MAC_TX_STATS_RESV4_2            0x00000838
585 #define MAC_TX_STATS_RESV4_3            0x0000083c
586 #define MAC_TX_STATS_RESV4_4            0x00000840
587 #define MAC_TX_STATS_RESV4_5            0x00000844
588 #define MAC_TX_STATS_RESV4_6            0x00000848
589 #define MAC_TX_STATS_RESV4_7            0x0000084c
590 #define MAC_TX_STATS_RESV4_8            0x00000850
591 #define MAC_TX_STATS_RESV4_9            0x00000854
592 #define MAC_TX_STATS_RESV4_10           0x00000858
593 #define MAC_TX_STATS_RESV4_11           0x0000085c
594 #define MAC_TX_STATS_RESV4_12           0x00000860
595 #define MAC_TX_STATS_RESV4_13           0x00000864
596 #define MAC_TX_STATS_RESV4_14           0x00000868
597 #define MAC_TX_STATS_UCAST              0x0000086c
598 #define MAC_TX_STATS_MCAST              0x00000870
599 #define MAC_TX_STATS_BCAST              0x00000874
600 #define MAC_TX_STATS_RESV5_1            0x00000878
601 #define MAC_TX_STATS_RESV5_2            0x0000087c
602 #define MAC_RX_STATS_OCTETS             0x00000880
603 #define MAC_RX_STATS_RESV1              0x00000884
604 #define MAC_RX_STATS_FRAGMENTS          0x00000888
605 #define MAC_RX_STATS_UCAST              0x0000088c
606 #define MAC_RX_STATS_MCAST              0x00000890
607 #define MAC_RX_STATS_BCAST              0x00000894
608 #define MAC_RX_STATS_FCS_ERRORS         0x00000898
609 #define MAC_RX_STATS_ALIGN_ERRORS       0x0000089c
610 #define MAC_RX_STATS_XON_PAUSE_RECVD    0x000008a0
611 #define MAC_RX_STATS_XOFF_PAUSE_RECVD   0x000008a4
612 #define MAC_RX_STATS_MAC_CTRL_RECVD     0x000008a8
613 #define MAC_RX_STATS_XOFF_ENTERED       0x000008ac
614 #define MAC_RX_STATS_FRAME_TOO_LONG     0x000008b0
615 #define MAC_RX_STATS_JABBERS            0x000008b4
616 #define MAC_RX_STATS_UNDERSIZE          0x000008b8
617 /* 0x8bc --> 0xc00 unused */
618
619 /* Send data initiator control registers */
620 #define SNDDATAI_MODE                   0x00000c00
621 #define  SNDDATAI_MODE_RESET             0x00000001
622 #define  SNDDATAI_MODE_ENABLE            0x00000002
623 #define  SNDDATAI_MODE_STAT_OFLOW_ENAB   0x00000004
624 #define SNDDATAI_STATUS                 0x00000c04
625 #define  SNDDATAI_STATUS_STAT_OFLOW      0x00000004
626 #define SNDDATAI_STATSCTRL              0x00000c08
627 #define  SNDDATAI_SCTRL_ENABLE           0x00000001
628 #define  SNDDATAI_SCTRL_FASTUPD          0x00000002
629 #define  SNDDATAI_SCTRL_CLEAR            0x00000004
630 #define  SNDDATAI_SCTRL_FLUSH            0x00000008
631 #define  SNDDATAI_SCTRL_FORCE_ZERO       0x00000010
632 #define SNDDATAI_STATSENAB              0x00000c0c
633 #define SNDDATAI_STATSINCMASK           0x00000c10
634 #define ISO_PKT_TX                      0x00000c20
635 /* 0xc24 --> 0xc80 unused */
636 #define SNDDATAI_COS_CNT_0              0x00000c80
637 #define SNDDATAI_COS_CNT_1              0x00000c84
638 #define SNDDATAI_COS_CNT_2              0x00000c88
639 #define SNDDATAI_COS_CNT_3              0x00000c8c
640 #define SNDDATAI_COS_CNT_4              0x00000c90
641 #define SNDDATAI_COS_CNT_5              0x00000c94
642 #define SNDDATAI_COS_CNT_6              0x00000c98
643 #define SNDDATAI_COS_CNT_7              0x00000c9c
644 #define SNDDATAI_COS_CNT_8              0x00000ca0
645 #define SNDDATAI_COS_CNT_9              0x00000ca4
646 #define SNDDATAI_COS_CNT_10             0x00000ca8
647 #define SNDDATAI_COS_CNT_11             0x00000cac
648 #define SNDDATAI_COS_CNT_12             0x00000cb0
649 #define SNDDATAI_COS_CNT_13             0x00000cb4
650 #define SNDDATAI_COS_CNT_14             0x00000cb8
651 #define SNDDATAI_COS_CNT_15             0x00000cbc
652 #define SNDDATAI_DMA_RDQ_FULL_CNT       0x00000cc0
653 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT  0x00000cc4
654 #define SNDDATAI_SDCQ_FULL_CNT          0x00000cc8
655 #define SNDDATAI_NICRNG_SSND_PIDX_CNT   0x00000ccc
656 #define SNDDATAI_STATS_UPDATED_CNT      0x00000cd0
657 #define SNDDATAI_INTERRUPTS_CNT         0x00000cd4
658 #define SNDDATAI_AVOID_INTERRUPTS_CNT   0x00000cd8
659 #define SNDDATAI_SND_THRESH_HIT_CNT     0x00000cdc
660 /* 0xce0 --> 0x1000 unused */
661
662 /* Send data completion control registers */
663 #define SNDDATAC_MODE                   0x00001000
664 #define  SNDDATAC_MODE_RESET             0x00000001
665 #define  SNDDATAC_MODE_ENABLE            0x00000002
666 /* 0x1004 --> 0x1400 unused */
667
668 /* Send BD ring selector */
669 #define SNDBDS_MODE                     0x00001400
670 #define  SNDBDS_MODE_RESET               0x00000001
671 #define  SNDBDS_MODE_ENABLE              0x00000002
672 #define  SNDBDS_MODE_ATTN_ENABLE         0x00000004
673 #define SNDBDS_STATUS                   0x00001404
674 #define  SNDBDS_STATUS_ERROR_ATTN        0x00000004
675 #define SNDBDS_HWDIAG                   0x00001408
676 /* 0x140c --> 0x1440 */
677 #define SNDBDS_SEL_CON_IDX_0            0x00001440
678 #define SNDBDS_SEL_CON_IDX_1            0x00001444
679 #define SNDBDS_SEL_CON_IDX_2            0x00001448
680 #define SNDBDS_SEL_CON_IDX_3            0x0000144c
681 #define SNDBDS_SEL_CON_IDX_4            0x00001450
682 #define SNDBDS_SEL_CON_IDX_5            0x00001454
683 #define SNDBDS_SEL_CON_IDX_6            0x00001458
684 #define SNDBDS_SEL_CON_IDX_7            0x0000145c
685 #define SNDBDS_SEL_CON_IDX_8            0x00001460
686 #define SNDBDS_SEL_CON_IDX_9            0x00001464
687 #define SNDBDS_SEL_CON_IDX_10           0x00001468
688 #define SNDBDS_SEL_CON_IDX_11           0x0000146c
689 #define SNDBDS_SEL_CON_IDX_12           0x00001470
690 #define SNDBDS_SEL_CON_IDX_13           0x00001474
691 #define SNDBDS_SEL_CON_IDX_14           0x00001478
692 #define SNDBDS_SEL_CON_IDX_15           0x0000147c
693 /* 0x1480 --> 0x1800 unused */
694
695 /* Send BD initiator control registers */
696 #define SNDBDI_MODE                     0x00001800
697 #define  SNDBDI_MODE_RESET               0x00000001
698 #define  SNDBDI_MODE_ENABLE              0x00000002
699 #define  SNDBDI_MODE_ATTN_ENABLE         0x00000004
700 #define SNDBDI_STATUS                   0x00001804
701 #define  SNDBDI_STATUS_ERROR_ATTN        0x00000004
702 #define SNDBDI_IN_PROD_IDX_0            0x00001808
703 #define SNDBDI_IN_PROD_IDX_1            0x0000180c
704 #define SNDBDI_IN_PROD_IDX_2            0x00001810
705 #define SNDBDI_IN_PROD_IDX_3            0x00001814
706 #define SNDBDI_IN_PROD_IDX_4            0x00001818
707 #define SNDBDI_IN_PROD_IDX_5            0x0000181c
708 #define SNDBDI_IN_PROD_IDX_6            0x00001820
709 #define SNDBDI_IN_PROD_IDX_7            0x00001824
710 #define SNDBDI_IN_PROD_IDX_8            0x00001828
711 #define SNDBDI_IN_PROD_IDX_9            0x0000182c
712 #define SNDBDI_IN_PROD_IDX_10           0x00001830
713 #define SNDBDI_IN_PROD_IDX_11           0x00001834
714 #define SNDBDI_IN_PROD_IDX_12           0x00001838
715 #define SNDBDI_IN_PROD_IDX_13           0x0000183c
716 #define SNDBDI_IN_PROD_IDX_14           0x00001840
717 #define SNDBDI_IN_PROD_IDX_15           0x00001844
718 /* 0x1848 --> 0x1c00 unused */
719
720 /* Send BD completion control registers */
721 #define SNDBDC_MODE                     0x00001c00
722 #define SNDBDC_MODE_RESET                0x00000001
723 #define SNDBDC_MODE_ENABLE               0x00000002
724 #define SNDBDC_MODE_ATTN_ENABLE          0x00000004
725 /* 0x1c04 --> 0x2000 unused */
726
727 /* Receive list placement control registers */
728 #define RCVLPC_MODE                     0x00002000
729 #define  RCVLPC_MODE_RESET               0x00000001
730 #define  RCVLPC_MODE_ENABLE              0x00000002
731 #define  RCVLPC_MODE_CLASS0_ATTN_ENAB    0x00000004
732 #define  RCVLPC_MODE_MAPOOR_AATTN_ENAB   0x00000008
733 #define  RCVLPC_MODE_STAT_OFLOW_ENAB     0x00000010
734 #define RCVLPC_STATUS                   0x00002004
735 #define  RCVLPC_STATUS_CLASS0            0x00000004
736 #define  RCVLPC_STATUS_MAPOOR            0x00000008
737 #define  RCVLPC_STATUS_STAT_OFLOW        0x00000010
738 #define RCVLPC_LOCK                     0x00002008
739 #define  RCVLPC_LOCK_REQ_MASK            0x0000ffff
740 #define  RCVLPC_LOCK_REQ_SHIFT           0
741 #define  RCVLPC_LOCK_GRANT_MASK          0xffff0000
742 #define  RCVLPC_LOCK_GRANT_SHIFT         16
743 #define RCVLPC_NON_EMPTY_BITS           0x0000200c
744 #define  RCVLPC_NON_EMPTY_BITS_MASK      0x0000ffff
745 #define RCVLPC_CONFIG                   0x00002010
746 #define RCVLPC_STATSCTRL                0x00002014
747 #define  RCVLPC_STATSCTRL_ENABLE         0x00000001
748 #define  RCVLPC_STATSCTRL_FASTUPD        0x00000002
749 #define RCVLPC_STATS_ENABLE             0x00002018
750 #define  RCVLPC_STATSENAB_DACK_FIX       0x00040000
751 #define  RCVLPC_STATSENAB_LNGBRST_RFIX   0x00400000
752 #define RCVLPC_STATS_INCMASK            0x0000201c
753 /* 0x2020 --> 0x2100 unused */
754 #define RCVLPC_SELLST_BASE              0x00002100 /* 16 16-byte entries */
755 #define  SELLST_TAIL                    0x00000004
756 #define  SELLST_CONT                    0x00000008
757 #define  SELLST_UNUSED                  0x0000000c
758 #define RCVLPC_COS_CNTL_BASE            0x00002200 /* 16 4-byte entries */
759 #define RCVLPC_DROP_FILTER_CNT          0x00002240
760 #define RCVLPC_DMA_WQ_FULL_CNT          0x00002244
761 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT   0x00002248
762 #define RCVLPC_NO_RCV_BD_CNT            0x0000224c
763 #define RCVLPC_IN_DISCARDS_CNT          0x00002250
764 #define RCVLPC_IN_ERRORS_CNT            0x00002254
765 #define RCVLPC_RCV_THRESH_HIT_CNT       0x00002258
766 /* 0x225c --> 0x2400 unused */
767
768 /* Receive Data and Receive BD Initiator Control */
769 #define RCVDBDI_MODE                    0x00002400
770 #define  RCVDBDI_MODE_RESET              0x00000001
771 #define  RCVDBDI_MODE_ENABLE             0x00000002
772 #define  RCVDBDI_MODE_JUMBOBD_NEEDED     0x00000004
773 #define  RCVDBDI_MODE_FRM_TOO_BIG        0x00000008
774 #define  RCVDBDI_MODE_INV_RING_SZ        0x00000010
775 #define RCVDBDI_STATUS                  0x00002404
776 #define  RCVDBDI_STATUS_JUMBOBD_NEEDED   0x00000004
777 #define  RCVDBDI_STATUS_FRM_TOO_BIG      0x00000008
778 #define  RCVDBDI_STATUS_INV_RING_SZ      0x00000010
779 #define RCVDBDI_SPLIT_FRAME_MINSZ       0x00002408
780 /* 0x240c --> 0x2440 unused */
781 #define RCVDBDI_JUMBO_BD                0x00002440 /* TG3_BDINFO_... */
782 #define RCVDBDI_STD_BD                  0x00002450 /* TG3_BDINFO_... */
783 #define RCVDBDI_MINI_BD                 0x00002460 /* TG3_BDINFO_... */
784 #define RCVDBDI_JUMBO_CON_IDX           0x00002470
785 #define RCVDBDI_STD_CON_IDX             0x00002474
786 #define RCVDBDI_MINI_CON_IDX            0x00002478
787 /* 0x247c --> 0x2480 unused */
788 #define RCVDBDI_BD_PROD_IDX_0           0x00002480
789 #define RCVDBDI_BD_PROD_IDX_1           0x00002484
790 #define RCVDBDI_BD_PROD_IDX_2           0x00002488
791 #define RCVDBDI_BD_PROD_IDX_3           0x0000248c
792 #define RCVDBDI_BD_PROD_IDX_4           0x00002490
793 #define RCVDBDI_BD_PROD_IDX_5           0x00002494
794 #define RCVDBDI_BD_PROD_IDX_6           0x00002498
795 #define RCVDBDI_BD_PROD_IDX_7           0x0000249c
796 #define RCVDBDI_BD_PROD_IDX_8           0x000024a0
797 #define RCVDBDI_BD_PROD_IDX_9           0x000024a4
798 #define RCVDBDI_BD_PROD_IDX_10          0x000024a8
799 #define RCVDBDI_BD_PROD_IDX_11          0x000024ac
800 #define RCVDBDI_BD_PROD_IDX_12          0x000024b0
801 #define RCVDBDI_BD_PROD_IDX_13          0x000024b4
802 #define RCVDBDI_BD_PROD_IDX_14          0x000024b8
803 #define RCVDBDI_BD_PROD_IDX_15          0x000024bc
804 #define RCVDBDI_HWDIAG                  0x000024c0
805 /* 0x24c4 --> 0x2800 unused */
806
807 /* Receive Data Completion Control */
808 #define RCVDCC_MODE                     0x00002800
809 #define  RCVDCC_MODE_RESET               0x00000001
810 #define  RCVDCC_MODE_ENABLE              0x00000002
811 #define  RCVDCC_MODE_ATTN_ENABLE         0x00000004
812 /* 0x2804 --> 0x2c00 unused */
813
814 /* Receive BD Initiator Control Registers */
815 #define RCVBDI_MODE                     0x00002c00
816 #define  RCVBDI_MODE_RESET               0x00000001
817 #define  RCVBDI_MODE_ENABLE              0x00000002
818 #define  RCVBDI_MODE_RCB_ATTN_ENAB       0x00000004
819 #define RCVBDI_STATUS                   0x00002c04
820 #define  RCVBDI_STATUS_RCB_ATTN          0x00000004
821 #define RCVBDI_JUMBO_PROD_IDX           0x00002c08
822 #define RCVBDI_STD_PROD_IDX             0x00002c0c
823 #define RCVBDI_MINI_PROD_IDX            0x00002c10
824 #define RCVBDI_MINI_THRESH              0x00002c14
825 #define RCVBDI_STD_THRESH               0x00002c18
826 #define RCVBDI_JUMBO_THRESH             0x00002c1c
827 /* 0x2c20 --> 0x3000 unused */
828
829 /* Receive BD Completion Control Registers */
830 #define RCVCC_MODE                      0x00003000
831 #define  RCVCC_MODE_RESET                0x00000001
832 #define  RCVCC_MODE_ENABLE               0x00000002
833 #define  RCVCC_MODE_ATTN_ENABLE          0x00000004
834 #define RCVCC_STATUS                    0x00003004
835 #define  RCVCC_STATUS_ERROR_ATTN         0x00000004
836 #define RCVCC_JUMP_PROD_IDX             0x00003008
837 #define RCVCC_STD_PROD_IDX              0x0000300c
838 #define RCVCC_MINI_PROD_IDX             0x00003010
839 /* 0x3014 --> 0x3400 unused */
840
841 /* Receive list selector control registers */
842 #define RCVLSC_MODE                     0x00003400
843 #define  RCVLSC_MODE_RESET               0x00000001
844 #define  RCVLSC_MODE_ENABLE              0x00000002
845 #define  RCVLSC_MODE_ATTN_ENABLE         0x00000004
846 #define RCVLSC_STATUS                   0x00003404
847 #define  RCVLSC_STATUS_ERROR_ATTN        0x00000004
848 /* 0x3408 --> 0x3600 unused */
849
850 /* CPMU registers */
851 #define TG3_CPMU_CTRL                   0x00003600
852 #define  CPMU_CTRL_LINK_IDLE_MODE        0x00000200
853 #define  CPMU_CTRL_LINK_AWARE_MODE       0x00000400
854 /* 0x3604 --> 0x3800 unused */
855
856 /* Mbuf cluster free registers */
857 #define MBFREE_MODE                     0x00003800
858 #define  MBFREE_MODE_RESET               0x00000001
859 #define  MBFREE_MODE_ENABLE              0x00000002
860 #define MBFREE_STATUS                   0x00003804
861 /* 0x3808 --> 0x3c00 unused */
862
863 /* Host coalescing control registers */
864 #define HOSTCC_MODE                     0x00003c00
865 #define  HOSTCC_MODE_RESET               0x00000001
866 #define  HOSTCC_MODE_ENABLE              0x00000002
867 #define  HOSTCC_MODE_ATTN                0x00000004
868 #define  HOSTCC_MODE_NOW                 0x00000008
869 #define  HOSTCC_MODE_FULL_STATUS         0x00000000
870 #define  HOSTCC_MODE_64BYTE              0x00000080
871 #define  HOSTCC_MODE_32BYTE              0x00000100
872 #define  HOSTCC_MODE_CLRTICK_RXBD        0x00000200
873 #define  HOSTCC_MODE_CLRTICK_TXBD        0x00000400
874 #define  HOSTCC_MODE_NOINT_ON_NOW        0x00000800
875 #define  HOSTCC_MODE_NOINT_ON_FORCE      0x00001000
876 #define HOSTCC_STATUS                   0x00003c04
877 #define  HOSTCC_STATUS_ERROR_ATTN        0x00000004
878 #define HOSTCC_RXCOL_TICKS              0x00003c08
879 #define  LOW_RXCOL_TICKS                 0x00000032
880 #define  LOW_RXCOL_TICKS_CLRTCKS         0x00000014
881 #define  DEFAULT_RXCOL_TICKS             0x00000048
882 #define  HIGH_RXCOL_TICKS                0x00000096
883 #define  MAX_RXCOL_TICKS                 0x000003ff
884 #define HOSTCC_TXCOL_TICKS              0x00003c0c
885 #define  LOW_TXCOL_TICKS                 0x00000096
886 #define  LOW_TXCOL_TICKS_CLRTCKS         0x00000048
887 #define  DEFAULT_TXCOL_TICKS             0x0000012c
888 #define  HIGH_TXCOL_TICKS                0x00000145
889 #define  MAX_TXCOL_TICKS                 0x000003ff
890 #define HOSTCC_RXMAX_FRAMES             0x00003c10
891 #define  LOW_RXMAX_FRAMES                0x00000005
892 #define  DEFAULT_RXMAX_FRAMES            0x00000008
893 #define  HIGH_RXMAX_FRAMES               0x00000012
894 #define  MAX_RXMAX_FRAMES                0x000000ff
895 #define HOSTCC_TXMAX_FRAMES             0x00003c14
896 #define  LOW_TXMAX_FRAMES                0x00000035
897 #define  DEFAULT_TXMAX_FRAMES            0x0000004b
898 #define  HIGH_TXMAX_FRAMES               0x00000052
899 #define  MAX_TXMAX_FRAMES                0x000000ff
900 #define HOSTCC_RXCOAL_TICK_INT          0x00003c18
901 #define  DEFAULT_RXCOAL_TICK_INT         0x00000019
902 #define  DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
903 #define  MAX_RXCOAL_TICK_INT             0x000003ff
904 #define HOSTCC_TXCOAL_TICK_INT          0x00003c1c
905 #define  DEFAULT_TXCOAL_TICK_INT         0x00000019
906 #define  DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
907 #define  MAX_TXCOAL_TICK_INT             0x000003ff
908 #define HOSTCC_RXCOAL_MAXF_INT          0x00003c20
909 #define  DEFAULT_RXCOAL_MAXF_INT         0x00000005
910 #define  MAX_RXCOAL_MAXF_INT             0x000000ff
911 #define HOSTCC_TXCOAL_MAXF_INT          0x00003c24
912 #define  DEFAULT_TXCOAL_MAXF_INT         0x00000005
913 #define  MAX_TXCOAL_MAXF_INT             0x000000ff
914 #define HOSTCC_STAT_COAL_TICKS          0x00003c28
915 #define  DEFAULT_STAT_COAL_TICKS         0x000f4240
916 #define  MAX_STAT_COAL_TICKS             0xd693d400
917 #define  MIN_STAT_COAL_TICKS             0x00000064
918 /* 0x3c2c --> 0x3c30 unused */
919 #define HOSTCC_STATS_BLK_HOST_ADDR      0x00003c30 /* 64-bit */
920 #define HOSTCC_STATUS_BLK_HOST_ADDR     0x00003c38 /* 64-bit */
921 #define HOSTCC_STATS_BLK_NIC_ADDR       0x00003c40
922 #define HOSTCC_STATUS_BLK_NIC_ADDR      0x00003c44
923 #define HOSTCC_FLOW_ATTN                0x00003c48
924 /* 0x3c4c --> 0x3c50 unused */
925 #define HOSTCC_JUMBO_CON_IDX            0x00003c50
926 #define HOSTCC_STD_CON_IDX              0x00003c54
927 #define HOSTCC_MINI_CON_IDX             0x00003c58
928 /* 0x3c5c --> 0x3c80 unused */
929 #define HOSTCC_RET_PROD_IDX_0           0x00003c80
930 #define HOSTCC_RET_PROD_IDX_1           0x00003c84
931 #define HOSTCC_RET_PROD_IDX_2           0x00003c88
932 #define HOSTCC_RET_PROD_IDX_3           0x00003c8c
933 #define HOSTCC_RET_PROD_IDX_4           0x00003c90
934 #define HOSTCC_RET_PROD_IDX_5           0x00003c94
935 #define HOSTCC_RET_PROD_IDX_6           0x00003c98
936 #define HOSTCC_RET_PROD_IDX_7           0x00003c9c
937 #define HOSTCC_RET_PROD_IDX_8           0x00003ca0
938 #define HOSTCC_RET_PROD_IDX_9           0x00003ca4
939 #define HOSTCC_RET_PROD_IDX_10          0x00003ca8
940 #define HOSTCC_RET_PROD_IDX_11          0x00003cac
941 #define HOSTCC_RET_PROD_IDX_12          0x00003cb0
942 #define HOSTCC_RET_PROD_IDX_13          0x00003cb4
943 #define HOSTCC_RET_PROD_IDX_14          0x00003cb8
944 #define HOSTCC_RET_PROD_IDX_15          0x00003cbc
945 #define HOSTCC_SND_CON_IDX_0            0x00003cc0
946 #define HOSTCC_SND_CON_IDX_1            0x00003cc4
947 #define HOSTCC_SND_CON_IDX_2            0x00003cc8
948 #define HOSTCC_SND_CON_IDX_3            0x00003ccc
949 #define HOSTCC_SND_CON_IDX_4            0x00003cd0
950 #define HOSTCC_SND_CON_IDX_5            0x00003cd4
951 #define HOSTCC_SND_CON_IDX_6            0x00003cd8
952 #define HOSTCC_SND_CON_IDX_7            0x00003cdc
953 #define HOSTCC_SND_CON_IDX_8            0x00003ce0
954 #define HOSTCC_SND_CON_IDX_9            0x00003ce4
955 #define HOSTCC_SND_CON_IDX_10           0x00003ce8
956 #define HOSTCC_SND_CON_IDX_11           0x00003cec
957 #define HOSTCC_SND_CON_IDX_12           0x00003cf0
958 #define HOSTCC_SND_CON_IDX_13           0x00003cf4
959 #define HOSTCC_SND_CON_IDX_14           0x00003cf8
960 #define HOSTCC_SND_CON_IDX_15           0x00003cfc
961 /* 0x3d00 --> 0x4000 unused */
962
963 /* Memory arbiter control registers */
964 #define MEMARB_MODE                     0x00004000
965 #define  MEMARB_MODE_RESET               0x00000001
966 #define  MEMARB_MODE_ENABLE              0x00000002
967 #define MEMARB_STATUS                   0x00004004
968 #define MEMARB_TRAP_ADDR_LOW            0x00004008
969 #define MEMARB_TRAP_ADDR_HIGH           0x0000400c
970 /* 0x4010 --> 0x4400 unused */
971
972 /* Buffer manager control registers */
973 #define BUFMGR_MODE                     0x00004400
974 #define  BUFMGR_MODE_RESET               0x00000001
975 #define  BUFMGR_MODE_ENABLE              0x00000002
976 #define  BUFMGR_MODE_ATTN_ENABLE         0x00000004
977 #define  BUFMGR_MODE_BM_TEST             0x00000008
978 #define  BUFMGR_MODE_MBLOW_ATTN_ENAB     0x00000010
979 #define BUFMGR_STATUS                   0x00004404
980 #define  BUFMGR_STATUS_ERROR             0x00000004
981 #define  BUFMGR_STATUS_MBLOW             0x00000010
982 #define BUFMGR_MB_POOL_ADDR             0x00004408
983 #define BUFMGR_MB_POOL_SIZE             0x0000440c
984 #define BUFMGR_MB_RDMA_LOW_WATER        0x00004410
985 #define  DEFAULT_MB_RDMA_LOW_WATER       0x00000050
986 #define  DEFAULT_MB_RDMA_LOW_WATER_5705  0x00000000
987 #define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
988 #define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
989 #define BUFMGR_MB_MACRX_LOW_WATER       0x00004414
990 #define  DEFAULT_MB_MACRX_LOW_WATER       0x00000020
991 #define  DEFAULT_MB_MACRX_LOW_WATER_5705  0x00000010
992 #define  DEFAULT_MB_MACRX_LOW_WATER_5906  0x00000004
993 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
994 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
995 #define BUFMGR_MB_HIGH_WATER            0x00004418
996 #define  DEFAULT_MB_HIGH_WATER           0x00000060
997 #define  DEFAULT_MB_HIGH_WATER_5705      0x00000060
998 #define  DEFAULT_MB_HIGH_WATER_5906      0x00000010
999 #define  DEFAULT_MB_HIGH_WATER_JUMBO     0x0000017c
1000 #define  DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
1001 #define BUFMGR_RX_MB_ALLOC_REQ          0x0000441c
1002 #define  BUFMGR_MB_ALLOC_BIT             0x10000000
1003 #define BUFMGR_RX_MB_ALLOC_RESP         0x00004420
1004 #define BUFMGR_TX_MB_ALLOC_REQ          0x00004424
1005 #define BUFMGR_TX_MB_ALLOC_RESP         0x00004428
1006 #define BUFMGR_DMA_DESC_POOL_ADDR       0x0000442c
1007 #define BUFMGR_DMA_DESC_POOL_SIZE       0x00004430
1008 #define BUFMGR_DMA_LOW_WATER            0x00004434
1009 #define  DEFAULT_DMA_LOW_WATER           0x00000005
1010 #define BUFMGR_DMA_HIGH_WATER           0x00004438
1011 #define  DEFAULT_DMA_HIGH_WATER          0x0000000a
1012 #define BUFMGR_RX_DMA_ALLOC_REQ         0x0000443c
1013 #define BUFMGR_RX_DMA_ALLOC_RESP        0x00004440
1014 #define BUFMGR_TX_DMA_ALLOC_REQ         0x00004444
1015 #define BUFMGR_TX_DMA_ALLOC_RESP        0x00004448
1016 #define BUFMGR_HWDIAG_0                 0x0000444c
1017 #define BUFMGR_HWDIAG_1                 0x00004450
1018 #define BUFMGR_HWDIAG_2                 0x00004454
1019 /* 0x4458 --> 0x4800 unused */
1020
1021 /* Read DMA control registers */
1022 #define RDMAC_MODE                      0x00004800
1023 #define  RDMAC_MODE_RESET                0x00000001
1024 #define  RDMAC_MODE_ENABLE               0x00000002
1025 #define  RDMAC_MODE_TGTABORT_ENAB        0x00000004
1026 #define  RDMAC_MODE_MSTABORT_ENAB        0x00000008
1027 #define  RDMAC_MODE_PARITYERR_ENAB       0x00000010
1028 #define  RDMAC_MODE_ADDROFLOW_ENAB       0x00000020
1029 #define  RDMAC_MODE_FIFOOFLOW_ENAB       0x00000040
1030 #define  RDMAC_MODE_FIFOURUN_ENAB        0x00000080
1031 #define  RDMAC_MODE_FIFOOREAD_ENAB       0x00000100
1032 #define  RDMAC_MODE_LNGREAD_ENAB         0x00000200
1033 #define  RDMAC_MODE_SPLIT_ENABLE         0x00000800
1034 #define  RDMAC_MODE_BD_SBD_CRPT_ENAB     0x00000800
1035 #define  RDMAC_MODE_SPLIT_RESET          0x00001000
1036 #define  RDMAC_MODE_MBUF_RBD_CRPT_ENAB   0x00001000
1037 #define  RDMAC_MODE_MBUF_SBD_CRPT_ENAB   0x00002000
1038 #define  RDMAC_MODE_FIFO_SIZE_128        0x00020000
1039 #define  RDMAC_MODE_FIFO_LONG_BURST      0x00030000
1040 #define RDMAC_STATUS                    0x00004804
1041 #define  RDMAC_STATUS_TGTABORT           0x00000004
1042 #define  RDMAC_STATUS_MSTABORT           0x00000008
1043 #define  RDMAC_STATUS_PARITYERR          0x00000010
1044 #define  RDMAC_STATUS_ADDROFLOW          0x00000020
1045 #define  RDMAC_STATUS_FIFOOFLOW          0x00000040
1046 #define  RDMAC_STATUS_FIFOURUN           0x00000080
1047 #define  RDMAC_STATUS_FIFOOREAD          0x00000100
1048 #define  RDMAC_STATUS_LNGREAD            0x00000200
1049 /* 0x4808 --> 0x4c00 unused */
1050
1051 /* Write DMA control registers */
1052 #define WDMAC_MODE                      0x00004c00
1053 #define  WDMAC_MODE_RESET                0x00000001
1054 #define  WDMAC_MODE_ENABLE               0x00000002
1055 #define  WDMAC_MODE_TGTABORT_ENAB        0x00000004
1056 #define  WDMAC_MODE_MSTABORT_ENAB        0x00000008
1057 #define  WDMAC_MODE_PARITYERR_ENAB       0x00000010
1058 #define  WDMAC_MODE_ADDROFLOW_ENAB       0x00000020
1059 #define  WDMAC_MODE_FIFOOFLOW_ENAB       0x00000040
1060 #define  WDMAC_MODE_FIFOURUN_ENAB        0x00000080
1061 #define  WDMAC_MODE_FIFOOREAD_ENAB       0x00000100
1062 #define  WDMAC_MODE_LNGREAD_ENAB         0x00000200
1063 #define  WDMAC_MODE_RX_ACCEL             0x00000400
1064 #define WDMAC_STATUS                    0x00004c04
1065 #define  WDMAC_STATUS_TGTABORT           0x00000004
1066 #define  WDMAC_STATUS_MSTABORT           0x00000008
1067 #define  WDMAC_STATUS_PARITYERR          0x00000010
1068 #define  WDMAC_STATUS_ADDROFLOW          0x00000020
1069 #define  WDMAC_STATUS_FIFOOFLOW          0x00000040
1070 #define  WDMAC_STATUS_FIFOURUN           0x00000080
1071 #define  WDMAC_STATUS_FIFOOREAD          0x00000100
1072 #define  WDMAC_STATUS_LNGREAD            0x00000200
1073 /* 0x4c08 --> 0x5000 unused */
1074
1075 /* Per-cpu register offsets (arm9) */
1076 #define CPU_MODE                        0x00000000
1077 #define  CPU_MODE_RESET                  0x00000001
1078 #define  CPU_MODE_HALT                   0x00000400
1079 #define CPU_STATE                       0x00000004
1080 #define CPU_EVTMASK                     0x00000008
1081 /* 0xc --> 0x1c reserved */
1082 #define CPU_PC                          0x0000001c
1083 #define CPU_INSN                        0x00000020
1084 #define CPU_SPAD_UFLOW                  0x00000024
1085 #define CPU_WDOG_CLEAR                  0x00000028
1086 #define CPU_WDOG_VECTOR                 0x0000002c
1087 #define CPU_WDOG_PC                     0x00000030
1088 #define CPU_HW_BP                       0x00000034
1089 /* 0x38 --> 0x44 unused */
1090 #define CPU_WDOG_SAVED_STATE            0x00000044
1091 #define CPU_LAST_BRANCH_ADDR            0x00000048
1092 #define CPU_SPAD_UFLOW_SET              0x0000004c
1093 /* 0x50 --> 0x200 unused */
1094 #define CPU_R0                          0x00000200
1095 #define CPU_R1                          0x00000204
1096 #define CPU_R2                          0x00000208
1097 #define CPU_R3                          0x0000020c
1098 #define CPU_R4                          0x00000210
1099 #define CPU_R5                          0x00000214
1100 #define CPU_R6                          0x00000218
1101 #define CPU_R7                          0x0000021c
1102 #define CPU_R8                          0x00000220
1103 #define CPU_R9                          0x00000224
1104 #define CPU_R10                         0x00000228
1105 #define CPU_R11                         0x0000022c
1106 #define CPU_R12                         0x00000230
1107 #define CPU_R13                         0x00000234
1108 #define CPU_R14                         0x00000238
1109 #define CPU_R15                         0x0000023c
1110 #define CPU_R16                         0x00000240
1111 #define CPU_R17                         0x00000244
1112 #define CPU_R18                         0x00000248
1113 #define CPU_R19                         0x0000024c
1114 #define CPU_R20                         0x00000250
1115 #define CPU_R21                         0x00000254
1116 #define CPU_R22                         0x00000258
1117 #define CPU_R23                         0x0000025c
1118 #define CPU_R24                         0x00000260
1119 #define CPU_R25                         0x00000264
1120 #define CPU_R26                         0x00000268
1121 #define CPU_R27                         0x0000026c
1122 #define CPU_R28                         0x00000270
1123 #define CPU_R29                         0x00000274
1124 #define CPU_R30                         0x00000278
1125 #define CPU_R31                         0x0000027c
1126 /* 0x280 --> 0x400 unused */
1127
1128 #define RX_CPU_BASE                     0x00005000
1129 #define RX_CPU_MODE                     0x00005000
1130 #define RX_CPU_STATE                    0x00005004
1131 #define RX_CPU_PGMCTR                   0x0000501c
1132 #define RX_CPU_HWBKPT                   0x00005034
1133 #define TX_CPU_BASE                     0x00005400
1134 #define TX_CPU_MODE                     0x00005400
1135 #define TX_CPU_STATE                    0x00005404
1136 #define TX_CPU_PGMCTR                   0x0000541c
1137
1138 #define VCPU_STATUS                     0x00005100
1139 #define  VCPU_STATUS_INIT_DONE           0x04000000
1140 #define  VCPU_STATUS_DRV_RESET           0x08000000
1141
1142 #define VCPU_CFGSHDW                    0x00005104
1143 #define  VCPU_CFGSHDW_ASPM_DBNC          0x00001000
1144
1145 /* Mailboxes */
1146 #define GRCMBOX_BASE                    0x00005600
1147 #define GRCMBOX_INTERRUPT_0             0x00005800 /* 64-bit */
1148 #define GRCMBOX_INTERRUPT_1             0x00005808 /* 64-bit */
1149 #define GRCMBOX_INTERRUPT_2             0x00005810 /* 64-bit */
1150 #define GRCMBOX_INTERRUPT_3             0x00005818 /* 64-bit */
1151 #define GRCMBOX_GENERAL_0               0x00005820 /* 64-bit */
1152 #define GRCMBOX_GENERAL_1               0x00005828 /* 64-bit */
1153 #define GRCMBOX_GENERAL_2               0x00005830 /* 64-bit */
1154 #define GRCMBOX_GENERAL_3               0x00005838 /* 64-bit */
1155 #define GRCMBOX_GENERAL_4               0x00005840 /* 64-bit */
1156 #define GRCMBOX_GENERAL_5               0x00005848 /* 64-bit */
1157 #define GRCMBOX_GENERAL_6               0x00005850 /* 64-bit */
1158 #define GRCMBOX_GENERAL_7               0x00005858 /* 64-bit */
1159 #define GRCMBOX_RELOAD_STAT             0x00005860 /* 64-bit */
1160 #define GRCMBOX_RCVSTD_PROD_IDX         0x00005868 /* 64-bit */
1161 #define GRCMBOX_RCVJUMBO_PROD_IDX       0x00005870 /* 64-bit */
1162 #define GRCMBOX_RCVMINI_PROD_IDX        0x00005878 /* 64-bit */
1163 #define GRCMBOX_RCVRET_CON_IDX_0        0x00005880 /* 64-bit */
1164 #define GRCMBOX_RCVRET_CON_IDX_1        0x00005888 /* 64-bit */
1165 #define GRCMBOX_RCVRET_CON_IDX_2        0x00005890 /* 64-bit */
1166 #define GRCMBOX_RCVRET_CON_IDX_3        0x00005898 /* 64-bit */
1167 #define GRCMBOX_RCVRET_CON_IDX_4        0x000058a0 /* 64-bit */
1168 #define GRCMBOX_RCVRET_CON_IDX_5        0x000058a8 /* 64-bit */
1169 #define GRCMBOX_RCVRET_CON_IDX_6        0x000058b0 /* 64-bit */
1170 #define GRCMBOX_RCVRET_CON_IDX_7        0x000058b8 /* 64-bit */
1171 #define GRCMBOX_RCVRET_CON_IDX_8        0x000058c0 /* 64-bit */
1172 #define GRCMBOX_RCVRET_CON_IDX_9        0x000058c8 /* 64-bit */
1173 #define GRCMBOX_RCVRET_CON_IDX_10       0x000058d0 /* 64-bit */
1174 #define GRCMBOX_RCVRET_CON_IDX_11       0x000058d8 /* 64-bit */
1175 #define GRCMBOX_RCVRET_CON_IDX_12       0x000058e0 /* 64-bit */
1176 #define GRCMBOX_RCVRET_CON_IDX_13       0x000058e8 /* 64-bit */
1177 #define GRCMBOX_RCVRET_CON_IDX_14       0x000058f0 /* 64-bit */
1178 #define GRCMBOX_RCVRET_CON_IDX_15       0x000058f8 /* 64-bit */
1179 #define GRCMBOX_SNDHOST_PROD_IDX_0      0x00005900 /* 64-bit */
1180 #define GRCMBOX_SNDHOST_PROD_IDX_1      0x00005908 /* 64-bit */
1181 #define GRCMBOX_SNDHOST_PROD_IDX_2      0x00005910 /* 64-bit */
1182 #define GRCMBOX_SNDHOST_PROD_IDX_3      0x00005918 /* 64-bit */
1183 #define GRCMBOX_SNDHOST_PROD_IDX_4      0x00005920 /* 64-bit */
1184 #define GRCMBOX_SNDHOST_PROD_IDX_5      0x00005928 /* 64-bit */
1185 #define GRCMBOX_SNDHOST_PROD_IDX_6      0x00005930 /* 64-bit */
1186 #define GRCMBOX_SNDHOST_PROD_IDX_7      0x00005938 /* 64-bit */
1187 #define GRCMBOX_SNDHOST_PROD_IDX_8      0x00005940 /* 64-bit */
1188 #define GRCMBOX_SNDHOST_PROD_IDX_9      0x00005948 /* 64-bit */
1189 #define GRCMBOX_SNDHOST_PROD_IDX_10     0x00005950 /* 64-bit */
1190 #define GRCMBOX_SNDHOST_PROD_IDX_11     0x00005958 /* 64-bit */
1191 #define GRCMBOX_SNDHOST_PROD_IDX_12     0x00005960 /* 64-bit */
1192 #define GRCMBOX_SNDHOST_PROD_IDX_13     0x00005968 /* 64-bit */
1193 #define GRCMBOX_SNDHOST_PROD_IDX_14     0x00005970 /* 64-bit */
1194 #define GRCMBOX_SNDHOST_PROD_IDX_15     0x00005978 /* 64-bit */
1195 #define GRCMBOX_SNDNIC_PROD_IDX_0       0x00005980 /* 64-bit */
1196 #define GRCMBOX_SNDNIC_PROD_IDX_1       0x00005988 /* 64-bit */
1197 #define GRCMBOX_SNDNIC_PROD_IDX_2       0x00005990 /* 64-bit */
1198 #define GRCMBOX_SNDNIC_PROD_IDX_3       0x00005998 /* 64-bit */
1199 #define GRCMBOX_SNDNIC_PROD_IDX_4       0x000059a0 /* 64-bit */
1200 #define GRCMBOX_SNDNIC_PROD_IDX_5       0x000059a8 /* 64-bit */
1201 #define GRCMBOX_SNDNIC_PROD_IDX_6       0x000059b0 /* 64-bit */
1202 #define GRCMBOX_SNDNIC_PROD_IDX_7       0x000059b8 /* 64-bit */
1203 #define GRCMBOX_SNDNIC_PROD_IDX_8       0x000059c0 /* 64-bit */
1204 #define GRCMBOX_SNDNIC_PROD_IDX_9       0x000059c8 /* 64-bit */
1205 #define GRCMBOX_SNDNIC_PROD_IDX_10      0x000059d0 /* 64-bit */
1206 #define GRCMBOX_SNDNIC_PROD_IDX_11      0x000059d8 /* 64-bit */
1207 #define GRCMBOX_SNDNIC_PROD_IDX_12      0x000059e0 /* 64-bit */
1208 #define GRCMBOX_SNDNIC_PROD_IDX_13      0x000059e8 /* 64-bit */
1209 #define GRCMBOX_SNDNIC_PROD_IDX_14      0x000059f0 /* 64-bit */
1210 #define GRCMBOX_SNDNIC_PROD_IDX_15      0x000059f8 /* 64-bit */
1211 #define GRCMBOX_HIGH_PRIO_EV_VECTOR     0x00005a00
1212 #define GRCMBOX_HIGH_PRIO_EV_MASK       0x00005a04
1213 #define GRCMBOX_LOW_PRIO_EV_VEC         0x00005a08
1214 #define GRCMBOX_LOW_PRIO_EV_MASK        0x00005a0c
1215 /* 0x5a10 --> 0x5c00 */
1216
1217 /* Flow Through queues */
1218 #define FTQ_RESET                       0x00005c00
1219 /* 0x5c04 --> 0x5c10 unused */
1220 #define FTQ_DMA_NORM_READ_CTL           0x00005c10
1221 #define FTQ_DMA_NORM_READ_FULL_CNT      0x00005c14
1222 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ   0x00005c18
1223 #define FTQ_DMA_NORM_READ_WRITE_PEEK    0x00005c1c
1224 #define FTQ_DMA_HIGH_READ_CTL           0x00005c20
1225 #define FTQ_DMA_HIGH_READ_FULL_CNT      0x00005c24
1226 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ   0x00005c28
1227 #define FTQ_DMA_HIGH_READ_WRITE_PEEK    0x00005c2c
1228 #define FTQ_DMA_COMP_DISC_CTL           0x00005c30
1229 #define FTQ_DMA_COMP_DISC_FULL_CNT      0x00005c34
1230 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ   0x00005c38
1231 #define FTQ_DMA_COMP_DISC_WRITE_PEEK    0x00005c3c
1232 #define FTQ_SEND_BD_COMP_CTL            0x00005c40
1233 #define FTQ_SEND_BD_COMP_FULL_CNT       0x00005c44
1234 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ    0x00005c48
1235 #define FTQ_SEND_BD_COMP_WRITE_PEEK     0x00005c4c
1236 #define FTQ_SEND_DATA_INIT_CTL          0x00005c50
1237 #define FTQ_SEND_DATA_INIT_FULL_CNT     0x00005c54
1238 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ  0x00005c58
1239 #define FTQ_SEND_DATA_INIT_WRITE_PEEK   0x00005c5c
1240 #define FTQ_DMA_NORM_WRITE_CTL          0x00005c60
1241 #define FTQ_DMA_NORM_WRITE_FULL_CNT     0x00005c64
1242 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ  0x00005c68
1243 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK   0x00005c6c
1244 #define FTQ_DMA_HIGH_WRITE_CTL          0x00005c70
1245 #define FTQ_DMA_HIGH_WRITE_FULL_CNT     0x00005c74
1246 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ  0x00005c78
1247 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK   0x00005c7c
1248 #define FTQ_SWTYPE1_CTL                 0x00005c80
1249 #define FTQ_SWTYPE1_FULL_CNT            0x00005c84
1250 #define FTQ_SWTYPE1_FIFO_ENQDEQ         0x00005c88
1251 #define FTQ_SWTYPE1_WRITE_PEEK          0x00005c8c
1252 #define FTQ_SEND_DATA_COMP_CTL          0x00005c90
1253 #define FTQ_SEND_DATA_COMP_FULL_CNT     0x00005c94
1254 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ  0x00005c98
1255 #define FTQ_SEND_DATA_COMP_WRITE_PEEK   0x00005c9c
1256 #define FTQ_HOST_COAL_CTL               0x00005ca0
1257 #define FTQ_HOST_COAL_FULL_CNT          0x00005ca4
1258 #define FTQ_HOST_COAL_FIFO_ENQDEQ       0x00005ca8
1259 #define FTQ_HOST_COAL_WRITE_PEEK        0x00005cac
1260 #define FTQ_MAC_TX_CTL                  0x00005cb0
1261 #define FTQ_MAC_TX_FULL_CNT             0x00005cb4
1262 #define FTQ_MAC_TX_FIFO_ENQDEQ          0x00005cb8
1263 #define FTQ_MAC_TX_WRITE_PEEK           0x00005cbc
1264 #define FTQ_MB_FREE_CTL                 0x00005cc0
1265 #define FTQ_MB_FREE_FULL_CNT            0x00005cc4
1266 #define FTQ_MB_FREE_FIFO_ENQDEQ         0x00005cc8
1267 #define FTQ_MB_FREE_WRITE_PEEK          0x00005ccc
1268 #define FTQ_RCVBD_COMP_CTL              0x00005cd0
1269 #define FTQ_RCVBD_COMP_FULL_CNT         0x00005cd4
1270 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ      0x00005cd8
1271 #define FTQ_RCVBD_COMP_WRITE_PEEK       0x00005cdc
1272 #define FTQ_RCVLST_PLMT_CTL             0x00005ce0
1273 #define FTQ_RCVLST_PLMT_FULL_CNT        0x00005ce4
1274 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ     0x00005ce8
1275 #define FTQ_RCVLST_PLMT_WRITE_PEEK      0x00005cec
1276 #define FTQ_RCVDATA_INI_CTL             0x00005cf0
1277 #define FTQ_RCVDATA_INI_FULL_CNT        0x00005cf4
1278 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ     0x00005cf8
1279 #define FTQ_RCVDATA_INI_WRITE_PEEK      0x00005cfc
1280 #define FTQ_RCVDATA_COMP_CTL            0x00005d00
1281 #define FTQ_RCVDATA_COMP_FULL_CNT       0x00005d04
1282 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ    0x00005d08
1283 #define FTQ_RCVDATA_COMP_WRITE_PEEK     0x00005d0c
1284 #define FTQ_SWTYPE2_CTL                 0x00005d10
1285 #define FTQ_SWTYPE2_FULL_CNT            0x00005d14
1286 #define FTQ_SWTYPE2_FIFO_ENQDEQ         0x00005d18
1287 #define FTQ_SWTYPE2_WRITE_PEEK          0x00005d1c
1288 /* 0x5d20 --> 0x6000 unused */
1289
1290 /* Message signaled interrupt registers */
1291 #define MSGINT_MODE                     0x00006000
1292 #define  MSGINT_MODE_RESET               0x00000001
1293 #define  MSGINT_MODE_ENABLE              0x00000002
1294 #define MSGINT_STATUS                   0x00006004
1295 #define MSGINT_FIFO                     0x00006008
1296 /* 0x600c --> 0x6400 unused */
1297
1298 /* DMA completion registers */
1299 #define DMAC_MODE                       0x00006400
1300 #define  DMAC_MODE_RESET                 0x00000001
1301 #define  DMAC_MODE_ENABLE                0x00000002
1302 /* 0x6404 --> 0x6800 unused */
1303
1304 /* GRC registers */
1305 #define GRC_MODE                        0x00006800
1306 #define  GRC_MODE_UPD_ON_COAL           0x00000001
1307 #define  GRC_MODE_BSWAP_NONFRM_DATA     0x00000002
1308 #define  GRC_MODE_WSWAP_NONFRM_DATA     0x00000004
1309 #define  GRC_MODE_BSWAP_DATA            0x00000010
1310 #define  GRC_MODE_WSWAP_DATA            0x00000020
1311 #define  GRC_MODE_SPLITHDR              0x00000100
1312 #define  GRC_MODE_NOFRM_CRACKING        0x00000200
1313 #define  GRC_MODE_INCL_CRC              0x00000400
1314 #define  GRC_MODE_ALLOW_BAD_FRMS        0x00000800
1315 #define  GRC_MODE_NOIRQ_ON_SENDS        0x00002000
1316 #define  GRC_MODE_NOIRQ_ON_RCV          0x00004000
1317 #define  GRC_MODE_FORCE_PCI32BIT        0x00008000
1318 #define  GRC_MODE_HOST_STACKUP          0x00010000
1319 #define  GRC_MODE_HOST_SENDBDS          0x00020000
1320 #define  GRC_MODE_NO_TX_PHDR_CSUM       0x00100000
1321 #define  GRC_MODE_NVRAM_WR_ENABLE       0x00200000
1322 #define  GRC_MODE_NO_RX_PHDR_CSUM       0x00800000
1323 #define  GRC_MODE_IRQ_ON_TX_CPU_ATTN    0x01000000
1324 #define  GRC_MODE_IRQ_ON_RX_CPU_ATTN    0x02000000
1325 #define  GRC_MODE_IRQ_ON_MAC_ATTN       0x04000000
1326 #define  GRC_MODE_IRQ_ON_DMA_ATTN       0x08000000
1327 #define  GRC_MODE_IRQ_ON_FLOW_ATTN      0x10000000
1328 #define  GRC_MODE_4X_NIC_SEND_RINGS     0x20000000
1329 #define  GRC_MODE_MCAST_FRM_ENABLE      0x40000000
1330 #define GRC_MISC_CFG                    0x00006804
1331 #define  GRC_MISC_CFG_CORECLK_RESET     0x00000001
1332 #define  GRC_MISC_CFG_PRESCALAR_MASK    0x000000fe
1333 #define  GRC_MISC_CFG_PRESCALAR_SHIFT   1
1334 #define  GRC_MISC_CFG_BOARD_ID_MASK     0x0001e000
1335 #define  GRC_MISC_CFG_BOARD_ID_5700     0x0001e000
1336 #define  GRC_MISC_CFG_BOARD_ID_5701     0x00000000
1337 #define  GRC_MISC_CFG_BOARD_ID_5702FE   0x00004000
1338 #define  GRC_MISC_CFG_BOARD_ID_5703     0x00000000
1339 #define  GRC_MISC_CFG_BOARD_ID_5703S    0x00002000
1340 #define  GRC_MISC_CFG_BOARD_ID_5704     0x00000000
1341 #define  GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1342 #define  GRC_MISC_CFG_BOARD_ID_5704_A2  0x00008000
1343 #define  GRC_MISC_CFG_BOARD_ID_5788     0x00010000
1344 #define  GRC_MISC_CFG_BOARD_ID_5788M    0x00018000
1345 #define  GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1346 #define  GRC_MISC_CFG_EPHY_IDDQ         0x00200000
1347 #define  GRC_MISC_CFG_KEEP_GPHY_POWER   0x04000000
1348 #define GRC_LOCAL_CTRL                  0x00006808
1349 #define  GRC_LCLCTRL_INT_ACTIVE         0x00000001
1350 #define  GRC_LCLCTRL_CLEARINT           0x00000002
1351 #define  GRC_LCLCTRL_SETINT             0x00000004
1352 #define  GRC_LCLCTRL_INT_ON_ATTN        0x00000008
1353 #define  GRC_LCLCTRL_GPIO_UART_SEL      0x00000010      /* 5755 only */
1354 #define  GRC_LCLCTRL_USE_SIG_DETECT     0x00000010      /* 5714/5780 only */
1355 #define  GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020      /* 5714/5780 only */
1356 #define  GRC_LCLCTRL_GPIO_INPUT3        0x00000020
1357 #define  GRC_LCLCTRL_GPIO_OE3           0x00000040
1358 #define  GRC_LCLCTRL_GPIO_OUTPUT3       0x00000080
1359 #define  GRC_LCLCTRL_GPIO_INPUT0        0x00000100
1360 #define  GRC_LCLCTRL_GPIO_INPUT1        0x00000200
1361 #define  GRC_LCLCTRL_GPIO_INPUT2        0x00000400
1362 #define  GRC_LCLCTRL_GPIO_OE0           0x00000800
1363 #define  GRC_LCLCTRL_GPIO_OE1           0x00001000
1364 #define  GRC_LCLCTRL_GPIO_OE2           0x00002000
1365 #define  GRC_LCLCTRL_GPIO_OUTPUT0       0x00004000
1366 #define  GRC_LCLCTRL_GPIO_OUTPUT1       0x00008000
1367 #define  GRC_LCLCTRL_GPIO_OUTPUT2       0x00010000
1368 #define  GRC_LCLCTRL_EXTMEM_ENABLE      0x00020000
1369 #define  GRC_LCLCTRL_MEMSZ_MASK         0x001c0000
1370 #define  GRC_LCLCTRL_MEMSZ_256K         0x00000000
1371 #define  GRC_LCLCTRL_MEMSZ_512K         0x00040000
1372 #define  GRC_LCLCTRL_MEMSZ_1M           0x00080000
1373 #define  GRC_LCLCTRL_MEMSZ_2M           0x000c0000
1374 #define  GRC_LCLCTRL_MEMSZ_4M           0x00100000
1375 #define  GRC_LCLCTRL_MEMSZ_8M           0x00140000
1376 #define  GRC_LCLCTRL_MEMSZ_16M          0x00180000
1377 #define  GRC_LCLCTRL_BANK_SELECT        0x00200000
1378 #define  GRC_LCLCTRL_SSRAM_TYPE         0x00400000
1379 #define  GRC_LCLCTRL_AUTO_SEEPROM       0x01000000
1380 #define GRC_TIMER                       0x0000680c
1381 #define GRC_RX_CPU_EVENT                0x00006810
1382 #define GRC_RX_TIMER_REF                0x00006814
1383 #define GRC_RX_CPU_SEM                  0x00006818
1384 #define GRC_REMOTE_RX_CPU_ATTN          0x0000681c
1385 #define GRC_TX_CPU_EVENT                0x00006820
1386 #define GRC_TX_TIMER_REF                0x00006824
1387 #define GRC_TX_CPU_SEM                  0x00006828
1388 #define GRC_REMOTE_TX_CPU_ATTN          0x0000682c
1389 #define GRC_MEM_POWER_UP                0x00006830 /* 64-bit */
1390 #define GRC_EEPROM_ADDR                 0x00006838
1391 #define  EEPROM_ADDR_WRITE              0x00000000
1392 #define  EEPROM_ADDR_READ               0x80000000
1393 #define  EEPROM_ADDR_COMPLETE           0x40000000
1394 #define  EEPROM_ADDR_FSM_RESET          0x20000000
1395 #define  EEPROM_ADDR_DEVID_MASK         0x1c000000
1396 #define  EEPROM_ADDR_DEVID_SHIFT        26
1397 #define  EEPROM_ADDR_START              0x02000000
1398 #define  EEPROM_ADDR_CLKPERD_SHIFT      16
1399 #define  EEPROM_ADDR_ADDR_MASK          0x0000ffff
1400 #define  EEPROM_ADDR_ADDR_SHIFT         0
1401 #define  EEPROM_DEFAULT_CLOCK_PERIOD    0x60
1402 #define  EEPROM_CHIP_SIZE               (64 * 1024)
1403 #define GRC_EEPROM_DATA                 0x0000683c
1404 #define GRC_EEPROM_CTRL                 0x00006840
1405 #define GRC_MDI_CTRL                    0x00006844
1406 #define GRC_SEEPROM_DELAY               0x00006848
1407 /* 0x684c --> 0x6890 unused */
1408 #define GRC_VCPU_EXT_CTRL               0x00006890
1409 #define GRC_VCPU_EXT_CTRL_HALT_CPU       0x00400000
1410 #define GRC_VCPU_EXT_CTRL_DISABLE_WOL    0x20000000
1411 #define GRC_FASTBOOT_PC                 0x00006894      /* 5752, 5755, 5787 */
1412
1413 /* 0x6c00 --> 0x7000 unused */
1414
1415 /* NVRAM Control registers */
1416 #define NVRAM_CMD                       0x00007000
1417 #define  NVRAM_CMD_RESET                 0x00000001
1418 #define  NVRAM_CMD_DONE                  0x00000008
1419 #define  NVRAM_CMD_GO                    0x00000010
1420 #define  NVRAM_CMD_WR                    0x00000020
1421 #define  NVRAM_CMD_RD                    0x00000000
1422 #define  NVRAM_CMD_ERASE                 0x00000040
1423 #define  NVRAM_CMD_FIRST                 0x00000080
1424 #define  NVRAM_CMD_LAST                  0x00000100
1425 #define  NVRAM_CMD_WREN                  0x00010000
1426 #define  NVRAM_CMD_WRDI                  0x00020000
1427 #define NVRAM_STAT                      0x00007004
1428 #define NVRAM_WRDATA                    0x00007008
1429 #define NVRAM_ADDR                      0x0000700c
1430 #define  NVRAM_ADDR_MSK                 0x00ffffff
1431 #define NVRAM_RDDATA                    0x00007010
1432 #define NVRAM_CFG1                      0x00007014
1433 #define  NVRAM_CFG1_FLASHIF_ENAB         0x00000001
1434 #define  NVRAM_CFG1_BUFFERED_MODE        0x00000002
1435 #define  NVRAM_CFG1_PASS_THRU            0x00000004
1436 #define  NVRAM_CFG1_STATUS_BITS          0x00000070
1437 #define  NVRAM_CFG1_BIT_BANG             0x00000008
1438 #define  NVRAM_CFG1_FLASH_SIZE           0x02000000
1439 #define  NVRAM_CFG1_COMPAT_BYPASS        0x80000000
1440 #define  NVRAM_CFG1_VENDOR_MASK          0x03000003
1441 #define  FLASH_VENDOR_ATMEL_EEPROM       0x02000000
1442 #define  FLASH_VENDOR_ATMEL_FLASH_BUFFERED       0x02000003
1443 #define  FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED     0x00000003
1444 #define  FLASH_VENDOR_ST                         0x03000001
1445 #define  FLASH_VENDOR_SAIFUN             0x01000003
1446 #define  FLASH_VENDOR_SST_SMALL          0x00000001
1447 #define  FLASH_VENDOR_SST_LARGE          0x02000001
1448 #define  NVRAM_CFG1_5752VENDOR_MASK      0x03c00003
1449 #define  FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ     0x00000000
1450 #define  FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ    0x02000000
1451 #define  FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED   0x02000003
1452 #define  FLASH_5752VENDOR_ST_M45PE10     0x02400000
1453 #define  FLASH_5752VENDOR_ST_M45PE20     0x02400002
1454 #define  FLASH_5752VENDOR_ST_M45PE40     0x02400001
1455 #define  FLASH_5755VENDOR_ATMEL_FLASH_1  0x03400001
1456 #define  FLASH_5755VENDOR_ATMEL_FLASH_2  0x03400002
1457 #define  FLASH_5755VENDOR_ATMEL_FLASH_3  0x03400000
1458 #define  FLASH_5755VENDOR_ATMEL_FLASH_4  0x00000003
1459 #define  FLASH_5755VENDOR_ATMEL_FLASH_5  0x02000003
1460 #define  FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ     0x03c00003
1461 #define  FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ    0x03c00002
1462 #define  FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ     0x03000003
1463 #define  FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ    0x03000002
1464 #define  FLASH_5787VENDOR_MICRO_EEPROM_64KHZ     0x03000000
1465 #define  FLASH_5787VENDOR_MICRO_EEPROM_376KHZ    0x02000000
1466 #define  NVRAM_CFG1_5752PAGE_SIZE_MASK   0x70000000
1467 #define  FLASH_5752PAGE_SIZE_256         0x00000000
1468 #define  FLASH_5752PAGE_SIZE_512         0x10000000
1469 #define  FLASH_5752PAGE_SIZE_1K          0x20000000
1470 #define  FLASH_5752PAGE_SIZE_2K          0x30000000
1471 #define  FLASH_5752PAGE_SIZE_4K          0x40000000
1472 #define  FLASH_5752PAGE_SIZE_264         0x50000000
1473 #define NVRAM_CFG2                      0x00007018
1474 #define NVRAM_CFG3                      0x0000701c
1475 #define NVRAM_SWARB                     0x00007020
1476 #define  SWARB_REQ_SET0                  0x00000001
1477 #define  SWARB_REQ_SET1                  0x00000002
1478 #define  SWARB_REQ_SET2                  0x00000004
1479 #define  SWARB_REQ_SET3                  0x00000008
1480 #define  SWARB_REQ_CLR0                  0x00000010
1481 #define  SWARB_REQ_CLR1                  0x00000020
1482 #define  SWARB_REQ_CLR2                  0x00000040
1483 #define  SWARB_REQ_CLR3                  0x00000080
1484 #define  SWARB_GNT0                      0x00000100
1485 #define  SWARB_GNT1                      0x00000200
1486 #define  SWARB_GNT2                      0x00000400
1487 #define  SWARB_GNT3                      0x00000800
1488 #define  SWARB_REQ0                      0x00001000
1489 #define  SWARB_REQ1                      0x00002000
1490 #define  SWARB_REQ2                      0x00004000
1491 #define  SWARB_REQ3                      0x00008000
1492 #define NVRAM_ACCESS                    0x00007024
1493 #define  ACCESS_ENABLE                   0x00000001
1494 #define  ACCESS_WR_ENABLE                0x00000002
1495 #define NVRAM_WRITE1                    0x00007028
1496 /* 0x702c --> 0x7400 unused */
1497
1498 /* 0x7400 --> 0x7c00 unused */
1499 #define PCIE_TRANSACTION_CFG            0x00007c04
1500 #define PCIE_TRANS_CFG_1SHOT_MSI         0x20000000
1501 #define PCIE_TRANS_CFG_LOM               0x00000020
1502
1503 #define PCIE_PWR_MGMT_THRESH            0x00007d28
1504 #define PCIE_PWR_MGMT_L1_THRESH_MSK      0x0000ff00
1505
1506 #define TG3_EEPROM_MAGIC                0x669955aa
1507 #define TG3_EEPROM_MAGIC_FW             0xa5000000
1508 #define TG3_EEPROM_MAGIC_FW_MSK         0xff000000
1509 #define TG3_EEPROM_MAGIC_HW             0xabcd
1510 #define TG3_EEPROM_MAGIC_HW_MSK         0xffff
1511
1512 /* 32K Window into NIC internal memory */
1513 #define NIC_SRAM_WIN_BASE               0x00008000
1514
1515 /* Offsets into first 32k of NIC internal memory. */
1516 #define NIC_SRAM_PAGE_ZERO              0x00000000
1517 #define NIC_SRAM_SEND_RCB               0x00000100 /* 16 * TG3_BDINFO_... */
1518 #define NIC_SRAM_RCV_RET_RCB            0x00000200 /* 16 * TG3_BDINFO_... */
1519 #define NIC_SRAM_STATS_BLK              0x00000300
1520 #define NIC_SRAM_STATUS_BLK             0x00000b00
1521
1522 #define NIC_SRAM_FIRMWARE_MBOX          0x00000b50
1523 #define  NIC_SRAM_FIRMWARE_MBOX_MAGIC1   0x4B657654
1524 #define  NIC_SRAM_FIRMWARE_MBOX_MAGIC2   0x4861764b /* !dma on linkchg */
1525
1526 #define NIC_SRAM_DATA_SIG               0x00000b54
1527 #define  NIC_SRAM_DATA_SIG_MAGIC         0x4b657654 /* ascii for 'KevT' */
1528
1529 #define NIC_SRAM_DATA_CFG                       0x00000b58
1530 #define  NIC_SRAM_DATA_CFG_LED_MODE_MASK         0x0000000c
1531 #define  NIC_SRAM_DATA_CFG_LED_MODE_MAC          0x00000000
1532 #define  NIC_SRAM_DATA_CFG_LED_MODE_PHY_1        0x00000004
1533 #define  NIC_SRAM_DATA_CFG_LED_MODE_PHY_2        0x00000008
1534 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_MASK         0x00000030
1535 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN      0x00000000
1536 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER       0x00000010
1537 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER        0x00000020
1538 #define  NIC_SRAM_DATA_CFG_WOL_ENABLE            0x00000040
1539 #define  NIC_SRAM_DATA_CFG_ASF_ENABLE            0x00000080
1540 #define  NIC_SRAM_DATA_CFG_EEPROM_WP             0x00000100
1541 #define  NIC_SRAM_DATA_CFG_MINI_PCI              0x00001000
1542 #define  NIC_SRAM_DATA_CFG_FIBER_WOL             0x00004000
1543 #define  NIC_SRAM_DATA_CFG_NO_GPIO2              0x00100000
1544
1545 #define NIC_SRAM_DATA_VER                       0x00000b5c
1546 #define  NIC_SRAM_DATA_VER_SHIFT                 16
1547
1548 #define NIC_SRAM_DATA_PHY_ID            0x00000b74
1549 #define  NIC_SRAM_DATA_PHY_ID1_MASK      0xffff0000
1550 #define  NIC_SRAM_DATA_PHY_ID2_MASK      0x0000ffff
1551
1552 #define NIC_SRAM_FW_CMD_MBOX            0x00000b78
1553 #define  FWCMD_NICDRV_ALIVE              0x00000001
1554 #define  FWCMD_NICDRV_PAUSE_FW           0x00000002
1555 #define  FWCMD_NICDRV_IPV4ADDR_CHG       0x00000003
1556 #define  FWCMD_NICDRV_IPV6ADDR_CHG       0x00000004
1557 #define  FWCMD_NICDRV_FIX_DMAR           0x00000005
1558 #define  FWCMD_NICDRV_FIX_DMAW           0x00000006
1559 #define  FWCMD_NICDRV_ALIVE2             0x0000000d
1560 #define  FWCMD_NICDRV_ALIVE3             0x0000000e
1561 #define NIC_SRAM_FW_CMD_LEN_MBOX        0x00000b7c
1562 #define NIC_SRAM_FW_CMD_DATA_MBOX       0x00000b80
1563 #define NIC_SRAM_FW_ASF_STATUS_MBOX     0x00000c00
1564 #define NIC_SRAM_FW_DRV_STATE_MBOX      0x00000c04
1565 #define  DRV_STATE_START                 0x00000001
1566 #define  DRV_STATE_START_DONE            0x80000001
1567 #define  DRV_STATE_UNLOAD                0x00000002
1568 #define  DRV_STATE_UNLOAD_DONE           0x80000002
1569 #define  DRV_STATE_WOL                   0x00000003
1570 #define  DRV_STATE_SUSPEND               0x00000004
1571
1572 #define NIC_SRAM_FW_RESET_TYPE_MBOX     0x00000c08
1573
1574 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX     0x00000c14
1575 #define NIC_SRAM_MAC_ADDR_LOW_MBOX      0x00000c18
1576
1577 #define NIC_SRAM_WOL_MBOX               0x00000d30
1578 #define  WOL_SIGNATURE                   0x474c0000
1579 #define  WOL_DRV_STATE_SHUTDOWN          0x00000001
1580 #define  WOL_DRV_WOL                     0x00000002
1581 #define  WOL_SET_MAGIC_PKT               0x00000004
1582
1583 #define NIC_SRAM_DATA_CFG_2             0x00000d38
1584
1585 #define  SHASTA_EXT_LED_MODE_MASK        0x00018000
1586 #define  SHASTA_EXT_LED_LEGACY           0x00000000
1587 #define  SHASTA_EXT_LED_SHARED           0x00008000
1588 #define  SHASTA_EXT_LED_MAC              0x00010000
1589 #define  SHASTA_EXT_LED_COMBO            0x00018000
1590
1591 #define NIC_SRAM_DATA_CFG_3             0x00000d3c
1592 #define  NIC_SRAM_ASPM_DEBOUNCE          0x00000002
1593
1594 #define NIC_SRAM_RX_MINI_BUFFER_DESC    0x00001000
1595
1596 #define NIC_SRAM_DMA_DESC_POOL_BASE     0x00002000
1597 #define  NIC_SRAM_DMA_DESC_POOL_SIZE     0x00002000
1598 #define NIC_SRAM_TX_BUFFER_DESC         0x00004000 /* 512 entries */
1599 #define NIC_SRAM_RX_BUFFER_DESC         0x00006000 /* 256 entries */
1600 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC   0x00007000 /* 256 entries */
1601 #define NIC_SRAM_MBUF_POOL_BASE         0x00008000
1602 #define  NIC_SRAM_MBUF_POOL_SIZE96       0x00018000
1603 #define  NIC_SRAM_MBUF_POOL_SIZE64       0x00010000
1604 #define  NIC_SRAM_MBUF_POOL_BASE5705    0x00010000
1605 #define  NIC_SRAM_MBUF_POOL_SIZE5705    0x0000e000
1606
1607 /* Currently this is fixed. */
1608 #define PHY_ADDR                0x01
1609
1610 /* Tigon3 specific PHY MII registers. */
1611 #define  TG3_BMCR_SPEED1000             0x0040
1612
1613 #define MII_TG3_CTRL                    0x09 /* 1000-baseT control register */
1614 #define  MII_TG3_CTRL_ADV_1000_HALF     0x0100
1615 #define  MII_TG3_CTRL_ADV_1000_FULL     0x0200
1616 #define  MII_TG3_CTRL_AS_MASTER         0x0800
1617 #define  MII_TG3_CTRL_ENABLE_AS_MASTER  0x1000
1618
1619 #define MII_TG3_EXT_CTRL                0x10 /* Extended control register */
1620 #define  MII_TG3_EXT_CTRL_FIFO_ELASTIC  0x0001
1621 #define  MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
1622 #define  MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
1623 #define  MII_TG3_EXT_CTRL_TBI           0x8000
1624
1625 #define MII_TG3_EXT_STAT                0x11 /* Extended status register */
1626 #define  MII_TG3_EXT_STAT_LPASS         0x0100
1627
1628 #define MII_TG3_DSP_RW_PORT             0x15 /* DSP coefficient read/write port */
1629
1630 #define MII_TG3_DSP_ADDRESS             0x17 /* DSP address register */
1631 #define MII_TG3_EPHY_PTEST              0x17 /* 5906 PHY register */
1632
1633 #define MII_TG3_AUX_CTRL                0x18 /* auxilliary control register */
1634
1635 #define MII_TG3_AUXCTL_MISC_WREN        0x8000
1636 #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
1637 #define MII_TG3_AUXCTL_MISC_RDSEL_MISC  0x7000
1638 #define MII_TG3_AUXCTL_SHDWSEL_MISC             0x0007
1639
1640 #define MII_TG3_AUX_STAT                0x19 /* auxilliary status register */
1641 #define MII_TG3_AUX_STAT_LPASS          0x0004
1642 #define MII_TG3_AUX_STAT_SPDMASK        0x0700
1643 #define MII_TG3_AUX_STAT_10HALF         0x0100
1644 #define MII_TG3_AUX_STAT_10FULL         0x0200
1645 #define MII_TG3_AUX_STAT_100HALF        0x0300
1646 #define MII_TG3_AUX_STAT_100_4          0x0400
1647 #define MII_TG3_AUX_STAT_100FULL        0x0500
1648 #define MII_TG3_AUX_STAT_1000HALF       0x0600
1649 #define MII_TG3_AUX_STAT_1000FULL       0x0700
1650 #define MII_TG3_AUX_STAT_100            0x0008
1651 #define MII_TG3_AUX_STAT_FULL           0x0001
1652
1653 #define MII_TG3_ISTAT                   0x1a /* IRQ status register */
1654 #define MII_TG3_IMASK                   0x1b /* IRQ mask register */
1655
1656 /* ISTAT/IMASK event bits */
1657 #define MII_TG3_INT_LINKCHG             0x0002
1658 #define MII_TG3_INT_SPEEDCHG            0x0004
1659 #define MII_TG3_INT_DUPLEXCHG           0x0008
1660 #define MII_TG3_INT_ANEG_PAGE_RX        0x0400
1661
1662 #define MII_TG3_EPHY_TEST               0x1f /* 5906 PHY register */
1663 #define MII_TG3_EPHY_SHADOW_EN          0x80
1664
1665 #define MII_TG3_EPHYTST_MISCCTRL        0x10 /* 5906 EPHY misc ctrl shadow register */
1666 #define MII_TG3_EPHYTST_MISCCTRL_MDIX   0x4000
1667
1668 #define MII_TG3_TEST1                   0x1e
1669 #define MII_TG3_TEST1_TRIM_EN           0x0010
1670 #define MII_TG3_TEST1_CRC_EN            0x8000
1671
1672 /* There are two ways to manage the TX descriptors on the tigon3.
1673  * Either the descriptors are in host DMA'able memory, or they
1674  * exist only in the cards on-chip SRAM.  All 16 send bds are under
1675  * the same mode, they may not be configured individually.
1676  *
1677  * This driver always uses host memory TX descriptors.
1678  *
1679  * To use host memory TX descriptors:
1680  *      1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
1681  *         Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
1682  *      2) Allocate DMA'able memory.
1683  *      3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1684  *         a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
1685  *            obtained in step 2
1686  *         b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
1687  *         c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
1688  *            of TX descriptors.  Leave flags field clear.
1689  *      4) Access TX descriptors via host memory.  The chip
1690  *         will refetch into local SRAM as needed when producer
1691  *         index mailboxes are updated.
1692  *
1693  * To use on-chip TX descriptors:
1694  *      1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
1695  *         Make sure GRC_MODE_HOST_SENDBDS is clear.
1696  *      2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1697  *         a) Set TG3_BDINFO_HOST_ADDR to zero.
1698  *         b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
1699  *         c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
1700  *      3) Access TX descriptors directly in on-chip SRAM
1701  *         using normal {read,write}l().  (and not using
1702  *         pointer dereferencing of ioremap()'d memory like
1703  *         the broken Broadcom driver does)
1704  *
1705  * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
1706  * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
1707  */
1708 struct tg3_tx_buffer_desc {
1709         u32                             addr_hi;
1710         u32                             addr_lo;
1711
1712         u32                             len_flags;
1713 #define TXD_FLAG_TCPUDP_CSUM            0x0001
1714 #define TXD_FLAG_IP_CSUM                0x0002
1715 #define TXD_FLAG_END                    0x0004
1716 #define TXD_FLAG_IP_FRAG                0x0008
1717 #define TXD_FLAG_IP_FRAG_END            0x0010
1718 #define TXD_FLAG_VLAN                   0x0040
1719 #define TXD_FLAG_COAL_NOW               0x0080
1720 #define TXD_FLAG_CPU_PRE_DMA            0x0100
1721 #define TXD_FLAG_CPU_POST_DMA           0x0200
1722 #define TXD_FLAG_ADD_SRC_ADDR           0x1000
1723 #define TXD_FLAG_CHOOSE_SRC_ADDR        0x6000
1724 #define TXD_FLAG_NO_CRC                 0x8000
1725 #define TXD_LEN_SHIFT                   16
1726
1727         u32                             vlan_tag;
1728 #define TXD_VLAN_TAG_SHIFT              0
1729 #define TXD_MSS_SHIFT                   16
1730 };
1731
1732 #define TXD_ADDR                        0x00UL /* 64-bit */
1733 #define TXD_LEN_FLAGS                   0x08UL /* 32-bit (upper 16-bits are len) */
1734 #define TXD_VLAN_TAG                    0x0cUL /* 32-bit (upper 16-bits are tag) */
1735 #define TXD_SIZE                        0x10UL
1736
1737 struct tg3_rx_buffer_desc {
1738         u32                             addr_hi;
1739         u32                             addr_lo;
1740
1741         u32                             idx_len;
1742 #define RXD_IDX_MASK    0xffff0000
1743 #define RXD_IDX_SHIFT   16
1744 #define RXD_LEN_MASK    0x0000ffff
1745 #define RXD_LEN_SHIFT   0
1746
1747         u32                             type_flags;
1748 #define RXD_TYPE_SHIFT  16
1749 #define RXD_FLAGS_SHIFT 0
1750
1751 #define RXD_FLAG_END                    0x0004
1752 #define RXD_FLAG_MINI                   0x0800
1753 #define RXD_FLAG_JUMBO                  0x0020
1754 #define RXD_FLAG_VLAN                   0x0040
1755 #define RXD_FLAG_ERROR                  0x0400
1756 #define RXD_FLAG_IP_CSUM                0x1000
1757 #define RXD_FLAG_TCPUDP_CSUM            0x2000
1758 #define RXD_FLAG_IS_TCP                 0x4000
1759
1760         u32                             ip_tcp_csum;
1761 #define RXD_IPCSUM_MASK         0xffff0000
1762 #define RXD_IPCSUM_SHIFT        16
1763 #define RXD_TCPCSUM_MASK        0x0000ffff
1764 #define RXD_TCPCSUM_SHIFT       0
1765
1766         u32                             err_vlan;
1767
1768 #define RXD_VLAN_MASK                   0x0000ffff
1769
1770 #define RXD_ERR_BAD_CRC                 0x00010000
1771 #define RXD_ERR_COLLISION               0x00020000
1772 #define RXD_ERR_LINK_LOST               0x00040000
1773 #define RXD_ERR_PHY_DECODE              0x00080000
1774 #define RXD_ERR_ODD_NIBBLE_RCVD_MII     0x00100000
1775 #define RXD_ERR_MAC_ABRT                0x00200000
1776 #define RXD_ERR_TOO_SMALL               0x00400000
1777 #define RXD_ERR_NO_RESOURCES            0x00800000
1778 #define RXD_ERR_HUGE_FRAME              0x01000000
1779 #define RXD_ERR_MASK                    0xffff0000
1780
1781         u32                             reserved;
1782         u32                             opaque;
1783 #define RXD_OPAQUE_INDEX_MASK           0x0000ffff
1784 #define RXD_OPAQUE_INDEX_SHIFT          0
1785 #define RXD_OPAQUE_RING_STD             0x00010000
1786 #define RXD_OPAQUE_RING_JUMBO           0x00020000
1787 #define RXD_OPAQUE_RING_MINI            0x00040000
1788 #define RXD_OPAQUE_RING_MASK            0x00070000
1789 };
1790
1791 struct tg3_ext_rx_buffer_desc {
1792         struct {
1793                 u32                     addr_hi;
1794                 u32                     addr_lo;
1795         }                               addrlist[3];
1796         u32                             len2_len1;
1797         u32                             resv_len3;
1798         struct tg3_rx_buffer_desc       std;
1799 };
1800
1801 /* We only use this when testing out the DMA engine
1802  * at probe time.  This is the internal format of buffer
1803  * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
1804  */
1805 struct tg3_internal_buffer_desc {
1806         u32                             addr_hi;
1807         u32                             addr_lo;
1808         u32                             nic_mbuf;
1809         /* XXX FIX THIS */
1810 #ifdef __BIG_ENDIAN
1811         u16                             cqid_sqid;
1812         u16                             len;
1813 #else
1814         u16                             len;
1815         u16                             cqid_sqid;
1816 #endif
1817         u32                             flags;
1818         u32                             __cookie1;
1819         u32                             __cookie2;
1820         u32                             __cookie3;
1821 };
1822
1823 #define TG3_HW_STATUS_SIZE              0x50
1824 struct tg3_hw_status {
1825         u32                             status;
1826 #define SD_STATUS_UPDATED               0x00000001
1827 #define SD_STATUS_LINK_CHG              0x00000002
1828 #define SD_STATUS_ERROR                 0x00000004
1829
1830         u32                             status_tag;
1831
1832 #ifdef __BIG_ENDIAN
1833         u16                             rx_consumer;
1834         u16                             rx_jumbo_consumer;
1835 #else
1836         u16                             rx_jumbo_consumer;
1837         u16                             rx_consumer;
1838 #endif
1839
1840 #ifdef __BIG_ENDIAN
1841         u16                             reserved;
1842         u16                             rx_mini_consumer;
1843 #else
1844         u16                             rx_mini_consumer;
1845         u16                             reserved;
1846 #endif
1847         struct {
1848 #ifdef __BIG_ENDIAN
1849                 u16                     tx_consumer;
1850                 u16                     rx_producer;
1851 #else
1852                 u16                     rx_producer;
1853                 u16                     tx_consumer;
1854 #endif
1855         }                               idx[16];
1856 };
1857
1858 typedef struct {
1859         u32 high, low;
1860 } tg3_stat64_t;
1861
1862 struct tg3_hw_stats {
1863         u8                              __reserved0[0x400-0x300];
1864
1865         /* Statistics maintained by Receive MAC. */
1866         tg3_stat64_t                    rx_octets;
1867         u64                             __reserved1;
1868         tg3_stat64_t                    rx_fragments;
1869         tg3_stat64_t                    rx_ucast_packets;
1870         tg3_stat64_t                    rx_mcast_packets;
1871         tg3_stat64_t                    rx_bcast_packets;
1872         tg3_stat64_t                    rx_fcs_errors;
1873         tg3_stat64_t                    rx_align_errors;
1874         tg3_stat64_t                    rx_xon_pause_rcvd;
1875         tg3_stat64_t                    rx_xoff_pause_rcvd;
1876         tg3_stat64_t                    rx_mac_ctrl_rcvd;
1877         tg3_stat64_t                    rx_xoff_entered;
1878         tg3_stat64_t                    rx_frame_too_long_errors;
1879         tg3_stat64_t                    rx_jabbers;
1880         tg3_stat64_t                    rx_undersize_packets;
1881         tg3_stat64_t                    rx_in_length_errors;
1882         tg3_stat64_t                    rx_out_length_errors;
1883         tg3_stat64_t                    rx_64_or_less_octet_packets;
1884         tg3_stat64_t                    rx_65_to_127_octet_packets;
1885         tg3_stat64_t                    rx_128_to_255_octet_packets;
1886         tg3_stat64_t                    rx_256_to_511_octet_packets;
1887         tg3_stat64_t                    rx_512_to_1023_octet_packets;
1888         tg3_stat64_t                    rx_1024_to_1522_octet_packets;
1889         tg3_stat64_t                    rx_1523_to_2047_octet_packets;
1890         tg3_stat64_t                    rx_2048_to_4095_octet_packets;
1891         tg3_stat64_t                    rx_4096_to_8191_octet_packets;
1892         tg3_stat64_t                    rx_8192_to_9022_octet_packets;
1893
1894         u64                             __unused0[37];
1895
1896         /* Statistics maintained by Transmit MAC. */
1897         tg3_stat64_t                    tx_octets;
1898         u64                             __reserved2;
1899         tg3_stat64_t                    tx_collisions;
1900         tg3_stat64_t                    tx_xon_sent;
1901         tg3_stat64_t                    tx_xoff_sent;
1902         tg3_stat64_t                    tx_flow_control;
1903         tg3_stat64_t                    tx_mac_errors;
1904         tg3_stat64_t                    tx_single_collisions;
1905         tg3_stat64_t                    tx_mult_collisions;
1906         tg3_stat64_t                    tx_deferred;
1907         u64                             __reserved3;
1908         tg3_stat64_t                    tx_excessive_collisions;
1909         tg3_stat64_t                    tx_late_collisions;
1910         tg3_stat64_t                    tx_collide_2times;
1911         tg3_stat64_t                    tx_collide_3times;
1912         tg3_stat64_t                    tx_collide_4times;
1913         tg3_stat64_t                    tx_collide_5times;
1914         tg3_stat64_t                    tx_collide_6times;
1915         tg3_stat64_t                    tx_collide_7times;
1916         tg3_stat64_t                    tx_collide_8times;
1917         tg3_stat64_t                    tx_collide_9times;
1918         tg3_stat64_t                    tx_collide_10times;
1919         tg3_stat64_t                    tx_collide_11times;
1920         tg3_stat64_t                    tx_collide_12times;
1921         tg3_stat64_t                    tx_collide_13times;
1922         tg3_stat64_t                    tx_collide_14times;
1923         tg3_stat64_t                    tx_collide_15times;
1924         tg3_stat64_t                    tx_ucast_packets;
1925         tg3_stat64_t                    tx_mcast_packets;
1926         tg3_stat64_t                    tx_bcast_packets;
1927         tg3_stat64_t                    tx_carrier_sense_errors;
1928         tg3_stat64_t                    tx_discards;
1929         tg3_stat64_t                    tx_errors;
1930
1931         u64                             __unused1[31];
1932
1933         /* Statistics maintained by Receive List Placement. */
1934         tg3_stat64_t                    COS_rx_packets[16];
1935         tg3_stat64_t                    COS_rx_filter_dropped;
1936         tg3_stat64_t                    dma_writeq_full;
1937         tg3_stat64_t                    dma_write_prioq_full;
1938         tg3_stat64_t                    rxbds_empty;
1939         tg3_stat64_t                    rx_discards;
1940         tg3_stat64_t                    rx_errors;
1941         tg3_stat64_t                    rx_threshold_hit;
1942
1943         u64                             __unused2[9];
1944
1945         /* Statistics maintained by Send Data Initiator. */
1946         tg3_stat64_t                    COS_out_packets[16];
1947         tg3_stat64_t                    dma_readq_full;
1948         tg3_stat64_t                    dma_read_prioq_full;
1949         tg3_stat64_t                    tx_comp_queue_full;
1950
1951         /* Statistics maintained by Host Coalescing. */
1952         tg3_stat64_t                    ring_set_send_prod_index;
1953         tg3_stat64_t                    ring_status_update;
1954         tg3_stat64_t                    nic_irqs;
1955         tg3_stat64_t                    nic_avoided_irqs;
1956         tg3_stat64_t                    nic_tx_threshold_hit;
1957
1958         u8                              __reserved4[0xb00-0x9c0];
1959 };
1960
1961 /* 'mapping' is superfluous as the chip does not write into
1962  * the tx/rx post rings so we could just fetch it from there.
1963  * But the cache behavior is better how we are doing it now.
1964  */
1965 struct ring_info {
1966         struct sk_buff                  *skb;
1967         DECLARE_PCI_UNMAP_ADDR(mapping)
1968 };
1969
1970 struct tx_ring_info {
1971         struct sk_buff                  *skb;
1972         DECLARE_PCI_UNMAP_ADDR(mapping)
1973         u32                             prev_vlan_tag;
1974 };
1975
1976 struct tg3_config_info {
1977         u32                             flags;
1978 };
1979
1980 struct tg3_link_config {
1981         /* Describes what we're trying to get. */
1982         u32                             advertising;
1983         u16                             speed;
1984         u8                              duplex;
1985         u8                              autoneg;
1986
1987         /* Describes what we actually have. */
1988         u16                             active_speed;
1989         u8                              active_duplex;
1990 #define SPEED_INVALID           0xffff
1991 #define DUPLEX_INVALID          0xff
1992 #define AUTONEG_INVALID         0xff
1993
1994         /* When we go in and out of low power mode we need
1995          * to swap with this state.
1996          */
1997         int                             phy_is_low_power;
1998         u16                             orig_speed;
1999         u8                              orig_duplex;
2000         u8                              orig_autoneg;
2001 };
2002
2003 struct tg3_bufmgr_config {
2004         u32             mbuf_read_dma_low_water;
2005         u32             mbuf_mac_rx_low_water;
2006         u32             mbuf_high_water;
2007
2008         u32             mbuf_read_dma_low_water_jumbo;
2009         u32             mbuf_mac_rx_low_water_jumbo;
2010         u32             mbuf_high_water_jumbo;
2011
2012         u32             dma_low_water;
2013         u32             dma_high_water;
2014 };
2015
2016 struct tg3_ethtool_stats {
2017         /* Statistics maintained by Receive MAC. */
2018         u64             rx_octets;
2019         u64             rx_fragments;
2020         u64             rx_ucast_packets;
2021         u64             rx_mcast_packets;
2022         u64             rx_bcast_packets;
2023         u64             rx_fcs_errors;
2024         u64             rx_align_errors;
2025         u64             rx_xon_pause_rcvd;
2026         u64             rx_xoff_pause_rcvd;
2027         u64             rx_mac_ctrl_rcvd;
2028         u64             rx_xoff_entered;
2029         u64             rx_frame_too_long_errors;
2030         u64             rx_jabbers;
2031         u64             rx_undersize_packets;
2032         u64             rx_in_length_errors;
2033         u64             rx_out_length_errors;
2034         u64             rx_64_or_less_octet_packets;
2035         u64             rx_65_to_127_octet_packets;
2036         u64             rx_128_to_255_octet_packets;
2037         u64             rx_256_to_511_octet_packets;
2038         u64             rx_512_to_1023_octet_packets;
2039         u64             rx_1024_to_1522_octet_packets;
2040         u64             rx_1523_to_2047_octet_packets;
2041         u64             rx_2048_to_4095_octet_packets;
2042         u64             rx_4096_to_8191_octet_packets;
2043         u64             rx_8192_to_9022_octet_packets;
2044
2045         /* Statistics maintained by Transmit MAC. */
2046         u64             tx_octets;
2047         u64             tx_collisions;
2048         u64             tx_xon_sent;
2049         u64             tx_xoff_sent;
2050         u64             tx_flow_control;
2051         u64             tx_mac_errors;
2052         u64             tx_single_collisions;
2053         u64             tx_mult_collisions;
2054         u64             tx_deferred;
2055         u64             tx_excessive_collisions;
2056         u64             tx_late_collisions;
2057         u64             tx_collide_2times;
2058         u64             tx_collide_3times;
2059         u64             tx_collide_4times;
2060         u64             tx_collide_5times;
2061         u64             tx_collide_6times;
2062         u64             tx_collide_7times;
2063         u64             tx_collide_8times;
2064         u64             tx_collide_9times;
2065         u64             tx_collide_10times;
2066         u64             tx_collide_11times;
2067         u64             tx_collide_12times;
2068         u64             tx_collide_13times;
2069         u64             tx_collide_14times;
2070         u64             tx_collide_15times;
2071         u64             tx_ucast_packets;
2072         u64             tx_mcast_packets;
2073         u64             tx_bcast_packets;
2074         u64             tx_carrier_sense_errors;
2075         u64             tx_discards;
2076         u64             tx_errors;
2077
2078         /* Statistics maintained by Receive List Placement. */
2079         u64             dma_writeq_full;
2080         u64             dma_write_prioq_full;
2081         u64             rxbds_empty;
2082         u64             rx_discards;
2083         u64             rx_errors;
2084         u64             rx_threshold_hit;
2085
2086         /* Statistics maintained by Send Data Initiator. */
2087         u64             dma_readq_full;
2088         u64             dma_read_prioq_full;
2089         u64             tx_comp_queue_full;
2090
2091         /* Statistics maintained by Host Coalescing. */
2092         u64             ring_set_send_prod_index;
2093         u64             ring_status_update;
2094         u64             nic_irqs;
2095         u64             nic_avoided_irqs;
2096         u64             nic_tx_threshold_hit;
2097 };
2098
2099 struct tg3 {
2100         /* begin "general, frequently-used members" cacheline section */
2101
2102         /* If the IRQ handler (which runs lockless) needs to be
2103          * quiesced, the following bitmask state is used.  The
2104          * SYNC flag is set by non-IRQ context code to initiate
2105          * the quiescence.
2106          *
2107          * When the IRQ handler notices that SYNC is set, it
2108          * disables interrupts and returns.
2109          *
2110          * When all outstanding IRQ handlers have returned after
2111          * the SYNC flag has been set, the setter can be assured
2112          * that interrupts will no longer get run.
2113          *
2114          * In this way all SMP driver locks are never acquired
2115          * in hw IRQ context, only sw IRQ context or lower.
2116          */
2117         unsigned int                    irq_sync;
2118
2119         /* SMP locking strategy:
2120          *
2121          * lock: Held during reset, PHY access, timer, and when
2122          *       updating tg3_flags and tg3_flags2.
2123          *
2124          * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
2125          *                netif_tx_lock when it needs to call
2126          *                netif_wake_queue.
2127          *
2128          * Both of these locks are to be held with BH safety.
2129          *
2130          * Because the IRQ handler, tg3_poll, and tg3_start_xmit
2131          * are running lockless, it is necessary to completely
2132          * quiesce the chip with tg3_netif_stop and tg3_full_lock
2133          * before reconfiguring the device.
2134          *
2135          * indirect_lock: Held when accessing registers indirectly
2136          *                with IRQ disabling.
2137          */
2138         spinlock_t                      lock;
2139         spinlock_t                      indirect_lock;
2140
2141         u32                             (*read32) (struct tg3 *, u32);
2142         void                            (*write32) (struct tg3 *, u32, u32);
2143         u32                             (*read32_mbox) (struct tg3 *, u32);
2144         void                            (*write32_mbox) (struct tg3 *, u32,
2145                                                          u32);
2146         void __iomem                    *regs;
2147         struct net_device               *dev;
2148         struct pci_dev                  *pdev;
2149
2150         struct tg3_hw_status            *hw_status;
2151         dma_addr_t                      status_mapping;
2152         u32                             last_tag;
2153
2154         u32                             msg_enable;
2155
2156         /* begin "tx thread" cacheline section */
2157         void                            (*write32_tx_mbox) (struct tg3 *, u32,
2158                                                             u32);
2159         u32                             tx_prod;
2160         u32                             tx_cons;
2161         u32                             tx_pending;
2162
2163         struct tg3_tx_buffer_desc       *tx_ring;
2164         struct tx_ring_info             *tx_buffers;
2165         dma_addr_t                      tx_desc_mapping;
2166
2167         /* begin "rx thread" cacheline section */
2168         struct napi_struct              napi;
2169         void                            (*write32_rx_mbox) (struct tg3 *, u32,
2170                                                             u32);
2171         u32                             rx_rcb_ptr;
2172         u32                             rx_std_ptr;
2173         u32                             rx_jumbo_ptr;
2174         u32                             rx_pending;
2175         u32                             rx_jumbo_pending;
2176 #if TG3_VLAN_TAG_USED
2177         struct vlan_group               *vlgrp;
2178 #endif
2179
2180         struct tg3_rx_buffer_desc       *rx_std;
2181         struct ring_info                *rx_std_buffers;
2182         dma_addr_t                      rx_std_mapping;
2183         u32                             rx_std_max_post;
2184
2185         struct tg3_rx_buffer_desc       *rx_jumbo;
2186         struct ring_info                *rx_jumbo_buffers;
2187         dma_addr_t                      rx_jumbo_mapping;
2188
2189         struct tg3_rx_buffer_desc       *rx_rcb;
2190         dma_addr_t                      rx_rcb_mapping;
2191
2192         u32                             rx_pkt_buf_sz;
2193
2194         /* begin "everything else" cacheline(s) section */
2195         struct net_device_stats         net_stats;
2196         struct net_device_stats         net_stats_prev;
2197         struct tg3_ethtool_stats        estats;
2198         struct tg3_ethtool_stats        estats_prev;
2199
2200         unsigned long                   phy_crc_errors;
2201
2202         u32                             rx_offset;
2203         u32                             tg3_flags;
2204 #define TG3_FLAG_TAGGED_STATUS          0x00000001
2205 #define TG3_FLAG_TXD_MBOX_HWBUG         0x00000002
2206 #define TG3_FLAG_RX_CHECKSUMS           0x00000004
2207 #define TG3_FLAG_USE_LINKCHG_REG        0x00000008
2208 #define TG3_FLAG_USE_MI_INTERRUPT       0x00000010
2209 #define TG3_FLAG_ENABLE_ASF             0x00000020
2210 #define TG3_FLAG_ASPM_WORKAROUND        0x00000040
2211 #define TG3_FLAG_POLL_SERDES            0x00000080
2212 #define TG3_FLAG_MBOX_WRITE_REORDER     0x00000100
2213 #define TG3_FLAG_PCIX_TARGET_HWBUG      0x00000200
2214 #define TG3_FLAG_WOL_SPEED_100MB        0x00000400
2215 #define TG3_FLAG_WOL_ENABLE             0x00000800
2216 #define TG3_FLAG_EEPROM_WRITE_PROT      0x00001000
2217 #define TG3_FLAG_NVRAM                  0x00002000
2218 #define TG3_FLAG_NVRAM_BUFFERED         0x00004000
2219 #define TG3_FLAG_RX_PAUSE               0x00008000
2220 #define TG3_FLAG_TX_PAUSE               0x00010000
2221 #define TG3_FLAG_PCIX_MODE              0x00020000
2222 #define TG3_FLAG_PCI_HIGH_SPEED         0x00040000
2223 #define TG3_FLAG_PCI_32BIT              0x00080000
2224 #define TG3_FLAG_SRAM_USE_CONFIG        0x00100000
2225 #define TG3_FLAG_TX_RECOVERY_PENDING    0x00200000
2226 #define TG3_FLAG_WOL_CAP                0x00400000
2227 #define TG3_FLAG_JUMBO_RING_ENABLE      0x00800000
2228 #define TG3_FLAG_10_100_ONLY            0x01000000
2229 #define TG3_FLAG_PAUSE_AUTONEG          0x02000000
2230 #define TG3_FLAG_CPMU_PRESENT           0x04000000
2231 #define TG3_FLAG_40BIT_DMA_BUG          0x08000000
2232 #define TG3_FLAG_BROKEN_CHECKSUMS       0x10000000
2233 #define TG3_FLAG_SUPPORT_MSI            0x20000000
2234 #define TG3_FLAG_CHIP_RESETTING         0x40000000
2235 #define TG3_FLAG_INIT_COMPLETE          0x80000000
2236         u32                             tg3_flags2;
2237 #define TG3_FLG2_RESTART_TIMER          0x00000001
2238 #define TG3_FLG2_TSO_BUG                0x00000002
2239 #define TG3_FLG2_NO_ETH_WIRE_SPEED      0x00000004
2240 #define TG3_FLG2_IS_5788                0x00000008
2241 #define TG3_FLG2_MAX_RXPEND_64          0x00000010
2242 #define TG3_FLG2_TSO_CAPABLE            0x00000020
2243 #define TG3_FLG2_PHY_ADC_BUG            0x00000040
2244 #define TG3_FLG2_PHY_5704_A0_BUG        0x00000080
2245 #define TG3_FLG2_PHY_BER_BUG            0x00000100
2246 #define TG3_FLG2_PCI_EXPRESS            0x00000200
2247 #define TG3_FLG2_ASF_NEW_HANDSHAKE      0x00000400
2248 #define TG3_FLG2_HW_AUTONEG             0x00000800
2249 #define TG3_FLG2_IS_NIC                 0x00001000
2250 #define TG3_FLG2_PHY_SERDES             0x00002000
2251 #define TG3_FLG2_CAPACITIVE_COUPLING    0x00004000
2252 #define TG3_FLG2_FLASH                  0x00008000
2253 #define TG3_FLG2_HW_TSO_1               0x00010000
2254 #define TG3_FLG2_SERDES_PREEMPHASIS     0x00020000
2255 #define TG3_FLG2_5705_PLUS              0x00040000
2256 #define TG3_FLG2_5750_PLUS              0x00080000
2257 #define TG3_FLG2_PROTECTED_NVRAM        0x00100000
2258 #define TG3_FLG2_USING_MSI              0x00200000
2259 #define TG3_FLG2_JUMBO_CAPABLE          0x00400000
2260 #define TG3_FLG2_MII_SERDES             0x00800000
2261 #define TG3_FLG2_ANY_SERDES             (TG3_FLG2_PHY_SERDES |  \
2262                                         TG3_FLG2_MII_SERDES)
2263 #define TG3_FLG2_PARALLEL_DETECT        0x01000000
2264 #define TG3_FLG2_ICH_WORKAROUND         0x02000000
2265 #define TG3_FLG2_5780_CLASS             0x04000000
2266 #define TG3_FLG2_HW_TSO_2               0x08000000
2267 #define TG3_FLG2_HW_TSO                 (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
2268 #define TG3_FLG2_1SHOT_MSI              0x10000000
2269 #define TG3_FLG2_PHY_JITTER_BUG         0x20000000
2270 #define TG3_FLG2_NO_FWARE_REPORTED      0x40000000
2271 #define TG3_FLG2_PHY_ADJUST_TRIM        0x80000000
2272
2273         struct timer_list               timer;
2274         u16                             timer_counter;
2275         u16                             timer_multiplier;
2276         u32                             timer_offset;
2277         u16                             asf_counter;
2278         u16                             asf_multiplier;
2279
2280         /* 1 second counter for transient serdes link events */
2281         u32                             serdes_counter;
2282 #define SERDES_AN_TIMEOUT_5704S         2
2283 #define SERDES_PARALLEL_DET_TIMEOUT     1
2284 #define SERDES_AN_TIMEOUT_5714S         1
2285
2286         struct tg3_link_config          link_config;
2287         struct tg3_bufmgr_config        bufmgr_config;
2288
2289         /* cache h/w values, often passed straight to h/w */
2290         u32                             rx_mode;
2291         u32                             tx_mode;
2292         u32                             mac_mode;
2293         u32                             mi_mode;
2294         u32                             misc_host_ctrl;
2295         u32                             grc_mode;
2296         u32                             grc_local_ctrl;
2297         u32                             dma_rwctrl;
2298         u32                             coalesce_mode;
2299         u32                             pwrmgmt_thresh;
2300
2301         /* PCI block */
2302         u32                             pci_chip_rev_id;
2303         u8                              pci_cacheline_sz;
2304         u8                              pci_lat_timer;
2305         u8                              pci_hdr_type;
2306         u8                              pci_bist;
2307
2308         int                             pm_cap;
2309         int                             msi_cap;
2310         int                             pcix_cap;
2311
2312         /* PHY info */
2313         u32                             phy_id;
2314 #define PHY_ID_MASK                     0xfffffff0
2315 #define PHY_ID_BCM5400                  0x60008040
2316 #define PHY_ID_BCM5401                  0x60008050
2317 #define PHY_ID_BCM5411                  0x60008070
2318 #define PHY_ID_BCM5701                  0x60008110
2319 #define PHY_ID_BCM5703                  0x60008160
2320 #define PHY_ID_BCM5704                  0x60008190
2321 #define PHY_ID_BCM5705                  0x600081a0
2322 #define PHY_ID_BCM5750                  0x60008180
2323 #define PHY_ID_BCM5752                  0x60008100
2324 #define PHY_ID_BCM5714                  0x60008340
2325 #define PHY_ID_BCM5780                  0x60008350
2326 #define PHY_ID_BCM5755                  0xbc050cc0
2327 #define PHY_ID_BCM5787                  0xbc050ce0
2328 #define PHY_ID_BCM5756                  0xbc050ed0
2329 #define PHY_ID_BCM5784                  0xbc050fa0
2330 #define PHY_ID_BCM5906                  0xdc00ac40
2331 #define PHY_ID_BCM8002                  0x60010140
2332 #define PHY_ID_INVALID                  0xffffffff
2333 #define PHY_ID_REV_MASK                 0x0000000f
2334 #define PHY_REV_BCM5401_B0              0x1
2335 #define PHY_REV_BCM5401_B2              0x3
2336 #define PHY_REV_BCM5401_C0              0x6
2337 #define PHY_REV_BCM5411_X0              0x1 /* Found on Netgear GA302T */
2338
2339         u32                             led_ctrl;
2340         u32                             pci_cmd;
2341
2342         char                            board_part_number[24];
2343         char                            fw_ver[16];
2344         u32                             nic_sram_data_cfg;
2345         u32                             pci_clock_ctrl;
2346         struct pci_dev                  *pdev_peer;
2347
2348         /* This macro assumes the passed PHY ID is already masked
2349          * with PHY_ID_MASK.
2350          */
2351 #define KNOWN_PHY_ID(X)         \
2352         ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
2353          (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
2354          (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
2355          (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
2356          (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
2357          (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
2358          (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
2359          (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM8002)
2360
2361         struct tg3_hw_stats             *hw_stats;
2362         dma_addr_t                      stats_mapping;
2363         struct work_struct              reset_task;
2364
2365         int                             nvram_lock_cnt;
2366         u32                             nvram_size;
2367         u32                             nvram_pagesize;
2368         u32                             nvram_jedecnum;
2369
2370 #define JEDEC_ATMEL                     0x1f
2371 #define JEDEC_ST                        0x20
2372 #define JEDEC_SAIFUN                    0x4f
2373 #define JEDEC_SST                       0xbf
2374
2375 #define ATMEL_AT24C64_CHIP_SIZE         (64 * 1024)
2376 #define ATMEL_AT24C64_PAGE_SIZE         (32)
2377
2378 #define ATMEL_AT24C512_CHIP_SIZE        (512 * 1024)
2379 #define ATMEL_AT24C512_PAGE_SIZE        (128)
2380
2381 #define ATMEL_AT45DB0X1B_PAGE_POS       9
2382 #define ATMEL_AT45DB0X1B_PAGE_SIZE      264
2383
2384 #define ATMEL_AT25F512_PAGE_SIZE        256
2385
2386 #define ST_M45PEX0_PAGE_SIZE            256
2387
2388 #define SAIFUN_SA25F0XX_PAGE_SIZE       256
2389
2390 #define SST_25VF0X0_PAGE_SIZE           4098
2391
2392         struct ethtool_coalesce         coal;
2393 };
2394
2395 #endif /* !(_T3_H) */