[TG3]: Fix array overrun in tg3_read_partno().
[linux-3.10.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40 #include <linux/dma-mapping.h>
41
42 #include <net/checksum.h>
43
44 #include <asm/system.h>
45 #include <asm/io.h>
46 #include <asm/byteorder.h>
47 #include <asm/uaccess.h>
48
49 #ifdef CONFIG_SPARC64
50 #include <asm/idprom.h>
51 #include <asm/oplib.h>
52 #include <asm/pbm.h>
53 #endif
54
55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56 #define TG3_VLAN_TAG_USED 1
57 #else
58 #define TG3_VLAN_TAG_USED 0
59 #endif
60
61 #ifdef NETIF_F_TSO
62 #define TG3_TSO_SUPPORT 1
63 #else
64 #define TG3_TSO_SUPPORT 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME         "tg3"
70 #define PFX DRV_MODULE_NAME     ": "
71 #define DRV_MODULE_VERSION      "3.68"
72 #define DRV_MODULE_RELDATE      "November 02, 2006"
73
74 #define TG3_DEF_MAC_MODE        0
75 #define TG3_DEF_RX_MODE         0
76 #define TG3_DEF_TX_MODE         0
77 #define TG3_DEF_MSG_ENABLE        \
78         (NETIF_MSG_DRV          | \
79          NETIF_MSG_PROBE        | \
80          NETIF_MSG_LINK         | \
81          NETIF_MSG_TIMER        | \
82          NETIF_MSG_IFDOWN       | \
83          NETIF_MSG_IFUP         | \
84          NETIF_MSG_RX_ERR       | \
85          NETIF_MSG_TX_ERR)
86
87 /* length of time before we decide the hardware is borked,
88  * and dev->tx_timeout() should be called to fix the problem
89  */
90 #define TG3_TX_TIMEOUT                  (5 * HZ)
91
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU                     60
94 #define TG3_MAX_MTU(tp) \
95         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
96
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98  * You can't change the ring sizes, but you can change where you place
99  * them in the NIC onboard memory.
100  */
101 #define TG3_RX_RING_SIZE                512
102 #define TG3_DEF_RX_RING_PENDING         200
103 #define TG3_RX_JUMBO_RING_SIZE          256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
105
106 /* Do not place this n-ring entries value into the tp struct itself,
107  * we really want to expose these constants to GCC so that modulo et
108  * al.  operations are done with shifts and masks instead of with
109  * hw multiply/modulo instructions.  Another solution would be to
110  * replace things like '% foo' with '& (foo - 1)'.
111  */
112 #define TG3_RX_RCB_RING_SIZE(tp)        \
113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
114
115 #define TG3_TX_RING_SIZE                512
116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
117
118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
119                                  TG3_RX_RING_SIZE)
120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121                                  TG3_RX_JUMBO_RING_SIZE)
122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123                                    TG3_RX_RCB_RING_SIZE(tp))
124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
125                                  TG3_TX_RING_SIZE)
126 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
128 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
129 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
130
131 /* minimum number of free TX descriptors required to wake up TX process */
132 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
133
134 /* number of ETHTOOL_GSTATS u64's */
135 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
136
137 #define TG3_NUM_TEST            6
138
139 static char version[] __devinitdata =
140         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
141
142 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
143 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
144 MODULE_LICENSE("GPL");
145 MODULE_VERSION(DRV_MODULE_VERSION);
146
147 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
148 module_param(tg3_debug, int, 0);
149 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
150
151 static struct pci_device_id tg3_pci_tbl[] = {
152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
204         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
205         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
206         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
207         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
208         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
209         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
210         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
211         {}
212 };
213
214 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
215
216 static const struct {
217         const char string[ETH_GSTRING_LEN];
218 } ethtool_stats_keys[TG3_NUM_STATS] = {
219         { "rx_octets" },
220         { "rx_fragments" },
221         { "rx_ucast_packets" },
222         { "rx_mcast_packets" },
223         { "rx_bcast_packets" },
224         { "rx_fcs_errors" },
225         { "rx_align_errors" },
226         { "rx_xon_pause_rcvd" },
227         { "rx_xoff_pause_rcvd" },
228         { "rx_mac_ctrl_rcvd" },
229         { "rx_xoff_entered" },
230         { "rx_frame_too_long_errors" },
231         { "rx_jabbers" },
232         { "rx_undersize_packets" },
233         { "rx_in_length_errors" },
234         { "rx_out_length_errors" },
235         { "rx_64_or_less_octet_packets" },
236         { "rx_65_to_127_octet_packets" },
237         { "rx_128_to_255_octet_packets" },
238         { "rx_256_to_511_octet_packets" },
239         { "rx_512_to_1023_octet_packets" },
240         { "rx_1024_to_1522_octet_packets" },
241         { "rx_1523_to_2047_octet_packets" },
242         { "rx_2048_to_4095_octet_packets" },
243         { "rx_4096_to_8191_octet_packets" },
244         { "rx_8192_to_9022_octet_packets" },
245
246         { "tx_octets" },
247         { "tx_collisions" },
248
249         { "tx_xon_sent" },
250         { "tx_xoff_sent" },
251         { "tx_flow_control" },
252         { "tx_mac_errors" },
253         { "tx_single_collisions" },
254         { "tx_mult_collisions" },
255         { "tx_deferred" },
256         { "tx_excessive_collisions" },
257         { "tx_late_collisions" },
258         { "tx_collide_2times" },
259         { "tx_collide_3times" },
260         { "tx_collide_4times" },
261         { "tx_collide_5times" },
262         { "tx_collide_6times" },
263         { "tx_collide_7times" },
264         { "tx_collide_8times" },
265         { "tx_collide_9times" },
266         { "tx_collide_10times" },
267         { "tx_collide_11times" },
268         { "tx_collide_12times" },
269         { "tx_collide_13times" },
270         { "tx_collide_14times" },
271         { "tx_collide_15times" },
272         { "tx_ucast_packets" },
273         { "tx_mcast_packets" },
274         { "tx_bcast_packets" },
275         { "tx_carrier_sense_errors" },
276         { "tx_discards" },
277         { "tx_errors" },
278
279         { "dma_writeq_full" },
280         { "dma_write_prioq_full" },
281         { "rxbds_empty" },
282         { "rx_discards" },
283         { "rx_errors" },
284         { "rx_threshold_hit" },
285
286         { "dma_readq_full" },
287         { "dma_read_prioq_full" },
288         { "tx_comp_queue_full" },
289
290         { "ring_set_send_prod_index" },
291         { "ring_status_update" },
292         { "nic_irqs" },
293         { "nic_avoided_irqs" },
294         { "nic_tx_threshold_hit" }
295 };
296
297 static const struct {
298         const char string[ETH_GSTRING_LEN];
299 } ethtool_test_keys[TG3_NUM_TEST] = {
300         { "nvram test     (online) " },
301         { "link test      (online) " },
302         { "register test  (offline)" },
303         { "memory test    (offline)" },
304         { "loopback test  (offline)" },
305         { "interrupt test (offline)" },
306 };
307
308 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
309 {
310         writel(val, tp->regs + off);
311 }
312
313 static u32 tg3_read32(struct tg3 *tp, u32 off)
314 {
315         return (readl(tp->regs + off));
316 }
317
318 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
319 {
320         unsigned long flags;
321
322         spin_lock_irqsave(&tp->indirect_lock, flags);
323         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
324         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
325         spin_unlock_irqrestore(&tp->indirect_lock, flags);
326 }
327
328 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
329 {
330         writel(val, tp->regs + off);
331         readl(tp->regs + off);
332 }
333
334 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
335 {
336         unsigned long flags;
337         u32 val;
338
339         spin_lock_irqsave(&tp->indirect_lock, flags);
340         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
341         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
342         spin_unlock_irqrestore(&tp->indirect_lock, flags);
343         return val;
344 }
345
346 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
347 {
348         unsigned long flags;
349
350         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
351                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
352                                        TG3_64BIT_REG_LOW, val);
353                 return;
354         }
355         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
356                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
357                                        TG3_64BIT_REG_LOW, val);
358                 return;
359         }
360
361         spin_lock_irqsave(&tp->indirect_lock, flags);
362         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
363         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
364         spin_unlock_irqrestore(&tp->indirect_lock, flags);
365
366         /* In indirect mode when disabling interrupts, we also need
367          * to clear the interrupt bit in the GRC local ctrl register.
368          */
369         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
370             (val == 0x1)) {
371                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
372                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
373         }
374 }
375
376 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
377 {
378         unsigned long flags;
379         u32 val;
380
381         spin_lock_irqsave(&tp->indirect_lock, flags);
382         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
383         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
384         spin_unlock_irqrestore(&tp->indirect_lock, flags);
385         return val;
386 }
387
388 /* usec_wait specifies the wait time in usec when writing to certain registers
389  * where it is unsafe to read back the register without some delay.
390  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
391  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
392  */
393 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
394 {
395         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
396             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
397                 /* Non-posted methods */
398                 tp->write32(tp, off, val);
399         else {
400                 /* Posted method */
401                 tg3_write32(tp, off, val);
402                 if (usec_wait)
403                         udelay(usec_wait);
404                 tp->read32(tp, off);
405         }
406         /* Wait again after the read for the posted method to guarantee that
407          * the wait time is met.
408          */
409         if (usec_wait)
410                 udelay(usec_wait);
411 }
412
413 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
414 {
415         tp->write32_mbox(tp, off, val);
416         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
417             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
418                 tp->read32_mbox(tp, off);
419 }
420
421 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
422 {
423         void __iomem *mbox = tp->regs + off;
424         writel(val, mbox);
425         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
426                 writel(val, mbox);
427         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
428                 readl(mbox);
429 }
430
431 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
432 {
433         return (readl(tp->regs + off + GRCMBOX_BASE));
434 }
435
436 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
437 {
438         writel(val, tp->regs + off + GRCMBOX_BASE);
439 }
440
441 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
442 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
443 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
444 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
445 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
446
447 #define tw32(reg,val)           tp->write32(tp, reg, val)
448 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
449 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
450 #define tr32(reg)               tp->read32(tp, reg)
451
452 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
453 {
454         unsigned long flags;
455
456         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
457             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
458                 return;
459
460         spin_lock_irqsave(&tp->indirect_lock, flags);
461         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
462                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
463                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
464
465                 /* Always leave this as zero. */
466                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
467         } else {
468                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
469                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
470
471                 /* Always leave this as zero. */
472                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
473         }
474         spin_unlock_irqrestore(&tp->indirect_lock, flags);
475 }
476
477 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
478 {
479         unsigned long flags;
480
481         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
482             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
483                 *val = 0;
484                 return;
485         }
486
487         spin_lock_irqsave(&tp->indirect_lock, flags);
488         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
489                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
490                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
491
492                 /* Always leave this as zero. */
493                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
494         } else {
495                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
496                 *val = tr32(TG3PCI_MEM_WIN_DATA);
497
498                 /* Always leave this as zero. */
499                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
500         }
501         spin_unlock_irqrestore(&tp->indirect_lock, flags);
502 }
503
504 static void tg3_disable_ints(struct tg3 *tp)
505 {
506         tw32(TG3PCI_MISC_HOST_CTRL,
507              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
508         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
509 }
510
511 static inline void tg3_cond_int(struct tg3 *tp)
512 {
513         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
514             (tp->hw_status->status & SD_STATUS_UPDATED))
515                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
516         else
517                 tw32(HOSTCC_MODE, tp->coalesce_mode |
518                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
519 }
520
521 static void tg3_enable_ints(struct tg3 *tp)
522 {
523         tp->irq_sync = 0;
524         wmb();
525
526         tw32(TG3PCI_MISC_HOST_CTRL,
527              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
528         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
529                        (tp->last_tag << 24));
530         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
531                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
532                                (tp->last_tag << 24));
533         tg3_cond_int(tp);
534 }
535
536 static inline unsigned int tg3_has_work(struct tg3 *tp)
537 {
538         struct tg3_hw_status *sblk = tp->hw_status;
539         unsigned int work_exists = 0;
540
541         /* check for phy events */
542         if (!(tp->tg3_flags &
543               (TG3_FLAG_USE_LINKCHG_REG |
544                TG3_FLAG_POLL_SERDES))) {
545                 if (sblk->status & SD_STATUS_LINK_CHG)
546                         work_exists = 1;
547         }
548         /* check for RX/TX work to do */
549         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
550             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
551                 work_exists = 1;
552
553         return work_exists;
554 }
555
556 /* tg3_restart_ints
557  *  similar to tg3_enable_ints, but it accurately determines whether there
558  *  is new work pending and can return without flushing the PIO write
559  *  which reenables interrupts
560  */
561 static void tg3_restart_ints(struct tg3 *tp)
562 {
563         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
564                      tp->last_tag << 24);
565         mmiowb();
566
567         /* When doing tagged status, this work check is unnecessary.
568          * The last_tag we write above tells the chip which piece of
569          * work we've completed.
570          */
571         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
572             tg3_has_work(tp))
573                 tw32(HOSTCC_MODE, tp->coalesce_mode |
574                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
575 }
576
577 static inline void tg3_netif_stop(struct tg3 *tp)
578 {
579         tp->dev->trans_start = jiffies; /* prevent tx timeout */
580         netif_poll_disable(tp->dev);
581         netif_tx_disable(tp->dev);
582 }
583
584 static inline void tg3_netif_start(struct tg3 *tp)
585 {
586         netif_wake_queue(tp->dev);
587         /* NOTE: unconditional netif_wake_queue is only appropriate
588          * so long as all callers are assured to have free tx slots
589          * (such as after tg3_init_hw)
590          */
591         netif_poll_enable(tp->dev);
592         tp->hw_status->status |= SD_STATUS_UPDATED;
593         tg3_enable_ints(tp);
594 }
595
596 static void tg3_switch_clocks(struct tg3 *tp)
597 {
598         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
599         u32 orig_clock_ctrl;
600
601         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
602                 return;
603
604         orig_clock_ctrl = clock_ctrl;
605         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
606                        CLOCK_CTRL_CLKRUN_OENABLE |
607                        0x1f);
608         tp->pci_clock_ctrl = clock_ctrl;
609
610         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
611                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
612                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
613                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
614                 }
615         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
616                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
617                             clock_ctrl |
618                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
619                             40);
620                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
621                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
622                             40);
623         }
624         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
625 }
626
627 #define PHY_BUSY_LOOPS  5000
628
629 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
630 {
631         u32 frame_val;
632         unsigned int loops;
633         int ret;
634
635         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
636                 tw32_f(MAC_MI_MODE,
637                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
638                 udelay(80);
639         }
640
641         *val = 0x0;
642
643         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
644                       MI_COM_PHY_ADDR_MASK);
645         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
646                       MI_COM_REG_ADDR_MASK);
647         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
648
649         tw32_f(MAC_MI_COM, frame_val);
650
651         loops = PHY_BUSY_LOOPS;
652         while (loops != 0) {
653                 udelay(10);
654                 frame_val = tr32(MAC_MI_COM);
655
656                 if ((frame_val & MI_COM_BUSY) == 0) {
657                         udelay(5);
658                         frame_val = tr32(MAC_MI_COM);
659                         break;
660                 }
661                 loops -= 1;
662         }
663
664         ret = -EBUSY;
665         if (loops != 0) {
666                 *val = frame_val & MI_COM_DATA_MASK;
667                 ret = 0;
668         }
669
670         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
671                 tw32_f(MAC_MI_MODE, tp->mi_mode);
672                 udelay(80);
673         }
674
675         return ret;
676 }
677
678 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
679 {
680         u32 frame_val;
681         unsigned int loops;
682         int ret;
683
684         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
685             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
686                 return 0;
687
688         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
689                 tw32_f(MAC_MI_MODE,
690                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
691                 udelay(80);
692         }
693
694         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
695                       MI_COM_PHY_ADDR_MASK);
696         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
697                       MI_COM_REG_ADDR_MASK);
698         frame_val |= (val & MI_COM_DATA_MASK);
699         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
700
701         tw32_f(MAC_MI_COM, frame_val);
702
703         loops = PHY_BUSY_LOOPS;
704         while (loops != 0) {
705                 udelay(10);
706                 frame_val = tr32(MAC_MI_COM);
707                 if ((frame_val & MI_COM_BUSY) == 0) {
708                         udelay(5);
709                         frame_val = tr32(MAC_MI_COM);
710                         break;
711                 }
712                 loops -= 1;
713         }
714
715         ret = -EBUSY;
716         if (loops != 0)
717                 ret = 0;
718
719         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
720                 tw32_f(MAC_MI_MODE, tp->mi_mode);
721                 udelay(80);
722         }
723
724         return ret;
725 }
726
727 static void tg3_phy_set_wirespeed(struct tg3 *tp)
728 {
729         u32 val;
730
731         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
732                 return;
733
734         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
735             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
736                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
737                              (val | (1 << 15) | (1 << 4)));
738 }
739
740 static int tg3_bmcr_reset(struct tg3 *tp)
741 {
742         u32 phy_control;
743         int limit, err;
744
745         /* OK, reset it, and poll the BMCR_RESET bit until it
746          * clears or we time out.
747          */
748         phy_control = BMCR_RESET;
749         err = tg3_writephy(tp, MII_BMCR, phy_control);
750         if (err != 0)
751                 return -EBUSY;
752
753         limit = 5000;
754         while (limit--) {
755                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
756                 if (err != 0)
757                         return -EBUSY;
758
759                 if ((phy_control & BMCR_RESET) == 0) {
760                         udelay(40);
761                         break;
762                 }
763                 udelay(10);
764         }
765         if (limit <= 0)
766                 return -EBUSY;
767
768         return 0;
769 }
770
771 static int tg3_wait_macro_done(struct tg3 *tp)
772 {
773         int limit = 100;
774
775         while (limit--) {
776                 u32 tmp32;
777
778                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
779                         if ((tmp32 & 0x1000) == 0)
780                                 break;
781                 }
782         }
783         if (limit <= 0)
784                 return -EBUSY;
785
786         return 0;
787 }
788
789 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
790 {
791         static const u32 test_pat[4][6] = {
792         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
793         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
794         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
795         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
796         };
797         int chan;
798
799         for (chan = 0; chan < 4; chan++) {
800                 int i;
801
802                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
803                              (chan * 0x2000) | 0x0200);
804                 tg3_writephy(tp, 0x16, 0x0002);
805
806                 for (i = 0; i < 6; i++)
807                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
808                                      test_pat[chan][i]);
809
810                 tg3_writephy(tp, 0x16, 0x0202);
811                 if (tg3_wait_macro_done(tp)) {
812                         *resetp = 1;
813                         return -EBUSY;
814                 }
815
816                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
817                              (chan * 0x2000) | 0x0200);
818                 tg3_writephy(tp, 0x16, 0x0082);
819                 if (tg3_wait_macro_done(tp)) {
820                         *resetp = 1;
821                         return -EBUSY;
822                 }
823
824                 tg3_writephy(tp, 0x16, 0x0802);
825                 if (tg3_wait_macro_done(tp)) {
826                         *resetp = 1;
827                         return -EBUSY;
828                 }
829
830                 for (i = 0; i < 6; i += 2) {
831                         u32 low, high;
832
833                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
834                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
835                             tg3_wait_macro_done(tp)) {
836                                 *resetp = 1;
837                                 return -EBUSY;
838                         }
839                         low &= 0x7fff;
840                         high &= 0x000f;
841                         if (low != test_pat[chan][i] ||
842                             high != test_pat[chan][i+1]) {
843                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
844                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
845                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
846
847                                 return -EBUSY;
848                         }
849                 }
850         }
851
852         return 0;
853 }
854
855 static int tg3_phy_reset_chanpat(struct tg3 *tp)
856 {
857         int chan;
858
859         for (chan = 0; chan < 4; chan++) {
860                 int i;
861
862                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
863                              (chan * 0x2000) | 0x0200);
864                 tg3_writephy(tp, 0x16, 0x0002);
865                 for (i = 0; i < 6; i++)
866                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
867                 tg3_writephy(tp, 0x16, 0x0202);
868                 if (tg3_wait_macro_done(tp))
869                         return -EBUSY;
870         }
871
872         return 0;
873 }
874
875 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
876 {
877         u32 reg32, phy9_orig;
878         int retries, do_phy_reset, err;
879
880         retries = 10;
881         do_phy_reset = 1;
882         do {
883                 if (do_phy_reset) {
884                         err = tg3_bmcr_reset(tp);
885                         if (err)
886                                 return err;
887                         do_phy_reset = 0;
888                 }
889
890                 /* Disable transmitter and interrupt.  */
891                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
892                         continue;
893
894                 reg32 |= 0x3000;
895                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
896
897                 /* Set full-duplex, 1000 mbps.  */
898                 tg3_writephy(tp, MII_BMCR,
899                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
900
901                 /* Set to master mode.  */
902                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
903                         continue;
904
905                 tg3_writephy(tp, MII_TG3_CTRL,
906                              (MII_TG3_CTRL_AS_MASTER |
907                               MII_TG3_CTRL_ENABLE_AS_MASTER));
908
909                 /* Enable SM_DSP_CLOCK and 6dB.  */
910                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
911
912                 /* Block the PHY control access.  */
913                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
914                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
915
916                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
917                 if (!err)
918                         break;
919         } while (--retries);
920
921         err = tg3_phy_reset_chanpat(tp);
922         if (err)
923                 return err;
924
925         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
926         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
927
928         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
929         tg3_writephy(tp, 0x16, 0x0000);
930
931         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
932             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
933                 /* Set Extended packet length bit for jumbo frames */
934                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
935         }
936         else {
937                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
938         }
939
940         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
941
942         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
943                 reg32 &= ~0x3000;
944                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
945         } else if (!err)
946                 err = -EBUSY;
947
948         return err;
949 }
950
951 static void tg3_link_report(struct tg3 *);
952
953 /* This will reset the tigon3 PHY if there is no valid
954  * link unless the FORCE argument is non-zero.
955  */
956 static int tg3_phy_reset(struct tg3 *tp)
957 {
958         u32 phy_status;
959         int err;
960
961         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
962         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
963         if (err != 0)
964                 return -EBUSY;
965
966         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
967                 netif_carrier_off(tp->dev);
968                 tg3_link_report(tp);
969         }
970
971         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
972             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
973             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
974                 err = tg3_phy_reset_5703_4_5(tp);
975                 if (err)
976                         return err;
977                 goto out;
978         }
979
980         err = tg3_bmcr_reset(tp);
981         if (err)
982                 return err;
983
984 out:
985         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
986                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
987                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
988                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
989                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
990                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
991                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
992         }
993         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
994                 tg3_writephy(tp, 0x1c, 0x8d68);
995                 tg3_writephy(tp, 0x1c, 0x8d68);
996         }
997         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
998                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
999                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1000                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1001                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1002                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1003                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1004                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1005                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1006         }
1007         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1008                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1009                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1010                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1011                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1012         }
1013         /* Set Extended packet length bit (bit 14) on all chips that */
1014         /* support jumbo frames */
1015         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1016                 /* Cannot do read-modify-write on 5401 */
1017                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1018         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1019                 u32 phy_reg;
1020
1021                 /* Set bit 14 with read-modify-write to preserve other bits */
1022                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1023                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1024                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1025         }
1026
1027         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1028          * jumbo frames transmission.
1029          */
1030         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1031                 u32 phy_reg;
1032
1033                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1034                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1035                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1036         }
1037
1038         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1039                 u32 phy_reg;
1040
1041                 /* adjust output voltage */
1042                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1043
1044                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1045                         u32 phy_reg2;
1046
1047                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1048                                      phy_reg | MII_TG3_EPHY_SHADOW_EN);
1049                         /* Enable auto-MDIX */
1050                         if (!tg3_readphy(tp, 0x10, &phy_reg2))
1051                                 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1052                         tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1053                 }
1054         }
1055
1056         tg3_phy_set_wirespeed(tp);
1057         return 0;
1058 }
1059
1060 static void tg3_frob_aux_power(struct tg3 *tp)
1061 {
1062         struct tg3 *tp_peer = tp;
1063
1064         if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1065                 return;
1066
1067         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1068             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1069                 struct net_device *dev_peer;
1070
1071                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1072                 /* remove_one() may have been run on the peer. */
1073                 if (!dev_peer)
1074                         tp_peer = tp;
1075                 else
1076                         tp_peer = netdev_priv(dev_peer);
1077         }
1078
1079         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1080             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1081             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1082             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1083                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1084                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1085                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1086                                     (GRC_LCLCTRL_GPIO_OE0 |
1087                                      GRC_LCLCTRL_GPIO_OE1 |
1088                                      GRC_LCLCTRL_GPIO_OE2 |
1089                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1090                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1091                                     100);
1092                 } else {
1093                         u32 no_gpio2;
1094                         u32 grc_local_ctrl = 0;
1095
1096                         if (tp_peer != tp &&
1097                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1098                                 return;
1099
1100                         /* Workaround to prevent overdrawing Amps. */
1101                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1102                             ASIC_REV_5714) {
1103                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1104                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1105                                             grc_local_ctrl, 100);
1106                         }
1107
1108                         /* On 5753 and variants, GPIO2 cannot be used. */
1109                         no_gpio2 = tp->nic_sram_data_cfg &
1110                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1111
1112                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1113                                          GRC_LCLCTRL_GPIO_OE1 |
1114                                          GRC_LCLCTRL_GPIO_OE2 |
1115                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1116                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1117                         if (no_gpio2) {
1118                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1119                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1120                         }
1121                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1122                                                     grc_local_ctrl, 100);
1123
1124                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1125
1126                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1127                                                     grc_local_ctrl, 100);
1128
1129                         if (!no_gpio2) {
1130                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1131                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1132                                             grc_local_ctrl, 100);
1133                         }
1134                 }
1135         } else {
1136                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1137                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1138                         if (tp_peer != tp &&
1139                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1140                                 return;
1141
1142                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1143                                     (GRC_LCLCTRL_GPIO_OE1 |
1144                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1145
1146                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1147                                     GRC_LCLCTRL_GPIO_OE1, 100);
1148
1149                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1150                                     (GRC_LCLCTRL_GPIO_OE1 |
1151                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1152                 }
1153         }
1154 }
1155
1156 static int tg3_setup_phy(struct tg3 *, int);
1157
1158 #define RESET_KIND_SHUTDOWN     0
1159 #define RESET_KIND_INIT         1
1160 #define RESET_KIND_SUSPEND      2
1161
1162 static void tg3_write_sig_post_reset(struct tg3 *, int);
1163 static int tg3_halt_cpu(struct tg3 *, u32);
1164 static int tg3_nvram_lock(struct tg3 *);
1165 static void tg3_nvram_unlock(struct tg3 *);
1166
1167 static void tg3_power_down_phy(struct tg3 *tp)
1168 {
1169         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
1170                 return;
1171
1172         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
1173                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1174                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1175                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1176         }
1177
1178         /* The PHY should not be powered down on some chips because
1179          * of bugs.
1180          */
1181         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1182             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1183             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1184              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1185                 return;
1186         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1187 }
1188
1189 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1190 {
1191         u32 misc_host_ctrl;
1192         u16 power_control, power_caps;
1193         int pm = tp->pm_cap;
1194
1195         /* Make sure register accesses (indirect or otherwise)
1196          * will function correctly.
1197          */
1198         pci_write_config_dword(tp->pdev,
1199                                TG3PCI_MISC_HOST_CTRL,
1200                                tp->misc_host_ctrl);
1201
1202         pci_read_config_word(tp->pdev,
1203                              pm + PCI_PM_CTRL,
1204                              &power_control);
1205         power_control |= PCI_PM_CTRL_PME_STATUS;
1206         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1207         switch (state) {
1208         case PCI_D0:
1209                 power_control |= 0;
1210                 pci_write_config_word(tp->pdev,
1211                                       pm + PCI_PM_CTRL,
1212                                       power_control);
1213                 udelay(100);    /* Delay after power state change */
1214
1215                 /* Switch out of Vaux if it is not a LOM */
1216                 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
1217                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1218
1219                 return 0;
1220
1221         case PCI_D1:
1222                 power_control |= 1;
1223                 break;
1224
1225         case PCI_D2:
1226                 power_control |= 2;
1227                 break;
1228
1229         case PCI_D3hot:
1230                 power_control |= 3;
1231                 break;
1232
1233         default:
1234                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1235                        "requested.\n",
1236                        tp->dev->name, state);
1237                 return -EINVAL;
1238         };
1239
1240         power_control |= PCI_PM_CTRL_PME_ENABLE;
1241
1242         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1243         tw32(TG3PCI_MISC_HOST_CTRL,
1244              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1245
1246         if (tp->link_config.phy_is_low_power == 0) {
1247                 tp->link_config.phy_is_low_power = 1;
1248                 tp->link_config.orig_speed = tp->link_config.speed;
1249                 tp->link_config.orig_duplex = tp->link_config.duplex;
1250                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1251         }
1252
1253         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1254                 tp->link_config.speed = SPEED_10;
1255                 tp->link_config.duplex = DUPLEX_HALF;
1256                 tp->link_config.autoneg = AUTONEG_ENABLE;
1257                 tg3_setup_phy(tp, 0);
1258         }
1259
1260         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1261                 u32 val;
1262
1263                 val = tr32(GRC_VCPU_EXT_CTRL);
1264                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1265         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1266                 int i;
1267                 u32 val;
1268
1269                 for (i = 0; i < 200; i++) {
1270                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1271                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1272                                 break;
1273                         msleep(1);
1274                 }
1275         }
1276         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1277                                              WOL_DRV_STATE_SHUTDOWN |
1278                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1279
1280         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1281
1282         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1283                 u32 mac_mode;
1284
1285                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1286                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1287                         udelay(40);
1288
1289                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1290                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1291                         else
1292                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1293
1294                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1295                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1296                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1297                 } else {
1298                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1299                 }
1300
1301                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1302                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1303
1304                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1305                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1306                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1307
1308                 tw32_f(MAC_MODE, mac_mode);
1309                 udelay(100);
1310
1311                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1312                 udelay(10);
1313         }
1314
1315         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1316             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1317              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1318                 u32 base_val;
1319
1320                 base_val = tp->pci_clock_ctrl;
1321                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1322                              CLOCK_CTRL_TXCLK_DISABLE);
1323
1324                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1325                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1326         } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1327                 /* do nothing */
1328         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1329                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1330                 u32 newbits1, newbits2;
1331
1332                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1333                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1334                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1335                                     CLOCK_CTRL_TXCLK_DISABLE |
1336                                     CLOCK_CTRL_ALTCLK);
1337                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1338                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1339                         newbits1 = CLOCK_CTRL_625_CORE;
1340                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1341                 } else {
1342                         newbits1 = CLOCK_CTRL_ALTCLK;
1343                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1344                 }
1345
1346                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1347                             40);
1348
1349                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1350                             40);
1351
1352                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1353                         u32 newbits3;
1354
1355                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1356                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1357                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1358                                             CLOCK_CTRL_TXCLK_DISABLE |
1359                                             CLOCK_CTRL_44MHZ_CORE);
1360                         } else {
1361                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1362                         }
1363
1364                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1365                                     tp->pci_clock_ctrl | newbits3, 40);
1366                 }
1367         }
1368
1369         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1370             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1371                 tg3_power_down_phy(tp);
1372
1373         tg3_frob_aux_power(tp);
1374
1375         /* Workaround for unstable PLL clock */
1376         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1377             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1378                 u32 val = tr32(0x7d00);
1379
1380                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1381                 tw32(0x7d00, val);
1382                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1383                         int err;
1384
1385                         err = tg3_nvram_lock(tp);
1386                         tg3_halt_cpu(tp, RX_CPU_BASE);
1387                         if (!err)
1388                                 tg3_nvram_unlock(tp);
1389                 }
1390         }
1391
1392         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1393
1394         /* Finally, set the new power state. */
1395         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1396         udelay(100);    /* Delay after power state change */
1397
1398         return 0;
1399 }
1400
1401 static void tg3_link_report(struct tg3 *tp)
1402 {
1403         if (!netif_carrier_ok(tp->dev)) {
1404                 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1405         } else {
1406                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1407                        tp->dev->name,
1408                        (tp->link_config.active_speed == SPEED_1000 ?
1409                         1000 :
1410                         (tp->link_config.active_speed == SPEED_100 ?
1411                          100 : 10)),
1412                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1413                         "full" : "half"));
1414
1415                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1416                        "%s for RX.\n",
1417                        tp->dev->name,
1418                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1419                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1420         }
1421 }
1422
1423 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1424 {
1425         u32 new_tg3_flags = 0;
1426         u32 old_rx_mode = tp->rx_mode;
1427         u32 old_tx_mode = tp->tx_mode;
1428
1429         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1430
1431                 /* Convert 1000BaseX flow control bits to 1000BaseT
1432                  * bits before resolving flow control.
1433                  */
1434                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1435                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1436                                        ADVERTISE_PAUSE_ASYM);
1437                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1438
1439                         if (local_adv & ADVERTISE_1000XPAUSE)
1440                                 local_adv |= ADVERTISE_PAUSE_CAP;
1441                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1442                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1443                         if (remote_adv & LPA_1000XPAUSE)
1444                                 remote_adv |= LPA_PAUSE_CAP;
1445                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1446                                 remote_adv |= LPA_PAUSE_ASYM;
1447                 }
1448
1449                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1450                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1451                                 if (remote_adv & LPA_PAUSE_CAP)
1452                                         new_tg3_flags |=
1453                                                 (TG3_FLAG_RX_PAUSE |
1454                                                 TG3_FLAG_TX_PAUSE);
1455                                 else if (remote_adv & LPA_PAUSE_ASYM)
1456                                         new_tg3_flags |=
1457                                                 (TG3_FLAG_RX_PAUSE);
1458                         } else {
1459                                 if (remote_adv & LPA_PAUSE_CAP)
1460                                         new_tg3_flags |=
1461                                                 (TG3_FLAG_RX_PAUSE |
1462                                                 TG3_FLAG_TX_PAUSE);
1463                         }
1464                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1465                         if ((remote_adv & LPA_PAUSE_CAP) &&
1466                         (remote_adv & LPA_PAUSE_ASYM))
1467                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1468                 }
1469
1470                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1471                 tp->tg3_flags |= new_tg3_flags;
1472         } else {
1473                 new_tg3_flags = tp->tg3_flags;
1474         }
1475
1476         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1477                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1478         else
1479                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1480
1481         if (old_rx_mode != tp->rx_mode) {
1482                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1483         }
1484
1485         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1486                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1487         else
1488                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1489
1490         if (old_tx_mode != tp->tx_mode) {
1491                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1492         }
1493 }
1494
1495 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1496 {
1497         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1498         case MII_TG3_AUX_STAT_10HALF:
1499                 *speed = SPEED_10;
1500                 *duplex = DUPLEX_HALF;
1501                 break;
1502
1503         case MII_TG3_AUX_STAT_10FULL:
1504                 *speed = SPEED_10;
1505                 *duplex = DUPLEX_FULL;
1506                 break;
1507
1508         case MII_TG3_AUX_STAT_100HALF:
1509                 *speed = SPEED_100;
1510                 *duplex = DUPLEX_HALF;
1511                 break;
1512
1513         case MII_TG3_AUX_STAT_100FULL:
1514                 *speed = SPEED_100;
1515                 *duplex = DUPLEX_FULL;
1516                 break;
1517
1518         case MII_TG3_AUX_STAT_1000HALF:
1519                 *speed = SPEED_1000;
1520                 *duplex = DUPLEX_HALF;
1521                 break;
1522
1523         case MII_TG3_AUX_STAT_1000FULL:
1524                 *speed = SPEED_1000;
1525                 *duplex = DUPLEX_FULL;
1526                 break;
1527
1528         default:
1529                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1530                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1531                                  SPEED_10;
1532                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1533                                   DUPLEX_HALF;
1534                         break;
1535                 }
1536                 *speed = SPEED_INVALID;
1537                 *duplex = DUPLEX_INVALID;
1538                 break;
1539         };
1540 }
1541
1542 static void tg3_phy_copper_begin(struct tg3 *tp)
1543 {
1544         u32 new_adv;
1545         int i;
1546
1547         if (tp->link_config.phy_is_low_power) {
1548                 /* Entering low power mode.  Disable gigabit and
1549                  * 100baseT advertisements.
1550                  */
1551                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1552
1553                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1554                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1555                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1556                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1557
1558                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1559         } else if (tp->link_config.speed == SPEED_INVALID) {
1560                 tp->link_config.advertising =
1561                         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1562                          ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1563                          ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1564                          ADVERTISED_Autoneg | ADVERTISED_MII);
1565
1566                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1567                         tp->link_config.advertising &=
1568                                 ~(ADVERTISED_1000baseT_Half |
1569                                   ADVERTISED_1000baseT_Full);
1570
1571                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1572                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1573                         new_adv |= ADVERTISE_10HALF;
1574                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1575                         new_adv |= ADVERTISE_10FULL;
1576                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1577                         new_adv |= ADVERTISE_100HALF;
1578                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1579                         new_adv |= ADVERTISE_100FULL;
1580                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1581
1582                 if (tp->link_config.advertising &
1583                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1584                         new_adv = 0;
1585                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1586                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1587                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1588                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1589                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1590                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1591                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1592                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1593                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1594                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1595                 } else {
1596                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1597                 }
1598         } else {
1599                 /* Asking for a specific link mode. */
1600                 if (tp->link_config.speed == SPEED_1000) {
1601                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1602                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1603
1604                         if (tp->link_config.duplex == DUPLEX_FULL)
1605                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1606                         else
1607                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1608                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1609                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1610                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1611                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1612                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1613                 } else {
1614                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1615
1616                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1617                         if (tp->link_config.speed == SPEED_100) {
1618                                 if (tp->link_config.duplex == DUPLEX_FULL)
1619                                         new_adv |= ADVERTISE_100FULL;
1620                                 else
1621                                         new_adv |= ADVERTISE_100HALF;
1622                         } else {
1623                                 if (tp->link_config.duplex == DUPLEX_FULL)
1624                                         new_adv |= ADVERTISE_10FULL;
1625                                 else
1626                                         new_adv |= ADVERTISE_10HALF;
1627                         }
1628                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1629                 }
1630         }
1631
1632         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1633             tp->link_config.speed != SPEED_INVALID) {
1634                 u32 bmcr, orig_bmcr;
1635
1636                 tp->link_config.active_speed = tp->link_config.speed;
1637                 tp->link_config.active_duplex = tp->link_config.duplex;
1638
1639                 bmcr = 0;
1640                 switch (tp->link_config.speed) {
1641                 default:
1642                 case SPEED_10:
1643                         break;
1644
1645                 case SPEED_100:
1646                         bmcr |= BMCR_SPEED100;
1647                         break;
1648
1649                 case SPEED_1000:
1650                         bmcr |= TG3_BMCR_SPEED1000;
1651                         break;
1652                 };
1653
1654                 if (tp->link_config.duplex == DUPLEX_FULL)
1655                         bmcr |= BMCR_FULLDPLX;
1656
1657                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1658                     (bmcr != orig_bmcr)) {
1659                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1660                         for (i = 0; i < 1500; i++) {
1661                                 u32 tmp;
1662
1663                                 udelay(10);
1664                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1665                                     tg3_readphy(tp, MII_BMSR, &tmp))
1666                                         continue;
1667                                 if (!(tmp & BMSR_LSTATUS)) {
1668                                         udelay(40);
1669                                         break;
1670                                 }
1671                         }
1672                         tg3_writephy(tp, MII_BMCR, bmcr);
1673                         udelay(40);
1674                 }
1675         } else {
1676                 tg3_writephy(tp, MII_BMCR,
1677                              BMCR_ANENABLE | BMCR_ANRESTART);
1678         }
1679 }
1680
1681 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1682 {
1683         int err;
1684
1685         /* Turn off tap power management. */
1686         /* Set Extended packet length bit */
1687         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1688
1689         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1690         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1691
1692         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1693         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1694
1695         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1696         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1697
1698         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1699         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1700
1701         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1702         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1703
1704         udelay(40);
1705
1706         return err;
1707 }
1708
1709 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1710 {
1711         u32 adv_reg, all_mask;
1712
1713         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1714                 return 0;
1715
1716         all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1717                     ADVERTISE_100HALF | ADVERTISE_100FULL);
1718         if ((adv_reg & all_mask) != all_mask)
1719                 return 0;
1720         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1721                 u32 tg3_ctrl;
1722
1723                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1724                         return 0;
1725
1726                 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1727                             MII_TG3_CTRL_ADV_1000_FULL);
1728                 if ((tg3_ctrl & all_mask) != all_mask)
1729                         return 0;
1730         }
1731         return 1;
1732 }
1733
1734 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1735 {
1736         int current_link_up;
1737         u32 bmsr, dummy;
1738         u16 current_speed;
1739         u8 current_duplex;
1740         int i, err;
1741
1742         tw32(MAC_EVENT, 0);
1743
1744         tw32_f(MAC_STATUS,
1745              (MAC_STATUS_SYNC_CHANGED |
1746               MAC_STATUS_CFG_CHANGED |
1747               MAC_STATUS_MI_COMPLETION |
1748               MAC_STATUS_LNKSTATE_CHANGED));
1749         udelay(40);
1750
1751         tp->mi_mode = MAC_MI_MODE_BASE;
1752         tw32_f(MAC_MI_MODE, tp->mi_mode);
1753         udelay(80);
1754
1755         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1756
1757         /* Some third-party PHYs need to be reset on link going
1758          * down.
1759          */
1760         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1761              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1762              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1763             netif_carrier_ok(tp->dev)) {
1764                 tg3_readphy(tp, MII_BMSR, &bmsr);
1765                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1766                     !(bmsr & BMSR_LSTATUS))
1767                         force_reset = 1;
1768         }
1769         if (force_reset)
1770                 tg3_phy_reset(tp);
1771
1772         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1773                 tg3_readphy(tp, MII_BMSR, &bmsr);
1774                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1775                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1776                         bmsr = 0;
1777
1778                 if (!(bmsr & BMSR_LSTATUS)) {
1779                         err = tg3_init_5401phy_dsp(tp);
1780                         if (err)
1781                                 return err;
1782
1783                         tg3_readphy(tp, MII_BMSR, &bmsr);
1784                         for (i = 0; i < 1000; i++) {
1785                                 udelay(10);
1786                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1787                                     (bmsr & BMSR_LSTATUS)) {
1788                                         udelay(40);
1789                                         break;
1790                                 }
1791                         }
1792
1793                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1794                             !(bmsr & BMSR_LSTATUS) &&
1795                             tp->link_config.active_speed == SPEED_1000) {
1796                                 err = tg3_phy_reset(tp);
1797                                 if (!err)
1798                                         err = tg3_init_5401phy_dsp(tp);
1799                                 if (err)
1800                                         return err;
1801                         }
1802                 }
1803         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1804                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1805                 /* 5701 {A0,B0} CRC bug workaround */
1806                 tg3_writephy(tp, 0x15, 0x0a75);
1807                 tg3_writephy(tp, 0x1c, 0x8c68);
1808                 tg3_writephy(tp, 0x1c, 0x8d68);
1809                 tg3_writephy(tp, 0x1c, 0x8c68);
1810         }
1811
1812         /* Clear pending interrupts... */
1813         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1814         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1815
1816         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1817                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1818         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1819                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1820
1821         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1822             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1823                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1824                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1825                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1826                 else
1827                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1828         }
1829
1830         current_link_up = 0;
1831         current_speed = SPEED_INVALID;
1832         current_duplex = DUPLEX_INVALID;
1833
1834         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1835                 u32 val;
1836
1837                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1838                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1839                 if (!(val & (1 << 10))) {
1840                         val |= (1 << 10);
1841                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1842                         goto relink;
1843                 }
1844         }
1845
1846         bmsr = 0;
1847         for (i = 0; i < 100; i++) {
1848                 tg3_readphy(tp, MII_BMSR, &bmsr);
1849                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1850                     (bmsr & BMSR_LSTATUS))
1851                         break;
1852                 udelay(40);
1853         }
1854
1855         if (bmsr & BMSR_LSTATUS) {
1856                 u32 aux_stat, bmcr;
1857
1858                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1859                 for (i = 0; i < 2000; i++) {
1860                         udelay(10);
1861                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1862                             aux_stat)
1863                                 break;
1864                 }
1865
1866                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1867                                              &current_speed,
1868                                              &current_duplex);
1869
1870                 bmcr = 0;
1871                 for (i = 0; i < 200; i++) {
1872                         tg3_readphy(tp, MII_BMCR, &bmcr);
1873                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1874                                 continue;
1875                         if (bmcr && bmcr != 0x7fff)
1876                                 break;
1877                         udelay(10);
1878                 }
1879
1880                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1881                         if (bmcr & BMCR_ANENABLE) {
1882                                 current_link_up = 1;
1883
1884                                 /* Force autoneg restart if we are exiting
1885                                  * low power mode.
1886                                  */
1887                                 if (!tg3_copper_is_advertising_all(tp))
1888                                         current_link_up = 0;
1889                         } else {
1890                                 current_link_up = 0;
1891                         }
1892                 } else {
1893                         if (!(bmcr & BMCR_ANENABLE) &&
1894                             tp->link_config.speed == current_speed &&
1895                             tp->link_config.duplex == current_duplex) {
1896                                 current_link_up = 1;
1897                         } else {
1898                                 current_link_up = 0;
1899                         }
1900                 }
1901
1902                 tp->link_config.active_speed = current_speed;
1903                 tp->link_config.active_duplex = current_duplex;
1904         }
1905
1906         if (current_link_up == 1 &&
1907             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1908             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1909                 u32 local_adv, remote_adv;
1910
1911                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1912                         local_adv = 0;
1913                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1914
1915                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1916                         remote_adv = 0;
1917
1918                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1919
1920                 /* If we are not advertising full pause capability,
1921                  * something is wrong.  Bring the link down and reconfigure.
1922                  */
1923                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1924                         current_link_up = 0;
1925                 } else {
1926                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1927                 }
1928         }
1929 relink:
1930         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1931                 u32 tmp;
1932
1933                 tg3_phy_copper_begin(tp);
1934
1935                 tg3_readphy(tp, MII_BMSR, &tmp);
1936                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1937                     (tmp & BMSR_LSTATUS))
1938                         current_link_up = 1;
1939         }
1940
1941         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1942         if (current_link_up == 1) {
1943                 if (tp->link_config.active_speed == SPEED_100 ||
1944                     tp->link_config.active_speed == SPEED_10)
1945                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1946                 else
1947                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1948         } else
1949                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1950
1951         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1952         if (tp->link_config.active_duplex == DUPLEX_HALF)
1953                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1954
1955         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1956         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1957                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1958                     (current_link_up == 1 &&
1959                      tp->link_config.active_speed == SPEED_10))
1960                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1961         } else {
1962                 if (current_link_up == 1)
1963                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1964         }
1965
1966         /* ??? Without this setting Netgear GA302T PHY does not
1967          * ??? send/receive packets...
1968          */
1969         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1970             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1971                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1972                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1973                 udelay(80);
1974         }
1975
1976         tw32_f(MAC_MODE, tp->mac_mode);
1977         udelay(40);
1978
1979         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1980                 /* Polled via timer. */
1981                 tw32_f(MAC_EVENT, 0);
1982         } else {
1983                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1984         }
1985         udelay(40);
1986
1987         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1988             current_link_up == 1 &&
1989             tp->link_config.active_speed == SPEED_1000 &&
1990             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1991              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1992                 udelay(120);
1993                 tw32_f(MAC_STATUS,
1994                      (MAC_STATUS_SYNC_CHANGED |
1995                       MAC_STATUS_CFG_CHANGED));
1996                 udelay(40);
1997                 tg3_write_mem(tp,
1998                               NIC_SRAM_FIRMWARE_MBOX,
1999                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2000         }
2001
2002         if (current_link_up != netif_carrier_ok(tp->dev)) {
2003                 if (current_link_up)
2004                         netif_carrier_on(tp->dev);
2005                 else
2006                         netif_carrier_off(tp->dev);
2007                 tg3_link_report(tp);
2008         }
2009
2010         return 0;
2011 }
2012
2013 struct tg3_fiber_aneginfo {
2014         int state;
2015 #define ANEG_STATE_UNKNOWN              0
2016 #define ANEG_STATE_AN_ENABLE            1
2017 #define ANEG_STATE_RESTART_INIT         2
2018 #define ANEG_STATE_RESTART              3
2019 #define ANEG_STATE_DISABLE_LINK_OK      4
2020 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2021 #define ANEG_STATE_ABILITY_DETECT       6
2022 #define ANEG_STATE_ACK_DETECT_INIT      7
2023 #define ANEG_STATE_ACK_DETECT           8
2024 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2025 #define ANEG_STATE_COMPLETE_ACK         10
2026 #define ANEG_STATE_IDLE_DETECT_INIT     11
2027 #define ANEG_STATE_IDLE_DETECT          12
2028 #define ANEG_STATE_LINK_OK              13
2029 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2030 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2031
2032         u32 flags;
2033 #define MR_AN_ENABLE            0x00000001
2034 #define MR_RESTART_AN           0x00000002
2035 #define MR_AN_COMPLETE          0x00000004
2036 #define MR_PAGE_RX              0x00000008
2037 #define MR_NP_LOADED            0x00000010
2038 #define MR_TOGGLE_TX            0x00000020
2039 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2040 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2041 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2042 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2043 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2044 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2045 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2046 #define MR_TOGGLE_RX            0x00002000
2047 #define MR_NP_RX                0x00004000
2048
2049 #define MR_LINK_OK              0x80000000
2050
2051         unsigned long link_time, cur_time;
2052
2053         u32 ability_match_cfg;
2054         int ability_match_count;
2055
2056         char ability_match, idle_match, ack_match;
2057
2058         u32 txconfig, rxconfig;
2059 #define ANEG_CFG_NP             0x00000080
2060 #define ANEG_CFG_ACK            0x00000040
2061 #define ANEG_CFG_RF2            0x00000020
2062 #define ANEG_CFG_RF1            0x00000010
2063 #define ANEG_CFG_PS2            0x00000001
2064 #define ANEG_CFG_PS1            0x00008000
2065 #define ANEG_CFG_HD             0x00004000
2066 #define ANEG_CFG_FD             0x00002000
2067 #define ANEG_CFG_INVAL          0x00001f06
2068
2069 };
2070 #define ANEG_OK         0
2071 #define ANEG_DONE       1
2072 #define ANEG_TIMER_ENAB 2
2073 #define ANEG_FAILED     -1
2074
2075 #define ANEG_STATE_SETTLE_TIME  10000
2076
2077 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2078                                    struct tg3_fiber_aneginfo *ap)
2079 {
2080         unsigned long delta;
2081         u32 rx_cfg_reg;
2082         int ret;
2083
2084         if (ap->state == ANEG_STATE_UNKNOWN) {
2085                 ap->rxconfig = 0;
2086                 ap->link_time = 0;
2087                 ap->cur_time = 0;
2088                 ap->ability_match_cfg = 0;
2089                 ap->ability_match_count = 0;
2090                 ap->ability_match = 0;
2091                 ap->idle_match = 0;
2092                 ap->ack_match = 0;
2093         }
2094         ap->cur_time++;
2095
2096         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2097                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2098
2099                 if (rx_cfg_reg != ap->ability_match_cfg) {
2100                         ap->ability_match_cfg = rx_cfg_reg;
2101                         ap->ability_match = 0;
2102                         ap->ability_match_count = 0;
2103                 } else {
2104                         if (++ap->ability_match_count > 1) {
2105                                 ap->ability_match = 1;
2106                                 ap->ability_match_cfg = rx_cfg_reg;
2107                         }
2108                 }
2109                 if (rx_cfg_reg & ANEG_CFG_ACK)
2110                         ap->ack_match = 1;
2111                 else
2112                         ap->ack_match = 0;
2113
2114                 ap->idle_match = 0;
2115         } else {
2116                 ap->idle_match = 1;
2117                 ap->ability_match_cfg = 0;
2118                 ap->ability_match_count = 0;
2119                 ap->ability_match = 0;
2120                 ap->ack_match = 0;
2121
2122                 rx_cfg_reg = 0;
2123         }
2124
2125         ap->rxconfig = rx_cfg_reg;
2126         ret = ANEG_OK;
2127
2128         switch(ap->state) {
2129         case ANEG_STATE_UNKNOWN:
2130                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2131                         ap->state = ANEG_STATE_AN_ENABLE;
2132
2133                 /* fallthru */
2134         case ANEG_STATE_AN_ENABLE:
2135                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2136                 if (ap->flags & MR_AN_ENABLE) {
2137                         ap->link_time = 0;
2138                         ap->cur_time = 0;
2139                         ap->ability_match_cfg = 0;
2140                         ap->ability_match_count = 0;
2141                         ap->ability_match = 0;
2142                         ap->idle_match = 0;
2143                         ap->ack_match = 0;
2144
2145                         ap->state = ANEG_STATE_RESTART_INIT;
2146                 } else {
2147                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2148                 }
2149                 break;
2150
2151         case ANEG_STATE_RESTART_INIT:
2152                 ap->link_time = ap->cur_time;
2153                 ap->flags &= ~(MR_NP_LOADED);
2154                 ap->txconfig = 0;
2155                 tw32(MAC_TX_AUTO_NEG, 0);
2156                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2157                 tw32_f(MAC_MODE, tp->mac_mode);
2158                 udelay(40);
2159
2160                 ret = ANEG_TIMER_ENAB;
2161                 ap->state = ANEG_STATE_RESTART;
2162
2163                 /* fallthru */
2164         case ANEG_STATE_RESTART:
2165                 delta = ap->cur_time - ap->link_time;
2166                 if (delta > ANEG_STATE_SETTLE_TIME) {
2167                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2168                 } else {
2169                         ret = ANEG_TIMER_ENAB;
2170                 }
2171                 break;
2172
2173         case ANEG_STATE_DISABLE_LINK_OK:
2174                 ret = ANEG_DONE;
2175                 break;
2176
2177         case ANEG_STATE_ABILITY_DETECT_INIT:
2178                 ap->flags &= ~(MR_TOGGLE_TX);
2179                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2180                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2181                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2182                 tw32_f(MAC_MODE, tp->mac_mode);
2183                 udelay(40);
2184
2185                 ap->state = ANEG_STATE_ABILITY_DETECT;
2186                 break;
2187
2188         case ANEG_STATE_ABILITY_DETECT:
2189                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2190                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2191                 }
2192                 break;
2193
2194         case ANEG_STATE_ACK_DETECT_INIT:
2195                 ap->txconfig |= ANEG_CFG_ACK;
2196                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2197                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2198                 tw32_f(MAC_MODE, tp->mac_mode);
2199                 udelay(40);
2200
2201                 ap->state = ANEG_STATE_ACK_DETECT;
2202
2203                 /* fallthru */
2204         case ANEG_STATE_ACK_DETECT:
2205                 if (ap->ack_match != 0) {
2206                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2207                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2208                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2209                         } else {
2210                                 ap->state = ANEG_STATE_AN_ENABLE;
2211                         }
2212                 } else if (ap->ability_match != 0 &&
2213                            ap->rxconfig == 0) {
2214                         ap->state = ANEG_STATE_AN_ENABLE;
2215                 }
2216                 break;
2217
2218         case ANEG_STATE_COMPLETE_ACK_INIT:
2219                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2220                         ret = ANEG_FAILED;
2221                         break;
2222                 }
2223                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2224                                MR_LP_ADV_HALF_DUPLEX |
2225                                MR_LP_ADV_SYM_PAUSE |
2226                                MR_LP_ADV_ASYM_PAUSE |
2227                                MR_LP_ADV_REMOTE_FAULT1 |
2228                                MR_LP_ADV_REMOTE_FAULT2 |
2229                                MR_LP_ADV_NEXT_PAGE |
2230                                MR_TOGGLE_RX |
2231                                MR_NP_RX);
2232                 if (ap->rxconfig & ANEG_CFG_FD)
2233                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2234                 if (ap->rxconfig & ANEG_CFG_HD)
2235                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2236                 if (ap->rxconfig & ANEG_CFG_PS1)
2237                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2238                 if (ap->rxconfig & ANEG_CFG_PS2)
2239                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2240                 if (ap->rxconfig & ANEG_CFG_RF1)
2241                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2242                 if (ap->rxconfig & ANEG_CFG_RF2)
2243                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2244                 if (ap->rxconfig & ANEG_CFG_NP)
2245                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2246
2247                 ap->link_time = ap->cur_time;
2248
2249                 ap->flags ^= (MR_TOGGLE_TX);
2250                 if (ap->rxconfig & 0x0008)
2251                         ap->flags |= MR_TOGGLE_RX;
2252                 if (ap->rxconfig & ANEG_CFG_NP)
2253                         ap->flags |= MR_NP_RX;
2254                 ap->flags |= MR_PAGE_RX;
2255
2256                 ap->state = ANEG_STATE_COMPLETE_ACK;
2257                 ret = ANEG_TIMER_ENAB;
2258                 break;
2259
2260         case ANEG_STATE_COMPLETE_ACK:
2261                 if (ap->ability_match != 0 &&
2262                     ap->rxconfig == 0) {
2263                         ap->state = ANEG_STATE_AN_ENABLE;
2264                         break;
2265                 }
2266                 delta = ap->cur_time - ap->link_time;
2267                 if (delta > ANEG_STATE_SETTLE_TIME) {
2268                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2269                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2270                         } else {
2271                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2272                                     !(ap->flags & MR_NP_RX)) {
2273                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2274                                 } else {
2275                                         ret = ANEG_FAILED;
2276                                 }
2277                         }
2278                 }
2279                 break;
2280
2281         case ANEG_STATE_IDLE_DETECT_INIT:
2282                 ap->link_time = ap->cur_time;
2283                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2284                 tw32_f(MAC_MODE, tp->mac_mode);
2285                 udelay(40);
2286
2287                 ap->state = ANEG_STATE_IDLE_DETECT;
2288                 ret = ANEG_TIMER_ENAB;
2289                 break;
2290
2291         case ANEG_STATE_IDLE_DETECT:
2292                 if (ap->ability_match != 0 &&
2293                     ap->rxconfig == 0) {
2294                         ap->state = ANEG_STATE_AN_ENABLE;
2295                         break;
2296                 }
2297                 delta = ap->cur_time - ap->link_time;
2298                 if (delta > ANEG_STATE_SETTLE_TIME) {
2299                         /* XXX another gem from the Broadcom driver :( */
2300                         ap->state = ANEG_STATE_LINK_OK;
2301                 }
2302                 break;
2303
2304         case ANEG_STATE_LINK_OK:
2305                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2306                 ret = ANEG_DONE;
2307                 break;
2308
2309         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2310                 /* ??? unimplemented */
2311                 break;
2312
2313         case ANEG_STATE_NEXT_PAGE_WAIT:
2314                 /* ??? unimplemented */
2315                 break;
2316
2317         default:
2318                 ret = ANEG_FAILED;
2319                 break;
2320         };
2321
2322         return ret;
2323 }
2324
2325 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2326 {
2327         int res = 0;
2328         struct tg3_fiber_aneginfo aninfo;
2329         int status = ANEG_FAILED;
2330         unsigned int tick;
2331         u32 tmp;
2332
2333         tw32_f(MAC_TX_AUTO_NEG, 0);
2334
2335         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2336         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2337         udelay(40);
2338
2339         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2340         udelay(40);
2341
2342         memset(&aninfo, 0, sizeof(aninfo));
2343         aninfo.flags |= MR_AN_ENABLE;
2344         aninfo.state = ANEG_STATE_UNKNOWN;
2345         aninfo.cur_time = 0;
2346         tick = 0;
2347         while (++tick < 195000) {
2348                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2349                 if (status == ANEG_DONE || status == ANEG_FAILED)
2350                         break;
2351
2352                 udelay(1);
2353         }
2354
2355         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2356         tw32_f(MAC_MODE, tp->mac_mode);
2357         udelay(40);
2358
2359         *flags = aninfo.flags;
2360
2361         if (status == ANEG_DONE &&
2362             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2363                              MR_LP_ADV_FULL_DUPLEX)))
2364                 res = 1;
2365
2366         return res;
2367 }
2368
2369 static void tg3_init_bcm8002(struct tg3 *tp)
2370 {
2371         u32 mac_status = tr32(MAC_STATUS);
2372         int i;
2373
2374         /* Reset when initting first time or we have a link. */
2375         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2376             !(mac_status & MAC_STATUS_PCS_SYNCED))
2377                 return;
2378
2379         /* Set PLL lock range. */
2380         tg3_writephy(tp, 0x16, 0x8007);
2381
2382         /* SW reset */
2383         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2384
2385         /* Wait for reset to complete. */
2386         /* XXX schedule_timeout() ... */
2387         for (i = 0; i < 500; i++)
2388                 udelay(10);
2389
2390         /* Config mode; select PMA/Ch 1 regs. */
2391         tg3_writephy(tp, 0x10, 0x8411);
2392
2393         /* Enable auto-lock and comdet, select txclk for tx. */
2394         tg3_writephy(tp, 0x11, 0x0a10);
2395
2396         tg3_writephy(tp, 0x18, 0x00a0);
2397         tg3_writephy(tp, 0x16, 0x41ff);
2398
2399         /* Assert and deassert POR. */
2400         tg3_writephy(tp, 0x13, 0x0400);
2401         udelay(40);
2402         tg3_writephy(tp, 0x13, 0x0000);
2403
2404         tg3_writephy(tp, 0x11, 0x0a50);
2405         udelay(40);
2406         tg3_writephy(tp, 0x11, 0x0a10);
2407
2408         /* Wait for signal to stabilize */
2409         /* XXX schedule_timeout() ... */
2410         for (i = 0; i < 15000; i++)
2411                 udelay(10);
2412
2413         /* Deselect the channel register so we can read the PHYID
2414          * later.
2415          */
2416         tg3_writephy(tp, 0x10, 0x8011);
2417 }
2418
2419 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2420 {
2421         u32 sg_dig_ctrl, sg_dig_status;
2422         u32 serdes_cfg, expected_sg_dig_ctrl;
2423         int workaround, port_a;
2424         int current_link_up;
2425
2426         serdes_cfg = 0;
2427         expected_sg_dig_ctrl = 0;
2428         workaround = 0;
2429         port_a = 1;
2430         current_link_up = 0;
2431
2432         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2433             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2434                 workaround = 1;
2435                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2436                         port_a = 0;
2437
2438                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2439                 /* preserve bits 20-23 for voltage regulator */
2440                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2441         }
2442
2443         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2444
2445         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2446                 if (sg_dig_ctrl & (1 << 31)) {
2447                         if (workaround) {
2448                                 u32 val = serdes_cfg;
2449
2450                                 if (port_a)
2451                                         val |= 0xc010000;
2452                                 else
2453                                         val |= 0x4010000;
2454                                 tw32_f(MAC_SERDES_CFG, val);
2455                         }
2456                         tw32_f(SG_DIG_CTRL, 0x01388400);
2457                 }
2458                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2459                         tg3_setup_flow_control(tp, 0, 0);
2460                         current_link_up = 1;
2461                 }
2462                 goto out;
2463         }
2464
2465         /* Want auto-negotiation.  */
2466         expected_sg_dig_ctrl = 0x81388400;
2467
2468         /* Pause capability */
2469         expected_sg_dig_ctrl |= (1 << 11);
2470
2471         /* Asymettric pause */
2472         expected_sg_dig_ctrl |= (1 << 12);
2473
2474         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2475                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2476                     tp->serdes_counter &&
2477                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2478                                     MAC_STATUS_RCVD_CFG)) ==
2479                      MAC_STATUS_PCS_SYNCED)) {
2480                         tp->serdes_counter--;
2481                         current_link_up = 1;
2482                         goto out;
2483                 }
2484 restart_autoneg:
2485                 if (workaround)
2486                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2487                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2488                 udelay(5);
2489                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2490
2491                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2492                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2493         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2494                                  MAC_STATUS_SIGNAL_DET)) {
2495                 sg_dig_status = tr32(SG_DIG_STATUS);
2496                 mac_status = tr32(MAC_STATUS);
2497
2498                 if ((sg_dig_status & (1 << 1)) &&
2499                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2500                         u32 local_adv, remote_adv;
2501
2502                         local_adv = ADVERTISE_PAUSE_CAP;
2503                         remote_adv = 0;
2504                         if (sg_dig_status & (1 << 19))
2505                                 remote_adv |= LPA_PAUSE_CAP;
2506                         if (sg_dig_status & (1 << 20))
2507                                 remote_adv |= LPA_PAUSE_ASYM;
2508
2509                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2510                         current_link_up = 1;
2511                         tp->serdes_counter = 0;
2512                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2513                 } else if (!(sg_dig_status & (1 << 1))) {
2514                         if (tp->serdes_counter)
2515                                 tp->serdes_counter--;
2516                         else {
2517                                 if (workaround) {
2518                                         u32 val = serdes_cfg;
2519
2520                                         if (port_a)
2521                                                 val |= 0xc010000;
2522                                         else
2523                                                 val |= 0x4010000;
2524
2525                                         tw32_f(MAC_SERDES_CFG, val);
2526                                 }
2527
2528                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2529                                 udelay(40);
2530
2531                                 /* Link parallel detection - link is up */
2532                                 /* only if we have PCS_SYNC and not */
2533                                 /* receiving config code words */
2534                                 mac_status = tr32(MAC_STATUS);
2535                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2536                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2537                                         tg3_setup_flow_control(tp, 0, 0);
2538                                         current_link_up = 1;
2539                                         tp->tg3_flags2 |=
2540                                                 TG3_FLG2_PARALLEL_DETECT;
2541                                         tp->serdes_counter =
2542                                                 SERDES_PARALLEL_DET_TIMEOUT;
2543                                 } else
2544                                         goto restart_autoneg;
2545                         }
2546                 }
2547         } else {
2548                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2549                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2550         }
2551
2552 out:
2553         return current_link_up;
2554 }
2555
2556 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2557 {
2558         int current_link_up = 0;
2559
2560         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2561                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2562                 goto out;
2563         }
2564
2565         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2566                 u32 flags;
2567                 int i;
2568
2569                 if (fiber_autoneg(tp, &flags)) {
2570                         u32 local_adv, remote_adv;
2571
2572                         local_adv = ADVERTISE_PAUSE_CAP;
2573                         remote_adv = 0;
2574                         if (flags & MR_LP_ADV_SYM_PAUSE)
2575                                 remote_adv |= LPA_PAUSE_CAP;
2576                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2577                                 remote_adv |= LPA_PAUSE_ASYM;
2578
2579                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2580
2581                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2582                         current_link_up = 1;
2583                 }
2584                 for (i = 0; i < 30; i++) {
2585                         udelay(20);
2586                         tw32_f(MAC_STATUS,
2587                                (MAC_STATUS_SYNC_CHANGED |
2588                                 MAC_STATUS_CFG_CHANGED));
2589                         udelay(40);
2590                         if ((tr32(MAC_STATUS) &
2591                              (MAC_STATUS_SYNC_CHANGED |
2592                               MAC_STATUS_CFG_CHANGED)) == 0)
2593                                 break;
2594                 }
2595
2596                 mac_status = tr32(MAC_STATUS);
2597                 if (current_link_up == 0 &&
2598                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2599                     !(mac_status & MAC_STATUS_RCVD_CFG))
2600                         current_link_up = 1;
2601         } else {
2602                 /* Forcing 1000FD link up. */
2603                 current_link_up = 1;
2604                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2605
2606                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2607                 udelay(40);
2608         }
2609
2610 out:
2611         return current_link_up;
2612 }
2613
2614 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2615 {
2616         u32 orig_pause_cfg;
2617         u16 orig_active_speed;
2618         u8 orig_active_duplex;
2619         u32 mac_status;
2620         int current_link_up;
2621         int i;
2622
2623         orig_pause_cfg =
2624                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2625                                   TG3_FLAG_TX_PAUSE));
2626         orig_active_speed = tp->link_config.active_speed;
2627         orig_active_duplex = tp->link_config.active_duplex;
2628
2629         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2630             netif_carrier_ok(tp->dev) &&
2631             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2632                 mac_status = tr32(MAC_STATUS);
2633                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2634                                MAC_STATUS_SIGNAL_DET |
2635                                MAC_STATUS_CFG_CHANGED |
2636                                MAC_STATUS_RCVD_CFG);
2637                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2638                                    MAC_STATUS_SIGNAL_DET)) {
2639                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2640                                             MAC_STATUS_CFG_CHANGED));
2641                         return 0;
2642                 }
2643         }
2644
2645         tw32_f(MAC_TX_AUTO_NEG, 0);
2646
2647         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2648         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2649         tw32_f(MAC_MODE, tp->mac_mode);
2650         udelay(40);
2651
2652         if (tp->phy_id == PHY_ID_BCM8002)
2653                 tg3_init_bcm8002(tp);
2654
2655         /* Enable link change event even when serdes polling.  */
2656         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2657         udelay(40);
2658
2659         current_link_up = 0;
2660         mac_status = tr32(MAC_STATUS);
2661
2662         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2663                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2664         else
2665                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2666
2667         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2668         tw32_f(MAC_MODE, tp->mac_mode);
2669         udelay(40);
2670
2671         tp->hw_status->status =
2672                 (SD_STATUS_UPDATED |
2673                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2674
2675         for (i = 0; i < 100; i++) {
2676                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2677                                     MAC_STATUS_CFG_CHANGED));
2678                 udelay(5);
2679                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2680                                          MAC_STATUS_CFG_CHANGED |
2681                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2682                         break;
2683         }
2684
2685         mac_status = tr32(MAC_STATUS);
2686         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2687                 current_link_up = 0;
2688                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2689                     tp->serdes_counter == 0) {
2690                         tw32_f(MAC_MODE, (tp->mac_mode |
2691                                           MAC_MODE_SEND_CONFIGS));
2692                         udelay(1);
2693                         tw32_f(MAC_MODE, tp->mac_mode);
2694                 }
2695         }
2696
2697         if (current_link_up == 1) {
2698                 tp->link_config.active_speed = SPEED_1000;
2699                 tp->link_config.active_duplex = DUPLEX_FULL;
2700                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2701                                     LED_CTRL_LNKLED_OVERRIDE |
2702                                     LED_CTRL_1000MBPS_ON));
2703         } else {
2704                 tp->link_config.active_speed = SPEED_INVALID;
2705                 tp->link_config.active_duplex = DUPLEX_INVALID;
2706                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2707                                     LED_CTRL_LNKLED_OVERRIDE |
2708                                     LED_CTRL_TRAFFIC_OVERRIDE));
2709         }
2710
2711         if (current_link_up != netif_carrier_ok(tp->dev)) {
2712                 if (current_link_up)
2713                         netif_carrier_on(tp->dev);
2714                 else
2715                         netif_carrier_off(tp->dev);
2716                 tg3_link_report(tp);
2717         } else {
2718                 u32 now_pause_cfg =
2719                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2720                                          TG3_FLAG_TX_PAUSE);
2721                 if (orig_pause_cfg != now_pause_cfg ||
2722                     orig_active_speed != tp->link_config.active_speed ||
2723                     orig_active_duplex != tp->link_config.active_duplex)
2724                         tg3_link_report(tp);
2725         }
2726
2727         return 0;
2728 }
2729
2730 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2731 {
2732         int current_link_up, err = 0;
2733         u32 bmsr, bmcr;
2734         u16 current_speed;
2735         u8 current_duplex;
2736
2737         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2738         tw32_f(MAC_MODE, tp->mac_mode);
2739         udelay(40);
2740
2741         tw32(MAC_EVENT, 0);
2742
2743         tw32_f(MAC_STATUS,
2744              (MAC_STATUS_SYNC_CHANGED |
2745               MAC_STATUS_CFG_CHANGED |
2746               MAC_STATUS_MI_COMPLETION |
2747               MAC_STATUS_LNKSTATE_CHANGED));
2748         udelay(40);
2749
2750         if (force_reset)
2751                 tg3_phy_reset(tp);
2752
2753         current_link_up = 0;
2754         current_speed = SPEED_INVALID;
2755         current_duplex = DUPLEX_INVALID;
2756
2757         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2758         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2759         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2760                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2761                         bmsr |= BMSR_LSTATUS;
2762                 else
2763                         bmsr &= ~BMSR_LSTATUS;
2764         }
2765
2766         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2767
2768         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2769             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2770                 /* do nothing, just check for link up at the end */
2771         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2772                 u32 adv, new_adv;
2773
2774                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2775                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2776                                   ADVERTISE_1000XPAUSE |
2777                                   ADVERTISE_1000XPSE_ASYM |
2778                                   ADVERTISE_SLCT);
2779
2780                 /* Always advertise symmetric PAUSE just like copper */
2781                 new_adv |= ADVERTISE_1000XPAUSE;
2782
2783                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2784                         new_adv |= ADVERTISE_1000XHALF;
2785                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2786                         new_adv |= ADVERTISE_1000XFULL;
2787
2788                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2789                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2790                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2791                         tg3_writephy(tp, MII_BMCR, bmcr);
2792
2793                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2794                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2795                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2796
2797                         return err;
2798                 }
2799         } else {
2800                 u32 new_bmcr;
2801
2802                 bmcr &= ~BMCR_SPEED1000;
2803                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2804
2805                 if (tp->link_config.duplex == DUPLEX_FULL)
2806                         new_bmcr |= BMCR_FULLDPLX;
2807
2808                 if (new_bmcr != bmcr) {
2809                         /* BMCR_SPEED1000 is a reserved bit that needs
2810                          * to be set on write.
2811                          */
2812                         new_bmcr |= BMCR_SPEED1000;
2813
2814                         /* Force a linkdown */
2815                         if (netif_carrier_ok(tp->dev)) {
2816                                 u32 adv;
2817
2818                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2819                                 adv &= ~(ADVERTISE_1000XFULL |
2820                                          ADVERTISE_1000XHALF |
2821                                          ADVERTISE_SLCT);
2822                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2823                                 tg3_writephy(tp, MII_BMCR, bmcr |
2824                                                            BMCR_ANRESTART |
2825                                                            BMCR_ANENABLE);
2826                                 udelay(10);
2827                                 netif_carrier_off(tp->dev);
2828                         }
2829                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2830                         bmcr = new_bmcr;
2831                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2832                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2833                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2834                             ASIC_REV_5714) {
2835                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2836                                         bmsr |= BMSR_LSTATUS;
2837                                 else
2838                                         bmsr &= ~BMSR_LSTATUS;
2839                         }
2840                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2841                 }
2842         }
2843
2844         if (bmsr & BMSR_LSTATUS) {
2845                 current_speed = SPEED_1000;
2846                 current_link_up = 1;
2847                 if (bmcr & BMCR_FULLDPLX)
2848                         current_duplex = DUPLEX_FULL;
2849                 else
2850                         current_duplex = DUPLEX_HALF;
2851
2852                 if (bmcr & BMCR_ANENABLE) {
2853                         u32 local_adv, remote_adv, common;
2854
2855                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2856                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2857                         common = local_adv & remote_adv;
2858                         if (common & (ADVERTISE_1000XHALF |
2859                                       ADVERTISE_1000XFULL)) {
2860                                 if (common & ADVERTISE_1000XFULL)
2861                                         current_duplex = DUPLEX_FULL;
2862                                 else
2863                                         current_duplex = DUPLEX_HALF;
2864
2865                                 tg3_setup_flow_control(tp, local_adv,
2866                                                        remote_adv);
2867                         }
2868                         else
2869                                 current_link_up = 0;
2870                 }
2871         }
2872
2873         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2874         if (tp->link_config.active_duplex == DUPLEX_HALF)
2875                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2876
2877         tw32_f(MAC_MODE, tp->mac_mode);
2878         udelay(40);
2879
2880         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2881
2882         tp->link_config.active_speed = current_speed;
2883         tp->link_config.active_duplex = current_duplex;
2884
2885         if (current_link_up != netif_carrier_ok(tp->dev)) {
2886                 if (current_link_up)
2887                         netif_carrier_on(tp->dev);
2888                 else {
2889                         netif_carrier_off(tp->dev);
2890                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2891                 }
2892                 tg3_link_report(tp);
2893         }
2894         return err;
2895 }
2896
2897 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2898 {
2899         if (tp->serdes_counter) {
2900                 /* Give autoneg time to complete. */
2901                 tp->serdes_counter--;
2902                 return;
2903         }
2904         if (!netif_carrier_ok(tp->dev) &&
2905             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2906                 u32 bmcr;
2907
2908                 tg3_readphy(tp, MII_BMCR, &bmcr);
2909                 if (bmcr & BMCR_ANENABLE) {
2910                         u32 phy1, phy2;
2911
2912                         /* Select shadow register 0x1f */
2913                         tg3_writephy(tp, 0x1c, 0x7c00);
2914                         tg3_readphy(tp, 0x1c, &phy1);
2915
2916                         /* Select expansion interrupt status register */
2917                         tg3_writephy(tp, 0x17, 0x0f01);
2918                         tg3_readphy(tp, 0x15, &phy2);
2919                         tg3_readphy(tp, 0x15, &phy2);
2920
2921                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2922                                 /* We have signal detect and not receiving
2923                                  * config code words, link is up by parallel
2924                                  * detection.
2925                                  */
2926
2927                                 bmcr &= ~BMCR_ANENABLE;
2928                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2929                                 tg3_writephy(tp, MII_BMCR, bmcr);
2930                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2931                         }
2932                 }
2933         }
2934         else if (netif_carrier_ok(tp->dev) &&
2935                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2936                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2937                 u32 phy2;
2938
2939                 /* Select expansion interrupt status register */
2940                 tg3_writephy(tp, 0x17, 0x0f01);
2941                 tg3_readphy(tp, 0x15, &phy2);
2942                 if (phy2 & 0x20) {
2943                         u32 bmcr;
2944
2945                         /* Config code words received, turn on autoneg. */
2946                         tg3_readphy(tp, MII_BMCR, &bmcr);
2947                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2948
2949                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2950
2951                 }
2952         }
2953 }
2954
2955 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2956 {
2957         int err;
2958
2959         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2960                 err = tg3_setup_fiber_phy(tp, force_reset);
2961         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2962                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2963         } else {
2964                 err = tg3_setup_copper_phy(tp, force_reset);
2965         }
2966
2967         if (tp->link_config.active_speed == SPEED_1000 &&
2968             tp->link_config.active_duplex == DUPLEX_HALF)
2969                 tw32(MAC_TX_LENGTHS,
2970                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2971                       (6 << TX_LENGTHS_IPG_SHIFT) |
2972                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2973         else
2974                 tw32(MAC_TX_LENGTHS,
2975                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2976                       (6 << TX_LENGTHS_IPG_SHIFT) |
2977                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2978
2979         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2980                 if (netif_carrier_ok(tp->dev)) {
2981                         tw32(HOSTCC_STAT_COAL_TICKS,
2982                              tp->coal.stats_block_coalesce_usecs);
2983                 } else {
2984                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2985                 }
2986         }
2987
2988         return err;
2989 }
2990
2991 /* This is called whenever we suspect that the system chipset is re-
2992  * ordering the sequence of MMIO to the tx send mailbox. The symptom
2993  * is bogus tx completions. We try to recover by setting the
2994  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
2995  * in the workqueue.
2996  */
2997 static void tg3_tx_recover(struct tg3 *tp)
2998 {
2999         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3000                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3001
3002         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3003                "mapped I/O cycles to the network device, attempting to "
3004                "recover. Please report the problem to the driver maintainer "
3005                "and include system chipset information.\n", tp->dev->name);
3006
3007         spin_lock(&tp->lock);
3008         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3009         spin_unlock(&tp->lock);
3010 }
3011
3012 static inline u32 tg3_tx_avail(struct tg3 *tp)
3013 {
3014         smp_mb();
3015         return (tp->tx_pending -
3016                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3017 }
3018
3019 /* Tigon3 never reports partial packet sends.  So we do not
3020  * need special logic to handle SKBs that have not had all
3021  * of their frags sent yet, like SunGEM does.
3022  */
3023 static void tg3_tx(struct tg3 *tp)
3024 {
3025         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3026         u32 sw_idx = tp->tx_cons;
3027
3028         while (sw_idx != hw_idx) {
3029                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3030                 struct sk_buff *skb = ri->skb;
3031                 int i, tx_bug = 0;
3032
3033                 if (unlikely(skb == NULL)) {
3034                         tg3_tx_recover(tp);
3035                         return;
3036                 }
3037
3038                 pci_unmap_single(tp->pdev,
3039                                  pci_unmap_addr(ri, mapping),
3040                                  skb_headlen(skb),
3041                                  PCI_DMA_TODEVICE);
3042
3043                 ri->skb = NULL;
3044
3045                 sw_idx = NEXT_TX(sw_idx);
3046
3047                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3048                         ri = &tp->tx_buffers[sw_idx];
3049                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3050                                 tx_bug = 1;
3051
3052                         pci_unmap_page(tp->pdev,
3053                                        pci_unmap_addr(ri, mapping),
3054                                        skb_shinfo(skb)->frags[i].size,
3055                                        PCI_DMA_TODEVICE);
3056
3057                         sw_idx = NEXT_TX(sw_idx);
3058                 }
3059
3060                 dev_kfree_skb(skb);
3061
3062                 if (unlikely(tx_bug)) {
3063                         tg3_tx_recover(tp);
3064                         return;
3065                 }
3066         }
3067
3068         tp->tx_cons = sw_idx;
3069
3070         /* Need to make the tx_cons update visible to tg3_start_xmit()
3071          * before checking for netif_queue_stopped().  Without the
3072          * memory barrier, there is a small possibility that tg3_start_xmit()
3073          * will miss it and cause the queue to be stopped forever.
3074          */
3075         smp_mb();
3076
3077         if (unlikely(netif_queue_stopped(tp->dev) &&
3078                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3079                 netif_tx_lock(tp->dev);
3080                 if (netif_queue_stopped(tp->dev) &&
3081                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3082                         netif_wake_queue(tp->dev);
3083                 netif_tx_unlock(tp->dev);
3084         }
3085 }
3086
3087 /* Returns size of skb allocated or < 0 on error.
3088  *
3089  * We only need to fill in the address because the other members
3090  * of the RX descriptor are invariant, see tg3_init_rings.
3091  *
3092  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3093  * posting buffers we only dirty the first cache line of the RX
3094  * descriptor (containing the address).  Whereas for the RX status
3095  * buffers the cpu only reads the last cacheline of the RX descriptor
3096  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3097  */
3098 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3099                             int src_idx, u32 dest_idx_unmasked)
3100 {
3101         struct tg3_rx_buffer_desc *desc;
3102         struct ring_info *map, *src_map;
3103         struct sk_buff *skb;
3104         dma_addr_t mapping;
3105         int skb_size, dest_idx;
3106
3107         src_map = NULL;
3108         switch (opaque_key) {
3109         case RXD_OPAQUE_RING_STD:
3110                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3111                 desc = &tp->rx_std[dest_idx];
3112                 map = &tp->rx_std_buffers[dest_idx];
3113                 if (src_idx >= 0)
3114                         src_map = &tp->rx_std_buffers[src_idx];
3115                 skb_size = tp->rx_pkt_buf_sz;
3116                 break;
3117
3118         case RXD_OPAQUE_RING_JUMBO:
3119                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3120                 desc = &tp->rx_jumbo[dest_idx];
3121                 map = &tp->rx_jumbo_buffers[dest_idx];
3122                 if (src_idx >= 0)
3123                         src_map = &tp->rx_jumbo_buffers[src_idx];
3124                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3125                 break;
3126
3127         default:
3128                 return -EINVAL;
3129         };
3130
3131         /* Do not overwrite any of the map or rp information
3132          * until we are sure we can commit to a new buffer.
3133          *
3134          * Callers depend upon this behavior and assume that
3135          * we leave everything unchanged if we fail.
3136          */
3137         skb = netdev_alloc_skb(tp->dev, skb_size);
3138         if (skb == NULL)
3139                 return -ENOMEM;
3140
3141         skb_reserve(skb, tp->rx_offset);
3142
3143         mapping = pci_map_single(tp->pdev, skb->data,
3144                                  skb_size - tp->rx_offset,
3145                                  PCI_DMA_FROMDEVICE);
3146
3147         map->skb = skb;
3148         pci_unmap_addr_set(map, mapping, mapping);
3149
3150         if (src_map != NULL)
3151                 src_map->skb = NULL;
3152
3153         desc->addr_hi = ((u64)mapping >> 32);
3154         desc->addr_lo = ((u64)mapping & 0xffffffff);
3155
3156         return skb_size;
3157 }
3158
3159 /* We only need to move over in the address because the other
3160  * members of the RX descriptor are invariant.  See notes above
3161  * tg3_alloc_rx_skb for full details.
3162  */
3163 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3164                            int src_idx, u32 dest_idx_unmasked)
3165 {
3166         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3167         struct ring_info *src_map, *dest_map;
3168         int dest_idx;
3169
3170         switch (opaque_key) {
3171         case RXD_OPAQUE_RING_STD:
3172                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3173                 dest_desc = &tp->rx_std[dest_idx];
3174                 dest_map = &tp->rx_std_buffers[dest_idx];
3175                 src_desc = &tp->rx_std[src_idx];
3176                 src_map = &tp->rx_std_buffers[src_idx];
3177                 break;
3178
3179         case RXD_OPAQUE_RING_JUMBO:
3180                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3181                 dest_desc = &tp->rx_jumbo[dest_idx];
3182                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3183                 src_desc = &tp->rx_jumbo[src_idx];
3184                 src_map = &tp->rx_jumbo_buffers[src_idx];
3185                 break;
3186
3187         default:
3188                 return;
3189         };
3190
3191         dest_map->skb = src_map->skb;
3192         pci_unmap_addr_set(dest_map, mapping,
3193                            pci_unmap_addr(src_map, mapping));
3194         dest_desc->addr_hi = src_desc->addr_hi;
3195         dest_desc->addr_lo = src_desc->addr_lo;
3196
3197         src_map->skb = NULL;
3198 }
3199
3200 #if TG3_VLAN_TAG_USED
3201 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3202 {
3203         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3204 }
3205 #endif
3206
3207 /* The RX ring scheme is composed of multiple rings which post fresh
3208  * buffers to the chip, and one special ring the chip uses to report
3209  * status back to the host.
3210  *
3211  * The special ring reports the status of received packets to the
3212  * host.  The chip does not write into the original descriptor the
3213  * RX buffer was obtained from.  The chip simply takes the original
3214  * descriptor as provided by the host, updates the status and length
3215  * field, then writes this into the next status ring entry.
3216  *
3217  * Each ring the host uses to post buffers to the chip is described
3218  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3219  * it is first placed into the on-chip ram.  When the packet's length
3220  * is known, it walks down the TG3_BDINFO entries to select the ring.
3221  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3222  * which is within the range of the new packet's length is chosen.
3223  *
3224  * The "separate ring for rx status" scheme may sound queer, but it makes
3225  * sense from a cache coherency perspective.  If only the host writes
3226  * to the buffer post rings, and only the chip writes to the rx status
3227  * rings, then cache lines never move beyond shared-modified state.
3228  * If both the host and chip were to write into the same ring, cache line
3229  * eviction could occur since both entities want it in an exclusive state.
3230  */
3231 static int tg3_rx(struct tg3 *tp, int budget)
3232 {
3233         u32 work_mask, rx_std_posted = 0;
3234         u32 sw_idx = tp->rx_rcb_ptr;
3235         u16 hw_idx;
3236         int received;
3237
3238         hw_idx = tp->hw_status->idx[0].rx_producer;
3239         /*
3240          * We need to order the read of hw_idx and the read of
3241          * the opaque cookie.
3242          */
3243         rmb();
3244         work_mask = 0;
3245         received = 0;
3246         while (sw_idx != hw_idx && budget > 0) {
3247                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3248                 unsigned int len;
3249                 struct sk_buff *skb;
3250                 dma_addr_t dma_addr;
3251                 u32 opaque_key, desc_idx, *post_ptr;
3252
3253                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3254                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3255                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3256                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3257                                                   mapping);
3258                         skb = tp->rx_std_buffers[desc_idx].skb;
3259                         post_ptr = &tp->rx_std_ptr;
3260                         rx_std_posted++;
3261                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3262                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3263                                                   mapping);
3264                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3265                         post_ptr = &tp->rx_jumbo_ptr;
3266                 }
3267                 else {
3268                         goto next_pkt_nopost;
3269                 }
3270
3271                 work_mask |= opaque_key;
3272
3273                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3274                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3275                 drop_it:
3276                         tg3_recycle_rx(tp, opaque_key,
3277                                        desc_idx, *post_ptr);
3278                 drop_it_no_recycle:
3279                         /* Other statistics kept track of by card. */
3280                         tp->net_stats.rx_dropped++;
3281                         goto next_pkt;
3282                 }
3283
3284                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3285
3286                 if (len > RX_COPY_THRESHOLD
3287                         && tp->rx_offset == 2
3288                         /* rx_offset != 2 iff this is a 5701 card running
3289                          * in PCI-X mode [see tg3_get_invariants()] */
3290                 ) {
3291                         int skb_size;
3292
3293                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3294                                                     desc_idx, *post_ptr);
3295                         if (skb_size < 0)
3296                                 goto drop_it;
3297
3298                         pci_unmap_single(tp->pdev, dma_addr,
3299                                          skb_size - tp->rx_offset,
3300                                          PCI_DMA_FROMDEVICE);
3301
3302                         skb_put(skb, len);
3303                 } else {
3304                         struct sk_buff *copy_skb;
3305
3306                         tg3_recycle_rx(tp, opaque_key,
3307                                        desc_idx, *post_ptr);
3308
3309                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3310                         if (copy_skb == NULL)
3311                                 goto drop_it_no_recycle;
3312
3313                         skb_reserve(copy_skb, 2);
3314                         skb_put(copy_skb, len);
3315                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3316                         memcpy(copy_skb->data, skb->data, len);
3317                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3318
3319                         /* We'll reuse the original ring buffer. */
3320                         skb = copy_skb;
3321                 }
3322
3323                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3324                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3325                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3326                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3327                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3328                 else
3329                         skb->ip_summed = CHECKSUM_NONE;
3330
3331                 skb->protocol = eth_type_trans(skb, tp->dev);
3332 #if TG3_VLAN_TAG_USED
3333                 if (tp->vlgrp != NULL &&
3334                     desc->type_flags & RXD_FLAG_VLAN) {
3335                         tg3_vlan_rx(tp, skb,
3336                                     desc->err_vlan & RXD_VLAN_MASK);
3337                 } else
3338 #endif
3339                         netif_receive_skb(skb);
3340
3341                 tp->dev->last_rx = jiffies;
3342                 received++;
3343                 budget--;
3344
3345 next_pkt:
3346                 (*post_ptr)++;
3347
3348                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3349                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3350
3351                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3352                                      TG3_64BIT_REG_LOW, idx);
3353                         work_mask &= ~RXD_OPAQUE_RING_STD;
3354                         rx_std_posted = 0;
3355                 }
3356 next_pkt_nopost:
3357                 sw_idx++;
3358                 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
3359
3360                 /* Refresh hw_idx to see if there is new work */
3361                 if (sw_idx == hw_idx) {
3362                         hw_idx = tp->hw_status->idx[0].rx_producer;
3363                         rmb();
3364                 }
3365         }
3366
3367         /* ACK the status ring. */
3368         tp->rx_rcb_ptr = sw_idx;
3369         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3370
3371         /* Refill RX ring(s). */
3372         if (work_mask & RXD_OPAQUE_RING_STD) {
3373                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3374                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3375                              sw_idx);
3376         }
3377         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3378                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3379                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3380                              sw_idx);
3381         }
3382         mmiowb();
3383
3384         return received;
3385 }
3386
3387 static int tg3_poll(struct net_device *netdev, int *budget)
3388 {
3389         struct tg3 *tp = netdev_priv(netdev);
3390         struct tg3_hw_status *sblk = tp->hw_status;
3391         int done;
3392
3393         /* handle link change and other phy events */
3394         if (!(tp->tg3_flags &
3395               (TG3_FLAG_USE_LINKCHG_REG |
3396                TG3_FLAG_POLL_SERDES))) {
3397                 if (sblk->status & SD_STATUS_LINK_CHG) {
3398                         sblk->status = SD_STATUS_UPDATED |
3399                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3400                         spin_lock(&tp->lock);
3401                         tg3_setup_phy(tp, 0);
3402                         spin_unlock(&tp->lock);
3403                 }
3404         }
3405
3406         /* run TX completion thread */
3407         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3408                 tg3_tx(tp);
3409                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3410                         netif_rx_complete(netdev);
3411                         schedule_work(&tp->reset_task);
3412                         return 0;
3413                 }
3414         }
3415
3416         /* run RX thread, within the bounds set by NAPI.
3417          * All RX "locking" is done by ensuring outside
3418          * code synchronizes with dev->poll()
3419          */
3420         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3421                 int orig_budget = *budget;
3422                 int work_done;
3423
3424                 if (orig_budget > netdev->quota)
3425                         orig_budget = netdev->quota;
3426
3427                 work_done = tg3_rx(tp, orig_budget);
3428
3429                 *budget -= work_done;
3430                 netdev->quota -= work_done;
3431         }
3432
3433         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3434                 tp->last_tag = sblk->status_tag;
3435                 rmb();
3436         } else
3437                 sblk->status &= ~SD_STATUS_UPDATED;
3438
3439         /* if no more work, tell net stack and NIC we're done */
3440         done = !tg3_has_work(tp);
3441         if (done) {
3442                 netif_rx_complete(netdev);
3443                 tg3_restart_ints(tp);
3444         }
3445
3446         return (done ? 0 : 1);
3447 }
3448
3449 static void tg3_irq_quiesce(struct tg3 *tp)
3450 {
3451         BUG_ON(tp->irq_sync);
3452
3453         tp->irq_sync = 1;
3454         smp_mb();
3455
3456         synchronize_irq(tp->pdev->irq);
3457 }
3458
3459 static inline int tg3_irq_sync(struct tg3 *tp)
3460 {
3461         return tp->irq_sync;
3462 }
3463
3464 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3465  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3466  * with as well.  Most of the time, this is not necessary except when
3467  * shutting down the device.
3468  */
3469 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3470 {
3471         if (irq_sync)
3472                 tg3_irq_quiesce(tp);
3473         spin_lock_bh(&tp->lock);
3474 }
3475
3476 static inline void tg3_full_unlock(struct tg3 *tp)
3477 {
3478         spin_unlock_bh(&tp->lock);
3479 }
3480
3481 /* One-shot MSI handler - Chip automatically disables interrupt
3482  * after sending MSI so driver doesn't have to do it.
3483  */
3484 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3485 {
3486         struct net_device *dev = dev_id;
3487         struct tg3 *tp = netdev_priv(dev);
3488
3489         prefetch(tp->hw_status);
3490         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3491
3492         if (likely(!tg3_irq_sync(tp)))
3493                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3494
3495         return IRQ_HANDLED;
3496 }
3497
3498 /* MSI ISR - No need to check for interrupt sharing and no need to
3499  * flush status block and interrupt mailbox. PCI ordering rules
3500  * guarantee that MSI will arrive after the status block.
3501  */
3502 static irqreturn_t tg3_msi(int irq, void *dev_id)
3503 {
3504         struct net_device *dev = dev_id;
3505         struct tg3 *tp = netdev_priv(dev);
3506
3507         prefetch(tp->hw_status);
3508         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3509         /*
3510          * Writing any value to intr-mbox-0 clears PCI INTA# and
3511          * chip-internal interrupt pending events.
3512          * Writing non-zero to intr-mbox-0 additional tells the
3513          * NIC to stop sending us irqs, engaging "in-intr-handler"
3514          * event coalescing.
3515          */
3516         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3517         if (likely(!tg3_irq_sync(tp)))
3518                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3519
3520         return IRQ_RETVAL(1);
3521 }
3522
3523 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3524 {
3525         struct net_device *dev = dev_id;
3526         struct tg3 *tp = netdev_priv(dev);
3527         struct tg3_hw_status *sblk = tp->hw_status;
3528         unsigned int handled = 1;
3529
3530         /* In INTx mode, it is possible for the interrupt to arrive at
3531          * the CPU before the status block posted prior to the interrupt.
3532          * Reading the PCI State register will confirm whether the
3533          * interrupt is ours and will flush the status block.
3534          */
3535         if ((sblk->status & SD_STATUS_UPDATED) ||
3536             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3537                 /*
3538                  * Writing any value to intr-mbox-0 clears PCI INTA# and
3539                  * chip-internal interrupt pending events.
3540                  * Writing non-zero to intr-mbox-0 additional tells the
3541                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3542                  * event coalescing.
3543                  */
3544                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3545                              0x00000001);
3546                 if (tg3_irq_sync(tp))
3547                         goto out;
3548                 sblk->status &= ~SD_STATUS_UPDATED;
3549                 if (likely(tg3_has_work(tp))) {
3550                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3551                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3552                 } else {
3553                         /* No work, shared interrupt perhaps?  re-enable
3554                          * interrupts, and flush that PCI write
3555                          */
3556                         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3557                                 0x00000000);
3558                 }
3559         } else {        /* shared interrupt */
3560                 handled = 0;
3561         }
3562 out:
3563         return IRQ_RETVAL(handled);
3564 }
3565
3566 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3567 {
3568         struct net_device *dev = dev_id;
3569         struct tg3 *tp = netdev_priv(dev);
3570         struct tg3_hw_status *sblk = tp->hw_status;
3571         unsigned int handled = 1;
3572
3573         /* In INTx mode, it is possible for the interrupt to arrive at
3574          * the CPU before the status block posted prior to the interrupt.
3575          * Reading the PCI State register will confirm whether the
3576          * interrupt is ours and will flush the status block.
3577          */
3578         if ((sblk->status_tag != tp->last_tag) ||
3579             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3580                 /*
3581                  * writing any value to intr-mbox-0 clears PCI INTA# and
3582                  * chip-internal interrupt pending events.
3583                  * writing non-zero to intr-mbox-0 additional tells the
3584                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3585                  * event coalescing.
3586                  */
3587                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3588                              0x00000001);
3589                 if (tg3_irq_sync(tp))
3590                         goto out;
3591                 if (netif_rx_schedule_prep(dev)) {
3592                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3593                         /* Update last_tag to mark that this status has been
3594                          * seen. Because interrupt may be shared, we may be
3595                          * racing with tg3_poll(), so only update last_tag
3596                          * if tg3_poll() is not scheduled.
3597                          */
3598                         tp->last_tag = sblk->status_tag;
3599                         __netif_rx_schedule(dev);
3600                 }
3601         } else {        /* shared interrupt */
3602                 handled = 0;
3603         }
3604 out:
3605         return IRQ_RETVAL(handled);
3606 }
3607
3608 /* ISR for interrupt test */
3609 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3610 {
3611         struct net_device *dev = dev_id;
3612         struct tg3 *tp = netdev_priv(dev);
3613         struct tg3_hw_status *sblk = tp->hw_status;
3614
3615         if ((sblk->status & SD_STATUS_UPDATED) ||
3616             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3617                 tg3_disable_ints(tp);
3618                 return IRQ_RETVAL(1);
3619         }
3620         return IRQ_RETVAL(0);
3621 }
3622
3623 static int tg3_init_hw(struct tg3 *, int);
3624 static int tg3_halt(struct tg3 *, int, int);
3625
3626 /* Restart hardware after configuration changes, self-test, etc.
3627  * Invoked with tp->lock held.
3628  */
3629 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3630 {
3631         int err;
3632
3633         err = tg3_init_hw(tp, reset_phy);
3634         if (err) {
3635                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3636                        "aborting.\n", tp->dev->name);
3637                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3638                 tg3_full_unlock(tp);
3639                 del_timer_sync(&tp->timer);
3640                 tp->irq_sync = 0;
3641                 netif_poll_enable(tp->dev);
3642                 dev_close(tp->dev);
3643                 tg3_full_lock(tp, 0);
3644         }
3645         return err;
3646 }
3647
3648 #ifdef CONFIG_NET_POLL_CONTROLLER
3649 static void tg3_poll_controller(struct net_device *dev)
3650 {
3651         struct tg3 *tp = netdev_priv(dev);
3652
3653         tg3_interrupt(tp->pdev->irq, dev);
3654 }
3655 #endif
3656
3657 static void tg3_reset_task(void *_data)
3658 {
3659         struct tg3 *tp = _data;
3660         unsigned int restart_timer;
3661
3662         tg3_full_lock(tp, 0);
3663         tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3664
3665         if (!netif_running(tp->dev)) {
3666                 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3667                 tg3_full_unlock(tp);
3668                 return;
3669         }
3670
3671         tg3_full_unlock(tp);
3672
3673         tg3_netif_stop(tp);
3674
3675         tg3_full_lock(tp, 1);
3676
3677         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3678         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3679
3680         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3681                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3682                 tp->write32_rx_mbox = tg3_write_flush_reg32;
3683                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3684                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3685         }
3686
3687         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3688         if (tg3_init_hw(tp, 1))
3689                 goto out;
3690
3691         tg3_netif_start(tp);
3692
3693         if (restart_timer)
3694                 mod_timer(&tp->timer, jiffies + 1);
3695
3696 out:
3697         tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3698
3699         tg3_full_unlock(tp);
3700 }
3701
3702 static void tg3_tx_timeout(struct net_device *dev)
3703 {
3704         struct tg3 *tp = netdev_priv(dev);
3705
3706         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3707                dev->name);
3708
3709         schedule_work(&tp->reset_task);
3710 }
3711
3712 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3713 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3714 {
3715         u32 base = (u32) mapping & 0xffffffff;
3716
3717         return ((base > 0xffffdcc0) &&
3718                 (base + len + 8 < base));
3719 }
3720
3721 /* Test for DMA addresses > 40-bit */
3722 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3723                                           int len)
3724 {
3725 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3726         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3727                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3728         return 0;
3729 #else
3730         return 0;
3731 #endif
3732 }
3733
3734 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3735
3736 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3737 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3738                                        u32 last_plus_one, u32 *start,
3739                                        u32 base_flags, u32 mss)
3740 {
3741         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3742         dma_addr_t new_addr = 0;
3743         u32 entry = *start;
3744         int i, ret = 0;
3745
3746         if (!new_skb) {
3747                 ret = -1;
3748         } else {
3749                 /* New SKB is guaranteed to be linear. */
3750                 entry = *start;
3751                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3752                                           PCI_DMA_TODEVICE);
3753                 /* Make sure new skb does not cross any 4G boundaries.
3754                  * Drop the packet if it does.
3755                  */
3756                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3757                         ret = -1;
3758                         dev_kfree_skb(new_skb);
3759                         new_skb = NULL;
3760                 } else {
3761                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3762                                     base_flags, 1 | (mss << 1));
3763                         *start = NEXT_TX(entry);
3764                 }
3765         }
3766
3767         /* Now clean up the sw ring entries. */
3768         i = 0;
3769         while (entry != last_plus_one) {
3770                 int len;
3771
3772                 if (i == 0)
3773                         len = skb_headlen(skb);
3774                 else
3775                         len = skb_shinfo(skb)->frags[i-1].size;
3776                 pci_unmap_single(tp->pdev,
3777                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3778                                  len, PCI_DMA_TODEVICE);
3779                 if (i == 0) {
3780                         tp->tx_buffers[entry].skb = new_skb;
3781                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3782                 } else {
3783                         tp->tx_buffers[entry].skb = NULL;
3784                 }
3785                 entry = NEXT_TX(entry);
3786                 i++;
3787         }
3788
3789         dev_kfree_skb(skb);
3790
3791         return ret;
3792 }
3793
3794 static void tg3_set_txd(struct tg3 *tp, int entry,
3795                         dma_addr_t mapping, int len, u32 flags,
3796                         u32 mss_and_is_end)
3797 {
3798         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3799         int is_end = (mss_and_is_end & 0x1);
3800         u32 mss = (mss_and_is_end >> 1);
3801         u32 vlan_tag = 0;
3802
3803         if (is_end)
3804                 flags |= TXD_FLAG_END;
3805         if (flags & TXD_FLAG_VLAN) {
3806                 vlan_tag = flags >> 16;
3807                 flags &= 0xffff;
3808         }
3809         vlan_tag |= (mss << TXD_MSS_SHIFT);
3810
3811         txd->addr_hi = ((u64) mapping >> 32);
3812         txd->addr_lo = ((u64) mapping & 0xffffffff);
3813         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3814         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3815 }
3816
3817 /* hard_start_xmit for devices that don't have any bugs and
3818  * support TG3_FLG2_HW_TSO_2 only.
3819  */
3820 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3821 {
3822         struct tg3 *tp = netdev_priv(dev);
3823         dma_addr_t mapping;
3824         u32 len, entry, base_flags, mss;
3825
3826         len = skb_headlen(skb);
3827
3828         /* We are running in BH disabled context with netif_tx_lock
3829          * and TX reclaim runs via tp->poll inside of a software
3830          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3831          * no IRQ context deadlocks to worry about either.  Rejoice!
3832          */
3833         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3834                 if (!netif_queue_stopped(dev)) {
3835                         netif_stop_queue(dev);
3836
3837                         /* This is a hard error, log it. */
3838                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3839                                "queue awake!\n", dev->name);
3840                 }
3841                 return NETDEV_TX_BUSY;
3842         }
3843
3844         entry = tp->tx_prod;
3845         base_flags = 0;
3846 #if TG3_TSO_SUPPORT != 0
3847         mss = 0;
3848         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3849             (mss = skb_shinfo(skb)->gso_size) != 0) {
3850                 int tcp_opt_len, ip_tcp_len;
3851
3852                 if (skb_header_cloned(skb) &&
3853                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3854                         dev_kfree_skb(skb);
3855                         goto out_unlock;
3856                 }
3857
3858                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3859                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3860                 else {
3861                         tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3862                         ip_tcp_len = (skb->nh.iph->ihl * 4) +
3863                                      sizeof(struct tcphdr);
3864
3865                         skb->nh.iph->check = 0;
3866                         skb->nh.iph->tot_len = htons(mss + ip_tcp_len +
3867                                                      tcp_opt_len);
3868                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
3869                 }
3870
3871                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3872                                TXD_FLAG_CPU_POST_DMA);
3873
3874                 skb->h.th->check = 0;
3875
3876         }
3877         else if (skb->ip_summed == CHECKSUM_PARTIAL)
3878                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3879 #else
3880         mss = 0;
3881         if (skb->ip_summed == CHECKSUM_PARTIAL)
3882                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3883 #endif
3884 #if TG3_VLAN_TAG_USED
3885         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3886                 base_flags |= (TXD_FLAG_VLAN |
3887                                (vlan_tx_tag_get(skb) << 16));
3888 #endif
3889
3890         /* Queue skb data, a.k.a. the main skb fragment. */
3891         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3892
3893         tp->tx_buffers[entry].skb = skb;
3894         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3895
3896         tg3_set_txd(tp, entry, mapping, len, base_flags,
3897                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3898
3899         entry = NEXT_TX(entry);
3900
3901         /* Now loop through additional data fragments, and queue them. */
3902         if (skb_shinfo(skb)->nr_frags > 0) {
3903                 unsigned int i, last;
3904
3905                 last = skb_shinfo(skb)->nr_frags - 1;
3906                 for (i = 0; i <= last; i++) {
3907                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3908
3909                         len = frag->size;
3910                         mapping = pci_map_page(tp->pdev,
3911                                                frag->page,
3912                                                frag->page_offset,
3913                                                len, PCI_DMA_TODEVICE);
3914
3915                         tp->tx_buffers[entry].skb = NULL;
3916                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3917
3918                         tg3_set_txd(tp, entry, mapping, len,
3919                                     base_flags, (i == last) | (mss << 1));
3920
3921                         entry = NEXT_TX(entry);
3922                 }
3923         }
3924
3925         /* Packets are ready, update Tx producer idx local and on card. */
3926         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3927
3928         tp->tx_prod = entry;
3929         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3930                 netif_stop_queue(dev);
3931                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3932                         netif_wake_queue(tp->dev);
3933         }
3934
3935 out_unlock:
3936         mmiowb();
3937
3938         dev->trans_start = jiffies;
3939
3940         return NETDEV_TX_OK;
3941 }
3942
3943 #if TG3_TSO_SUPPORT != 0
3944 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3945
3946 /* Use GSO to workaround a rare TSO bug that may be triggered when the
3947  * TSO header is greater than 80 bytes.
3948  */
3949 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3950 {
3951         struct sk_buff *segs, *nskb;
3952
3953         /* Estimate the number of fragments in the worst case */
3954         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
3955                 netif_stop_queue(tp->dev);
3956                 return NETDEV_TX_BUSY;
3957         }
3958
3959         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
3960         if (unlikely(IS_ERR(segs)))
3961                 goto tg3_tso_bug_end;
3962
3963         do {
3964                 nskb = segs;
3965                 segs = segs->next;
3966                 nskb->next = NULL;
3967                 tg3_start_xmit_dma_bug(nskb, tp->dev);
3968         } while (segs);
3969
3970 tg3_tso_bug_end:
3971         dev_kfree_skb(skb);
3972
3973         return NETDEV_TX_OK;
3974 }
3975 #endif
3976
3977 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
3978  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
3979  */
3980 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
3981 {
3982         struct tg3 *tp = netdev_priv(dev);
3983         dma_addr_t mapping;
3984         u32 len, entry, base_flags, mss;
3985         int would_hit_hwbug;
3986
3987         len = skb_headlen(skb);
3988
3989         /* We are running in BH disabled context with netif_tx_lock
3990          * and TX reclaim runs via tp->poll inside of a software
3991          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3992          * no IRQ context deadlocks to worry about either.  Rejoice!
3993          */
3994         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3995                 if (!netif_queue_stopped(dev)) {
3996                         netif_stop_queue(dev);
3997
3998                         /* This is a hard error, log it. */
3999                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4000                                "queue awake!\n", dev->name);
4001                 }
4002                 return NETDEV_TX_BUSY;
4003         }
4004
4005         entry = tp->tx_prod;
4006         base_flags = 0;
4007         if (skb->ip_summed == CHECKSUM_PARTIAL)
4008                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4009 #if TG3_TSO_SUPPORT != 0
4010         mss = 0;
4011         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
4012             (mss = skb_shinfo(skb)->gso_size) != 0) {
4013                 int tcp_opt_len, ip_tcp_len, hdr_len;
4014
4015                 if (skb_header_cloned(skb) &&
4016                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4017                         dev_kfree_skb(skb);
4018                         goto out_unlock;
4019                 }
4020
4021                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4022                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
4023
4024                 hdr_len = ip_tcp_len + tcp_opt_len;
4025                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4026                              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG))
4027                         return (tg3_tso_bug(tp, skb));
4028
4029                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4030                                TXD_FLAG_CPU_POST_DMA);
4031
4032                 skb->nh.iph->check = 0;
4033                 skb->nh.iph->tot_len = htons(mss + hdr_len);
4034                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4035                         skb->h.th->check = 0;
4036                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4037                 }
4038                 else {
4039                         skb->h.th->check =
4040                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4041                                                    skb->nh.iph->daddr,
4042                                                    0, IPPROTO_TCP, 0);
4043                 }
4044
4045                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4046                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4047                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4048                                 int tsflags;
4049
4050                                 tsflags = ((skb->nh.iph->ihl - 5) +
4051                                            (tcp_opt_len >> 2));
4052                                 mss |= (tsflags << 11);
4053                         }
4054                 } else {
4055                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4056                                 int tsflags;
4057
4058                                 tsflags = ((skb->nh.iph->ihl - 5) +
4059                                            (tcp_opt_len >> 2));
4060                                 base_flags |= tsflags << 12;
4061                         }
4062                 }
4063         }
4064 #else
4065         mss = 0;
4066 #endif
4067 #if TG3_VLAN_TAG_USED
4068         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4069                 base_flags |= (TXD_FLAG_VLAN |
4070                                (vlan_tx_tag_get(skb) << 16));
4071 #endif
4072
4073         /* Queue skb data, a.k.a. the main skb fragment. */
4074         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4075
4076         tp->tx_buffers[entry].skb = skb;
4077         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4078
4079         would_hit_hwbug = 0;
4080
4081         if (tg3_4g_overflow_test(mapping, len))
4082                 would_hit_hwbug = 1;
4083
4084         tg3_set_txd(tp, entry, mapping, len, base_flags,
4085                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4086
4087         entry = NEXT_TX(entry);
4088
4089         /* Now loop through additional data fragments, and queue them. */
4090         if (skb_shinfo(skb)->nr_frags > 0) {
4091                 unsigned int i, last;
4092
4093                 last = skb_shinfo(skb)->nr_frags - 1;
4094                 for (i = 0; i <= last; i++) {
4095                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4096
4097                         len = frag->size;
4098                         mapping = pci_map_page(tp->pdev,
4099                                                frag->page,
4100                                                frag->page_offset,
4101                                                len, PCI_DMA_TODEVICE);
4102
4103                         tp->tx_buffers[entry].skb = NULL;
4104                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4105
4106                         if (tg3_4g_overflow_test(mapping, len))
4107                                 would_hit_hwbug = 1;
4108
4109                         if (tg3_40bit_overflow_test(tp, mapping, len))
4110                                 would_hit_hwbug = 1;
4111
4112                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4113                                 tg3_set_txd(tp, entry, mapping, len,
4114                                             base_flags, (i == last)|(mss << 1));
4115                         else
4116                                 tg3_set_txd(tp, entry, mapping, len,
4117                                             base_flags, (i == last));
4118
4119                         entry = NEXT_TX(entry);
4120                 }
4121         }
4122
4123         if (would_hit_hwbug) {
4124                 u32 last_plus_one = entry;
4125                 u32 start;
4126
4127                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4128                 start &= (TG3_TX_RING_SIZE - 1);
4129
4130                 /* If the workaround fails due to memory/mapping
4131                  * failure, silently drop this packet.
4132                  */
4133                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4134                                                 &start, base_flags, mss))
4135                         goto out_unlock;
4136
4137                 entry = start;
4138         }
4139
4140         /* Packets are ready, update Tx producer idx local and on card. */
4141         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4142
4143         tp->tx_prod = entry;
4144         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4145                 netif_stop_queue(dev);
4146                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4147                         netif_wake_queue(tp->dev);
4148         }
4149
4150 out_unlock:
4151         mmiowb();
4152
4153         dev->trans_start = jiffies;
4154
4155         return NETDEV_TX_OK;
4156 }
4157
4158 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4159                                int new_mtu)
4160 {
4161         dev->mtu = new_mtu;
4162
4163         if (new_mtu > ETH_DATA_LEN) {
4164                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4165                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4166                         ethtool_op_set_tso(dev, 0);
4167                 }
4168                 else
4169                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4170         } else {
4171                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4172                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4173                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4174         }
4175 }
4176
4177 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4178 {
4179         struct tg3 *tp = netdev_priv(dev);
4180         int err;
4181
4182         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4183                 return -EINVAL;
4184
4185         if (!netif_running(dev)) {
4186                 /* We'll just catch it later when the
4187                  * device is up'd.
4188                  */
4189                 tg3_set_mtu(dev, tp, new_mtu);
4190                 return 0;
4191         }
4192
4193         tg3_netif_stop(tp);
4194
4195         tg3_full_lock(tp, 1);
4196
4197         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4198
4199         tg3_set_mtu(dev, tp, new_mtu);
4200
4201         err = tg3_restart_hw(tp, 0);
4202
4203         if (!err)
4204                 tg3_netif_start(tp);
4205
4206         tg3_full_unlock(tp);
4207
4208         return err;
4209 }
4210
4211 /* Free up pending packets in all rx/tx rings.
4212  *
4213  * The chip has been shut down and the driver detached from
4214  * the networking, so no interrupts or new tx packets will
4215  * end up in the driver.  tp->{tx,}lock is not held and we are not
4216  * in an interrupt context and thus may sleep.
4217  */
4218 static void tg3_free_rings(struct tg3 *tp)
4219 {
4220         struct ring_info *rxp;
4221         int i;
4222
4223         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4224                 rxp = &tp->rx_std_buffers[i];
4225
4226                 if (rxp->skb == NULL)
4227                         continue;
4228                 pci_unmap_single(tp->pdev,
4229                                  pci_unmap_addr(rxp, mapping),
4230                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4231                                  PCI_DMA_FROMDEVICE);
4232                 dev_kfree_skb_any(rxp->skb);
4233                 rxp->skb = NULL;
4234         }
4235
4236         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4237                 rxp = &tp->rx_jumbo_buffers[i];
4238
4239                 if (rxp->skb == NULL)
4240                         continue;
4241                 pci_unmap_single(tp->pdev,
4242                                  pci_unmap_addr(rxp, mapping),
4243                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4244                                  PCI_DMA_FROMDEVICE);
4245                 dev_kfree_skb_any(rxp->skb);
4246                 rxp->skb = NULL;
4247         }
4248
4249         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4250                 struct tx_ring_info *txp;
4251                 struct sk_buff *skb;
4252                 int j;
4253
4254                 txp = &tp->tx_buffers[i];
4255                 skb = txp->skb;
4256
4257                 if (skb == NULL) {
4258                         i++;
4259                         continue;
4260                 }
4261
4262                 pci_unmap_single(tp->pdev,
4263                                  pci_unmap_addr(txp, mapping),
4264                                  skb_headlen(skb),
4265                                  PCI_DMA_TODEVICE);
4266                 txp->skb = NULL;
4267
4268                 i++;
4269
4270                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4271                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4272                         pci_unmap_page(tp->pdev,
4273                                        pci_unmap_addr(txp, mapping),
4274                                        skb_shinfo(skb)->frags[j].size,
4275                                        PCI_DMA_TODEVICE);
4276                         i++;
4277                 }
4278
4279                 dev_kfree_skb_any(skb);
4280         }
4281 }
4282
4283 /* Initialize tx/rx rings for packet processing.
4284  *
4285  * The chip has been shut down and the driver detached from
4286  * the networking, so no interrupts or new tx packets will
4287  * end up in the driver.  tp->{tx,}lock are held and thus
4288  * we may not sleep.
4289  */
4290 static int tg3_init_rings(struct tg3 *tp)
4291 {
4292         u32 i;
4293
4294         /* Free up all the SKBs. */
4295         tg3_free_rings(tp);
4296
4297         /* Zero out all descriptors. */
4298         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4299         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4300         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4301         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4302
4303         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4304         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4305             (tp->dev->mtu > ETH_DATA_LEN))
4306                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4307
4308         /* Initialize invariants of the rings, we only set this
4309          * stuff once.  This works because the card does not
4310          * write into the rx buffer posting rings.
4311          */
4312         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4313                 struct tg3_rx_buffer_desc *rxd;
4314
4315                 rxd = &tp->rx_std[i];
4316                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4317                         << RXD_LEN_SHIFT;
4318                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4319                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4320                                (i << RXD_OPAQUE_INDEX_SHIFT));
4321         }
4322
4323         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4324                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4325                         struct tg3_rx_buffer_desc *rxd;
4326
4327                         rxd = &tp->rx_jumbo[i];
4328                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4329                                 << RXD_LEN_SHIFT;
4330                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4331                                 RXD_FLAG_JUMBO;
4332                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4333                                (i << RXD_OPAQUE_INDEX_SHIFT));
4334                 }
4335         }
4336
4337         /* Now allocate fresh SKBs for each rx ring. */
4338         for (i = 0; i < tp->rx_pending; i++) {
4339                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4340                         printk(KERN_WARNING PFX
4341                                "%s: Using a smaller RX standard ring, "
4342                                "only %d out of %d buffers were allocated "
4343                                "successfully.\n",
4344                                tp->dev->name, i, tp->rx_pending);
4345                         if (i == 0)
4346                                 return -ENOMEM;
4347                         tp->rx_pending = i;
4348                         break;
4349                 }
4350         }
4351
4352         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4353                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4354                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4355                                              -1, i) < 0) {
4356                                 printk(KERN_WARNING PFX
4357                                        "%s: Using a smaller RX jumbo ring, "
4358                                        "only %d out of %d buffers were "
4359                                        "allocated successfully.\n",
4360                                        tp->dev->name, i, tp->rx_jumbo_pending);
4361                                 if (i == 0) {
4362                                         tg3_free_rings(tp);
4363                                         return -ENOMEM;
4364                                 }
4365                                 tp->rx_jumbo_pending = i;
4366                                 break;
4367                         }
4368                 }
4369         }
4370         return 0;
4371 }
4372
4373 /*
4374  * Must not be invoked with interrupt sources disabled and
4375  * the hardware shutdown down.
4376  */
4377 static void tg3_free_consistent(struct tg3 *tp)
4378 {
4379         kfree(tp->rx_std_buffers);
4380         tp->rx_std_buffers = NULL;
4381         if (tp->rx_std) {
4382                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4383                                     tp->rx_std, tp->rx_std_mapping);
4384                 tp->rx_std = NULL;
4385         }
4386         if (tp->rx_jumbo) {
4387                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4388                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4389                 tp->rx_jumbo = NULL;
4390         }
4391         if (tp->rx_rcb) {
4392                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4393                                     tp->rx_rcb, tp->rx_rcb_mapping);
4394                 tp->rx_rcb = NULL;
4395         }
4396         if (tp->tx_ring) {
4397                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4398                         tp->tx_ring, tp->tx_desc_mapping);
4399                 tp->tx_ring = NULL;
4400         }
4401         if (tp->hw_status) {
4402                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4403                                     tp->hw_status, tp->status_mapping);
4404                 tp->hw_status = NULL;
4405         }
4406         if (tp->hw_stats) {
4407                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4408                                     tp->hw_stats, tp->stats_mapping);
4409                 tp->hw_stats = NULL;
4410         }
4411 }
4412
4413 /*
4414  * Must not be invoked with interrupt sources disabled and
4415  * the hardware shutdown down.  Can sleep.
4416  */
4417 static int tg3_alloc_consistent(struct tg3 *tp)
4418 {
4419         tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
4420                                       (TG3_RX_RING_SIZE +
4421                                        TG3_RX_JUMBO_RING_SIZE)) +
4422                                      (sizeof(struct tx_ring_info) *
4423                                       TG3_TX_RING_SIZE),
4424                                      GFP_KERNEL);
4425         if (!tp->rx_std_buffers)
4426                 return -ENOMEM;
4427
4428         memset(tp->rx_std_buffers, 0,
4429                (sizeof(struct ring_info) *
4430                 (TG3_RX_RING_SIZE +
4431                  TG3_RX_JUMBO_RING_SIZE)) +
4432                (sizeof(struct tx_ring_info) *
4433                 TG3_TX_RING_SIZE));
4434
4435         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4436         tp->tx_buffers = (struct tx_ring_info *)
4437                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4438
4439         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4440                                           &tp->rx_std_mapping);
4441         if (!tp->rx_std)
4442                 goto err_out;
4443
4444         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4445                                             &tp->rx_jumbo_mapping);
4446
4447         if (!tp->rx_jumbo)
4448                 goto err_out;
4449
4450         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4451                                           &tp->rx_rcb_mapping);
4452         if (!tp->rx_rcb)
4453                 goto err_out;
4454
4455         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4456                                            &tp->tx_desc_mapping);
4457         if (!tp->tx_ring)
4458                 goto err_out;
4459
4460         tp->hw_status = pci_alloc_consistent(tp->pdev,
4461                                              TG3_HW_STATUS_SIZE,
4462                                              &tp->status_mapping);
4463         if (!tp->hw_status)
4464                 goto err_out;
4465
4466         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4467                                             sizeof(struct tg3_hw_stats),
4468                                             &tp->stats_mapping);
4469         if (!tp->hw_stats)
4470                 goto err_out;
4471
4472         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4473         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4474
4475         return 0;
4476
4477 err_out:
4478         tg3_free_consistent(tp);
4479         return -ENOMEM;
4480 }
4481
4482 #define MAX_WAIT_CNT 1000
4483
4484 /* To stop a block, clear the enable bit and poll till it
4485  * clears.  tp->lock is held.
4486  */
4487 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4488 {
4489         unsigned int i;
4490         u32 val;
4491
4492         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4493                 switch (ofs) {
4494                 case RCVLSC_MODE:
4495                 case DMAC_MODE:
4496                 case MBFREE_MODE:
4497                 case BUFMGR_MODE:
4498                 case MEMARB_MODE:
4499                         /* We can't enable/disable these bits of the
4500                          * 5705/5750, just say success.
4501                          */
4502                         return 0;
4503
4504                 default:
4505                         break;
4506                 };
4507         }
4508
4509         val = tr32(ofs);
4510         val &= ~enable_bit;
4511         tw32_f(ofs, val);
4512
4513         for (i = 0; i < MAX_WAIT_CNT; i++) {
4514                 udelay(100);
4515                 val = tr32(ofs);
4516                 if ((val & enable_bit) == 0)
4517                         break;
4518         }
4519
4520         if (i == MAX_WAIT_CNT && !silent) {
4521                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4522                        "ofs=%lx enable_bit=%x\n",
4523                        ofs, enable_bit);
4524                 return -ENODEV;
4525         }
4526
4527         return 0;
4528 }
4529
4530 /* tp->lock is held. */
4531 static int tg3_abort_hw(struct tg3 *tp, int silent)
4532 {
4533         int i, err;
4534
4535         tg3_disable_ints(tp);
4536
4537         tp->rx_mode &= ~RX_MODE_ENABLE;
4538         tw32_f(MAC_RX_MODE, tp->rx_mode);
4539         udelay(10);
4540
4541         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4542         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4543         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4544         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4545         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4546         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4547
4548         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4549         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4550         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4551         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4552         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4553         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4554         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4555
4556         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4557         tw32_f(MAC_MODE, tp->mac_mode);
4558         udelay(40);
4559
4560         tp->tx_mode &= ~TX_MODE_ENABLE;
4561         tw32_f(MAC_TX_MODE, tp->tx_mode);
4562
4563         for (i = 0; i < MAX_WAIT_CNT; i++) {
4564                 udelay(100);
4565                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4566                         break;
4567         }
4568         if (i >= MAX_WAIT_CNT) {
4569                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4570                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4571                        tp->dev->name, tr32(MAC_TX_MODE));
4572                 err |= -ENODEV;
4573         }
4574
4575         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4576         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4577         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4578
4579         tw32(FTQ_RESET, 0xffffffff);
4580         tw32(FTQ_RESET, 0x00000000);
4581
4582         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4583         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4584
4585         if (tp->hw_status)
4586                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4587         if (tp->hw_stats)
4588                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4589
4590         return err;
4591 }
4592
4593 /* tp->lock is held. */
4594 static int tg3_nvram_lock(struct tg3 *tp)
4595 {
4596         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4597                 int i;
4598
4599                 if (tp->nvram_lock_cnt == 0) {
4600                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4601                         for (i = 0; i < 8000; i++) {
4602                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4603                                         break;
4604                                 udelay(20);
4605                         }
4606                         if (i == 8000) {
4607                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4608                                 return -ENODEV;
4609                         }
4610                 }
4611                 tp->nvram_lock_cnt++;
4612         }
4613         return 0;
4614 }
4615
4616 /* tp->lock is held. */
4617 static void tg3_nvram_unlock(struct tg3 *tp)
4618 {
4619         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4620                 if (tp->nvram_lock_cnt > 0)
4621                         tp->nvram_lock_cnt--;
4622                 if (tp->nvram_lock_cnt == 0)
4623                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4624         }
4625 }
4626
4627 /* tp->lock is held. */
4628 static void tg3_enable_nvram_access(struct tg3 *tp)
4629 {
4630         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4631             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4632                 u32 nvaccess = tr32(NVRAM_ACCESS);
4633
4634                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4635         }
4636 }
4637
4638 /* tp->lock is held. */
4639 static void tg3_disable_nvram_access(struct tg3 *tp)
4640 {
4641         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4642             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4643                 u32 nvaccess = tr32(NVRAM_ACCESS);
4644
4645                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4646         }
4647 }
4648
4649 /* tp->lock is held. */
4650 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4651 {
4652         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4653                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4654
4655         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4656                 switch (kind) {
4657                 case RESET_KIND_INIT:
4658                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4659                                       DRV_STATE_START);
4660                         break;
4661
4662                 case RESET_KIND_SHUTDOWN:
4663                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4664                                       DRV_STATE_UNLOAD);
4665                         break;
4666
4667                 case RESET_KIND_SUSPEND:
4668                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4669                                       DRV_STATE_SUSPEND);
4670                         break;
4671
4672                 default:
4673                         break;
4674                 };
4675         }
4676 }
4677
4678 /* tp->lock is held. */
4679 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4680 {
4681         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4682                 switch (kind) {
4683                 case RESET_KIND_INIT:
4684                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4685                                       DRV_STATE_START_DONE);
4686                         break;
4687
4688                 case RESET_KIND_SHUTDOWN:
4689                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4690                                       DRV_STATE_UNLOAD_DONE);
4691                         break;
4692
4693                 default:
4694                         break;
4695                 };
4696         }
4697 }
4698
4699 /* tp->lock is held. */
4700 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4701 {
4702         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4703                 switch (kind) {
4704                 case RESET_KIND_INIT:
4705                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4706                                       DRV_STATE_START);
4707                         break;
4708
4709                 case RESET_KIND_SHUTDOWN:
4710                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4711                                       DRV_STATE_UNLOAD);
4712                         break;
4713
4714                 case RESET_KIND_SUSPEND:
4715                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4716                                       DRV_STATE_SUSPEND);
4717                         break;
4718
4719                 default:
4720                         break;
4721                 };
4722         }
4723 }
4724
4725 static int tg3_poll_fw(struct tg3 *tp)
4726 {
4727         int i;
4728         u32 val;
4729
4730         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4731                 for (i = 0; i < 400; i++) {
4732                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4733                                 return 0;
4734                         udelay(10);
4735                 }
4736                 return -ENODEV;
4737         }
4738
4739         /* Wait for firmware initialization to complete. */
4740         for (i = 0; i < 100000; i++) {
4741                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4742                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4743                         break;
4744                 udelay(10);
4745         }
4746
4747         /* Chip might not be fitted with firmware.  Some Sun onboard
4748          * parts are configured like that.  So don't signal the timeout
4749          * of the above loop as an error, but do report the lack of
4750          * running firmware once.
4751          */
4752         if (i >= 100000 &&
4753             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4754                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4755
4756                 printk(KERN_INFO PFX "%s: No firmware running.\n",
4757                        tp->dev->name);
4758         }
4759
4760         return 0;
4761 }
4762
4763 static void tg3_stop_fw(struct tg3 *);
4764
4765 /* tp->lock is held. */
4766 static int tg3_chip_reset(struct tg3 *tp)
4767 {
4768         u32 val;
4769         void (*write_op)(struct tg3 *, u32, u32);
4770         int err;
4771
4772         tg3_nvram_lock(tp);
4773
4774         /* No matching tg3_nvram_unlock() after this because
4775          * chip reset below will undo the nvram lock.
4776          */
4777         tp->nvram_lock_cnt = 0;
4778
4779         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4780             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4781             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4782                 tw32(GRC_FASTBOOT_PC, 0);
4783
4784         /*
4785          * We must avoid the readl() that normally takes place.
4786          * It locks machines, causes machine checks, and other
4787          * fun things.  So, temporarily disable the 5701
4788          * hardware workaround, while we do the reset.
4789          */
4790         write_op = tp->write32;
4791         if (write_op == tg3_write_flush_reg32)
4792                 tp->write32 = tg3_write32;
4793
4794         /* do the reset */
4795         val = GRC_MISC_CFG_CORECLK_RESET;
4796
4797         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4798                 if (tr32(0x7e2c) == 0x60) {
4799                         tw32(0x7e2c, 0x20);
4800                 }
4801                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4802                         tw32(GRC_MISC_CFG, (1 << 29));
4803                         val |= (1 << 29);
4804                 }
4805         }
4806
4807         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4808                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4809                 tw32(GRC_VCPU_EXT_CTRL,
4810                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4811         }
4812
4813         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4814                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4815         tw32(GRC_MISC_CFG, val);
4816
4817         /* restore 5701 hardware bug workaround write method */
4818         tp->write32 = write_op;
4819
4820         /* Unfortunately, we have to delay before the PCI read back.
4821          * Some 575X chips even will not respond to a PCI cfg access
4822          * when the reset command is given to the chip.
4823          *
4824          * How do these hardware designers expect things to work
4825          * properly if the PCI write is posted for a long period
4826          * of time?  It is always necessary to have some method by
4827          * which a register read back can occur to push the write
4828          * out which does the reset.
4829          *
4830          * For most tg3 variants the trick below was working.
4831          * Ho hum...
4832          */
4833         udelay(120);
4834
4835         /* Flush PCI posted writes.  The normal MMIO registers
4836          * are inaccessible at this time so this is the only
4837          * way to make this reliably (actually, this is no longer
4838          * the case, see above).  I tried to use indirect
4839          * register read/write but this upset some 5701 variants.
4840          */
4841         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4842
4843         udelay(120);
4844
4845         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4846                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4847                         int i;
4848                         u32 cfg_val;
4849
4850                         /* Wait for link training to complete.  */
4851                         for (i = 0; i < 5000; i++)
4852                                 udelay(100);
4853
4854                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4855                         pci_write_config_dword(tp->pdev, 0xc4,
4856                                                cfg_val | (1 << 15));
4857                 }
4858                 /* Set PCIE max payload size and clear error status.  */
4859                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4860         }
4861
4862         /* Re-enable indirect register accesses. */
4863         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4864                                tp->misc_host_ctrl);
4865
4866         /* Set MAX PCI retry to zero. */
4867         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4868         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4869             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4870                 val |= PCISTATE_RETRY_SAME_DMA;
4871         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4872
4873         pci_restore_state(tp->pdev);
4874
4875         /* Make sure PCI-X relaxed ordering bit is clear. */
4876         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4877         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4878         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4879
4880         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4881                 u32 val;
4882
4883                 /* Chip reset on 5780 will reset MSI enable bit,
4884                  * so need to restore it.
4885                  */
4886                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4887                         u16 ctrl;
4888
4889                         pci_read_config_word(tp->pdev,
4890                                              tp->msi_cap + PCI_MSI_FLAGS,
4891                                              &ctrl);
4892                         pci_write_config_word(tp->pdev,
4893                                               tp->msi_cap + PCI_MSI_FLAGS,
4894                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4895                         val = tr32(MSGINT_MODE);
4896                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4897                 }
4898
4899                 val = tr32(MEMARB_MODE);
4900                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4901
4902         } else
4903                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4904
4905         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4906                 tg3_stop_fw(tp);
4907                 tw32(0x5000, 0x400);
4908         }
4909
4910         tw32(GRC_MODE, tp->grc_mode);
4911
4912         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4913                 u32 val = tr32(0xc4);
4914
4915                 tw32(0xc4, val | (1 << 15));
4916         }
4917
4918         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4919             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4920                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4921                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4922                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4923                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4924         }
4925
4926         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4927                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4928                 tw32_f(MAC_MODE, tp->mac_mode);
4929         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4930                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4931                 tw32_f(MAC_MODE, tp->mac_mode);
4932         } else
4933                 tw32_f(MAC_MODE, 0);
4934         udelay(40);
4935
4936         err = tg3_poll_fw(tp);
4937         if (err)
4938                 return err;
4939
4940         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4941             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4942                 u32 val = tr32(0x7c00);
4943
4944                 tw32(0x7c00, val | (1 << 25));
4945         }
4946
4947         /* Reprobe ASF enable state.  */
4948         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4949         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4950         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4951         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4952                 u32 nic_cfg;
4953
4954                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4955                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4956                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4957                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4958                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4959                 }
4960         }
4961
4962         return 0;
4963 }
4964
4965 /* tp->lock is held. */
4966 static void tg3_stop_fw(struct tg3 *tp)
4967 {
4968         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4969                 u32 val;
4970                 int i;
4971
4972                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4973                 val = tr32(GRC_RX_CPU_EVENT);
4974                 val |= (1 << 14);
4975                 tw32(GRC_RX_CPU_EVENT, val);
4976
4977                 /* Wait for RX cpu to ACK the event.  */
4978                 for (i = 0; i < 100; i++) {
4979                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4980                                 break;
4981                         udelay(1);
4982                 }
4983         }
4984 }
4985
4986 /* tp->lock is held. */
4987 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4988 {
4989         int err;
4990
4991         tg3_stop_fw(tp);
4992
4993         tg3_write_sig_pre_reset(tp, kind);
4994
4995         tg3_abort_hw(tp, silent);
4996         err = tg3_chip_reset(tp);
4997
4998         tg3_write_sig_legacy(tp, kind);
4999         tg3_write_sig_post_reset(tp, kind);
5000
5001         if (err)
5002                 return err;
5003
5004         return 0;
5005 }
5006
5007 #define TG3_FW_RELEASE_MAJOR    0x0
5008 #define TG3_FW_RELASE_MINOR     0x0
5009 #define TG3_FW_RELEASE_FIX      0x0
5010 #define TG3_FW_START_ADDR       0x08000000
5011 #define TG3_FW_TEXT_ADDR        0x08000000
5012 #define TG3_FW_TEXT_LEN         0x9c0
5013 #define TG3_FW_RODATA_ADDR      0x080009c0
5014 #define TG3_FW_RODATA_LEN       0x60
5015 #define TG3_FW_DATA_ADDR        0x08000a40
5016 #define TG3_FW_DATA_LEN         0x20
5017 #define TG3_FW_SBSS_ADDR        0x08000a60
5018 #define TG3_FW_SBSS_LEN         0xc
5019 #define TG3_FW_BSS_ADDR         0x08000a70
5020 #define TG3_FW_BSS_LEN          0x10
5021
5022 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5023         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5024         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5025         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5026         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5027         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5028         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5029         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5030         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5031         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5032         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5033         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5034         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5035         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5036         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5037         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5038         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5039         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5040         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5041         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5042         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5043         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5044         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5045         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5046         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5047         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5048         0, 0, 0, 0, 0, 0,
5049         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5050         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5051         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5052         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5053         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5054         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5055         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5056         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5057         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5058         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5059         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5060         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5061         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5062         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5063         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5064         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5065         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5066         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5067         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5068         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5069         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5070         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5071         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5072         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5073         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5074         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5075         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5076         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5077         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5078         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5079         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5080         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5081         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5082         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5083         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5084         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5085         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5086         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5087         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5088         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5089         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5090         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5091         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5092         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5093         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5094         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5095         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5096         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5097         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5098         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5099         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5100         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5101         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5102         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5103         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5104         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5105         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5106         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5107         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5108         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5109         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5110         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5111         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5112         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5113         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5114 };
5115
5116 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5117         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5118         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5119         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5120         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5121         0x00000000
5122 };
5123
5124 #if 0 /* All zeros, don't eat up space with it. */
5125 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5126         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5127         0x00000000, 0x00000000, 0x00000000, 0x00000000
5128 };
5129 #endif
5130
5131 #define RX_CPU_SCRATCH_BASE     0x30000
5132 #define RX_CPU_SCRATCH_SIZE     0x04000
5133 #define TX_CPU_SCRATCH_BASE     0x34000
5134 #define TX_CPU_SCRATCH_SIZE     0x04000
5135
5136 /* tp->lock is held. */
5137 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5138 {
5139         int i;
5140
5141         BUG_ON(offset == TX_CPU_BASE &&
5142             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5143
5144         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5145                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5146
5147                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5148                 return 0;
5149         }
5150         if (offset == RX_CPU_BASE) {
5151                 for (i = 0; i < 10000; i++) {
5152                         tw32(offset + CPU_STATE, 0xffffffff);
5153                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5154                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5155                                 break;
5156                 }
5157
5158                 tw32(offset + CPU_STATE, 0xffffffff);
5159                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5160                 udelay(10);
5161         } else {
5162                 for (i = 0; i < 10000; i++) {
5163                         tw32(offset + CPU_STATE, 0xffffffff);
5164                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5165                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5166                                 break;
5167                 }
5168         }
5169
5170         if (i >= 10000) {
5171                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5172                        "and %s CPU\n",
5173                        tp->dev->name,
5174                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5175                 return -ENODEV;
5176         }
5177
5178         /* Clear firmware's nvram arbitration. */
5179         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5180                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5181         return 0;
5182 }
5183
5184 struct fw_info {
5185         unsigned int text_base;
5186         unsigned int text_len;
5187         const u32 *text_data;
5188         unsigned int rodata_base;
5189         unsigned int rodata_len;
5190         const u32 *rodata_data;
5191         unsigned int data_base;
5192         unsigned int data_len;
5193         const u32 *data_data;
5194 };
5195
5196 /* tp->lock is held. */
5197 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5198                                  int cpu_scratch_size, struct fw_info *info)
5199 {
5200         int err, lock_err, i;
5201         void (*write_op)(struct tg3 *, u32, u32);
5202
5203         if (cpu_base == TX_CPU_BASE &&
5204             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5205                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5206                        "TX cpu firmware on %s which is 5705.\n",
5207                        tp->dev->name);
5208                 return -EINVAL;
5209         }
5210
5211         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5212                 write_op = tg3_write_mem;
5213         else
5214                 write_op = tg3_write_indirect_reg32;
5215
5216         /* It is possible that bootcode is still loading at this point.
5217          * Get the nvram lock first before halting the cpu.
5218          */
5219         lock_err = tg3_nvram_lock(tp);
5220         err = tg3_halt_cpu(tp, cpu_base);
5221         if (!lock_err)
5222                 tg3_nvram_unlock(tp);
5223         if (err)
5224                 goto out;
5225
5226         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5227                 write_op(tp, cpu_scratch_base + i, 0);
5228         tw32(cpu_base + CPU_STATE, 0xffffffff);
5229         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5230         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5231                 write_op(tp, (cpu_scratch_base +
5232                               (info->text_base & 0xffff) +
5233                               (i * sizeof(u32))),
5234                          (info->text_data ?
5235                           info->text_data[i] : 0));
5236         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5237                 write_op(tp, (cpu_scratch_base +
5238                               (info->rodata_base & 0xffff) +
5239                               (i * sizeof(u32))),
5240                          (info->rodata_data ?
5241                           info->rodata_data[i] : 0));
5242         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5243                 write_op(tp, (cpu_scratch_base +
5244                               (info->data_base & 0xffff) +
5245                               (i * sizeof(u32))),
5246                          (info->data_data ?
5247                           info->data_data[i] : 0));
5248
5249         err = 0;
5250
5251 out:
5252         return err;
5253 }
5254
5255 /* tp->lock is held. */
5256 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5257 {
5258         struct fw_info info;
5259         int err, i;
5260
5261         info.text_base = TG3_FW_TEXT_ADDR;
5262         info.text_len = TG3_FW_TEXT_LEN;
5263         info.text_data = &tg3FwText[0];
5264         info.rodata_base = TG3_FW_RODATA_ADDR;
5265         info.rodata_len = TG3_FW_RODATA_LEN;
5266         info.rodata_data = &tg3FwRodata[0];
5267         info.data_base = TG3_FW_DATA_ADDR;
5268         info.data_len = TG3_FW_DATA_LEN;
5269         info.data_data = NULL;
5270
5271         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5272                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5273                                     &info);
5274         if (err)
5275                 return err;
5276
5277         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5278                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5279                                     &info);
5280         if (err)
5281                 return err;
5282
5283         /* Now startup only the RX cpu. */
5284         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5285         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5286
5287         for (i = 0; i < 5; i++) {
5288                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5289                         break;
5290                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5291                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5292                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5293                 udelay(1000);
5294         }
5295         if (i >= 5) {
5296                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5297                        "to set RX CPU PC, is %08x should be %08x\n",
5298                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5299                        TG3_FW_TEXT_ADDR);
5300                 return -ENODEV;
5301         }
5302         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5303         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5304
5305         return 0;
5306 }
5307
5308 #if TG3_TSO_SUPPORT != 0
5309
5310 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5311 #define TG3_TSO_FW_RELASE_MINOR         0x6
5312 #define TG3_TSO_FW_RELEASE_FIX          0x0
5313 #define TG3_TSO_FW_START_ADDR           0x08000000
5314 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5315 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5316 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5317 #define TG3_TSO_FW_RODATA_LEN           0x60
5318 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5319 #define TG3_TSO_FW_DATA_LEN             0x30
5320 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5321 #define TG3_TSO_FW_SBSS_LEN             0x2c
5322 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5323 #define TG3_TSO_FW_BSS_LEN              0x894
5324
5325 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5326         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5327         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5328         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5329         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5330         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5331         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5332         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5333         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5334         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5335         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5336         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5337         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5338         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5339         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5340         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5341         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5342         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5343         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5344         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5345         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5346         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5347         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5348         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5349         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5350         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5351         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5352         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5353         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5354         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5355         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5356         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5357         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5358         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5359         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5360         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5361         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5362         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5363         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5364         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5365         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5366         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5367         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5368         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5369         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5370         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5371         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5372         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5373         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5374         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5375         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5376         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5377         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5378         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5379         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5380         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5381         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5382         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5383         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5384         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5385         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5386         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5387         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5388         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5389         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5390         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5391         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5392         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5393         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5394         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5395         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5396         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5397         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5398         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5399         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5400         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5401         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5402         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5403         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5404         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5405         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5406         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5407         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5408         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5409         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5410         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5411         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5412         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5413         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5414         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5415         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5416         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5417         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5418         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5419         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5420         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5421         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5422         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5423         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5424         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5425         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5426         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5427         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5428         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5429         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5430         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5431         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5432         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5433         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5434         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5435         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5436         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5437         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5438         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5439         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5440         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5441         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5442         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5443         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5444         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5445         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5446         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5447         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5448         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5449         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5450         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5451         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5452         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5453         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5454         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5455         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5456         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5457         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5458         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5459         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5460         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5461         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5462         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5463         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5464         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5465         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5466         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5467         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5468         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5469         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5470         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5471         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5472         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5473         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5474         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5475         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5476         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5477         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5478         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5479         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5480         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5481         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5482         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5483         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5484         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5485         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5486         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5487         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5488         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5489         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5490         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5491         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5492         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5493         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5494         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5495         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5496         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5497         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5498         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5499         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5500         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5501         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5502         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5503         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5504         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5505         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5506         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5507         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5508         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5509         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5510         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5511         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5512         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5513         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5514         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5515         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5516         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5517         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5518         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5519         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5520         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5521         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5522         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5523         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5524         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5525         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5526         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5527         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5528         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5529         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5530         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5531         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5532         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5533         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5534         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5535         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5536         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5537         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5538         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5539         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5540         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5541         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5542         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5543         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5544         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5545         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5546         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5547         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5548         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5549         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5550         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5551         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5552         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5553         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5554         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5555         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5556         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5557         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5558         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5559         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5560         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5561         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5562         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5563         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5564         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5565         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5566         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5567         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5568         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5569         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5570         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5571         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5572         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5573         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5574         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5575         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5576         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5577         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5578         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5579         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5580         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5581         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5582         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5583         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5584         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5585         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5586         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5587         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5588         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5589         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5590         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5591         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5592         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5593         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5594         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5595         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5596         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5597         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5598         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5599         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5600         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5601         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5602         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5603         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5604         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5605         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5606         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5607         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5608         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5609         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5610 };
5611
5612 static const u32 tg3TsoFwRodata[] = {
5613         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5614         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5615         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5616         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5617         0x00000000,
5618 };
5619
5620 static const u32 tg3TsoFwData[] = {
5621         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5622         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5623         0x00000000,
5624 };
5625
5626 /* 5705 needs a special version of the TSO firmware.  */
5627 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5628 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5629 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5630 #define TG3_TSO5_FW_START_ADDR          0x00010000
5631 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5632 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5633 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5634 #define TG3_TSO5_FW_RODATA_LEN          0x50
5635 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5636 #define TG3_TSO5_FW_DATA_LEN            0x20
5637 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5638 #define TG3_TSO5_FW_SBSS_LEN            0x28
5639 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5640 #define TG3_TSO5_FW_BSS_LEN             0x88
5641
5642 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5643         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5644         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde