[TG3]: Add 5787F device ID.
[linux-3.10.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40 #include <linux/dma-mapping.h>
41
42 #include <net/checksum.h>
43
44 #include <asm/system.h>
45 #include <asm/io.h>
46 #include <asm/byteorder.h>
47 #include <asm/uaccess.h>
48
49 #ifdef CONFIG_SPARC64
50 #include <asm/idprom.h>
51 #include <asm/oplib.h>
52 #include <asm/pbm.h>
53 #endif
54
55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56 #define TG3_VLAN_TAG_USED 1
57 #else
58 #define TG3_VLAN_TAG_USED 0
59 #endif
60
61 #ifdef NETIF_F_TSO
62 #define TG3_TSO_SUPPORT 1
63 #else
64 #define TG3_TSO_SUPPORT 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME         "tg3"
70 #define PFX DRV_MODULE_NAME     ": "
71 #define DRV_MODULE_VERSION      "3.69"
72 #define DRV_MODULE_RELDATE      "November 15, 2006"
73
74 #define TG3_DEF_MAC_MODE        0
75 #define TG3_DEF_RX_MODE         0
76 #define TG3_DEF_TX_MODE         0
77 #define TG3_DEF_MSG_ENABLE        \
78         (NETIF_MSG_DRV          | \
79          NETIF_MSG_PROBE        | \
80          NETIF_MSG_LINK         | \
81          NETIF_MSG_TIMER        | \
82          NETIF_MSG_IFDOWN       | \
83          NETIF_MSG_IFUP         | \
84          NETIF_MSG_RX_ERR       | \
85          NETIF_MSG_TX_ERR)
86
87 /* length of time before we decide the hardware is borked,
88  * and dev->tx_timeout() should be called to fix the problem
89  */
90 #define TG3_TX_TIMEOUT                  (5 * HZ)
91
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU                     60
94 #define TG3_MAX_MTU(tp) \
95         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
96
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98  * You can't change the ring sizes, but you can change where you place
99  * them in the NIC onboard memory.
100  */
101 #define TG3_RX_RING_SIZE                512
102 #define TG3_DEF_RX_RING_PENDING         200
103 #define TG3_RX_JUMBO_RING_SIZE          256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
105
106 /* Do not place this n-ring entries value into the tp struct itself,
107  * we really want to expose these constants to GCC so that modulo et
108  * al.  operations are done with shifts and masks instead of with
109  * hw multiply/modulo instructions.  Another solution would be to
110  * replace things like '% foo' with '& (foo - 1)'.
111  */
112 #define TG3_RX_RCB_RING_SIZE(tp)        \
113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
114
115 #define TG3_TX_RING_SIZE                512
116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
117
118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
119                                  TG3_RX_RING_SIZE)
120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121                                  TG3_RX_JUMBO_RING_SIZE)
122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123                                    TG3_RX_RCB_RING_SIZE(tp))
124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
125                                  TG3_TX_RING_SIZE)
126 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
128 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
129 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
130
131 /* minimum number of free TX descriptors required to wake up TX process */
132 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
133
134 /* number of ETHTOOL_GSTATS u64's */
135 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
136
137 #define TG3_NUM_TEST            6
138
139 static char version[] __devinitdata =
140         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
141
142 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
143 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
144 MODULE_LICENSE("GPL");
145 MODULE_VERSION(DRV_MODULE_VERSION);
146
147 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
148 module_param(tg3_debug, int, 0);
149 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
150
151 static struct pci_device_id tg3_pci_tbl[] = {
152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
205         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
206         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
207         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
208         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
209         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
210         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
211         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
212         {}
213 };
214
215 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
216
217 static const struct {
218         const char string[ETH_GSTRING_LEN];
219 } ethtool_stats_keys[TG3_NUM_STATS] = {
220         { "rx_octets" },
221         { "rx_fragments" },
222         { "rx_ucast_packets" },
223         { "rx_mcast_packets" },
224         { "rx_bcast_packets" },
225         { "rx_fcs_errors" },
226         { "rx_align_errors" },
227         { "rx_xon_pause_rcvd" },
228         { "rx_xoff_pause_rcvd" },
229         { "rx_mac_ctrl_rcvd" },
230         { "rx_xoff_entered" },
231         { "rx_frame_too_long_errors" },
232         { "rx_jabbers" },
233         { "rx_undersize_packets" },
234         { "rx_in_length_errors" },
235         { "rx_out_length_errors" },
236         { "rx_64_or_less_octet_packets" },
237         { "rx_65_to_127_octet_packets" },
238         { "rx_128_to_255_octet_packets" },
239         { "rx_256_to_511_octet_packets" },
240         { "rx_512_to_1023_octet_packets" },
241         { "rx_1024_to_1522_octet_packets" },
242         { "rx_1523_to_2047_octet_packets" },
243         { "rx_2048_to_4095_octet_packets" },
244         { "rx_4096_to_8191_octet_packets" },
245         { "rx_8192_to_9022_octet_packets" },
246
247         { "tx_octets" },
248         { "tx_collisions" },
249
250         { "tx_xon_sent" },
251         { "tx_xoff_sent" },
252         { "tx_flow_control" },
253         { "tx_mac_errors" },
254         { "tx_single_collisions" },
255         { "tx_mult_collisions" },
256         { "tx_deferred" },
257         { "tx_excessive_collisions" },
258         { "tx_late_collisions" },
259         { "tx_collide_2times" },
260         { "tx_collide_3times" },
261         { "tx_collide_4times" },
262         { "tx_collide_5times" },
263         { "tx_collide_6times" },
264         { "tx_collide_7times" },
265         { "tx_collide_8times" },
266         { "tx_collide_9times" },
267         { "tx_collide_10times" },
268         { "tx_collide_11times" },
269         { "tx_collide_12times" },
270         { "tx_collide_13times" },
271         { "tx_collide_14times" },
272         { "tx_collide_15times" },
273         { "tx_ucast_packets" },
274         { "tx_mcast_packets" },
275         { "tx_bcast_packets" },
276         { "tx_carrier_sense_errors" },
277         { "tx_discards" },
278         { "tx_errors" },
279
280         { "dma_writeq_full" },
281         { "dma_write_prioq_full" },
282         { "rxbds_empty" },
283         { "rx_discards" },
284         { "rx_errors" },
285         { "rx_threshold_hit" },
286
287         { "dma_readq_full" },
288         { "dma_read_prioq_full" },
289         { "tx_comp_queue_full" },
290
291         { "ring_set_send_prod_index" },
292         { "ring_status_update" },
293         { "nic_irqs" },
294         { "nic_avoided_irqs" },
295         { "nic_tx_threshold_hit" }
296 };
297
298 static const struct {
299         const char string[ETH_GSTRING_LEN];
300 } ethtool_test_keys[TG3_NUM_TEST] = {
301         { "nvram test     (online) " },
302         { "link test      (online) " },
303         { "register test  (offline)" },
304         { "memory test    (offline)" },
305         { "loopback test  (offline)" },
306         { "interrupt test (offline)" },
307 };
308
309 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
310 {
311         writel(val, tp->regs + off);
312 }
313
314 static u32 tg3_read32(struct tg3 *tp, u32 off)
315 {
316         return (readl(tp->regs + off));
317 }
318
319 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
320 {
321         unsigned long flags;
322
323         spin_lock_irqsave(&tp->indirect_lock, flags);
324         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
325         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
326         spin_unlock_irqrestore(&tp->indirect_lock, flags);
327 }
328
329 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
330 {
331         writel(val, tp->regs + off);
332         readl(tp->regs + off);
333 }
334
335 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
336 {
337         unsigned long flags;
338         u32 val;
339
340         spin_lock_irqsave(&tp->indirect_lock, flags);
341         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
342         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
343         spin_unlock_irqrestore(&tp->indirect_lock, flags);
344         return val;
345 }
346
347 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
348 {
349         unsigned long flags;
350
351         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
352                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
353                                        TG3_64BIT_REG_LOW, val);
354                 return;
355         }
356         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
357                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
358                                        TG3_64BIT_REG_LOW, val);
359                 return;
360         }
361
362         spin_lock_irqsave(&tp->indirect_lock, flags);
363         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
364         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
365         spin_unlock_irqrestore(&tp->indirect_lock, flags);
366
367         /* In indirect mode when disabling interrupts, we also need
368          * to clear the interrupt bit in the GRC local ctrl register.
369          */
370         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
371             (val == 0x1)) {
372                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
373                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
374         }
375 }
376
377 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
378 {
379         unsigned long flags;
380         u32 val;
381
382         spin_lock_irqsave(&tp->indirect_lock, flags);
383         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
384         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
385         spin_unlock_irqrestore(&tp->indirect_lock, flags);
386         return val;
387 }
388
389 /* usec_wait specifies the wait time in usec when writing to certain registers
390  * where it is unsafe to read back the register without some delay.
391  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
392  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
393  */
394 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
395 {
396         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
397             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
398                 /* Non-posted methods */
399                 tp->write32(tp, off, val);
400         else {
401                 /* Posted method */
402                 tg3_write32(tp, off, val);
403                 if (usec_wait)
404                         udelay(usec_wait);
405                 tp->read32(tp, off);
406         }
407         /* Wait again after the read for the posted method to guarantee that
408          * the wait time is met.
409          */
410         if (usec_wait)
411                 udelay(usec_wait);
412 }
413
414 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
415 {
416         tp->write32_mbox(tp, off, val);
417         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
418             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
419                 tp->read32_mbox(tp, off);
420 }
421
422 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
423 {
424         void __iomem *mbox = tp->regs + off;
425         writel(val, mbox);
426         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
427                 writel(val, mbox);
428         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
429                 readl(mbox);
430 }
431
432 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
433 {
434         return (readl(tp->regs + off + GRCMBOX_BASE));
435 }
436
437 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
438 {
439         writel(val, tp->regs + off + GRCMBOX_BASE);
440 }
441
442 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
443 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
444 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
445 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
446 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
447
448 #define tw32(reg,val)           tp->write32(tp, reg, val)
449 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
450 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
451 #define tr32(reg)               tp->read32(tp, reg)
452
453 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
454 {
455         unsigned long flags;
456
457         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
458             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
459                 return;
460
461         spin_lock_irqsave(&tp->indirect_lock, flags);
462         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
463                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
464                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
465
466                 /* Always leave this as zero. */
467                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
468         } else {
469                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
470                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
471
472                 /* Always leave this as zero. */
473                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
474         }
475         spin_unlock_irqrestore(&tp->indirect_lock, flags);
476 }
477
478 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
479 {
480         unsigned long flags;
481
482         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
483             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
484                 *val = 0;
485                 return;
486         }
487
488         spin_lock_irqsave(&tp->indirect_lock, flags);
489         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
490                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
491                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
492
493                 /* Always leave this as zero. */
494                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
495         } else {
496                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
497                 *val = tr32(TG3PCI_MEM_WIN_DATA);
498
499                 /* Always leave this as zero. */
500                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
501         }
502         spin_unlock_irqrestore(&tp->indirect_lock, flags);
503 }
504
505 static void tg3_disable_ints(struct tg3 *tp)
506 {
507         tw32(TG3PCI_MISC_HOST_CTRL,
508              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
509         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
510 }
511
512 static inline void tg3_cond_int(struct tg3 *tp)
513 {
514         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
515             (tp->hw_status->status & SD_STATUS_UPDATED))
516                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
517         else
518                 tw32(HOSTCC_MODE, tp->coalesce_mode |
519                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
520 }
521
522 static void tg3_enable_ints(struct tg3 *tp)
523 {
524         tp->irq_sync = 0;
525         wmb();
526
527         tw32(TG3PCI_MISC_HOST_CTRL,
528              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
529         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
530                        (tp->last_tag << 24));
531         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
532                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
533                                (tp->last_tag << 24));
534         tg3_cond_int(tp);
535 }
536
537 static inline unsigned int tg3_has_work(struct tg3 *tp)
538 {
539         struct tg3_hw_status *sblk = tp->hw_status;
540         unsigned int work_exists = 0;
541
542         /* check for phy events */
543         if (!(tp->tg3_flags &
544               (TG3_FLAG_USE_LINKCHG_REG |
545                TG3_FLAG_POLL_SERDES))) {
546                 if (sblk->status & SD_STATUS_LINK_CHG)
547                         work_exists = 1;
548         }
549         /* check for RX/TX work to do */
550         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
551             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
552                 work_exists = 1;
553
554         return work_exists;
555 }
556
557 /* tg3_restart_ints
558  *  similar to tg3_enable_ints, but it accurately determines whether there
559  *  is new work pending and can return without flushing the PIO write
560  *  which reenables interrupts
561  */
562 static void tg3_restart_ints(struct tg3 *tp)
563 {
564         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
565                      tp->last_tag << 24);
566         mmiowb();
567
568         /* When doing tagged status, this work check is unnecessary.
569          * The last_tag we write above tells the chip which piece of
570          * work we've completed.
571          */
572         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
573             tg3_has_work(tp))
574                 tw32(HOSTCC_MODE, tp->coalesce_mode |
575                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
576 }
577
578 static inline void tg3_netif_stop(struct tg3 *tp)
579 {
580         tp->dev->trans_start = jiffies; /* prevent tx timeout */
581         netif_poll_disable(tp->dev);
582         netif_tx_disable(tp->dev);
583 }
584
585 static inline void tg3_netif_start(struct tg3 *tp)
586 {
587         netif_wake_queue(tp->dev);
588         /* NOTE: unconditional netif_wake_queue is only appropriate
589          * so long as all callers are assured to have free tx slots
590          * (such as after tg3_init_hw)
591          */
592         netif_poll_enable(tp->dev);
593         tp->hw_status->status |= SD_STATUS_UPDATED;
594         tg3_enable_ints(tp);
595 }
596
597 static void tg3_switch_clocks(struct tg3 *tp)
598 {
599         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
600         u32 orig_clock_ctrl;
601
602         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
603                 return;
604
605         orig_clock_ctrl = clock_ctrl;
606         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
607                        CLOCK_CTRL_CLKRUN_OENABLE |
608                        0x1f);
609         tp->pci_clock_ctrl = clock_ctrl;
610
611         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
612                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
613                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
614                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
615                 }
616         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
617                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
618                             clock_ctrl |
619                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
620                             40);
621                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
622                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
623                             40);
624         }
625         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
626 }
627
628 #define PHY_BUSY_LOOPS  5000
629
630 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
631 {
632         u32 frame_val;
633         unsigned int loops;
634         int ret;
635
636         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
637                 tw32_f(MAC_MI_MODE,
638                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
639                 udelay(80);
640         }
641
642         *val = 0x0;
643
644         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
645                       MI_COM_PHY_ADDR_MASK);
646         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
647                       MI_COM_REG_ADDR_MASK);
648         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
649
650         tw32_f(MAC_MI_COM, frame_val);
651
652         loops = PHY_BUSY_LOOPS;
653         while (loops != 0) {
654                 udelay(10);
655                 frame_val = tr32(MAC_MI_COM);
656
657                 if ((frame_val & MI_COM_BUSY) == 0) {
658                         udelay(5);
659                         frame_val = tr32(MAC_MI_COM);
660                         break;
661                 }
662                 loops -= 1;
663         }
664
665         ret = -EBUSY;
666         if (loops != 0) {
667                 *val = frame_val & MI_COM_DATA_MASK;
668                 ret = 0;
669         }
670
671         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
672                 tw32_f(MAC_MI_MODE, tp->mi_mode);
673                 udelay(80);
674         }
675
676         return ret;
677 }
678
679 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
680 {
681         u32 frame_val;
682         unsigned int loops;
683         int ret;
684
685         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
686             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
687                 return 0;
688
689         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
690                 tw32_f(MAC_MI_MODE,
691                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
692                 udelay(80);
693         }
694
695         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
696                       MI_COM_PHY_ADDR_MASK);
697         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
698                       MI_COM_REG_ADDR_MASK);
699         frame_val |= (val & MI_COM_DATA_MASK);
700         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
701
702         tw32_f(MAC_MI_COM, frame_val);
703
704         loops = PHY_BUSY_LOOPS;
705         while (loops != 0) {
706                 udelay(10);
707                 frame_val = tr32(MAC_MI_COM);
708                 if ((frame_val & MI_COM_BUSY) == 0) {
709                         udelay(5);
710                         frame_val = tr32(MAC_MI_COM);
711                         break;
712                 }
713                 loops -= 1;
714         }
715
716         ret = -EBUSY;
717         if (loops != 0)
718                 ret = 0;
719
720         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
721                 tw32_f(MAC_MI_MODE, tp->mi_mode);
722                 udelay(80);
723         }
724
725         return ret;
726 }
727
728 static void tg3_phy_set_wirespeed(struct tg3 *tp)
729 {
730         u32 val;
731
732         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
733                 return;
734
735         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
736             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
737                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
738                              (val | (1 << 15) | (1 << 4)));
739 }
740
741 static int tg3_bmcr_reset(struct tg3 *tp)
742 {
743         u32 phy_control;
744         int limit, err;
745
746         /* OK, reset it, and poll the BMCR_RESET bit until it
747          * clears or we time out.
748          */
749         phy_control = BMCR_RESET;
750         err = tg3_writephy(tp, MII_BMCR, phy_control);
751         if (err != 0)
752                 return -EBUSY;
753
754         limit = 5000;
755         while (limit--) {
756                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
757                 if (err != 0)
758                         return -EBUSY;
759
760                 if ((phy_control & BMCR_RESET) == 0) {
761                         udelay(40);
762                         break;
763                 }
764                 udelay(10);
765         }
766         if (limit <= 0)
767                 return -EBUSY;
768
769         return 0;
770 }
771
772 static int tg3_wait_macro_done(struct tg3 *tp)
773 {
774         int limit = 100;
775
776         while (limit--) {
777                 u32 tmp32;
778
779                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
780                         if ((tmp32 & 0x1000) == 0)
781                                 break;
782                 }
783         }
784         if (limit <= 0)
785                 return -EBUSY;
786
787         return 0;
788 }
789
790 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
791 {
792         static const u32 test_pat[4][6] = {
793         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
794         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
795         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
796         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
797         };
798         int chan;
799
800         for (chan = 0; chan < 4; chan++) {
801                 int i;
802
803                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
804                              (chan * 0x2000) | 0x0200);
805                 tg3_writephy(tp, 0x16, 0x0002);
806
807                 for (i = 0; i < 6; i++)
808                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
809                                      test_pat[chan][i]);
810
811                 tg3_writephy(tp, 0x16, 0x0202);
812                 if (tg3_wait_macro_done(tp)) {
813                         *resetp = 1;
814                         return -EBUSY;
815                 }
816
817                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
818                              (chan * 0x2000) | 0x0200);
819                 tg3_writephy(tp, 0x16, 0x0082);
820                 if (tg3_wait_macro_done(tp)) {
821                         *resetp = 1;
822                         return -EBUSY;
823                 }
824
825                 tg3_writephy(tp, 0x16, 0x0802);
826                 if (tg3_wait_macro_done(tp)) {
827                         *resetp = 1;
828                         return -EBUSY;
829                 }
830
831                 for (i = 0; i < 6; i += 2) {
832                         u32 low, high;
833
834                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
835                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
836                             tg3_wait_macro_done(tp)) {
837                                 *resetp = 1;
838                                 return -EBUSY;
839                         }
840                         low &= 0x7fff;
841                         high &= 0x000f;
842                         if (low != test_pat[chan][i] ||
843                             high != test_pat[chan][i+1]) {
844                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
845                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
846                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
847
848                                 return -EBUSY;
849                         }
850                 }
851         }
852
853         return 0;
854 }
855
856 static int tg3_phy_reset_chanpat(struct tg3 *tp)
857 {
858         int chan;
859
860         for (chan = 0; chan < 4; chan++) {
861                 int i;
862
863                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
864                              (chan * 0x2000) | 0x0200);
865                 tg3_writephy(tp, 0x16, 0x0002);
866                 for (i = 0; i < 6; i++)
867                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
868                 tg3_writephy(tp, 0x16, 0x0202);
869                 if (tg3_wait_macro_done(tp))
870                         return -EBUSY;
871         }
872
873         return 0;
874 }
875
876 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
877 {
878         u32 reg32, phy9_orig;
879         int retries, do_phy_reset, err;
880
881         retries = 10;
882         do_phy_reset = 1;
883         do {
884                 if (do_phy_reset) {
885                         err = tg3_bmcr_reset(tp);
886                         if (err)
887                                 return err;
888                         do_phy_reset = 0;
889                 }
890
891                 /* Disable transmitter and interrupt.  */
892                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
893                         continue;
894
895                 reg32 |= 0x3000;
896                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
897
898                 /* Set full-duplex, 1000 mbps.  */
899                 tg3_writephy(tp, MII_BMCR,
900                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
901
902                 /* Set to master mode.  */
903                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
904                         continue;
905
906                 tg3_writephy(tp, MII_TG3_CTRL,
907                              (MII_TG3_CTRL_AS_MASTER |
908                               MII_TG3_CTRL_ENABLE_AS_MASTER));
909
910                 /* Enable SM_DSP_CLOCK and 6dB.  */
911                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
912
913                 /* Block the PHY control access.  */
914                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
915                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
916
917                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
918                 if (!err)
919                         break;
920         } while (--retries);
921
922         err = tg3_phy_reset_chanpat(tp);
923         if (err)
924                 return err;
925
926         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
927         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
928
929         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
930         tg3_writephy(tp, 0x16, 0x0000);
931
932         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
933             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
934                 /* Set Extended packet length bit for jumbo frames */
935                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
936         }
937         else {
938                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
939         }
940
941         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
942
943         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
944                 reg32 &= ~0x3000;
945                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
946         } else if (!err)
947                 err = -EBUSY;
948
949         return err;
950 }
951
952 static void tg3_link_report(struct tg3 *);
953
954 /* This will reset the tigon3 PHY if there is no valid
955  * link unless the FORCE argument is non-zero.
956  */
957 static int tg3_phy_reset(struct tg3 *tp)
958 {
959         u32 phy_status;
960         int err;
961
962         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
963         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
964         if (err != 0)
965                 return -EBUSY;
966
967         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
968                 netif_carrier_off(tp->dev);
969                 tg3_link_report(tp);
970         }
971
972         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
973             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
974             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
975                 err = tg3_phy_reset_5703_4_5(tp);
976                 if (err)
977                         return err;
978                 goto out;
979         }
980
981         err = tg3_bmcr_reset(tp);
982         if (err)
983                 return err;
984
985 out:
986         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
987                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
988                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
989                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
990                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
991                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
992                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
993         }
994         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
995                 tg3_writephy(tp, 0x1c, 0x8d68);
996                 tg3_writephy(tp, 0x1c, 0x8d68);
997         }
998         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
999                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1000                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1001                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1002                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1003                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1004                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1005                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1006                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1007         }
1008         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1009                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1010                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1011                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1012                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1013         }
1014         /* Set Extended packet length bit (bit 14) on all chips that */
1015         /* support jumbo frames */
1016         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1017                 /* Cannot do read-modify-write on 5401 */
1018                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1019         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1020                 u32 phy_reg;
1021
1022                 /* Set bit 14 with read-modify-write to preserve other bits */
1023                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1024                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1025                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1026         }
1027
1028         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1029          * jumbo frames transmission.
1030          */
1031         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1032                 u32 phy_reg;
1033
1034                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1035                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1036                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1037         }
1038
1039         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1040                 u32 phy_reg;
1041
1042                 /* adjust output voltage */
1043                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1044
1045                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1046                         u32 phy_reg2;
1047
1048                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1049                                      phy_reg | MII_TG3_EPHY_SHADOW_EN);
1050                         /* Enable auto-MDIX */
1051                         if (!tg3_readphy(tp, 0x10, &phy_reg2))
1052                                 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1053                         tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1054                 }
1055         }
1056
1057         tg3_phy_set_wirespeed(tp);
1058         return 0;
1059 }
1060
1061 static void tg3_frob_aux_power(struct tg3 *tp)
1062 {
1063         struct tg3 *tp_peer = tp;
1064
1065         if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1066                 return;
1067
1068         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1069             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1070                 struct net_device *dev_peer;
1071
1072                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1073                 /* remove_one() may have been run on the peer. */
1074                 if (!dev_peer)
1075                         tp_peer = tp;
1076                 else
1077                         tp_peer = netdev_priv(dev_peer);
1078         }
1079
1080         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1081             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1082             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1083             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1084                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1085                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1086                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1087                                     (GRC_LCLCTRL_GPIO_OE0 |
1088                                      GRC_LCLCTRL_GPIO_OE1 |
1089                                      GRC_LCLCTRL_GPIO_OE2 |
1090                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1091                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1092                                     100);
1093                 } else {
1094                         u32 no_gpio2;
1095                         u32 grc_local_ctrl = 0;
1096
1097                         if (tp_peer != tp &&
1098                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1099                                 return;
1100
1101                         /* Workaround to prevent overdrawing Amps. */
1102                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1103                             ASIC_REV_5714) {
1104                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1105                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1106                                             grc_local_ctrl, 100);
1107                         }
1108
1109                         /* On 5753 and variants, GPIO2 cannot be used. */
1110                         no_gpio2 = tp->nic_sram_data_cfg &
1111                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1112
1113                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1114                                          GRC_LCLCTRL_GPIO_OE1 |
1115                                          GRC_LCLCTRL_GPIO_OE2 |
1116                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1117                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1118                         if (no_gpio2) {
1119                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1120                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1121                         }
1122                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1123                                                     grc_local_ctrl, 100);
1124
1125                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1126
1127                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1128                                                     grc_local_ctrl, 100);
1129
1130                         if (!no_gpio2) {
1131                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1132                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1133                                             grc_local_ctrl, 100);
1134                         }
1135                 }
1136         } else {
1137                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1138                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1139                         if (tp_peer != tp &&
1140                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1141                                 return;
1142
1143                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1144                                     (GRC_LCLCTRL_GPIO_OE1 |
1145                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1146
1147                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1148                                     GRC_LCLCTRL_GPIO_OE1, 100);
1149
1150                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1151                                     (GRC_LCLCTRL_GPIO_OE1 |
1152                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1153                 }
1154         }
1155 }
1156
1157 static int tg3_setup_phy(struct tg3 *, int);
1158
1159 #define RESET_KIND_SHUTDOWN     0
1160 #define RESET_KIND_INIT         1
1161 #define RESET_KIND_SUSPEND      2
1162
1163 static void tg3_write_sig_post_reset(struct tg3 *, int);
1164 static int tg3_halt_cpu(struct tg3 *, u32);
1165 static int tg3_nvram_lock(struct tg3 *);
1166 static void tg3_nvram_unlock(struct tg3 *);
1167
1168 static void tg3_power_down_phy(struct tg3 *tp)
1169 {
1170         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
1171                 return;
1172
1173         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
1174                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1175                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1176                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1177         }
1178
1179         /* The PHY should not be powered down on some chips because
1180          * of bugs.
1181          */
1182         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1183             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1184             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1185              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1186                 return;
1187         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1188 }
1189
1190 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1191 {
1192         u32 misc_host_ctrl;
1193         u16 power_control, power_caps;
1194         int pm = tp->pm_cap;
1195
1196         /* Make sure register accesses (indirect or otherwise)
1197          * will function correctly.
1198          */
1199         pci_write_config_dword(tp->pdev,
1200                                TG3PCI_MISC_HOST_CTRL,
1201                                tp->misc_host_ctrl);
1202
1203         pci_read_config_word(tp->pdev,
1204                              pm + PCI_PM_CTRL,
1205                              &power_control);
1206         power_control |= PCI_PM_CTRL_PME_STATUS;
1207         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1208         switch (state) {
1209         case PCI_D0:
1210                 power_control |= 0;
1211                 pci_write_config_word(tp->pdev,
1212                                       pm + PCI_PM_CTRL,
1213                                       power_control);
1214                 udelay(100);    /* Delay after power state change */
1215
1216                 /* Switch out of Vaux if it is not a LOM */
1217                 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
1218                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1219
1220                 return 0;
1221
1222         case PCI_D1:
1223                 power_control |= 1;
1224                 break;
1225
1226         case PCI_D2:
1227                 power_control |= 2;
1228                 break;
1229
1230         case PCI_D3hot:
1231                 power_control |= 3;
1232                 break;
1233
1234         default:
1235                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1236                        "requested.\n",
1237                        tp->dev->name, state);
1238                 return -EINVAL;
1239         };
1240
1241         power_control |= PCI_PM_CTRL_PME_ENABLE;
1242
1243         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1244         tw32(TG3PCI_MISC_HOST_CTRL,
1245              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1246
1247         if (tp->link_config.phy_is_low_power == 0) {
1248                 tp->link_config.phy_is_low_power = 1;
1249                 tp->link_config.orig_speed = tp->link_config.speed;
1250                 tp->link_config.orig_duplex = tp->link_config.duplex;
1251                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1252         }
1253
1254         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1255                 tp->link_config.speed = SPEED_10;
1256                 tp->link_config.duplex = DUPLEX_HALF;
1257                 tp->link_config.autoneg = AUTONEG_ENABLE;
1258                 tg3_setup_phy(tp, 0);
1259         }
1260
1261         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1262                 u32 val;
1263
1264                 val = tr32(GRC_VCPU_EXT_CTRL);
1265                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1266         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1267                 int i;
1268                 u32 val;
1269
1270                 for (i = 0; i < 200; i++) {
1271                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1272                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1273                                 break;
1274                         msleep(1);
1275                 }
1276         }
1277         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1278                                              WOL_DRV_STATE_SHUTDOWN |
1279                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1280
1281         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1282
1283         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1284                 u32 mac_mode;
1285
1286                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1287                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1288                         udelay(40);
1289
1290                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1291                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1292                         else
1293                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1294
1295                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1296                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1297                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1298                 } else {
1299                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1300                 }
1301
1302                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1303                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1304
1305                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1306                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1307                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1308
1309                 tw32_f(MAC_MODE, mac_mode);
1310                 udelay(100);
1311
1312                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1313                 udelay(10);
1314         }
1315
1316         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1317             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1318              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1319                 u32 base_val;
1320
1321                 base_val = tp->pci_clock_ctrl;
1322                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1323                              CLOCK_CTRL_TXCLK_DISABLE);
1324
1325                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1326                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1327         } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1328                 /* do nothing */
1329         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1330                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1331                 u32 newbits1, newbits2;
1332
1333                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1334                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1335                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1336                                     CLOCK_CTRL_TXCLK_DISABLE |
1337                                     CLOCK_CTRL_ALTCLK);
1338                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1339                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1340                         newbits1 = CLOCK_CTRL_625_CORE;
1341                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1342                 } else {
1343                         newbits1 = CLOCK_CTRL_ALTCLK;
1344                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1345                 }
1346
1347                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1348                             40);
1349
1350                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1351                             40);
1352
1353                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1354                         u32 newbits3;
1355
1356                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1357                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1358                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1359                                             CLOCK_CTRL_TXCLK_DISABLE |
1360                                             CLOCK_CTRL_44MHZ_CORE);
1361                         } else {
1362                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1363                         }
1364
1365                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1366                                     tp->pci_clock_ctrl | newbits3, 40);
1367                 }
1368         }
1369
1370         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1371             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1372                 tg3_power_down_phy(tp);
1373
1374         tg3_frob_aux_power(tp);
1375
1376         /* Workaround for unstable PLL clock */
1377         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1378             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1379                 u32 val = tr32(0x7d00);
1380
1381                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1382                 tw32(0x7d00, val);
1383                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1384                         int err;
1385
1386                         err = tg3_nvram_lock(tp);
1387                         tg3_halt_cpu(tp, RX_CPU_BASE);
1388                         if (!err)
1389                                 tg3_nvram_unlock(tp);
1390                 }
1391         }
1392
1393         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1394
1395         /* Finally, set the new power state. */
1396         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1397         udelay(100);    /* Delay after power state change */
1398
1399         return 0;
1400 }
1401
1402 static void tg3_link_report(struct tg3 *tp)
1403 {
1404         if (!netif_carrier_ok(tp->dev)) {
1405                 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1406         } else {
1407                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1408                        tp->dev->name,
1409                        (tp->link_config.active_speed == SPEED_1000 ?
1410                         1000 :
1411                         (tp->link_config.active_speed == SPEED_100 ?
1412                          100 : 10)),
1413                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1414                         "full" : "half"));
1415
1416                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1417                        "%s for RX.\n",
1418                        tp->dev->name,
1419                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1420                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1421         }
1422 }
1423
1424 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1425 {
1426         u32 new_tg3_flags = 0;
1427         u32 old_rx_mode = tp->rx_mode;
1428         u32 old_tx_mode = tp->tx_mode;
1429
1430         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1431
1432                 /* Convert 1000BaseX flow control bits to 1000BaseT
1433                  * bits before resolving flow control.
1434                  */
1435                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1436                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1437                                        ADVERTISE_PAUSE_ASYM);
1438                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1439
1440                         if (local_adv & ADVERTISE_1000XPAUSE)
1441                                 local_adv |= ADVERTISE_PAUSE_CAP;
1442                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1443                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1444                         if (remote_adv & LPA_1000XPAUSE)
1445                                 remote_adv |= LPA_PAUSE_CAP;
1446                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1447                                 remote_adv |= LPA_PAUSE_ASYM;
1448                 }
1449
1450                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1451                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1452                                 if (remote_adv & LPA_PAUSE_CAP)
1453                                         new_tg3_flags |=
1454                                                 (TG3_FLAG_RX_PAUSE |
1455                                                 TG3_FLAG_TX_PAUSE);
1456                                 else if (remote_adv & LPA_PAUSE_ASYM)
1457                                         new_tg3_flags |=
1458                                                 (TG3_FLAG_RX_PAUSE);
1459                         } else {
1460                                 if (remote_adv & LPA_PAUSE_CAP)
1461                                         new_tg3_flags |=
1462                                                 (TG3_FLAG_RX_PAUSE |
1463                                                 TG3_FLAG_TX_PAUSE);
1464                         }
1465                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1466                         if ((remote_adv & LPA_PAUSE_CAP) &&
1467                         (remote_adv & LPA_PAUSE_ASYM))
1468                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1469                 }
1470
1471                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1472                 tp->tg3_flags |= new_tg3_flags;
1473         } else {
1474                 new_tg3_flags = tp->tg3_flags;
1475         }
1476
1477         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1478                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1479         else
1480                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1481
1482         if (old_rx_mode != tp->rx_mode) {
1483                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1484         }
1485
1486         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1487                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1488         else
1489                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1490
1491         if (old_tx_mode != tp->tx_mode) {
1492                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1493         }
1494 }
1495
1496 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1497 {
1498         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1499         case MII_TG3_AUX_STAT_10HALF:
1500                 *speed = SPEED_10;
1501                 *duplex = DUPLEX_HALF;
1502                 break;
1503
1504         case MII_TG3_AUX_STAT_10FULL:
1505                 *speed = SPEED_10;
1506                 *duplex = DUPLEX_FULL;
1507                 break;
1508
1509         case MII_TG3_AUX_STAT_100HALF:
1510                 *speed = SPEED_100;
1511                 *duplex = DUPLEX_HALF;
1512                 break;
1513
1514         case MII_TG3_AUX_STAT_100FULL:
1515                 *speed = SPEED_100;
1516                 *duplex = DUPLEX_FULL;
1517                 break;
1518
1519         case MII_TG3_AUX_STAT_1000HALF:
1520                 *speed = SPEED_1000;
1521                 *duplex = DUPLEX_HALF;
1522                 break;
1523
1524         case MII_TG3_AUX_STAT_1000FULL:
1525                 *speed = SPEED_1000;
1526                 *duplex = DUPLEX_FULL;
1527                 break;
1528
1529         default:
1530                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1531                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1532                                  SPEED_10;
1533                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1534                                   DUPLEX_HALF;
1535                         break;
1536                 }
1537                 *speed = SPEED_INVALID;
1538                 *duplex = DUPLEX_INVALID;
1539                 break;
1540         };
1541 }
1542
1543 static void tg3_phy_copper_begin(struct tg3 *tp)
1544 {
1545         u32 new_adv;
1546         int i;
1547
1548         if (tp->link_config.phy_is_low_power) {
1549                 /* Entering low power mode.  Disable gigabit and
1550                  * 100baseT advertisements.
1551                  */
1552                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1553
1554                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1555                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1556                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1557                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1558
1559                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1560         } else if (tp->link_config.speed == SPEED_INVALID) {
1561                 tp->link_config.advertising =
1562                         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1563                          ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1564                          ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1565                          ADVERTISED_Autoneg | ADVERTISED_MII);
1566
1567                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1568                         tp->link_config.advertising &=
1569                                 ~(ADVERTISED_1000baseT_Half |
1570                                   ADVERTISED_1000baseT_Full);
1571
1572                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1573                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1574                         new_adv |= ADVERTISE_10HALF;
1575                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1576                         new_adv |= ADVERTISE_10FULL;
1577                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1578                         new_adv |= ADVERTISE_100HALF;
1579                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1580                         new_adv |= ADVERTISE_100FULL;
1581                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1582
1583                 if (tp->link_config.advertising &
1584                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1585                         new_adv = 0;
1586                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1587                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1588                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1589                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1590                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1591                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1592                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1593                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1594                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1595                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1596                 } else {
1597                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1598                 }
1599         } else {
1600                 /* Asking for a specific link mode. */
1601                 if (tp->link_config.speed == SPEED_1000) {
1602                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1603                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1604
1605                         if (tp->link_config.duplex == DUPLEX_FULL)
1606                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1607                         else
1608                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1609                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1610                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1611                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1612                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1613                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1614                 } else {
1615                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1616
1617                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1618                         if (tp->link_config.speed == SPEED_100) {
1619                                 if (tp->link_config.duplex == DUPLEX_FULL)
1620                                         new_adv |= ADVERTISE_100FULL;
1621                                 else
1622                                         new_adv |= ADVERTISE_100HALF;
1623                         } else {
1624                                 if (tp->link_config.duplex == DUPLEX_FULL)
1625                                         new_adv |= ADVERTISE_10FULL;
1626                                 else
1627                                         new_adv |= ADVERTISE_10HALF;
1628                         }
1629                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1630                 }
1631         }
1632
1633         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1634             tp->link_config.speed != SPEED_INVALID) {
1635                 u32 bmcr, orig_bmcr;
1636
1637                 tp->link_config.active_speed = tp->link_config.speed;
1638                 tp->link_config.active_duplex = tp->link_config.duplex;
1639
1640                 bmcr = 0;
1641                 switch (tp->link_config.speed) {
1642                 default:
1643                 case SPEED_10:
1644                         break;
1645
1646                 case SPEED_100:
1647                         bmcr |= BMCR_SPEED100;
1648                         break;
1649
1650                 case SPEED_1000:
1651                         bmcr |= TG3_BMCR_SPEED1000;
1652                         break;
1653                 };
1654
1655                 if (tp->link_config.duplex == DUPLEX_FULL)
1656                         bmcr |= BMCR_FULLDPLX;
1657
1658                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1659                     (bmcr != orig_bmcr)) {
1660                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1661                         for (i = 0; i < 1500; i++) {
1662                                 u32 tmp;
1663
1664                                 udelay(10);
1665                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1666                                     tg3_readphy(tp, MII_BMSR, &tmp))
1667                                         continue;
1668                                 if (!(tmp & BMSR_LSTATUS)) {
1669                                         udelay(40);
1670                                         break;
1671                                 }
1672                         }
1673                         tg3_writephy(tp, MII_BMCR, bmcr);
1674                         udelay(40);
1675                 }
1676         } else {
1677                 tg3_writephy(tp, MII_BMCR,
1678                              BMCR_ANENABLE | BMCR_ANRESTART);
1679         }
1680 }
1681
1682 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1683 {
1684         int err;
1685
1686         /* Turn off tap power management. */
1687         /* Set Extended packet length bit */
1688         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1689
1690         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1691         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1692
1693         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1694         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1695
1696         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1697         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1698
1699         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1700         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1701
1702         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1703         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1704
1705         udelay(40);
1706
1707         return err;
1708 }
1709
1710 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1711 {
1712         u32 adv_reg, all_mask;
1713
1714         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1715                 return 0;
1716
1717         all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1718                     ADVERTISE_100HALF | ADVERTISE_100FULL);
1719         if ((adv_reg & all_mask) != all_mask)
1720                 return 0;
1721         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1722                 u32 tg3_ctrl;
1723
1724                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1725                         return 0;
1726
1727                 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1728                             MII_TG3_CTRL_ADV_1000_FULL);
1729                 if ((tg3_ctrl & all_mask) != all_mask)
1730                         return 0;
1731         }
1732         return 1;
1733 }
1734
1735 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1736 {
1737         int current_link_up;
1738         u32 bmsr, dummy;
1739         u16 current_speed;
1740         u8 current_duplex;
1741         int i, err;
1742
1743         tw32(MAC_EVENT, 0);
1744
1745         tw32_f(MAC_STATUS,
1746              (MAC_STATUS_SYNC_CHANGED |
1747               MAC_STATUS_CFG_CHANGED |
1748               MAC_STATUS_MI_COMPLETION |
1749               MAC_STATUS_LNKSTATE_CHANGED));
1750         udelay(40);
1751
1752         tp->mi_mode = MAC_MI_MODE_BASE;
1753         tw32_f(MAC_MI_MODE, tp->mi_mode);
1754         udelay(80);
1755
1756         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1757
1758         /* Some third-party PHYs need to be reset on link going
1759          * down.
1760          */
1761         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1762              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1763              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1764             netif_carrier_ok(tp->dev)) {
1765                 tg3_readphy(tp, MII_BMSR, &bmsr);
1766                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1767                     !(bmsr & BMSR_LSTATUS))
1768                         force_reset = 1;
1769         }
1770         if (force_reset)
1771                 tg3_phy_reset(tp);
1772
1773         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1774                 tg3_readphy(tp, MII_BMSR, &bmsr);
1775                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1776                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1777                         bmsr = 0;
1778
1779                 if (!(bmsr & BMSR_LSTATUS)) {
1780                         err = tg3_init_5401phy_dsp(tp);
1781                         if (err)
1782                                 return err;
1783
1784                         tg3_readphy(tp, MII_BMSR, &bmsr);
1785                         for (i = 0; i < 1000; i++) {
1786                                 udelay(10);
1787                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1788                                     (bmsr & BMSR_LSTATUS)) {
1789                                         udelay(40);
1790                                         break;
1791                                 }
1792                         }
1793
1794                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1795                             !(bmsr & BMSR_LSTATUS) &&
1796                             tp->link_config.active_speed == SPEED_1000) {
1797                                 err = tg3_phy_reset(tp);
1798                                 if (!err)
1799                                         err = tg3_init_5401phy_dsp(tp);
1800                                 if (err)
1801                                         return err;
1802                         }
1803                 }
1804         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1805                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1806                 /* 5701 {A0,B0} CRC bug workaround */
1807                 tg3_writephy(tp, 0x15, 0x0a75);
1808                 tg3_writephy(tp, 0x1c, 0x8c68);
1809                 tg3_writephy(tp, 0x1c, 0x8d68);
1810                 tg3_writephy(tp, 0x1c, 0x8c68);
1811         }
1812
1813         /* Clear pending interrupts... */
1814         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1815         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1816
1817         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1818                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1819         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1820                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1821
1822         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1823             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1824                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1825                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1826                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1827                 else
1828                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1829         }
1830
1831         current_link_up = 0;
1832         current_speed = SPEED_INVALID;
1833         current_duplex = DUPLEX_INVALID;
1834
1835         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1836                 u32 val;
1837
1838                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1839                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1840                 if (!(val & (1 << 10))) {
1841                         val |= (1 << 10);
1842                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1843                         goto relink;
1844                 }
1845         }
1846
1847         bmsr = 0;
1848         for (i = 0; i < 100; i++) {
1849                 tg3_readphy(tp, MII_BMSR, &bmsr);
1850                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1851                     (bmsr & BMSR_LSTATUS))
1852                         break;
1853                 udelay(40);
1854         }
1855
1856         if (bmsr & BMSR_LSTATUS) {
1857                 u32 aux_stat, bmcr;
1858
1859                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1860                 for (i = 0; i < 2000; i++) {
1861                         udelay(10);
1862                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1863                             aux_stat)
1864                                 break;
1865                 }
1866
1867                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1868                                              &current_speed,
1869                                              &current_duplex);
1870
1871                 bmcr = 0;
1872                 for (i = 0; i < 200; i++) {
1873                         tg3_readphy(tp, MII_BMCR, &bmcr);
1874                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1875                                 continue;
1876                         if (bmcr && bmcr != 0x7fff)
1877                                 break;
1878                         udelay(10);
1879                 }
1880
1881                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1882                         if (bmcr & BMCR_ANENABLE) {
1883                                 current_link_up = 1;
1884
1885                                 /* Force autoneg restart if we are exiting
1886                                  * low power mode.
1887                                  */
1888                                 if (!tg3_copper_is_advertising_all(tp))
1889                                         current_link_up = 0;
1890                         } else {
1891                                 current_link_up = 0;
1892                         }
1893                 } else {
1894                         if (!(bmcr & BMCR_ANENABLE) &&
1895                             tp->link_config.speed == current_speed &&
1896                             tp->link_config.duplex == current_duplex) {
1897                                 current_link_up = 1;
1898                         } else {
1899                                 current_link_up = 0;
1900                         }
1901                 }
1902
1903                 tp->link_config.active_speed = current_speed;
1904                 tp->link_config.active_duplex = current_duplex;
1905         }
1906
1907         if (current_link_up == 1 &&
1908             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1909             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1910                 u32 local_adv, remote_adv;
1911
1912                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1913                         local_adv = 0;
1914                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1915
1916                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1917                         remote_adv = 0;
1918
1919                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1920
1921                 /* If we are not advertising full pause capability,
1922                  * something is wrong.  Bring the link down and reconfigure.
1923                  */
1924                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1925                         current_link_up = 0;
1926                 } else {
1927                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1928                 }
1929         }
1930 relink:
1931         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1932                 u32 tmp;
1933
1934                 tg3_phy_copper_begin(tp);
1935
1936                 tg3_readphy(tp, MII_BMSR, &tmp);
1937                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1938                     (tmp & BMSR_LSTATUS))
1939                         current_link_up = 1;
1940         }
1941
1942         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1943         if (current_link_up == 1) {
1944                 if (tp->link_config.active_speed == SPEED_100 ||
1945                     tp->link_config.active_speed == SPEED_10)
1946                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1947                 else
1948                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1949         } else
1950                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1951
1952         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1953         if (tp->link_config.active_duplex == DUPLEX_HALF)
1954                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1955
1956         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1957         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1958                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1959                     (current_link_up == 1 &&
1960                      tp->link_config.active_speed == SPEED_10))
1961                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1962         } else {
1963                 if (current_link_up == 1)
1964                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1965         }
1966
1967         /* ??? Without this setting Netgear GA302T PHY does not
1968          * ??? send/receive packets...
1969          */
1970         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1971             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1972                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1973                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1974                 udelay(80);
1975         }
1976
1977         tw32_f(MAC_MODE, tp->mac_mode);
1978         udelay(40);
1979
1980         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1981                 /* Polled via timer. */
1982                 tw32_f(MAC_EVENT, 0);
1983         } else {
1984                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1985         }
1986         udelay(40);
1987
1988         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1989             current_link_up == 1 &&
1990             tp->link_config.active_speed == SPEED_1000 &&
1991             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1992              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1993                 udelay(120);
1994                 tw32_f(MAC_STATUS,
1995                      (MAC_STATUS_SYNC_CHANGED |
1996                       MAC_STATUS_CFG_CHANGED));
1997                 udelay(40);
1998                 tg3_write_mem(tp,
1999                               NIC_SRAM_FIRMWARE_MBOX,
2000                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2001         }
2002
2003         if (current_link_up != netif_carrier_ok(tp->dev)) {
2004                 if (current_link_up)
2005                         netif_carrier_on(tp->dev);
2006                 else
2007                         netif_carrier_off(tp->dev);
2008                 tg3_link_report(tp);
2009         }
2010
2011         return 0;
2012 }
2013
2014 struct tg3_fiber_aneginfo {
2015         int state;
2016 #define ANEG_STATE_UNKNOWN              0
2017 #define ANEG_STATE_AN_ENABLE            1
2018 #define ANEG_STATE_RESTART_INIT         2
2019 #define ANEG_STATE_RESTART              3
2020 #define ANEG_STATE_DISABLE_LINK_OK      4
2021 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2022 #define ANEG_STATE_ABILITY_DETECT       6
2023 #define ANEG_STATE_ACK_DETECT_INIT      7
2024 #define ANEG_STATE_ACK_DETECT           8
2025 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2026 #define ANEG_STATE_COMPLETE_ACK         10
2027 #define ANEG_STATE_IDLE_DETECT_INIT     11
2028 #define ANEG_STATE_IDLE_DETECT          12
2029 #define ANEG_STATE_LINK_OK              13
2030 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2031 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2032
2033         u32 flags;
2034 #define MR_AN_ENABLE            0x00000001
2035 #define MR_RESTART_AN           0x00000002
2036 #define MR_AN_COMPLETE          0x00000004
2037 #define MR_PAGE_RX              0x00000008
2038 #define MR_NP_LOADED            0x00000010
2039 #define MR_TOGGLE_TX            0x00000020
2040 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2041 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2042 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2043 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2044 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2045 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2046 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2047 #define MR_TOGGLE_RX            0x00002000
2048 #define MR_NP_RX                0x00004000
2049
2050 #define MR_LINK_OK              0x80000000
2051
2052         unsigned long link_time, cur_time;
2053
2054         u32 ability_match_cfg;
2055         int ability_match_count;
2056
2057         char ability_match, idle_match, ack_match;
2058
2059         u32 txconfig, rxconfig;
2060 #define ANEG_CFG_NP             0x00000080
2061 #define ANEG_CFG_ACK            0x00000040
2062 #define ANEG_CFG_RF2            0x00000020
2063 #define ANEG_CFG_RF1            0x00000010
2064 #define ANEG_CFG_PS2            0x00000001
2065 #define ANEG_CFG_PS1            0x00008000
2066 #define ANEG_CFG_HD             0x00004000
2067 #define ANEG_CFG_FD             0x00002000
2068 #define ANEG_CFG_INVAL          0x00001f06
2069
2070 };
2071 #define ANEG_OK         0
2072 #define ANEG_DONE       1
2073 #define ANEG_TIMER_ENAB 2
2074 #define ANEG_FAILED     -1
2075
2076 #define ANEG_STATE_SETTLE_TIME  10000
2077
2078 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2079                                    struct tg3_fiber_aneginfo *ap)
2080 {
2081         unsigned long delta;
2082         u32 rx_cfg_reg;
2083         int ret;
2084
2085         if (ap->state == ANEG_STATE_UNKNOWN) {
2086                 ap->rxconfig = 0;
2087                 ap->link_time = 0;
2088                 ap->cur_time = 0;
2089                 ap->ability_match_cfg = 0;
2090                 ap->ability_match_count = 0;
2091                 ap->ability_match = 0;
2092                 ap->idle_match = 0;
2093                 ap->ack_match = 0;
2094         }
2095         ap->cur_time++;
2096
2097         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2098                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2099
2100                 if (rx_cfg_reg != ap->ability_match_cfg) {
2101                         ap->ability_match_cfg = rx_cfg_reg;
2102                         ap->ability_match = 0;
2103                         ap->ability_match_count = 0;
2104                 } else {
2105                         if (++ap->ability_match_count > 1) {
2106                                 ap->ability_match = 1;
2107                                 ap->ability_match_cfg = rx_cfg_reg;
2108                         }
2109                 }
2110                 if (rx_cfg_reg & ANEG_CFG_ACK)
2111                         ap->ack_match = 1;
2112                 else
2113                         ap->ack_match = 0;
2114
2115                 ap->idle_match = 0;
2116         } else {
2117                 ap->idle_match = 1;
2118                 ap->ability_match_cfg = 0;
2119                 ap->ability_match_count = 0;
2120                 ap->ability_match = 0;
2121                 ap->ack_match = 0;
2122
2123                 rx_cfg_reg = 0;
2124         }
2125
2126         ap->rxconfig = rx_cfg_reg;
2127         ret = ANEG_OK;
2128
2129         switch(ap->state) {
2130         case ANEG_STATE_UNKNOWN:
2131                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2132                         ap->state = ANEG_STATE_AN_ENABLE;
2133
2134                 /* fallthru */
2135         case ANEG_STATE_AN_ENABLE:
2136                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2137                 if (ap->flags & MR_AN_ENABLE) {
2138                         ap->link_time = 0;
2139                         ap->cur_time = 0;
2140                         ap->ability_match_cfg = 0;
2141                         ap->ability_match_count = 0;
2142                         ap->ability_match = 0;
2143                         ap->idle_match = 0;
2144                         ap->ack_match = 0;
2145
2146                         ap->state = ANEG_STATE_RESTART_INIT;
2147                 } else {
2148                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2149                 }
2150                 break;
2151
2152         case ANEG_STATE_RESTART_INIT:
2153                 ap->link_time = ap->cur_time;
2154                 ap->flags &= ~(MR_NP_LOADED);
2155                 ap->txconfig = 0;
2156                 tw32(MAC_TX_AUTO_NEG, 0);
2157                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2158                 tw32_f(MAC_MODE, tp->mac_mode);
2159                 udelay(40);
2160
2161                 ret = ANEG_TIMER_ENAB;
2162                 ap->state = ANEG_STATE_RESTART;
2163
2164                 /* fallthru */
2165         case ANEG_STATE_RESTART:
2166                 delta = ap->cur_time - ap->link_time;
2167                 if (delta > ANEG_STATE_SETTLE_TIME) {
2168                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2169                 } else {
2170                         ret = ANEG_TIMER_ENAB;
2171                 }
2172                 break;
2173
2174         case ANEG_STATE_DISABLE_LINK_OK:
2175                 ret = ANEG_DONE;
2176                 break;
2177
2178         case ANEG_STATE_ABILITY_DETECT_INIT:
2179                 ap->flags &= ~(MR_TOGGLE_TX);
2180                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2181                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2182                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2183                 tw32_f(MAC_MODE, tp->mac_mode);
2184                 udelay(40);
2185
2186                 ap->state = ANEG_STATE_ABILITY_DETECT;
2187                 break;
2188
2189         case ANEG_STATE_ABILITY_DETECT:
2190                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2191                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2192                 }
2193                 break;
2194
2195         case ANEG_STATE_ACK_DETECT_INIT:
2196                 ap->txconfig |= ANEG_CFG_ACK;
2197                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2198                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2199                 tw32_f(MAC_MODE, tp->mac_mode);
2200                 udelay(40);
2201
2202                 ap->state = ANEG_STATE_ACK_DETECT;
2203
2204                 /* fallthru */
2205         case ANEG_STATE_ACK_DETECT:
2206                 if (ap->ack_match != 0) {
2207                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2208                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2209                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2210                         } else {
2211                                 ap->state = ANEG_STATE_AN_ENABLE;
2212                         }
2213                 } else if (ap->ability_match != 0 &&
2214                            ap->rxconfig == 0) {
2215                         ap->state = ANEG_STATE_AN_ENABLE;
2216                 }
2217                 break;
2218
2219         case ANEG_STATE_COMPLETE_ACK_INIT:
2220                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2221                         ret = ANEG_FAILED;
2222                         break;
2223                 }
2224                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2225                                MR_LP_ADV_HALF_DUPLEX |
2226                                MR_LP_ADV_SYM_PAUSE |
2227                                MR_LP_ADV_ASYM_PAUSE |
2228                                MR_LP_ADV_REMOTE_FAULT1 |
2229                                MR_LP_ADV_REMOTE_FAULT2 |
2230                                MR_LP_ADV_NEXT_PAGE |
2231                                MR_TOGGLE_RX |
2232                                MR_NP_RX);
2233                 if (ap->rxconfig & ANEG_CFG_FD)
2234                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2235                 if (ap->rxconfig & ANEG_CFG_HD)
2236                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2237                 if (ap->rxconfig & ANEG_CFG_PS1)
2238                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2239                 if (ap->rxconfig & ANEG_CFG_PS2)
2240                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2241                 if (ap->rxconfig & ANEG_CFG_RF1)
2242                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2243                 if (ap->rxconfig & ANEG_CFG_RF2)
2244                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2245                 if (ap->rxconfig & ANEG_CFG_NP)
2246                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2247
2248                 ap->link_time = ap->cur_time;
2249
2250                 ap->flags ^= (MR_TOGGLE_TX);
2251                 if (ap->rxconfig & 0x0008)
2252                         ap->flags |= MR_TOGGLE_RX;
2253                 if (ap->rxconfig & ANEG_CFG_NP)
2254                         ap->flags |= MR_NP_RX;
2255                 ap->flags |= MR_PAGE_RX;
2256
2257                 ap->state = ANEG_STATE_COMPLETE_ACK;
2258                 ret = ANEG_TIMER_ENAB;
2259                 break;
2260
2261         case ANEG_STATE_COMPLETE_ACK:
2262                 if (ap->ability_match != 0 &&
2263                     ap->rxconfig == 0) {
2264                         ap->state = ANEG_STATE_AN_ENABLE;
2265                         break;
2266                 }
2267                 delta = ap->cur_time - ap->link_time;
2268                 if (delta > ANEG_STATE_SETTLE_TIME) {
2269                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2270                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2271                         } else {
2272                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2273                                     !(ap->flags & MR_NP_RX)) {
2274                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2275                                 } else {
2276                                         ret = ANEG_FAILED;
2277                                 }
2278                         }
2279                 }
2280                 break;
2281
2282         case ANEG_STATE_IDLE_DETECT_INIT:
2283                 ap->link_time = ap->cur_time;
2284                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2285                 tw32_f(MAC_MODE, tp->mac_mode);
2286                 udelay(40);
2287
2288                 ap->state = ANEG_STATE_IDLE_DETECT;
2289                 ret = ANEG_TIMER_ENAB;
2290                 break;
2291
2292         case ANEG_STATE_IDLE_DETECT:
2293                 if (ap->ability_match != 0 &&
2294                     ap->rxconfig == 0) {
2295                         ap->state = ANEG_STATE_AN_ENABLE;
2296                         break;
2297                 }
2298                 delta = ap->cur_time - ap->link_time;
2299                 if (delta > ANEG_STATE_SETTLE_TIME) {
2300                         /* XXX another gem from the Broadcom driver :( */
2301                         ap->state = ANEG_STATE_LINK_OK;
2302                 }
2303                 break;
2304
2305         case ANEG_STATE_LINK_OK:
2306                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2307                 ret = ANEG_DONE;
2308                 break;
2309
2310         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2311                 /* ??? unimplemented */
2312                 break;
2313
2314         case ANEG_STATE_NEXT_PAGE_WAIT:
2315                 /* ??? unimplemented */
2316                 break;
2317
2318         default:
2319                 ret = ANEG_FAILED;
2320                 break;
2321         };
2322
2323         return ret;
2324 }
2325
2326 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2327 {
2328         int res = 0;
2329         struct tg3_fiber_aneginfo aninfo;
2330         int status = ANEG_FAILED;
2331         unsigned int tick;
2332         u32 tmp;
2333
2334         tw32_f(MAC_TX_AUTO_NEG, 0);
2335
2336         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2337         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2338         udelay(40);
2339
2340         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2341         udelay(40);
2342
2343         memset(&aninfo, 0, sizeof(aninfo));
2344         aninfo.flags |= MR_AN_ENABLE;
2345         aninfo.state = ANEG_STATE_UNKNOWN;
2346         aninfo.cur_time = 0;
2347         tick = 0;
2348         while (++tick < 195000) {
2349                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2350                 if (status == ANEG_DONE || status == ANEG_FAILED)
2351                         break;
2352
2353                 udelay(1);
2354         }
2355
2356         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2357         tw32_f(MAC_MODE, tp->mac_mode);
2358         udelay(40);
2359
2360         *flags = aninfo.flags;
2361
2362         if (status == ANEG_DONE &&
2363             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2364                              MR_LP_ADV_FULL_DUPLEX)))
2365                 res = 1;
2366
2367         return res;
2368 }
2369
2370 static void tg3_init_bcm8002(struct tg3 *tp)
2371 {
2372         u32 mac_status = tr32(MAC_STATUS);
2373         int i;
2374
2375         /* Reset when initting first time or we have a link. */
2376         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2377             !(mac_status & MAC_STATUS_PCS_SYNCED))
2378                 return;
2379
2380         /* Set PLL lock range. */
2381         tg3_writephy(tp, 0x16, 0x8007);
2382
2383         /* SW reset */
2384         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2385
2386         /* Wait for reset to complete. */
2387         /* XXX schedule_timeout() ... */
2388         for (i = 0; i < 500; i++)
2389                 udelay(10);
2390
2391         /* Config mode; select PMA/Ch 1 regs. */
2392         tg3_writephy(tp, 0x10, 0x8411);
2393
2394         /* Enable auto-lock and comdet, select txclk for tx. */
2395         tg3_writephy(tp, 0x11, 0x0a10);
2396
2397         tg3_writephy(tp, 0x18, 0x00a0);
2398         tg3_writephy(tp, 0x16, 0x41ff);
2399
2400         /* Assert and deassert POR. */
2401         tg3_writephy(tp, 0x13, 0x0400);
2402         udelay(40);
2403         tg3_writephy(tp, 0x13, 0x0000);
2404
2405         tg3_writephy(tp, 0x11, 0x0a50);
2406         udelay(40);
2407         tg3_writephy(tp, 0x11, 0x0a10);
2408
2409         /* Wait for signal to stabilize */
2410         /* XXX schedule_timeout() ... */
2411         for (i = 0; i < 15000; i++)
2412                 udelay(10);
2413
2414         /* Deselect the channel register so we can read the PHYID
2415          * later.
2416          */
2417         tg3_writephy(tp, 0x10, 0x8011);
2418 }
2419
2420 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2421 {
2422         u32 sg_dig_ctrl, sg_dig_status;
2423         u32 serdes_cfg, expected_sg_dig_ctrl;
2424         int workaround, port_a;
2425         int current_link_up;
2426
2427         serdes_cfg = 0;
2428         expected_sg_dig_ctrl = 0;
2429         workaround = 0;
2430         port_a = 1;
2431         current_link_up = 0;
2432
2433         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2434             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2435                 workaround = 1;
2436                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2437                         port_a = 0;
2438
2439                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2440                 /* preserve bits 20-23 for voltage regulator */
2441                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2442         }
2443
2444         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2445
2446         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2447                 if (sg_dig_ctrl & (1 << 31)) {
2448                         if (workaround) {
2449                                 u32 val = serdes_cfg;
2450
2451                                 if (port_a)
2452                                         val |= 0xc010000;
2453                                 else
2454                                         val |= 0x4010000;
2455                                 tw32_f(MAC_SERDES_CFG, val);
2456                         }
2457                         tw32_f(SG_DIG_CTRL, 0x01388400);
2458                 }
2459                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2460                         tg3_setup_flow_control(tp, 0, 0);
2461                         current_link_up = 1;
2462                 }
2463                 goto out;
2464         }
2465
2466         /* Want auto-negotiation.  */
2467         expected_sg_dig_ctrl = 0x81388400;
2468
2469         /* Pause capability */
2470         expected_sg_dig_ctrl |= (1 << 11);
2471
2472         /* Asymettric pause */
2473         expected_sg_dig_ctrl |= (1 << 12);
2474
2475         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2476                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2477                     tp->serdes_counter &&
2478                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2479                                     MAC_STATUS_RCVD_CFG)) ==
2480                      MAC_STATUS_PCS_SYNCED)) {
2481                         tp->serdes_counter--;
2482                         current_link_up = 1;
2483                         goto out;
2484                 }
2485 restart_autoneg:
2486                 if (workaround)
2487                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2488                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2489                 udelay(5);
2490                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2491
2492                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2493                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2494         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2495                                  MAC_STATUS_SIGNAL_DET)) {
2496                 sg_dig_status = tr32(SG_DIG_STATUS);
2497                 mac_status = tr32(MAC_STATUS);
2498
2499                 if ((sg_dig_status & (1 << 1)) &&
2500                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2501                         u32 local_adv, remote_adv;
2502
2503                         local_adv = ADVERTISE_PAUSE_CAP;
2504                         remote_adv = 0;
2505                         if (sg_dig_status & (1 << 19))
2506                                 remote_adv |= LPA_PAUSE_CAP;
2507                         if (sg_dig_status & (1 << 20))
2508                                 remote_adv |= LPA_PAUSE_ASYM;
2509
2510                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2511                         current_link_up = 1;
2512                         tp->serdes_counter = 0;
2513                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2514                 } else if (!(sg_dig_status & (1 << 1))) {
2515                         if (tp->serdes_counter)
2516                                 tp->serdes_counter--;
2517                         else {
2518                                 if (workaround) {
2519                                         u32 val = serdes_cfg;
2520
2521                                         if (port_a)
2522                                                 val |= 0xc010000;
2523                                         else
2524                                                 val |= 0x4010000;
2525
2526                                         tw32_f(MAC_SERDES_CFG, val);
2527                                 }
2528
2529                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2530                                 udelay(40);
2531
2532                                 /* Link parallel detection - link is up */
2533                                 /* only if we have PCS_SYNC and not */
2534                                 /* receiving config code words */
2535                                 mac_status = tr32(MAC_STATUS);
2536                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2537                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2538                                         tg3_setup_flow_control(tp, 0, 0);
2539                                         current_link_up = 1;
2540                                         tp->tg3_flags2 |=
2541                                                 TG3_FLG2_PARALLEL_DETECT;
2542                                         tp->serdes_counter =
2543                                                 SERDES_PARALLEL_DET_TIMEOUT;
2544                                 } else
2545                                         goto restart_autoneg;
2546                         }
2547                 }
2548         } else {
2549                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2550                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2551         }
2552
2553 out:
2554         return current_link_up;
2555 }
2556
2557 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2558 {
2559         int current_link_up = 0;
2560
2561         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2562                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2563                 goto out;
2564         }
2565
2566         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2567                 u32 flags;
2568                 int i;
2569
2570                 if (fiber_autoneg(tp, &flags)) {
2571                         u32 local_adv, remote_adv;
2572
2573                         local_adv = ADVERTISE_PAUSE_CAP;
2574                         remote_adv = 0;
2575                         if (flags & MR_LP_ADV_SYM_PAUSE)
2576                                 remote_adv |= LPA_PAUSE_CAP;
2577                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2578                                 remote_adv |= LPA_PAUSE_ASYM;
2579
2580                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2581
2582                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2583                         current_link_up = 1;
2584                 }
2585                 for (i = 0; i < 30; i++) {
2586                         udelay(20);
2587                         tw32_f(MAC_STATUS,
2588                                (MAC_STATUS_SYNC_CHANGED |
2589                                 MAC_STATUS_CFG_CHANGED));
2590                         udelay(40);
2591                         if ((tr32(MAC_STATUS) &
2592                              (MAC_STATUS_SYNC_CHANGED |
2593                               MAC_STATUS_CFG_CHANGED)) == 0)
2594                                 break;
2595                 }
2596
2597                 mac_status = tr32(MAC_STATUS);
2598                 if (current_link_up == 0 &&
2599                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2600                     !(mac_status & MAC_STATUS_RCVD_CFG))
2601                         current_link_up = 1;
2602         } else {
2603                 /* Forcing 1000FD link up. */
2604                 current_link_up = 1;
2605                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2606
2607                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2608                 udelay(40);
2609         }
2610
2611 out:
2612         return current_link_up;
2613 }
2614
2615 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2616 {
2617         u32 orig_pause_cfg;
2618         u16 orig_active_speed;
2619         u8 orig_active_duplex;
2620         u32 mac_status;
2621         int current_link_up;
2622         int i;
2623
2624         orig_pause_cfg =
2625                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2626                                   TG3_FLAG_TX_PAUSE));
2627         orig_active_speed = tp->link_config.active_speed;
2628         orig_active_duplex = tp->link_config.active_duplex;
2629
2630         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2631             netif_carrier_ok(tp->dev) &&
2632             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2633                 mac_status = tr32(MAC_STATUS);
2634                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2635                                MAC_STATUS_SIGNAL_DET |
2636                                MAC_STATUS_CFG_CHANGED |
2637                                MAC_STATUS_RCVD_CFG);
2638                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2639                                    MAC_STATUS_SIGNAL_DET)) {
2640                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2641                                             MAC_STATUS_CFG_CHANGED));
2642                         return 0;
2643                 }
2644         }
2645
2646         tw32_f(MAC_TX_AUTO_NEG, 0);
2647
2648         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2649         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2650         tw32_f(MAC_MODE, tp->mac_mode);
2651         udelay(40);
2652
2653         if (tp->phy_id == PHY_ID_BCM8002)
2654                 tg3_init_bcm8002(tp);
2655
2656         /* Enable link change event even when serdes polling.  */
2657         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2658         udelay(40);
2659
2660         current_link_up = 0;
2661         mac_status = tr32(MAC_STATUS);
2662
2663         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2664                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2665         else
2666                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2667
2668         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2669         tw32_f(MAC_MODE, tp->mac_mode);
2670         udelay(40);
2671
2672         tp->hw_status->status =
2673                 (SD_STATUS_UPDATED |
2674                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2675
2676         for (i = 0; i < 100; i++) {
2677                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2678                                     MAC_STATUS_CFG_CHANGED));
2679                 udelay(5);
2680                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2681                                          MAC_STATUS_CFG_CHANGED |
2682                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2683                         break;
2684         }
2685
2686         mac_status = tr32(MAC_STATUS);
2687         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2688                 current_link_up = 0;
2689                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2690                     tp->serdes_counter == 0) {
2691                         tw32_f(MAC_MODE, (tp->mac_mode |
2692                                           MAC_MODE_SEND_CONFIGS));
2693                         udelay(1);
2694                         tw32_f(MAC_MODE, tp->mac_mode);
2695                 }
2696         }
2697
2698         if (current_link_up == 1) {
2699                 tp->link_config.active_speed = SPEED_1000;
2700                 tp->link_config.active_duplex = DUPLEX_FULL;
2701                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2702                                     LED_CTRL_LNKLED_OVERRIDE |
2703                                     LED_CTRL_1000MBPS_ON));
2704         } else {
2705                 tp->link_config.active_speed = SPEED_INVALID;
2706                 tp->link_config.active_duplex = DUPLEX_INVALID;
2707                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2708                                     LED_CTRL_LNKLED_OVERRIDE |
2709                                     LED_CTRL_TRAFFIC_OVERRIDE));
2710         }
2711
2712         if (current_link_up != netif_carrier_ok(tp->dev)) {
2713                 if (current_link_up)
2714                         netif_carrier_on(tp->dev);
2715                 else
2716                         netif_carrier_off(tp->dev);
2717                 tg3_link_report(tp);
2718         } else {
2719                 u32 now_pause_cfg =
2720                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2721                                          TG3_FLAG_TX_PAUSE);
2722                 if (orig_pause_cfg != now_pause_cfg ||
2723                     orig_active_speed != tp->link_config.active_speed ||
2724                     orig_active_duplex != tp->link_config.active_duplex)
2725                         tg3_link_report(tp);
2726         }
2727
2728         return 0;
2729 }
2730
2731 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2732 {
2733         int current_link_up, err = 0;
2734         u32 bmsr, bmcr;
2735         u16 current_speed;
2736         u8 current_duplex;
2737
2738         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2739         tw32_f(MAC_MODE, tp->mac_mode);
2740         udelay(40);
2741
2742         tw32(MAC_EVENT, 0);
2743
2744         tw32_f(MAC_STATUS,
2745              (MAC_STATUS_SYNC_CHANGED |
2746               MAC_STATUS_CFG_CHANGED |
2747               MAC_STATUS_MI_COMPLETION |
2748               MAC_STATUS_LNKSTATE_CHANGED));
2749         udelay(40);
2750
2751         if (force_reset)
2752                 tg3_phy_reset(tp);
2753
2754         current_link_up = 0;
2755         current_speed = SPEED_INVALID;
2756         current_duplex = DUPLEX_INVALID;
2757
2758         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2759         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2760         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2761                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2762                         bmsr |= BMSR_LSTATUS;
2763                 else
2764                         bmsr &= ~BMSR_LSTATUS;
2765         }
2766
2767         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2768
2769         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2770             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2771                 /* do nothing, just check for link up at the end */
2772         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2773                 u32 adv, new_adv;
2774
2775                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2776                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2777                                   ADVERTISE_1000XPAUSE |
2778                                   ADVERTISE_1000XPSE_ASYM |
2779                                   ADVERTISE_SLCT);
2780
2781                 /* Always advertise symmetric PAUSE just like copper */
2782                 new_adv |= ADVERTISE_1000XPAUSE;
2783
2784                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2785                         new_adv |= ADVERTISE_1000XHALF;
2786                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2787                         new_adv |= ADVERTISE_1000XFULL;
2788
2789                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2790                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2791                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2792                         tg3_writephy(tp, MII_BMCR, bmcr);
2793
2794                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2795                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2796                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2797
2798                         return err;
2799                 }
2800         } else {
2801                 u32 new_bmcr;
2802
2803                 bmcr &= ~BMCR_SPEED1000;
2804                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2805
2806                 if (tp->link_config.duplex == DUPLEX_FULL)
2807                         new_bmcr |= BMCR_FULLDPLX;
2808
2809                 if (new_bmcr != bmcr) {
2810                         /* BMCR_SPEED1000 is a reserved bit that needs
2811                          * to be set on write.
2812                          */
2813                         new_bmcr |= BMCR_SPEED1000;
2814
2815                         /* Force a linkdown */
2816                         if (netif_carrier_ok(tp->dev)) {
2817                                 u32 adv;
2818
2819                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2820                                 adv &= ~(ADVERTISE_1000XFULL |
2821                                          ADVERTISE_1000XHALF |
2822                                          ADVERTISE_SLCT);
2823                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2824                                 tg3_writephy(tp, MII_BMCR, bmcr |
2825                                                            BMCR_ANRESTART |
2826                                                            BMCR_ANENABLE);
2827                                 udelay(10);
2828                                 netif_carrier_off(tp->dev);
2829                         }
2830                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2831                         bmcr = new_bmcr;
2832                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2833                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2834                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2835                             ASIC_REV_5714) {
2836                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2837                                         bmsr |= BMSR_LSTATUS;
2838                                 else
2839                                         bmsr &= ~BMSR_LSTATUS;
2840                         }
2841                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2842                 }
2843         }
2844
2845         if (bmsr & BMSR_LSTATUS) {
2846                 current_speed = SPEED_1000;
2847                 current_link_up = 1;
2848                 if (bmcr & BMCR_FULLDPLX)
2849                         current_duplex = DUPLEX_FULL;
2850                 else
2851                         current_duplex = DUPLEX_HALF;
2852
2853                 if (bmcr & BMCR_ANENABLE) {
2854                         u32 local_adv, remote_adv, common;
2855
2856                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2857                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2858                         common = local_adv & remote_adv;
2859                         if (common & (ADVERTISE_1000XHALF |
2860                                       ADVERTISE_1000XFULL)) {
2861                                 if (common & ADVERTISE_1000XFULL)
2862                                         current_duplex = DUPLEX_FULL;
2863                                 else
2864                                         current_duplex = DUPLEX_HALF;
2865
2866                                 tg3_setup_flow_control(tp, local_adv,
2867                                                        remote_adv);
2868                         }
2869                         else
2870                                 current_link_up = 0;
2871                 }
2872         }
2873
2874         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2875         if (tp->link_config.active_duplex == DUPLEX_HALF)
2876                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2877
2878         tw32_f(MAC_MODE, tp->mac_mode);
2879         udelay(40);
2880
2881         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2882
2883         tp->link_config.active_speed = current_speed;
2884         tp->link_config.active_duplex = current_duplex;
2885
2886         if (current_link_up != netif_carrier_ok(tp->dev)) {
2887                 if (current_link_up)
2888                         netif_carrier_on(tp->dev);
2889                 else {
2890                         netif_carrier_off(tp->dev);
2891                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2892                 }
2893                 tg3_link_report(tp);
2894         }
2895         return err;
2896 }
2897
2898 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2899 {
2900         if (tp->serdes_counter) {
2901                 /* Give autoneg time to complete. */
2902                 tp->serdes_counter--;
2903                 return;
2904         }
2905         if (!netif_carrier_ok(tp->dev) &&
2906             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2907                 u32 bmcr;
2908
2909                 tg3_readphy(tp, MII_BMCR, &bmcr);
2910                 if (bmcr & BMCR_ANENABLE) {
2911                         u32 phy1, phy2;
2912
2913                         /* Select shadow register 0x1f */
2914                         tg3_writephy(tp, 0x1c, 0x7c00);
2915                         tg3_readphy(tp, 0x1c, &phy1);
2916
2917                         /* Select expansion interrupt status register */
2918                         tg3_writephy(tp, 0x17, 0x0f01);
2919                         tg3_readphy(tp, 0x15, &phy2);
2920                         tg3_readphy(tp, 0x15, &phy2);
2921
2922                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2923                                 /* We have signal detect and not receiving
2924                                  * config code words, link is up by parallel
2925                                  * detection.
2926                                  */
2927
2928                                 bmcr &= ~BMCR_ANENABLE;
2929                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2930                                 tg3_writephy(tp, MII_BMCR, bmcr);
2931                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2932                         }
2933                 }
2934         }
2935         else if (netif_carrier_ok(tp->dev) &&
2936                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2937                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2938                 u32 phy2;
2939
2940                 /* Select expansion interrupt status register */
2941                 tg3_writephy(tp, 0x17, 0x0f01);
2942                 tg3_readphy(tp, 0x15, &phy2);
2943                 if (phy2 & 0x20) {
2944                         u32 bmcr;
2945
2946                         /* Config code words received, turn on autoneg. */
2947                         tg3_readphy(tp, MII_BMCR, &bmcr);
2948                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2949
2950                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2951
2952                 }
2953         }
2954 }
2955
2956 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2957 {
2958         int err;
2959
2960         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2961                 err = tg3_setup_fiber_phy(tp, force_reset);
2962         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2963                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2964         } else {
2965                 err = tg3_setup_copper_phy(tp, force_reset);
2966         }
2967
2968         if (tp->link_config.active_speed == SPEED_1000 &&
2969             tp->link_config.active_duplex == DUPLEX_HALF)
2970                 tw32(MAC_TX_LENGTHS,
2971                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2972                       (6 << TX_LENGTHS_IPG_SHIFT) |
2973                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2974         else
2975                 tw32(MAC_TX_LENGTHS,
2976                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2977                       (6 << TX_LENGTHS_IPG_SHIFT) |
2978                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2979
2980         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2981                 if (netif_carrier_ok(tp->dev)) {
2982                         tw32(HOSTCC_STAT_COAL_TICKS,
2983                              tp->coal.stats_block_coalesce_usecs);
2984                 } else {
2985                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2986                 }
2987         }
2988
2989         return err;
2990 }
2991
2992 /* This is called whenever we suspect that the system chipset is re-
2993  * ordering the sequence of MMIO to the tx send mailbox. The symptom
2994  * is bogus tx completions. We try to recover by setting the
2995  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
2996  * in the workqueue.
2997  */
2998 static void tg3_tx_recover(struct tg3 *tp)
2999 {
3000         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3001                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3002
3003         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3004                "mapped I/O cycles to the network device, attempting to "
3005                "recover. Please report the problem to the driver maintainer "
3006                "and include system chipset information.\n", tp->dev->name);
3007
3008         spin_lock(&tp->lock);
3009         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3010         spin_unlock(&tp->lock);
3011 }
3012
3013 static inline u32 tg3_tx_avail(struct tg3 *tp)
3014 {
3015         smp_mb();
3016         return (tp->tx_pending -
3017                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3018 }
3019
3020 /* Tigon3 never reports partial packet sends.  So we do not
3021  * need special logic to handle SKBs that have not had all
3022  * of their frags sent yet, like SunGEM does.
3023  */
3024 static void tg3_tx(struct tg3 *tp)
3025 {
3026         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3027         u32 sw_idx = tp->tx_cons;
3028
3029         while (sw_idx != hw_idx) {
3030                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3031                 struct sk_buff *skb = ri->skb;
3032                 int i, tx_bug = 0;
3033
3034                 if (unlikely(skb == NULL)) {
3035                         tg3_tx_recover(tp);
3036                         return;
3037                 }
3038
3039                 pci_unmap_single(tp->pdev,
3040                                  pci_unmap_addr(ri, mapping),
3041                                  skb_headlen(skb),
3042                                  PCI_DMA_TODEVICE);
3043
3044                 ri->skb = NULL;
3045
3046                 sw_idx = NEXT_TX(sw_idx);
3047
3048                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3049                         ri = &tp->tx_buffers[sw_idx];
3050                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3051                                 tx_bug = 1;
3052
3053                         pci_unmap_page(tp->pdev,
3054                                        pci_unmap_addr(ri, mapping),
3055                                        skb_shinfo(skb)->frags[i].size,
3056                                        PCI_DMA_TODEVICE);
3057
3058                         sw_idx = NEXT_TX(sw_idx);
3059                 }
3060
3061                 dev_kfree_skb(skb);
3062
3063                 if (unlikely(tx_bug)) {
3064                         tg3_tx_recover(tp);
3065                         return;
3066                 }
3067         }
3068
3069         tp->tx_cons = sw_idx;
3070
3071         /* Need to make the tx_cons update visible to tg3_start_xmit()
3072          * before checking for netif_queue_stopped().  Without the
3073          * memory barrier, there is a small possibility that tg3_start_xmit()
3074          * will miss it and cause the queue to be stopped forever.
3075          */
3076         smp_mb();
3077
3078         if (unlikely(netif_queue_stopped(tp->dev) &&
3079                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3080                 netif_tx_lock(tp->dev);
3081                 if (netif_queue_stopped(tp->dev) &&
3082                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3083                         netif_wake_queue(tp->dev);
3084                 netif_tx_unlock(tp->dev);
3085         }
3086 }
3087
3088 /* Returns size of skb allocated or < 0 on error.
3089  *
3090  * We only need to fill in the address because the other members
3091  * of the RX descriptor are invariant, see tg3_init_rings.
3092  *
3093  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3094  * posting buffers we only dirty the first cache line of the RX
3095  * descriptor (containing the address).  Whereas for the RX status
3096  * buffers the cpu only reads the last cacheline of the RX descriptor
3097  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3098  */
3099 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3100                             int src_idx, u32 dest_idx_unmasked)
3101 {
3102         struct tg3_rx_buffer_desc *desc;
3103         struct ring_info *map, *src_map;
3104         struct sk_buff *skb;
3105         dma_addr_t mapping;
3106         int skb_size, dest_idx;
3107
3108         src_map = NULL;
3109         switch (opaque_key) {
3110         case RXD_OPAQUE_RING_STD:
3111                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3112                 desc = &tp->rx_std[dest_idx];
3113                 map = &tp->rx_std_buffers[dest_idx];
3114                 if (src_idx >= 0)
3115                         src_map = &tp->rx_std_buffers[src_idx];
3116                 skb_size = tp->rx_pkt_buf_sz;
3117                 break;
3118
3119         case RXD_OPAQUE_RING_JUMBO:
3120                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3121                 desc = &tp->rx_jumbo[dest_idx];
3122                 map = &tp->rx_jumbo_buffers[dest_idx];
3123                 if (src_idx >= 0)
3124                         src_map = &tp->rx_jumbo_buffers[src_idx];
3125                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3126                 break;
3127
3128         default:
3129                 return -EINVAL;
3130         };
3131
3132         /* Do not overwrite any of the map or rp information
3133          * until we are sure we can commit to a new buffer.
3134          *
3135          * Callers depend upon this behavior and assume that
3136          * we leave everything unchanged if we fail.
3137          */
3138         skb = netdev_alloc_skb(tp->dev, skb_size);
3139         if (skb == NULL)
3140                 return -ENOMEM;
3141
3142         skb_reserve(skb, tp->rx_offset);
3143
3144         mapping = pci_map_single(tp->pdev, skb->data,
3145                                  skb_size - tp->rx_offset,
3146                                  PCI_DMA_FROMDEVICE);
3147
3148         map->skb = skb;
3149         pci_unmap_addr_set(map, mapping, mapping);
3150
3151         if (src_map != NULL)
3152                 src_map->skb = NULL;
3153
3154         desc->addr_hi = ((u64)mapping >> 32);
3155         desc->addr_lo = ((u64)mapping & 0xffffffff);
3156
3157         return skb_size;
3158 }
3159
3160 /* We only need to move over in the address because the other
3161  * members of the RX descriptor are invariant.  See notes above
3162  * tg3_alloc_rx_skb for full details.
3163  */
3164 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3165                            int src_idx, u32 dest_idx_unmasked)
3166 {
3167         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3168         struct ring_info *src_map, *dest_map;
3169         int dest_idx;
3170
3171         switch (opaque_key) {
3172         case RXD_OPAQUE_RING_STD:
3173                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3174                 dest_desc = &tp->rx_std[dest_idx];
3175                 dest_map = &tp->rx_std_buffers[dest_idx];
3176                 src_desc = &tp->rx_std[src_idx];
3177                 src_map = &tp->rx_std_buffers[src_idx];
3178                 break;
3179
3180         case RXD_OPAQUE_RING_JUMBO:
3181                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3182                 dest_desc = &tp->rx_jumbo[dest_idx];
3183                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3184                 src_desc = &tp->rx_jumbo[src_idx];
3185                 src_map = &tp->rx_jumbo_buffers[src_idx];
3186                 break;
3187
3188         default:
3189                 return;
3190         };
3191
3192         dest_map->skb = src_map->skb;
3193         pci_unmap_addr_set(dest_map, mapping,
3194                            pci_unmap_addr(src_map, mapping));
3195         dest_desc->addr_hi = src_desc->addr_hi;
3196         dest_desc->addr_lo = src_desc->addr_lo;
3197
3198         src_map->skb = NULL;
3199 }
3200
3201 #if TG3_VLAN_TAG_USED
3202 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3203 {
3204         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3205 }
3206 #endif
3207
3208 /* The RX ring scheme is composed of multiple rings which post fresh
3209  * buffers to the chip, and one special ring the chip uses to report
3210  * status back to the host.
3211  *
3212  * The special ring reports the status of received packets to the
3213  * host.  The chip does not write into the original descriptor the
3214  * RX buffer was obtained from.  The chip simply takes the original
3215  * descriptor as provided by the host, updates the status and length
3216  * field, then writes this into the next status ring entry.
3217  *
3218  * Each ring the host uses to post buffers to the chip is described
3219  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3220  * it is first placed into the on-chip ram.  When the packet's length
3221  * is known, it walks down the TG3_BDINFO entries to select the ring.
3222  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3223  * which is within the range of the new packet's length is chosen.
3224  *
3225  * The "separate ring for rx status" scheme may sound queer, but it makes
3226  * sense from a cache coherency perspective.  If only the host writes
3227  * to the buffer post rings, and only the chip writes to the rx status
3228  * rings, then cache lines never move beyond shared-modified state.
3229  * If both the host and chip were to write into the same ring, cache line
3230  * eviction could occur since both entities want it in an exclusive state.
3231  */
3232 static int tg3_rx(struct tg3 *tp, int budget)
3233 {
3234         u32 work_mask, rx_std_posted = 0;
3235         u32 sw_idx = tp->rx_rcb_ptr;
3236         u16 hw_idx;
3237         int received;
3238
3239         hw_idx = tp->hw_status->idx[0].rx_producer;
3240         /*
3241          * We need to order the read of hw_idx and the read of
3242          * the opaque cookie.
3243          */
3244         rmb();
3245         work_mask = 0;
3246         received = 0;
3247         while (sw_idx != hw_idx && budget > 0) {
3248                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3249                 unsigned int len;
3250                 struct sk_buff *skb;
3251                 dma_addr_t dma_addr;
3252                 u32 opaque_key, desc_idx, *post_ptr;
3253
3254                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3255                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3256                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3257                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3258                                                   mapping);
3259                         skb = tp->rx_std_buffers[desc_idx].skb;
3260                         post_ptr = &tp->rx_std_ptr;
3261                         rx_std_posted++;
3262                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3263                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3264                                                   mapping);
3265                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3266                         post_ptr = &tp->rx_jumbo_ptr;
3267                 }
3268                 else {
3269                         goto next_pkt_nopost;
3270                 }
3271
3272                 work_mask |= opaque_key;
3273
3274                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3275                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3276                 drop_it:
3277                         tg3_recycle_rx(tp, opaque_key,
3278                                        desc_idx, *post_ptr);
3279                 drop_it_no_recycle:
3280                         /* Other statistics kept track of by card. */
3281                         tp->net_stats.rx_dropped++;
3282                         goto next_pkt;
3283                 }
3284
3285                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3286
3287                 if (len > RX_COPY_THRESHOLD
3288                         && tp->rx_offset == 2
3289                         /* rx_offset != 2 iff this is a 5701 card running
3290                          * in PCI-X mode [see tg3_get_invariants()] */
3291                 ) {
3292                         int skb_size;
3293
3294                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3295                                                     desc_idx, *post_ptr);
3296                         if (skb_size < 0)
3297                                 goto drop_it;
3298
3299                         pci_unmap_single(tp->pdev, dma_addr,
3300                                          skb_size - tp->rx_offset,
3301                                          PCI_DMA_FROMDEVICE);
3302
3303                         skb_put(skb, len);
3304                 } else {
3305                         struct sk_buff *copy_skb;
3306
3307                         tg3_recycle_rx(tp, opaque_key,
3308                                        desc_idx, *post_ptr);
3309
3310                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3311                         if (copy_skb == NULL)
3312                                 goto drop_it_no_recycle;
3313
3314                         skb_reserve(copy_skb, 2);
3315                         skb_put(copy_skb, len);
3316                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3317                         memcpy(copy_skb->data, skb->data, len);
3318                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3319
3320                         /* We'll reuse the original ring buffer. */
3321                         skb = copy_skb;
3322                 }
3323
3324                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3325                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3326                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3327                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3328                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3329                 else
3330                         skb->ip_summed = CHECKSUM_NONE;
3331
3332                 skb->protocol = eth_type_trans(skb, tp->dev);
3333 #if TG3_VLAN_TAG_USED
3334                 if (tp->vlgrp != NULL &&
3335                     desc->type_flags & RXD_FLAG_VLAN) {
3336                         tg3_vlan_rx(tp, skb,
3337                                     desc->err_vlan & RXD_VLAN_MASK);
3338                 } else
3339 #endif
3340                         netif_receive_skb(skb);
3341
3342                 tp->dev->last_rx = jiffies;
3343                 received++;
3344                 budget--;
3345
3346 next_pkt:
3347                 (*post_ptr)++;
3348
3349                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3350                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3351
3352                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3353                                      TG3_64BIT_REG_LOW, idx);
3354                         work_mask &= ~RXD_OPAQUE_RING_STD;
3355                         rx_std_posted = 0;
3356                 }
3357 next_pkt_nopost:
3358                 sw_idx++;
3359                 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
3360
3361                 /* Refresh hw_idx to see if there is new work */
3362                 if (sw_idx == hw_idx) {
3363                         hw_idx = tp->hw_status->idx[0].rx_producer;
3364                         rmb();
3365                 }
3366         }
3367
3368         /* ACK the status ring. */
3369         tp->rx_rcb_ptr = sw_idx;
3370         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3371
3372         /* Refill RX ring(s). */
3373         if (work_mask & RXD_OPAQUE_RING_STD) {
3374                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3375                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3376                              sw_idx);
3377         }
3378         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3379                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3380                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3381                              sw_idx);
3382         }
3383         mmiowb();
3384
3385         return received;
3386 }
3387
3388 static int tg3_poll(struct net_device *netdev, int *budget)
3389 {
3390         struct tg3 *tp = netdev_priv(netdev);
3391         struct tg3_hw_status *sblk = tp->hw_status;
3392         int done;
3393
3394         /* handle link change and other phy events */
3395         if (!(tp->tg3_flags &
3396               (TG3_FLAG_USE_LINKCHG_REG |
3397                TG3_FLAG_POLL_SERDES))) {
3398                 if (sblk->status & SD_STATUS_LINK_CHG) {
3399                         sblk->status = SD_STATUS_UPDATED |
3400                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3401                         spin_lock(&tp->lock);
3402                         tg3_setup_phy(tp, 0);
3403                         spin_unlock(&tp->lock);
3404                 }
3405         }
3406
3407         /* run TX completion thread */
3408         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3409                 tg3_tx(tp);
3410                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3411                         netif_rx_complete(netdev);
3412                         schedule_work(&tp->reset_task);
3413                         return 0;
3414                 }
3415         }
3416
3417         /* run RX thread, within the bounds set by NAPI.
3418          * All RX "locking" is done by ensuring outside
3419          * code synchronizes with dev->poll()
3420          */
3421         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3422                 int orig_budget = *budget;
3423                 int work_done;
3424
3425                 if (orig_budget > netdev->quota)
3426                         orig_budget = netdev->quota;
3427
3428                 work_done = tg3_rx(tp, orig_budget);
3429
3430                 *budget -= work_done;
3431                 netdev->quota -= work_done;
3432         }
3433
3434         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3435                 tp->last_tag = sblk->status_tag;
3436                 rmb();
3437         } else
3438                 sblk->status &= ~SD_STATUS_UPDATED;
3439
3440         /* if no more work, tell net stack and NIC we're done */
3441         done = !tg3_has_work(tp);
3442         if (done) {
3443                 netif_rx_complete(netdev);
3444                 tg3_restart_ints(tp);
3445         }
3446
3447         return (done ? 0 : 1);
3448 }
3449
3450 static void tg3_irq_quiesce(struct tg3 *tp)
3451 {
3452         BUG_ON(tp->irq_sync);
3453
3454         tp->irq_sync = 1;
3455         smp_mb();
3456
3457         synchronize_irq(tp->pdev->irq);
3458 }
3459
3460 static inline int tg3_irq_sync(struct tg3 *tp)
3461 {
3462         return tp->irq_sync;
3463 }
3464
3465 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3466  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3467  * with as well.  Most of the time, this is not necessary except when
3468  * shutting down the device.
3469  */
3470 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3471 {
3472         if (irq_sync)
3473                 tg3_irq_quiesce(tp);
3474         spin_lock_bh(&tp->lock);
3475 }
3476
3477 static inline void tg3_full_unlock(struct tg3 *tp)
3478 {
3479         spin_unlock_bh(&tp->lock);
3480 }
3481
3482 /* One-shot MSI handler - Chip automatically disables interrupt
3483  * after sending MSI so driver doesn't have to do it.
3484  */
3485 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3486 {
3487         struct net_device *dev = dev_id;
3488         struct tg3 *tp = netdev_priv(dev);
3489
3490         prefetch(tp->hw_status);
3491         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3492
3493         if (likely(!tg3_irq_sync(tp)))
3494                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3495
3496         return IRQ_HANDLED;
3497 }
3498
3499 /* MSI ISR - No need to check for interrupt sharing and no need to
3500  * flush status block and interrupt mailbox. PCI ordering rules
3501  * guarantee that MSI will arrive after the status block.
3502  */
3503 static irqreturn_t tg3_msi(int irq, void *dev_id)
3504 {
3505         struct net_device *dev = dev_id;
3506         struct tg3 *tp = netdev_priv(dev);
3507
3508         prefetch(tp->hw_status);
3509         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3510         /*
3511          * Writing any value to intr-mbox-0 clears PCI INTA# and
3512          * chip-internal interrupt pending events.
3513          * Writing non-zero to intr-mbox-0 additional tells the
3514          * NIC to stop sending us irqs, engaging "in-intr-handler"
3515          * event coalescing.
3516          */
3517         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3518         if (likely(!tg3_irq_sync(tp)))
3519                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3520
3521         return IRQ_RETVAL(1);
3522 }
3523
3524 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3525 {
3526         struct net_device *dev = dev_id;
3527         struct tg3 *tp = netdev_priv(dev);
3528         struct tg3_hw_status *sblk = tp->hw_status;
3529         unsigned int handled = 1;
3530
3531         /* In INTx mode, it is possible for the interrupt to arrive at
3532          * the CPU before the status block posted prior to the interrupt.
3533          * Reading the PCI State register will confirm whether the
3534          * interrupt is ours and will flush the status block.
3535          */
3536         if ((sblk->status & SD_STATUS_UPDATED) ||
3537             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3538                 /*
3539                  * Writing any value to intr-mbox-0 clears PCI INTA# and
3540                  * chip-internal interrupt pending events.
3541                  * Writing non-zero to intr-mbox-0 additional tells the
3542                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3543                  * event coalescing.
3544                  */
3545                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3546                              0x00000001);
3547                 if (tg3_irq_sync(tp))
3548                         goto out;
3549                 sblk->status &= ~SD_STATUS_UPDATED;
3550                 if (likely(tg3_has_work(tp))) {
3551                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3552                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3553                 } else {
3554                         /* No work, shared interrupt perhaps?  re-enable
3555                          * interrupts, and flush that PCI write
3556                          */
3557                         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3558                                 0x00000000);
3559                 }
3560         } else {        /* shared interrupt */
3561                 handled = 0;
3562         }
3563 out:
3564         return IRQ_RETVAL(handled);
3565 }
3566
3567 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3568 {
3569         struct net_device *dev = dev_id;
3570         struct tg3 *tp = netdev_priv(dev);
3571         struct tg3_hw_status *sblk = tp->hw_status;
3572         unsigned int handled = 1;
3573
3574         /* In INTx mode, it is possible for the interrupt to arrive at
3575          * the CPU before the status block posted prior to the interrupt.
3576          * Reading the PCI State register will confirm whether the
3577          * interrupt is ours and will flush the status block.
3578          */
3579         if ((sblk->status_tag != tp->last_tag) ||
3580             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3581                 /*
3582                  * writing any value to intr-mbox-0 clears PCI INTA# and
3583                  * chip-internal interrupt pending events.
3584                  * writing non-zero to intr-mbox-0 additional tells the
3585                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3586                  * event coalescing.
3587                  */
3588                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3589                              0x00000001);
3590                 if (tg3_irq_sync(tp))
3591                         goto out;
3592                 if (netif_rx_schedule_prep(dev)) {
3593                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3594                         /* Update last_tag to mark that this status has been
3595                          * seen. Because interrupt may be shared, we may be
3596                          * racing with tg3_poll(), so only update last_tag
3597                          * if tg3_poll() is not scheduled.
3598                          */
3599                         tp->last_tag = sblk->status_tag;
3600                         __netif_rx_schedule(dev);
3601                 }
3602         } else {        /* shared interrupt */
3603                 handled = 0;
3604         }
3605 out:
3606         return IRQ_RETVAL(handled);
3607 }
3608
3609 /* ISR for interrupt test */
3610 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3611 {
3612         struct net_device *dev = dev_id;
3613         struct tg3 *tp = netdev_priv(dev);
3614         struct tg3_hw_status *sblk = tp->hw_status;
3615
3616         if ((sblk->status & SD_STATUS_UPDATED) ||
3617             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3618                 tg3_disable_ints(tp);
3619                 return IRQ_RETVAL(1);
3620         }
3621         return IRQ_RETVAL(0);
3622 }
3623
3624 static int tg3_init_hw(struct tg3 *, int);
3625 static int tg3_halt(struct tg3 *, int, int);
3626
3627 /* Restart hardware after configuration changes, self-test, etc.
3628  * Invoked with tp->lock held.
3629  */
3630 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3631 {
3632         int err;
3633
3634         err = tg3_init_hw(tp, reset_phy);
3635         if (err) {
3636                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3637                        "aborting.\n", tp->dev->name);
3638                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3639                 tg3_full_unlock(tp);
3640                 del_timer_sync(&tp->timer);
3641                 tp->irq_sync = 0;
3642                 netif_poll_enable(tp->dev);
3643                 dev_close(tp->dev);
3644                 tg3_full_lock(tp, 0);
3645         }
3646         return err;
3647 }
3648
3649 #ifdef CONFIG_NET_POLL_CONTROLLER
3650 static void tg3_poll_controller(struct net_device *dev)
3651 {
3652         struct tg3 *tp = netdev_priv(dev);
3653
3654         tg3_interrupt(tp->pdev->irq, dev);
3655 }
3656 #endif
3657
3658 static void tg3_reset_task(struct work_struct *work)
3659 {
3660         struct tg3 *tp = container_of(work, struct tg3, reset_task);
3661         unsigned int restart_timer;
3662
3663         tg3_full_lock(tp, 0);
3664         tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3665
3666         if (!netif_running(tp->dev)) {
3667                 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3668                 tg3_full_unlock(tp);
3669                 return;
3670         }
3671
3672         tg3_full_unlock(tp);
3673
3674         tg3_netif_stop(tp);
3675
3676         tg3_full_lock(tp, 1);
3677
3678         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3679         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3680
3681         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3682                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3683                 tp->write32_rx_mbox = tg3_write_flush_reg32;
3684                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3685                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3686         }
3687
3688         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3689         if (tg3_init_hw(tp, 1))
3690                 goto out;
3691
3692         tg3_netif_start(tp);
3693
3694         if (restart_timer)
3695                 mod_timer(&tp->timer, jiffies + 1);
3696
3697 out:
3698         tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3699
3700         tg3_full_unlock(tp);
3701 }
3702
3703 static void tg3_tx_timeout(struct net_device *dev)
3704 {
3705         struct tg3 *tp = netdev_priv(dev);
3706
3707         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3708                dev->name);
3709
3710         schedule_work(&tp->reset_task);
3711 }
3712
3713 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3714 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3715 {
3716         u32 base = (u32) mapping & 0xffffffff;
3717
3718         return ((base > 0xffffdcc0) &&
3719                 (base + len + 8 < base));
3720 }
3721
3722 /* Test for DMA addresses > 40-bit */
3723 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3724                                           int len)
3725 {
3726 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3727         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3728                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3729         return 0;
3730 #else
3731         return 0;
3732 #endif
3733 }
3734
3735 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3736
3737 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3738 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3739                                        u32 last_plus_one, u32 *start,
3740                                        u32 base_flags, u32 mss)
3741 {
3742         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3743         dma_addr_t new_addr = 0;
3744         u32 entry = *start;
3745         int i, ret = 0;
3746
3747         if (!new_skb) {
3748                 ret = -1;
3749         } else {
3750                 /* New SKB is guaranteed to be linear. */
3751                 entry = *start;
3752                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3753                                           PCI_DMA_TODEVICE);
3754                 /* Make sure new skb does not cross any 4G boundaries.
3755                  * Drop the packet if it does.
3756                  */
3757                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3758                         ret = -1;
3759                         dev_kfree_skb(new_skb);
3760                         new_skb = NULL;
3761                 } else {
3762                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3763                                     base_flags, 1 | (mss << 1));
3764                         *start = NEXT_TX(entry);
3765                 }
3766         }
3767
3768         /* Now clean up the sw ring entries. */
3769         i = 0;
3770         while (entry != last_plus_one) {
3771                 int len;
3772
3773                 if (i == 0)
3774                         len = skb_headlen(skb);
3775                 else
3776                         len = skb_shinfo(skb)->frags[i-1].size;
3777                 pci_unmap_single(tp->pdev,
3778                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3779                                  len, PCI_DMA_TODEVICE);
3780                 if (i == 0) {
3781                         tp->tx_buffers[entry].skb = new_skb;
3782                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3783                 } else {
3784                         tp->tx_buffers[entry].skb = NULL;
3785                 }
3786                 entry = NEXT_TX(entry);
3787                 i++;
3788         }
3789
3790         dev_kfree_skb(skb);
3791
3792         return ret;
3793 }
3794
3795 static void tg3_set_txd(struct tg3 *tp, int entry,
3796                         dma_addr_t mapping, int len, u32 flags,
3797                         u32 mss_and_is_end)
3798 {
3799         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3800         int is_end = (mss_and_is_end & 0x1);
3801         u32 mss = (mss_and_is_end >> 1);
3802         u32 vlan_tag = 0;
3803
3804         if (is_end)
3805                 flags |= TXD_FLAG_END;
3806         if (flags & TXD_FLAG_VLAN) {
3807                 vlan_tag = flags >> 16;
3808                 flags &= 0xffff;
3809         }
3810         vlan_tag |= (mss << TXD_MSS_SHIFT);
3811
3812         txd->addr_hi = ((u64) mapping >> 32);
3813         txd->addr_lo = ((u64) mapping & 0xffffffff);
3814         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3815         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3816 }
3817
3818 /* hard_start_xmit for devices that don't have any bugs and
3819  * support TG3_FLG2_HW_TSO_2 only.
3820  */
3821 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3822 {
3823         struct tg3 *tp = netdev_priv(dev);
3824         dma_addr_t mapping;
3825         u32 len, entry, base_flags, mss;
3826
3827         len = skb_headlen(skb);
3828
3829         /* We are running in BH disabled context with netif_tx_lock
3830          * and TX reclaim runs via tp->poll inside of a software
3831          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3832          * no IRQ context deadlocks to worry about either.  Rejoice!
3833          */
3834         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3835                 if (!netif_queue_stopped(dev)) {
3836                         netif_stop_queue(dev);
3837
3838                         /* This is a hard error, log it. */
3839                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3840                                "queue awake!\n", dev->name);
3841                 }
3842                 return NETDEV_TX_BUSY;
3843         }
3844
3845         entry = tp->tx_prod;
3846         base_flags = 0;
3847 #if TG3_TSO_SUPPORT != 0
3848         mss = 0;
3849         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3850             (mss = skb_shinfo(skb)->gso_size) != 0) {
3851                 int tcp_opt_len, ip_tcp_len;
3852
3853                 if (skb_header_cloned(skb) &&
3854                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3855                         dev_kfree_skb(skb);
3856                         goto out_unlock;
3857                 }
3858
3859                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3860                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3861                 else {
3862                         tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3863                         ip_tcp_len = (skb->nh.iph->ihl * 4) +
3864                                      sizeof(struct tcphdr);
3865
3866                         skb->nh.iph->check = 0;
3867                         skb->nh.iph->tot_len = htons(mss + ip_tcp_len +
3868                                                      tcp_opt_len);
3869                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
3870                 }
3871
3872                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3873                                TXD_FLAG_CPU_POST_DMA);
3874
3875                 skb->h.th->check = 0;
3876
3877         }
3878         else if (skb->ip_summed == CHECKSUM_PARTIAL)
3879                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3880 #else
3881         mss = 0;
3882         if (skb->ip_summed == CHECKSUM_PARTIAL)
3883                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3884 #endif
3885 #if TG3_VLAN_TAG_USED
3886         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3887                 base_flags |= (TXD_FLAG_VLAN |
3888                                (vlan_tx_tag_get(skb) << 16));
3889 #endif
3890
3891         /* Queue skb data, a.k.a. the main skb fragment. */
3892         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3893
3894         tp->tx_buffers[entry].skb = skb;
3895         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3896
3897         tg3_set_txd(tp, entry, mapping, len, base_flags,
3898                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3899
3900         entry = NEXT_TX(entry);
3901
3902         /* Now loop through additional data fragments, and queue them. */
3903         if (skb_shinfo(skb)->nr_frags > 0) {
3904                 unsigned int i, last;
3905
3906                 last = skb_shinfo(skb)->nr_frags - 1;
3907                 for (i = 0; i <= last; i++) {
3908                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3909
3910                         len = frag->size;
3911                         mapping = pci_map_page(tp->pdev,
3912                                                frag->page,
3913                                                frag->page_offset,
3914                                                len, PCI_DMA_TODEVICE);
3915
3916                         tp->tx_buffers[entry].skb = NULL;
3917                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3918
3919                         tg3_set_txd(tp, entry, mapping, len,
3920                                     base_flags, (i == last) | (mss << 1));
3921
3922                         entry = NEXT_TX(entry);
3923                 }
3924         }
3925
3926         /* Packets are ready, update Tx producer idx local and on card. */
3927         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3928
3929         tp->tx_prod = entry;
3930         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3931                 netif_stop_queue(dev);
3932                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3933                         netif_wake_queue(tp->dev);
3934         }
3935
3936 out_unlock:
3937         mmiowb();
3938
3939         dev->trans_start = jiffies;
3940
3941         return NETDEV_TX_OK;
3942 }
3943
3944 #if TG3_TSO_SUPPORT != 0
3945 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3946
3947 /* Use GSO to workaround a rare TSO bug that may be triggered when the
3948  * TSO header is greater than 80 bytes.
3949  */
3950 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3951 {
3952         struct sk_buff *segs, *nskb;
3953
3954         /* Estimate the number of fragments in the worst case */
3955         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
3956                 netif_stop_queue(tp->dev);
3957                 return NETDEV_TX_BUSY;
3958         }
3959
3960         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
3961         if (unlikely(IS_ERR(segs)))
3962                 goto tg3_tso_bug_end;
3963
3964         do {
3965                 nskb = segs;
3966                 segs = segs->next;
3967                 nskb->next = NULL;
3968                 tg3_start_xmit_dma_bug(nskb, tp->dev);
3969         } while (segs);
3970
3971 tg3_tso_bug_end:
3972         dev_kfree_skb(skb);
3973
3974         return NETDEV_TX_OK;
3975 }
3976 #endif
3977
3978 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
3979  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
3980  */
3981 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
3982 {
3983         struct tg3 *tp = netdev_priv(dev);
3984         dma_addr_t mapping;
3985         u32 len, entry, base_flags, mss;
3986         int would_hit_hwbug;
3987
3988         len = skb_headlen(skb);
3989
3990         /* We are running in BH disabled context with netif_tx_lock
3991          * and TX reclaim runs via tp->poll inside of a software
3992          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3993          * no IRQ context deadlocks to worry about either.  Rejoice!
3994          */
3995         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3996                 if (!netif_queue_stopped(dev)) {
3997                         netif_stop_queue(dev);
3998
3999                         /* This is a hard error, log it. */
4000                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4001                                "queue awake!\n", dev->name);
4002                 }
4003                 return NETDEV_TX_BUSY;
4004         }
4005
4006         entry = tp->tx_prod;
4007         base_flags = 0;
4008         if (skb->ip_summed == CHECKSUM_PARTIAL)
4009                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4010 #if TG3_TSO_SUPPORT != 0
4011         mss = 0;
4012         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
4013             (mss = skb_shinfo(skb)->gso_size) != 0) {
4014                 int tcp_opt_len, ip_tcp_len, hdr_len;
4015
4016                 if (skb_header_cloned(skb) &&
4017                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4018                         dev_kfree_skb(skb);
4019                         goto out_unlock;
4020                 }
4021
4022                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4023                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
4024
4025                 hdr_len = ip_tcp_len + tcp_opt_len;
4026                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4027                              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG))
4028                         return (tg3_tso_bug(tp, skb));
4029
4030                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4031                                TXD_FLAG_CPU_POST_DMA);
4032
4033                 skb->nh.iph->check = 0;
4034                 skb->nh.iph->tot_len = htons(mss + hdr_len);
4035                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4036                         skb->h.th->check = 0;
4037                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4038                 }
4039                 else {
4040                         skb->h.th->check =
4041                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4042                                                    skb->nh.iph->daddr,
4043                                                    0, IPPROTO_TCP, 0);
4044                 }
4045
4046                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4047                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4048                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4049                                 int tsflags;
4050
4051                                 tsflags = ((skb->nh.iph->ihl - 5) +
4052                                            (tcp_opt_len >> 2));
4053                                 mss |= (tsflags << 11);
4054                         }
4055                 } else {
4056                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4057                                 int tsflags;
4058
4059                                 tsflags = ((skb->nh.iph->ihl - 5) +
4060                                            (tcp_opt_len >> 2));
4061                                 base_flags |= tsflags << 12;
4062                         }
4063                 }
4064         }
4065 #else
4066         mss = 0;
4067 #endif
4068 #if TG3_VLAN_TAG_USED
4069         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4070                 base_flags |= (TXD_FLAG_VLAN |
4071                                (vlan_tx_tag_get(skb) << 16));
4072 #endif
4073
4074         /* Queue skb data, a.k.a. the main skb fragment. */
4075         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4076
4077         tp->tx_buffers[entry].skb = skb;
4078         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4079
4080         would_hit_hwbug = 0;
4081
4082         if (tg3_4g_overflow_test(mapping, len))
4083                 would_hit_hwbug = 1;
4084
4085         tg3_set_txd(tp, entry, mapping, len, base_flags,
4086                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4087
4088         entry = NEXT_TX(entry);
4089
4090         /* Now loop through additional data fragments, and queue them. */
4091         if (skb_shinfo(skb)->nr_frags > 0) {
4092                 unsigned int i, last;
4093
4094                 last = skb_shinfo(skb)->nr_frags - 1;
4095                 for (i = 0; i <= last; i++) {
4096                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4097
4098                         len = frag->size;
4099                         mapping = pci_map_page(tp->pdev,
4100                                                frag->page,
4101                                                frag->page_offset,
4102                                                len, PCI_DMA_TODEVICE);
4103
4104                         tp->tx_buffers[entry].skb = NULL;
4105                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4106
4107                         if (tg3_4g_overflow_test(mapping, len))
4108                                 would_hit_hwbug = 1;
4109
4110                         if (tg3_40bit_overflow_test(tp, mapping, len))
4111                                 would_hit_hwbug = 1;
4112
4113                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4114                                 tg3_set_txd(tp, entry, mapping, len,
4115                                             base_flags, (i == last)|(mss << 1));
4116                         else
4117                                 tg3_set_txd(tp, entry, mapping, len,
4118                                             base_flags, (i == last));
4119
4120                         entry = NEXT_TX(entry);
4121                 }
4122         }
4123
4124         if (would_hit_hwbug) {
4125                 u32 last_plus_one = entry;
4126                 u32 start;
4127
4128                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4129                 start &= (TG3_TX_RING_SIZE - 1);
4130
4131                 /* If the workaround fails due to memory/mapping
4132                  * failure, silently drop this packet.
4133                  */
4134                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4135                                                 &start, base_flags, mss))
4136                         goto out_unlock;
4137
4138                 entry = start;
4139         }
4140
4141         /* Packets are ready, update Tx producer idx local and on card. */
4142         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4143
4144         tp->tx_prod = entry;
4145         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4146                 netif_stop_queue(dev);
4147                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4148                         netif_wake_queue(tp->dev);
4149         }
4150
4151 out_unlock:
4152         mmiowb();
4153
4154         dev->trans_start = jiffies;
4155
4156         return NETDEV_TX_OK;
4157 }
4158
4159 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4160                                int new_mtu)
4161 {
4162         dev->mtu = new_mtu;
4163
4164         if (new_mtu > ETH_DATA_LEN) {
4165                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4166                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4167                         ethtool_op_set_tso(dev, 0);
4168                 }
4169                 else
4170                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4171         } else {
4172                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4173                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4174                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4175         }
4176 }
4177
4178 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4179 {
4180         struct tg3 *tp = netdev_priv(dev);
4181         int err;
4182
4183         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4184                 return -EINVAL;
4185
4186         if (!netif_running(dev)) {
4187                 /* We'll just catch it later when the
4188                  * device is up'd.
4189                  */
4190                 tg3_set_mtu(dev, tp, new_mtu);
4191                 return 0;
4192         }
4193
4194         tg3_netif_stop(tp);
4195
4196         tg3_full_lock(tp, 1);
4197
4198         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4199
4200         tg3_set_mtu(dev, tp, new_mtu);
4201
4202         err = tg3_restart_hw(tp, 0);
4203
4204         if (!err)
4205                 tg3_netif_start(tp);
4206
4207         tg3_full_unlock(tp);
4208
4209         return err;
4210 }
4211
4212 /* Free up pending packets in all rx/tx rings.
4213  *
4214  * The chip has been shut down and the driver detached from
4215  * the networking, so no interrupts or new tx packets will
4216  * end up in the driver.  tp->{tx,}lock is not held and we are not
4217  * in an interrupt context and thus may sleep.
4218  */
4219 static void tg3_free_rings(struct tg3 *tp)
4220 {
4221         struct ring_info *rxp;
4222         int i;
4223
4224         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4225                 rxp = &tp->rx_std_buffers[i];
4226
4227                 if (rxp->skb == NULL)
4228                         continue;
4229                 pci_unmap_single(tp->pdev,
4230                                  pci_unmap_addr(rxp, mapping),
4231                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4232                                  PCI_DMA_FROMDEVICE);
4233                 dev_kfree_skb_any(rxp->skb);
4234                 rxp->skb = NULL;
4235         }
4236
4237         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4238                 rxp = &tp->rx_jumbo_buffers[i];
4239
4240                 if (rxp->skb == NULL)
4241                         continue;
4242                 pci_unmap_single(tp->pdev,
4243                                  pci_unmap_addr(rxp, mapping),
4244                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4245                                  PCI_DMA_FROMDEVICE);
4246                 dev_kfree_skb_any(rxp->skb);
4247                 rxp->skb = NULL;
4248         }
4249
4250         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4251                 struct tx_ring_info *txp;
4252                 struct sk_buff *skb;
4253                 int j;
4254
4255                 txp = &tp->tx_buffers[i];
4256                 skb = txp->skb;
4257
4258                 if (skb == NULL) {
4259                         i++;
4260                         continue;
4261                 }
4262
4263                 pci_unmap_single(tp->pdev,
4264                                  pci_unmap_addr(txp, mapping),
4265                                  skb_headlen(skb),
4266                                  PCI_DMA_TODEVICE);
4267                 txp->skb = NULL;
4268
4269                 i++;
4270
4271                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4272                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4273                         pci_unmap_page(tp->pdev,
4274                                        pci_unmap_addr(txp, mapping),
4275                                        skb_shinfo(skb)->frags[j].size,
4276                                        PCI_DMA_TODEVICE);
4277                         i++;
4278                 }
4279
4280                 dev_kfree_skb_any(skb);
4281         }
4282 }
4283
4284 /* Initialize tx/rx rings for packet processing.
4285  *
4286  * The chip has been shut down and the driver detached from
4287  * the networking, so no interrupts or new tx packets will
4288  * end up in the driver.  tp->{tx,}lock are held and thus
4289  * we may not sleep.
4290  */
4291 static int tg3_init_rings(struct tg3 *tp)
4292 {
4293         u32 i;
4294
4295         /* Free up all the SKBs. */
4296         tg3_free_rings(tp);
4297
4298         /* Zero out all descriptors. */
4299         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4300         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4301         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4302         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4303
4304         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4305         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4306             (tp->dev->mtu > ETH_DATA_LEN))
4307                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4308
4309         /* Initialize invariants of the rings, we only set this
4310          * stuff once.  This works because the card does not
4311          * write into the rx buffer posting rings.
4312          */
4313         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4314                 struct tg3_rx_buffer_desc *rxd;
4315
4316                 rxd = &tp->rx_std[i];
4317                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4318                         << RXD_LEN_SHIFT;
4319                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4320                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4321                                (i << RXD_OPAQUE_INDEX_SHIFT));
4322         }
4323
4324         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4325                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4326                         struct tg3_rx_buffer_desc *rxd;
4327
4328                         rxd = &tp->rx_jumbo[i];
4329                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4330                                 << RXD_LEN_SHIFT;
4331                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4332                                 RXD_FLAG_JUMBO;
4333                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4334                                (i << RXD_OPAQUE_INDEX_SHIFT));
4335                 }
4336         }
4337
4338         /* Now allocate fresh SKBs for each rx ring. */
4339         for (i = 0; i < tp->rx_pending; i++) {
4340                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4341                         printk(KERN_WARNING PFX
4342                                "%s: Using a smaller RX standard ring, "
4343                                "only %d out of %d buffers were allocated "
4344                                "successfully.\n",
4345                                tp->dev->name, i, tp->rx_pending);
4346                         if (i == 0)
4347                                 return -ENOMEM;
4348                         tp->rx_pending = i;
4349                         break;
4350                 }
4351         }
4352
4353         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4354                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4355                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4356                                              -1, i) < 0) {
4357                                 printk(KERN_WARNING PFX
4358                                        "%s: Using a smaller RX jumbo ring, "
4359                                        "only %d out of %d buffers were "
4360                                        "allocated successfully.\n",
4361                                        tp->dev->name, i, tp->rx_jumbo_pending);
4362                                 if (i == 0) {
4363                                         tg3_free_rings(tp);
4364                                         return -ENOMEM;
4365                                 }
4366                                 tp->rx_jumbo_pending = i;
4367                                 break;
4368                         }
4369                 }
4370         }
4371         return 0;
4372 }
4373
4374 /*
4375  * Must not be invoked with interrupt sources disabled and
4376  * the hardware shutdown down.
4377  */
4378 static void tg3_free_consistent(struct tg3 *tp)
4379 {
4380         kfree(tp->rx_std_buffers);
4381         tp->rx_std_buffers = NULL;
4382         if (tp->rx_std) {
4383                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4384                                     tp->rx_std, tp->rx_std_mapping);
4385                 tp->rx_std = NULL;
4386         }
4387         if (tp->rx_jumbo) {
4388                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4389                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4390                 tp->rx_jumbo = NULL;
4391         }
4392         if (tp->rx_rcb) {
4393                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4394                                     tp->rx_rcb, tp->rx_rcb_mapping);
4395                 tp->rx_rcb = NULL;
4396         }
4397         if (tp->tx_ring) {
4398                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4399                         tp->tx_ring, tp->tx_desc_mapping);
4400                 tp->tx_ring = NULL;
4401         }
4402         if (tp->hw_status) {
4403                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4404                                     tp->hw_status, tp->status_mapping);
4405                 tp->hw_status = NULL;
4406         }
4407         if (tp->hw_stats) {
4408                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4409                                     tp->hw_stats, tp->stats_mapping);
4410                 tp->hw_stats = NULL;
4411         }
4412 }
4413
4414 /*
4415  * Must not be invoked with interrupt sources disabled and
4416  * the hardware shutdown down.  Can sleep.
4417  */
4418 static int tg3_alloc_consistent(struct tg3 *tp)
4419 {
4420         tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
4421                                       (TG3_RX_RING_SIZE +
4422                                        TG3_RX_JUMBO_RING_SIZE)) +
4423                                      (sizeof(struct tx_ring_info) *
4424                                       TG3_TX_RING_SIZE),
4425                                      GFP_KERNEL);
4426         if (!tp->rx_std_buffers)
4427                 return -ENOMEM;
4428
4429         memset(tp->rx_std_buffers, 0,
4430                (sizeof(struct ring_info) *
4431                 (TG3_RX_RING_SIZE +
4432                  TG3_RX_JUMBO_RING_SIZE)) +
4433                (sizeof(struct tx_ring_info) *
4434                 TG3_TX_RING_SIZE));
4435
4436         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4437         tp->tx_buffers = (struct tx_ring_info *)
4438                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4439
4440         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4441                                           &tp->rx_std_mapping);
4442         if (!tp->rx_std)
4443                 goto err_out;
4444
4445         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4446                                             &tp->rx_jumbo_mapping);
4447
4448         if (!tp->rx_jumbo)
4449                 goto err_out;
4450
4451         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4452                                           &tp->rx_rcb_mapping);
4453         if (!tp->rx_rcb)
4454                 goto err_out;
4455
4456         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4457                                            &tp->tx_desc_mapping);
4458         if (!tp->tx_ring)
4459                 goto err_out;
4460
4461         tp->hw_status = pci_alloc_consistent(tp->pdev,
4462                                              TG3_HW_STATUS_SIZE,
4463                                              &tp->status_mapping);
4464         if (!tp->hw_status)
4465                 goto err_out;
4466
4467         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4468                                             sizeof(struct tg3_hw_stats),
4469                                             &tp->stats_mapping);
4470         if (!tp->hw_stats)
4471                 goto err_out;
4472
4473         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4474         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4475
4476         return 0;
4477
4478 err_out:
4479         tg3_free_consistent(tp);
4480         return -ENOMEM;
4481 }
4482
4483 #define MAX_WAIT_CNT 1000
4484
4485 /* To stop a block, clear the enable bit and poll till it
4486  * clears.  tp->lock is held.
4487  */
4488 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4489 {
4490         unsigned int i;
4491         u32 val;
4492
4493         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4494                 switch (ofs) {
4495                 case RCVLSC_MODE:
4496                 case DMAC_MODE:
4497                 case MBFREE_MODE:
4498                 case BUFMGR_MODE:
4499                 case MEMARB_MODE:
4500                         /* We can't enable/disable these bits of the
4501                          * 5705/5750, just say success.
4502                          */
4503                         return 0;
4504
4505                 default:
4506                         break;
4507                 };
4508         }
4509
4510         val = tr32(ofs);
4511         val &= ~enable_bit;
4512         tw32_f(ofs, val);
4513
4514         for (i = 0; i < MAX_WAIT_CNT; i++) {
4515                 udelay(100);
4516                 val = tr32(ofs);
4517                 if ((val & enable_bit) == 0)
4518                         break;
4519         }
4520
4521         if (i == MAX_WAIT_CNT && !silent) {
4522                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4523                        "ofs=%lx enable_bit=%x\n",
4524                        ofs, enable_bit);
4525                 return -ENODEV;
4526         }
4527
4528         return 0;
4529 }
4530
4531 /* tp->lock is held. */
4532 static int tg3_abort_hw(struct tg3 *tp, int silent)
4533 {
4534         int i, err;
4535
4536         tg3_disable_ints(tp);
4537
4538         tp->rx_mode &= ~RX_MODE_ENABLE;
4539         tw32_f(MAC_RX_MODE, tp->rx_mode);
4540         udelay(10);
4541
4542         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4543         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4544         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4545         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4546         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4547         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4548
4549         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4550         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4551         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4552         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4553         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4554         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4555         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4556
4557         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4558         tw32_f(MAC_MODE, tp->mac_mode);
4559         udelay(40);
4560
4561         tp->tx_mode &= ~TX_MODE_ENABLE;
4562         tw32_f(MAC_TX_MODE, tp->tx_mode);
4563
4564         for (i = 0; i < MAX_WAIT_CNT; i++) {
4565                 udelay(100);
4566                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4567                         break;
4568         }
4569         if (i >= MAX_WAIT_CNT) {
4570                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4571                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4572                        tp->dev->name, tr32(MAC_TX_MODE));
4573                 err |= -ENODEV;
4574         }
4575
4576         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4577         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4578         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4579
4580         tw32(FTQ_RESET, 0xffffffff);
4581         tw32(FTQ_RESET, 0x00000000);
4582
4583         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4584         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4585
4586         if (tp->hw_status)
4587                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4588         if (tp->hw_stats)
4589                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4590
4591         return err;
4592 }
4593
4594 /* tp->lock is held. */
4595 static int tg3_nvram_lock(struct tg3 *tp)
4596 {
4597         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4598                 int i;
4599
4600                 if (tp->nvram_lock_cnt == 0) {
4601                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4602                         for (i = 0; i < 8000; i++) {
4603                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4604                                         break;
4605                                 udelay(20);
4606                         }
4607                         if (i == 8000) {
4608                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4609                                 return -ENODEV;
4610                         }
4611                 }
4612                 tp->nvram_lock_cnt++;
4613         }
4614         return 0;
4615 }
4616
4617 /* tp->lock is held. */
4618 static void tg3_nvram_unlock(struct tg3 *tp)
4619 {
4620         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4621                 if (tp->nvram_lock_cnt > 0)
4622                         tp->nvram_lock_cnt--;
4623                 if (tp->nvram_lock_cnt == 0)
4624                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4625         }
4626 }
4627
4628 /* tp->lock is held. */
4629 static void tg3_enable_nvram_access(struct tg3 *tp)
4630 {
4631         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4632             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4633                 u32 nvaccess = tr32(NVRAM_ACCESS);
4634
4635                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4636         }
4637 }
4638
4639 /* tp->lock is held. */
4640 static void tg3_disable_nvram_access(struct tg3 *tp)
4641 {
4642         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4643             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4644                 u32 nvaccess = tr32(NVRAM_ACCESS);
4645
4646                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4647         }
4648 }
4649
4650 /* tp->lock is held. */
4651 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4652 {
4653         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4654                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4655
4656         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4657                 switch (kind) {
4658                 case RESET_KIND_INIT:
4659                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4660                                       DRV_STATE_START);
4661                         break;
4662
4663                 case RESET_KIND_SHUTDOWN:
4664                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4665                                       DRV_STATE_UNLOAD);
4666                         break;
4667
4668                 case RESET_KIND_SUSPEND:
4669                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4670                                       DRV_STATE_SUSPEND);
4671                         break;
4672
4673                 default:
4674                         break;
4675                 };
4676         }
4677 }
4678
4679 /* tp->lock is held. */
4680 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4681 {
4682         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4683                 switch (kind) {
4684                 case RESET_KIND_INIT:
4685                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4686                                       DRV_STATE_START_DONE);
4687                         break;
4688
4689                 case RESET_KIND_SHUTDOWN:
4690                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4691                                       DRV_STATE_UNLOAD_DONE);
4692                         break;
4693
4694                 default:
4695                         break;
4696                 };
4697         }
4698 }
4699
4700 /* tp->lock is held. */
4701 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4702 {
4703         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4704                 switch (kind) {
4705                 case RESET_KIND_INIT:
4706                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4707                                       DRV_STATE_START);
4708                         break;
4709
4710                 case RESET_KIND_SHUTDOWN:
4711                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4712                                       DRV_STATE_UNLOAD);
4713                         break;
4714
4715                 case RESET_KIND_SUSPEND:
4716                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4717                                       DRV_STATE_SUSPEND);
4718                         break;
4719
4720                 default:
4721                         break;
4722                 };
4723         }
4724 }
4725
4726 static int tg3_poll_fw(struct tg3 *tp)
4727 {
4728         int i;
4729         u32 val;
4730
4731         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4732                 /* Wait up to 20ms for init done. */
4733                 for (i = 0; i < 200; i++) {
4734                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4735                                 return 0;
4736                         udelay(100);
4737                 }
4738                 return -ENODEV;
4739         }
4740
4741         /* Wait for firmware initialization to complete. */
4742         for (i = 0; i < 100000; i++) {
4743                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4744                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4745                         break;
4746                 udelay(10);
4747         }
4748
4749         /* Chip might not be fitted with firmware.  Some Sun onboard
4750          * parts are configured like that.  So don't signal the timeout
4751          * of the above loop as an error, but do report the lack of
4752          * running firmware once.
4753          */
4754         if (i >= 100000 &&
4755             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4756                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4757
4758                 printk(KERN_INFO PFX "%s: No firmware running.\n",
4759                        tp->dev->name);
4760         }
4761
4762         return 0;
4763 }
4764
4765 static void tg3_stop_fw(struct tg3 *);
4766
4767 /* tp->lock is held. */
4768 static int tg3_chip_reset(struct tg3 *tp)
4769 {
4770         u32 val;
4771         void (*write_op)(struct tg3 *, u32, u32);
4772         int err;
4773
4774         tg3_nvram_lock(tp);
4775
4776         /* No matching tg3_nvram_unlock() after this because
4777          * chip reset below will undo the nvram lock.
4778          */
4779         tp->nvram_lock_cnt = 0;
4780
4781         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4782             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4783             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4784                 tw32(GRC_FASTBOOT_PC, 0);
4785
4786         /*
4787          * We must avoid the readl() that normally takes place.
4788          * It locks machines, causes machine checks, and other
4789          * fun things.  So, temporarily disable the 5701
4790          * hardware workaround, while we do the reset.
4791          */
4792         write_op = tp->write32;
4793         if (write_op == tg3_write_flush_reg32)
4794                 tp->write32 = tg3_write32;
4795
4796         /* do the reset */
4797         val = GRC_MISC_CFG_CORECLK_RESET;
4798
4799         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4800                 if (tr32(0x7e2c) == 0x60) {
4801                         tw32(0x7e2c, 0x20);
4802                 }
4803                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4804                         tw32(GRC_MISC_CFG, (1 << 29));
4805                         val |= (1 << 29);
4806                 }
4807         }
4808
4809         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4810                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4811                 tw32(GRC_VCPU_EXT_CTRL,
4812                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4813         }
4814
4815         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4816                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4817         tw32(GRC_MISC_CFG, val);
4818
4819         /* restore 5701 hardware bug workaround write method */
4820         tp->write32 = write_op;
4821
4822         /* Unfortunately, we have to delay before the PCI read back.
4823          * Some 575X chips even will not respond to a PCI cfg access
4824          * when the reset command is given to the chip.
4825          *
4826          * How do these hardware designers expect things to work
4827          * properly if the PCI write is posted for a long period
4828          * of time?  It is always necessary to have some method by
4829          * which a register read back can occur to push the write
4830          * out which does the reset.
4831          *
4832          * For most tg3 variants the trick below was working.
4833          * Ho hum...
4834          */
4835         udelay(120);
4836
4837         /* Flush PCI posted writes.  The normal MMIO registers
4838          * are inaccessible at this time so this is the only
4839          * way to make this reliably (actually, this is no longer
4840          * the case, see above).  I tried to use indirect
4841          * register read/write but this upset some 5701 variants.
4842          */
4843         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4844
4845         udelay(120);
4846
4847         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4848                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4849                         int i;
4850                         u32 cfg_val;
4851
4852                         /* Wait for link training to complete.  */
4853                         for (i = 0; i < 5000; i++)
4854                                 udelay(100);
4855
4856                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4857                         pci_write_config_dword(tp->pdev, 0xc4,
4858                                                cfg_val | (1 << 15));
4859                 }
4860                 /* Set PCIE max payload size and clear error status.  */
4861                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4862         }
4863
4864         /* Re-enable indirect register accesses. */
4865         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4866                                tp->misc_host_ctrl);
4867
4868         /* Set MAX PCI retry to zero. */
4869         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4870         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4871             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4872                 val |= PCISTATE_RETRY_SAME_DMA;
4873         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4874
4875         pci_restore_state(tp->pdev);
4876
4877         /* Make sure PCI-X relaxed ordering bit is clear. */
4878         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4879         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4880         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4881
4882         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4883                 u32 val;
4884
4885                 /* Chip reset on 5780 will reset MSI enable bit,
4886                  * so need to restore it.
4887                  */
4888                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4889                         u16 ctrl;
4890
4891                         pci_read_config_word(tp->pdev,
4892                                              tp->msi_cap + PCI_MSI_FLAGS,
4893                                              &ctrl);
4894                         pci_write_config_word(tp->pdev,
4895                                               tp->msi_cap + PCI_MSI_FLAGS,
4896                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4897                         val = tr32(MSGINT_MODE);
4898                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4899                 }
4900
4901                 val = tr32(MEMARB_MODE);
4902                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4903
4904         } else
4905                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4906
4907         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4908                 tg3_stop_fw(tp);
4909                 tw32(0x5000, 0x400);
4910         }
4911
4912         tw32(GRC_MODE, tp->grc_mode);
4913
4914         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4915                 u32 val = tr32(0xc4);
4916
4917                 tw32(0xc4, val | (1 << 15));
4918         }
4919
4920         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4921             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4922                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4923                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4924                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4925                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4926         }
4927
4928         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4929                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4930                 tw32_f(MAC_MODE, tp->mac_mode);
4931         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4932                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4933                 tw32_f(MAC_MODE, tp->mac_mode);
4934         } else
4935                 tw32_f(MAC_MODE, 0);
4936         udelay(40);
4937
4938         err = tg3_poll_fw(tp);
4939         if (err)
4940                 return err;
4941
4942         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4943             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4944                 u32 val = tr32(0x7c00);
4945
4946                 tw32(0x7c00, val | (1 << 25));
4947         }
4948
4949         /* Reprobe ASF enable state.  */
4950         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4951         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4952         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4953         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4954                 u32 nic_cfg;
4955
4956                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4957                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4958                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4959                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4960                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4961                 }
4962         }
4963
4964         return 0;
4965 }
4966
4967 /* tp->lock is held. */
4968 static void tg3_stop_fw(struct tg3 *tp)
4969 {
4970         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4971                 u32 val;
4972                 int i;
4973
4974                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4975                 val = tr32(GRC_RX_CPU_EVENT);
4976                 val |= (1 << 14);
4977                 tw32(GRC_RX_CPU_EVENT, val);
4978
4979                 /* Wait for RX cpu to ACK the event.  */
4980                 for (i = 0; i < 100; i++) {
4981                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4982                                 break;
4983                         udelay(1);
4984                 }
4985         }
4986 }
4987
4988 /* tp->lock is held. */
4989 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4990 {
4991         int err;
4992
4993         tg3_stop_fw(tp);
4994
4995         tg3_write_sig_pre_reset(tp, kind);
4996
4997         tg3_abort_hw(tp, silent);
4998         err = tg3_chip_reset(tp);
4999
5000         tg3_write_sig_legacy(tp, kind);
5001         tg3_write_sig_post_reset(tp, kind);
5002
5003         if (err)
5004                 return err;
5005
5006         return 0;
5007 }
5008
5009 #define TG3_FW_RELEASE_MAJOR    0x0
5010 #define TG3_FW_RELASE_MINOR     0x0
5011 #define TG3_FW_RELEASE_FIX      0x0
5012 #define TG3_FW_START_ADDR       0x08000000
5013 #define TG3_FW_TEXT_ADDR        0x08000000
5014 #define TG3_FW_TEXT_LEN         0x9c0
5015 #define TG3_FW_RODATA_ADDR      0x080009c0
5016 #define TG3_FW_RODATA_LEN       0x60
5017 #define TG3_FW_DATA_ADDR        0x08000a40
5018 #define TG3_FW_DATA_LEN         0x20
5019 #define TG3_FW_SBSS_ADDR        0x08000a60
5020 #define TG3_FW_SBSS_LEN         0xc
5021 #define TG3_FW_BSS_ADDR         0x08000a70
5022 #define TG3_FW_BSS_LEN          0x10
5023
5024 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5025         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5026         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5027         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5028         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5029         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5030         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5031         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5032         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5033         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5034         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5035         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5036         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5037         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5038         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5039         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5040         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5041         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5042         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5043         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5044         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5045         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5046         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5047         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5048         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5049         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5050         0, 0, 0, 0, 0, 0,
5051         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5052         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5053         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5054         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5055         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5056         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5057         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5058         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5059         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5060         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5061         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5062         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5063         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5064         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5065         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5066         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5067         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5068         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5069         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5070         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5071         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5072         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5073         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5074         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5075         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5076         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5077         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5078         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5079         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5080         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5081         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5082         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5083         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5084         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5085         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5086         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5087         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5088         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5089         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5090         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5091         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5092         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5093         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5094         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5095         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5096         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5097         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5098         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5099         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5100         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5101         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5102         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5103         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5104         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5105         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5106         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5107         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5108         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5109         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5110         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5111         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5112         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5113         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5114         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5115         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5116 };
5117
5118 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5119         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5120         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5121         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5122         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5123         0x00000000
5124 };
5125
5126 #if 0 /* All zeros, don't eat up space with it. */
5127 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5128         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5129         0x00000000, 0x00000000, 0x00000000, 0x00000000
5130 };
5131 #endif
5132
5133 #define RX_CPU_SCRATCH_BASE     0x30000
5134 #define RX_CPU_SCRATCH_SIZE     0x04000
5135 #define TX_CPU_SCRATCH_BASE     0x34000
5136 #define TX_CPU_SCRATCH_SIZE     0x04000
5137
5138 /* tp->lock is held. */
5139 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5140 {
5141         int i;
5142
5143         BUG_ON(offset == TX_CPU_BASE &&
5144             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5145
5146         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5147                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5148
5149                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5150                 return 0;
5151         }
5152         if (offset == RX_CPU_BASE) {
5153                 for (i = 0; i < 10000; i++) {
5154                         tw32(offset + CPU_STATE, 0xffffffff);
5155                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5156                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5157                                 break;
5158                 }
5159
5160                 tw32(offset + CPU_STATE, 0xffffffff);
5161                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5162                 udelay(10);
5163         } else {
5164                 for (i = 0; i < 10000; i++) {
5165                         tw32(offset + CPU_STATE, 0xffffffff);
5166                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5167                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5168                                 break;
5169                 }
5170         }
5171
5172         if (i >= 10000) {
5173                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5174                        "and %s CPU\n",
5175                        tp->dev->name,
5176                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5177                 return -ENODEV;
5178         }
5179
5180         /* Clear firmware's nvram arbitration. */
5181         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5182                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5183         return 0;
5184 }
5185
5186 struct fw_info {
5187         unsigned int text_base;
5188         unsigned int text_len;
5189         const u32 *text_data;
5190         unsigned int rodata_base;
5191         unsigned int rodata_len;
5192         const u32 *rodata_data;
5193         unsigned int data_base;
5194         unsigned int data_len;
5195         const u32 *data_data;
5196 };
5197
5198 /* tp->lock is held. */
5199 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5200                                  int cpu_scratch_size, struct fw_info *info)
5201 {
5202         int err, lock_err, i;
5203         void (*write_op)(struct tg3 *, u32, u32);
5204
5205         if (cpu_base == TX_CPU_BASE &&
5206             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5207                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5208                        "TX cpu firmware on %s which is 5705.\n",
5209                        tp->dev->name);
5210                 return -EINVAL;
5211         }
5212
5213         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5214                 write_op = tg3_write_mem;
5215         else
5216                 write_op = tg3_write_indirect_reg32;
5217
5218         /* It is possible that bootcode is still loading at this point.
5219          * Get the nvram lock first before halting the cpu.
5220          */
5221         lock_err = tg3_nvram_lock(tp);
5222         err = tg3_halt_cpu(tp, cpu_base);
5223         if (!lock_err)
5224                 tg3_nvram_unlock(tp);
5225         if (err)
5226                 goto out;
5227
5228         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5229                 write_op(tp, cpu_scratch_base + i, 0);
5230         tw32(cpu_base + CPU_STATE, 0xffffffff);
5231         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5232         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5233                 write_op(tp, (cpu_scratch_base +
5234                               (info->text_base & 0xffff) +
5235                               (i * sizeof(u32))),
5236                          (info->text_data ?
5237                           info->text_data[i] : 0));
5238         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5239                 write_op(tp, (cpu_scratch_base +
5240                               (info->rodata_base & 0xffff) +
5241                               (i * sizeof(u32))),
5242                          (info->rodata_data ?
5243                           info->rodata_data[i] : 0));
5244         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5245                 write_op(tp, (cpu_scratch_base +
5246                               (info->data_base & 0xffff) +
5247                               (i * sizeof(u32))),
5248                          (info->data_data ?
5249                           info->data_data[i] : 0));
5250
5251         err = 0;
5252
5253 out:
5254         return err;
5255 }
5256
5257 /* tp->lock is held. */
5258 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5259 {
5260         struct fw_info info;
5261         int err, i;
5262
5263         info.text_base = TG3_FW_TEXT_ADDR;
5264         info.text_len = TG3_FW_TEXT_LEN;
5265         info.text_data = &tg3FwText[0];
5266         info.rodata_base = TG3_FW_RODATA_ADDR;
5267         info.rodata_len = TG3_FW_RODATA_LEN;
5268         info.rodata_data = &tg3FwRodata[0];
5269         info.data_base = TG3_FW_DATA_ADDR;
5270         info.data_len = TG3_FW_DATA_LEN;
5271         info.data_data = NULL;
5272
5273         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5274                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5275                                     &info);
5276         if (err)
5277                 return err;
5278
5279         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5280                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5281                                     &info);
5282         if (err)
5283                 return err;
5284
5285         /* Now startup only the RX cpu. */
5286         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5287         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5288
5289         for (i = 0; i < 5; i++) {
5290                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5291                         break;
5292                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5293                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5294                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5295                 udelay(1000);
5296         }
5297         if (i >= 5) {
5298                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5299                        "to set RX CPU PC, is %08x should be %08x\n",
5300                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5301                        TG3_FW_TEXT_ADDR);
5302                 return -ENODEV;
5303         }
5304         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5305         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5306
5307         return 0;
5308 }
5309
5310 #if TG3_TSO_SUPPORT != 0
5311
5312 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5313 #define TG3_TSO_FW_RELASE_MINOR         0x6
5314 #define TG3_TSO_FW_RELEASE_FIX          0x0
5315 #define TG3_TSO_FW_START_ADDR           0x08000000
5316 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5317 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5318 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5319 #define TG3_TSO_FW_RODATA_LEN           0x60
5320 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5321 #define TG3_TSO_FW_DATA_LEN             0x30
5322 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5323 #define TG3_TSO_FW_SBSS_LEN             0x2c
5324 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5325 #define TG3_TSO_FW_BSS_LEN              0x894
5326
5327 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5328         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5329         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5330         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5331         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5332         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5333         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5334         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5335         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5336         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5337         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5338         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5339         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5340         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5341         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5342         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5343         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5344         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5345         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5346         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5347         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5348         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5349         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5350         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5351         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5352         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5353         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5354         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5355         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5356         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5357         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5358         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5359         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5360         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5361         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5362         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5363         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5364         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5365         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5366         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5367         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5368         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5369         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5370         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5371         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5372         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5373         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5374         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5375         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5376         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5377         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5378         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5379         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5380         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5381         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5382         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5383         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5384         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5385         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5386         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5387         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5388         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5389         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5390         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5391         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5392         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5393         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5394         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5395         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5396         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5397         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5398         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5399         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5400         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5401         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5402         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5403         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5404         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5405         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5406         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5407         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5408         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5409         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5410         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5411         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5412         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5413         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5414         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5415         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5416         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5417         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5418         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5419         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5420         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5421         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5422         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5423         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5424         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5425         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5426         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5427         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5428         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5429         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5430         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5431         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5432         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5433         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5434         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5435         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5436         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5437         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5438         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5439         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5440         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5441         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5442         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5443         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5444         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5445         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5446         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5447         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5448         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5449         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5450         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5451         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5452         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5453         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5454         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5455         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5456         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5457         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5458         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5459         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5460         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5461         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5462         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5463         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5464         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5465         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5466         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5467         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5468         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5469         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5470         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5471         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5472         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5473         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5474         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5475         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5476         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5477         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5478         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5479         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5480         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5481         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5482         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5483         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5484         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5485         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5486         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5487         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5488         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5489         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5490         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5491         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5492         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5493         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5494         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5495         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5496         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5497         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5498         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5499         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5500         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5501         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5502         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5503         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5504         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5505         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5506         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5507         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5508         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5509         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5510         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5511         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5512         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5513         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5514         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5515         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5516         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5517         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5518         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5519         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5520         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5521         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5522         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5523         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5524         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5525         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5526         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5527         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5528         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5529         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5530         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5531         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5532         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5533         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5534         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5535         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5536         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5537         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5538         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5539         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5540         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5541         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5542         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5543         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5544         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5545         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5546         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5547         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5548         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5549         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5550         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5551         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5552         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5553         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5554         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5555         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5556         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5557         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5558         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5559         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5560         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5561         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5562         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5563         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5564         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5565         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5566         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5567         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5568         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5569         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5570         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5571         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5572         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5573         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5574         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5575         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5576         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5577         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5578         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5579         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5580         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5581         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5582         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5583         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5584         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5585         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5586         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5587         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5588         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5589         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5590         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5591         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5592         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5593         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5594         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5595         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5596         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5597         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5598         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5599         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5600         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5601         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5602         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5603         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5604         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5605         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5606         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5607         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5608         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5609         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5610         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5611         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5612 };
5613
5614 static const u32 tg3TsoFwRodata[] = {
5615         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5616         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5617         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5618         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5619         0x00000000,
5620 };
5621
5622 static const u32 tg3TsoFwData[] = {
5623         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5624         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5625         0x00000000,
5626 };
5627
5628 /* 5705 needs a special version of the TSO firmware.  */
5629 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5630 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5631 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5632 #define TG3_TSO5_FW_START_ADDR          0x00010000
5633 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5634 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5635 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5636 #define TG3_TSO5_FW_RODATA_LEN          0x50
5637 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5638 #define TG3_TSO5_FW_DATA_LEN            0x20
5639 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5640 #define TG3_TSO5_FW_SBSS_LEN            0x28
5641 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5642 #define TG3_TSO5_FW_BSS_LEN             0x88
5643
5644 static const&n