[TG3]: Fix suspend/resume problem.
[linux-3.10.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2007 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40 #include <linux/dma-mapping.h>
41
42 #include <net/checksum.h>
43 #include <net/ip.h>
44
45 #include <asm/system.h>
46 #include <asm/io.h>
47 #include <asm/byteorder.h>
48 #include <asm/uaccess.h>
49
50 #ifdef CONFIG_SPARC
51 #include <asm/idprom.h>
52 #include <asm/prom.h>
53 #endif
54
55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56 #define TG3_VLAN_TAG_USED 1
57 #else
58 #define TG3_VLAN_TAG_USED 0
59 #endif
60
61 #define TG3_TSO_SUPPORT 1
62
63 #include "tg3.h"
64
65 #define DRV_MODULE_NAME         "tg3"
66 #define PFX DRV_MODULE_NAME     ": "
67 #define DRV_MODULE_VERSION      "3.80"
68 #define DRV_MODULE_RELDATE      "August 2, 2007"
69
70 #define TG3_DEF_MAC_MODE        0
71 #define TG3_DEF_RX_MODE         0
72 #define TG3_DEF_TX_MODE         0
73 #define TG3_DEF_MSG_ENABLE        \
74         (NETIF_MSG_DRV          | \
75          NETIF_MSG_PROBE        | \
76          NETIF_MSG_LINK         | \
77          NETIF_MSG_TIMER        | \
78          NETIF_MSG_IFDOWN       | \
79          NETIF_MSG_IFUP         | \
80          NETIF_MSG_RX_ERR       | \
81          NETIF_MSG_TX_ERR)
82
83 /* length of time before we decide the hardware is borked,
84  * and dev->tx_timeout() should be called to fix the problem
85  */
86 #define TG3_TX_TIMEOUT                  (5 * HZ)
87
88 /* hardware minimum and maximum for a single frame's data payload */
89 #define TG3_MIN_MTU                     60
90 #define TG3_MAX_MTU(tp) \
91         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
92
93 /* These numbers seem to be hard coded in the NIC firmware somehow.
94  * You can't change the ring sizes, but you can change where you place
95  * them in the NIC onboard memory.
96  */
97 #define TG3_RX_RING_SIZE                512
98 #define TG3_DEF_RX_RING_PENDING         200
99 #define TG3_RX_JUMBO_RING_SIZE          256
100 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
101
102 /* Do not place this n-ring entries value into the tp struct itself,
103  * we really want to expose these constants to GCC so that modulo et
104  * al.  operations are done with shifts and masks instead of with
105  * hw multiply/modulo instructions.  Another solution would be to
106  * replace things like '% foo' with '& (foo - 1)'.
107  */
108 #define TG3_RX_RCB_RING_SIZE(tp)        \
109         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
110
111 #define TG3_TX_RING_SIZE                512
112 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
113
114 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
115                                  TG3_RX_RING_SIZE)
116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117                                  TG3_RX_JUMBO_RING_SIZE)
118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119                                    TG3_RX_RCB_RING_SIZE(tp))
120 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
121                                  TG3_TX_RING_SIZE)
122 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
123
124 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
125 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
126
127 /* minimum number of free TX descriptors required to wake up TX process */
128 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
129
130 /* number of ETHTOOL_GSTATS u64's */
131 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
132
133 #define TG3_NUM_TEST            6
134
135 static char version[] __devinitdata =
136         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
137
138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_MODULE_VERSION);
142
143 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
144 module_param(tg3_debug, int, 0);
145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
146
147 static struct pci_device_id tg3_pci_tbl[] = {
148         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
201         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
202         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
203         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
204         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
205         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
206         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
207         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
208         {}
209 };
210
211 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
212
213 static const struct {
214         const char string[ETH_GSTRING_LEN];
215 } ethtool_stats_keys[TG3_NUM_STATS] = {
216         { "rx_octets" },
217         { "rx_fragments" },
218         { "rx_ucast_packets" },
219         { "rx_mcast_packets" },
220         { "rx_bcast_packets" },
221         { "rx_fcs_errors" },
222         { "rx_align_errors" },
223         { "rx_xon_pause_rcvd" },
224         { "rx_xoff_pause_rcvd" },
225         { "rx_mac_ctrl_rcvd" },
226         { "rx_xoff_entered" },
227         { "rx_frame_too_long_errors" },
228         { "rx_jabbers" },
229         { "rx_undersize_packets" },
230         { "rx_in_length_errors" },
231         { "rx_out_length_errors" },
232         { "rx_64_or_less_octet_packets" },
233         { "rx_65_to_127_octet_packets" },
234         { "rx_128_to_255_octet_packets" },
235         { "rx_256_to_511_octet_packets" },
236         { "rx_512_to_1023_octet_packets" },
237         { "rx_1024_to_1522_octet_packets" },
238         { "rx_1523_to_2047_octet_packets" },
239         { "rx_2048_to_4095_octet_packets" },
240         { "rx_4096_to_8191_octet_packets" },
241         { "rx_8192_to_9022_octet_packets" },
242
243         { "tx_octets" },
244         { "tx_collisions" },
245
246         { "tx_xon_sent" },
247         { "tx_xoff_sent" },
248         { "tx_flow_control" },
249         { "tx_mac_errors" },
250         { "tx_single_collisions" },
251         { "tx_mult_collisions" },
252         { "tx_deferred" },
253         { "tx_excessive_collisions" },
254         { "tx_late_collisions" },
255         { "tx_collide_2times" },
256         { "tx_collide_3times" },
257         { "tx_collide_4times" },
258         { "tx_collide_5times" },
259         { "tx_collide_6times" },
260         { "tx_collide_7times" },
261         { "tx_collide_8times" },
262         { "tx_collide_9times" },
263         { "tx_collide_10times" },
264         { "tx_collide_11times" },
265         { "tx_collide_12times" },
266         { "tx_collide_13times" },
267         { "tx_collide_14times" },
268         { "tx_collide_15times" },
269         { "tx_ucast_packets" },
270         { "tx_mcast_packets" },
271         { "tx_bcast_packets" },
272         { "tx_carrier_sense_errors" },
273         { "tx_discards" },
274         { "tx_errors" },
275
276         { "dma_writeq_full" },
277         { "dma_write_prioq_full" },
278         { "rxbds_empty" },
279         { "rx_discards" },
280         { "rx_errors" },
281         { "rx_threshold_hit" },
282
283         { "dma_readq_full" },
284         { "dma_read_prioq_full" },
285         { "tx_comp_queue_full" },
286
287         { "ring_set_send_prod_index" },
288         { "ring_status_update" },
289         { "nic_irqs" },
290         { "nic_avoided_irqs" },
291         { "nic_tx_threshold_hit" }
292 };
293
294 static const struct {
295         const char string[ETH_GSTRING_LEN];
296 } ethtool_test_keys[TG3_NUM_TEST] = {
297         { "nvram test     (online) " },
298         { "link test      (online) " },
299         { "register test  (offline)" },
300         { "memory test    (offline)" },
301         { "loopback test  (offline)" },
302         { "interrupt test (offline)" },
303 };
304
305 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
306 {
307         writel(val, tp->regs + off);
308 }
309
310 static u32 tg3_read32(struct tg3 *tp, u32 off)
311 {
312         return (readl(tp->regs + off));
313 }
314
315 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
316 {
317         unsigned long flags;
318
319         spin_lock_irqsave(&tp->indirect_lock, flags);
320         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
321         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
322         spin_unlock_irqrestore(&tp->indirect_lock, flags);
323 }
324
325 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
326 {
327         writel(val, tp->regs + off);
328         readl(tp->regs + off);
329 }
330
331 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
332 {
333         unsigned long flags;
334         u32 val;
335
336         spin_lock_irqsave(&tp->indirect_lock, flags);
337         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
338         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
339         spin_unlock_irqrestore(&tp->indirect_lock, flags);
340         return val;
341 }
342
343 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
344 {
345         unsigned long flags;
346
347         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
348                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
349                                        TG3_64BIT_REG_LOW, val);
350                 return;
351         }
352         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
353                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
354                                        TG3_64BIT_REG_LOW, val);
355                 return;
356         }
357
358         spin_lock_irqsave(&tp->indirect_lock, flags);
359         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
360         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
361         spin_unlock_irqrestore(&tp->indirect_lock, flags);
362
363         /* In indirect mode when disabling interrupts, we also need
364          * to clear the interrupt bit in the GRC local ctrl register.
365          */
366         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
367             (val == 0x1)) {
368                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
369                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
370         }
371 }
372
373 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
374 {
375         unsigned long flags;
376         u32 val;
377
378         spin_lock_irqsave(&tp->indirect_lock, flags);
379         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
380         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
381         spin_unlock_irqrestore(&tp->indirect_lock, flags);
382         return val;
383 }
384
385 /* usec_wait specifies the wait time in usec when writing to certain registers
386  * where it is unsafe to read back the register without some delay.
387  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
388  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
389  */
390 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
391 {
392         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
393             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
394                 /* Non-posted methods */
395                 tp->write32(tp, off, val);
396         else {
397                 /* Posted method */
398                 tg3_write32(tp, off, val);
399                 if (usec_wait)
400                         udelay(usec_wait);
401                 tp->read32(tp, off);
402         }
403         /* Wait again after the read for the posted method to guarantee that
404          * the wait time is met.
405          */
406         if (usec_wait)
407                 udelay(usec_wait);
408 }
409
410 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
411 {
412         tp->write32_mbox(tp, off, val);
413         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
414             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
415                 tp->read32_mbox(tp, off);
416 }
417
418 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
419 {
420         void __iomem *mbox = tp->regs + off;
421         writel(val, mbox);
422         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
423                 writel(val, mbox);
424         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
425                 readl(mbox);
426 }
427
428 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
429 {
430         return (readl(tp->regs + off + GRCMBOX_BASE));
431 }
432
433 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
434 {
435         writel(val, tp->regs + off + GRCMBOX_BASE);
436 }
437
438 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
439 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
440 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
441 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
442 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
443
444 #define tw32(reg,val)           tp->write32(tp, reg, val)
445 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
446 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
447 #define tr32(reg)               tp->read32(tp, reg)
448
449 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
450 {
451         unsigned long flags;
452
453         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
454             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
455                 return;
456
457         spin_lock_irqsave(&tp->indirect_lock, flags);
458         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
459                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
460                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
461
462                 /* Always leave this as zero. */
463                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
464         } else {
465                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
466                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
467
468                 /* Always leave this as zero. */
469                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
470         }
471         spin_unlock_irqrestore(&tp->indirect_lock, flags);
472 }
473
474 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
475 {
476         unsigned long flags;
477
478         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
479             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
480                 *val = 0;
481                 return;
482         }
483
484         spin_lock_irqsave(&tp->indirect_lock, flags);
485         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
486                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
487                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
488
489                 /* Always leave this as zero. */
490                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
491         } else {
492                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
493                 *val = tr32(TG3PCI_MEM_WIN_DATA);
494
495                 /* Always leave this as zero. */
496                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
497         }
498         spin_unlock_irqrestore(&tp->indirect_lock, flags);
499 }
500
501 static void tg3_disable_ints(struct tg3 *tp)
502 {
503         tw32(TG3PCI_MISC_HOST_CTRL,
504              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
505         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
506 }
507
508 static inline void tg3_cond_int(struct tg3 *tp)
509 {
510         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
511             (tp->hw_status->status & SD_STATUS_UPDATED))
512                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
513         else
514                 tw32(HOSTCC_MODE, tp->coalesce_mode |
515                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
516 }
517
518 static void tg3_enable_ints(struct tg3 *tp)
519 {
520         tp->irq_sync = 0;
521         wmb();
522
523         tw32(TG3PCI_MISC_HOST_CTRL,
524              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
525         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
526                        (tp->last_tag << 24));
527         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
528                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
529                                (tp->last_tag << 24));
530         tg3_cond_int(tp);
531 }
532
533 static inline unsigned int tg3_has_work(struct tg3 *tp)
534 {
535         struct tg3_hw_status *sblk = tp->hw_status;
536         unsigned int work_exists = 0;
537
538         /* check for phy events */
539         if (!(tp->tg3_flags &
540               (TG3_FLAG_USE_LINKCHG_REG |
541                TG3_FLAG_POLL_SERDES))) {
542                 if (sblk->status & SD_STATUS_LINK_CHG)
543                         work_exists = 1;
544         }
545         /* check for RX/TX work to do */
546         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
547             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
548                 work_exists = 1;
549
550         return work_exists;
551 }
552
553 /* tg3_restart_ints
554  *  similar to tg3_enable_ints, but it accurately determines whether there
555  *  is new work pending and can return without flushing the PIO write
556  *  which reenables interrupts
557  */
558 static void tg3_restart_ints(struct tg3 *tp)
559 {
560         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
561                      tp->last_tag << 24);
562         mmiowb();
563
564         /* When doing tagged status, this work check is unnecessary.
565          * The last_tag we write above tells the chip which piece of
566          * work we've completed.
567          */
568         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
569             tg3_has_work(tp))
570                 tw32(HOSTCC_MODE, tp->coalesce_mode |
571                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
572 }
573
574 static inline void tg3_netif_stop(struct tg3 *tp)
575 {
576         tp->dev->trans_start = jiffies; /* prevent tx timeout */
577         netif_poll_disable(tp->dev);
578         netif_tx_disable(tp->dev);
579 }
580
581 static inline void tg3_netif_start(struct tg3 *tp)
582 {
583         netif_wake_queue(tp->dev);
584         /* NOTE: unconditional netif_wake_queue is only appropriate
585          * so long as all callers are assured to have free tx slots
586          * (such as after tg3_init_hw)
587          */
588         netif_poll_enable(tp->dev);
589         tp->hw_status->status |= SD_STATUS_UPDATED;
590         tg3_enable_ints(tp);
591 }
592
593 static void tg3_switch_clocks(struct tg3 *tp)
594 {
595         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
596         u32 orig_clock_ctrl;
597
598         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
599                 return;
600
601         orig_clock_ctrl = clock_ctrl;
602         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
603                        CLOCK_CTRL_CLKRUN_OENABLE |
604                        0x1f);
605         tp->pci_clock_ctrl = clock_ctrl;
606
607         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
608                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
609                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
610                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
611                 }
612         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
613                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
614                             clock_ctrl |
615                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
616                             40);
617                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
618                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
619                             40);
620         }
621         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
622 }
623
624 #define PHY_BUSY_LOOPS  5000
625
626 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
627 {
628         u32 frame_val;
629         unsigned int loops;
630         int ret;
631
632         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
633                 tw32_f(MAC_MI_MODE,
634                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
635                 udelay(80);
636         }
637
638         *val = 0x0;
639
640         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
641                       MI_COM_PHY_ADDR_MASK);
642         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
643                       MI_COM_REG_ADDR_MASK);
644         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
645
646         tw32_f(MAC_MI_COM, frame_val);
647
648         loops = PHY_BUSY_LOOPS;
649         while (loops != 0) {
650                 udelay(10);
651                 frame_val = tr32(MAC_MI_COM);
652
653                 if ((frame_val & MI_COM_BUSY) == 0) {
654                         udelay(5);
655                         frame_val = tr32(MAC_MI_COM);
656                         break;
657                 }
658                 loops -= 1;
659         }
660
661         ret = -EBUSY;
662         if (loops != 0) {
663                 *val = frame_val & MI_COM_DATA_MASK;
664                 ret = 0;
665         }
666
667         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
668                 tw32_f(MAC_MI_MODE, tp->mi_mode);
669                 udelay(80);
670         }
671
672         return ret;
673 }
674
675 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
676 {
677         u32 frame_val;
678         unsigned int loops;
679         int ret;
680
681         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
682             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
683                 return 0;
684
685         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
686                 tw32_f(MAC_MI_MODE,
687                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
688                 udelay(80);
689         }
690
691         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
692                       MI_COM_PHY_ADDR_MASK);
693         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
694                       MI_COM_REG_ADDR_MASK);
695         frame_val |= (val & MI_COM_DATA_MASK);
696         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
697
698         tw32_f(MAC_MI_COM, frame_val);
699
700         loops = PHY_BUSY_LOOPS;
701         while (loops != 0) {
702                 udelay(10);
703                 frame_val = tr32(MAC_MI_COM);
704                 if ((frame_val & MI_COM_BUSY) == 0) {
705                         udelay(5);
706                         frame_val = tr32(MAC_MI_COM);
707                         break;
708                 }
709                 loops -= 1;
710         }
711
712         ret = -EBUSY;
713         if (loops != 0)
714                 ret = 0;
715
716         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
717                 tw32_f(MAC_MI_MODE, tp->mi_mode);
718                 udelay(80);
719         }
720
721         return ret;
722 }
723
724 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
725 {
726         u32 phy;
727
728         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
729             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
730                 return;
731
732         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
733                 u32 ephy;
734
735                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
736                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
737                                      ephy | MII_TG3_EPHY_SHADOW_EN);
738                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
739                                 if (enable)
740                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
741                                 else
742                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
743                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
744                         }
745                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
746                 }
747         } else {
748                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
749                       MII_TG3_AUXCTL_SHDWSEL_MISC;
750                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
751                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
752                         if (enable)
753                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
754                         else
755                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
756                         phy |= MII_TG3_AUXCTL_MISC_WREN;
757                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
758                 }
759         }
760 }
761
762 static void tg3_phy_set_wirespeed(struct tg3 *tp)
763 {
764         u32 val;
765
766         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
767                 return;
768
769         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
770             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
771                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
772                              (val | (1 << 15) | (1 << 4)));
773 }
774
775 static int tg3_bmcr_reset(struct tg3 *tp)
776 {
777         u32 phy_control;
778         int limit, err;
779
780         /* OK, reset it, and poll the BMCR_RESET bit until it
781          * clears or we time out.
782          */
783         phy_control = BMCR_RESET;
784         err = tg3_writephy(tp, MII_BMCR, phy_control);
785         if (err != 0)
786                 return -EBUSY;
787
788         limit = 5000;
789         while (limit--) {
790                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
791                 if (err != 0)
792                         return -EBUSY;
793
794                 if ((phy_control & BMCR_RESET) == 0) {
795                         udelay(40);
796                         break;
797                 }
798                 udelay(10);
799         }
800         if (limit <= 0)
801                 return -EBUSY;
802
803         return 0;
804 }
805
806 static int tg3_wait_macro_done(struct tg3 *tp)
807 {
808         int limit = 100;
809
810         while (limit--) {
811                 u32 tmp32;
812
813                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
814                         if ((tmp32 & 0x1000) == 0)
815                                 break;
816                 }
817         }
818         if (limit <= 0)
819                 return -EBUSY;
820
821         return 0;
822 }
823
824 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
825 {
826         static const u32 test_pat[4][6] = {
827         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
828         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
829         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
830         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
831         };
832         int chan;
833
834         for (chan = 0; chan < 4; chan++) {
835                 int i;
836
837                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
838                              (chan * 0x2000) | 0x0200);
839                 tg3_writephy(tp, 0x16, 0x0002);
840
841                 for (i = 0; i < 6; i++)
842                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
843                                      test_pat[chan][i]);
844
845                 tg3_writephy(tp, 0x16, 0x0202);
846                 if (tg3_wait_macro_done(tp)) {
847                         *resetp = 1;
848                         return -EBUSY;
849                 }
850
851                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
852                              (chan * 0x2000) | 0x0200);
853                 tg3_writephy(tp, 0x16, 0x0082);
854                 if (tg3_wait_macro_done(tp)) {
855                         *resetp = 1;
856                         return -EBUSY;
857                 }
858
859                 tg3_writephy(tp, 0x16, 0x0802);
860                 if (tg3_wait_macro_done(tp)) {
861                         *resetp = 1;
862                         return -EBUSY;
863                 }
864
865                 for (i = 0; i < 6; i += 2) {
866                         u32 low, high;
867
868                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
869                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
870                             tg3_wait_macro_done(tp)) {
871                                 *resetp = 1;
872                                 return -EBUSY;
873                         }
874                         low &= 0x7fff;
875                         high &= 0x000f;
876                         if (low != test_pat[chan][i] ||
877                             high != test_pat[chan][i+1]) {
878                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
879                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
880                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
881
882                                 return -EBUSY;
883                         }
884                 }
885         }
886
887         return 0;
888 }
889
890 static int tg3_phy_reset_chanpat(struct tg3 *tp)
891 {
892         int chan;
893
894         for (chan = 0; chan < 4; chan++) {
895                 int i;
896
897                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
898                              (chan * 0x2000) | 0x0200);
899                 tg3_writephy(tp, 0x16, 0x0002);
900                 for (i = 0; i < 6; i++)
901                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
902                 tg3_writephy(tp, 0x16, 0x0202);
903                 if (tg3_wait_macro_done(tp))
904                         return -EBUSY;
905         }
906
907         return 0;
908 }
909
910 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
911 {
912         u32 reg32, phy9_orig;
913         int retries, do_phy_reset, err;
914
915         retries = 10;
916         do_phy_reset = 1;
917         do {
918                 if (do_phy_reset) {
919                         err = tg3_bmcr_reset(tp);
920                         if (err)
921                                 return err;
922                         do_phy_reset = 0;
923                 }
924
925                 /* Disable transmitter and interrupt.  */
926                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
927                         continue;
928
929                 reg32 |= 0x3000;
930                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
931
932                 /* Set full-duplex, 1000 mbps.  */
933                 tg3_writephy(tp, MII_BMCR,
934                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
935
936                 /* Set to master mode.  */
937                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
938                         continue;
939
940                 tg3_writephy(tp, MII_TG3_CTRL,
941                              (MII_TG3_CTRL_AS_MASTER |
942                               MII_TG3_CTRL_ENABLE_AS_MASTER));
943
944                 /* Enable SM_DSP_CLOCK and 6dB.  */
945                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
946
947                 /* Block the PHY control access.  */
948                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
949                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
950
951                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
952                 if (!err)
953                         break;
954         } while (--retries);
955
956         err = tg3_phy_reset_chanpat(tp);
957         if (err)
958                 return err;
959
960         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
961         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
962
963         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
964         tg3_writephy(tp, 0x16, 0x0000);
965
966         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
967             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
968                 /* Set Extended packet length bit for jumbo frames */
969                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
970         }
971         else {
972                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
973         }
974
975         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
976
977         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
978                 reg32 &= ~0x3000;
979                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
980         } else if (!err)
981                 err = -EBUSY;
982
983         return err;
984 }
985
986 static void tg3_link_report(struct tg3 *);
987
988 /* This will reset the tigon3 PHY if there is no valid
989  * link unless the FORCE argument is non-zero.
990  */
991 static int tg3_phy_reset(struct tg3 *tp)
992 {
993         u32 phy_status;
994         int err;
995
996         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
997                 u32 val;
998
999                 val = tr32(GRC_MISC_CFG);
1000                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1001                 udelay(40);
1002         }
1003         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1004         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1005         if (err != 0)
1006                 return -EBUSY;
1007
1008         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1009                 netif_carrier_off(tp->dev);
1010                 tg3_link_report(tp);
1011         }
1012
1013         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1014             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1015             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1016                 err = tg3_phy_reset_5703_4_5(tp);
1017                 if (err)
1018                         return err;
1019                 goto out;
1020         }
1021
1022         err = tg3_bmcr_reset(tp);
1023         if (err)
1024                 return err;
1025
1026 out:
1027         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1028                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1029                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1030                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1031                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1032                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1033                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1034         }
1035         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1036                 tg3_writephy(tp, 0x1c, 0x8d68);
1037                 tg3_writephy(tp, 0x1c, 0x8d68);
1038         }
1039         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1040                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1041                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1042                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1043                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1044                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1045                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1046                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1047                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1048         }
1049         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1050                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1051                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1052                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1053                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1054                         tg3_writephy(tp, MII_TG3_TEST1,
1055                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1056                 } else
1057                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1058                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1059         }
1060         /* Set Extended packet length bit (bit 14) on all chips that */
1061         /* support jumbo frames */
1062         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1063                 /* Cannot do read-modify-write on 5401 */
1064                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1065         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1066                 u32 phy_reg;
1067
1068                 /* Set bit 14 with read-modify-write to preserve other bits */
1069                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1070                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1071                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1072         }
1073
1074         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1075          * jumbo frames transmission.
1076          */
1077         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1078                 u32 phy_reg;
1079
1080                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1081                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1082                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1083         }
1084
1085         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1086                 /* adjust output voltage */
1087                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1088         }
1089
1090         tg3_phy_toggle_automdix(tp, 1);
1091         tg3_phy_set_wirespeed(tp);
1092         return 0;
1093 }
1094
1095 static void tg3_frob_aux_power(struct tg3 *tp)
1096 {
1097         struct tg3 *tp_peer = tp;
1098
1099         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1100                 return;
1101
1102         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1103             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1104                 struct net_device *dev_peer;
1105
1106                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1107                 /* remove_one() may have been run on the peer. */
1108                 if (!dev_peer)
1109                         tp_peer = tp;
1110                 else
1111                         tp_peer = netdev_priv(dev_peer);
1112         }
1113
1114         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1115             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1116             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1117             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1118                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1119                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1120                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1121                                     (GRC_LCLCTRL_GPIO_OE0 |
1122                                      GRC_LCLCTRL_GPIO_OE1 |
1123                                      GRC_LCLCTRL_GPIO_OE2 |
1124                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1125                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1126                                     100);
1127                 } else {
1128                         u32 no_gpio2;
1129                         u32 grc_local_ctrl = 0;
1130
1131                         if (tp_peer != tp &&
1132                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1133                                 return;
1134
1135                         /* Workaround to prevent overdrawing Amps. */
1136                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1137                             ASIC_REV_5714) {
1138                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1139                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1140                                             grc_local_ctrl, 100);
1141                         }
1142
1143                         /* On 5753 and variants, GPIO2 cannot be used. */
1144                         no_gpio2 = tp->nic_sram_data_cfg &
1145                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1146
1147                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1148                                          GRC_LCLCTRL_GPIO_OE1 |
1149                                          GRC_LCLCTRL_GPIO_OE2 |
1150                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1151                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1152                         if (no_gpio2) {
1153                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1154                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1155                         }
1156                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1157                                                     grc_local_ctrl, 100);
1158
1159                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1160
1161                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1162                                                     grc_local_ctrl, 100);
1163
1164                         if (!no_gpio2) {
1165                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1166                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1167                                             grc_local_ctrl, 100);
1168                         }
1169                 }
1170         } else {
1171                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1172                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1173                         if (tp_peer != tp &&
1174                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1175                                 return;
1176
1177                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1178                                     (GRC_LCLCTRL_GPIO_OE1 |
1179                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1180
1181                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1182                                     GRC_LCLCTRL_GPIO_OE1, 100);
1183
1184                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1185                                     (GRC_LCLCTRL_GPIO_OE1 |
1186                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1187                 }
1188         }
1189 }
1190
1191 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1192 {
1193         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1194                 return 1;
1195         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1196                 if (speed != SPEED_10)
1197                         return 1;
1198         } else if (speed == SPEED_10)
1199                 return 1;
1200
1201         return 0;
1202 }
1203
1204 static int tg3_setup_phy(struct tg3 *, int);
1205
1206 #define RESET_KIND_SHUTDOWN     0
1207 #define RESET_KIND_INIT         1
1208 #define RESET_KIND_SUSPEND      2
1209
1210 static void tg3_write_sig_post_reset(struct tg3 *, int);
1211 static int tg3_halt_cpu(struct tg3 *, u32);
1212 static int tg3_nvram_lock(struct tg3 *);
1213 static void tg3_nvram_unlock(struct tg3 *);
1214
1215 static void tg3_power_down_phy(struct tg3 *tp)
1216 {
1217         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1218                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1219                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1220                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1221
1222                         sg_dig_ctrl |=
1223                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1224                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1225                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1226                 }
1227                 return;
1228         }
1229
1230         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1231                 u32 val;
1232
1233                 tg3_bmcr_reset(tp);
1234                 val = tr32(GRC_MISC_CFG);
1235                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1236                 udelay(40);
1237                 return;
1238         } else {
1239                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1240                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1241                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1242         }
1243
1244         /* The PHY should not be powered down on some chips because
1245          * of bugs.
1246          */
1247         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1248             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1249             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1250              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1251                 return;
1252         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1253 }
1254
1255 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1256 {
1257         u32 misc_host_ctrl;
1258         u16 power_control, power_caps;
1259         int pm = tp->pm_cap;
1260
1261         /* Make sure register accesses (indirect or otherwise)
1262          * will function correctly.
1263          */
1264         pci_write_config_dword(tp->pdev,
1265                                TG3PCI_MISC_HOST_CTRL,
1266                                tp->misc_host_ctrl);
1267
1268         pci_read_config_word(tp->pdev,
1269                              pm + PCI_PM_CTRL,
1270                              &power_control);
1271         power_control |= PCI_PM_CTRL_PME_STATUS;
1272         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1273         switch (state) {
1274         case PCI_D0:
1275                 power_control |= 0;
1276                 pci_write_config_word(tp->pdev,
1277                                       pm + PCI_PM_CTRL,
1278                                       power_control);
1279                 udelay(100);    /* Delay after power state change */
1280
1281                 /* Switch out of Vaux if it is a NIC */
1282                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1283                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1284
1285                 return 0;
1286
1287         case PCI_D1:
1288                 power_control |= 1;
1289                 break;
1290
1291         case PCI_D2:
1292                 power_control |= 2;
1293                 break;
1294
1295         case PCI_D3hot:
1296                 power_control |= 3;
1297                 break;
1298
1299         default:
1300                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1301                        "requested.\n",
1302                        tp->dev->name, state);
1303                 return -EINVAL;
1304         };
1305
1306         power_control |= PCI_PM_CTRL_PME_ENABLE;
1307
1308         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1309         tw32(TG3PCI_MISC_HOST_CTRL,
1310              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1311
1312         if (tp->link_config.phy_is_low_power == 0) {
1313                 tp->link_config.phy_is_low_power = 1;
1314                 tp->link_config.orig_speed = tp->link_config.speed;
1315                 tp->link_config.orig_duplex = tp->link_config.duplex;
1316                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1317         }
1318
1319         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1320                 tp->link_config.speed = SPEED_10;
1321                 tp->link_config.duplex = DUPLEX_HALF;
1322                 tp->link_config.autoneg = AUTONEG_ENABLE;
1323                 tg3_setup_phy(tp, 0);
1324         }
1325
1326         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1327                 u32 val;
1328
1329                 val = tr32(GRC_VCPU_EXT_CTRL);
1330                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1331         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1332                 int i;
1333                 u32 val;
1334
1335                 for (i = 0; i < 200; i++) {
1336                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1337                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1338                                 break;
1339                         msleep(1);
1340                 }
1341         }
1342         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1343                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1344                                                      WOL_DRV_STATE_SHUTDOWN |
1345                                                      WOL_DRV_WOL |
1346                                                      WOL_SET_MAGIC_PKT);
1347
1348         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1349
1350         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1351                 u32 mac_mode;
1352
1353                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1354                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1355                         udelay(40);
1356
1357                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1358                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1359                         else
1360                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1361
1362                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
1363                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1364                             ASIC_REV_5700) {
1365                                 u32 speed = (tp->tg3_flags &
1366                                              TG3_FLAG_WOL_SPEED_100MB) ?
1367                                              SPEED_100 : SPEED_10;
1368                                 if (tg3_5700_link_polarity(tp, speed))
1369                                         mac_mode |= MAC_MODE_LINK_POLARITY;
1370                                 else
1371                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
1372                         }
1373                 } else {
1374                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1375                 }
1376
1377                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1378                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1379
1380                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1381                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1382                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1383
1384                 tw32_f(MAC_MODE, mac_mode);
1385                 udelay(100);
1386
1387                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1388                 udelay(10);
1389         }
1390
1391         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1392             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1393              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1394                 u32 base_val;
1395
1396                 base_val = tp->pci_clock_ctrl;
1397                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1398                              CLOCK_CTRL_TXCLK_DISABLE);
1399
1400                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1401                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1402         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1403                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1404                 /* do nothing */
1405         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1406                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1407                 u32 newbits1, newbits2;
1408
1409                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1410                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1411                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1412                                     CLOCK_CTRL_TXCLK_DISABLE |
1413                                     CLOCK_CTRL_ALTCLK);
1414                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1415                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1416                         newbits1 = CLOCK_CTRL_625_CORE;
1417                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1418                 } else {
1419                         newbits1 = CLOCK_CTRL_ALTCLK;
1420                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1421                 }
1422
1423                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1424                             40);
1425
1426                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1427                             40);
1428
1429                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1430                         u32 newbits3;
1431
1432                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1433                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1434                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1435                                             CLOCK_CTRL_TXCLK_DISABLE |
1436                                             CLOCK_CTRL_44MHZ_CORE);
1437                         } else {
1438                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1439                         }
1440
1441                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1442                                     tp->pci_clock_ctrl | newbits3, 40);
1443                 }
1444         }
1445
1446         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1447             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1448                 tg3_power_down_phy(tp);
1449
1450         tg3_frob_aux_power(tp);
1451
1452         /* Workaround for unstable PLL clock */
1453         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1454             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1455                 u32 val = tr32(0x7d00);
1456
1457                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1458                 tw32(0x7d00, val);
1459                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1460                         int err;
1461
1462                         err = tg3_nvram_lock(tp);
1463                         tg3_halt_cpu(tp, RX_CPU_BASE);
1464                         if (!err)
1465                                 tg3_nvram_unlock(tp);
1466                 }
1467         }
1468
1469         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1470
1471         /* Finally, set the new power state. */
1472         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1473         udelay(100);    /* Delay after power state change */
1474
1475         return 0;
1476 }
1477
1478 static void tg3_link_report(struct tg3 *tp)
1479 {
1480         if (!netif_carrier_ok(tp->dev)) {
1481                 if (netif_msg_link(tp))
1482                         printk(KERN_INFO PFX "%s: Link is down.\n",
1483                                tp->dev->name);
1484         } else if (netif_msg_link(tp)) {
1485                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1486                        tp->dev->name,
1487                        (tp->link_config.active_speed == SPEED_1000 ?
1488                         1000 :
1489                         (tp->link_config.active_speed == SPEED_100 ?
1490                          100 : 10)),
1491                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1492                         "full" : "half"));
1493
1494                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1495                        "%s for RX.\n",
1496                        tp->dev->name,
1497                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1498                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1499         }
1500 }
1501
1502 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1503 {
1504         u32 new_tg3_flags = 0;
1505         u32 old_rx_mode = tp->rx_mode;
1506         u32 old_tx_mode = tp->tx_mode;
1507
1508         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1509
1510                 /* Convert 1000BaseX flow control bits to 1000BaseT
1511                  * bits before resolving flow control.
1512                  */
1513                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1514                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1515                                        ADVERTISE_PAUSE_ASYM);
1516                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1517
1518                         if (local_adv & ADVERTISE_1000XPAUSE)
1519                                 local_adv |= ADVERTISE_PAUSE_CAP;
1520                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1521                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1522                         if (remote_adv & LPA_1000XPAUSE)
1523                                 remote_adv |= LPA_PAUSE_CAP;
1524                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1525                                 remote_adv |= LPA_PAUSE_ASYM;
1526                 }
1527
1528                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1529                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1530                                 if (remote_adv & LPA_PAUSE_CAP)
1531                                         new_tg3_flags |=
1532                                                 (TG3_FLAG_RX_PAUSE |
1533                                                 TG3_FLAG_TX_PAUSE);
1534                                 else if (remote_adv & LPA_PAUSE_ASYM)
1535                                         new_tg3_flags |=
1536                                                 (TG3_FLAG_RX_PAUSE);
1537                         } else {
1538                                 if (remote_adv & LPA_PAUSE_CAP)
1539                                         new_tg3_flags |=
1540                                                 (TG3_FLAG_RX_PAUSE |
1541                                                 TG3_FLAG_TX_PAUSE);
1542                         }
1543                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1544                         if ((remote_adv & LPA_PAUSE_CAP) &&
1545                         (remote_adv & LPA_PAUSE_ASYM))
1546                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1547                 }
1548
1549                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1550                 tp->tg3_flags |= new_tg3_flags;
1551         } else {
1552                 new_tg3_flags = tp->tg3_flags;
1553         }
1554
1555         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1556                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1557         else
1558                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1559
1560         if (old_rx_mode != tp->rx_mode) {
1561                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1562         }
1563
1564         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1565                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1566         else
1567                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1568
1569         if (old_tx_mode != tp->tx_mode) {
1570                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1571         }
1572 }
1573
1574 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1575 {
1576         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1577         case MII_TG3_AUX_STAT_10HALF:
1578                 *speed = SPEED_10;
1579                 *duplex = DUPLEX_HALF;
1580                 break;
1581
1582         case MII_TG3_AUX_STAT_10FULL:
1583                 *speed = SPEED_10;
1584                 *duplex = DUPLEX_FULL;
1585                 break;
1586
1587         case MII_TG3_AUX_STAT_100HALF:
1588                 *speed = SPEED_100;
1589                 *duplex = DUPLEX_HALF;
1590                 break;
1591
1592         case MII_TG3_AUX_STAT_100FULL:
1593                 *speed = SPEED_100;
1594                 *duplex = DUPLEX_FULL;
1595                 break;
1596
1597         case MII_TG3_AUX_STAT_1000HALF:
1598                 *speed = SPEED_1000;
1599                 *duplex = DUPLEX_HALF;
1600                 break;
1601
1602         case MII_TG3_AUX_STAT_1000FULL:
1603                 *speed = SPEED_1000;
1604                 *duplex = DUPLEX_FULL;
1605                 break;
1606
1607         default:
1608                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1609                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1610                                  SPEED_10;
1611                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1612                                   DUPLEX_HALF;
1613                         break;
1614                 }
1615                 *speed = SPEED_INVALID;
1616                 *duplex = DUPLEX_INVALID;
1617                 break;
1618         };
1619 }
1620
1621 static void tg3_phy_copper_begin(struct tg3 *tp)
1622 {
1623         u32 new_adv;
1624         int i;
1625
1626         if (tp->link_config.phy_is_low_power) {
1627                 /* Entering low power mode.  Disable gigabit and
1628                  * 100baseT advertisements.
1629                  */
1630                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1631
1632                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1633                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1634                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1635                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1636
1637                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1638         } else if (tp->link_config.speed == SPEED_INVALID) {
1639                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1640                         tp->link_config.advertising &=
1641                                 ~(ADVERTISED_1000baseT_Half |
1642                                   ADVERTISED_1000baseT_Full);
1643
1644                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1645                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1646                         new_adv |= ADVERTISE_10HALF;
1647                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1648                         new_adv |= ADVERTISE_10FULL;
1649                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1650                         new_adv |= ADVERTISE_100HALF;
1651                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1652                         new_adv |= ADVERTISE_100FULL;
1653                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1654
1655                 if (tp->link_config.advertising &
1656                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1657                         new_adv = 0;
1658                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1659                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1660                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1661                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1662                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1663                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1664                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1665                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1666                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1667                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1668                 } else {
1669                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1670                 }
1671         } else {
1672                 /* Asking for a specific link mode. */
1673                 if (tp->link_config.speed == SPEED_1000) {
1674                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1675                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1676
1677                         if (tp->link_config.duplex == DUPLEX_FULL)
1678                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1679                         else
1680                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1681                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1682                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1683                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1684                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1685                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1686                 } else {
1687                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1688
1689                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1690                         if (tp->link_config.speed == SPEED_100) {
1691                                 if (tp->link_config.duplex == DUPLEX_FULL)
1692                                         new_adv |= ADVERTISE_100FULL;
1693                                 else
1694                                         new_adv |= ADVERTISE_100HALF;
1695                         } else {
1696                                 if (tp->link_config.duplex == DUPLEX_FULL)
1697                                         new_adv |= ADVERTISE_10FULL;
1698                                 else
1699                                         new_adv |= ADVERTISE_10HALF;
1700                         }
1701                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1702                 }
1703         }
1704
1705         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1706             tp->link_config.speed != SPEED_INVALID) {
1707                 u32 bmcr, orig_bmcr;
1708
1709                 tp->link_config.active_speed = tp->link_config.speed;
1710                 tp->link_config.active_duplex = tp->link_config.duplex;
1711
1712                 bmcr = 0;
1713                 switch (tp->link_config.speed) {
1714                 default:
1715                 case SPEED_10:
1716                         break;
1717
1718                 case SPEED_100:
1719                         bmcr |= BMCR_SPEED100;
1720                         break;
1721
1722                 case SPEED_1000:
1723                         bmcr |= TG3_BMCR_SPEED1000;
1724                         break;
1725                 };
1726
1727                 if (tp->link_config.duplex == DUPLEX_FULL)
1728                         bmcr |= BMCR_FULLDPLX;
1729
1730                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1731                     (bmcr != orig_bmcr)) {
1732                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1733                         for (i = 0; i < 1500; i++) {
1734                                 u32 tmp;
1735
1736                                 udelay(10);
1737                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1738                                     tg3_readphy(tp, MII_BMSR, &tmp))
1739                                         continue;
1740                                 if (!(tmp & BMSR_LSTATUS)) {
1741                                         udelay(40);
1742                                         break;
1743                                 }
1744                         }
1745                         tg3_writephy(tp, MII_BMCR, bmcr);
1746                         udelay(40);
1747                 }
1748         } else {
1749                 tg3_writephy(tp, MII_BMCR,
1750                              BMCR_ANENABLE | BMCR_ANRESTART);
1751         }
1752 }
1753
1754 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1755 {
1756         int err;
1757
1758         /* Turn off tap power management. */
1759         /* Set Extended packet length bit */
1760         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1761
1762         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1763         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1764
1765         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1766         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1767
1768         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1769         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1770
1771         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1772         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1773
1774         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1775         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1776
1777         udelay(40);
1778
1779         return err;
1780 }
1781
1782 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1783 {
1784         u32 adv_reg, all_mask = 0;
1785
1786         if (mask & ADVERTISED_10baseT_Half)
1787                 all_mask |= ADVERTISE_10HALF;
1788         if (mask & ADVERTISED_10baseT_Full)
1789                 all_mask |= ADVERTISE_10FULL;
1790         if (mask & ADVERTISED_100baseT_Half)
1791                 all_mask |= ADVERTISE_100HALF;
1792         if (mask & ADVERTISED_100baseT_Full)
1793                 all_mask |= ADVERTISE_100FULL;
1794
1795         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1796                 return 0;
1797
1798         if ((adv_reg & all_mask) != all_mask)
1799                 return 0;
1800         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1801                 u32 tg3_ctrl;
1802
1803                 all_mask = 0;
1804                 if (mask & ADVERTISED_1000baseT_Half)
1805                         all_mask |= ADVERTISE_1000HALF;
1806                 if (mask & ADVERTISED_1000baseT_Full)
1807                         all_mask |= ADVERTISE_1000FULL;
1808
1809                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1810                         return 0;
1811
1812                 if ((tg3_ctrl & all_mask) != all_mask)
1813                         return 0;
1814         }
1815         return 1;
1816 }
1817
1818 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1819 {
1820         int current_link_up;
1821         u32 bmsr, dummy;
1822         u16 current_speed;
1823         u8 current_duplex;
1824         int i, err;
1825
1826         tw32(MAC_EVENT, 0);
1827
1828         tw32_f(MAC_STATUS,
1829              (MAC_STATUS_SYNC_CHANGED |
1830               MAC_STATUS_CFG_CHANGED |
1831               MAC_STATUS_MI_COMPLETION |
1832               MAC_STATUS_LNKSTATE_CHANGED));
1833         udelay(40);
1834
1835         tp->mi_mode = MAC_MI_MODE_BASE;
1836         tw32_f(MAC_MI_MODE, tp->mi_mode);
1837         udelay(80);
1838
1839         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1840
1841         /* Some third-party PHYs need to be reset on link going
1842          * down.
1843          */
1844         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1845              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1846              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1847             netif_carrier_ok(tp->dev)) {
1848                 tg3_readphy(tp, MII_BMSR, &bmsr);
1849                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1850                     !(bmsr & BMSR_LSTATUS))
1851                         force_reset = 1;
1852         }
1853         if (force_reset)
1854                 tg3_phy_reset(tp);
1855
1856         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1857                 tg3_readphy(tp, MII_BMSR, &bmsr);
1858                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1859                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1860                         bmsr = 0;
1861
1862                 if (!(bmsr & BMSR_LSTATUS)) {
1863                         err = tg3_init_5401phy_dsp(tp);
1864                         if (err)
1865                                 return err;
1866
1867                         tg3_readphy(tp, MII_BMSR, &bmsr);
1868                         for (i = 0; i < 1000; i++) {
1869                                 udelay(10);
1870                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1871                                     (bmsr & BMSR_LSTATUS)) {
1872                                         udelay(40);
1873                                         break;
1874                                 }
1875                         }
1876
1877                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1878                             !(bmsr & BMSR_LSTATUS) &&
1879                             tp->link_config.active_speed == SPEED_1000) {
1880                                 err = tg3_phy_reset(tp);
1881                                 if (!err)
1882                                         err = tg3_init_5401phy_dsp(tp);
1883                                 if (err)
1884                                         return err;
1885                         }
1886                 }
1887         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1888                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1889                 /* 5701 {A0,B0} CRC bug workaround */
1890                 tg3_writephy(tp, 0x15, 0x0a75);
1891                 tg3_writephy(tp, 0x1c, 0x8c68);
1892                 tg3_writephy(tp, 0x1c, 0x8d68);
1893                 tg3_writephy(tp, 0x1c, 0x8c68);
1894         }
1895
1896         /* Clear pending interrupts... */
1897         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1898         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1899
1900         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1901                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1902         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1903                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1904
1905         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1906             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1907                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1908                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1909                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1910                 else
1911                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1912         }
1913
1914         current_link_up = 0;
1915         current_speed = SPEED_INVALID;
1916         current_duplex = DUPLEX_INVALID;
1917
1918         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1919                 u32 val;
1920
1921                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1922                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1923                 if (!(val & (1 << 10))) {
1924                         val |= (1 << 10);
1925                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1926                         goto relink;
1927                 }
1928         }
1929
1930         bmsr = 0;
1931         for (i = 0; i < 100; i++) {
1932                 tg3_readphy(tp, MII_BMSR, &bmsr);
1933                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1934                     (bmsr & BMSR_LSTATUS))
1935                         break;
1936                 udelay(40);
1937         }
1938
1939         if (bmsr & BMSR_LSTATUS) {
1940                 u32 aux_stat, bmcr;
1941
1942                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1943                 for (i = 0; i < 2000; i++) {
1944                         udelay(10);
1945                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1946                             aux_stat)
1947                                 break;
1948                 }
1949
1950                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1951                                              &current_speed,
1952                                              &current_duplex);
1953
1954                 bmcr = 0;
1955                 for (i = 0; i < 200; i++) {
1956                         tg3_readphy(tp, MII_BMCR, &bmcr);
1957                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1958                                 continue;
1959                         if (bmcr && bmcr != 0x7fff)
1960                                 break;
1961                         udelay(10);
1962                 }
1963
1964                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1965                         if (bmcr & BMCR_ANENABLE) {
1966                                 current_link_up = 1;
1967
1968                                 /* Force autoneg restart if we are exiting
1969                                  * low power mode.
1970                                  */
1971                                 if (!tg3_copper_is_advertising_all(tp,
1972                                                 tp->link_config.advertising))
1973                                         current_link_up = 0;
1974                         } else {
1975                                 current_link_up = 0;
1976                         }
1977                 } else {
1978                         if (!(bmcr & BMCR_ANENABLE) &&
1979                             tp->link_config.speed == current_speed &&
1980                             tp->link_config.duplex == current_duplex) {
1981                                 current_link_up = 1;
1982                         } else {
1983                                 current_link_up = 0;
1984                         }
1985                 }
1986
1987                 tp->link_config.active_speed = current_speed;
1988                 tp->link_config.active_duplex = current_duplex;
1989         }
1990
1991         if (current_link_up == 1 &&
1992             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1993             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1994                 u32 local_adv, remote_adv;
1995
1996                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1997                         local_adv = 0;
1998                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1999
2000                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
2001                         remote_adv = 0;
2002
2003                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
2004
2005                 /* If we are not advertising full pause capability,
2006                  * something is wrong.  Bring the link down and reconfigure.
2007                  */
2008                 if (local_adv != ADVERTISE_PAUSE_CAP) {
2009                         current_link_up = 0;
2010                 } else {
2011                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2012                 }
2013         }
2014 relink:
2015         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2016                 u32 tmp;
2017
2018                 tg3_phy_copper_begin(tp);
2019
2020                 tg3_readphy(tp, MII_BMSR, &tmp);
2021                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2022                     (tmp & BMSR_LSTATUS))
2023                         current_link_up = 1;
2024         }
2025
2026         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2027         if (current_link_up == 1) {
2028                 if (tp->link_config.active_speed == SPEED_100 ||
2029                     tp->link_config.active_speed == SPEED_10)
2030                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2031                 else
2032                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2033         } else
2034                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2035
2036         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2037         if (tp->link_config.active_duplex == DUPLEX_HALF)
2038                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2039
2040         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2041                 if (current_link_up == 1 &&
2042                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2043                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2044                 else
2045                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2046         }
2047
2048         /* ??? Without this setting Netgear GA302T PHY does not
2049          * ??? send/receive packets...
2050          */
2051         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2052             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2053                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2054                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2055                 udelay(80);
2056         }
2057
2058         tw32_f(MAC_MODE, tp->mac_mode);
2059         udelay(40);
2060
2061         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2062                 /* Polled via timer. */
2063                 tw32_f(MAC_EVENT, 0);
2064         } else {
2065                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2066         }
2067         udelay(40);
2068
2069         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2070             current_link_up == 1 &&
2071             tp->link_config.active_speed == SPEED_1000 &&
2072             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2073              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2074                 udelay(120);
2075                 tw32_f(MAC_STATUS,
2076                      (MAC_STATUS_SYNC_CHANGED |
2077                       MAC_STATUS_CFG_CHANGED));
2078                 udelay(40);
2079                 tg3_write_mem(tp,
2080                               NIC_SRAM_FIRMWARE_MBOX,
2081                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2082         }
2083
2084         if (current_link_up != netif_carrier_ok(tp->dev)) {
2085                 if (current_link_up)
2086                         netif_carrier_on(tp->dev);
2087                 else
2088                         netif_carrier_off(tp->dev);
2089                 tg3_link_report(tp);
2090         }
2091
2092         return 0;
2093 }
2094
2095 struct tg3_fiber_aneginfo {
2096         int state;
2097 #define ANEG_STATE_UNKNOWN              0
2098 #define ANEG_STATE_AN_ENABLE            1
2099 #define ANEG_STATE_RESTART_INIT         2
2100 #define ANEG_STATE_RESTART              3
2101 #define ANEG_STATE_DISABLE_LINK_OK      4
2102 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2103 #define ANEG_STATE_ABILITY_DETECT       6
2104 #define ANEG_STATE_ACK_DETECT_INIT      7
2105 #define ANEG_STATE_ACK_DETECT           8
2106 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2107 #define ANEG_STATE_COMPLETE_ACK         10
2108 #define ANEG_STATE_IDLE_DETECT_INIT     11
2109 #define ANEG_STATE_IDLE_DETECT          12
2110 #define ANEG_STATE_LINK_OK              13
2111 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2112 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2113
2114         u32 flags;
2115 #define MR_AN_ENABLE            0x00000001
2116 #define MR_RESTART_AN           0x00000002
2117 #define MR_AN_COMPLETE          0x00000004
2118 #define MR_PAGE_RX              0x00000008
2119 #define MR_NP_LOADED            0x00000010
2120 #define MR_TOGGLE_TX            0x00000020
2121 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2122 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2123 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2124 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2125 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2126 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2127 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2128 #define MR_TOGGLE_RX            0x00002000
2129 #define MR_NP_RX                0x00004000
2130
2131 #define MR_LINK_OK              0x80000000
2132
2133         unsigned long link_time, cur_time;
2134
2135         u32 ability_match_cfg;
2136         int ability_match_count;
2137
2138         char ability_match, idle_match, ack_match;
2139
2140         u32 txconfig, rxconfig;
2141 #define ANEG_CFG_NP             0x00000080
2142 #define ANEG_CFG_ACK            0x00000040
2143 #define ANEG_CFG_RF2            0x00000020
2144 #define ANEG_CFG_RF1            0x00000010
2145 #define ANEG_CFG_PS2            0x00000001
2146 #define ANEG_CFG_PS1            0x00008000
2147 #define ANEG_CFG_HD             0x00004000
2148 #define ANEG_CFG_FD             0x00002000
2149 #define ANEG_CFG_INVAL          0x00001f06
2150
2151 };
2152 #define ANEG_OK         0
2153 #define ANEG_DONE       1
2154 #define ANEG_TIMER_ENAB 2
2155 #define ANEG_FAILED     -1
2156
2157 #define ANEG_STATE_SETTLE_TIME  10000
2158
2159 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2160                                    struct tg3_fiber_aneginfo *ap)
2161 {
2162         unsigned long delta;
2163         u32 rx_cfg_reg;
2164         int ret;
2165
2166         if (ap->state == ANEG_STATE_UNKNOWN) {
2167                 ap->rxconfig = 0;
2168                 ap->link_time = 0;
2169                 ap->cur_time = 0;
2170                 ap->ability_match_cfg = 0;
2171                 ap->ability_match_count = 0;
2172                 ap->ability_match = 0;
2173                 ap->idle_match = 0;
2174                 ap->ack_match = 0;
2175         }
2176         ap->cur_time++;
2177
2178         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2179                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2180
2181                 if (rx_cfg_reg != ap->ability_match_cfg) {
2182                         ap->ability_match_cfg = rx_cfg_reg;
2183                         ap->ability_match = 0;
2184                         ap->ability_match_count = 0;
2185                 } else {
2186                         if (++ap->ability_match_count > 1) {
2187                                 ap->ability_match = 1;
2188                                 ap->ability_match_cfg = rx_cfg_reg;
2189                         }
2190                 }
2191                 if (rx_cfg_reg & ANEG_CFG_ACK)
2192                         ap->ack_match = 1;
2193                 else
2194                         ap->ack_match = 0;
2195
2196                 ap->idle_match = 0;
2197         } else {
2198                 ap->idle_match = 1;
2199                 ap->ability_match_cfg = 0;
2200                 ap->ability_match_count = 0;
2201                 ap->ability_match = 0;
2202                 ap->ack_match = 0;
2203
2204                 rx_cfg_reg = 0;
2205         }
2206
2207         ap->rxconfig = rx_cfg_reg;
2208         ret = ANEG_OK;
2209
2210         switch(ap->state) {
2211         case ANEG_STATE_UNKNOWN:
2212                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2213                         ap->state = ANEG_STATE_AN_ENABLE;
2214
2215                 /* fallthru */
2216         case ANEG_STATE_AN_ENABLE:
2217                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2218                 if (ap->flags & MR_AN_ENABLE) {
2219                         ap->link_time = 0;
2220                         ap->cur_time = 0;
2221                         ap->ability_match_cfg = 0;
2222                         ap->ability_match_count = 0;
2223                         ap->ability_match = 0;
2224                         ap->idle_match = 0;
2225                         ap->ack_match = 0;
2226
2227                         ap->state = ANEG_STATE_RESTART_INIT;
2228                 } else {
2229                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2230                 }
2231                 break;
2232
2233         case ANEG_STATE_RESTART_INIT:
2234                 ap->link_time = ap->cur_time;
2235                 ap->flags &= ~(MR_NP_LOADED);
2236                 ap->txconfig = 0;
2237                 tw32(MAC_TX_AUTO_NEG, 0);
2238                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2239                 tw32_f(MAC_MODE, tp->mac_mode);
2240                 udelay(40);
2241
2242                 ret = ANEG_TIMER_ENAB;
2243                 ap->state = ANEG_STATE_RESTART;
2244
2245                 /* fallthru */
2246         case ANEG_STATE_RESTART:
2247                 delta = ap->cur_time - ap->link_time;
2248                 if (delta > ANEG_STATE_SETTLE_TIME) {
2249                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2250                 } else {
2251                         ret = ANEG_TIMER_ENAB;
2252                 }
2253                 break;
2254
2255         case ANEG_STATE_DISABLE_LINK_OK:
2256                 ret = ANEG_DONE;
2257                 break;
2258
2259         case ANEG_STATE_ABILITY_DETECT_INIT:
2260                 ap->flags &= ~(MR_TOGGLE_TX);
2261                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2262                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2263                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2264                 tw32_f(MAC_MODE, tp->mac_mode);
2265                 udelay(40);
2266
2267                 ap->state = ANEG_STATE_ABILITY_DETECT;
2268                 break;
2269
2270         case ANEG_STATE_ABILITY_DETECT:
2271                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2272                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2273                 }
2274                 break;
2275
2276         case ANEG_STATE_ACK_DETECT_INIT:
2277                 ap->txconfig |= ANEG_CFG_ACK;
2278                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2279                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2280                 tw32_f(MAC_MODE, tp->mac_mode);
2281                 udelay(40);
2282
2283                 ap->state = ANEG_STATE_ACK_DETECT;
2284
2285                 /* fallthru */
2286         case ANEG_STATE_ACK_DETECT:
2287                 if (ap->ack_match != 0) {
2288                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2289                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2290                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2291                         } else {
2292                                 ap->state = ANEG_STATE_AN_ENABLE;
2293                         }
2294                 } else if (ap->ability_match != 0 &&
2295                            ap->rxconfig == 0) {
2296                         ap->state = ANEG_STATE_AN_ENABLE;
2297                 }
2298                 break;
2299
2300         case ANEG_STATE_COMPLETE_ACK_INIT:
2301                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2302                         ret = ANEG_FAILED;
2303                         break;
2304                 }
2305                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2306                                MR_LP_ADV_HALF_DUPLEX |
2307                                MR_LP_ADV_SYM_PAUSE |
2308                                MR_LP_ADV_ASYM_PAUSE |
2309                                MR_LP_ADV_REMOTE_FAULT1 |
2310                                MR_LP_ADV_REMOTE_FAULT2 |
2311                                MR_LP_ADV_NEXT_PAGE |
2312                                MR_TOGGLE_RX |
2313                                MR_NP_RX);
2314                 if (ap->rxconfig & ANEG_CFG_FD)
2315                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2316                 if (ap->rxconfig & ANEG_CFG_HD)
2317                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2318                 if (ap->rxconfig & ANEG_CFG_PS1)
2319                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2320                 if (ap->rxconfig & ANEG_CFG_PS2)
2321                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2322                 if (ap->rxconfig & ANEG_CFG_RF1)
2323                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2324                 if (ap->rxconfig & ANEG_CFG_RF2)
2325                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2326                 if (ap->rxconfig & ANEG_CFG_NP)
2327                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2328
2329                 ap->link_time = ap->cur_time;
2330
2331                 ap->flags ^= (MR_TOGGLE_TX);
2332                 if (ap->rxconfig & 0x0008)
2333                         ap->flags |= MR_TOGGLE_RX;
2334                 if (ap->rxconfig & ANEG_CFG_NP)
2335                         ap->flags |= MR_NP_RX;
2336                 ap->flags |= MR_PAGE_RX;
2337
2338                 ap->state = ANEG_STATE_COMPLETE_ACK;
2339                 ret = ANEG_TIMER_ENAB;
2340                 break;
2341
2342         case ANEG_STATE_COMPLETE_ACK:
2343                 if (ap->ability_match != 0 &&
2344                     ap->rxconfig == 0) {
2345                         ap->state = ANEG_STATE_AN_ENABLE;
2346                         break;
2347                 }
2348                 delta = ap->cur_time - ap->link_time;
2349                 if (delta > ANEG_STATE_SETTLE_TIME) {
2350                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2351                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2352                         } else {
2353                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2354                                     !(ap->flags & MR_NP_RX)) {
2355                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2356                                 } else {
2357                                         ret = ANEG_FAILED;
2358                                 }
2359                         }
2360                 }
2361                 break;
2362
2363         case ANEG_STATE_IDLE_DETECT_INIT:
2364                 ap->link_time = ap->cur_time;
2365                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2366                 tw32_f(MAC_MODE, tp->mac_mode);
2367                 udelay(40);
2368
2369                 ap->state = ANEG_STATE_IDLE_DETECT;
2370                 ret = ANEG_TIMER_ENAB;
2371                 break;
2372
2373         case ANEG_STATE_IDLE_DETECT:
2374                 if (ap->ability_match != 0 &&
2375                     ap->rxconfig == 0) {
2376                         ap->state = ANEG_STATE_AN_ENABLE;
2377                         break;
2378                 }
2379                 delta = ap->cur_time - ap->link_time;
2380                 if (delta > ANEG_STATE_SETTLE_TIME) {
2381                         /* XXX another gem from the Broadcom driver :( */
2382                         ap->state = ANEG_STATE_LINK_OK;
2383                 }
2384                 break;
2385
2386         case ANEG_STATE_LINK_OK:
2387                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2388                 ret = ANEG_DONE;
2389                 break;
2390
2391         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2392                 /* ??? unimplemented */
2393                 break;
2394
2395         case ANEG_STATE_NEXT_PAGE_WAIT:
2396                 /* ??? unimplemented */
2397                 break;
2398
2399         default:
2400                 ret = ANEG_FAILED;
2401                 break;
2402         };
2403
2404         return ret;
2405 }
2406
2407 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2408 {
2409         int res = 0;
2410         struct tg3_fiber_aneginfo aninfo;
2411         int status = ANEG_FAILED;
2412         unsigned int tick;
2413         u32 tmp;
2414
2415         tw32_f(MAC_TX_AUTO_NEG, 0);
2416
2417         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2418         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2419         udelay(40);
2420
2421         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2422         udelay(40);
2423
2424         memset(&aninfo, 0, sizeof(aninfo));
2425         aninfo.flags |= MR_AN_ENABLE;
2426         aninfo.state = ANEG_STATE_UNKNOWN;
2427         aninfo.cur_time = 0;
2428         tick = 0;
2429         while (++tick < 195000) {
2430                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2431                 if (status == ANEG_DONE || status == ANEG_FAILED)
2432                         break;
2433
2434                 udelay(1);
2435         }
2436
2437         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2438         tw32_f(MAC_MODE, tp->mac_mode);
2439         udelay(40);
2440
2441         *flags = aninfo.flags;
2442
2443         if (status == ANEG_DONE &&
2444             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2445                              MR_LP_ADV_FULL_DUPLEX)))
2446                 res = 1;
2447
2448         return res;
2449 }
2450
2451 static void tg3_init_bcm8002(struct tg3 *tp)
2452 {
2453         u32 mac_status = tr32(MAC_STATUS);
2454         int i;
2455
2456         /* Reset when initting first time or we have a link. */
2457         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2458             !(mac_status & MAC_STATUS_PCS_SYNCED))
2459                 return;
2460
2461         /* Set PLL lock range. */
2462         tg3_writephy(tp, 0x16, 0x8007);
2463
2464         /* SW reset */
2465         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2466
2467         /* Wait for reset to complete. */
2468         /* XXX schedule_timeout() ... */
2469         for (i = 0; i < 500; i++)
2470                 udelay(10);
2471
2472         /* Config mode; select PMA/Ch 1 regs. */
2473         tg3_writephy(tp, 0x10, 0x8411);
2474
2475         /* Enable auto-lock and comdet, select txclk for tx. */
2476         tg3_writephy(tp, 0x11, 0x0a10);
2477
2478         tg3_writephy(tp, 0x18, 0x00a0);
2479         tg3_writephy(tp, 0x16, 0x41ff);
2480
2481         /* Assert and deassert POR. */
2482         tg3_writephy(tp, 0x13, 0x0400);
2483         udelay(40);
2484         tg3_writephy(tp, 0x13, 0x0000);
2485
2486         tg3_writephy(tp, 0x11, 0x0a50);
2487         udelay(40);
2488         tg3_writephy(tp, 0x11, 0x0a10);
2489
2490         /* Wait for signal to stabilize */
2491         /* XXX schedule_timeout() ... */
2492         for (i = 0; i < 15000; i++)
2493                 udelay(10);
2494
2495         /* Deselect the channel register so we can read the PHYID
2496          * later.
2497          */
2498         tg3_writephy(tp, 0x10, 0x8011);
2499 }
2500
2501 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2502 {
2503         u32 sg_dig_ctrl, sg_dig_status;
2504         u32 serdes_cfg, expected_sg_dig_ctrl;
2505         int workaround, port_a;
2506         int current_link_up;
2507
2508         serdes_cfg = 0;
2509         expected_sg_dig_ctrl = 0;
2510         workaround = 0;
2511         port_a = 1;
2512         current_link_up = 0;
2513
2514         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2515             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2516                 workaround = 1;
2517                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2518                         port_a = 0;
2519
2520                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2521                 /* preserve bits 20-23 for voltage regulator */
2522                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2523         }
2524
2525         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2526
2527         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2528                 if (sg_dig_ctrl & (1 << 31)) {
2529                         if (workaround) {
2530                                 u32 val = serdes_cfg;
2531
2532                                 if (port_a)
2533                                         val |= 0xc010000;
2534                                 else
2535                                         val |= 0x4010000;
2536                                 tw32_f(MAC_SERDES_CFG, val);
2537                         }
2538                         tw32_f(SG_DIG_CTRL, 0x01388400);
2539                 }
2540                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2541                         tg3_setup_flow_control(tp, 0, 0);
2542                         current_link_up = 1;
2543                 }
2544                 goto out;
2545         }
2546
2547         /* Want auto-negotiation.  */
2548         expected_sg_dig_ctrl = 0x81388400;
2549
2550         /* Pause capability */
2551         expected_sg_dig_ctrl |= (1 << 11);
2552
2553         /* Asymettric pause */
2554         expected_sg_dig_ctrl |= (1 << 12);
2555
2556         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2557                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2558                     tp->serdes_counter &&
2559                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2560                                     MAC_STATUS_RCVD_CFG)) ==
2561                      MAC_STATUS_PCS_SYNCED)) {
2562                         tp->serdes_counter--;
2563                         current_link_up = 1;
2564                         goto out;
2565                 }
2566 restart_autoneg:
2567                 if (workaround)
2568                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2569                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2570                 udelay(5);
2571                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2572
2573                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2574                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2575         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2576                                  MAC_STATUS_SIGNAL_DET)) {
2577                 sg_dig_status = tr32(SG_DIG_STATUS);
2578                 mac_status = tr32(MAC_STATUS);
2579
2580                 if ((sg_dig_status & (1 << 1)) &&
2581                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2582                         u32 local_adv, remote_adv;
2583
2584                         local_adv = ADVERTISE_PAUSE_CAP;
2585                         remote_adv = 0;
2586                         if (sg_dig_status & (1 << 19))
2587                                 remote_adv |= LPA_PAUSE_CAP;
2588                         if (sg_dig_status & (1 << 20))
2589                                 remote_adv |= LPA_PAUSE_ASYM;
2590
2591                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2592                         current_link_up = 1;
2593                         tp->serdes_counter = 0;
2594                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2595                 } else if (!(sg_dig_status & (1 << 1))) {
2596                         if (tp->serdes_counter)
2597                                 tp->serdes_counter--;
2598                         else {
2599                                 if (workaround) {
2600                                         u32 val = serdes_cfg;
2601
2602                                         if (port_a)
2603                                                 val |= 0xc010000;
2604                                         else
2605                                                 val |= 0x4010000;
2606
2607                                         tw32_f(MAC_SERDES_CFG, val);
2608                                 }
2609
2610                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2611                                 udelay(40);
2612
2613                                 /* Link parallel detection - link is up */
2614                                 /* only if we have PCS_SYNC and not */
2615                                 /* receiving config code words */
2616                                 mac_status = tr32(MAC_STATUS);
2617                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2618                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2619                                         tg3_setup_flow_control(tp, 0, 0);
2620                                         current_link_up = 1;
2621                                         tp->tg3_flags2 |=
2622                                                 TG3_FLG2_PARALLEL_DETECT;
2623                                         tp->serdes_counter =
2624                                                 SERDES_PARALLEL_DET_TIMEOUT;
2625                                 } else
2626                                         goto restart_autoneg;
2627                         }
2628                 }
2629         } else {
2630                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2631                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2632         }
2633
2634 out:
2635         return current_link_up;
2636 }
2637
2638 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2639 {
2640         int current_link_up = 0;
2641
2642         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
2643                 goto out;
2644
2645         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2646                 u32 flags;
2647                 int i;
2648
2649                 if (fiber_autoneg(tp, &flags)) {
2650                         u32 local_adv, remote_adv;
2651
2652                         local_adv = ADVERTISE_PAUSE_CAP;
2653                         remote_adv = 0;
2654                         if (flags & MR_LP_ADV_SYM_PAUSE)
2655                                 remote_adv |= LPA_PAUSE_CAP;
2656                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2657                                 remote_adv |= LPA_PAUSE_ASYM;
2658
2659                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2660
2661                         current_link_up = 1;
2662                 }
2663                 for (i = 0; i < 30; i++) {
2664                         udelay(20);
2665                         tw32_f(MAC_STATUS,
2666                                (MAC_STATUS_SYNC_CHANGED |
2667                                 MAC_STATUS_CFG_CHANGED));
2668                         udelay(40);
2669                         if ((tr32(MAC_STATUS) &
2670                              (MAC_STATUS_SYNC_CHANGED |
2671                               MAC_STATUS_CFG_CHANGED)) == 0)
2672                                 break;
2673                 }
2674
2675                 mac_status = tr32(MAC_STATUS);
2676                 if (current_link_up == 0 &&
2677                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2678                     !(mac_status & MAC_STATUS_RCVD_CFG))
2679                         current_link_up = 1;
2680         } else {
2681                 /* Forcing 1000FD link up. */
2682                 current_link_up = 1;
2683
2684                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2685                 udelay(40);
2686
2687                 tw32_f(MAC_MODE, tp->mac_mode);
2688                 udelay(40);
2689         }
2690
2691 out:
2692         return current_link_up;
2693 }
2694
2695 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2696 {
2697         u32 orig_pause_cfg;
2698         u16 orig_active_speed;
2699         u8 orig_active_duplex;
2700         u32 mac_status;
2701         int current_link_up;
2702         int i;
2703
2704         orig_pause_cfg =
2705                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2706                                   TG3_FLAG_TX_PAUSE));
2707         orig_active_speed = tp->link_config.active_speed;
2708         orig_active_duplex = tp->link_config.active_duplex;
2709
2710         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2711             netif_carrier_ok(tp->dev) &&
2712             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2713                 mac_status = tr32(MAC_STATUS);
2714                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2715                                MAC_STATUS_SIGNAL_DET |
2716                                MAC_STATUS_CFG_CHANGED |
2717                                MAC_STATUS_RCVD_CFG);
2718                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2719                                    MAC_STATUS_SIGNAL_DET)) {
2720                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2721                                             MAC_STATUS_CFG_CHANGED));
2722                         return 0;
2723                 }
2724         }
2725
2726         tw32_f(MAC_TX_AUTO_NEG, 0);
2727
2728         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2729         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2730         tw32_f(MAC_MODE, tp->mac_mode);
2731         udelay(40);
2732
2733         if (tp->phy_id == PHY_ID_BCM8002)
2734                 tg3_init_bcm8002(tp);
2735
2736         /* Enable link change event even when serdes polling.  */
2737         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2738         udelay(40);
2739
2740         current_link_up = 0;
2741         mac_status = tr32(MAC_STATUS);
2742
2743         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2744                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2745         else
2746                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2747
2748         tp->hw_status->status =
2749                 (SD_STATUS_UPDATED |
2750                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2751
2752         for (i = 0; i < 100; i++) {
2753                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2754                                     MAC_STATUS_CFG_CHANGED));
2755                 udelay(5);
2756                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2757                                          MAC_STATUS_CFG_CHANGED |
2758                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2759                         break;
2760         }
2761
2762         mac_status = tr32(MAC_STATUS);
2763         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2764                 current_link_up = 0;
2765                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2766                     tp->serdes_counter == 0) {
2767                         tw32_f(MAC_MODE, (tp->mac_mode |
2768                                           MAC_MODE_SEND_CONFIGS));
2769                         udelay(1);
2770                         tw32_f(MAC_MODE, tp->mac_mode);
2771                 }
2772         }
2773
2774         if (current_link_up == 1) {
2775                 tp->link_config.active_speed = SPEED_1000;
2776                 tp->link_config.active_duplex = DUPLEX_FULL;
2777                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2778                                     LED_CTRL_LNKLED_OVERRIDE |
2779                                     LED_CTRL_1000MBPS_ON));
2780         } else {
2781                 tp->link_config.active_speed = SPEED_INVALID;
2782                 tp->link_config.active_duplex = DUPLEX_INVALID;
2783                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2784                                     LED_CTRL_LNKLED_OVERRIDE |
2785                                     LED_CTRL_TRAFFIC_OVERRIDE));
2786         }
2787
2788         if (current_link_up != netif_carrier_ok(tp->dev)) {
2789                 if (current_link_up)
2790                         netif_carrier_on(tp->dev);
2791                 else
2792                         netif_carrier_off(tp->dev);
2793                 tg3_link_report(tp);
2794         } else {
2795                 u32 now_pause_cfg =
2796                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2797                                          TG3_FLAG_TX_PAUSE);
2798                 if (orig_pause_cfg != now_pause_cfg ||
2799                     orig_active_speed != tp->link_config.active_speed ||
2800                     orig_active_duplex != tp->link_config.active_duplex)
2801                         tg3_link_report(tp);
2802         }
2803
2804         return 0;
2805 }
2806
2807 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2808 {
2809         int current_link_up, err = 0;
2810         u32 bmsr, bmcr;
2811         u16 current_speed;
2812         u8 current_duplex;
2813
2814         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2815         tw32_f(MAC_MODE, tp->mac_mode);
2816         udelay(40);
2817
2818         tw32(MAC_EVENT, 0);
2819
2820         tw32_f(MAC_STATUS,
2821              (MAC_STATUS_SYNC_CHANGED |
2822               MAC_STATUS_CFG_CHANGED |
2823               MAC_STATUS_MI_COMPLETION |
2824               MAC_STATUS_LNKSTATE_CHANGED));
2825         udelay(40);
2826
2827         if (force_reset)
2828                 tg3_phy_reset(tp);
2829
2830         current_link_up = 0;
2831         current_speed = SPEED_INVALID;
2832         current_duplex = DUPLEX_INVALID;
2833
2834         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2835         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2836         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2837                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2838                         bmsr |= BMSR_LSTATUS;
2839                 else
2840                         bmsr &= ~BMSR_LSTATUS;
2841         }
2842
2843         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2844
2845         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2846             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2847                 /* do nothing, just check for link up at the end */
2848         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2849                 u32 adv, new_adv;
2850
2851                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2852                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2853                                   ADVERTISE_1000XPAUSE |
2854                                   ADVERTISE_1000XPSE_ASYM |
2855                                   ADVERTISE_SLCT);
2856
2857                 /* Always advertise symmetric PAUSE just like copper */
2858                 new_adv |= ADVERTISE_1000XPAUSE;
2859
2860                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2861                         new_adv |= ADVERTISE_1000XHALF;
2862                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2863                         new_adv |= ADVERTISE_1000XFULL;
2864
2865                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2866                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2867                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2868                         tg3_writephy(tp, MII_BMCR, bmcr);
2869
2870                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2871                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2872                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2873
2874                         return err;
2875                 }
2876         } else {
2877                 u32 new_bmcr;
2878
2879                 bmcr &= ~BMCR_SPEED1000;
2880                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2881
2882                 if (tp->link_config.duplex == DUPLEX_FULL)
2883                         new_bmcr |= BMCR_FULLDPLX;
2884
2885                 if (new_bmcr != bmcr) {
2886                         /* BMCR_SPEED1000 is a reserved bit that needs
2887                          * to be set on write.
2888                          */
2889                         new_bmcr |= BMCR_SPEED1000;
2890
2891                         /* Force a linkdown */
2892                         if (netif_carrier_ok(tp->dev)) {
2893                                 u32 adv;
2894
2895                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2896                                 adv &= ~(ADVERTISE_1000XFULL |
2897                                          ADVERTISE_1000XHALF |
2898                                          ADVERTISE_SLCT);
2899                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2900                                 tg3_writephy(tp, MII_BMCR, bmcr |
2901                                                            BMCR_ANRESTART |
2902                                                            BMCR_ANENABLE);
2903                                 udelay(10);
2904                                 netif_carrier_off(tp->dev);
2905                         }
2906                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2907                         bmcr = new_bmcr;
2908                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2909                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2910                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2911                             ASIC_REV_5714) {
2912                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2913                                         bmsr |= BMSR_LSTATUS;
2914                                 else
2915                                         bmsr &= ~BMSR_LSTATUS;
2916                         }
2917                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2918                 }
2919         }
2920
2921         if (bmsr & BMSR_LSTATUS) {
2922                 current_speed = SPEED_1000;
2923                 current_link_up = 1;
2924                 if (bmcr & BMCR_FULLDPLX)
2925                         current_duplex = DUPLEX_FULL;
2926                 else
2927                         current_duplex = DUPLEX_HALF;
2928
2929                 if (bmcr & BMCR_ANENABLE) {
2930                         u32 local_adv, remote_adv, common;
2931
2932                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2933                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2934                         common = local_adv & remote_adv;
2935                         if (common & (ADVERTISE_1000XHALF |
2936                                       ADVERTISE_1000XFULL)) {
2937                                 if (common & ADVERTISE_1000XFULL)
2938                                         current_duplex = DUPLEX_FULL;
2939                                 else
2940                                         current_duplex = DUPLEX_HALF;
2941
2942                                 tg3_setup_flow_control(tp, local_adv,
2943                                                        remote_adv);
2944                         }
2945                         else
2946                                 current_link_up = 0;
2947                 }
2948         }
2949
2950         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2951         if (tp->link_config.active_duplex == DUPLEX_HALF)
2952                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2953
2954         tw32_f(MAC_MODE, tp->mac_mode);
2955         udelay(40);
2956
2957         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2958
2959         tp->link_config.active_speed = current_speed;
2960         tp->link_config.active_duplex = current_duplex;
2961
2962         if (current_link_up != netif_carrier_ok(tp->dev)) {
2963                 if (current_link_up)
2964                         netif_carrier_on(tp->dev);
2965                 else {
2966                         netif_carrier_off(tp->dev);
2967                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2968                 }
2969                 tg3_link_report(tp);
2970         }
2971         return err;
2972 }
2973
2974 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2975 {
2976         if (tp->serdes_counter) {
2977                 /* Give autoneg time to complete. */
2978                 tp->serdes_counter--;
2979                 return;
2980         }
2981         if (!netif_carrier_ok(tp->dev) &&
2982             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2983                 u32 bmcr;
2984
2985                 tg3_readphy(tp, MII_BMCR, &bmcr);
2986                 if (bmcr & BMCR_ANENABLE) {
2987                         u32 phy1, phy2;
2988
2989                         /* Select shadow register 0x1f */
2990                         tg3_writephy(tp, 0x1c, 0x7c00);
2991                         tg3_readphy(tp, 0x1c, &phy1);
2992
2993                         /* Select expansion interrupt status register */
2994                         tg3_writephy(tp, 0x17, 0x0f01);
2995                         tg3_readphy(tp, 0x15, &phy2);
2996                         tg3_readphy(tp, 0x15, &phy2);
2997
2998                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2999                                 /* We have signal detect and not receiving
3000                                  * config code words, link is up by parallel
3001                                  * detection.
3002                                  */
3003
3004                                 bmcr &= ~BMCR_ANENABLE;
3005                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3006                                 tg3_writephy(tp, MII_BMCR, bmcr);
3007                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3008                         }
3009                 }
3010         }
3011         else if (netif_carrier_ok(tp->dev) &&
3012                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3013                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3014                 u32 phy2;
3015
3016                 /* Select expansion interrupt status register */
3017                 tg3_writephy(tp, 0x17, 0x0f01);
3018                 tg3_readphy(tp, 0x15, &phy2);
3019                 if (phy2 & 0x20) {
3020                         u32 bmcr;
3021
3022                         /* Config code words received, turn on autoneg. */
3023                         tg3_readphy(tp, MII_BMCR, &bmcr);
3024                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3025
3026                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3027
3028                 }
3029         }
3030 }
3031
3032 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3033 {
3034         int err;
3035
3036         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3037                 err = tg3_setup_fiber_phy(tp, force_reset);
3038         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3039                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3040         } else {
3041                 err = tg3_setup_copper_phy(tp, force_reset);
3042         }
3043
3044         if (tp->link_config.active_speed == SPEED_1000 &&
3045             tp->link_config.active_duplex == DUPLEX_HALF)
3046                 tw32(MAC_TX_LENGTHS,
3047                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3048                       (6 << TX_LENGTHS_IPG_SHIFT) |
3049                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3050         else
3051                 tw32(MAC_TX_LENGTHS,
3052                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3053                       (6 << TX_LENGTHS_IPG_SHIFT) |
3054                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3055
3056         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3057                 if (netif_carrier_ok(tp->dev)) {
3058                         tw32(HOSTCC_STAT_COAL_TICKS,
3059                              tp->coal.stats_block_coalesce_usecs);
3060                 } else {
3061                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3062                 }
3063         }
3064
3065         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3066                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3067                 if (!netif_carrier_ok(tp->dev))
3068                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3069                               tp->pwrmgmt_thresh;
3070                 else
3071                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3072                 tw32(PCIE_PWR_MGMT_THRESH, val);
3073         }
3074
3075         return err;
3076 }
3077
3078 /* This is called whenever we suspect that the system chipset is re-
3079  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3080  * is bogus tx completions. We try to recover by setting the
3081  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3082  * in the workqueue.
3083  */
3084 static void tg3_tx_recover(struct tg3 *tp)
3085 {
3086         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3087                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3088
3089         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3090                "mapped I/O cycles to the network device, attempting to "
3091                "recover. Please report the problem to the driver maintainer "
3092                "and include system chipset information.\n", tp->dev->name);
3093
3094         spin_lock(&tp->lock);
3095         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3096         spin_unlock(&tp->lock);
3097 }
3098
3099 static inline u32 tg3_tx_avail(struct tg3 *tp)
3100 {
3101         smp_mb();
3102         return (tp->tx_pending -
3103                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3104 }
3105
3106 /* Tigon3 never reports partial packet sends.  So we do not
3107  * need special logic to handle SKBs that have not had all
3108  * of their frags sent yet, like SunGEM does.
3109  */
3110 static void tg3_tx(struct tg3 *tp)
3111 {
3112         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3113         u32 sw_idx = tp->tx_cons;
3114
3115         while (sw_idx != hw_idx) {
3116                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3117                 struct sk_buff *skb = ri->skb;
3118                 int i, tx_bug = 0;
3119
3120                 if (unlikely(skb == NULL)) {
3121                         tg3_tx_recover(tp);
3122                         return;
3123                 }
3124
3125                 pci_unmap_single(tp->pdev,
3126                                  pci_unmap_addr(ri, mapping),
3127                                  skb_headlen(skb),
3128                                  PCI_DMA_TODEVICE);
3129
3130                 ri->skb = NULL;
3131
3132                 sw_idx = NEXT_TX(sw_idx);
3133
3134                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3135                         ri = &tp->tx_buffers[sw_idx];
3136                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3137                                 tx_bug = 1;
3138
3139                         pci_unmap_page(tp->pdev,
3140                                        pci_unmap_addr(ri, mapping),
3141                                        skb_shinfo(skb)->frags[i].size,
3142                                        PCI_DMA_TODEVICE);
3143
3144                         sw_idx = NEXT_TX(sw_idx);
3145                 }
3146
3147                 dev_kfree_skb(skb);
3148
3149                 if (unlikely(tx_bug)) {
3150                         tg3_tx_recover(tp);
3151                         return;
3152                 }
3153         }
3154
3155         tp->tx_cons = sw_idx;
3156
3157         /* Need to make the tx_cons update visible to tg3_start_xmit()
3158          * before checking for netif_queue_stopped().  Without the
3159          * memory barrier, there is a small possibility that tg3_start_xmit()
3160          * will miss it and cause the queue to be stopped forever.
3161          */
3162         smp_mb();
3163
3164         if (unlikely(netif_queue_stopped(tp->dev) &&
3165                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3166                 netif_tx_lock(tp->dev);
3167                 if (netif_queue_stopped(tp->dev) &&
3168                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3169                         netif_wake_queue(tp->dev);
3170                 netif_tx_unlock(tp->dev);
3171         }
3172 }
3173
3174 /* Returns size of skb allocated or < 0 on error.
3175  *
3176  * We only need to fill in the address because the other members
3177  * of the RX descriptor are invariant, see tg3_init_rings.
3178  *
3179  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3180  * posting buffers we only dirty the first cache line of the RX
3181  * descriptor (containing the address).  Whereas for the RX status
3182  * buffers the cpu only reads the last cacheline of the RX descriptor
3183  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3184  */
3185 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3186                             int src_idx, u32 dest_idx_unmasked)
3187 {
3188         struct tg3_rx_buffer_desc *desc;
3189         struct ring_info *map, *src_map;
3190         struct sk_buff *skb;
3191         dma_addr_t mapping;
3192         int skb_size, dest_idx;
3193
3194         src_map = NULL;
3195         switch (opaque_key) {
3196         case RXD_OPAQUE_RING_STD:
3197                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3198                 desc = &tp->rx_std[dest_idx];
3199                 map = &tp->rx_std_buffers[dest_idx];
3200                 if (src_idx >= 0)
3201                         src_map = &tp->rx_std_buffers[src_idx];
3202                 skb_size = tp->rx_pkt_buf_sz;
3203                 break;
3204
3205         case RXD_OPAQUE_RING_JUMBO:
3206                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3207                 desc = &tp->rx_jumbo[dest_idx];
3208                 map = &tp->rx_jumbo_buffers[dest_idx];
3209                 if (src_idx >= 0)
3210                         src_map = &tp->rx_jumbo_buffers[src_idx];
3211                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3212                 break;
3213
3214         default:
3215                 return -EINVAL;
3216         };
3217
3218         /* Do not overwrite any of the map or rp information
3219          * until we are sure we can commit to a new buffer.
3220          *
3221          * Callers depend upon this behavior and assume that
3222          * we leave everything unchanged if we fail.
3223          */
3224         skb = netdev_alloc_skb(tp->dev, skb_size);
3225         if (skb == NULL)
3226                 return -ENOMEM;
3227
3228         skb_reserve(skb, tp->rx_offset);
3229
3230         mapping = pci_map_single(tp->pdev, skb->data,
3231                                  skb_size - tp->rx_offset,
3232                                  PCI_DMA_FROMDEVICE);
3233
3234         map->skb = skb;
3235         pci_unmap_addr_set(map, mapping, mapping);
3236
3237         if (src_map != NULL)
3238                 src_map->skb = NULL;
3239
3240         desc->addr_hi = ((u64)mapping >> 32);
3241         desc->addr_lo = ((u64)mapping & 0xffffffff);
3242
3243         return skb_size;
3244 }
3245
3246 /* We only need to move over in the address because the other
3247  * members of the RX descriptor are invariant.  See notes above
3248  * tg3_alloc_rx_skb for full details.
3249  */
3250 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3251                            int src_idx, u32 dest_idx_unmasked)
3252 {
3253         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3254         struct ring_info *src_map, *dest_map;
3255         int dest_idx;
3256
3257         switch (opaque_key) {
3258         case RXD_OPAQUE_RING_STD:
3259                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3260                 dest_desc = &tp->rx_std[dest_idx];
3261                 dest_map = &tp->rx_std_buffers[dest_idx];
3262                 src_desc = &tp->rx_std[src_idx];
3263                 src_map = &tp->rx_std_buffers[src_idx];
3264                 break;
3265
3266         case RXD_OPAQUE_RING_JUMBO:
3267                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3268                 dest_desc = &tp->rx_jumbo[dest_idx];
3269                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3270                 src_desc = &tp->rx_jumbo[src_idx];
3271                 src_map = &tp->rx_jumbo_buffers[src_idx];
3272                 break;
3273
3274         default:
3275                 return;
3276         };
3277
3278         dest_map->skb = src_map->skb;
3279         pci_unmap_addr_set(dest_map, mapping,
3280                            pci_unmap_addr(src_map, mapping));
3281         dest_desc->addr_hi = src_desc->addr_hi;
3282         dest_desc->addr_lo = src_desc->addr_lo;
3283
3284         src_map->skb = NULL;
3285 }
3286
3287 #if TG3_VLAN_TAG_USED
3288 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3289 {
3290         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3291 }
3292 #endif
3293
3294 /* The RX ring scheme is composed of multiple rings which post fresh
3295  * buffers to the chip, and one special ring the chip uses to report
3296  * status back to the host.
3297  *
3298  * The special ring reports the status of received packets to the
3299  * host.  The chip does not write into the original descriptor the
3300  * RX buffer was obtained from.  The chip simply takes the original
3301  * descriptor as provided by the host, updates the status and length
3302  * field, then writes this into the next status ring entry.
3303  *
3304  * Each ring the host uses to post buffers to the chip is described
3305  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3306  * it is first placed into the on-chip ram.  When the packet's length
3307  * is known, it walks down the TG3_BDINFO entries to select the ring.
3308  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3309  * which is within the range of the new packet's length is chosen.
3310  *
3311  * The "separate ring for rx status" scheme may sound queer, but it makes
3312  * sense from a cache coherency perspective.  If only the host writes
3313  * to the buffer post rings, and only the chip writes to the rx status
3314  * rings, then cache lines never move beyond shared-modified state.
3315  * If both the host and chip were to write into the same ring, cache line
3316  * eviction could occur since both entities want it in an exclusive state.
3317  */
3318 static int tg3_rx(struct tg3 *tp, int budget)
3319 {
3320         u32 work_mask, rx_std_posted = 0;
3321         u32 sw_idx = tp->rx_rcb_ptr;
3322         u16 hw_idx;
3323         int received;
3324
3325         hw_idx = tp->hw_status->idx[0].rx_producer;
3326         /*
3327          * We need to order the read of hw_idx and the read of
3328          * the opaque cookie.
3329          */
3330         rmb();
3331         work_mask = 0;
3332         received = 0;
3333         while (sw_idx != hw_idx && budget > 0) {
3334                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3335                 unsigned int len;
3336                 struct sk_buff *skb;
3337                 dma_addr_t dma_addr;
3338                 u32 opaque_key, desc_idx, *post_ptr;
3339
3340                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3341                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3342                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3343                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3344                                                   mapping);
3345                         skb = tp->rx_std_buffers[desc_idx].skb;
3346                         post_ptr = &tp->rx_std_ptr;
3347                         rx_std_posted++;
3348                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3349                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3350                                                   mapping);
3351                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3352                         post_ptr = &tp->rx_jumbo_ptr;
3353                 }
3354                 else {
3355                         goto next_pkt_nopost;
3356                 }
3357
3358                 work_mask |= opaque_key;
3359
3360                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3361                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3362                 drop_it:
3363                         tg3_recycle_rx(tp, opaque_key,
3364                                        desc_idx, *post_ptr);
3365                 drop_it_no_recycle:
3366                         /* Other statistics kept track of by card. */
3367                         tp->net_stats.rx_dropped++;
3368                         goto next_pkt;
3369                 }
3370
3371                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3372
3373                 if (len > RX_COPY_THRESHOLD
3374                         && tp->rx_offset == 2
3375                         /* rx_offset != 2 iff this is a 5701 card running
3376                          * in PCI-X mode [see tg3_get_invariants()] */
3377                 ) {
3378                         int skb_size;
3379
3380                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3381                                                     desc_idx, *post_ptr);
3382                         if (skb_size < 0)
3383                                 goto drop_it;
3384
3385                         pci_unmap_single(tp->pdev, dma_addr,
3386                                          skb_size - tp->rx_offset,
3387                                          PCI_DMA_FROMDEVICE);
3388
3389                         skb_put(skb, len);
3390                 } else {
3391                         struct sk_buff *copy_skb;
3392
3393                         tg3_recycle_rx(tp, opaque_key,
3394                                        desc_idx, *post_ptr);
3395
3396                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3397                         if (copy_skb == NULL)
3398                                 goto drop_it_no_recycle;
3399
3400                         skb_reserve(copy_skb, 2);
3401                         skb_put(copy_skb, len);
3402                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3403                         skb_copy_from_linear_data(skb, copy_skb->data, len);
3404                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3405
3406                         /* We'll reuse the original ring buffer. */
3407                         skb = copy_skb;
3408                 }
3409
3410                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3411                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3412                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3413                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3414                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3415                 else
3416                         skb->ip_summed = CHECKSUM_NONE;
3417
3418                 skb->protocol = eth_type_trans(skb, tp->dev);
3419 #if TG3_VLAN_TAG_USED
3420                 if (tp->vlgrp != NULL &&
3421                     desc->type_flags & RXD_FLAG_VLAN) {
3422                         tg3_vlan_rx(tp, skb,
3423                                     desc->err_vlan & RXD_VLAN_MASK);
3424                 } else
3425 #endif
3426                         netif_receive_skb(skb);
3427
3428                 tp->dev->last_rx = jiffies;
3429                 received++;
3430                 budget--;
3431
3432 next_pkt:
3433                 (*post_ptr)++;
3434
3435                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3436                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3437
3438                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3439                                      TG3_64BIT_REG_LOW, idx);
3440                         work_mask &= ~RXD_OPAQUE_RING_STD;
3441                         rx_std_posted = 0;
3442                 }
3443 next_pkt_nopost:
3444                 sw_idx++;
3445                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3446
3447                 /* Refresh hw_idx to see if there is new work */
3448                 if (sw_idx == hw_idx) {
3449                         hw_idx = tp->hw_status->idx[0].rx_producer;
3450                         rmb();
3451                 }
3452         }
3453
3454         /* ACK the status ring. */
3455         tp->rx_rcb_ptr = sw_idx;
3456         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3457
3458         /* Refill RX ring(s). */
3459         if (work_mask & RXD_OPAQUE_RING_STD) {
3460                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3461                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3462                              sw_idx);
3463         }
3464         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3465                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3466                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3467                              sw_idx);
3468         }
3469         mmiowb();
3470
3471         return received;
3472 }
3473
3474 static int tg3_poll(struct net_device *netdev, int *budget)
3475 {
3476         struct tg3 *tp = netdev_priv(netdev);
3477         struct tg3_hw_status *sblk = tp->hw_status;
3478         int done;
3479
3480         /* handle link change and other phy events */
3481         if (!(tp->tg3_flags &
3482               (TG3_FLAG_USE_LINKCHG_REG |
3483                TG3_FLAG_POLL_SERDES))) {
3484                 if (sblk->status & SD_STATUS_LINK_CHG) {
3485                         sblk->status = SD_STATUS_UPDATED |
3486                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3487                         spin_lock(&tp->lock);
3488                         tg3_setup_phy(tp, 0);
3489                         spin_unlock(&tp->lock);
3490                 }
3491         }
3492
3493         /* run TX completion thread */
3494         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3495                 tg3_tx(tp);
3496                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3497                         netif_rx_complete(netdev);
3498                         schedule_work(&tp->reset_task);
3499                         return 0;
3500                 }
3501         }
3502
3503         /* run RX thread, within the bounds set by NAPI.
3504          * All RX "locking" is done by ensuring outside
3505          * code synchronizes with dev->poll()
3506          */
3507         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3508                 int orig_budget = *budget;
3509                 int work_done;
3510
3511                 if (orig_budget > netdev->quota)
3512                         orig_budget = netdev->quota;
3513
3514                 work_done = tg3_rx(tp, orig_budget);
3515
3516                 *budget -= work_done;
3517                 netdev->quota -= work_done;
3518         }
3519
3520         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3521                 tp->last_tag = sblk->status_tag;
3522                 rmb();
3523         } else
3524                 sblk->status &= ~SD_STATUS_UPDATED;
3525
3526         /* if no more work, tell net stack and NIC we're done */
3527         done = !tg3_has_work(tp);
3528         if (done) {
3529                 netif_rx_complete(netdev);
3530                 tg3_restart_ints(tp);
3531         }
3532
3533         return (done ? 0 : 1);
3534 }
3535
3536 static void tg3_irq_quiesce(struct tg3 *tp)
3537 {
3538         BUG_ON(tp->irq_sync);
3539
3540         tp->irq_sync = 1;
3541         smp_mb();
3542
3543         synchronize_irq(tp->pdev->irq);
3544 }
3545
3546 static inline int tg3_irq_sync(struct tg3 *tp)
3547 {
3548         return tp->irq_sync;
3549 }
3550
3551 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3552  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3553  * with as well.  Most of the time, this is not necessary except when
3554  * shutting down the device.
3555  */
3556 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3557 {
3558         spin_lock_bh(&tp->lock);
3559         if (irq_sync)
3560                 tg3_irq_quiesce(tp);
3561 }
3562
3563 static inline void tg3_full_unlock(struct tg3 *tp)
3564 {
3565         spin_unlock_bh(&tp->lock);
3566 }
3567
3568 /* One-shot MSI handler - Chip automatically disables interrupt
3569  * after sending MSI so driver doesn't have to do it.
3570  */
3571 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3572 {
3573         struct net_device *dev = dev_id;
3574         struct tg3 *tp = netdev_priv(dev);
3575
3576         prefetch(tp->hw_status);
3577         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3578
3579         if (likely(!tg3_irq_sync(tp)))
3580                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3581
3582         return IRQ_HANDLED;
3583 }
3584
3585 /* MSI ISR - No need to check for interrupt sharing and no need to
3586  * flush status block and interrupt mailbox. PCI ordering rules
3587  * guarantee that MSI will arrive after the status block.
3588  */
3589 static irqreturn_t tg3_msi(int irq, void *dev_id)
3590 {
3591         struct net_device *dev = dev_id;
3592         struct tg3 *tp = netdev_priv(dev);
3593
3594         prefetch(tp->hw_status);
3595         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3596         /*
3597          * Writing any value to intr-mbox-0 clears PCI INTA# and
3598          * chip-internal interrupt pending events.
3599          * Writing non-zero to intr-mbox-0 additional tells the
3600          * NIC to stop sending us irqs, engaging "in-intr-handler"
3601          * event coalescing.
3602          */
3603         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3604         if (likely(!tg3_irq_sync(tp)))
3605                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3606
3607         return IRQ_RETVAL(1);
3608 }
3609
3610 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3611 {
3612         struct net_device *dev = dev_id;
3613         struct tg3 *tp = netdev_priv(dev);
3614         struct tg3_hw_status *sblk = tp->hw_status;
3615         unsigned int handled = 1;
3616
3617         /* In INTx mode, it is possible for the interrupt to arrive at
3618          * the CPU before the status block posted prior to the interrupt.
3619          * Reading the PCI State register will confirm whether the
3620          * interrupt is ours and will flush the status block.
3621          */
3622         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3623                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3624                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3625                         handled = 0;
3626                         goto out;
3627                 }
3628         }
3629
3630         /*
3631          * Writing any value to intr-mbox-0 clears PCI INTA# and
3632          * chip-internal interrupt pending events.
3633          * Writing non-zero to intr-mbox-0 additional tells the
3634          * NIC to stop sending us irqs, engaging "in-intr-handler"
3635          * event coalescing.
3636          *
3637          * Flush the mailbox to de-assert the IRQ immediately to prevent
3638          * spurious interrupts.  The flush impacts performance but
3639          * excessive spurious interrupts can be worse in some cases.
3640          */
3641         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3642         if (tg3_irq_sync(tp))
3643                 goto out;
3644         sblk->status &= ~SD_STATUS_UPDATED;
3645         if (likely(tg3_has_work(tp))) {
3646                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3647                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3648         } else {
3649                 /* No work, shared interrupt perhaps?  re-enable
3650                  * interrupts, and flush that PCI write
3651                  */
3652                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3653                                0x00000000);
3654         }
3655 out:
3656         return IRQ_RETVAL(handled);
3657 }
3658
3659 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3660 {
3661         struct net_device *dev = dev_id;
3662         struct tg3 *tp = netdev_priv(dev);
3663         struct tg3_hw_status *sblk = tp->hw_status;
3664         unsigned int handled = 1;
3665
3666         /* In INTx mode, it is possible for the interrupt to arrive at
3667          * the CPU before the status block posted prior to the interrupt.
3668          * Reading the PCI State register will confirm whether the
3669          * interrupt is ours and will flush the status block.
3670          */
3671         if (unlikely(sblk->status_tag == tp->last_tag)) {
3672                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3673                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3674                         handled = 0;
3675                         goto out;
3676                 }
3677         }
3678
3679         /*
3680          * writing any value to intr-mbox-0 clears PCI INTA# and
3681          * chip-internal interrupt pending events.
3682          * writing non-zero to intr-mbox-0 additional tells the
3683          * NIC to stop sending us irqs, engaging "in-intr-handler"
3684          * event coalescing.
3685          *
3686          * Flush the mailbox to de-assert the IRQ immediately to prevent
3687          * spurious interrupts.  The flush impacts performance but
3688          * excessive spurious interrupts can be worse in some cases.
3689          */
3690         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3691         if (tg3_irq_sync(tp))
3692                 goto out;
3693         if (netif_rx_schedule_prep(dev)) {
3694                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3695                 /* Update last_tag to mark that this status has been
3696                  * seen. Because interrupt may be shared, we may be
3697                  * racing with tg3_poll(), so only update last_tag
3698                  * if tg3_poll() is not scheduled.
3699                  */
3700                 tp->last_tag = sblk->status_tag;
3701                 __netif_rx_schedule(dev);
3702         }
3703 out:
3704         return IRQ_RETVAL(handled);
3705 }
3706
3707 /* ISR for interrupt test */
3708 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3709 {
3710         struct net_device *dev = dev_id;
3711         struct tg3 *tp = netdev_priv(dev);
3712         struct tg3_hw_status *sblk = tp->hw_status;
3713
3714         if ((sblk->status & SD_STATUS_UPDATED) ||
3715             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3716                 tg3_disable_ints(tp);
3717                 return IRQ_RETVAL(1);
3718         }
3719         return IRQ_RETVAL(0);
3720 }
3721
3722 static int tg3_init_hw(struct tg3 *, int);
3723 static int tg3_halt(struct tg3 *, int, int);
3724
3725 /* Restart hardware after configuration changes, self-test, etc.
3726  * Invoked with tp->lock held.
3727  */
3728 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3729 {
3730         int err;
3731
3732         err = tg3_init_hw(tp, reset_phy);
3733         if (err) {
3734                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3735                        "aborting.\n", tp->dev->name);
3736                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3737                 tg3_full_unlock(tp);
3738                 del_timer_sync(&tp->timer);
3739                 tp->irq_sync = 0;
3740                 netif_poll_enable(tp->dev);
3741                 dev_close(tp->dev);
3742                 tg3_full_lock(tp, 0);
3743         }
3744         return err;
3745 }
3746
3747 #ifdef CONFIG_NET_POLL_CONTROLLER
3748 static void tg3_poll_controller(struct net_device *dev)
3749 {
3750         struct tg3 *tp = netdev_priv(dev);
3751
3752         tg3_interrupt(tp->pdev->irq, dev);
3753 }
3754 #endif
3755
3756 static void tg3_reset_task(struct work_struct *work)
3757 {
3758         struct tg3 *tp = container_of(work, struct tg3, reset_task);
3759         unsigned int restart_timer;
3760
3761         tg3_full_lock(tp, 0);
3762
3763         if (!netif_running(tp->dev)) {
3764                 tg3_full_unlock(tp);
3765                 return;
3766         }
3767
3768         tg3_full_unlock(tp);
3769
3770         tg3_netif_stop(tp);
3771
3772         tg3_full_lock(tp, 1);
3773
3774         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3775         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3776
3777         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3778                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3779                 tp->write32_rx_mbox = tg3_write_flush_reg32;
3780                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3781                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3782         }
3783
3784         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3785         if (tg3_init_hw(tp, 1))
3786                 goto out;
3787
3788         tg3_netif_start(tp);
3789
3790         if (restart_timer)
3791                 mod_timer(&tp->timer, jiffies + 1);
3792
3793 out:
3794         tg3_full_unlock(tp);
3795 }
3796
3797 static void tg3_dump_short_state(struct tg3 *tp)
3798 {
3799         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3800                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3801         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3802                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3803 }
3804
3805 static void tg3_tx_timeout(struct net_device *dev)
3806 {
3807         struct tg3 *tp = netdev_priv(dev);
3808
3809         if (netif_msg_tx_err(tp)) {
3810                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3811                        dev->name);
3812                 tg3_dump_short_state(tp);
3813         }
3814
3815         schedule_work(&tp->reset_task);
3816 }
3817
3818 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3819 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3820 {
3821         u32 base = (u32) mapping & 0xffffffff;
3822
3823         return ((base > 0xffffdcc0) &&
3824                 (base + len + 8 < base));
3825 }
3826
3827 /* Test for DMA addresses > 40-bit */
3828 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3829                                           int len)
3830 {
3831 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3832         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3833                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3834         return 0;
3835 #else
3836         return 0;
3837 #endif
3838 }
3839
3840 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3841
3842 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3843 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3844                                        u32 last_plus_one, u32 *start,
3845                                        u32 base_flags, u32 mss)
3846 {
3847         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3848         dma_addr_t new_addr = 0;
3849         u32 entry = *start;
3850         int i, ret = 0;
3851
3852         if (!new_skb) {
3853                 ret = -1;
3854         } else {
3855                 /* New SKB is guaranteed to be linear. */
3856                 entry = *start;
3857                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3858                                           PCI_DMA_TODEVICE);
3859                 /* Make sure new skb does not cross any 4G boundaries.
3860                  * Drop the packet if it does.
3861                  */
3862                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3863                         ret = -1;
3864                         dev_kfree_skb(new_skb);
3865                         new_skb = NULL;
3866                 } else {
3867                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3868                                     base_flags, 1 | (mss << 1));
3869                         *start = NEXT_TX(entry);
3870                 }
3871         }
3872
3873         /* Now clean up the sw ring entries. */
3874         i = 0;
3875         while (entry != last_plus_one) {
3876                 int len;
3877
3878                 if (i == 0)
3879                         len = skb_headlen(skb);
3880                 else
3881                         len = skb_shinfo(skb)->frags[i-1].size;
3882                 pci_unmap_single(tp->pdev,
3883                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3884                                  len, PCI_DMA_TODEVICE);
3885                 if (i == 0) {
3886                         tp->tx_buffers[entry].skb = new_skb;
3887                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3888                 } else {
3889                         tp->tx_buffers[entry].skb = NULL;
3890                 }
3891                 entry = NEXT_TX(entry);
3892                 i++;
3893         }
3894
3895         dev_kfree_skb(skb);
3896
3897         return ret;
3898 }
3899
3900 static void tg3_set_txd(struct tg3 *tp, int entry,
3901                         dma_addr_t mapping, int len, u32 flags,
3902                         u32 mss_and_is_end)
3903 {
3904         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3905         int is_end = (mss_and_is_end & 0x1);
3906         u32 mss = (mss_and_is_end >> 1);
3907         u32 vlan_tag = 0;
3908
3909         if (is_end)
3910                 flags |= TXD_FLAG_END;
3911         if (flags & TXD_FLAG_VLAN) {
3912                 vlan_tag = flags >> 16;
3913                 flags &= 0xffff;
3914         }
3915         vlan_tag |= (mss << TXD_MSS_SHIFT);
3916
3917         txd->addr_hi = ((u64) mapping >> 32);
3918         txd->addr_lo = ((u64) mapping & 0xffffffff);
3919         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3920         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3921 }
3922
3923 /* hard_start_xmit for devices that don't have any bugs and
3924  * support TG3_FLG2_HW_TSO_2 only.
3925  */
3926 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3927 {
3928         struct tg3 *tp = netdev_priv(dev);
3929         dma_addr_t mapping;
3930         u32 len, entry, base_flags, mss;
3931
3932         len = skb_headlen(skb);
3933
3934         /* We are running in BH disabled context with netif_tx_lock
3935          * and TX reclaim runs via tp->poll inside of a software
3936          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3937          * no IRQ context deadlocks to worry about either.  Rejoice!
3938          */
3939         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3940                 if (!netif_queue_stopped(dev)) {
3941                         netif_stop_queue(dev);
3942
3943                         /* This is a hard error, log it. */
3944                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3945                                "queue awake!\n", dev->name);
3946                 }
3947                 return NETDEV_TX_BUSY;
3948         }
3949
3950         entry = tp->tx_prod;
3951         base_flags = 0;
3952         mss = 0;
3953         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
3954                 int tcp_opt_len, ip_tcp_len;
3955
3956                 if (skb_header_cloned(skb) &&
3957                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3958                         dev_kfree_skb(skb);
3959                         goto out_unlock;
3960                 }
3961
3962                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3963                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3964                 else {
3965                         struct iphdr *iph = ip_hdr(skb);
3966
3967                         tcp_opt_len = tcp_optlen(skb);
3968                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
3969
3970                         iph->check = 0;
3971                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3972                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
3973                 }
3974
3975                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3976                                TXD_FLAG_CPU_POST_DMA);
3977
3978                 tcp_hdr(skb)->check = 0;
3979
3980         }
3981         else if (skb->ip_summed == CHECKSUM_PARTIAL)
3982                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3983 #if TG3_VLAN_TAG_USED
3984         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3985                 base_flags |= (TXD_FLAG_VLAN |
3986                                (vlan_tx_tag_get(skb) << 16));
3987 #endif
3988
3989         /* Queue skb data, a.k.a. the main skb fragment. */
3990         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3991
3992         tp->tx_buffers[entry].skb = skb;
3993         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3994
3995         tg3_set_txd(tp, entry, mapping, len, base_flags,
3996                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3997
3998         entry = NEXT_TX(entry);
3999
4000         /* Now loop through additional data fragments, and queue them. */
4001         if (skb_shinfo(skb)->nr_frags > 0) {
4002                 unsigned int i, last;
4003
4004                 last = skb_shinfo(skb)->nr_frags - 1;
4005                 for (i = 0; i <= last; i++) {
4006                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4007
4008                         len = frag->size;
4009                         mapping = pci_map_page(tp->pdev,
4010                                                frag->page,
4011                                                frag->page_offset,
4012                                                len, PCI_DMA_TODEVICE);
4013
4014                         tp->tx_buffers[entry].skb = NULL;
4015                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4016
4017                         tg3_set_txd(tp, entry, mapping, len,
4018                                     base_flags, (i == last) | (mss << 1));
4019
4020                         entry = NEXT_TX(entry);
4021                 }
4022         }
4023
4024         /* Packets are ready, update Tx producer idx local and on card. */
4025         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4026
4027         tp->tx_prod = entry;
4028         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4029                 netif_stop_queue(dev);
4030                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4031                         netif_wake_queue(tp->dev);
4032         }
4033
4034 out_unlock:
4035         mmiowb();
4036
4037         dev->trans_start = jiffies;
4038
4039         return NETDEV_TX_OK;
4040 }
4041
4042 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4043
4044 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4045  * TSO header is greater than 80 bytes.
4046  */
4047 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4048 {
4049         struct sk_buff *segs, *nskb;
4050
4051         /* Estimate the number of fragments in the worst case */
4052         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4053                 netif_stop_queue(tp->dev);
4054                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4055                         return NETDEV_TX_BUSY;
4056
4057                 netif_wake_queue(tp->dev);
4058         }
4059
4060         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4061         if (unlikely(IS_ERR(segs)))
4062                 goto tg3_tso_bug_end;
4063
4064         do {
4065                 nskb = segs;
4066                 segs = segs->next;
4067                 nskb->next = NULL;
4068                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4069         } while (segs);
4070
4071 tg3_tso_bug_end:
4072         dev_kfree_skb(skb);
4073
4074         return NETDEV_TX_OK;
4075 }
4076
4077 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4078  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4079  */
4080 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4081 {
4082         struct tg3 *tp = netdev_priv(dev);
4083         dma_addr_t mapping;
4084         u32 len, entry, base_flags, mss;
4085         int would_hit_hwbug;
4086
4087         len = skb_headlen(skb);
4088
4089         /* We are running in BH disabled context with netif_tx_lock
4090          * and TX reclaim runs via tp->poll inside of a software
4091          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4092          * no IRQ context deadlocks to worry about either.  Rejoice!
4093          */
4094         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4095                 if (!netif_queue_stopped(dev)) {
4096                         netif_stop_queue(dev);
4097
4098                         /* This is a hard error, log it. */
4099                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4100                                "queue awake!\n", dev->name);
4101                 }
4102                 return NETDEV_TX_BUSY;
4103         }
4104
4105         entry = tp->tx_prod;
4106         base_flags = 0;
4107         if (skb->ip_summed == CHECKSUM_PARTIAL)
4108                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4109         mss = 0;
4110         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4111                 struct iphdr *iph;
4112                 int tcp_opt_len, ip_tcp_len, hdr_len;
4113
4114                 if (skb_header_cloned(skb) &&
4115                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4116                         dev_kfree_skb(skb);
4117                         goto out_unlock;
4118                 }
4119
4120                 tcp_opt_len = tcp_optlen(skb);
4121                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4122
4123                 hdr_len = ip_tcp_len + tcp_opt_len;
4124                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4125                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4126                         return (tg3_tso_bug(tp, skb));
4127
4128                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4129                                TXD_FLAG_CPU_POST_DMA);
4130
4131                 iph = ip_hdr(skb);
4132                 iph->check = 0;
4133                 iph->tot_len = htons(mss + hdr_len);
4134                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4135                         tcp_hdr(skb)->check = 0;
4136                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4137                 } else
4138                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4139                                                                  iph->daddr, 0,
4140                                                                  IPPROTO_TCP,
4141                                                                  0);
4142
4143                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4144                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4145                         if (tcp_opt_len || iph->ihl > 5) {
4146                                 int tsflags;
4147
4148                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4149                                 mss |= (tsflags << 11);
4150                         }
4151                 } else {
4152                         if (tcp_opt_len || iph->ihl > 5) {
4153                                 int tsflags;
4154
4155                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4156                                 base_flags |= tsflags << 12;
4157                         }
4158                 }
4159         }
4160 #if TG3_VLAN_TAG_USED
4161         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4162                 base_flags |= (TXD_FLAG_VLAN |
4163                                (vlan_tx_tag_get(skb) << 16));
4164 #endif
4165
4166         /* Queue skb data, a.k.a. the main skb fragment. */
4167         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4168
4169         tp->tx_buffers[entry].skb = skb;
4170         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4171
4172         would_hit_hwbug = 0;
4173
4174         if (tg3_4g_overflow_test(mapping, len))
4175                 would_hit_hwbug = 1;
4176
4177         tg3_set_txd(tp, entry, mapping, len, base_flags,
4178                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4179
4180         entry = NEXT_TX(entry);
4181
4182         /* Now loop through additional data fragments, and queue them. */
4183         if (skb_shinfo(skb)->nr_frags > 0) {
4184                 unsigned int i, last;
4185
4186                 last = skb_shinfo(skb)->nr_frags - 1;
4187                 for (i = 0; i <= last; i++) {
4188                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4189
4190                         len = frag->size;
4191                         mapping = pci_map_page(tp->pdev,
4192                                                frag->page,
4193                                                frag->page_offset,
4194                                                len, PCI_DMA_TODEVICE);
4195
4196                         tp->tx_buffers[entry].skb = NULL;
4197                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4198
4199                         if (tg3_4g_overflow_test(mapping, len))
4200                                 would_hit_hwbug = 1;
4201
4202                         if (tg3_40bit_overflow_test(tp, mapping, len))
4203                                 would_hit_hwbug = 1;
4204
4205                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4206                                 tg3_set_txd(tp, entry, mapping, len,
4207                                             base_flags, (i == last)|(mss << 1));
4208                         else
4209                                 tg3_set_txd(tp, entry, mapping, len,
4210                                             base_flags, (i == last));
4211
4212                         entry = NEXT_TX(entry);
4213                 }
4214         }
4215
4216         if (would_hit_hwbug) {
4217                 u32 last_plus_one = entry;
4218                 u32 start;
4219
4220                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4221                 start &= (TG3_TX_RING_SIZE - 1);
4222
4223                 /* If the workaround fails due to memory/mapping
4224                  * failure, silently drop this packet.
4225                  */
4226                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4227                                                 &start, base_flags, mss))
4228                         goto out_unlock;
4229
4230                 entry = start;
4231         }
4232
4233         /* Packets are ready, update Tx producer idx local and on card. */
4234         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4235
4236         tp->tx_prod = entry;
4237         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4238                 netif_stop_queue(dev);
4239                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4240                         netif_wake_queue(tp->dev);
4241         }
4242
4243 out_unlock:
4244         mmiowb();
4245
4246         dev->trans_start = jiffies;
4247
4248         return NETDEV_TX_OK;
4249 }
4250
4251 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4252                                int new_mtu)
4253 {
4254         dev->mtu = new_mtu;
4255
4256         if (new_mtu > ETH_DATA_LEN) {
4257                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4258                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4259                         ethtool_op_set_tso(dev, 0);
4260                 }
4261                 else
4262                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4263         } else {
4264                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4265                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4266                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4267         }
4268 }
4269
4270 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4271 {
4272         struct tg3 *tp = netdev_priv(dev);
4273         int err;
4274
4275         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4276                 return -EINVAL;
4277
4278         if (!netif_running(dev)) {
4279                 /* We'll just catch it later when the
4280                  * device is up'd.
4281                  */
4282                 tg3_set_mtu(dev, tp, new_mtu);
4283                 return 0;
4284         }
4285
4286         tg3_netif_stop(tp);
4287
4288         tg3_full_lock(tp, 1);
4289
4290         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4291
4292         tg3_set_mtu(dev, tp, new_mtu);
4293
4294         err = tg3_restart_hw(tp, 0);
4295
4296         if (!err)
4297                 tg3_netif_start(tp);
4298
4299         tg3_full_unlock(tp);
4300
4301         return err;
4302 }
4303
4304 /* Free up pending packets in all rx/tx rings.
4305  *
4306  * The chip has been shut down and the driver detached from
4307  * the networking, so no interrupts or new tx packets will
4308  * end up in the driver.  tp->{tx,}lock is not held and we are not
4309  * in an interrupt context and thus may sleep.
4310  */
4311 static void tg3_free_rings(struct tg3 *tp)
4312 {
4313         struct ring_info *rxp;
4314         int i;
4315
4316         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4317                 rxp = &tp->rx_std_buffers[i];
4318
4319                 if (rxp->skb == NULL)
4320                         continue;
4321                 pci_unmap_single(tp->pdev,
4322                                  pci_unmap_addr(rxp, mapping),
4323                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4324                                  PCI_DMA_FROMDEVICE);
4325                 dev_kfree_skb_any(rxp->skb);
4326                 rxp->skb = NULL;
4327         }
4328
4329         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4330                 rxp = &tp->rx_jumbo_buffers[i];
4331
4332                 if (rxp->skb == NULL)
4333                         continue;
4334                 pci_unmap_single(tp->pdev,
4335                                  pci_unmap_addr(rxp, mapping),
4336                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4337                                  PCI_DMA_FROMDEVICE);
4338                 dev_kfree_skb_any(rxp->skb);
4339                 rxp->skb = NULL;
4340         }
4341
4342         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4343                 struct tx_ring_info *txp;
4344                 struct sk_buff *skb;
4345                 int j;
4346
4347                 txp = &tp->tx_buffers[i];
4348                 skb = txp->skb;
4349
4350                 if (skb == NULL) {
4351                         i++;
4352                         continue;
4353                 }
4354
4355                 pci_unmap_single(tp->pdev,
4356                                  pci_unmap_addr(txp, mapping),
4357                                  skb_headlen(skb),
4358                                  PCI_DMA_TODEVICE);
4359                 txp->skb = NULL;
4360
4361                 i++;
4362
4363                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4364                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4365                         pci_unmap_page(tp->pdev,
4366                                        pci_unmap_addr(txp, mapping),
4367                                        skb_shinfo(skb)->frags[j].size,
4368                                        PCI_DMA_TODEVICE);
4369                         i++;
4370                 }
4371
4372                 dev_kfree_skb_any(skb);
4373         }
4374 }
4375
4376 /* Initialize tx/rx rings for packet processing.
4377  *
4378  * The chip has been shut down and the driver detached from
4379  * the networking, so no interrupts or new tx packets will
4380  * end up in the driver.  tp->{tx,}lock are held and thus
4381  * we may not sleep.
4382  */
4383 static int tg3_init_rings(struct tg3 *tp)
4384 {
4385         u32 i;
4386
4387         /* Free up all the SKBs. */
4388         tg3_free_rings(tp);
4389
4390         /* Zero out all descriptors. */
4391         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4392         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4393         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4394         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4395
4396         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4397         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4398             (tp->dev->mtu > ETH_DATA_LEN))
4399                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4400
4401         /* Initialize invariants of the rings, we only set this
4402          * stuff once.  This works because the card does not
4403          * write into the rx buffer posting rings.
4404          */
4405         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4406                 struct tg3_rx_buffer_desc *rxd;
4407
4408                 rxd = &tp->rx_std[i];
4409                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4410                         << RXD_LEN_SHIFT;
4411                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4412                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4413                                (i << RXD_OPAQUE_INDEX_SHIFT));
4414         }
4415
4416         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4417                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4418                         struct tg3_rx_buffer_desc *rxd;
4419
4420                         rxd = &tp->rx_jumbo[i];
4421                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4422                                 << RXD_LEN_SHIFT;
4423                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4424                                 RXD_FLAG_JUMBO;
4425                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4426                                (i << RXD_OPAQUE_INDEX_SHIFT));
4427                 }
4428         }
4429
4430         /* Now allocate fresh SKBs for each rx ring. */
4431         for (i = 0; i < tp->rx_pending; i++) {
4432                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4433                         printk(KERN_WARNING PFX
4434                                "%s: Using a smaller RX standard ring, "
4435                                "only %d out of %d buffers were allocated "
4436                                "successfully.\n",
4437                                tp->dev->name, i, tp->rx_pending);
4438                         if (i == 0)
4439                                 return -ENOMEM;
4440                         tp->rx_pending = i;
4441                         break;
4442                 }
4443         }
4444
4445         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4446                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4447                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4448                                              -1, i) < 0) {
4449                                 printk(KERN_WARNING PFX
4450                                        "%s: Using a smaller RX jumbo ring, "
4451                                        "only %d out of %d buffers were "
4452                                        "allocated successfully.\n",
4453                                        tp->dev->name, i, tp->rx_jumbo_pending);
4454                                 if (i == 0) {
4455                                         tg3_free_rings(tp);
4456                                         return -ENOMEM;
4457                                 }
4458                                 tp->rx_jumbo_pending = i;
4459                                 break;
4460                         }
4461                 }
4462         }
4463         return 0;
4464 }
4465
4466 /*
4467  * Must not be invoked with interrupt sources disabled and
4468  * the hardware shutdown down.
4469  */
4470 static void tg3_free_consistent(struct tg3 *tp)
4471 {
4472         kfree(tp->rx_std_buffers);
4473         tp->rx_std_buffers = NULL;
4474         if (tp->rx_std) {
4475                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4476                                     tp->rx_std, tp->rx_std_mapping);
4477                 tp->rx_std = NULL;
4478         }
4479         if (tp->rx_jumbo) {
4480                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4481                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4482                 tp->rx_jumbo = NULL;
4483         }
4484         if (tp->rx_rcb) {
4485                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4486                                     tp->rx_rcb, tp->rx_rcb_mapping);
4487                 tp->rx_rcb = NULL;
4488         }
4489         if (tp->tx_ring) {
4490                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4491                         tp->tx_ring, tp->tx_desc_mapping);
4492                 tp->tx_ring = NULL;
4493         }
4494         if (tp->hw_status) {
4495                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4496                                     tp->hw_status, tp->status_mapping);
4497                 tp->hw_status = NULL;
4498         }
4499         if (tp->hw_stats) {
4500                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4501                                     tp->hw_stats, tp->stats_mapping);
4502                 tp->hw_stats = NULL;
4503         }
4504 }
4505
4506 /*
4507  * Must not be invoked with interrupt sources disabled and
4508  * the hardware shutdown down.  Can sleep.
4509  */
4510 static int tg3_alloc_consistent(struct tg3 *tp)
4511 {
4512         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4513                                       (TG3_RX_RING_SIZE +
4514                                        TG3_RX_JUMBO_RING_SIZE)) +
4515                                      (sizeof(struct tx_ring_info) *
4516                                       TG3_TX_RING_SIZE),
4517                                      GFP_KERNEL);
4518         if (!tp->rx_std_buffers)
4519                 return -ENOMEM;
4520
4521         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4522         tp->tx_buffers = (struct tx_ring_info *)
4523                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4524
4525         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4526                                           &tp->rx_std_mapping);
4527         if (!tp->rx_std)
4528                 goto err_out;
4529
4530         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4531                                             &tp->rx_jumbo_mapping);
4532
4533         if (!tp->rx_jumbo)
4534                 goto err_out;
4535
4536         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4537                                           &tp->rx_rcb_mapping);
4538         if (!tp->rx_rcb)
4539                 goto err_out;
4540
4541         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4542                                            &tp->tx_desc_mapping);
4543         if (!tp->tx_ring)
4544                 goto err_out;
4545
4546         tp->hw_status = pci_alloc_consistent(tp->pdev,
4547                                              TG3_HW_STATUS_SIZE,
4548                                              &tp->status_mapping);
4549         if (!tp->hw_status)
4550                 goto err_out;
4551
4552         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4553                                             sizeof(struct tg3_hw_stats),
4554                                             &tp->stats_mapping);
4555         if (!tp->hw_stats)
4556                 goto err_out;
4557
4558         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4559         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4560
4561         return 0;
4562
4563 err_out:
4564         tg3_free_consistent(tp);
4565         return -ENOMEM;
4566 }
4567
4568 #define MAX_WAIT_CNT 1000
4569
4570 /* To stop a block, clear the enable bit and poll till it
4571  * clears.  tp->lock is held.
4572  */
4573 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4574 {
4575         unsigned int i;
4576         u32 val;
4577
4578         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4579                 switch (ofs) {
4580                 case RCVLSC_MODE:
4581                 case DMAC_MODE:
4582                 case MBFREE_MODE:
4583                 case BUFMGR_MODE:
4584                 case MEMARB_MODE:
4585                         /* We can't enable/disable these bits of the
4586                          * 5705/5750, just say success.
4587                          */
4588                         return 0;
4589
4590                 default:
4591                         break;
4592                 };
4593         }
4594
4595         val = tr32(ofs);
4596         val &= ~enable_bit;
4597         tw32_f(ofs, val);
4598
4599         for (i = 0; i < MAX_WAIT_CNT; i++) {
4600                 udelay(100);
4601                 val = tr32(ofs);
4602                 if ((val & enable_bit) == 0)
4603                         break;
4604         }
4605
4606         if (i == MAX_WAIT_CNT && !silent) {
4607                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4608                        "ofs=%lx enable_bit=%x\n",
4609                        ofs, enable_bit);
4610                 return -ENODEV;
4611         }
4612
4613         return 0;
4614 }
4615
4616 /* tp->lock is held. */
4617 static int tg3_abort_hw(struct tg3 *tp, int silent)
4618 {
4619         int i, err;
4620
4621         tg3_disable_ints(tp);
4622
4623         tp->rx_mode &= ~RX_MODE_ENABLE;
4624         tw32_f(MAC_RX_MODE, tp->rx_mode);
4625         udelay(10);
4626
4627         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4628         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4629         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4630         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4631         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4632         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4633
4634         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4635         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4636         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4637         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4638         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4639         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4640         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4641
4642         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4643         tw32_f(MAC_MODE, tp->mac_mode);
4644         udelay(40);
4645
4646         tp->tx_mode &= ~TX_MODE_ENABLE;
4647         tw32_f(MAC_TX_MODE, tp->tx_mode);
4648
4649         for (i = 0; i < MAX_WAIT_CNT; i++) {
4650                 udelay(100);
4651                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4652                         break;
4653         }
4654         if (i >= MAX_WAIT_CNT) {
4655                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4656                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4657                        tp->dev->name, tr32(MAC_TX_MODE));
4658                 err |= -ENODEV;
4659         }
4660
4661         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4662         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4663         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4664
4665         tw32(FTQ_RESET, 0xffffffff);
4666         tw32(FTQ_RESET, 0x00000000);
4667
4668         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4669         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4670
4671         if (tp->hw_status)
4672                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4673         if (tp->hw_stats)
4674                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4675
4676         return err;
4677 }
4678
4679 /* tp->lock is held. */
4680 static int tg3_nvram_lock(struct tg3 *tp)
4681 {
4682         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4683                 int i;
4684
4685                 if (tp->nvram_lock_cnt == 0) {
4686                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4687                         for (i = 0; i < 8000; i++) {
4688                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4689                                         break;
4690                                 udelay(20);
4691                         }
4692                         if (i == 8000) {
4693                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4694                                 return -ENODEV;
4695                         }
4696                 }
4697                 tp->nvram_lock_cnt++;
4698         }
4699         return 0;
4700 }
4701
4702 /* tp->lock is held. */
4703 static void tg3_nvram_unlock(struct tg3 *tp)
4704 {
4705         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4706                 if (tp->nvram_lock_cnt > 0)
4707                         tp->nvram_lock_cnt--;
4708                 if (tp->nvram_lock_cnt == 0)
4709                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4710         }
4711 }
4712
4713 /* tp->lock is held. */
4714 static void tg3_enable_nvram_access(struct tg3 *tp)
4715 {
4716         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4717             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4718                 u32 nvaccess = tr32(NVRAM_ACCESS);
4719
4720                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4721         }
4722 }
4723
4724 /* tp->lock is held. */
4725 static void tg3_disable_nvram_access(struct tg3 *tp)
4726 {
4727         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4728             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4729                 u32 nvaccess = tr32(NVRAM_ACCESS);
4730
4731                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4732         }
4733 }
4734
4735 /* tp->lock is held. */
4736 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4737 {
4738         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4739                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4740
4741         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4742                 switch (kind) {
4743                 case RESET_KIND_INIT:
4744                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4745                                       DRV_STATE_START);
4746                         break;
4747
4748                 case RESET_KIND_SHUTDOWN:
4749                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4750                                       DRV_STATE_UNLOAD);
4751                         break;
4752
4753                 case RESET_KIND_SUSPEND:
4754                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4755                                       DRV_STATE_SUSPEND);
4756                         break;
4757
4758                 default:
4759                         break;
4760                 };
4761         }
4762 }
4763
4764 /* tp->lock is held. */
4765 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4766 {
4767         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4768                 switch (kind) {
4769                 case RESET_KIND_INIT:
4770                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4771                                       DRV_STATE_START_DONE);
4772                         break;
4773
4774                 case RESET_KIND_SHUTDOWN:
4775                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4776                                       DRV_STATE_UNLOAD_DONE);
4777                         break;
4778
4779                 default:
4780                         break;
4781                 };
4782         }
4783 }
4784
4785 /* tp->lock is held. */
4786 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4787 {
4788         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4789                 switch (kind) {
4790                 case RESET_KIND_INIT:
4791                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4792                                       DRV_STATE_START);
4793                         break;
4794
4795                 case RESET_KIND_SHUTDOWN:
4796                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4797                                       DRV_STATE_UNLOAD);
4798                         break;
4799
4800                 case RESET_KIND_SUSPEND:
4801                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4802                                       DRV_STATE_SUSPEND);
4803                         break;
4804
4805                 default:
4806                         break;
4807                 };
4808         }
4809 }
4810
4811 static int tg3_poll_fw(struct tg3 *tp)
4812 {
4813         int i;
4814         u32 val;
4815
4816         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4817                 /* Wait up to 20ms for init done. */
4818                 for (i = 0; i < 200; i++) {
4819                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4820                                 return 0;
4821                         udelay(100);
4822                 }
4823                 return -ENODEV;
4824         }
4825
4826         /* Wait for firmware initialization to complete. */
4827         for (i = 0; i < 100000; i++) {
4828                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4829                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4830                         break;
4831                 udelay(10);
4832         }
4833
4834         /* Chip might not be fitted with firmware.  Some Sun onboard
4835          * parts are configured like that.  So don't signal the timeout
4836          * of the above loop as an error, but do report the lack of
4837          * running firmware once.
4838          */
4839         if (i >= 100000 &&
4840             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4841                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4842
4843                 printk(KERN_INFO PFX "%s: No firmware running.\n",
4844                        tp->dev->name);
4845         }
4846
4847         return 0;
4848 }
4849
4850 /* Save PCI command register before chip reset */
4851 static void tg3_save_pci_state(struct tg3 *tp)
4852 {
4853         u32 val;
4854
4855         pci_read_config_dword(tp->pdev, TG3PCI_COMMAND, &val);
4856         tp->pci_cmd = val;
4857 }
4858
4859 /* Restore PCI state after chip reset */
4860 static void tg3_restore_pci_state(struct tg3 *tp)
4861 {
4862         u32 val;
4863
4864         /* Re-enable indirect register accesses. */
4865         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4866                                tp->misc_host_ctrl);
4867
4868         /* Set MAX PCI retry to zero. */
4869         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4870         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4871             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4872                 val |= PCISTATE_RETRY_SAME_DMA;
4873         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4874
4875         pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd);
4876
4877         /* Make sure PCI-X relaxed ordering bit is clear. */
4878         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4879         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4880         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4881
4882         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4883                 u32 val;
4884
4885                 /* Chip reset on 5780 will reset MSI enable bit,
4886                  * so need to restore it.
4887                  */
4888                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4889                         u16 ctrl;
4890
4891                         pci_read_config_word(tp->pdev,
4892                                              tp->msi_cap + PCI_MSI_FLAGS,
4893                                              &ctrl);
4894                         pci_write_config_word(tp->pdev,
4895                                               tp->msi_cap + PCI_MSI_FLAGS,
4896                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4897                         val = tr32(MSGINT_MODE);
4898                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4899                 }
4900         }
4901 }
4902
4903 static void tg3_stop_fw(struct tg3 *);
4904
4905 /* tp->lock is held. */
4906 static int tg3_chip_reset(struct tg3 *tp)
4907 {
4908         u32 val;
4909         void (*write_op)(struct tg3 *, u32, u32);
4910         int err;
4911
4912         tg3_nvram_lock(tp);
4913
4914         /* No matching tg3_nvram_unlock() after this because
4915          * chip reset below will undo the nvram lock.
4916          */
4917         tp->nvram_lock_cnt = 0;
4918
4919         /* GRC_MISC_CFG core clock reset will clear the memory
4920          * enable bit in PCI register 4 and the MSI enable bit
4921          * on some chips, so we save relevant registers here.
4922          */
4923         tg3_save_pci_state(tp);
4924
4925         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4926             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4927             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4928                 tw32(GRC_FASTBOOT_PC, 0);
4929
4930         /*
4931          * We must avoid the readl() that normally takes place.
4932          * It locks machines, causes machine checks, and other
4933          * fun things.  So, temporarily disable the 5701
4934          * hardware workaround, while we do the reset.
4935          */
4936         write_op = tp->write32;
4937         if (write_op == tg3_write_flush_reg32)
4938                 tp->write32 = tg3_write32;
4939
4940         /* Prevent the irq handler from reading or writing PCI registers
4941          * during chip reset when the memory enable bit in the PCI command
4942          * register may be cleared.  The chip does not generate interrupt
4943          * at this time, but the irq handler may still be called due to irq
4944          * sharing or irqpoll.
4945          */
4946         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
4947         if (tp->hw_status) {
4948                 tp->hw_status->status = 0;
4949                 tp->hw_status->status_tag = 0;
4950         }
4951         tp->last_tag = 0;
4952         smp_mb();
4953         synchronize_irq(tp->pdev->irq);
4954
4955         /* do the reset */
4956         val = GRC_MISC_CFG_CORECLK_RESET;
4957
4958         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4959                 if (tr32(0x7e2c) == 0x60) {
4960                         tw32(0x7e2c, 0x20);
4961                 }
4962                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4963                         tw32(GRC_MISC_CFG, (1 << 29));
4964                         val |= (1 << 29);
4965                 }
4966         }
4967
4968         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4969                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4970                 tw32(GRC_VCPU_EXT_CTRL,
4971                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4972         }
4973
4974         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4975                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4976         tw32(GRC_MISC_CFG, val);
4977
4978         /* restore 5701 hardware bug workaround write method */
4979         tp->write32 = write_op;
4980
4981         /* Unfortunately, we have to delay before the PCI read back.
4982          * Some 575X chips even will not respond to a PCI cfg access
4983          * when the reset command is given to the chip.
4984          *
4985          * How do these hardware designers expect things to work
4986          * properly if the PCI write is posted for a long period
4987          * of time?  It is always necessary to have some method by
4988          * which a register read back can occur to push the write
4989          * out which does the reset.
4990          *
4991          * For most tg3 variants the trick below was working.
4992          * Ho hum...
4993          */
4994         udelay(120);
4995
4996         /* Flush PCI posted writes.  The normal MMIO registers
4997          * are inaccessible at this time so this is the only
4998          * way to make this reliably (actually, this is no longer
4999          * the case, see above).  I tried to use indirect
5000          * register read/write but this upset some 5701 variants.
5001          */
5002         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
5003
5004         udelay(120);
5005
5006         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5007                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5008                         int i;
5009                         u32 cfg_val;
5010
5011                         /* Wait for link training to complete.  */
5012                         for (i = 0; i < 5000; i++)
5013                                 udelay(100);
5014
5015                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5016                         pci_write_config_dword(tp->pdev, 0xc4,
5017                                                cfg_val | (1 << 15));
5018                 }
5019                 /* Set PCIE max payload size and clear error status.  */
5020                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5021         }
5022
5023         tg3_restore_pci_state(tp);
5024
5025         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5026
5027         val = 0;
5028         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5029                 val = tr32(MEMARB_MODE);
5030         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5031
5032         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5033                 tg3_stop_fw(tp);
5034                 tw32(0x5000, 0x400);
5035         }
5036
5037         tw32(GRC_MODE, tp->grc_mode);
5038
5039         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5040                 u32 val = tr32(0xc4);
5041
5042                 tw32(0xc4, val | (1 << 15));
5043         }
5044
5045         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5046             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5047                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5048                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5049                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5050                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5051         }
5052
5053         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5054                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5055                 tw32_f(MAC_MODE, tp->mac_mode);
5056         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5057                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5058                 tw32_f(MAC_MODE, tp->mac_mode);
5059         } else
5060                 tw32_f(MAC_MODE, 0);
5061         udelay(40);
5062
5063         err = tg3_poll_fw(tp);
5064         if (err)
5065                 return err;
5066
5067         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5068             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5069                 u32 val = tr32(0x7c00);
5070
5071                 tw32(0x7c00, val | (1 << 25));
5072         }
5073
5074         /* Reprobe ASF enable state.  */
5075         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5076         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5077         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5078         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5079                 u32 nic_cfg;
5080
5081                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5082                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5083                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5084                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5085                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5086                 }
5087         }
5088
5089         return 0;
5090 }
5091
5092 /* tp->lock is held. */
5093 static void tg3_stop_fw(struct tg3 *tp)
5094 {
5095         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5096                 u32 val;
5097                 int i;
5098
5099                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5100                 val = tr32(GRC_RX_CPU_EVENT);
5101                 val |= (1 << 14);
5102                 tw32(GRC_RX_CPU_EVENT, val);
5103
5104                 /* Wait for RX cpu to ACK the event.  */
5105                 for (i = 0; i < 100; i++) {
5106                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5107                                 break;
5108                         udelay(1);
5109                 }
5110         }
5111 }
5112
5113 /* tp->lock is held. */
5114 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5115 {
5116         int err;
5117
5118         tg3_stop_fw(tp);
5119
5120         tg3_write_sig_pre_reset(tp, kind);
5121
5122         tg3_abort_hw(tp, silent);
5123         err = tg3_chip_reset(tp);
5124
5125         tg3_write_sig_legacy(tp, kind);
5126         tg3_write_sig_post_reset(tp, kind);
5127
5128         if (err)
5129                 return err;
5130
5131         return 0;
5132 }
5133
5134 #define TG3_FW_RELEASE_MAJOR    0x0
5135 #define TG3_FW_RELASE_MINOR     0x0
5136 #define TG3_FW_RELEASE_FIX      0x0
5137 #define TG3_FW_START_ADDR       0x08000000
5138 #define TG3_FW_TEXT_ADDR        0x08000000
5139 #define TG3_FW_TEXT_LEN         0x9c0
5140 #define TG3_FW_RODATA_ADDR      0x080009c0
5141 #define TG3_FW_RODATA_LEN       0x60
5142 #define TG3_FW_DATA_ADDR        0x08000a40
5143 #define TG3_FW_DATA_LEN         0x20
5144 #define TG3_FW_SBSS_ADDR        0x08000a60
5145 #define TG3_FW_SBSS_LEN         0xc
5146 #define TG3_FW_BSS_ADDR         0x08000a70
5147 #define TG3_FW_BSS_LEN          0x10
5148
5149 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5150         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5151         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5152         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5153         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5154         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5155         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5156         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5157         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5158         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5159         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5160         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5161         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5162         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5163         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5164         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5165         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5166         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5167         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5168         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5169         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5170         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5171         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5172         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5173         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5174         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5175         0, 0, 0, 0, 0, 0,
5176         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5177         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5178         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5179         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5180         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5181         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5182         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5183         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5184         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5185         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5186         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5187         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5188         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5189         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5190         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5191         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5192         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5193         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5194         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5195         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5196         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5197         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5198         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5199         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5200         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5201         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5202         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5203         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5204         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5205         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5206         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5207         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5208         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5209         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5210         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5211         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5212         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5213         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5214         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5215         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5216         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5217         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5218         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5219         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5220         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5221         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5222         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5223         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5224         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5225         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5226         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5227         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5228         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5229         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5230         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5231         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5232         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5233         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5234         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5235         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5236         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5237         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5238         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5239         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5240         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5241 };
5242
5243 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5244         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5245         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5246         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5247         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5248         0x00000000
5249 };
5250
5251 #if 0 /* All zeros, don't eat up space with it. */
5252 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5253         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5254         0x00000000, 0x00000000, 0x00000000, 0x00000000
5255 };
5256 #endif
5257
5258 #define RX_CPU_SCRATCH_BASE     0x30000
5259 #define RX_CPU_SCRATCH_SIZE     0x04000
5260 #define TX_CPU_SCRATCH_BASE     0x34000
5261 #define TX_CPU_SCRATCH_SIZE     0x04000
5262
5263 /* tp->lock is held. */
5264 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5265 {
5266         int i;
5267
5268         BUG_ON(offset == TX_CPU_BASE &&
5269             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5270
5271         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5272                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5273
5274                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5275                 return 0;
5276         }
5277         if (offset == RX_CPU_BASE) {
5278                 for (i = 0; i < 10000; i++) {
5279                         tw32(offset + CPU_STATE, 0xffffffff);
5280                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5281                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5282                                 break;
5283                 }
5284
5285                 tw32(offset + CPU_STATE, 0xffffffff);
5286                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5287                 udelay(10);
5288         } else {
5289                 for (i = 0; i < 10000; i++) {
5290                         tw32(offset + CPU_STATE, 0xffffffff);
5291                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5292                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5293                                 break;
5294                 }
5295         }
5296
5297         if (i >= 10000) {
5298                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5299                        "and %s CPU\n",
5300                        tp->dev->name,
5301                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5302                 return -ENODEV;
5303         }
5304
5305         /* Clear firmware's nvram arbitration. */
5306         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5307                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5308         return 0;
5309 }
5310
5311 struct fw_info {
5312         unsigned int text_base;
5313         unsigned int text_len;
5314         const u32 *text_data;
5315         unsigned int rodata_base;
5316         unsigned int rodata_len;
5317         const u32 *rodata_data;
5318         unsigned int data_base;
5319         unsigned int data_len;
5320         const u32 *data_data;
5321 };
5322
5323 /* tp->lock is held. */
5324 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5325                                  int cpu_scratch_size, struct fw_info *info)
5326 {
5327         int err, lock_err, i;
5328         void (*write_op)(struct tg3 *, u32, u32);
5329
5330         if (cpu_base == TX_CPU_BASE &&
5331             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5332                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5333                        "TX cpu firmware on %s which is 5705.\n",
5334                        tp->dev->name);
5335                 return -EINVAL;
5336         }
5337
5338         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5339                 write_op = tg3_write_mem;
5340         else
5341                 write_op = tg3_write_indirect_reg32;
5342
5343         /* It is possible that bootcode is still loading at this point.
5344          * Get the nvram lock first before halting the cpu.
5345          */
5346         lock_err = tg3_nvram_lock(tp);
5347         err = tg3_halt_cpu(tp, cpu_base);
5348         if (!lock_err)
5349                 tg3_nvram_unlock(tp);
5350         if (err)
5351                 goto out;
5352
5353         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5354                 write_op(tp, cpu_scratch_base + i, 0);
5355         tw32(cpu_base + CPU_STATE, 0xffffffff);
5356         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5357         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5358                 write_op(tp, (cpu_scratch_base +
5359                               (info->text_base & 0xffff) +
5360                               (i * sizeof(u32))),
5361                          (info->text_data ?
5362                           info->text_data[i] : 0));
5363         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5364                 write_op(tp, (cpu_scratch_base +
5365                               (info->rodata_base & 0xffff) +
5366                               (i * sizeof(u32))),
5367                          (info->rodata_data ?
5368                           info->rodata_data[i] : 0));
5369         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5370                 write_op(tp, (cpu_scratch_base +
5371                               (info->data_base & 0xffff) +
5372                               (i * sizeof(u32))),
5373                          (info->data_data ?
5374                           info->data_data[i] : 0));
5375
5376         err = 0;
5377
5378 out:
5379         return err;
5380 }
5381
5382 /* tp->lock is held. */
5383 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5384 {
5385         struct fw_info info;
5386         int err, i;
5387
5388         info.text_base = TG3_FW_TEXT_ADDR;
5389         info.text_len = TG3_FW_TEXT_LEN;
5390         info.text_data = &tg3FwText[0];
5391         info.rodata_base = TG3_FW_RODATA_ADDR;
5392         info.rodata_len = TG3_FW_RODATA_LEN;
5393         info.rodata_data = &tg3FwRodata[0];
5394         info.data_base = TG3_FW_DATA_ADDR;
5395         info.data_len = TG3_FW_DATA_LEN;
5396         info.data_data = NULL;
5397
5398         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5399                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5400                                     &info);
5401         if (err)
5402                 return err;
5403
5404         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5405                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5406                                     &info);
5407         if (err)
5408                 return err;
5409
5410         /* Now startup only the RX cpu. */
5411         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5412         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5413
5414         for (i = 0; i < 5; i++) {
5415                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5416                         break;
5417                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5418                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5419                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5420                 udelay(1000);
5421         }
5422         if (i >= 5) {
5423                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5424                        "to set RX CPU PC, is %08x should be %08x\n",
5425                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5426                        TG3_FW_TEXT_ADDR);
5427                 return -ENODEV;
5428         }
5429         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5430         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5431
5432         return 0;
5433 }
5434
5435
5436 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5437 #define TG3_TSO_FW_RELASE_MINOR         0x6
5438 #define TG3_TSO_FW_RELEASE_FIX          0x0
5439 #define TG3_TSO_FW_START_ADDR           0x08000000
5440 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5441 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5442 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5443 #define TG3_TSO_FW_RODATA_LEN           0x60
5444 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5445 #define TG3_TSO_FW_DATA_LEN             0x30
5446 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5447 #define TG3_TSO_FW_SBSS_LEN             0x2c
5448 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5449 #define TG3_TSO_FW_BSS_LEN              0x894
5450
5451 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5452         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5453         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5454         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5455         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5456         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5457         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5458         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5459         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5460         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5461         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5462         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5463         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5464         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5465         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5466         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5467         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5468         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5469         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5470         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5471         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5472         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5473         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5474         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5475         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5476         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5477         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5478         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5479         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5480         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5481         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5482         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5483         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5484         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5485         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5486         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5487         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5488         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5489         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5490         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5491         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5492         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5493         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5494         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5495         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5496         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5497         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5498         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5499         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5500         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5501         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5502         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5503         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5504         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5505         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5506         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5507         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5508         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5509         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5510         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5511         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5512         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5513         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5514         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5515         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5516         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5517         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5518         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5519         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5520         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5521         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5522         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5523         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5524         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5525         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5526         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5527         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5528         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5529         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5530         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5531         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5532         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5533         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5534         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5535         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5536         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5537         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5538         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5539         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5540         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5541         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5542         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5543         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5544         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5545         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5546         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5547         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5548         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5549         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5550         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5551         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5552         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5553         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5554         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5555         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5556         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5557         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5558         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5559         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5560         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5561         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5562         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5563         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5564         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5565         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5566         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5567         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5568         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5569         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5570         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5571         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5572         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5573         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5574         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5575         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5576         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5577         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5578         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5579         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5580         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5581         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5582         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5583         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5584         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5585         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5586         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5587         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5588         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5589         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5590         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5591         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5592         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5593         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5594         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5595         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5596         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5597         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5598         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5599         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5600         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5601         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5602         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5603         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5604         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5605         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5606         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5607         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5608         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5609         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5610         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5611         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5612         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5613         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5614         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5615         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5616         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5617         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5618         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5619         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5620         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5621         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5622         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5623         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5624         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5625         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5626         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5627         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5628         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5629         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5630         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5631         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5632         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5633         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5634         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5635         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5636         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5637         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5638         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5639         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5640         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5641         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5642         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5643         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5644         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5645         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5646         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5647         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5648         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5649         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5650         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5651         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5652         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5653         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5654         0x3c010800, 0xac23