[TG3]: Fix link problem on Dell's onboard 5906.
[linux-3.10.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2007 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40 #include <linux/dma-mapping.h>
41
42 #include <net/checksum.h>
43 #include <net/ip.h>
44
45 #include <asm/system.h>
46 #include <asm/io.h>
47 #include <asm/byteorder.h>
48 #include <asm/uaccess.h>
49
50 #ifdef CONFIG_SPARC
51 #include <asm/idprom.h>
52 #include <asm/prom.h>
53 #endif
54
55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56 #define TG3_VLAN_TAG_USED 1
57 #else
58 #define TG3_VLAN_TAG_USED 0
59 #endif
60
61 #define TG3_TSO_SUPPORT 1
62
63 #include "tg3.h"
64
65 #define DRV_MODULE_NAME         "tg3"
66 #define PFX DRV_MODULE_NAME     ": "
67 #define DRV_MODULE_VERSION      "3.77"
68 #define DRV_MODULE_RELDATE      "May 31, 2007"
69
70 #define TG3_DEF_MAC_MODE        0
71 #define TG3_DEF_RX_MODE         0
72 #define TG3_DEF_TX_MODE         0
73 #define TG3_DEF_MSG_ENABLE        \
74         (NETIF_MSG_DRV          | \
75          NETIF_MSG_PROBE        | \
76          NETIF_MSG_LINK         | \
77          NETIF_MSG_TIMER        | \
78          NETIF_MSG_IFDOWN       | \
79          NETIF_MSG_IFUP         | \
80          NETIF_MSG_RX_ERR       | \
81          NETIF_MSG_TX_ERR)
82
83 /* length of time before we decide the hardware is borked,
84  * and dev->tx_timeout() should be called to fix the problem
85  */
86 #define TG3_TX_TIMEOUT                  (5 * HZ)
87
88 /* hardware minimum and maximum for a single frame's data payload */
89 #define TG3_MIN_MTU                     60
90 #define TG3_MAX_MTU(tp) \
91         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
92
93 /* These numbers seem to be hard coded in the NIC firmware somehow.
94  * You can't change the ring sizes, but you can change where you place
95  * them in the NIC onboard memory.
96  */
97 #define TG3_RX_RING_SIZE                512
98 #define TG3_DEF_RX_RING_PENDING         200
99 #define TG3_RX_JUMBO_RING_SIZE          256
100 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
101
102 /* Do not place this n-ring entries value into the tp struct itself,
103  * we really want to expose these constants to GCC so that modulo et
104  * al.  operations are done with shifts and masks instead of with
105  * hw multiply/modulo instructions.  Another solution would be to
106  * replace things like '% foo' with '& (foo - 1)'.
107  */
108 #define TG3_RX_RCB_RING_SIZE(tp)        \
109         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
110
111 #define TG3_TX_RING_SIZE                512
112 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
113
114 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
115                                  TG3_RX_RING_SIZE)
116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117                                  TG3_RX_JUMBO_RING_SIZE)
118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119                                    TG3_RX_RCB_RING_SIZE(tp))
120 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
121                                  TG3_TX_RING_SIZE)
122 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
123
124 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
125 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
126
127 /* minimum number of free TX descriptors required to wake up TX process */
128 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
129
130 /* number of ETHTOOL_GSTATS u64's */
131 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
132
133 #define TG3_NUM_TEST            6
134
135 static char version[] __devinitdata =
136         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
137
138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_MODULE_VERSION);
142
143 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
144 module_param(tg3_debug, int, 0);
145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
146
147 static struct pci_device_id tg3_pci_tbl[] = {
148         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
201         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
202         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
203         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
204         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
205         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
206         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
207         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
208         {}
209 };
210
211 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
212
213 static const struct {
214         const char string[ETH_GSTRING_LEN];
215 } ethtool_stats_keys[TG3_NUM_STATS] = {
216         { "rx_octets" },
217         { "rx_fragments" },
218         { "rx_ucast_packets" },
219         { "rx_mcast_packets" },
220         { "rx_bcast_packets" },
221         { "rx_fcs_errors" },
222         { "rx_align_errors" },
223         { "rx_xon_pause_rcvd" },
224         { "rx_xoff_pause_rcvd" },
225         { "rx_mac_ctrl_rcvd" },
226         { "rx_xoff_entered" },
227         { "rx_frame_too_long_errors" },
228         { "rx_jabbers" },
229         { "rx_undersize_packets" },
230         { "rx_in_length_errors" },
231         { "rx_out_length_errors" },
232         { "rx_64_or_less_octet_packets" },
233         { "rx_65_to_127_octet_packets" },
234         { "rx_128_to_255_octet_packets" },
235         { "rx_256_to_511_octet_packets" },
236         { "rx_512_to_1023_octet_packets" },
237         { "rx_1024_to_1522_octet_packets" },
238         { "rx_1523_to_2047_octet_packets" },
239         { "rx_2048_to_4095_octet_packets" },
240         { "rx_4096_to_8191_octet_packets" },
241         { "rx_8192_to_9022_octet_packets" },
242
243         { "tx_octets" },
244         { "tx_collisions" },
245
246         { "tx_xon_sent" },
247         { "tx_xoff_sent" },
248         { "tx_flow_control" },
249         { "tx_mac_errors" },
250         { "tx_single_collisions" },
251         { "tx_mult_collisions" },
252         { "tx_deferred" },
253         { "tx_excessive_collisions" },
254         { "tx_late_collisions" },
255         { "tx_collide_2times" },
256         { "tx_collide_3times" },
257         { "tx_collide_4times" },
258         { "tx_collide_5times" },
259         { "tx_collide_6times" },
260         { "tx_collide_7times" },
261         { "tx_collide_8times" },
262         { "tx_collide_9times" },
263         { "tx_collide_10times" },
264         { "tx_collide_11times" },
265         { "tx_collide_12times" },
266         { "tx_collide_13times" },
267         { "tx_collide_14times" },
268         { "tx_collide_15times" },
269         { "tx_ucast_packets" },
270         { "tx_mcast_packets" },
271         { "tx_bcast_packets" },
272         { "tx_carrier_sense_errors" },
273         { "tx_discards" },
274         { "tx_errors" },
275
276         { "dma_writeq_full" },
277         { "dma_write_prioq_full" },
278         { "rxbds_empty" },
279         { "rx_discards" },
280         { "rx_errors" },
281         { "rx_threshold_hit" },
282
283         { "dma_readq_full" },
284         { "dma_read_prioq_full" },
285         { "tx_comp_queue_full" },
286
287         { "ring_set_send_prod_index" },
288         { "ring_status_update" },
289         { "nic_irqs" },
290         { "nic_avoided_irqs" },
291         { "nic_tx_threshold_hit" }
292 };
293
294 static const struct {
295         const char string[ETH_GSTRING_LEN];
296 } ethtool_test_keys[TG3_NUM_TEST] = {
297         { "nvram test     (online) " },
298         { "link test      (online) " },
299         { "register test  (offline)" },
300         { "memory test    (offline)" },
301         { "loopback test  (offline)" },
302         { "interrupt test (offline)" },
303 };
304
305 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
306 {
307         writel(val, tp->regs + off);
308 }
309
310 static u32 tg3_read32(struct tg3 *tp, u32 off)
311 {
312         return (readl(tp->regs + off));
313 }
314
315 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
316 {
317         unsigned long flags;
318
319         spin_lock_irqsave(&tp->indirect_lock, flags);
320         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
321         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
322         spin_unlock_irqrestore(&tp->indirect_lock, flags);
323 }
324
325 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
326 {
327         writel(val, tp->regs + off);
328         readl(tp->regs + off);
329 }
330
331 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
332 {
333         unsigned long flags;
334         u32 val;
335
336         spin_lock_irqsave(&tp->indirect_lock, flags);
337         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
338         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
339         spin_unlock_irqrestore(&tp->indirect_lock, flags);
340         return val;
341 }
342
343 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
344 {
345         unsigned long flags;
346
347         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
348                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
349                                        TG3_64BIT_REG_LOW, val);
350                 return;
351         }
352         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
353                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
354                                        TG3_64BIT_REG_LOW, val);
355                 return;
356         }
357
358         spin_lock_irqsave(&tp->indirect_lock, flags);
359         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
360         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
361         spin_unlock_irqrestore(&tp->indirect_lock, flags);
362
363         /* In indirect mode when disabling interrupts, we also need
364          * to clear the interrupt bit in the GRC local ctrl register.
365          */
366         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
367             (val == 0x1)) {
368                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
369                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
370         }
371 }
372
373 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
374 {
375         unsigned long flags;
376         u32 val;
377
378         spin_lock_irqsave(&tp->indirect_lock, flags);
379         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
380         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
381         spin_unlock_irqrestore(&tp->indirect_lock, flags);
382         return val;
383 }
384
385 /* usec_wait specifies the wait time in usec when writing to certain registers
386  * where it is unsafe to read back the register without some delay.
387  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
388  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
389  */
390 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
391 {
392         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
393             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
394                 /* Non-posted methods */
395                 tp->write32(tp, off, val);
396         else {
397                 /* Posted method */
398                 tg3_write32(tp, off, val);
399                 if (usec_wait)
400                         udelay(usec_wait);
401                 tp->read32(tp, off);
402         }
403         /* Wait again after the read for the posted method to guarantee that
404          * the wait time is met.
405          */
406         if (usec_wait)
407                 udelay(usec_wait);
408 }
409
410 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
411 {
412         tp->write32_mbox(tp, off, val);
413         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
414             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
415                 tp->read32_mbox(tp, off);
416 }
417
418 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
419 {
420         void __iomem *mbox = tp->regs + off;
421         writel(val, mbox);
422         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
423                 writel(val, mbox);
424         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
425                 readl(mbox);
426 }
427
428 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
429 {
430         return (readl(tp->regs + off + GRCMBOX_BASE));
431 }
432
433 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
434 {
435         writel(val, tp->regs + off + GRCMBOX_BASE);
436 }
437
438 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
439 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
440 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
441 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
442 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
443
444 #define tw32(reg,val)           tp->write32(tp, reg, val)
445 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
446 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
447 #define tr32(reg)               tp->read32(tp, reg)
448
449 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
450 {
451         unsigned long flags;
452
453         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
454             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
455                 return;
456
457         spin_lock_irqsave(&tp->indirect_lock, flags);
458         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
459                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
460                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
461
462                 /* Always leave this as zero. */
463                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
464         } else {
465                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
466                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
467
468                 /* Always leave this as zero. */
469                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
470         }
471         spin_unlock_irqrestore(&tp->indirect_lock, flags);
472 }
473
474 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
475 {
476         unsigned long flags;
477
478         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
479             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
480                 *val = 0;
481                 return;
482         }
483
484         spin_lock_irqsave(&tp->indirect_lock, flags);
485         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
486                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
487                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
488
489                 /* Always leave this as zero. */
490                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
491         } else {
492                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
493                 *val = tr32(TG3PCI_MEM_WIN_DATA);
494
495                 /* Always leave this as zero. */
496                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
497         }
498         spin_unlock_irqrestore(&tp->indirect_lock, flags);
499 }
500
501 static void tg3_disable_ints(struct tg3 *tp)
502 {
503         tw32(TG3PCI_MISC_HOST_CTRL,
504              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
505         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
506 }
507
508 static inline void tg3_cond_int(struct tg3 *tp)
509 {
510         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
511             (tp->hw_status->status & SD_STATUS_UPDATED))
512                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
513         else
514                 tw32(HOSTCC_MODE, tp->coalesce_mode |
515                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
516 }
517
518 static void tg3_enable_ints(struct tg3 *tp)
519 {
520         tp->irq_sync = 0;
521         wmb();
522
523         tw32(TG3PCI_MISC_HOST_CTRL,
524              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
525         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
526                        (tp->last_tag << 24));
527         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
528                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
529                                (tp->last_tag << 24));
530         tg3_cond_int(tp);
531 }
532
533 static inline unsigned int tg3_has_work(struct tg3 *tp)
534 {
535         struct tg3_hw_status *sblk = tp->hw_status;
536         unsigned int work_exists = 0;
537
538         /* check for phy events */
539         if (!(tp->tg3_flags &
540               (TG3_FLAG_USE_LINKCHG_REG |
541                TG3_FLAG_POLL_SERDES))) {
542                 if (sblk->status & SD_STATUS_LINK_CHG)
543                         work_exists = 1;
544         }
545         /* check for RX/TX work to do */
546         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
547             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
548                 work_exists = 1;
549
550         return work_exists;
551 }
552
553 /* tg3_restart_ints
554  *  similar to tg3_enable_ints, but it accurately determines whether there
555  *  is new work pending and can return without flushing the PIO write
556  *  which reenables interrupts
557  */
558 static void tg3_restart_ints(struct tg3 *tp)
559 {
560         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
561                      tp->last_tag << 24);
562         mmiowb();
563
564         /* When doing tagged status, this work check is unnecessary.
565          * The last_tag we write above tells the chip which piece of
566          * work we've completed.
567          */
568         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
569             tg3_has_work(tp))
570                 tw32(HOSTCC_MODE, tp->coalesce_mode |
571                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
572 }
573
574 static inline void tg3_netif_stop(struct tg3 *tp)
575 {
576         tp->dev->trans_start = jiffies; /* prevent tx timeout */
577         netif_poll_disable(tp->dev);
578         netif_tx_disable(tp->dev);
579 }
580
581 static inline void tg3_netif_start(struct tg3 *tp)
582 {
583         netif_wake_queue(tp->dev);
584         /* NOTE: unconditional netif_wake_queue is only appropriate
585          * so long as all callers are assured to have free tx slots
586          * (such as after tg3_init_hw)
587          */
588         netif_poll_enable(tp->dev);
589         tp->hw_status->status |= SD_STATUS_UPDATED;
590         tg3_enable_ints(tp);
591 }
592
593 static void tg3_switch_clocks(struct tg3 *tp)
594 {
595         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
596         u32 orig_clock_ctrl;
597
598         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
599                 return;
600
601         orig_clock_ctrl = clock_ctrl;
602         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
603                        CLOCK_CTRL_CLKRUN_OENABLE |
604                        0x1f);
605         tp->pci_clock_ctrl = clock_ctrl;
606
607         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
608                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
609                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
610                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
611                 }
612         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
613                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
614                             clock_ctrl |
615                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
616                             40);
617                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
618                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
619                             40);
620         }
621         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
622 }
623
624 #define PHY_BUSY_LOOPS  5000
625
626 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
627 {
628         u32 frame_val;
629         unsigned int loops;
630         int ret;
631
632         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
633                 tw32_f(MAC_MI_MODE,
634                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
635                 udelay(80);
636         }
637
638         *val = 0x0;
639
640         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
641                       MI_COM_PHY_ADDR_MASK);
642         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
643                       MI_COM_REG_ADDR_MASK);
644         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
645
646         tw32_f(MAC_MI_COM, frame_val);
647
648         loops = PHY_BUSY_LOOPS;
649         while (loops != 0) {
650                 udelay(10);
651                 frame_val = tr32(MAC_MI_COM);
652
653                 if ((frame_val & MI_COM_BUSY) == 0) {
654                         udelay(5);
655                         frame_val = tr32(MAC_MI_COM);
656                         break;
657                 }
658                 loops -= 1;
659         }
660
661         ret = -EBUSY;
662         if (loops != 0) {
663                 *val = frame_val & MI_COM_DATA_MASK;
664                 ret = 0;
665         }
666
667         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
668                 tw32_f(MAC_MI_MODE, tp->mi_mode);
669                 udelay(80);
670         }
671
672         return ret;
673 }
674
675 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
676 {
677         u32 frame_val;
678         unsigned int loops;
679         int ret;
680
681         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
682             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
683                 return 0;
684
685         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
686                 tw32_f(MAC_MI_MODE,
687                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
688                 udelay(80);
689         }
690
691         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
692                       MI_COM_PHY_ADDR_MASK);
693         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
694                       MI_COM_REG_ADDR_MASK);
695         frame_val |= (val & MI_COM_DATA_MASK);
696         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
697
698         tw32_f(MAC_MI_COM, frame_val);
699
700         loops = PHY_BUSY_LOOPS;
701         while (loops != 0) {
702                 udelay(10);
703                 frame_val = tr32(MAC_MI_COM);
704                 if ((frame_val & MI_COM_BUSY) == 0) {
705                         udelay(5);
706                         frame_val = tr32(MAC_MI_COM);
707                         break;
708                 }
709                 loops -= 1;
710         }
711
712         ret = -EBUSY;
713         if (loops != 0)
714                 ret = 0;
715
716         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
717                 tw32_f(MAC_MI_MODE, tp->mi_mode);
718                 udelay(80);
719         }
720
721         return ret;
722 }
723
724 static void tg3_phy_set_wirespeed(struct tg3 *tp)
725 {
726         u32 val;
727
728         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
729                 return;
730
731         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
732             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
733                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
734                              (val | (1 << 15) | (1 << 4)));
735 }
736
737 static int tg3_bmcr_reset(struct tg3 *tp)
738 {
739         u32 phy_control;
740         int limit, err;
741
742         /* OK, reset it, and poll the BMCR_RESET bit until it
743          * clears or we time out.
744          */
745         phy_control = BMCR_RESET;
746         err = tg3_writephy(tp, MII_BMCR, phy_control);
747         if (err != 0)
748                 return -EBUSY;
749
750         limit = 5000;
751         while (limit--) {
752                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
753                 if (err != 0)
754                         return -EBUSY;
755
756                 if ((phy_control & BMCR_RESET) == 0) {
757                         udelay(40);
758                         break;
759                 }
760                 udelay(10);
761         }
762         if (limit <= 0)
763                 return -EBUSY;
764
765         return 0;
766 }
767
768 static int tg3_wait_macro_done(struct tg3 *tp)
769 {
770         int limit = 100;
771
772         while (limit--) {
773                 u32 tmp32;
774
775                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
776                         if ((tmp32 & 0x1000) == 0)
777                                 break;
778                 }
779         }
780         if (limit <= 0)
781                 return -EBUSY;
782
783         return 0;
784 }
785
786 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
787 {
788         static const u32 test_pat[4][6] = {
789         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
790         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
791         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
792         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
793         };
794         int chan;
795
796         for (chan = 0; chan < 4; chan++) {
797                 int i;
798
799                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
800                              (chan * 0x2000) | 0x0200);
801                 tg3_writephy(tp, 0x16, 0x0002);
802
803                 for (i = 0; i < 6; i++)
804                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
805                                      test_pat[chan][i]);
806
807                 tg3_writephy(tp, 0x16, 0x0202);
808                 if (tg3_wait_macro_done(tp)) {
809                         *resetp = 1;
810                         return -EBUSY;
811                 }
812
813                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
814                              (chan * 0x2000) | 0x0200);
815                 tg3_writephy(tp, 0x16, 0x0082);
816                 if (tg3_wait_macro_done(tp)) {
817                         *resetp = 1;
818                         return -EBUSY;
819                 }
820
821                 tg3_writephy(tp, 0x16, 0x0802);
822                 if (tg3_wait_macro_done(tp)) {
823                         *resetp = 1;
824                         return -EBUSY;
825                 }
826
827                 for (i = 0; i < 6; i += 2) {
828                         u32 low, high;
829
830                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
831                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
832                             tg3_wait_macro_done(tp)) {
833                                 *resetp = 1;
834                                 return -EBUSY;
835                         }
836                         low &= 0x7fff;
837                         high &= 0x000f;
838                         if (low != test_pat[chan][i] ||
839                             high != test_pat[chan][i+1]) {
840                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
841                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
842                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
843
844                                 return -EBUSY;
845                         }
846                 }
847         }
848
849         return 0;
850 }
851
852 static int tg3_phy_reset_chanpat(struct tg3 *tp)
853 {
854         int chan;
855
856         for (chan = 0; chan < 4; chan++) {
857                 int i;
858
859                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
860                              (chan * 0x2000) | 0x0200);
861                 tg3_writephy(tp, 0x16, 0x0002);
862                 for (i = 0; i < 6; i++)
863                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
864                 tg3_writephy(tp, 0x16, 0x0202);
865                 if (tg3_wait_macro_done(tp))
866                         return -EBUSY;
867         }
868
869         return 0;
870 }
871
872 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
873 {
874         u32 reg32, phy9_orig;
875         int retries, do_phy_reset, err;
876
877         retries = 10;
878         do_phy_reset = 1;
879         do {
880                 if (do_phy_reset) {
881                         err = tg3_bmcr_reset(tp);
882                         if (err)
883                                 return err;
884                         do_phy_reset = 0;
885                 }
886
887                 /* Disable transmitter and interrupt.  */
888                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
889                         continue;
890
891                 reg32 |= 0x3000;
892                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
893
894                 /* Set full-duplex, 1000 mbps.  */
895                 tg3_writephy(tp, MII_BMCR,
896                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
897
898                 /* Set to master mode.  */
899                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
900                         continue;
901
902                 tg3_writephy(tp, MII_TG3_CTRL,
903                              (MII_TG3_CTRL_AS_MASTER |
904                               MII_TG3_CTRL_ENABLE_AS_MASTER));
905
906                 /* Enable SM_DSP_CLOCK and 6dB.  */
907                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
908
909                 /* Block the PHY control access.  */
910                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
911                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
912
913                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
914                 if (!err)
915                         break;
916         } while (--retries);
917
918         err = tg3_phy_reset_chanpat(tp);
919         if (err)
920                 return err;
921
922         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
923         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
924
925         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
926         tg3_writephy(tp, 0x16, 0x0000);
927
928         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
929             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
930                 /* Set Extended packet length bit for jumbo frames */
931                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
932         }
933         else {
934                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
935         }
936
937         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
938
939         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
940                 reg32 &= ~0x3000;
941                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
942         } else if (!err)
943                 err = -EBUSY;
944
945         return err;
946 }
947
948 static void tg3_link_report(struct tg3 *);
949
950 /* This will reset the tigon3 PHY if there is no valid
951  * link unless the FORCE argument is non-zero.
952  */
953 static int tg3_phy_reset(struct tg3 *tp)
954 {
955         u32 phy_status;
956         int err;
957
958         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
959                 u32 val;
960
961                 val = tr32(GRC_MISC_CFG);
962                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
963                 udelay(40);
964         }
965         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
966         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
967         if (err != 0)
968                 return -EBUSY;
969
970         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
971                 netif_carrier_off(tp->dev);
972                 tg3_link_report(tp);
973         }
974
975         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
976             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
977             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
978                 err = tg3_phy_reset_5703_4_5(tp);
979                 if (err)
980                         return err;
981                 goto out;
982         }
983
984         err = tg3_bmcr_reset(tp);
985         if (err)
986                 return err;
987
988 out:
989         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
990                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
991                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
992                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
993                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
994                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
995                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
996         }
997         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
998                 tg3_writephy(tp, 0x1c, 0x8d68);
999                 tg3_writephy(tp, 0x1c, 0x8d68);
1000         }
1001         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1002                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1003                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1004                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1005                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1006                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1007                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1008                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1009                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1010         }
1011         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1012                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1013                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1014                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1015                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1016                         tg3_writephy(tp, MII_TG3_TEST1,
1017                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1018                 } else
1019                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1020                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1021         }
1022         /* Set Extended packet length bit (bit 14) on all chips that */
1023         /* support jumbo frames */
1024         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1025                 /* Cannot do read-modify-write on 5401 */
1026                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1027         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1028                 u32 phy_reg;
1029
1030                 /* Set bit 14 with read-modify-write to preserve other bits */
1031                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1032                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1033                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1034         }
1035
1036         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1037          * jumbo frames transmission.
1038          */
1039         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1040                 u32 phy_reg;
1041
1042                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1043                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1044                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1045         }
1046
1047         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1048                 u32 phy_reg;
1049
1050                 /* adjust output voltage */
1051                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1052
1053                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1054                         u32 phy_reg2;
1055
1056                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1057                                      phy_reg | MII_TG3_EPHY_SHADOW_EN);
1058                         /* Enable auto-MDIX */
1059                         if (!tg3_readphy(tp, 0x10, &phy_reg2))
1060                                 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1061                         tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1062                 }
1063         }
1064
1065         tg3_phy_set_wirespeed(tp);
1066         return 0;
1067 }
1068
1069 static void tg3_frob_aux_power(struct tg3 *tp)
1070 {
1071         struct tg3 *tp_peer = tp;
1072
1073         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1074                 return;
1075
1076         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1077             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1078                 struct net_device *dev_peer;
1079
1080                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1081                 /* remove_one() may have been run on the peer. */
1082                 if (!dev_peer)
1083                         tp_peer = tp;
1084                 else
1085                         tp_peer = netdev_priv(dev_peer);
1086         }
1087
1088         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1089             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1090             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1091             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1092                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1093                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1094                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1095                                     (GRC_LCLCTRL_GPIO_OE0 |
1096                                      GRC_LCLCTRL_GPIO_OE1 |
1097                                      GRC_LCLCTRL_GPIO_OE2 |
1098                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1099                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1100                                     100);
1101                 } else {
1102                         u32 no_gpio2;
1103                         u32 grc_local_ctrl = 0;
1104
1105                         if (tp_peer != tp &&
1106                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1107                                 return;
1108
1109                         /* Workaround to prevent overdrawing Amps. */
1110                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1111                             ASIC_REV_5714) {
1112                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1113                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1114                                             grc_local_ctrl, 100);
1115                         }
1116
1117                         /* On 5753 and variants, GPIO2 cannot be used. */
1118                         no_gpio2 = tp->nic_sram_data_cfg &
1119                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1120
1121                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1122                                          GRC_LCLCTRL_GPIO_OE1 |
1123                                          GRC_LCLCTRL_GPIO_OE2 |
1124                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1125                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1126                         if (no_gpio2) {
1127                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1128                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1129                         }
1130                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1131                                                     grc_local_ctrl, 100);
1132
1133                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1134
1135                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1136                                                     grc_local_ctrl, 100);
1137
1138                         if (!no_gpio2) {
1139                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1140                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1141                                             grc_local_ctrl, 100);
1142                         }
1143                 }
1144         } else {
1145                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1146                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1147                         if (tp_peer != tp &&
1148                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1149                                 return;
1150
1151                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1152                                     (GRC_LCLCTRL_GPIO_OE1 |
1153                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1154
1155                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1156                                     GRC_LCLCTRL_GPIO_OE1, 100);
1157
1158                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1159                                     (GRC_LCLCTRL_GPIO_OE1 |
1160                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1161                 }
1162         }
1163 }
1164
1165 static int tg3_setup_phy(struct tg3 *, int);
1166
1167 #define RESET_KIND_SHUTDOWN     0
1168 #define RESET_KIND_INIT         1
1169 #define RESET_KIND_SUSPEND      2
1170
1171 static void tg3_write_sig_post_reset(struct tg3 *, int);
1172 static int tg3_halt_cpu(struct tg3 *, u32);
1173 static int tg3_nvram_lock(struct tg3 *);
1174 static void tg3_nvram_unlock(struct tg3 *);
1175
1176 static void tg3_power_down_phy(struct tg3 *tp)
1177 {
1178         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1179                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1180                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1181                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1182
1183                         sg_dig_ctrl |=
1184                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1185                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1186                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1187                 }
1188                 return;
1189         }
1190
1191         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1192                 u32 val;
1193
1194                 tg3_bmcr_reset(tp);
1195                 val = tr32(GRC_MISC_CFG);
1196                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1197                 udelay(40);
1198                 return;
1199         } else {
1200                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1201                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1202                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1203         }
1204
1205         /* The PHY should not be powered down on some chips because
1206          * of bugs.
1207          */
1208         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1209             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1210             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1211              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1212                 return;
1213         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1214 }
1215
1216 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1217 {
1218         u32 misc_host_ctrl;
1219         u16 power_control, power_caps;
1220         int pm = tp->pm_cap;
1221
1222         /* Make sure register accesses (indirect or otherwise)
1223          * will function correctly.
1224          */
1225         pci_write_config_dword(tp->pdev,
1226                                TG3PCI_MISC_HOST_CTRL,
1227                                tp->misc_host_ctrl);
1228
1229         pci_read_config_word(tp->pdev,
1230                              pm + PCI_PM_CTRL,
1231                              &power_control);
1232         power_control |= PCI_PM_CTRL_PME_STATUS;
1233         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1234         switch (state) {
1235         case PCI_D0:
1236                 power_control |= 0;
1237                 pci_write_config_word(tp->pdev,
1238                                       pm + PCI_PM_CTRL,
1239                                       power_control);
1240                 udelay(100);    /* Delay after power state change */
1241
1242                 /* Switch out of Vaux if it is a NIC */
1243                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1244                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1245
1246                 return 0;
1247
1248         case PCI_D1:
1249                 power_control |= 1;
1250                 break;
1251
1252         case PCI_D2:
1253                 power_control |= 2;
1254                 break;
1255
1256         case PCI_D3hot:
1257                 power_control |= 3;
1258                 break;
1259
1260         default:
1261                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1262                        "requested.\n",
1263                        tp->dev->name, state);
1264                 return -EINVAL;
1265         };
1266
1267         power_control |= PCI_PM_CTRL_PME_ENABLE;
1268
1269         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1270         tw32(TG3PCI_MISC_HOST_CTRL,
1271              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1272
1273         if (tp->link_config.phy_is_low_power == 0) {
1274                 tp->link_config.phy_is_low_power = 1;
1275                 tp->link_config.orig_speed = tp->link_config.speed;
1276                 tp->link_config.orig_duplex = tp->link_config.duplex;
1277                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1278         }
1279
1280         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1281                 tp->link_config.speed = SPEED_10;
1282                 tp->link_config.duplex = DUPLEX_HALF;
1283                 tp->link_config.autoneg = AUTONEG_ENABLE;
1284                 tg3_setup_phy(tp, 0);
1285         }
1286
1287         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1288                 u32 val;
1289
1290                 val = tr32(GRC_VCPU_EXT_CTRL);
1291                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1292         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1293                 int i;
1294                 u32 val;
1295
1296                 for (i = 0; i < 200; i++) {
1297                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1298                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1299                                 break;
1300                         msleep(1);
1301                 }
1302         }
1303         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1304                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1305                                                      WOL_DRV_STATE_SHUTDOWN |
1306                                                      WOL_DRV_WOL |
1307                                                      WOL_SET_MAGIC_PKT);
1308
1309         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1310
1311         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1312                 u32 mac_mode;
1313
1314                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1315                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1316                         udelay(40);
1317
1318                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1319                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1320                         else
1321                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1322
1323                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1324                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1325                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1326                 } else {
1327                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1328                 }
1329
1330                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1331                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1332
1333                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1334                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1335                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1336
1337                 tw32_f(MAC_MODE, mac_mode);
1338                 udelay(100);
1339
1340                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1341                 udelay(10);
1342         }
1343
1344         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1345             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1346              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1347                 u32 base_val;
1348
1349                 base_val = tp->pci_clock_ctrl;
1350                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1351                              CLOCK_CTRL_TXCLK_DISABLE);
1352
1353                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1354                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1355         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1356                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1357                 /* do nothing */
1358         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1359                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1360                 u32 newbits1, newbits2;
1361
1362                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1363                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1364                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1365                                     CLOCK_CTRL_TXCLK_DISABLE |
1366                                     CLOCK_CTRL_ALTCLK);
1367                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1368                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1369                         newbits1 = CLOCK_CTRL_625_CORE;
1370                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1371                 } else {
1372                         newbits1 = CLOCK_CTRL_ALTCLK;
1373                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1374                 }
1375
1376                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1377                             40);
1378
1379                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1380                             40);
1381
1382                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1383                         u32 newbits3;
1384
1385                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1386                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1387                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1388                                             CLOCK_CTRL_TXCLK_DISABLE |
1389                                             CLOCK_CTRL_44MHZ_CORE);
1390                         } else {
1391                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1392                         }
1393
1394                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1395                                     tp->pci_clock_ctrl | newbits3, 40);
1396                 }
1397         }
1398
1399         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1400             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1401                 tg3_power_down_phy(tp);
1402
1403         tg3_frob_aux_power(tp);
1404
1405         /* Workaround for unstable PLL clock */
1406         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1407             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1408                 u32 val = tr32(0x7d00);
1409
1410                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1411                 tw32(0x7d00, val);
1412                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1413                         int err;
1414
1415                         err = tg3_nvram_lock(tp);
1416                         tg3_halt_cpu(tp, RX_CPU_BASE);
1417                         if (!err)
1418                                 tg3_nvram_unlock(tp);
1419                 }
1420         }
1421
1422         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1423
1424         /* Finally, set the new power state. */
1425         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1426         udelay(100);    /* Delay after power state change */
1427
1428         return 0;
1429 }
1430
1431 static void tg3_link_report(struct tg3 *tp)
1432 {
1433         if (!netif_carrier_ok(tp->dev)) {
1434                 if (netif_msg_link(tp))
1435                         printk(KERN_INFO PFX "%s: Link is down.\n",
1436                                tp->dev->name);
1437         } else if (netif_msg_link(tp)) {
1438                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1439                        tp->dev->name,
1440                        (tp->link_config.active_speed == SPEED_1000 ?
1441                         1000 :
1442                         (tp->link_config.active_speed == SPEED_100 ?
1443                          100 : 10)),
1444                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1445                         "full" : "half"));
1446
1447                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1448                        "%s for RX.\n",
1449                        tp->dev->name,
1450                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1451                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1452         }
1453 }
1454
1455 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1456 {
1457         u32 new_tg3_flags = 0;
1458         u32 old_rx_mode = tp->rx_mode;
1459         u32 old_tx_mode = tp->tx_mode;
1460
1461         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1462
1463                 /* Convert 1000BaseX flow control bits to 1000BaseT
1464                  * bits before resolving flow control.
1465                  */
1466                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1467                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1468                                        ADVERTISE_PAUSE_ASYM);
1469                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1470
1471                         if (local_adv & ADVERTISE_1000XPAUSE)
1472                                 local_adv |= ADVERTISE_PAUSE_CAP;
1473                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1474                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1475                         if (remote_adv & LPA_1000XPAUSE)
1476                                 remote_adv |= LPA_PAUSE_CAP;
1477                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1478                                 remote_adv |= LPA_PAUSE_ASYM;
1479                 }
1480
1481                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1482                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1483                                 if (remote_adv & LPA_PAUSE_CAP)
1484                                         new_tg3_flags |=
1485                                                 (TG3_FLAG_RX_PAUSE |
1486                                                 TG3_FLAG_TX_PAUSE);
1487                                 else if (remote_adv & LPA_PAUSE_ASYM)
1488                                         new_tg3_flags |=
1489                                                 (TG3_FLAG_RX_PAUSE);
1490                         } else {
1491                                 if (remote_adv & LPA_PAUSE_CAP)
1492                                         new_tg3_flags |=
1493                                                 (TG3_FLAG_RX_PAUSE |
1494                                                 TG3_FLAG_TX_PAUSE);
1495                         }
1496                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1497                         if ((remote_adv & LPA_PAUSE_CAP) &&
1498                         (remote_adv & LPA_PAUSE_ASYM))
1499                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1500                 }
1501
1502                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1503                 tp->tg3_flags |= new_tg3_flags;
1504         } else {
1505                 new_tg3_flags = tp->tg3_flags;
1506         }
1507
1508         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1509                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1510         else
1511                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1512
1513         if (old_rx_mode != tp->rx_mode) {
1514                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1515         }
1516
1517         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1518                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1519         else
1520                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1521
1522         if (old_tx_mode != tp->tx_mode) {
1523                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1524         }
1525 }
1526
1527 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1528 {
1529         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1530         case MII_TG3_AUX_STAT_10HALF:
1531                 *speed = SPEED_10;
1532                 *duplex = DUPLEX_HALF;
1533                 break;
1534
1535         case MII_TG3_AUX_STAT_10FULL:
1536                 *speed = SPEED_10;
1537                 *duplex = DUPLEX_FULL;
1538                 break;
1539
1540         case MII_TG3_AUX_STAT_100HALF:
1541                 *speed = SPEED_100;
1542                 *duplex = DUPLEX_HALF;
1543                 break;
1544
1545         case MII_TG3_AUX_STAT_100FULL:
1546                 *speed = SPEED_100;
1547                 *duplex = DUPLEX_FULL;
1548                 break;
1549
1550         case MII_TG3_AUX_STAT_1000HALF:
1551                 *speed = SPEED_1000;
1552                 *duplex = DUPLEX_HALF;
1553                 break;
1554
1555         case MII_TG3_AUX_STAT_1000FULL:
1556                 *speed = SPEED_1000;
1557                 *duplex = DUPLEX_FULL;
1558                 break;
1559
1560         default:
1561                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1562                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1563                                  SPEED_10;
1564                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1565                                   DUPLEX_HALF;
1566                         break;
1567                 }
1568                 *speed = SPEED_INVALID;
1569                 *duplex = DUPLEX_INVALID;
1570                 break;
1571         };
1572 }
1573
1574 static void tg3_phy_copper_begin(struct tg3 *tp)
1575 {
1576         u32 new_adv;
1577         int i;
1578
1579         if (tp->link_config.phy_is_low_power) {
1580                 /* Entering low power mode.  Disable gigabit and
1581                  * 100baseT advertisements.
1582                  */
1583                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1584
1585                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1586                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1587                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1588                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1589
1590                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1591         } else if (tp->link_config.speed == SPEED_INVALID) {
1592                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1593                         tp->link_config.advertising &=
1594                                 ~(ADVERTISED_1000baseT_Half |
1595                                   ADVERTISED_1000baseT_Full);
1596
1597                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1598                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1599                         new_adv |= ADVERTISE_10HALF;
1600                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1601                         new_adv |= ADVERTISE_10FULL;
1602                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1603                         new_adv |= ADVERTISE_100HALF;
1604                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1605                         new_adv |= ADVERTISE_100FULL;
1606                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1607
1608                 if (tp->link_config.advertising &
1609                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1610                         new_adv = 0;
1611                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1612                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1613                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1614                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1615                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1616                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1617                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1618                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1619                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1620                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1621                 } else {
1622                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1623                 }
1624         } else {
1625                 /* Asking for a specific link mode. */
1626                 if (tp->link_config.speed == SPEED_1000) {
1627                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1628                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1629
1630                         if (tp->link_config.duplex == DUPLEX_FULL)
1631                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1632                         else
1633                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1634                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1635                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1636                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1637                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1638                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1639                 } else {
1640                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1641
1642                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1643                         if (tp->link_config.speed == SPEED_100) {
1644                                 if (tp->link_config.duplex == DUPLEX_FULL)
1645                                         new_adv |= ADVERTISE_100FULL;
1646                                 else
1647                                         new_adv |= ADVERTISE_100HALF;
1648                         } else {
1649                                 if (tp->link_config.duplex == DUPLEX_FULL)
1650                                         new_adv |= ADVERTISE_10FULL;
1651                                 else
1652                                         new_adv |= ADVERTISE_10HALF;
1653                         }
1654                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1655                 }
1656         }
1657
1658         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1659             tp->link_config.speed != SPEED_INVALID) {
1660                 u32 bmcr, orig_bmcr;
1661
1662                 tp->link_config.active_speed = tp->link_config.speed;
1663                 tp->link_config.active_duplex = tp->link_config.duplex;
1664
1665                 bmcr = 0;
1666                 switch (tp->link_config.speed) {
1667                 default:
1668                 case SPEED_10:
1669                         break;
1670
1671                 case SPEED_100:
1672                         bmcr |= BMCR_SPEED100;
1673                         break;
1674
1675                 case SPEED_1000:
1676                         bmcr |= TG3_BMCR_SPEED1000;
1677                         break;
1678                 };
1679
1680                 if (tp->link_config.duplex == DUPLEX_FULL)
1681                         bmcr |= BMCR_FULLDPLX;
1682
1683                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1684                     (bmcr != orig_bmcr)) {
1685                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1686                         for (i = 0; i < 1500; i++) {
1687                                 u32 tmp;
1688
1689                                 udelay(10);
1690                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1691                                     tg3_readphy(tp, MII_BMSR, &tmp))
1692                                         continue;
1693                                 if (!(tmp & BMSR_LSTATUS)) {
1694                                         udelay(40);
1695                                         break;
1696                                 }
1697                         }
1698                         tg3_writephy(tp, MII_BMCR, bmcr);
1699                         udelay(40);
1700                 }
1701         } else {
1702                 tg3_writephy(tp, MII_BMCR,
1703                              BMCR_ANENABLE | BMCR_ANRESTART);
1704         }
1705 }
1706
1707 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1708 {
1709         int err;
1710
1711         /* Turn off tap power management. */
1712         /* Set Extended packet length bit */
1713         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1714
1715         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1716         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1717
1718         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1719         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1720
1721         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1722         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1723
1724         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1725         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1726
1727         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1728         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1729
1730         udelay(40);
1731
1732         return err;
1733 }
1734
1735 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1736 {
1737         u32 adv_reg, all_mask = 0;
1738
1739         if (mask & ADVERTISED_10baseT_Half)
1740                 all_mask |= ADVERTISE_10HALF;
1741         if (mask & ADVERTISED_10baseT_Full)
1742                 all_mask |= ADVERTISE_10FULL;
1743         if (mask & ADVERTISED_100baseT_Half)
1744                 all_mask |= ADVERTISE_100HALF;
1745         if (mask & ADVERTISED_100baseT_Full)
1746                 all_mask |= ADVERTISE_100FULL;
1747
1748         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1749                 return 0;
1750
1751         if ((adv_reg & all_mask) != all_mask)
1752                 return 0;
1753         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1754                 u32 tg3_ctrl;
1755
1756                 all_mask = 0;
1757                 if (mask & ADVERTISED_1000baseT_Half)
1758                         all_mask |= ADVERTISE_1000HALF;
1759                 if (mask & ADVERTISED_1000baseT_Full)
1760                         all_mask |= ADVERTISE_1000FULL;
1761
1762                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1763                         return 0;
1764
1765                 if ((tg3_ctrl & all_mask) != all_mask)
1766                         return 0;
1767         }
1768         return 1;
1769 }
1770
1771 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1772 {
1773         int current_link_up;
1774         u32 bmsr, dummy;
1775         u16 current_speed;
1776         u8 current_duplex;
1777         int i, err;
1778
1779         tw32(MAC_EVENT, 0);
1780
1781         tw32_f(MAC_STATUS,
1782              (MAC_STATUS_SYNC_CHANGED |
1783               MAC_STATUS_CFG_CHANGED |
1784               MAC_STATUS_MI_COMPLETION |
1785               MAC_STATUS_LNKSTATE_CHANGED));
1786         udelay(40);
1787
1788         tp->mi_mode = MAC_MI_MODE_BASE;
1789         tw32_f(MAC_MI_MODE, tp->mi_mode);
1790         udelay(80);
1791
1792         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1793
1794         /* Some third-party PHYs need to be reset on link going
1795          * down.
1796          */
1797         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1798              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1799              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1800             netif_carrier_ok(tp->dev)) {
1801                 tg3_readphy(tp, MII_BMSR, &bmsr);
1802                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1803                     !(bmsr & BMSR_LSTATUS))
1804                         force_reset = 1;
1805         }
1806         if (force_reset)
1807                 tg3_phy_reset(tp);
1808
1809         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1810                 tg3_readphy(tp, MII_BMSR, &bmsr);
1811                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1812                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1813                         bmsr = 0;
1814
1815                 if (!(bmsr & BMSR_LSTATUS)) {
1816                         err = tg3_init_5401phy_dsp(tp);
1817                         if (err)
1818                                 return err;
1819
1820                         tg3_readphy(tp, MII_BMSR, &bmsr);
1821                         for (i = 0; i < 1000; i++) {
1822                                 udelay(10);
1823                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1824                                     (bmsr & BMSR_LSTATUS)) {
1825                                         udelay(40);
1826                                         break;
1827                                 }
1828                         }
1829
1830                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1831                             !(bmsr & BMSR_LSTATUS) &&
1832                             tp->link_config.active_speed == SPEED_1000) {
1833                                 err = tg3_phy_reset(tp);
1834                                 if (!err)
1835                                         err = tg3_init_5401phy_dsp(tp);
1836                                 if (err)
1837                                         return err;
1838                         }
1839                 }
1840         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1841                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1842                 /* 5701 {A0,B0} CRC bug workaround */
1843                 tg3_writephy(tp, 0x15, 0x0a75);
1844                 tg3_writephy(tp, 0x1c, 0x8c68);
1845                 tg3_writephy(tp, 0x1c, 0x8d68);
1846                 tg3_writephy(tp, 0x1c, 0x8c68);
1847         }
1848
1849         /* Clear pending interrupts... */
1850         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1851         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1852
1853         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1854                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1855         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1856                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1857
1858         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1859             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1860                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1861                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1862                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1863                 else
1864                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1865         }
1866
1867         current_link_up = 0;
1868         current_speed = SPEED_INVALID;
1869         current_duplex = DUPLEX_INVALID;
1870
1871         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1872                 u32 val;
1873
1874                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1875                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1876                 if (!(val & (1 << 10))) {
1877                         val |= (1 << 10);
1878                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1879                         goto relink;
1880                 }
1881         }
1882
1883         bmsr = 0;
1884         for (i = 0; i < 100; i++) {
1885                 tg3_readphy(tp, MII_BMSR, &bmsr);
1886                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1887                     (bmsr & BMSR_LSTATUS))
1888                         break;
1889                 udelay(40);
1890         }
1891
1892         if (bmsr & BMSR_LSTATUS) {
1893                 u32 aux_stat, bmcr;
1894
1895                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1896                 for (i = 0; i < 2000; i++) {
1897                         udelay(10);
1898                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1899                             aux_stat)
1900                                 break;
1901                 }
1902
1903                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1904                                              &current_speed,
1905                                              &current_duplex);
1906
1907                 bmcr = 0;
1908                 for (i = 0; i < 200; i++) {
1909                         tg3_readphy(tp, MII_BMCR, &bmcr);
1910                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1911                                 continue;
1912                         if (bmcr && bmcr != 0x7fff)
1913                                 break;
1914                         udelay(10);
1915                 }
1916
1917                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1918                         if (bmcr & BMCR_ANENABLE) {
1919                                 current_link_up = 1;
1920
1921                                 /* Force autoneg restart if we are exiting
1922                                  * low power mode.
1923                                  */
1924                                 if (!tg3_copper_is_advertising_all(tp,
1925                                                 tp->link_config.advertising))
1926                                         current_link_up = 0;
1927                         } else {
1928                                 current_link_up = 0;
1929                         }
1930                 } else {
1931                         if (!(bmcr & BMCR_ANENABLE) &&
1932                             tp->link_config.speed == current_speed &&
1933                             tp->link_config.duplex == current_duplex) {
1934                                 current_link_up = 1;
1935                         } else {
1936                                 current_link_up = 0;
1937                         }
1938                 }
1939
1940                 tp->link_config.active_speed = current_speed;
1941                 tp->link_config.active_duplex = current_duplex;
1942         }
1943
1944         if (current_link_up == 1 &&
1945             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1946             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1947                 u32 local_adv, remote_adv;
1948
1949                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1950                         local_adv = 0;
1951                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1952
1953                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1954                         remote_adv = 0;
1955
1956                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1957
1958                 /* If we are not advertising full pause capability,
1959                  * something is wrong.  Bring the link down and reconfigure.
1960                  */
1961                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1962                         current_link_up = 0;
1963                 } else {
1964                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1965                 }
1966         }
1967 relink:
1968         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1969                 u32 tmp;
1970
1971                 tg3_phy_copper_begin(tp);
1972
1973                 tg3_readphy(tp, MII_BMSR, &tmp);
1974                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1975                     (tmp & BMSR_LSTATUS))
1976                         current_link_up = 1;
1977         }
1978
1979         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1980         if (current_link_up == 1) {
1981                 if (tp->link_config.active_speed == SPEED_100 ||
1982                     tp->link_config.active_speed == SPEED_10)
1983                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1984                 else
1985                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1986         } else
1987                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1988
1989         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1990         if (tp->link_config.active_duplex == DUPLEX_HALF)
1991                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1992
1993         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1994         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1995                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1996                     (current_link_up == 1 &&
1997                      tp->link_config.active_speed == SPEED_10))
1998                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1999         } else {
2000                 if (current_link_up == 1)
2001                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2002         }
2003
2004         /* ??? Without this setting Netgear GA302T PHY does not
2005          * ??? send/receive packets...
2006          */
2007         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2008             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2009                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2010                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2011                 udelay(80);
2012         }
2013
2014         tw32_f(MAC_MODE, tp->mac_mode);
2015         udelay(40);
2016
2017         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2018                 /* Polled via timer. */
2019                 tw32_f(MAC_EVENT, 0);
2020         } else {
2021                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2022         }
2023         udelay(40);
2024
2025         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2026             current_link_up == 1 &&
2027             tp->link_config.active_speed == SPEED_1000 &&
2028             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2029              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2030                 udelay(120);
2031                 tw32_f(MAC_STATUS,
2032                      (MAC_STATUS_SYNC_CHANGED |
2033                       MAC_STATUS_CFG_CHANGED));
2034                 udelay(40);
2035                 tg3_write_mem(tp,
2036                               NIC_SRAM_FIRMWARE_MBOX,
2037                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2038         }
2039
2040         if (current_link_up != netif_carrier_ok(tp->dev)) {
2041                 if (current_link_up)
2042                         netif_carrier_on(tp->dev);
2043                 else
2044                         netif_carrier_off(tp->dev);
2045                 tg3_link_report(tp);
2046         }
2047
2048         return 0;
2049 }
2050
2051 struct tg3_fiber_aneginfo {
2052         int state;
2053 #define ANEG_STATE_UNKNOWN              0
2054 #define ANEG_STATE_AN_ENABLE            1
2055 #define ANEG_STATE_RESTART_INIT         2
2056 #define ANEG_STATE_RESTART              3
2057 #define ANEG_STATE_DISABLE_LINK_OK      4
2058 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2059 #define ANEG_STATE_ABILITY_DETECT       6
2060 #define ANEG_STATE_ACK_DETECT_INIT      7
2061 #define ANEG_STATE_ACK_DETECT           8
2062 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2063 #define ANEG_STATE_COMPLETE_ACK         10
2064 #define ANEG_STATE_IDLE_DETECT_INIT     11
2065 #define ANEG_STATE_IDLE_DETECT          12
2066 #define ANEG_STATE_LINK_OK              13
2067 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2068 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2069
2070         u32 flags;
2071 #define MR_AN_ENABLE            0x00000001
2072 #define MR_RESTART_AN           0x00000002
2073 #define MR_AN_COMPLETE          0x00000004
2074 #define MR_PAGE_RX              0x00000008
2075 #define MR_NP_LOADED            0x00000010
2076 #define MR_TOGGLE_TX            0x00000020
2077 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2078 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2079 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2080 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2081 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2082 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2083 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2084 #define MR_TOGGLE_RX            0x00002000
2085 #define MR_NP_RX                0x00004000
2086
2087 #define MR_LINK_OK              0x80000000
2088
2089         unsigned long link_time, cur_time;
2090
2091         u32 ability_match_cfg;
2092         int ability_match_count;
2093
2094         char ability_match, idle_match, ack_match;
2095
2096         u32 txconfig, rxconfig;
2097 #define ANEG_CFG_NP             0x00000080
2098 #define ANEG_CFG_ACK            0x00000040
2099 #define ANEG_CFG_RF2            0x00000020
2100 #define ANEG_CFG_RF1            0x00000010
2101 #define ANEG_CFG_PS2            0x00000001
2102 #define ANEG_CFG_PS1            0x00008000
2103 #define ANEG_CFG_HD             0x00004000
2104 #define ANEG_CFG_FD             0x00002000
2105 #define ANEG_CFG_INVAL          0x00001f06
2106
2107 };
2108 #define ANEG_OK         0
2109 #define ANEG_DONE       1
2110 #define ANEG_TIMER_ENAB 2
2111 #define ANEG_FAILED     -1
2112
2113 #define ANEG_STATE_SETTLE_TIME  10000
2114
2115 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2116                                    struct tg3_fiber_aneginfo *ap)
2117 {
2118         unsigned long delta;
2119         u32 rx_cfg_reg;
2120         int ret;
2121
2122         if (ap->state == ANEG_STATE_UNKNOWN) {
2123                 ap->rxconfig = 0;
2124                 ap->link_time = 0;
2125                 ap->cur_time = 0;
2126                 ap->ability_match_cfg = 0;
2127                 ap->ability_match_count = 0;
2128                 ap->ability_match = 0;
2129                 ap->idle_match = 0;
2130                 ap->ack_match = 0;
2131         }
2132         ap->cur_time++;
2133
2134         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2135                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2136
2137                 if (rx_cfg_reg != ap->ability_match_cfg) {
2138                         ap->ability_match_cfg = rx_cfg_reg;
2139                         ap->ability_match = 0;
2140                         ap->ability_match_count = 0;
2141                 } else {
2142                         if (++ap->ability_match_count > 1) {
2143                                 ap->ability_match = 1;
2144                                 ap->ability_match_cfg = rx_cfg_reg;
2145                         }
2146                 }
2147                 if (rx_cfg_reg & ANEG_CFG_ACK)
2148                         ap->ack_match = 1;
2149                 else
2150                         ap->ack_match = 0;
2151
2152                 ap->idle_match = 0;
2153         } else {
2154                 ap->idle_match = 1;
2155                 ap->ability_match_cfg = 0;
2156                 ap->ability_match_count = 0;
2157                 ap->ability_match = 0;
2158                 ap->ack_match = 0;
2159
2160                 rx_cfg_reg = 0;
2161         }
2162
2163         ap->rxconfig = rx_cfg_reg;
2164         ret = ANEG_OK;
2165
2166         switch(ap->state) {
2167         case ANEG_STATE_UNKNOWN:
2168                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2169                         ap->state = ANEG_STATE_AN_ENABLE;
2170
2171                 /* fallthru */
2172         case ANEG_STATE_AN_ENABLE:
2173                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2174                 if (ap->flags & MR_AN_ENABLE) {
2175                         ap->link_time = 0;
2176                         ap->cur_time = 0;
2177                         ap->ability_match_cfg = 0;
2178                         ap->ability_match_count = 0;
2179                         ap->ability_match = 0;
2180                         ap->idle_match = 0;
2181                         ap->ack_match = 0;
2182
2183                         ap->state = ANEG_STATE_RESTART_INIT;
2184                 } else {
2185                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2186                 }
2187                 break;
2188
2189         case ANEG_STATE_RESTART_INIT:
2190                 ap->link_time = ap->cur_time;
2191                 ap->flags &= ~(MR_NP_LOADED);
2192                 ap->txconfig = 0;
2193                 tw32(MAC_TX_AUTO_NEG, 0);
2194                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2195                 tw32_f(MAC_MODE, tp->mac_mode);
2196                 udelay(40);
2197
2198                 ret = ANEG_TIMER_ENAB;
2199                 ap->state = ANEG_STATE_RESTART;
2200
2201                 /* fallthru */
2202         case ANEG_STATE_RESTART:
2203                 delta = ap->cur_time - ap->link_time;
2204                 if (delta > ANEG_STATE_SETTLE_TIME) {
2205                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2206                 } else {
2207                         ret = ANEG_TIMER_ENAB;
2208                 }
2209                 break;
2210
2211         case ANEG_STATE_DISABLE_LINK_OK:
2212                 ret = ANEG_DONE;
2213                 break;
2214
2215         case ANEG_STATE_ABILITY_DETECT_INIT:
2216                 ap->flags &= ~(MR_TOGGLE_TX);
2217                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2218                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2219                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2220                 tw32_f(MAC_MODE, tp->mac_mode);
2221                 udelay(40);
2222
2223                 ap->state = ANEG_STATE_ABILITY_DETECT;
2224                 break;
2225
2226         case ANEG_STATE_ABILITY_DETECT:
2227                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2228                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2229                 }
2230                 break;
2231
2232         case ANEG_STATE_ACK_DETECT_INIT:
2233                 ap->txconfig |= ANEG_CFG_ACK;
2234                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2235                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2236                 tw32_f(MAC_MODE, tp->mac_mode);
2237                 udelay(40);
2238
2239                 ap->state = ANEG_STATE_ACK_DETECT;
2240
2241                 /* fallthru */
2242         case ANEG_STATE_ACK_DETECT:
2243                 if (ap->ack_match != 0) {
2244                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2245                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2246                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2247                         } else {
2248                                 ap->state = ANEG_STATE_AN_ENABLE;
2249                         }
2250                 } else if (ap->ability_match != 0 &&
2251                            ap->rxconfig == 0) {
2252                         ap->state = ANEG_STATE_AN_ENABLE;
2253                 }
2254                 break;
2255
2256         case ANEG_STATE_COMPLETE_ACK_INIT:
2257                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2258                         ret = ANEG_FAILED;
2259                         break;
2260                 }
2261                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2262                                MR_LP_ADV_HALF_DUPLEX |
2263                                MR_LP_ADV_SYM_PAUSE |
2264                                MR_LP_ADV_ASYM_PAUSE |
2265                                MR_LP_ADV_REMOTE_FAULT1 |
2266                                MR_LP_ADV_REMOTE_FAULT2 |
2267                                MR_LP_ADV_NEXT_PAGE |
2268                                MR_TOGGLE_RX |
2269                                MR_NP_RX);
2270                 if (ap->rxconfig & ANEG_CFG_FD)
2271                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2272                 if (ap->rxconfig & ANEG_CFG_HD)
2273                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2274                 if (ap->rxconfig & ANEG_CFG_PS1)
2275                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2276                 if (ap->rxconfig & ANEG_CFG_PS2)
2277                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2278                 if (ap->rxconfig & ANEG_CFG_RF1)
2279                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2280                 if (ap->rxconfig & ANEG_CFG_RF2)
2281                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2282                 if (ap->rxconfig & ANEG_CFG_NP)
2283                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2284
2285                 ap->link_time = ap->cur_time;
2286
2287                 ap->flags ^= (MR_TOGGLE_TX);
2288                 if (ap->rxconfig & 0x0008)
2289                         ap->flags |= MR_TOGGLE_RX;
2290                 if (ap->rxconfig & ANEG_CFG_NP)
2291                         ap->flags |= MR_NP_RX;
2292                 ap->flags |= MR_PAGE_RX;
2293
2294                 ap->state = ANEG_STATE_COMPLETE_ACK;
2295                 ret = ANEG_TIMER_ENAB;
2296                 break;
2297
2298         case ANEG_STATE_COMPLETE_ACK:
2299                 if (ap->ability_match != 0 &&
2300                     ap->rxconfig == 0) {
2301                         ap->state = ANEG_STATE_AN_ENABLE;
2302                         break;
2303                 }
2304                 delta = ap->cur_time - ap->link_time;
2305                 if (delta > ANEG_STATE_SETTLE_TIME) {
2306                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2307                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2308                         } else {
2309                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2310                                     !(ap->flags & MR_NP_RX)) {
2311                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2312                                 } else {
2313                                         ret = ANEG_FAILED;
2314                                 }
2315                         }
2316                 }
2317                 break;
2318
2319         case ANEG_STATE_IDLE_DETECT_INIT:
2320                 ap->link_time = ap->cur_time;
2321                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2322                 tw32_f(MAC_MODE, tp->mac_mode);
2323                 udelay(40);
2324
2325                 ap->state = ANEG_STATE_IDLE_DETECT;
2326                 ret = ANEG_TIMER_ENAB;
2327                 break;
2328
2329         case ANEG_STATE_IDLE_DETECT:
2330                 if (ap->ability_match != 0 &&
2331                     ap->rxconfig == 0) {
2332                         ap->state = ANEG_STATE_AN_ENABLE;
2333                         break;
2334                 }
2335                 delta = ap->cur_time - ap->link_time;
2336                 if (delta > ANEG_STATE_SETTLE_TIME) {
2337                         /* XXX another gem from the Broadcom driver :( */
2338                         ap->state = ANEG_STATE_LINK_OK;
2339                 }
2340                 break;
2341
2342         case ANEG_STATE_LINK_OK:
2343                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2344                 ret = ANEG_DONE;
2345                 break;
2346
2347         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2348                 /* ??? unimplemented */
2349                 break;
2350
2351         case ANEG_STATE_NEXT_PAGE_WAIT:
2352                 /* ??? unimplemented */
2353                 break;
2354
2355         default:
2356                 ret = ANEG_FAILED;
2357                 break;
2358         };
2359
2360         return ret;
2361 }
2362
2363 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2364 {
2365         int res = 0;
2366         struct tg3_fiber_aneginfo aninfo;
2367         int status = ANEG_FAILED;
2368         unsigned int tick;
2369         u32 tmp;
2370
2371         tw32_f(MAC_TX_AUTO_NEG, 0);
2372
2373         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2374         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2375         udelay(40);
2376
2377         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2378         udelay(40);
2379
2380         memset(&aninfo, 0, sizeof(aninfo));
2381         aninfo.flags |= MR_AN_ENABLE;
2382         aninfo.state = ANEG_STATE_UNKNOWN;
2383         aninfo.cur_time = 0;
2384         tick = 0;
2385         while (++tick < 195000) {
2386                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2387                 if (status == ANEG_DONE || status == ANEG_FAILED)
2388                         break;
2389
2390                 udelay(1);
2391         }
2392
2393         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2394         tw32_f(MAC_MODE, tp->mac_mode);
2395         udelay(40);
2396
2397         *flags = aninfo.flags;
2398
2399         if (status == ANEG_DONE &&
2400             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2401                              MR_LP_ADV_FULL_DUPLEX)))
2402                 res = 1;
2403
2404         return res;
2405 }
2406
2407 static void tg3_init_bcm8002(struct tg3 *tp)
2408 {
2409         u32 mac_status = tr32(MAC_STATUS);
2410         int i;
2411
2412         /* Reset when initting first time or we have a link. */
2413         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2414             !(mac_status & MAC_STATUS_PCS_SYNCED))
2415                 return;
2416
2417         /* Set PLL lock range. */
2418         tg3_writephy(tp, 0x16, 0x8007);
2419
2420         /* SW reset */
2421         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2422
2423         /* Wait for reset to complete. */
2424         /* XXX schedule_timeout() ... */
2425         for (i = 0; i < 500; i++)
2426                 udelay(10);
2427
2428         /* Config mode; select PMA/Ch 1 regs. */
2429         tg3_writephy(tp, 0x10, 0x8411);
2430
2431         /* Enable auto-lock and comdet, select txclk for tx. */
2432         tg3_writephy(tp, 0x11, 0x0a10);
2433
2434         tg3_writephy(tp, 0x18, 0x00a0);
2435         tg3_writephy(tp, 0x16, 0x41ff);
2436
2437         /* Assert and deassert POR. */
2438         tg3_writephy(tp, 0x13, 0x0400);
2439         udelay(40);
2440         tg3_writephy(tp, 0x13, 0x0000);
2441
2442         tg3_writephy(tp, 0x11, 0x0a50);
2443         udelay(40);
2444         tg3_writephy(tp, 0x11, 0x0a10);
2445
2446         /* Wait for signal to stabilize */
2447         /* XXX schedule_timeout() ... */
2448         for (i = 0; i < 15000; i++)
2449                 udelay(10);
2450
2451         /* Deselect the channel register so we can read the PHYID
2452          * later.
2453          */
2454         tg3_writephy(tp, 0x10, 0x8011);
2455 }
2456
2457 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2458 {
2459         u32 sg_dig_ctrl, sg_dig_status;
2460         u32 serdes_cfg, expected_sg_dig_ctrl;
2461         int workaround, port_a;
2462         int current_link_up;
2463
2464         serdes_cfg = 0;
2465         expected_sg_dig_ctrl = 0;
2466         workaround = 0;
2467         port_a = 1;
2468         current_link_up = 0;
2469
2470         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2471             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2472                 workaround = 1;
2473                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2474                         port_a = 0;
2475
2476                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2477                 /* preserve bits 20-23 for voltage regulator */
2478                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2479         }
2480
2481         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2482
2483         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2484                 if (sg_dig_ctrl & (1 << 31)) {
2485                         if (workaround) {
2486                                 u32 val = serdes_cfg;
2487
2488                                 if (port_a)
2489                                         val |= 0xc010000;
2490                                 else
2491                                         val |= 0x4010000;
2492                                 tw32_f(MAC_SERDES_CFG, val);
2493                         }
2494                         tw32_f(SG_DIG_CTRL, 0x01388400);
2495                 }
2496                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2497                         tg3_setup_flow_control(tp, 0, 0);
2498                         current_link_up = 1;
2499                 }
2500                 goto out;
2501         }
2502
2503         /* Want auto-negotiation.  */
2504         expected_sg_dig_ctrl = 0x81388400;
2505
2506         /* Pause capability */
2507         expected_sg_dig_ctrl |= (1 << 11);
2508
2509         /* Asymettric pause */
2510         expected_sg_dig_ctrl |= (1 << 12);
2511
2512         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2513                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2514                     tp->serdes_counter &&
2515                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2516                                     MAC_STATUS_RCVD_CFG)) ==
2517                      MAC_STATUS_PCS_SYNCED)) {
2518                         tp->serdes_counter--;
2519                         current_link_up = 1;
2520                         goto out;
2521                 }
2522 restart_autoneg:
2523                 if (workaround)
2524                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2525                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2526                 udelay(5);
2527                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2528
2529                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2530                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2531         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2532                                  MAC_STATUS_SIGNAL_DET)) {
2533                 sg_dig_status = tr32(SG_DIG_STATUS);
2534                 mac_status = tr32(MAC_STATUS);
2535
2536                 if ((sg_dig_status & (1 << 1)) &&
2537                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2538                         u32 local_adv, remote_adv;
2539
2540                         local_adv = ADVERTISE_PAUSE_CAP;
2541                         remote_adv = 0;
2542                         if (sg_dig_status & (1 << 19))
2543                                 remote_adv |= LPA_PAUSE_CAP;
2544                         if (sg_dig_status & (1 << 20))
2545                                 remote_adv |= LPA_PAUSE_ASYM;
2546
2547                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2548                         current_link_up = 1;
2549                         tp->serdes_counter = 0;
2550                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2551                 } else if (!(sg_dig_status & (1 << 1))) {
2552                         if (tp->serdes_counter)
2553                                 tp->serdes_counter--;
2554                         else {
2555                                 if (workaround) {
2556                                         u32 val = serdes_cfg;
2557
2558                                         if (port_a)
2559                                                 val |= 0xc010000;
2560                                         else
2561                                                 val |= 0x4010000;
2562
2563                                         tw32_f(MAC_SERDES_CFG, val);
2564                                 }
2565
2566                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2567                                 udelay(40);
2568
2569                                 /* Link parallel detection - link is up */
2570                                 /* only if we have PCS_SYNC and not */
2571                                 /* receiving config code words */
2572                                 mac_status = tr32(MAC_STATUS);
2573                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2574                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2575                                         tg3_setup_flow_control(tp, 0, 0);
2576                                         current_link_up = 1;
2577                                         tp->tg3_flags2 |=
2578                                                 TG3_FLG2_PARALLEL_DETECT;
2579                                         tp->serdes_counter =
2580                                                 SERDES_PARALLEL_DET_TIMEOUT;
2581                                 } else
2582                                         goto restart_autoneg;
2583                         }
2584                 }
2585         } else {
2586                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2587                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2588         }
2589
2590 out:
2591         return current_link_up;
2592 }
2593
2594 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2595 {
2596         int current_link_up = 0;
2597
2598         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
2599                 goto out;
2600
2601         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2602                 u32 flags;
2603                 int i;
2604
2605                 if (fiber_autoneg(tp, &flags)) {
2606                         u32 local_adv, remote_adv;
2607
2608                         local_adv = ADVERTISE_PAUSE_CAP;
2609                         remote_adv = 0;
2610                         if (flags & MR_LP_ADV_SYM_PAUSE)
2611                                 remote_adv |= LPA_PAUSE_CAP;
2612                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2613                                 remote_adv |= LPA_PAUSE_ASYM;
2614
2615                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2616
2617                         current_link_up = 1;
2618                 }
2619                 for (i = 0; i < 30; i++) {
2620                         udelay(20);
2621                         tw32_f(MAC_STATUS,
2622                                (MAC_STATUS_SYNC_CHANGED |
2623                                 MAC_STATUS_CFG_CHANGED));
2624                         udelay(40);
2625                         if ((tr32(MAC_STATUS) &
2626                              (MAC_STATUS_SYNC_CHANGED |
2627                               MAC_STATUS_CFG_CHANGED)) == 0)
2628                                 break;
2629                 }
2630
2631                 mac_status = tr32(MAC_STATUS);
2632                 if (current_link_up == 0 &&
2633                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2634                     !(mac_status & MAC_STATUS_RCVD_CFG))
2635                         current_link_up = 1;
2636         } else {
2637                 /* Forcing 1000FD link up. */
2638                 current_link_up = 1;
2639
2640                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2641                 udelay(40);
2642         }
2643
2644 out:
2645         return current_link_up;
2646 }
2647
2648 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2649 {
2650         u32 orig_pause_cfg;
2651         u16 orig_active_speed;
2652         u8 orig_active_duplex;
2653         u32 mac_status;
2654         int current_link_up;
2655         int i;
2656
2657         orig_pause_cfg =
2658                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2659                                   TG3_FLAG_TX_PAUSE));
2660         orig_active_speed = tp->link_config.active_speed;
2661         orig_active_duplex = tp->link_config.active_duplex;
2662
2663         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2664             netif_carrier_ok(tp->dev) &&
2665             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2666                 mac_status = tr32(MAC_STATUS);
2667                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2668                                MAC_STATUS_SIGNAL_DET |
2669                                MAC_STATUS_CFG_CHANGED |
2670                                MAC_STATUS_RCVD_CFG);
2671                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2672                                    MAC_STATUS_SIGNAL_DET)) {
2673                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2674                                             MAC_STATUS_CFG_CHANGED));
2675                         return 0;
2676                 }
2677         }
2678
2679         tw32_f(MAC_TX_AUTO_NEG, 0);
2680
2681         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2682         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2683         tw32_f(MAC_MODE, tp->mac_mode);
2684         udelay(40);
2685
2686         if (tp->phy_id == PHY_ID_BCM8002)
2687                 tg3_init_bcm8002(tp);
2688
2689         /* Enable link change event even when serdes polling.  */
2690         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2691         udelay(40);
2692
2693         current_link_up = 0;
2694         mac_status = tr32(MAC_STATUS);
2695
2696         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2697                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2698         else
2699                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2700
2701         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2702         tw32_f(MAC_MODE, tp->mac_mode);
2703         udelay(40);
2704
2705         tp->hw_status->status =
2706                 (SD_STATUS_UPDATED |
2707                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2708
2709         for (i = 0; i < 100; i++) {
2710                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2711                                     MAC_STATUS_CFG_CHANGED));
2712                 udelay(5);
2713                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2714                                          MAC_STATUS_CFG_CHANGED |
2715                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2716                         break;
2717         }
2718
2719         mac_status = tr32(MAC_STATUS);
2720         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2721                 current_link_up = 0;
2722                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2723                     tp->serdes_counter == 0) {
2724                         tw32_f(MAC_MODE, (tp->mac_mode |
2725                                           MAC_MODE_SEND_CONFIGS));
2726                         udelay(1);
2727                         tw32_f(MAC_MODE, tp->mac_mode);
2728                 }
2729         }
2730
2731         if (current_link_up == 1) {
2732                 tp->link_config.active_speed = SPEED_1000;
2733                 tp->link_config.active_duplex = DUPLEX_FULL;
2734                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2735                                     LED_CTRL_LNKLED_OVERRIDE |
2736                                     LED_CTRL_1000MBPS_ON));
2737         } else {
2738                 tp->link_config.active_speed = SPEED_INVALID;
2739                 tp->link_config.active_duplex = DUPLEX_INVALID;
2740                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2741                                     LED_CTRL_LNKLED_OVERRIDE |
2742                                     LED_CTRL_TRAFFIC_OVERRIDE));
2743         }
2744
2745         if (current_link_up != netif_carrier_ok(tp->dev)) {
2746                 if (current_link_up)
2747                         netif_carrier_on(tp->dev);
2748                 else
2749                         netif_carrier_off(tp->dev);
2750                 tg3_link_report(tp);
2751         } else {
2752                 u32 now_pause_cfg =
2753                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2754                                          TG3_FLAG_TX_PAUSE);
2755                 if (orig_pause_cfg != now_pause_cfg ||
2756                     orig_active_speed != tp->link_config.active_speed ||
2757                     orig_active_duplex != tp->link_config.active_duplex)
2758                         tg3_link_report(tp);
2759         }
2760
2761         return 0;
2762 }
2763
2764 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2765 {
2766         int current_link_up, err = 0;
2767         u32 bmsr, bmcr;
2768         u16 current_speed;
2769         u8 current_duplex;
2770
2771         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2772         tw32_f(MAC_MODE, tp->mac_mode);
2773         udelay(40);
2774
2775         tw32(MAC_EVENT, 0);
2776
2777         tw32_f(MAC_STATUS,
2778              (MAC_STATUS_SYNC_CHANGED |
2779               MAC_STATUS_CFG_CHANGED |
2780               MAC_STATUS_MI_COMPLETION |
2781               MAC_STATUS_LNKSTATE_CHANGED));
2782         udelay(40);
2783
2784         if (force_reset)
2785                 tg3_phy_reset(tp);
2786
2787         current_link_up = 0;
2788         current_speed = SPEED_INVALID;
2789         current_duplex = DUPLEX_INVALID;
2790
2791         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2792         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2793         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2794                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2795                         bmsr |= BMSR_LSTATUS;
2796                 else
2797                         bmsr &= ~BMSR_LSTATUS;
2798         }
2799
2800         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2801
2802         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2803             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2804                 /* do nothing, just check for link up at the end */
2805         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2806                 u32 adv, new_adv;
2807
2808                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2809                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2810                                   ADVERTISE_1000XPAUSE |
2811                                   ADVERTISE_1000XPSE_ASYM |
2812                                   ADVERTISE_SLCT);
2813
2814                 /* Always advertise symmetric PAUSE just like copper */
2815                 new_adv |= ADVERTISE_1000XPAUSE;
2816
2817                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2818                         new_adv |= ADVERTISE_1000XHALF;
2819                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2820                         new_adv |= ADVERTISE_1000XFULL;
2821
2822                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2823                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2824                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2825                         tg3_writephy(tp, MII_BMCR, bmcr);
2826
2827                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2828                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2829                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2830
2831                         return err;
2832                 }
2833         } else {
2834                 u32 new_bmcr;
2835
2836                 bmcr &= ~BMCR_SPEED1000;
2837                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2838
2839                 if (tp->link_config.duplex == DUPLEX_FULL)
2840                         new_bmcr |= BMCR_FULLDPLX;
2841
2842                 if (new_bmcr != bmcr) {
2843                         /* BMCR_SPEED1000 is a reserved bit that needs
2844                          * to be set on write.
2845                          */
2846                         new_bmcr |= BMCR_SPEED1000;
2847
2848                         /* Force a linkdown */
2849                         if (netif_carrier_ok(tp->dev)) {
2850                                 u32 adv;
2851
2852                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2853                                 adv &= ~(ADVERTISE_1000XFULL |
2854                                          ADVERTISE_1000XHALF |
2855                                          ADVERTISE_SLCT);
2856                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2857                                 tg3_writephy(tp, MII_BMCR, bmcr |
2858                                                            BMCR_ANRESTART |
2859                                                            BMCR_ANENABLE);
2860                                 udelay(10);
2861                                 netif_carrier_off(tp->dev);
2862                         }
2863                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2864                         bmcr = new_bmcr;
2865                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2866                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2867                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2868                             ASIC_REV_5714) {
2869                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2870                                         bmsr |= BMSR_LSTATUS;
2871                                 else
2872                                         bmsr &= ~BMSR_LSTATUS;
2873                         }
2874                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2875                 }
2876         }
2877
2878         if (bmsr & BMSR_LSTATUS) {
2879                 current_speed = SPEED_1000;
2880                 current_link_up = 1;
2881                 if (bmcr & BMCR_FULLDPLX)
2882                         current_duplex = DUPLEX_FULL;
2883                 else
2884                         current_duplex = DUPLEX_HALF;
2885
2886                 if (bmcr & BMCR_ANENABLE) {
2887                         u32 local_adv, remote_adv, common;
2888
2889                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2890                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2891                         common = local_adv & remote_adv;
2892                         if (common & (ADVERTISE_1000XHALF |
2893                                       ADVERTISE_1000XFULL)) {
2894                                 if (common & ADVERTISE_1000XFULL)
2895                                         current_duplex = DUPLEX_FULL;
2896                                 else
2897                                         current_duplex = DUPLEX_HALF;
2898
2899                                 tg3_setup_flow_control(tp, local_adv,
2900                                                        remote_adv);
2901                         }
2902                         else
2903                                 current_link_up = 0;
2904                 }
2905         }
2906
2907         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2908         if (tp->link_config.active_duplex == DUPLEX_HALF)
2909                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2910
2911         tw32_f(MAC_MODE, tp->mac_mode);
2912         udelay(40);
2913
2914         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2915
2916         tp->link_config.active_speed = current_speed;
2917         tp->link_config.active_duplex = current_duplex;
2918
2919         if (current_link_up != netif_carrier_ok(tp->dev)) {
2920                 if (current_link_up)
2921                         netif_carrier_on(tp->dev);
2922                 else {
2923                         netif_carrier_off(tp->dev);
2924                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2925                 }
2926                 tg3_link_report(tp);
2927         }
2928         return err;
2929 }
2930
2931 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2932 {
2933         if (tp->serdes_counter) {
2934                 /* Give autoneg time to complete. */
2935                 tp->serdes_counter--;
2936                 return;
2937         }
2938         if (!netif_carrier_ok(tp->dev) &&
2939             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2940                 u32 bmcr;
2941
2942                 tg3_readphy(tp, MII_BMCR, &bmcr);
2943                 if (bmcr & BMCR_ANENABLE) {
2944                         u32 phy1, phy2;
2945
2946                         /* Select shadow register 0x1f */
2947                         tg3_writephy(tp, 0x1c, 0x7c00);
2948                         tg3_readphy(tp, 0x1c, &phy1);
2949
2950                         /* Select expansion interrupt status register */
2951                         tg3_writephy(tp, 0x17, 0x0f01);
2952                         tg3_readphy(tp, 0x15, &phy2);
2953                         tg3_readphy(tp, 0x15, &phy2);
2954
2955                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2956                                 /* We have signal detect and not receiving
2957                                  * config code words, link is up by parallel
2958                                  * detection.
2959                                  */
2960
2961                                 bmcr &= ~BMCR_ANENABLE;
2962                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2963                                 tg3_writephy(tp, MII_BMCR, bmcr);
2964                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2965                         }
2966                 }
2967         }
2968         else if (netif_carrier_ok(tp->dev) &&
2969                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2970                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2971                 u32 phy2;
2972
2973                 /* Select expansion interrupt status register */
2974                 tg3_writephy(tp, 0x17, 0x0f01);
2975                 tg3_readphy(tp, 0x15, &phy2);
2976                 if (phy2 & 0x20) {
2977                         u32 bmcr;
2978
2979                         /* Config code words received, turn on autoneg. */
2980                         tg3_readphy(tp, MII_BMCR, &bmcr);
2981                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2982
2983                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2984
2985                 }
2986         }
2987 }
2988
2989 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2990 {
2991         int err;
2992
2993         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2994                 err = tg3_setup_fiber_phy(tp, force_reset);
2995         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2996                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2997         } else {
2998                 err = tg3_setup_copper_phy(tp, force_reset);
2999         }
3000
3001         if (tp->link_config.active_speed == SPEED_1000 &&
3002             tp->link_config.active_duplex == DUPLEX_HALF)
3003                 tw32(MAC_TX_LENGTHS,
3004                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3005                       (6 << TX_LENGTHS_IPG_SHIFT) |
3006                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3007         else
3008                 tw32(MAC_TX_LENGTHS,
3009                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3010                       (6 << TX_LENGTHS_IPG_SHIFT) |
3011                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3012
3013         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3014                 if (netif_carrier_ok(tp->dev)) {
3015                         tw32(HOSTCC_STAT_COAL_TICKS,
3016                              tp->coal.stats_block_coalesce_usecs);
3017                 } else {
3018                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3019                 }
3020         }
3021
3022         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3023                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3024                 if (!netif_carrier_ok(tp->dev))
3025                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3026                               tp->pwrmgmt_thresh;
3027                 else
3028                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3029                 tw32(PCIE_PWR_MGMT_THRESH, val);
3030         }
3031
3032         return err;
3033 }
3034
3035 /* This is called whenever we suspect that the system chipset is re-
3036  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3037  * is bogus tx completions. We try to recover by setting the
3038  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3039  * in the workqueue.
3040  */
3041 static void tg3_tx_recover(struct tg3 *tp)
3042 {
3043         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3044                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3045
3046         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3047                "mapped I/O cycles to the network device, attempting to "
3048                "recover. Please report the problem to the driver maintainer "
3049                "and include system chipset information.\n", tp->dev->name);
3050
3051         spin_lock(&tp->lock);
3052         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3053         spin_unlock(&tp->lock);
3054 }
3055
3056 static inline u32 tg3_tx_avail(struct tg3 *tp)
3057 {
3058         smp_mb();
3059         return (tp->tx_pending -
3060                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3061 }
3062
3063 /* Tigon3 never reports partial packet sends.  So we do not
3064  * need special logic to handle SKBs that have not had all
3065  * of their frags sent yet, like SunGEM does.
3066  */
3067 static void tg3_tx(struct tg3 *tp)
3068 {
3069         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3070         u32 sw_idx = tp->tx_cons;
3071
3072         while (sw_idx != hw_idx) {
3073                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3074                 struct sk_buff *skb = ri->skb;
3075                 int i, tx_bug = 0;
3076
3077                 if (unlikely(skb == NULL)) {
3078                         tg3_tx_recover(tp);
3079                         return;
3080                 }
3081
3082                 pci_unmap_single(tp->pdev,
3083                                  pci_unmap_addr(ri, mapping),
3084                                  skb_headlen(skb),
3085                                  PCI_DMA_TODEVICE);
3086
3087                 ri->skb = NULL;
3088
3089                 sw_idx = NEXT_TX(sw_idx);
3090
3091                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3092                         ri = &tp->tx_buffers[sw_idx];
3093                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3094                                 tx_bug = 1;
3095
3096                         pci_unmap_page(tp->pdev,
3097                                        pci_unmap_addr(ri, mapping),
3098                                        skb_shinfo(skb)->frags[i].size,
3099                                        PCI_DMA_TODEVICE);
3100
3101                         sw_idx = NEXT_TX(sw_idx);
3102                 }
3103
3104                 dev_kfree_skb(skb);
3105
3106                 if (unlikely(tx_bug)) {
3107                         tg3_tx_recover(tp);
3108                         return;
3109                 }
3110         }
3111
3112         tp->tx_cons = sw_idx;
3113
3114         /* Need to make the tx_cons update visible to tg3_start_xmit()
3115          * before checking for netif_queue_stopped().  Without the
3116          * memory barrier, there is a small possibility that tg3_start_xmit()
3117          * will miss it and cause the queue to be stopped forever.
3118          */
3119         smp_mb();
3120
3121         if (unlikely(netif_queue_stopped(tp->dev) &&
3122                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3123                 netif_tx_lock(tp->dev);
3124                 if (netif_queue_stopped(tp->dev) &&
3125                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3126                         netif_wake_queue(tp->dev);
3127                 netif_tx_unlock(tp->dev);
3128         }
3129 }
3130
3131 /* Returns size of skb allocated or < 0 on error.
3132  *
3133  * We only need to fill in the address because the other members
3134  * of the RX descriptor are invariant, see tg3_init_rings.
3135  *
3136  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3137  * posting buffers we only dirty the first cache line of the RX
3138  * descriptor (containing the address).  Whereas for the RX status
3139  * buffers the cpu only reads the last cacheline of the RX descriptor
3140  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3141  */
3142 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3143                             int src_idx, u32 dest_idx_unmasked)
3144 {
3145         struct tg3_rx_buffer_desc *desc;
3146         struct ring_info *map, *src_map;
3147         struct sk_buff *skb;
3148         dma_addr_t mapping;
3149         int skb_size, dest_idx;
3150
3151         src_map = NULL;
3152         switch (opaque_key) {
3153         case RXD_OPAQUE_RING_STD:
3154                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3155                 desc = &tp->rx_std[dest_idx];
3156                 map = &tp->rx_std_buffers[dest_idx];
3157                 if (src_idx >= 0)
3158                         src_map = &tp->rx_std_buffers[src_idx];
3159                 skb_size = tp->rx_pkt_buf_sz;
3160                 break;
3161
3162         case RXD_OPAQUE_RING_JUMBO:
3163                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3164                 desc = &tp->rx_jumbo[dest_idx];
3165                 map = &tp->rx_jumbo_buffers[dest_idx];
3166                 if (src_idx >= 0)
3167                         src_map = &tp->rx_jumbo_buffers[src_idx];
3168                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3169                 break;
3170
3171         default:
3172                 return -EINVAL;
3173         };
3174
3175         /* Do not overwrite any of the map or rp information
3176          * until we are sure we can commit to a new buffer.
3177          *
3178          * Callers depend upon this behavior and assume that
3179          * we leave everything unchanged if we fail.
3180          */
3181         skb = netdev_alloc_skb(tp->dev, skb_size);
3182         if (skb == NULL)
3183                 return -ENOMEM;
3184
3185         skb_reserve(skb, tp->rx_offset);
3186
3187         mapping = pci_map_single(tp->pdev, skb->data,
3188                                  skb_size - tp->rx_offset,
3189                                  PCI_DMA_FROMDEVICE);
3190
3191         map->skb = skb;
3192         pci_unmap_addr_set(map, mapping, mapping);
3193
3194         if (src_map != NULL)
3195                 src_map->skb = NULL;
3196
3197         desc->addr_hi = ((u64)mapping >> 32);
3198         desc->addr_lo = ((u64)mapping & 0xffffffff);
3199
3200         return skb_size;
3201 }
3202
3203 /* We only need to move over in the address because the other
3204  * members of the RX descriptor are invariant.  See notes above
3205  * tg3_alloc_rx_skb for full details.
3206  */
3207 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3208                            int src_idx, u32 dest_idx_unmasked)
3209 {
3210         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3211         struct ring_info *src_map, *dest_map;
3212         int dest_idx;
3213
3214         switch (opaque_key) {
3215         case RXD_OPAQUE_RING_STD:
3216                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3217                 dest_desc = &tp->rx_std[dest_idx];
3218                 dest_map = &tp->rx_std_buffers[dest_idx];
3219                 src_desc = &tp->rx_std[src_idx];
3220                 src_map = &tp->rx_std_buffers[src_idx];
3221                 break;
3222
3223         case RXD_OPAQUE_RING_JUMBO:
3224                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3225                 dest_desc = &tp->rx_jumbo[dest_idx];
3226                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3227                 src_desc = &tp->rx_jumbo[src_idx];
3228                 src_map = &tp->rx_jumbo_buffers[src_idx];
3229                 break;
3230
3231         default:
3232                 return;
3233         };
3234
3235         dest_map->skb = src_map->skb;
3236         pci_unmap_addr_set(dest_map, mapping,
3237                            pci_unmap_addr(src_map, mapping));
3238         dest_desc->addr_hi = src_desc->addr_hi;
3239         dest_desc->addr_lo = src_desc->addr_lo;
3240
3241         src_map->skb = NULL;
3242 }
3243
3244 #if TG3_VLAN_TAG_USED
3245 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3246 {
3247         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3248 }
3249 #endif
3250
3251 /* The RX ring scheme is composed of multiple rings which post fresh
3252  * buffers to the chip, and one special ring the chip uses to report
3253  * status back to the host.
3254  *
3255  * The special ring reports the status of received packets to the
3256  * host.  The chip does not write into the original descriptor the
3257  * RX buffer was obtained from.  The chip simply takes the original
3258  * descriptor as provided by the host, updates the status and length
3259  * field, then writes this into the next status ring entry.
3260  *
3261  * Each ring the host uses to post buffers to the chip is described
3262  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3263  * it is first placed into the on-chip ram.  When the packet's length
3264  * is known, it walks down the TG3_BDINFO entries to select the ring.
3265  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3266  * which is within the range of the new packet's length is chosen.
3267  *
3268  * The "separate ring for rx status" scheme may sound queer, but it makes
3269  * sense from a cache coherency perspective.  If only the host writes
3270  * to the buffer post rings, and only the chip writes to the rx status
3271  * rings, then cache lines never move beyond shared-modified state.
3272  * If both the host and chip were to write into the same ring, cache line
3273  * eviction could occur since both entities want it in an exclusive state.
3274  */
3275 static int tg3_rx(struct tg3 *tp, int budget)
3276 {
3277         u32 work_mask, rx_std_posted = 0;
3278         u32 sw_idx = tp->rx_rcb_ptr;
3279         u16 hw_idx;
3280         int received;
3281
3282         hw_idx = tp->hw_status->idx[0].rx_producer;
3283         /*
3284          * We need to order the read of hw_idx and the read of
3285          * the opaque cookie.
3286          */
3287         rmb();
3288         work_mask = 0;
3289         received = 0;
3290         while (sw_idx != hw_idx && budget > 0) {
3291                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3292                 unsigned int len;
3293                 struct sk_buff *skb;
3294                 dma_addr_t dma_addr;
3295                 u32 opaque_key, desc_idx, *post_ptr;
3296
3297                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3298                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3299                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3300                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3301                                                   mapping);
3302                         skb = tp->rx_std_buffers[desc_idx].skb;
3303                         post_ptr = &tp->rx_std_ptr;
3304                         rx_std_posted++;
3305                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3306                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3307                                                   mapping);
3308                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3309                         post_ptr = &tp->rx_jumbo_ptr;
3310                 }
3311                 else {
3312                         goto next_pkt_nopost;
3313                 }
3314
3315                 work_mask |= opaque_key;
3316
3317                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3318                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3319                 drop_it:
3320                         tg3_recycle_rx(tp, opaque_key,
3321                                        desc_idx, *post_ptr);
3322                 drop_it_no_recycle:
3323                         /* Other statistics kept track of by card. */
3324                         tp->net_stats.rx_dropped++;
3325                         goto next_pkt;
3326                 }
3327
3328                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3329
3330                 if (len > RX_COPY_THRESHOLD
3331                         && tp->rx_offset == 2
3332                         /* rx_offset != 2 iff this is a 5701 card running
3333                          * in PCI-X mode [see tg3_get_invariants()] */
3334                 ) {
3335                         int skb_size;
3336
3337                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3338                                                     desc_idx, *post_ptr);
3339                         if (skb_size < 0)
3340                                 goto drop_it;
3341
3342                         pci_unmap_single(tp->pdev, dma_addr,
3343                                          skb_size - tp->rx_offset,
3344                                          PCI_DMA_FROMDEVICE);
3345
3346                         skb_put(skb, len);
3347                 } else {
3348                         struct sk_buff *copy_skb;
3349
3350                         tg3_recycle_rx(tp, opaque_key,
3351                                        desc_idx, *post_ptr);
3352
3353                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3354                         if (copy_skb == NULL)
3355                                 goto drop_it_no_recycle;
3356
3357                         skb_reserve(copy_skb, 2);
3358                         skb_put(copy_skb, len);
3359                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3360                         skb_copy_from_linear_data(skb, copy_skb->data, len);
3361                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3362
3363                         /* We'll reuse the original ring buffer. */
3364                         skb = copy_skb;
3365                 }
3366
3367                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3368                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3369                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3370                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3371                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3372                 else
3373                         skb->ip_summed = CHECKSUM_NONE;
3374
3375                 skb->protocol = eth_type_trans(skb, tp->dev);
3376 #if TG3_VLAN_TAG_USED
3377                 if (tp->vlgrp != NULL &&
3378                     desc->type_flags & RXD_FLAG_VLAN) {
3379                         tg3_vlan_rx(tp, skb,
3380                                     desc->err_vlan & RXD_VLAN_MASK);
3381                 } else
3382 #endif
3383                         netif_receive_skb(skb);
3384
3385                 tp->dev->last_rx = jiffies;
3386                 received++;
3387                 budget--;
3388
3389 next_pkt:
3390                 (*post_ptr)++;
3391
3392                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3393                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3394
3395                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3396                                      TG3_64BIT_REG_LOW, idx);
3397                         work_mask &= ~RXD_OPAQUE_RING_STD;
3398                         rx_std_posted = 0;
3399                 }
3400 next_pkt_nopost:
3401                 sw_idx++;
3402                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3403
3404                 /* Refresh hw_idx to see if there is new work */
3405                 if (sw_idx == hw_idx) {
3406                         hw_idx = tp->hw_status->idx[0].rx_producer;
3407                         rmb();
3408                 }
3409         }
3410
3411         /* ACK the status ring. */
3412         tp->rx_rcb_ptr = sw_idx;
3413         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3414
3415         /* Refill RX ring(s). */
3416         if (work_mask & RXD_OPAQUE_RING_STD) {
3417                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3418                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3419                              sw_idx);
3420         }
3421         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3422                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3423                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3424                              sw_idx);
3425         }
3426         mmiowb();
3427
3428         return received;
3429 }
3430
3431 static int tg3_poll(struct net_device *netdev, int *budget)
3432 {
3433         struct tg3 *tp = netdev_priv(netdev);
3434         struct tg3_hw_status *sblk = tp->hw_status;
3435         int done;
3436
3437         /* handle link change and other phy events */
3438         if (!(tp->tg3_flags &
3439               (TG3_FLAG_USE_LINKCHG_REG |
3440                TG3_FLAG_POLL_SERDES))) {
3441                 if (sblk->status & SD_STATUS_LINK_CHG) {
3442                         sblk->status = SD_STATUS_UPDATED |
3443                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3444                         spin_lock(&tp->lock);
3445                         tg3_setup_phy(tp, 0);
3446                         spin_unlock(&tp->lock);
3447                 }
3448         }
3449
3450         /* run TX completion thread */
3451         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3452                 tg3_tx(tp);
3453                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3454                         netif_rx_complete(netdev);
3455                         schedule_work(&tp->reset_task);
3456                         return 0;
3457                 }
3458         }
3459
3460         /* run RX thread, within the bounds set by NAPI.
3461          * All RX "locking" is done by ensuring outside
3462          * code synchronizes with dev->poll()
3463          */
3464         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3465                 int orig_budget = *budget;
3466                 int work_done;
3467
3468                 if (orig_budget > netdev->quota)
3469                         orig_budget = netdev->quota;
3470
3471                 work_done = tg3_rx(tp, orig_budget);
3472
3473                 *budget -= work_done;
3474                 netdev->quota -= work_done;
3475         }
3476
3477         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3478                 tp->last_tag = sblk->status_tag;
3479                 rmb();
3480         } else
3481                 sblk->status &= ~SD_STATUS_UPDATED;
3482
3483         /* if no more work, tell net stack and NIC we're done */
3484         done = !tg3_has_work(tp);
3485         if (done) {
3486                 netif_rx_complete(netdev);
3487                 tg3_restart_ints(tp);
3488         }
3489
3490         return (done ? 0 : 1);
3491 }
3492
3493 static void tg3_irq_quiesce(struct tg3 *tp)
3494 {
3495         BUG_ON(tp->irq_sync);
3496
3497         tp->irq_sync = 1;
3498         smp_mb();
3499
3500         synchronize_irq(tp->pdev->irq);
3501 }
3502
3503 static inline int tg3_irq_sync(struct tg3 *tp)
3504 {
3505         return tp->irq_sync;
3506 }
3507
3508 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3509  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3510  * with as well.  Most of the time, this is not necessary except when
3511  * shutting down the device.
3512  */
3513 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3514 {
3515         if (irq_sync)
3516                 tg3_irq_quiesce(tp);
3517         spin_lock_bh(&tp->lock);
3518 }
3519
3520 static inline void tg3_full_unlock(struct tg3 *tp)
3521 {
3522         spin_unlock_bh(&tp->lock);
3523 }
3524
3525 /* One-shot MSI handler - Chip automatically disables interrupt
3526  * after sending MSI so driver doesn't have to do it.
3527  */
3528 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3529 {
3530         struct net_device *dev = dev_id;
3531         struct tg3 *tp = netdev_priv(dev);
3532
3533         prefetch(tp->hw_status);
3534         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3535
3536         if (likely(!tg3_irq_sync(tp)))
3537                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3538
3539         return IRQ_HANDLED;
3540 }
3541
3542 /* MSI ISR - No need to check for interrupt sharing and no need to
3543  * flush status block and interrupt mailbox. PCI ordering rules
3544  * guarantee that MSI will arrive after the status block.
3545  */
3546 static irqreturn_t tg3_msi(int irq, void *dev_id)
3547 {
3548         struct net_device *dev = dev_id;
3549         struct tg3 *tp = netdev_priv(dev);
3550
3551         prefetch(tp->hw_status);
3552         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3553         /*
3554          * Writing any value to intr-mbox-0 clears PCI INTA# and
3555          * chip-internal interrupt pending events.
3556          * Writing non-zero to intr-mbox-0 additional tells the
3557          * NIC to stop sending us irqs, engaging "in-intr-handler"
3558          * event coalescing.
3559          */
3560         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3561         if (likely(!tg3_irq_sync(tp)))
3562                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3563
3564         return IRQ_RETVAL(1);
3565 }
3566
3567 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3568 {
3569         struct net_device *dev = dev_id;
3570         struct tg3 *tp = netdev_priv(dev);
3571         struct tg3_hw_status *sblk = tp->hw_status;
3572         unsigned int handled = 1;
3573
3574         /* In INTx mode, it is possible for the interrupt to arrive at
3575          * the CPU before the status block posted prior to the interrupt.
3576          * Reading the PCI State register will confirm whether the
3577          * interrupt is ours and will flush the status block.
3578          */
3579         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3580                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3581                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3582                         handled = 0;
3583                         goto out;
3584                 }
3585         }
3586
3587         /*
3588          * Writing any value to intr-mbox-0 clears PCI INTA# and
3589          * chip-internal interrupt pending events.
3590          * Writing non-zero to intr-mbox-0 additional tells the
3591          * NIC to stop sending us irqs, engaging "in-intr-handler"
3592          * event coalescing.
3593          *
3594          * Flush the mailbox to de-assert the IRQ immediately to prevent
3595          * spurious interrupts.  The flush impacts performance but
3596          * excessive spurious interrupts can be worse in some cases.
3597          */
3598         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3599         if (tg3_irq_sync(tp))
3600                 goto out;
3601         sblk->status &= ~SD_STATUS_UPDATED;
3602         if (likely(tg3_has_work(tp))) {
3603                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3604                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3605         } else {
3606                 /* No work, shared interrupt perhaps?  re-enable
3607                  * interrupts, and flush that PCI write
3608                  */
3609                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3610                                0x00000000);
3611         }
3612 out:
3613         return IRQ_RETVAL(handled);
3614 }
3615
3616 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3617 {
3618         struct net_device *dev = dev_id;
3619         struct tg3 *tp = netdev_priv(dev);
3620         struct tg3_hw_status *sblk = tp->hw_status;
3621         unsigned int handled = 1;
3622
3623         /* In INTx mode, it is possible for the interrupt to arrive at
3624          * the CPU before the status block posted prior to the interrupt.
3625          * Reading the PCI State register will confirm whether the
3626          * interrupt is ours and will flush the status block.
3627          */
3628         if (unlikely(sblk->status_tag == tp->last_tag)) {
3629                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3630                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3631                         handled = 0;
3632                         goto out;
3633                 }
3634         }
3635
3636         /*
3637          * writing any value to intr-mbox-0 clears PCI INTA# and
3638          * chip-internal interrupt pending events.
3639          * writing non-zero to intr-mbox-0 additional tells the
3640          * NIC to stop sending us irqs, engaging "in-intr-handler"
3641          * event coalescing.
3642          *
3643          * Flush the mailbox to de-assert the IRQ immediately to prevent
3644          * spurious interrupts.  The flush impacts performance but
3645          * excessive spurious interrupts can be worse in some cases.
3646          */
3647         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3648         if (tg3_irq_sync(tp))
3649                 goto out;
3650         if (netif_rx_schedule_prep(dev)) {
3651                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3652                 /* Update last_tag to mark that this status has been
3653                  * seen. Because interrupt may be shared, we may be
3654                  * racing with tg3_poll(), so only update last_tag
3655                  * if tg3_poll() is not scheduled.
3656                  */
3657                 tp->last_tag = sblk->status_tag;
3658                 __netif_rx_schedule(dev);
3659         }
3660 out:
3661         return IRQ_RETVAL(handled);
3662 }
3663
3664 /* ISR for interrupt test */
3665 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3666 {
3667         struct net_device *dev = dev_id;
3668         struct tg3 *tp = netdev_priv(dev);
3669         struct tg3_hw_status *sblk = tp->hw_status;
3670
3671         if ((sblk->status & SD_STATUS_UPDATED) ||
3672             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3673                 tg3_disable_ints(tp);
3674                 return IRQ_RETVAL(1);
3675         }
3676         return IRQ_RETVAL(0);
3677 }
3678
3679 static int tg3_init_hw(struct tg3 *, int);
3680 static int tg3_halt(struct tg3 *, int, int);
3681
3682 /* Restart hardware after configuration changes, self-test, etc.
3683  * Invoked with tp->lock held.
3684  */
3685 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3686 {
3687         int err;
3688
3689         err = tg3_init_hw(tp, reset_phy);
3690         if (err) {
3691                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3692                        "aborting.\n", tp->dev->name);
3693                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3694                 tg3_full_unlock(tp);
3695                 del_timer_sync(&tp->timer);
3696                 tp->irq_sync = 0;
3697                 netif_poll_enable(tp->dev);
3698                 dev_close(tp->dev);
3699                 tg3_full_lock(tp, 0);
3700         }
3701         return err;
3702 }
3703
3704 #ifdef CONFIG_NET_POLL_CONTROLLER
3705 static void tg3_poll_controller(struct net_device *dev)
3706 {
3707         struct tg3 *tp = netdev_priv(dev);
3708
3709         tg3_interrupt(tp->pdev->irq, dev);
3710 }
3711 #endif
3712
3713 static void tg3_reset_task(struct work_struct *work)
3714 {
3715         struct tg3 *tp = container_of(work, struct tg3, reset_task);
3716         unsigned int restart_timer;
3717
3718         tg3_full_lock(tp, 0);
3719
3720         if (!netif_running(tp->dev)) {
3721                 tg3_full_unlock(tp);
3722                 return;
3723         }
3724
3725         tg3_full_unlock(tp);
3726
3727         tg3_netif_stop(tp);
3728
3729         tg3_full_lock(tp, 1);
3730
3731         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3732         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3733
3734         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3735                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3736                 tp->write32_rx_mbox = tg3_write_flush_reg32;
3737                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3738                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3739         }
3740
3741         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3742         if (tg3_init_hw(tp, 1))
3743                 goto out;
3744
3745         tg3_netif_start(tp);
3746
3747         if (restart_timer)
3748                 mod_timer(&tp->timer, jiffies + 1);
3749
3750 out:
3751         tg3_full_unlock(tp);
3752 }
3753
3754 static void tg3_dump_short_state(struct tg3 *tp)
3755 {
3756         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3757                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3758         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3759                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3760 }
3761
3762 static void tg3_tx_timeout(struct net_device *dev)
3763 {
3764         struct tg3 *tp = netdev_priv(dev);
3765
3766         if (netif_msg_tx_err(tp)) {
3767                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3768                        dev->name);
3769                 tg3_dump_short_state(tp);
3770         }
3771
3772         schedule_work(&tp->reset_task);
3773 }
3774
3775 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3776 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3777 {
3778         u32 base = (u32) mapping & 0xffffffff;
3779
3780         return ((base > 0xffffdcc0) &&
3781                 (base + len + 8 < base));
3782 }
3783
3784 /* Test for DMA addresses > 40-bit */
3785 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3786                                           int len)
3787 {
3788 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3789         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3790                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3791         return 0;
3792 #else
3793         return 0;
3794 #endif
3795 }
3796
3797 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3798
3799 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3800 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3801                                        u32 last_plus_one, u32 *start,
3802                                        u32 base_flags, u32 mss)
3803 {
3804         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3805         dma_addr_t new_addr = 0;
3806         u32 entry = *start;
3807         int i, ret = 0;
3808
3809         if (!new_skb) {
3810                 ret = -1;
3811         } else {
3812                 /* New SKB is guaranteed to be linear. */
3813                 entry = *start;
3814                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3815                                           PCI_DMA_TODEVICE);
3816                 /* Make sure new skb does not cross any 4G boundaries.
3817                  * Drop the packet if it does.
3818                  */
3819                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3820                         ret = -1;
3821                         dev_kfree_skb(new_skb);
3822                         new_skb = NULL;
3823                 } else {
3824                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3825                                     base_flags, 1 | (mss << 1));
3826                         *start = NEXT_TX(entry);
3827                 }
3828         }
3829
3830         /* Now clean up the sw ring entries. */
3831         i = 0;
3832         while (entry != last_plus_one) {
3833                 int len;
3834
3835                 if (i == 0)
3836                         len = skb_headlen(skb);
3837                 else
3838                         len = skb_shinfo(skb)->frags[i-1].size;
3839                 pci_unmap_single(tp->pdev,
3840                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3841                                  len, PCI_DMA_TODEVICE);
3842                 if (i == 0) {
3843                         tp->tx_buffers[entry].skb = new_skb;
3844                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3845                 } else {
3846                         tp->tx_buffers[entry].skb = NULL;
3847                 }
3848                 entry = NEXT_TX(entry);
3849                 i++;
3850         }
3851
3852         dev_kfree_skb(skb);
3853
3854         return ret;
3855 }
3856
3857 static void tg3_set_txd(struct tg3 *tp, int entry,
3858                         dma_addr_t mapping, int len, u32 flags,
3859                         u32 mss_and_is_end)
3860 {
3861         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3862         int is_end = (mss_and_is_end & 0x1);
3863         u32 mss = (mss_and_is_end >> 1);
3864         u32 vlan_tag = 0;
3865
3866         if (is_end)
3867                 flags |= TXD_FLAG_END;
3868         if (flags & TXD_FLAG_VLAN) {
3869                 vlan_tag = flags >> 16;
3870                 flags &= 0xffff;
3871         }
3872         vlan_tag |= (mss << TXD_MSS_SHIFT);
3873
3874         txd->addr_hi = ((u64) mapping >> 32);
3875         txd->addr_lo = ((u64) mapping & 0xffffffff);
3876         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3877         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3878 }
3879
3880 /* hard_start_xmit for devices that don't have any bugs and
3881  * support TG3_FLG2_HW_TSO_2 only.
3882  */
3883 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3884 {
3885         struct tg3 *tp = netdev_priv(dev);
3886         dma_addr_t mapping;
3887         u32 len, entry, base_flags, mss;
3888
3889         len = skb_headlen(skb);
3890
3891         /* We are running in BH disabled context with netif_tx_lock
3892          * and TX reclaim runs via tp->poll inside of a software
3893          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3894          * no IRQ context deadlocks to worry about either.  Rejoice!
3895          */
3896         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3897                 if (!netif_queue_stopped(dev)) {
3898                         netif_stop_queue(dev);
3899
3900                         /* This is a hard error, log it. */
3901                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3902                                "queue awake!\n", dev->name);
3903                 }
3904                 return NETDEV_TX_BUSY;
3905         }
3906
3907         entry = tp->tx_prod;
3908         base_flags = 0;
3909         mss = 0;
3910         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
3911                 int tcp_opt_len, ip_tcp_len;
3912
3913                 if (skb_header_cloned(skb) &&
3914                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3915                         dev_kfree_skb(skb);
3916                         goto out_unlock;
3917                 }
3918
3919                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3920                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3921                 else {
3922                         struct iphdr *iph = ip_hdr(skb);
3923
3924                         tcp_opt_len = tcp_optlen(skb);
3925                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
3926
3927                         iph->check = 0;
3928                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3929                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
3930                 }
3931
3932                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3933                                TXD_FLAG_CPU_POST_DMA);
3934
3935                 tcp_hdr(skb)->check = 0;
3936
3937         }
3938         else if (skb->ip_summed == CHECKSUM_PARTIAL)
3939                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3940 #if TG3_VLAN_TAG_USED
3941         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3942                 base_flags |= (TXD_FLAG_VLAN |
3943                                (vlan_tx_tag_get(skb) << 16));
3944 #endif
3945
3946         /* Queue skb data, a.k.a. the main skb fragment. */
3947         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3948
3949         tp->tx_buffers[entry].skb = skb;
3950         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3951
3952         tg3_set_txd(tp, entry, mapping, len, base_flags,
3953                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3954
3955         entry = NEXT_TX(entry);
3956
3957         /* Now loop through additional data fragments, and queue them. */
3958         if (skb_shinfo(skb)->nr_frags > 0) {
3959                 unsigned int i, last;
3960
3961                 last = skb_shinfo(skb)->nr_frags - 1;
3962                 for (i = 0; i <= last; i++) {
3963                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3964
3965                         len = frag->size;
3966                         mapping = pci_map_page(tp->pdev,
3967                                                frag->page,
3968                                                frag->page_offset,
3969                                                len, PCI_DMA_TODEVICE);
3970
3971                         tp->tx_buffers[entry].skb = NULL;
3972                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3973
3974                         tg3_set_txd(tp, entry, mapping, len,
3975                                     base_flags, (i == last) | (mss << 1));
3976
3977                         entry = NEXT_TX(entry);
3978                 }
3979         }
3980
3981         /* Packets are ready, update Tx producer idx local and on card. */
3982         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3983
3984         tp->tx_prod = entry;
3985         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3986                 netif_stop_queue(dev);
3987                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3988                         netif_wake_queue(tp->dev);
3989         }
3990
3991 out_unlock:
3992         mmiowb();
3993
3994         dev->trans_start = jiffies;
3995
3996         return NETDEV_TX_OK;
3997 }
3998
3999 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4000
4001 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4002  * TSO header is greater than 80 bytes.
4003  */
4004 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4005 {
4006         struct sk_buff *segs, *nskb;
4007
4008         /* Estimate the number of fragments in the worst case */
4009         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4010                 netif_stop_queue(tp->dev);
4011                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4012                         return NETDEV_TX_BUSY;
4013
4014                 netif_wake_queue(tp->dev);
4015         }
4016
4017         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4018         if (unlikely(IS_ERR(segs)))
4019                 goto tg3_tso_bug_end;
4020
4021         do {
4022                 nskb = segs;
4023                 segs = segs->next;
4024                 nskb->next = NULL;
4025                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4026         } while (segs);
4027
4028 tg3_tso_bug_end:
4029         dev_kfree_skb(skb);
4030
4031         return NETDEV_TX_OK;
4032 }
4033
4034 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4035  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4036  */
4037 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4038 {
4039         struct tg3 *tp = netdev_priv(dev);
4040         dma_addr_t mapping;
4041         u32 len, entry, base_flags, mss;
4042         int would_hit_hwbug;
4043
4044         len = skb_headlen(skb);
4045
4046         /* We are running in BH disabled context with netif_tx_lock
4047          * and TX reclaim runs via tp->poll inside of a software
4048          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4049          * no IRQ context deadlocks to worry about either.  Rejoice!
4050          */
4051         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4052                 if (!netif_queue_stopped(dev)) {
4053                         netif_stop_queue(dev);
4054
4055                         /* This is a hard error, log it. */
4056                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4057                                "queue awake!\n", dev->name);
4058                 }
4059                 return NETDEV_TX_BUSY;
4060         }
4061
4062         entry = tp->tx_prod;
4063         base_flags = 0;
4064         if (skb->ip_summed == CHECKSUM_PARTIAL)
4065                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4066         mss = 0;
4067         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4068                 struct iphdr *iph;
4069                 int tcp_opt_len, ip_tcp_len, hdr_len;
4070
4071                 if (skb_header_cloned(skb) &&
4072                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4073                         dev_kfree_skb(skb);
4074                         goto out_unlock;
4075                 }
4076
4077                 tcp_opt_len = tcp_optlen(skb);
4078                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4079
4080                 hdr_len = ip_tcp_len + tcp_opt_len;
4081                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4082                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4083                         return (tg3_tso_bug(tp, skb));
4084
4085                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4086                                TXD_FLAG_CPU_POST_DMA);
4087
4088                 iph = ip_hdr(skb);
4089                 iph->check = 0;
4090                 iph->tot_len = htons(mss + hdr_len);
4091                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4092                         tcp_hdr(skb)->check = 0;
4093                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4094                 } else
4095                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4096                                                                  iph->daddr, 0,
4097                                                                  IPPROTO_TCP,
4098                                                                  0);
4099
4100                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4101                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4102                         if (tcp_opt_len || iph->ihl > 5) {
4103                                 int tsflags;
4104
4105                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4106                                 mss |= (tsflags << 11);
4107                         }
4108                 } else {
4109                         if (tcp_opt_len || iph->ihl > 5) {
4110                                 int tsflags;
4111
4112                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4113                                 base_flags |= tsflags << 12;
4114                         }
4115                 }
4116         }
4117 #if TG3_VLAN_TAG_USED
4118         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4119                 base_flags |= (TXD_FLAG_VLAN |
4120                                (vlan_tx_tag_get(skb) << 16));
4121 #endif
4122
4123         /* Queue skb data, a.k.a. the main skb fragment. */
4124         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4125
4126         tp->tx_buffers[entry].skb = skb;
4127         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4128
4129         would_hit_hwbug = 0;
4130
4131         if (tg3_4g_overflow_test(mapping, len))
4132                 would_hit_hwbug = 1;
4133
4134         tg3_set_txd(tp, entry, mapping, len, base_flags,
4135                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4136
4137         entry = NEXT_TX(entry);
4138
4139         /* Now loop through additional data fragments, and queue them. */
4140         if (skb_shinfo(skb)->nr_frags > 0) {
4141                 unsigned int i, last;
4142
4143                 last = skb_shinfo(skb)->nr_frags - 1;
4144                 for (i = 0; i <= last; i++) {
4145                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4146
4147                         len = frag->size;
4148                         mapping = pci_map_page(tp->pdev,
4149                                                frag->page,
4150                                                frag->page_offset,
4151                                                len, PCI_DMA_TODEVICE);
4152
4153                         tp->tx_buffers[entry].skb = NULL;
4154                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4155
4156                         if (tg3_4g_overflow_test(mapping, len))
4157                                 would_hit_hwbug = 1;
4158
4159                         if (tg3_40bit_overflow_test(tp, mapping, len))
4160                                 would_hit_hwbug = 1;
4161
4162                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4163                                 tg3_set_txd(tp, entry, mapping, len,
4164                                             base_flags, (i == last)|(mss << 1));
4165                         else
4166                                 tg3_set_txd(tp, entry, mapping, len,
4167                                             base_flags, (i == last));
4168
4169                         entry = NEXT_TX(entry);
4170                 }
4171         }
4172
4173         if (would_hit_hwbug) {
4174                 u32 last_plus_one = entry;
4175                 u32 start;
4176
4177                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4178                 start &= (TG3_TX_RING_SIZE - 1);
4179
4180                 /* If the workaround fails due to memory/mapping
4181                  * failure, silently drop this packet.
4182                  */
4183                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4184                                                 &start, base_flags, mss))
4185                         goto out_unlock;
4186
4187                 entry = start;
4188         }
4189
4190         /* Packets are ready, update Tx producer idx local and on card. */
4191         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4192
4193         tp->tx_prod = entry;
4194         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4195                 netif_stop_queue(dev);
4196                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4197                         netif_wake_queue(tp->dev);
4198         }
4199
4200 out_unlock:
4201         mmiowb();
4202
4203         dev->trans_start = jiffies;
4204
4205         return NETDEV_TX_OK;
4206 }
4207
4208 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4209                                int new_mtu)
4210 {
4211         dev->mtu = new_mtu;
4212
4213         if (new_mtu > ETH_DATA_LEN) {
4214                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4215                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4216                         ethtool_op_set_tso(dev, 0);
4217                 }
4218                 else
4219                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4220         } else {
4221                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4222                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4223                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4224         }
4225 }
4226
4227 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4228 {
4229         struct tg3 *tp = netdev_priv(dev);
4230         int err;
4231
4232         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4233                 return -EINVAL;
4234
4235         if (!netif_running(dev)) {
4236                 /* We'll just catch it later when the
4237                  * device is up'd.
4238                  */
4239                 tg3_set_mtu(dev, tp, new_mtu);
4240                 return 0;
4241         }
4242
4243         tg3_netif_stop(tp);
4244
4245         tg3_full_lock(tp, 1);
4246
4247         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4248
4249         tg3_set_mtu(dev, tp, new_mtu);
4250
4251         err = tg3_restart_hw(tp, 0);
4252
4253         if (!err)
4254                 tg3_netif_start(tp);
4255
4256         tg3_full_unlock(tp);
4257
4258         return err;
4259 }
4260
4261 /* Free up pending packets in all rx/tx rings.
4262  *
4263  * The chip has been shut down and the driver detached from
4264  * the networking, so no interrupts or new tx packets will
4265  * end up in the driver.  tp->{tx,}lock is not held and we are not
4266  * in an interrupt context and thus may sleep.
4267  */
4268 static void tg3_free_rings(struct tg3 *tp)
4269 {
4270         struct ring_info *rxp;
4271         int i;
4272
4273         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4274                 rxp = &tp->rx_std_buffers[i];
4275
4276                 if (rxp->skb == NULL)
4277                         continue;
4278                 pci_unmap_single(tp->pdev,
4279                                  pci_unmap_addr(rxp, mapping),
4280                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4281                                  PCI_DMA_FROMDEVICE);
4282                 dev_kfree_skb_any(rxp->skb);
4283                 rxp->skb = NULL;
4284         }
4285
4286         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4287                 rxp = &tp->rx_jumbo_buffers[i];
4288
4289                 if (rxp->skb == NULL)
4290                         continue;
4291                 pci_unmap_single(tp->pdev,
4292                                  pci_unmap_addr(rxp, mapping),
4293                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4294                                  PCI_DMA_FROMDEVICE);
4295                 dev_kfree_skb_any(rxp->skb);
4296                 rxp->skb = NULL;
4297         }
4298
4299         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4300                 struct tx_ring_info *txp;
4301                 struct sk_buff *skb;
4302                 int j;
4303
4304                 txp = &tp->tx_buffers[i];
4305                 skb = txp->skb;
4306
4307                 if (skb == NULL) {
4308                         i++;
4309                         continue;
4310                 }
4311
4312                 pci_unmap_single(tp->pdev,
4313                                  pci_unmap_addr(txp, mapping),
4314                                  skb_headlen(skb),
4315                                  PCI_DMA_TODEVICE);
4316                 txp->skb = NULL;
4317
4318                 i++;
4319
4320                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4321                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4322                         pci_unmap_page(tp->pdev,
4323                                        pci_unmap_addr(txp, mapping),
4324                                        skb_shinfo(skb)->frags[j].size,
4325                                        PCI_DMA_TODEVICE);
4326                         i++;
4327                 }
4328
4329                 dev_kfree_skb_any(skb);
4330         }
4331 }
4332
4333 /* Initialize tx/rx rings for packet processing.
4334  *
4335  * The chip has been shut down and the driver detached from
4336  * the networking, so no interrupts or new tx packets will
4337  * end up in the driver.  tp->{tx,}lock are held and thus
4338  * we may not sleep.
4339  */
4340 static int tg3_init_rings(struct tg3 *tp)
4341 {
4342         u32 i;
4343
4344         /* Free up all the SKBs. */
4345         tg3_free_rings(tp);
4346
4347         /* Zero out all descriptors. */
4348         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4349         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4350         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4351         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4352
4353         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4354         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4355             (tp->dev->mtu > ETH_DATA_LEN))
4356                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4357
4358         /* Initialize invariants of the rings, we only set this
4359          * stuff once.  This works because the card does not
4360          * write into the rx buffer posting rings.
4361          */
4362         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4363                 struct tg3_rx_buffer_desc *rxd;
4364
4365                 rxd = &tp->rx_std[i];
4366                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4367                         << RXD_LEN_SHIFT;
4368                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4369                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4370                                (i << RXD_OPAQUE_INDEX_SHIFT));
4371         }
4372
4373         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4374                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4375                         struct tg3_rx_buffer_desc *rxd;
4376
4377                         rxd = &tp->rx_jumbo[i];
4378                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4379                                 << RXD_LEN_SHIFT;
4380                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4381                                 RXD_FLAG_JUMBO;
4382                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4383                                (i << RXD_OPAQUE_INDEX_SHIFT));
4384                 }
4385         }
4386
4387         /* Now allocate fresh SKBs for each rx ring. */
4388         for (i = 0; i < tp->rx_pending; i++) {
4389                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4390                         printk(KERN_WARNING PFX
4391                                "%s: Using a smaller RX standard ring, "
4392                                "only %d out of %d buffers were allocated "
4393                                "successfully.\n",
4394                                tp->dev->name, i, tp->rx_pending);
4395                         if (i == 0)
4396                                 return -ENOMEM;
4397                         tp->rx_pending = i;
4398                         break;
4399                 }
4400         }
4401
4402         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4403                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4404                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4405                                              -1, i) < 0) {
4406                                 printk(KERN_WARNING PFX
4407                                        "%s: Using a smaller RX jumbo ring, "
4408                                        "only %d out of %d buffers were "
4409                                        "allocated successfully.\n",
4410                                        tp->dev->name, i, tp->rx_jumbo_pending);
4411                                 if (i == 0) {
4412                                         tg3_free_rings(tp);
4413                                         return -ENOMEM;
4414                                 }
4415                                 tp->rx_jumbo_pending = i;
4416                                 break;
4417                         }
4418                 }
4419         }
4420         return 0;
4421 }
4422
4423 /*
4424  * Must not be invoked with interrupt sources disabled and
4425  * the hardware shutdown down.
4426  */
4427 static void tg3_free_consistent(struct tg3 *tp)
4428 {
4429         kfree(tp->rx_std_buffers);
4430         tp->rx_std_buffers = NULL;
4431         if (tp->rx_std) {
4432                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4433                                     tp->rx_std, tp->rx_std_mapping);
4434                 tp->rx_std = NULL;
4435         }
4436         if (tp->rx_jumbo) {
4437                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4438                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4439                 tp->rx_jumbo = NULL;
4440         }
4441         if (tp->rx_rcb) {
4442                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4443                                     tp->rx_rcb, tp->rx_rcb_mapping);
4444                 tp->rx_rcb = NULL;
4445         }
4446         if (tp->tx_ring) {
4447                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4448                         tp->tx_ring, tp->tx_desc_mapping);
4449                 tp->tx_ring = NULL;
4450         }
4451         if (tp->hw_status) {
4452                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4453                                     tp->hw_status, tp->status_mapping);
4454                 tp->hw_status = NULL;
4455         }
4456         if (tp->hw_stats) {
4457                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4458                                     tp->hw_stats, tp->stats_mapping);
4459                 tp->hw_stats = NULL;
4460         }
4461 }
4462
4463 /*
4464  * Must not be invoked with interrupt sources disabled and
4465  * the hardware shutdown down.  Can sleep.
4466  */
4467 static int tg3_alloc_consistent(struct tg3 *tp)
4468 {
4469         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4470                                       (TG3_RX_RING_SIZE +
4471                                        TG3_RX_JUMBO_RING_SIZE)) +
4472                                      (sizeof(struct tx_ring_info) *
4473                                       TG3_TX_RING_SIZE),
4474                                      GFP_KERNEL);
4475         if (!tp->rx_std_buffers)
4476                 return -ENOMEM;
4477
4478         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4479         tp->tx_buffers = (struct tx_ring_info *)
4480                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4481
4482         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4483                                           &tp->rx_std_mapping);
4484         if (!tp->rx_std)
4485                 goto err_out;
4486
4487         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4488                                             &tp->rx_jumbo_mapping);
4489
4490         if (!tp->rx_jumbo)
4491                 goto err_out;
4492
4493         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4494                                           &tp->rx_rcb_mapping);
4495         if (!tp->rx_rcb)
4496                 goto err_out;
4497
4498         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4499                                            &tp->tx_desc_mapping);
4500         if (!tp->tx_ring)
4501                 goto err_out;
4502
4503         tp->hw_status = pci_alloc_consistent(tp->pdev,
4504                                              TG3_HW_STATUS_SIZE,
4505                                              &tp->status_mapping);
4506         if (!tp->hw_status)
4507                 goto err_out;
4508
4509         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4510                                             sizeof(struct tg3_hw_stats),
4511                                             &tp->stats_mapping);
4512         if (!tp->hw_stats)
4513                 goto err_out;
4514
4515         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4516         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4517
4518         return 0;
4519
4520 err_out:
4521         tg3_free_consistent(tp);
4522         return -ENOMEM;
4523 }
4524
4525 #define MAX_WAIT_CNT 1000
4526
4527 /* To stop a block, clear the enable bit and poll till it
4528  * clears.  tp->lock is held.
4529  */
4530 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4531 {
4532         unsigned int i;
4533         u32 val;
4534
4535         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4536                 switch (ofs) {
4537                 case RCVLSC_MODE:
4538                 case DMAC_MODE:
4539                 case MBFREE_MODE:
4540                 case BUFMGR_MODE:
4541                 case MEMARB_MODE:
4542                         /* We can't enable/disable these bits of the
4543                          * 5705/5750, just say success.
4544                          */
4545                         return 0;
4546
4547                 default:
4548                         break;
4549                 };
4550         }
4551
4552         val = tr32(ofs);
4553         val &= ~enable_bit;
4554         tw32_f(ofs, val);
4555
4556         for (i = 0; i < MAX_WAIT_CNT; i++) {
4557                 udelay(100);
4558                 val = tr32(ofs);
4559                 if ((val & enable_bit) == 0)
4560                         break;
4561         }
4562
4563         if (i == MAX_WAIT_CNT && !silent) {
4564                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4565                        "ofs=%lx enable_bit=%x\n",
4566                        ofs, enable_bit);
4567                 return -ENODEV;
4568         }
4569
4570         return 0;
4571 }
4572
4573 /* tp->lock is held. */
4574 static int tg3_abort_hw(struct tg3 *tp, int silent)
4575 {
4576         int i, err;
4577
4578         tg3_disable_ints(tp);
4579
4580         tp->rx_mode &= ~RX_MODE_ENABLE;
4581         tw32_f(MAC_RX_MODE, tp->rx_mode);
4582         udelay(10);
4583
4584         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4585         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4586         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4587         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4588         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4589         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4590
4591         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4592         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4593         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4594         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4595         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4596         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4597         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4598
4599         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4600         tw32_f(MAC_MODE, tp->mac_mode);
4601         udelay(40);
4602
4603         tp->tx_mode &= ~TX_MODE_ENABLE;
4604         tw32_f(MAC_TX_MODE, tp->tx_mode);
4605
4606         for (i = 0; i < MAX_WAIT_CNT; i++) {
4607                 udelay(100);
4608                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4609                         break;
4610         }
4611         if (i >= MAX_WAIT_CNT) {
4612                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4613                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4614                        tp->dev->name, tr32(MAC_TX_MODE));
4615                 err |= -ENODEV;
4616         }
4617
4618         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4619         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4620         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4621
4622         tw32(FTQ_RESET, 0xffffffff);
4623         tw32(FTQ_RESET, 0x00000000);
4624
4625         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4626         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4627
4628         if (tp->hw_status)
4629                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4630         if (tp->hw_stats)
4631                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4632
4633         return err;
4634 }
4635
4636 /* tp->lock is held. */
4637 static int tg3_nvram_lock(struct tg3 *tp)
4638 {
4639         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4640                 int i;
4641
4642                 if (tp->nvram_lock_cnt == 0) {
4643                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4644                         for (i = 0; i < 8000; i++) {
4645                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4646                                         break;
4647                                 udelay(20);
4648                         }
4649                         if (i == 8000) {
4650                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4651                                 return -ENODEV;
4652                         }
4653                 }
4654                 tp->nvram_lock_cnt++;
4655         }
4656         return 0;
4657 }
4658
4659 /* tp->lock is held. */
4660 static void tg3_nvram_unlock(struct tg3 *tp)
4661 {
4662         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4663                 if (tp->nvram_lock_cnt > 0)
4664                         tp->nvram_lock_cnt--;
4665                 if (tp->nvram_lock_cnt == 0)
4666                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4667         }
4668 }
4669
4670 /* tp->lock is held. */
4671 static void tg3_enable_nvram_access(struct tg3 *tp)
4672 {
4673         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4674             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4675                 u32 nvaccess = tr32(NVRAM_ACCESS);
4676
4677                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4678         }
4679 }
4680
4681 /* tp->lock is held. */
4682 static void tg3_disable_nvram_access(struct tg3 *tp)
4683 {
4684         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4685             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4686                 u32 nvaccess = tr32(NVRAM_ACCESS);
4687
4688                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4689         }
4690 }
4691
4692 /* tp->lock is held. */
4693 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4694 {
4695         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4696                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4697
4698         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4699                 switch (kind) {
4700                 case RESET_KIND_INIT:
4701                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4702                                       DRV_STATE_START);
4703                         break;
4704
4705                 case RESET_KIND_SHUTDOWN:
4706                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4707                                       DRV_STATE_UNLOAD);
4708                         break;
4709
4710                 case RESET_KIND_SUSPEND:
4711                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4712                                       DRV_STATE_SUSPEND);
4713                         break;
4714
4715                 default:
4716                         break;
4717                 };
4718         }
4719 }
4720
4721 /* tp->lock is held. */
4722 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4723 {
4724         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4725                 switch (kind) {
4726                 case RESET_KIND_INIT:
4727                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4728                                       DRV_STATE_START_DONE);
4729                         break;
4730
4731                 case RESET_KIND_SHUTDOWN:
4732                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4733                                       DRV_STATE_UNLOAD_DONE);
4734                         break;
4735
4736                 default:
4737                         break;
4738                 };
4739         }
4740 }
4741
4742 /* tp->lock is held. */
4743 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4744 {
4745         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4746                 switch (kind) {
4747                 case RESET_KIND_INIT:
4748                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4749                                       DRV_STATE_START);
4750                         break;
4751
4752                 case RESET_KIND_SHUTDOWN:
4753                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4754                                       DRV_STATE_UNLOAD);
4755                         break;
4756
4757                 case RESET_KIND_SUSPEND:
4758                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4759                                       DRV_STATE_SUSPEND);
4760                         break;
4761
4762                 default:
4763                         break;
4764                 };
4765         }
4766 }
4767
4768 static int tg3_poll_fw(struct tg3 *tp)
4769 {
4770         int i;
4771         u32 val;
4772
4773         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4774                 /* Wait up to 20ms for init done. */
4775                 for (i = 0; i < 200; i++) {
4776                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4777                                 return 0;
4778                         udelay(100);
4779                 }
4780                 return -ENODEV;
4781         }
4782
4783         /* Wait for firmware initialization to complete. */
4784         for (i = 0; i < 100000; i++) {
4785                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4786                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4787                         break;
4788                 udelay(10);
4789         }
4790
4791         /* Chip might not be fitted with firmware.  Some Sun onboard
4792          * parts are configured like that.  So don't signal the timeout
4793          * of the above loop as an error, but do report the lack of
4794          * running firmware once.
4795          */
4796         if (i >= 100000 &&
4797             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4798                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4799
4800                 printk(KERN_INFO PFX "%s: No firmware running.\n",
4801                        tp->dev->name);
4802         }
4803
4804         return 0;
4805 }
4806
4807 static void tg3_stop_fw(struct tg3 *);
4808
4809 /* tp->lock is held. */
4810 static int tg3_chip_reset(struct tg3 *tp)
4811 {
4812         u32 val;
4813         void (*write_op)(struct tg3 *, u32, u32);
4814         int err;
4815
4816         tg3_nvram_lock(tp);
4817
4818         /* No matching tg3_nvram_unlock() after this because
4819          * chip reset below will undo the nvram lock.
4820          */
4821         tp->nvram_lock_cnt = 0;
4822
4823         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4824             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4825             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4826                 tw32(GRC_FASTBOOT_PC, 0);
4827
4828         /*
4829          * We must avoid the readl() that normally takes place.
4830          * It locks machines, causes machine checks, and other
4831          * fun things.  So, temporarily disable the 5701
4832          * hardware workaround, while we do the reset.
4833          */
4834         write_op = tp->write32;
4835         if (write_op == tg3_write_flush_reg32)
4836                 tp->write32 = tg3_write32;
4837
4838         /* Prevent the irq handler from reading or writing PCI registers
4839          * during chip reset when the memory enable bit in the PCI command
4840          * register may be cleared.  The chip does not generate interrupt
4841          * at this time, but the irq handler may still be called due to irq
4842          * sharing or irqpoll.
4843          */
4844         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
4845         if (tp->hw_status) {
4846                 tp->hw_status->status = 0;
4847                 tp->hw_status->status_tag = 0;
4848         }
4849         tp->last_tag = 0;
4850         smp_mb();
4851         synchronize_irq(tp->pdev->irq);
4852
4853         /* do the reset */
4854         val = GRC_MISC_CFG_CORECLK_RESET;
4855
4856         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4857                 if (tr32(0x7e2c) == 0x60) {
4858                         tw32(0x7e2c, 0x20);
4859                 }
4860                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4861                         tw32(GRC_MISC_CFG, (1 << 29));
4862                         val |= (1 << 29);
4863                 }
4864         }
4865
4866         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4867                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4868                 tw32(GRC_VCPU_EXT_CTRL,
4869                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4870         }
4871
4872         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4873                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4874         tw32(GRC_MISC_CFG, val);
4875
4876         /* restore 5701 hardware bug workaround write method */
4877         tp->write32 = write_op;
4878
4879         /* Unfortunately, we have to delay before the PCI read back.
4880          * Some 575X chips even will not respond to a PCI cfg access
4881          * when the reset command is given to the chip.
4882          *
4883          * How do these hardware designers expect things to work
4884          * properly if the PCI write is posted for a long period
4885          * of time?  It is always necessary to have some method by
4886          * which a register read back can occur to push the write
4887          * out which does the reset.
4888          *
4889          * For most tg3 variants the trick below was working.
4890          * Ho hum...
4891          */
4892         udelay(120);
4893
4894         /* Flush PCI posted writes.  The normal MMIO registers
4895          * are inaccessible at this time so this is the only
4896          * way to make this reliably (actually, this is no longer
4897          * the case, see above).  I tried to use indirect
4898          * register read/write but this upset some 5701 variants.
4899          */
4900         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4901
4902         udelay(120);
4903
4904         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4905                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4906                         int i;
4907                         u32 cfg_val;
4908
4909                         /* Wait for link training to complete.  */
4910                         for (i = 0; i < 5000; i++)
4911                                 udelay(100);
4912
4913                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4914                         pci_write_config_dword(tp->pdev, 0xc4,
4915                                                cfg_val | (1 << 15));
4916                 }
4917                 /* Set PCIE max payload size and clear error status.  */
4918                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4919         }
4920
4921         /* Re-enable indirect register accesses. */
4922         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4923                                tp->misc_host_ctrl);
4924
4925         /* Set MAX PCI retry to zero. */
4926         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4927         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4928             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4929                 val |= PCISTATE_RETRY_SAME_DMA;
4930         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4931
4932         pci_restore_state(tp->pdev);
4933
4934         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
4935
4936         /* Make sure PCI-X relaxed ordering bit is clear. */
4937         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4938         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4939         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4940
4941         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4942                 u32 val;
4943
4944                 /* Chip reset on 5780 will reset MSI enable bit,
4945                  * so need to restore it.
4946                  */
4947                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4948                         u16 ctrl;
4949
4950                         pci_read_config_word(tp->pdev,
4951                                              tp->msi_cap + PCI_MSI_FLAGS,
4952                                              &ctrl);
4953                         pci_write_config_word(tp->pdev,
4954                                               tp->msi_cap + PCI_MSI_FLAGS,
4955                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4956                         val = tr32(MSGINT_MODE);
4957                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4958                 }
4959
4960                 val = tr32(MEMARB_MODE);
4961                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4962
4963         } else
4964                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4965
4966         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4967                 tg3_stop_fw(tp);
4968                 tw32(0x5000, 0x400);
4969         }
4970
4971         tw32(GRC_MODE, tp->grc_mode);
4972
4973         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4974                 u32 val = tr32(0xc4);
4975
4976                 tw32(0xc4, val | (1 << 15));
4977         }
4978
4979         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4980             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4981                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4982                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4983                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4984                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4985         }
4986
4987         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4988                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4989                 tw32_f(MAC_MODE, tp->mac_mode);
4990         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4991                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4992                 tw32_f(MAC_MODE, tp->mac_mode);
4993         } else
4994                 tw32_f(MAC_MODE, 0);
4995         udelay(40);
4996
4997         err = tg3_poll_fw(tp);
4998         if (err)
4999                 return err;
5000
5001         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5002             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5003                 u32 val = tr32(0x7c00);
5004
5005                 tw32(0x7c00, val | (1 << 25));
5006         }
5007
5008         /* Reprobe ASF enable state.  */
5009         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5010         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5011         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5012         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5013                 u32 nic_cfg;
5014
5015                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5016                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5017                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5018                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5019                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5020                 }
5021         }
5022
5023         return 0;
5024 }
5025
5026 /* tp->lock is held. */
5027 static void tg3_stop_fw(struct tg3 *tp)
5028 {
5029         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5030                 u32 val;
5031                 int i;
5032
5033                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5034                 val = tr32(GRC_RX_CPU_EVENT);
5035                 val |= (1 << 14);
5036                 tw32(GRC_RX_CPU_EVENT, val);
5037
5038                 /* Wait for RX cpu to ACK the event.  */
5039                 for (i = 0; i < 100; i++) {
5040                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5041                                 break;
5042                         udelay(1);
5043                 }
5044         }
5045 }
5046
5047 /* tp->lock is held. */
5048 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5049 {
5050         int err;
5051
5052         tg3_stop_fw(tp);
5053
5054         tg3_write_sig_pre_reset(tp, kind);
5055
5056         tg3_abort_hw(tp, silent);
5057         err = tg3_chip_reset(tp);
5058
5059         tg3_write_sig_legacy(tp, kind);
5060         tg3_write_sig_post_reset(tp, kind);
5061
5062         if (err)
5063                 return err;
5064
5065         return 0;
5066 }
5067
5068 #define TG3_FW_RELEASE_MAJOR    0x0
5069 #define TG3_FW_RELASE_MINOR     0x0
5070 #define TG3_FW_RELEASE_FIX      0x0
5071 #define TG3_FW_START_ADDR       0x08000000
5072 #define TG3_FW_TEXT_ADDR        0x08000000
5073 #define TG3_FW_TEXT_LEN         0x9c0
5074 #define TG3_FW_RODATA_ADDR      0x080009c0
5075 #define TG3_FW_RODATA_LEN       0x60
5076 #define TG3_FW_DATA_ADDR        0x08000a40
5077 #define TG3_FW_DATA_LEN         0x20
5078 #define TG3_FW_SBSS_ADDR        0x08000a60
5079 #define TG3_FW_SBSS_LEN         0xc
5080 #define TG3_FW_BSS_ADDR         0x08000a70
5081 #define TG3_FW_BSS_LEN          0x10
5082
5083 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5084         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5085         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5086         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5087         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5088         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5089         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5090         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5091         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5092         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5093         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5094         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5095         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5096         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5097         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5098         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5099         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5100         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5101         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5102         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5103         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5104         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5105         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5106         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5107         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5108         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5109         0, 0, 0, 0, 0, 0,
5110         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5111         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5112         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5113         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5114         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5115         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5116         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5117         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5118         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5119         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5120         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5121         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5122         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5123         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5124         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5125         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5126         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5127         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5128         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5129         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5130         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5131         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5132         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5133         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5134         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5135         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5136         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5137         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5138         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5139         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5140         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5141         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5142         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5143         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5144         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5145         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5146         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5147         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5148         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5149         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5150         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5151         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5152         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5153         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5154         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5155         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5156         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5157         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5158         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5159         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5160         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5161         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5162         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5163         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5164         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5165         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5166         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5167         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5168         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5169         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5170         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5171         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5172         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5173         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5174         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5175 };
5176
5177 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5178         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5179         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5180         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5181         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5182         0x00000000
5183 };
5184
5185 #if 0 /* All zeros, don't eat up space with it. */
5186 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5187         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5188         0x00000000, 0x00000000, 0x00000000, 0x00000000
5189 };
5190 #endif
5191
5192 #define RX_CPU_SCRATCH_BASE     0x30000
5193 #define RX_CPU_SCRATCH_SIZE     0x04000
5194 #define TX_CPU_SCRATCH_BASE     0x34000
5195 #define TX_CPU_SCRATCH_SIZE     0x04000
5196
5197 /* tp->lock is held. */
5198 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5199 {
5200         int i;
5201
5202         BUG_ON(offset == TX_CPU_BASE &&
5203             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5204
5205         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5206                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5207
5208                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5209                 return 0;
5210         }
5211         if (offset == RX_CPU_BASE) {
5212                 for (i = 0; i < 10000; i++) {
5213                         tw32(offset + CPU_STATE, 0xffffffff);
5214                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5215                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5216                                 break;
5217                 }
5218
5219                 tw32(offset + CPU_STATE, 0xffffffff);
5220                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5221                 udelay(10);
5222         } else {
5223                 for (i = 0; i < 10000; i++) {
5224                         tw32(offset + CPU_STATE, 0xffffffff);
5225                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5226                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5227                                 break;
5228                 }
5229         }
5230
5231         if (i >= 10000) {
5232                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5233                        "and %s CPU\n",
5234                        tp->dev->name,
5235                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5236                 return -ENODEV;
5237         }
5238
5239         /* Clear firmware's nvram arbitration. */
5240         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5241                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5242         return 0;
5243 }
5244
5245 struct fw_info {
5246         unsigned int text_base;
5247         unsigned int text_len;
5248         const u32 *text_data;
5249         unsigned int rodata_base;
5250         unsigned int rodata_len;
5251         const u32 *rodata_data;
5252         unsigned int data_base;
5253         unsigned int data_len;
5254         const u32 *data_data;
5255 };
5256
5257 /* tp->lock is held. */
5258 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5259                                  int cpu_scratch_size, struct fw_info *info)
5260 {
5261         int err, lock_err, i;
5262         void (*write_op)(struct tg3 *, u32, u32);
5263
5264         if (cpu_base == TX_CPU_BASE &&
5265             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5266                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5267                        "TX cpu firmware on %s which is 5705.\n",
5268                        tp->dev->name);
5269                 return -EINVAL;
5270         }
5271
5272         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5273                 write_op = tg3_write_mem;
5274         else
5275                 write_op = tg3_write_indirect_reg32;
5276
5277         /* It is possible that bootcode is still loading at this point.
5278          * Get the nvram lock first before halting the cpu.
5279          */
5280         lock_err = tg3_nvram_lock(tp);
5281         err = tg3_halt_cpu(tp, cpu_base);
5282         if (!lock_err)
5283                 tg3_nvram_unlock(tp);
5284         if (err)
5285                 goto out;
5286
5287         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5288                 write_op(tp, cpu_scratch_base + i, 0);
5289         tw32(cpu_base + CPU_STATE, 0xffffffff);
5290         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5291         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5292                 write_op(tp, (cpu_scratch_base +
5293                               (info->text_base & 0xffff) +
5294                               (i * sizeof(u32))),
5295                          (info->text_data ?
5296                           info->text_data[i] : 0));
5297         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5298                 write_op(tp, (cpu_scratch_base +
5299                               (info->rodata_base & 0xffff) +
5300                               (i * sizeof(u32))),
5301                          (info->rodata_data ?
5302                           info->rodata_data[i] : 0));
5303         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5304                 write_op(tp, (cpu_scratch_base +
5305                               (info->data_base & 0xffff) +
5306                               (i * sizeof(u32))),
5307                          (info->data_data ?
5308                           info->data_data[i] : 0));
5309
5310         err = 0;
5311
5312 out:
5313         return err;
5314 }
5315
5316 /* tp->lock is held. */
5317 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5318 {
5319         struct fw_info info;
5320         int err, i;
5321
5322         info.text_base = TG3_FW_TEXT_ADDR;
5323         info.text_len = TG3_FW_TEXT_LEN;
5324         info.text_data = &tg3FwText[0];
5325         info.rodata_base = TG3_FW_RODATA_ADDR;
5326         info.rodata_len = TG3_FW_RODATA_LEN;
5327         info.rodata_data = &tg3FwRodata[0];
5328         info.data_base = TG3_FW_DATA_ADDR;
5329         info.data_len = TG3_FW_DATA_LEN;
5330         info.data_data = NULL;
5331
5332         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5333                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5334                                     &info);
5335         if (err)
5336                 return err;
5337
5338         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5339                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5340                                     &info);
5341         if (err)
5342                 return err;
5343
5344         /* Now startup only the RX cpu. */
5345         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5346         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5347
5348         for (i = 0; i < 5; i++) {
5349                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5350                         break;
5351                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5352                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5353                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5354                 udelay(1000);
5355         }
5356         if (i >= 5) {
5357                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5358                        "to set RX CPU PC, is %08x should be %08x\n",
5359                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5360                        TG3_FW_TEXT_ADDR);
5361                 return -ENODEV;
5362         }
5363         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5364         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5365
5366         return 0;
5367 }
5368
5369
5370 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5371 #define TG3_TSO_FW_RELASE_MINOR         0x6
5372 #define TG3_TSO_FW_RELEASE_FIX          0x0
5373 #define TG3_TSO_FW_START_ADDR           0x08000000
5374 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5375 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5376 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5377 #define TG3_TSO_FW_RODATA_LEN           0x60
5378 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5379 #define TG3_TSO_FW_DATA_LEN             0x30
5380 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5381 #define TG3_TSO_FW_SBSS_LEN             0x2c
5382 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5383 #define TG3_TSO_FW_BSS_LEN              0x894
5384
5385 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5386         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5387         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5388         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5389         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5390         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5391         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5392         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5393         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5394         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5395         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5396         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5397         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5398         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5399         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5400         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5401         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5402         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5403         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5404         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5405         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5406         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5407         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5408         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5409         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5410         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5411         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5412         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5413         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5414         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5415         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5416         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5417         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5418         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5419         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5420         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5421         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5422         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5423         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5424         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5425         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5426         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5427         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5428         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5429         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5430         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5431         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5432         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5433         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5434         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5435         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5436         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5437         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5438         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5439         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5440         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5441         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5442         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5443         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5444         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5445         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5446         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5447         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5448         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5449         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5450         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5451         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5452         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5453         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5454         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5455         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5456         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5457         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5458         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5459         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5460         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5461         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5462         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5463         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5464         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5465         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5466         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5467         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5468         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5469         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5470         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5471         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5472         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5473         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5474         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5475         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5476         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5477         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5478         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5479         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5480         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5481         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5482         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5483         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5484         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5485         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5486         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5487         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5488         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5489         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5490         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5491         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5492         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5493         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5494         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5495         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5496         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5497         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5498         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5499         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5500         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5501         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5502         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5503         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5504         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5505         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5506         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5507         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5508         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5509         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5510         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5511         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5512         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5513         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5514         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5515         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5516         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5517         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5518         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5519         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5520         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5521         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5522         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5523         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5524         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5525         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5526         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5527         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5528         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5529         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5530         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5531         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5532         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5533         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5534         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5535         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5536         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5537         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5538         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5539         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5540         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5541         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5542         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5543         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5544         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5545         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5546         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5547         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5548         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5549         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5550         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5551         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5552         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5553         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5554         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5555         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5556         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5557         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5558         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5559         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5560         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5561         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5562         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5563         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5564         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5565         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5566         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5567         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5568         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5569         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5570         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5571         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5572         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5573         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5574         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5575         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5576         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5577         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5578         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5579         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5580         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5581         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5582         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5583         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5584         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5585         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5586         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5587         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5588         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5589         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5590         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5591         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5592         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5593         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5594         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5595         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5596         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5597         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5598         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5599         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5600         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5601         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5602         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5603         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5604         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5605         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5606         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5607         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5608         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5609         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5610         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5611         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5612         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5613         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5614         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5615         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5616         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5617         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5618         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5619         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5620         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5621         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5622         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5623         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5624         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5625         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5626         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5627         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5628         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5629         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5630         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5631         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5632         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5633         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5634         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5635         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5636         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5637         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5638         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5639         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5640         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5641         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5642         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5643         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5644         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,