[IP]: Introduce ip_hdrlen()
[linux-3.10.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2007 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40 #include <linux/dma-mapping.h>
41
42 #include <net/checksum.h>
43 #include <net/ip.h>
44
45 #include <asm/system.h>
46 #include <asm/io.h>
47 #include <asm/byteorder.h>
48 #include <asm/uaccess.h>
49
50 #ifdef CONFIG_SPARC64
51 #include <asm/idprom.h>
52 #include <asm/oplib.h>
53 #include <asm/pbm.h>
54 #endif
55
56 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
57 #define TG3_VLAN_TAG_USED 1
58 #else
59 #define TG3_VLAN_TAG_USED 0
60 #endif
61
62 #define TG3_TSO_SUPPORT 1
63
64 #include "tg3.h"
65
66 #define DRV_MODULE_NAME         "tg3"
67 #define PFX DRV_MODULE_NAME     ": "
68 #define DRV_MODULE_VERSION      "3.75"
69 #define DRV_MODULE_RELDATE      "March 23, 2007"
70
71 #define TG3_DEF_MAC_MODE        0
72 #define TG3_DEF_RX_MODE         0
73 #define TG3_DEF_TX_MODE         0
74 #define TG3_DEF_MSG_ENABLE        \
75         (NETIF_MSG_DRV          | \
76          NETIF_MSG_PROBE        | \
77          NETIF_MSG_LINK         | \
78          NETIF_MSG_TIMER        | \
79          NETIF_MSG_IFDOWN       | \
80          NETIF_MSG_IFUP         | \
81          NETIF_MSG_RX_ERR       | \
82          NETIF_MSG_TX_ERR)
83
84 /* length of time before we decide the hardware is borked,
85  * and dev->tx_timeout() should be called to fix the problem
86  */
87 #define TG3_TX_TIMEOUT                  (5 * HZ)
88
89 /* hardware minimum and maximum for a single frame's data payload */
90 #define TG3_MIN_MTU                     60
91 #define TG3_MAX_MTU(tp) \
92         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
93
94 /* These numbers seem to be hard coded in the NIC firmware somehow.
95  * You can't change the ring sizes, but you can change where you place
96  * them in the NIC onboard memory.
97  */
98 #define TG3_RX_RING_SIZE                512
99 #define TG3_DEF_RX_RING_PENDING         200
100 #define TG3_RX_JUMBO_RING_SIZE          256
101 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
102
103 /* Do not place this n-ring entries value into the tp struct itself,
104  * we really want to expose these constants to GCC so that modulo et
105  * al.  operations are done with shifts and masks instead of with
106  * hw multiply/modulo instructions.  Another solution would be to
107  * replace things like '% foo' with '& (foo - 1)'.
108  */
109 #define TG3_RX_RCB_RING_SIZE(tp)        \
110         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
111
112 #define TG3_TX_RING_SIZE                512
113 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
114
115 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
116                                  TG3_RX_RING_SIZE)
117 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
118                                  TG3_RX_JUMBO_RING_SIZE)
119 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
120                                    TG3_RX_RCB_RING_SIZE(tp))
121 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
122                                  TG3_TX_RING_SIZE)
123 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
124
125 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
126 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
127
128 /* minimum number of free TX descriptors required to wake up TX process */
129 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
130
131 /* number of ETHTOOL_GSTATS u64's */
132 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
133
134 #define TG3_NUM_TEST            6
135
136 static char version[] __devinitdata =
137         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
138
139 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
140 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
141 MODULE_LICENSE("GPL");
142 MODULE_VERSION(DRV_MODULE_VERSION);
143
144 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
145 module_param(tg3_debug, int, 0);
146 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
147
148 static struct pci_device_id tg3_pci_tbl[] = {
149         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
202         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
203         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
204         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
205         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
206         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
207         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
208         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
209         {}
210 };
211
212 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
213
214 static const struct {
215         const char string[ETH_GSTRING_LEN];
216 } ethtool_stats_keys[TG3_NUM_STATS] = {
217         { "rx_octets" },
218         { "rx_fragments" },
219         { "rx_ucast_packets" },
220         { "rx_mcast_packets" },
221         { "rx_bcast_packets" },
222         { "rx_fcs_errors" },
223         { "rx_align_errors" },
224         { "rx_xon_pause_rcvd" },
225         { "rx_xoff_pause_rcvd" },
226         { "rx_mac_ctrl_rcvd" },
227         { "rx_xoff_entered" },
228         { "rx_frame_too_long_errors" },
229         { "rx_jabbers" },
230         { "rx_undersize_packets" },
231         { "rx_in_length_errors" },
232         { "rx_out_length_errors" },
233         { "rx_64_or_less_octet_packets" },
234         { "rx_65_to_127_octet_packets" },
235         { "rx_128_to_255_octet_packets" },
236         { "rx_256_to_511_octet_packets" },
237         { "rx_512_to_1023_octet_packets" },
238         { "rx_1024_to_1522_octet_packets" },
239         { "rx_1523_to_2047_octet_packets" },
240         { "rx_2048_to_4095_octet_packets" },
241         { "rx_4096_to_8191_octet_packets" },
242         { "rx_8192_to_9022_octet_packets" },
243
244         { "tx_octets" },
245         { "tx_collisions" },
246
247         { "tx_xon_sent" },
248         { "tx_xoff_sent" },
249         { "tx_flow_control" },
250         { "tx_mac_errors" },
251         { "tx_single_collisions" },
252         { "tx_mult_collisions" },
253         { "tx_deferred" },
254         { "tx_excessive_collisions" },
255         { "tx_late_collisions" },
256         { "tx_collide_2times" },
257         { "tx_collide_3times" },
258         { "tx_collide_4times" },
259         { "tx_collide_5times" },
260         { "tx_collide_6times" },
261         { "tx_collide_7times" },
262         { "tx_collide_8times" },
263         { "tx_collide_9times" },
264         { "tx_collide_10times" },
265         { "tx_collide_11times" },
266         { "tx_collide_12times" },
267         { "tx_collide_13times" },
268         { "tx_collide_14times" },
269         { "tx_collide_15times" },
270         { "tx_ucast_packets" },
271         { "tx_mcast_packets" },
272         { "tx_bcast_packets" },
273         { "tx_carrier_sense_errors" },
274         { "tx_discards" },
275         { "tx_errors" },
276
277         { "dma_writeq_full" },
278         { "dma_write_prioq_full" },
279         { "rxbds_empty" },
280         { "rx_discards" },
281         { "rx_errors" },
282         { "rx_threshold_hit" },
283
284         { "dma_readq_full" },
285         { "dma_read_prioq_full" },
286         { "tx_comp_queue_full" },
287
288         { "ring_set_send_prod_index" },
289         { "ring_status_update" },
290         { "nic_irqs" },
291         { "nic_avoided_irqs" },
292         { "nic_tx_threshold_hit" }
293 };
294
295 static const struct {
296         const char string[ETH_GSTRING_LEN];
297 } ethtool_test_keys[TG3_NUM_TEST] = {
298         { "nvram test     (online) " },
299         { "link test      (online) " },
300         { "register test  (offline)" },
301         { "memory test    (offline)" },
302         { "loopback test  (offline)" },
303         { "interrupt test (offline)" },
304 };
305
306 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
307 {
308         writel(val, tp->regs + off);
309 }
310
311 static u32 tg3_read32(struct tg3 *tp, u32 off)
312 {
313         return (readl(tp->regs + off));
314 }
315
316 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
317 {
318         unsigned long flags;
319
320         spin_lock_irqsave(&tp->indirect_lock, flags);
321         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
322         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
323         spin_unlock_irqrestore(&tp->indirect_lock, flags);
324 }
325
326 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
327 {
328         writel(val, tp->regs + off);
329         readl(tp->regs + off);
330 }
331
332 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
333 {
334         unsigned long flags;
335         u32 val;
336
337         spin_lock_irqsave(&tp->indirect_lock, flags);
338         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
339         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
340         spin_unlock_irqrestore(&tp->indirect_lock, flags);
341         return val;
342 }
343
344 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
345 {
346         unsigned long flags;
347
348         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
349                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
350                                        TG3_64BIT_REG_LOW, val);
351                 return;
352         }
353         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
354                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
355                                        TG3_64BIT_REG_LOW, val);
356                 return;
357         }
358
359         spin_lock_irqsave(&tp->indirect_lock, flags);
360         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
361         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
362         spin_unlock_irqrestore(&tp->indirect_lock, flags);
363
364         /* In indirect mode when disabling interrupts, we also need
365          * to clear the interrupt bit in the GRC local ctrl register.
366          */
367         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
368             (val == 0x1)) {
369                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
370                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
371         }
372 }
373
374 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
375 {
376         unsigned long flags;
377         u32 val;
378
379         spin_lock_irqsave(&tp->indirect_lock, flags);
380         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
381         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
382         spin_unlock_irqrestore(&tp->indirect_lock, flags);
383         return val;
384 }
385
386 /* usec_wait specifies the wait time in usec when writing to certain registers
387  * where it is unsafe to read back the register without some delay.
388  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
389  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
390  */
391 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
392 {
393         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
394             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
395                 /* Non-posted methods */
396                 tp->write32(tp, off, val);
397         else {
398                 /* Posted method */
399                 tg3_write32(tp, off, val);
400                 if (usec_wait)
401                         udelay(usec_wait);
402                 tp->read32(tp, off);
403         }
404         /* Wait again after the read for the posted method to guarantee that
405          * the wait time is met.
406          */
407         if (usec_wait)
408                 udelay(usec_wait);
409 }
410
411 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
412 {
413         tp->write32_mbox(tp, off, val);
414         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
415             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
416                 tp->read32_mbox(tp, off);
417 }
418
419 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
420 {
421         void __iomem *mbox = tp->regs + off;
422         writel(val, mbox);
423         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
424                 writel(val, mbox);
425         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
426                 readl(mbox);
427 }
428
429 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
430 {
431         return (readl(tp->regs + off + GRCMBOX_BASE));
432 }
433
434 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
435 {
436         writel(val, tp->regs + off + GRCMBOX_BASE);
437 }
438
439 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
440 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
441 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
442 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
443 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
444
445 #define tw32(reg,val)           tp->write32(tp, reg, val)
446 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
447 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
448 #define tr32(reg)               tp->read32(tp, reg)
449
450 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
451 {
452         unsigned long flags;
453
454         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
455             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
456                 return;
457
458         spin_lock_irqsave(&tp->indirect_lock, flags);
459         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
460                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
461                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
462
463                 /* Always leave this as zero. */
464                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
465         } else {
466                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
467                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
468
469                 /* Always leave this as zero. */
470                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
471         }
472         spin_unlock_irqrestore(&tp->indirect_lock, flags);
473 }
474
475 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
476 {
477         unsigned long flags;
478
479         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
480             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
481                 *val = 0;
482                 return;
483         }
484
485         spin_lock_irqsave(&tp->indirect_lock, flags);
486         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
487                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
488                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
489
490                 /* Always leave this as zero. */
491                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
492         } else {
493                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
494                 *val = tr32(TG3PCI_MEM_WIN_DATA);
495
496                 /* Always leave this as zero. */
497                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
498         }
499         spin_unlock_irqrestore(&tp->indirect_lock, flags);
500 }
501
502 static void tg3_disable_ints(struct tg3 *tp)
503 {
504         tw32(TG3PCI_MISC_HOST_CTRL,
505              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
506         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
507 }
508
509 static inline void tg3_cond_int(struct tg3 *tp)
510 {
511         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
512             (tp->hw_status->status & SD_STATUS_UPDATED))
513                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
514         else
515                 tw32(HOSTCC_MODE, tp->coalesce_mode |
516                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
517 }
518
519 static void tg3_enable_ints(struct tg3 *tp)
520 {
521         tp->irq_sync = 0;
522         wmb();
523
524         tw32(TG3PCI_MISC_HOST_CTRL,
525              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
526         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
527                        (tp->last_tag << 24));
528         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
529                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
530                                (tp->last_tag << 24));
531         tg3_cond_int(tp);
532 }
533
534 static inline unsigned int tg3_has_work(struct tg3 *tp)
535 {
536         struct tg3_hw_status *sblk = tp->hw_status;
537         unsigned int work_exists = 0;
538
539         /* check for phy events */
540         if (!(tp->tg3_flags &
541               (TG3_FLAG_USE_LINKCHG_REG |
542                TG3_FLAG_POLL_SERDES))) {
543                 if (sblk->status & SD_STATUS_LINK_CHG)
544                         work_exists = 1;
545         }
546         /* check for RX/TX work to do */
547         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
548             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
549                 work_exists = 1;
550
551         return work_exists;
552 }
553
554 /* tg3_restart_ints
555  *  similar to tg3_enable_ints, but it accurately determines whether there
556  *  is new work pending and can return without flushing the PIO write
557  *  which reenables interrupts
558  */
559 static void tg3_restart_ints(struct tg3 *tp)
560 {
561         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
562                      tp->last_tag << 24);
563         mmiowb();
564
565         /* When doing tagged status, this work check is unnecessary.
566          * The last_tag we write above tells the chip which piece of
567          * work we've completed.
568          */
569         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
570             tg3_has_work(tp))
571                 tw32(HOSTCC_MODE, tp->coalesce_mode |
572                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
573 }
574
575 static inline void tg3_netif_stop(struct tg3 *tp)
576 {
577         tp->dev->trans_start = jiffies; /* prevent tx timeout */
578         netif_poll_disable(tp->dev);
579         netif_tx_disable(tp->dev);
580 }
581
582 static inline void tg3_netif_start(struct tg3 *tp)
583 {
584         netif_wake_queue(tp->dev);
585         /* NOTE: unconditional netif_wake_queue is only appropriate
586          * so long as all callers are assured to have free tx slots
587          * (such as after tg3_init_hw)
588          */
589         netif_poll_enable(tp->dev);
590         tp->hw_status->status |= SD_STATUS_UPDATED;
591         tg3_enable_ints(tp);
592 }
593
594 static void tg3_switch_clocks(struct tg3 *tp)
595 {
596         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
597         u32 orig_clock_ctrl;
598
599         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
600                 return;
601
602         orig_clock_ctrl = clock_ctrl;
603         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
604                        CLOCK_CTRL_CLKRUN_OENABLE |
605                        0x1f);
606         tp->pci_clock_ctrl = clock_ctrl;
607
608         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
609                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
610                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
611                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
612                 }
613         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
614                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
615                             clock_ctrl |
616                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
617                             40);
618                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
619                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
620                             40);
621         }
622         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
623 }
624
625 #define PHY_BUSY_LOOPS  5000
626
627 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
628 {
629         u32 frame_val;
630         unsigned int loops;
631         int ret;
632
633         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
634                 tw32_f(MAC_MI_MODE,
635                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
636                 udelay(80);
637         }
638
639         *val = 0x0;
640
641         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
642                       MI_COM_PHY_ADDR_MASK);
643         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
644                       MI_COM_REG_ADDR_MASK);
645         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
646
647         tw32_f(MAC_MI_COM, frame_val);
648
649         loops = PHY_BUSY_LOOPS;
650         while (loops != 0) {
651                 udelay(10);
652                 frame_val = tr32(MAC_MI_COM);
653
654                 if ((frame_val & MI_COM_BUSY) == 0) {
655                         udelay(5);
656                         frame_val = tr32(MAC_MI_COM);
657                         break;
658                 }
659                 loops -= 1;
660         }
661
662         ret = -EBUSY;
663         if (loops != 0) {
664                 *val = frame_val & MI_COM_DATA_MASK;
665                 ret = 0;
666         }
667
668         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
669                 tw32_f(MAC_MI_MODE, tp->mi_mode);
670                 udelay(80);
671         }
672
673         return ret;
674 }
675
676 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
677 {
678         u32 frame_val;
679         unsigned int loops;
680         int ret;
681
682         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
683             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
684                 return 0;
685
686         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
687                 tw32_f(MAC_MI_MODE,
688                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
689                 udelay(80);
690         }
691
692         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
693                       MI_COM_PHY_ADDR_MASK);
694         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
695                       MI_COM_REG_ADDR_MASK);
696         frame_val |= (val & MI_COM_DATA_MASK);
697         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
698
699         tw32_f(MAC_MI_COM, frame_val);
700
701         loops = PHY_BUSY_LOOPS;
702         while (loops != 0) {
703                 udelay(10);
704                 frame_val = tr32(MAC_MI_COM);
705                 if ((frame_val & MI_COM_BUSY) == 0) {
706                         udelay(5);
707                         frame_val = tr32(MAC_MI_COM);
708                         break;
709                 }
710                 loops -= 1;
711         }
712
713         ret = -EBUSY;
714         if (loops != 0)
715                 ret = 0;
716
717         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
718                 tw32_f(MAC_MI_MODE, tp->mi_mode);
719                 udelay(80);
720         }
721
722         return ret;
723 }
724
725 static void tg3_phy_set_wirespeed(struct tg3 *tp)
726 {
727         u32 val;
728
729         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
730                 return;
731
732         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
733             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
734                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
735                              (val | (1 << 15) | (1 << 4)));
736 }
737
738 static int tg3_bmcr_reset(struct tg3 *tp)
739 {
740         u32 phy_control;
741         int limit, err;
742
743         /* OK, reset it, and poll the BMCR_RESET bit until it
744          * clears or we time out.
745          */
746         phy_control = BMCR_RESET;
747         err = tg3_writephy(tp, MII_BMCR, phy_control);
748         if (err != 0)
749                 return -EBUSY;
750
751         limit = 5000;
752         while (limit--) {
753                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
754                 if (err != 0)
755                         return -EBUSY;
756
757                 if ((phy_control & BMCR_RESET) == 0) {
758                         udelay(40);
759                         break;
760                 }
761                 udelay(10);
762         }
763         if (limit <= 0)
764                 return -EBUSY;
765
766         return 0;
767 }
768
769 static int tg3_wait_macro_done(struct tg3 *tp)
770 {
771         int limit = 100;
772
773         while (limit--) {
774                 u32 tmp32;
775
776                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
777                         if ((tmp32 & 0x1000) == 0)
778                                 break;
779                 }
780         }
781         if (limit <= 0)
782                 return -EBUSY;
783
784         return 0;
785 }
786
787 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
788 {
789         static const u32 test_pat[4][6] = {
790         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
791         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
792         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
793         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
794         };
795         int chan;
796
797         for (chan = 0; chan < 4; chan++) {
798                 int i;
799
800                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
801                              (chan * 0x2000) | 0x0200);
802                 tg3_writephy(tp, 0x16, 0x0002);
803
804                 for (i = 0; i < 6; i++)
805                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
806                                      test_pat[chan][i]);
807
808                 tg3_writephy(tp, 0x16, 0x0202);
809                 if (tg3_wait_macro_done(tp)) {
810                         *resetp = 1;
811                         return -EBUSY;
812                 }
813
814                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
815                              (chan * 0x2000) | 0x0200);
816                 tg3_writephy(tp, 0x16, 0x0082);
817                 if (tg3_wait_macro_done(tp)) {
818                         *resetp = 1;
819                         return -EBUSY;
820                 }
821
822                 tg3_writephy(tp, 0x16, 0x0802);
823                 if (tg3_wait_macro_done(tp)) {
824                         *resetp = 1;
825                         return -EBUSY;
826                 }
827
828                 for (i = 0; i < 6; i += 2) {
829                         u32 low, high;
830
831                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
832                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
833                             tg3_wait_macro_done(tp)) {
834                                 *resetp = 1;
835                                 return -EBUSY;
836                         }
837                         low &= 0x7fff;
838                         high &= 0x000f;
839                         if (low != test_pat[chan][i] ||
840                             high != test_pat[chan][i+1]) {
841                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
842                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
843                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
844
845                                 return -EBUSY;
846                         }
847                 }
848         }
849
850         return 0;
851 }
852
853 static int tg3_phy_reset_chanpat(struct tg3 *tp)
854 {
855         int chan;
856
857         for (chan = 0; chan < 4; chan++) {
858                 int i;
859
860                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
861                              (chan * 0x2000) | 0x0200);
862                 tg3_writephy(tp, 0x16, 0x0002);
863                 for (i = 0; i < 6; i++)
864                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
865                 tg3_writephy(tp, 0x16, 0x0202);
866                 if (tg3_wait_macro_done(tp))
867                         return -EBUSY;
868         }
869
870         return 0;
871 }
872
873 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
874 {
875         u32 reg32, phy9_orig;
876         int retries, do_phy_reset, err;
877
878         retries = 10;
879         do_phy_reset = 1;
880         do {
881                 if (do_phy_reset) {
882                         err = tg3_bmcr_reset(tp);
883                         if (err)
884                                 return err;
885                         do_phy_reset = 0;
886                 }
887
888                 /* Disable transmitter and interrupt.  */
889                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
890                         continue;
891
892                 reg32 |= 0x3000;
893                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
894
895                 /* Set full-duplex, 1000 mbps.  */
896                 tg3_writephy(tp, MII_BMCR,
897                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
898
899                 /* Set to master mode.  */
900                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
901                         continue;
902
903                 tg3_writephy(tp, MII_TG3_CTRL,
904                              (MII_TG3_CTRL_AS_MASTER |
905                               MII_TG3_CTRL_ENABLE_AS_MASTER));
906
907                 /* Enable SM_DSP_CLOCK and 6dB.  */
908                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
909
910                 /* Block the PHY control access.  */
911                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
912                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
913
914                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
915                 if (!err)
916                         break;
917         } while (--retries);
918
919         err = tg3_phy_reset_chanpat(tp);
920         if (err)
921                 return err;
922
923         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
924         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
925
926         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
927         tg3_writephy(tp, 0x16, 0x0000);
928
929         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
930             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
931                 /* Set Extended packet length bit for jumbo frames */
932                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
933         }
934         else {
935                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
936         }
937
938         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
939
940         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
941                 reg32 &= ~0x3000;
942                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
943         } else if (!err)
944                 err = -EBUSY;
945
946         return err;
947 }
948
949 static void tg3_link_report(struct tg3 *);
950
951 /* This will reset the tigon3 PHY if there is no valid
952  * link unless the FORCE argument is non-zero.
953  */
954 static int tg3_phy_reset(struct tg3 *tp)
955 {
956         u32 phy_status;
957         int err;
958
959         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
960                 u32 val;
961
962                 val = tr32(GRC_MISC_CFG);
963                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
964                 udelay(40);
965         }
966         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
967         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
968         if (err != 0)
969                 return -EBUSY;
970
971         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
972                 netif_carrier_off(tp->dev);
973                 tg3_link_report(tp);
974         }
975
976         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
977             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
978             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
979                 err = tg3_phy_reset_5703_4_5(tp);
980                 if (err)
981                         return err;
982                 goto out;
983         }
984
985         err = tg3_bmcr_reset(tp);
986         if (err)
987                 return err;
988
989 out:
990         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
991                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
992                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
993                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
994                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
995                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
996                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
997         }
998         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
999                 tg3_writephy(tp, 0x1c, 0x8d68);
1000                 tg3_writephy(tp, 0x1c, 0x8d68);
1001         }
1002         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1003                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1004                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1005                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1006                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1007                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1008                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1009                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1010                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1011         }
1012         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1013                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1014                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1015                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1016                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1017                         tg3_writephy(tp, MII_TG3_TEST1,
1018                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1019                 } else
1020                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1021                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1022         }
1023         /* Set Extended packet length bit (bit 14) on all chips that */
1024         /* support jumbo frames */
1025         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1026                 /* Cannot do read-modify-write on 5401 */
1027                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1028         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1029                 u32 phy_reg;
1030
1031                 /* Set bit 14 with read-modify-write to preserve other bits */
1032                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1033                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1034                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1035         }
1036
1037         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1038          * jumbo frames transmission.
1039          */
1040         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1041                 u32 phy_reg;
1042
1043                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1044                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1045                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1046         }
1047
1048         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1049                 u32 phy_reg;
1050
1051                 /* adjust output voltage */
1052                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1053
1054                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1055                         u32 phy_reg2;
1056
1057                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1058                                      phy_reg | MII_TG3_EPHY_SHADOW_EN);
1059                         /* Enable auto-MDIX */
1060                         if (!tg3_readphy(tp, 0x10, &phy_reg2))
1061                                 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1062                         tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1063                 }
1064         }
1065
1066         tg3_phy_set_wirespeed(tp);
1067         return 0;
1068 }
1069
1070 static void tg3_frob_aux_power(struct tg3 *tp)
1071 {
1072         struct tg3 *tp_peer = tp;
1073
1074         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1075                 return;
1076
1077         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1078             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1079                 struct net_device *dev_peer;
1080
1081                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1082                 /* remove_one() may have been run on the peer. */
1083                 if (!dev_peer)
1084                         tp_peer = tp;
1085                 else
1086                         tp_peer = netdev_priv(dev_peer);
1087         }
1088
1089         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1090             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1091             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1092             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1093                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1094                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1095                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1096                                     (GRC_LCLCTRL_GPIO_OE0 |
1097                                      GRC_LCLCTRL_GPIO_OE1 |
1098                                      GRC_LCLCTRL_GPIO_OE2 |
1099                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1100                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1101                                     100);
1102                 } else {
1103                         u32 no_gpio2;
1104                         u32 grc_local_ctrl = 0;
1105
1106                         if (tp_peer != tp &&
1107                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1108                                 return;
1109
1110                         /* Workaround to prevent overdrawing Amps. */
1111                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1112                             ASIC_REV_5714) {
1113                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1114                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1115                                             grc_local_ctrl, 100);
1116                         }
1117
1118                         /* On 5753 and variants, GPIO2 cannot be used. */
1119                         no_gpio2 = tp->nic_sram_data_cfg &
1120                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1121
1122                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1123                                          GRC_LCLCTRL_GPIO_OE1 |
1124                                          GRC_LCLCTRL_GPIO_OE2 |
1125                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1126                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1127                         if (no_gpio2) {
1128                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1129                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1130                         }
1131                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1132                                                     grc_local_ctrl, 100);
1133
1134                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1135
1136                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1137                                                     grc_local_ctrl, 100);
1138
1139                         if (!no_gpio2) {
1140                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1141                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1142                                             grc_local_ctrl, 100);
1143                         }
1144                 }
1145         } else {
1146                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1147                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1148                         if (tp_peer != tp &&
1149                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1150                                 return;
1151
1152                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1153                                     (GRC_LCLCTRL_GPIO_OE1 |
1154                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1155
1156                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1157                                     GRC_LCLCTRL_GPIO_OE1, 100);
1158
1159                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1160                                     (GRC_LCLCTRL_GPIO_OE1 |
1161                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1162                 }
1163         }
1164 }
1165
1166 static int tg3_setup_phy(struct tg3 *, int);
1167
1168 #define RESET_KIND_SHUTDOWN     0
1169 #define RESET_KIND_INIT         1
1170 #define RESET_KIND_SUSPEND      2
1171
1172 static void tg3_write_sig_post_reset(struct tg3 *, int);
1173 static int tg3_halt_cpu(struct tg3 *, u32);
1174 static int tg3_nvram_lock(struct tg3 *);
1175 static void tg3_nvram_unlock(struct tg3 *);
1176
1177 static void tg3_power_down_phy(struct tg3 *tp)
1178 {
1179         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1180                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1181                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1182                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1183
1184                         sg_dig_ctrl |=
1185                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1186                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1187                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1188                 }
1189                 return;
1190         }
1191
1192         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1193                 u32 val;
1194
1195                 tg3_bmcr_reset(tp);
1196                 val = tr32(GRC_MISC_CFG);
1197                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1198                 udelay(40);
1199                 return;
1200         } else {
1201                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1202                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1203                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1204         }
1205
1206         /* The PHY should not be powered down on some chips because
1207          * of bugs.
1208          */
1209         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1210             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1211             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1212              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1213                 return;
1214         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1215 }
1216
1217 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1218 {
1219         u32 misc_host_ctrl;
1220         u16 power_control, power_caps;
1221         int pm = tp->pm_cap;
1222
1223         /* Make sure register accesses (indirect or otherwise)
1224          * will function correctly.
1225          */
1226         pci_write_config_dword(tp->pdev,
1227                                TG3PCI_MISC_HOST_CTRL,
1228                                tp->misc_host_ctrl);
1229
1230         pci_read_config_word(tp->pdev,
1231                              pm + PCI_PM_CTRL,
1232                              &power_control);
1233         power_control |= PCI_PM_CTRL_PME_STATUS;
1234         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1235         switch (state) {
1236         case PCI_D0:
1237                 power_control |= 0;
1238                 pci_write_config_word(tp->pdev,
1239                                       pm + PCI_PM_CTRL,
1240                                       power_control);
1241                 udelay(100);    /* Delay after power state change */
1242
1243                 /* Switch out of Vaux if it is a NIC */
1244                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1245                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1246
1247                 return 0;
1248
1249         case PCI_D1:
1250                 power_control |= 1;
1251                 break;
1252
1253         case PCI_D2:
1254                 power_control |= 2;
1255                 break;
1256
1257         case PCI_D3hot:
1258                 power_control |= 3;
1259                 break;
1260
1261         default:
1262                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1263                        "requested.\n",
1264                        tp->dev->name, state);
1265                 return -EINVAL;
1266         };
1267
1268         power_control |= PCI_PM_CTRL_PME_ENABLE;
1269
1270         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1271         tw32(TG3PCI_MISC_HOST_CTRL,
1272              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1273
1274         if (tp->link_config.phy_is_low_power == 0) {
1275                 tp->link_config.phy_is_low_power = 1;
1276                 tp->link_config.orig_speed = tp->link_config.speed;
1277                 tp->link_config.orig_duplex = tp->link_config.duplex;
1278                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1279         }
1280
1281         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1282                 tp->link_config.speed = SPEED_10;
1283                 tp->link_config.duplex = DUPLEX_HALF;
1284                 tp->link_config.autoneg = AUTONEG_ENABLE;
1285                 tg3_setup_phy(tp, 0);
1286         }
1287
1288         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1289                 u32 val;
1290
1291                 val = tr32(GRC_VCPU_EXT_CTRL);
1292                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1293         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1294                 int i;
1295                 u32 val;
1296
1297                 for (i = 0; i < 200; i++) {
1298                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1299                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1300                                 break;
1301                         msleep(1);
1302                 }
1303         }
1304         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1305                                              WOL_DRV_STATE_SHUTDOWN |
1306                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1307
1308         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1309
1310         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1311                 u32 mac_mode;
1312
1313                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1314                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1315                         udelay(40);
1316
1317                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1318                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1319                         else
1320                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1321
1322                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1323                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1324                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1325                 } else {
1326                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1327                 }
1328
1329                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1330                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1331
1332                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1333                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1334                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1335
1336                 tw32_f(MAC_MODE, mac_mode);
1337                 udelay(100);
1338
1339                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1340                 udelay(10);
1341         }
1342
1343         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1344             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1345              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1346                 u32 base_val;
1347
1348                 base_val = tp->pci_clock_ctrl;
1349                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1350                              CLOCK_CTRL_TXCLK_DISABLE);
1351
1352                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1353                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1354         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1355                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1356                 /* do nothing */
1357         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1358                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1359                 u32 newbits1, newbits2;
1360
1361                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1362                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1363                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1364                                     CLOCK_CTRL_TXCLK_DISABLE |
1365                                     CLOCK_CTRL_ALTCLK);
1366                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1367                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1368                         newbits1 = CLOCK_CTRL_625_CORE;
1369                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1370                 } else {
1371                         newbits1 = CLOCK_CTRL_ALTCLK;
1372                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1373                 }
1374
1375                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1376                             40);
1377
1378                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1379                             40);
1380
1381                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1382                         u32 newbits3;
1383
1384                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1385                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1386                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1387                                             CLOCK_CTRL_TXCLK_DISABLE |
1388                                             CLOCK_CTRL_44MHZ_CORE);
1389                         } else {
1390                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1391                         }
1392
1393                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1394                                     tp->pci_clock_ctrl | newbits3, 40);
1395                 }
1396         }
1397
1398         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1399             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1400                 tg3_power_down_phy(tp);
1401
1402         tg3_frob_aux_power(tp);
1403
1404         /* Workaround for unstable PLL clock */
1405         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1406             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1407                 u32 val = tr32(0x7d00);
1408
1409                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1410                 tw32(0x7d00, val);
1411                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1412                         int err;
1413
1414                         err = tg3_nvram_lock(tp);
1415                         tg3_halt_cpu(tp, RX_CPU_BASE);
1416                         if (!err)
1417                                 tg3_nvram_unlock(tp);
1418                 }
1419         }
1420
1421         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1422
1423         /* Finally, set the new power state. */
1424         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1425         udelay(100);    /* Delay after power state change */
1426
1427         return 0;
1428 }
1429
1430 static void tg3_link_report(struct tg3 *tp)
1431 {
1432         if (!netif_carrier_ok(tp->dev)) {
1433                 if (netif_msg_link(tp))
1434                         printk(KERN_INFO PFX "%s: Link is down.\n",
1435                                tp->dev->name);
1436         } else if (netif_msg_link(tp)) {
1437                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1438                        tp->dev->name,
1439                        (tp->link_config.active_speed == SPEED_1000 ?
1440                         1000 :
1441                         (tp->link_config.active_speed == SPEED_100 ?
1442                          100 : 10)),
1443                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1444                         "full" : "half"));
1445
1446                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1447                        "%s for RX.\n",
1448                        tp->dev->name,
1449                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1450                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1451         }
1452 }
1453
1454 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1455 {
1456         u32 new_tg3_flags = 0;
1457         u32 old_rx_mode = tp->rx_mode;
1458         u32 old_tx_mode = tp->tx_mode;
1459
1460         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1461
1462                 /* Convert 1000BaseX flow control bits to 1000BaseT
1463                  * bits before resolving flow control.
1464                  */
1465                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1466                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1467                                        ADVERTISE_PAUSE_ASYM);
1468                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1469
1470                         if (local_adv & ADVERTISE_1000XPAUSE)
1471                                 local_adv |= ADVERTISE_PAUSE_CAP;
1472                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1473                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1474                         if (remote_adv & LPA_1000XPAUSE)
1475                                 remote_adv |= LPA_PAUSE_CAP;
1476                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1477                                 remote_adv |= LPA_PAUSE_ASYM;
1478                 }
1479
1480                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1481                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1482                                 if (remote_adv & LPA_PAUSE_CAP)
1483                                         new_tg3_flags |=
1484                                                 (TG3_FLAG_RX_PAUSE |
1485                                                 TG3_FLAG_TX_PAUSE);
1486                                 else if (remote_adv & LPA_PAUSE_ASYM)
1487                                         new_tg3_flags |=
1488                                                 (TG3_FLAG_RX_PAUSE);
1489                         } else {
1490                                 if (remote_adv & LPA_PAUSE_CAP)
1491                                         new_tg3_flags |=
1492                                                 (TG3_FLAG_RX_PAUSE |
1493                                                 TG3_FLAG_TX_PAUSE);
1494                         }
1495                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1496                         if ((remote_adv & LPA_PAUSE_CAP) &&
1497                         (remote_adv & LPA_PAUSE_ASYM))
1498                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1499                 }
1500
1501                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1502                 tp->tg3_flags |= new_tg3_flags;
1503         } else {
1504                 new_tg3_flags = tp->tg3_flags;
1505         }
1506
1507         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1508                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1509         else
1510                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1511
1512         if (old_rx_mode != tp->rx_mode) {
1513                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1514         }
1515
1516         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1517                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1518         else
1519                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1520
1521         if (old_tx_mode != tp->tx_mode) {
1522                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1523         }
1524 }
1525
1526 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1527 {
1528         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1529         case MII_TG3_AUX_STAT_10HALF:
1530                 *speed = SPEED_10;
1531                 *duplex = DUPLEX_HALF;
1532                 break;
1533
1534         case MII_TG3_AUX_STAT_10FULL:
1535                 *speed = SPEED_10;
1536                 *duplex = DUPLEX_FULL;
1537                 break;
1538
1539         case MII_TG3_AUX_STAT_100HALF:
1540                 *speed = SPEED_100;
1541                 *duplex = DUPLEX_HALF;
1542                 break;
1543
1544         case MII_TG3_AUX_STAT_100FULL:
1545                 *speed = SPEED_100;
1546                 *duplex = DUPLEX_FULL;
1547                 break;
1548
1549         case MII_TG3_AUX_STAT_1000HALF:
1550                 *speed = SPEED_1000;
1551                 *duplex = DUPLEX_HALF;
1552                 break;
1553
1554         case MII_TG3_AUX_STAT_1000FULL:
1555                 *speed = SPEED_1000;
1556                 *duplex = DUPLEX_FULL;
1557                 break;
1558
1559         default:
1560                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1561                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1562                                  SPEED_10;
1563                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1564                                   DUPLEX_HALF;
1565                         break;
1566                 }
1567                 *speed = SPEED_INVALID;
1568                 *duplex = DUPLEX_INVALID;
1569                 break;
1570         };
1571 }
1572
1573 static void tg3_phy_copper_begin(struct tg3 *tp)
1574 {
1575         u32 new_adv;
1576         int i;
1577
1578         if (tp->link_config.phy_is_low_power) {
1579                 /* Entering low power mode.  Disable gigabit and
1580                  * 100baseT advertisements.
1581                  */
1582                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1583
1584                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1585                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1586                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1587                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1588
1589                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1590         } else if (tp->link_config.speed == SPEED_INVALID) {
1591                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1592                         tp->link_config.advertising &=
1593                                 ~(ADVERTISED_1000baseT_Half |
1594                                   ADVERTISED_1000baseT_Full);
1595
1596                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1597                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1598                         new_adv |= ADVERTISE_10HALF;
1599                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1600                         new_adv |= ADVERTISE_10FULL;
1601                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1602                         new_adv |= ADVERTISE_100HALF;
1603                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1604                         new_adv |= ADVERTISE_100FULL;
1605                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1606
1607                 if (tp->link_config.advertising &
1608                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1609                         new_adv = 0;
1610                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1611                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1612                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1613                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1614                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1615                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1616                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1617                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1618                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1619                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1620                 } else {
1621                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1622                 }
1623         } else {
1624                 /* Asking for a specific link mode. */
1625                 if (tp->link_config.speed == SPEED_1000) {
1626                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1627                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1628
1629                         if (tp->link_config.duplex == DUPLEX_FULL)
1630                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1631                         else
1632                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1633                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1634                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1635                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1636                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1637                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1638                 } else {
1639                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1640
1641                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1642                         if (tp->link_config.speed == SPEED_100) {
1643                                 if (tp->link_config.duplex == DUPLEX_FULL)
1644                                         new_adv |= ADVERTISE_100FULL;
1645                                 else
1646                                         new_adv |= ADVERTISE_100HALF;
1647                         } else {
1648                                 if (tp->link_config.duplex == DUPLEX_FULL)
1649                                         new_adv |= ADVERTISE_10FULL;
1650                                 else
1651                                         new_adv |= ADVERTISE_10HALF;
1652                         }
1653                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1654                 }
1655         }
1656
1657         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1658             tp->link_config.speed != SPEED_INVALID) {
1659                 u32 bmcr, orig_bmcr;
1660
1661                 tp->link_config.active_speed = tp->link_config.speed;
1662                 tp->link_config.active_duplex = tp->link_config.duplex;
1663
1664                 bmcr = 0;
1665                 switch (tp->link_config.speed) {
1666                 default:
1667                 case SPEED_10:
1668                         break;
1669
1670                 case SPEED_100:
1671                         bmcr |= BMCR_SPEED100;
1672                         break;
1673
1674                 case SPEED_1000:
1675                         bmcr |= TG3_BMCR_SPEED1000;
1676                         break;
1677                 };
1678
1679                 if (tp->link_config.duplex == DUPLEX_FULL)
1680                         bmcr |= BMCR_FULLDPLX;
1681
1682                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1683                     (bmcr != orig_bmcr)) {
1684                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1685                         for (i = 0; i < 1500; i++) {
1686                                 u32 tmp;
1687
1688                                 udelay(10);
1689                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1690                                     tg3_readphy(tp, MII_BMSR, &tmp))
1691                                         continue;
1692                                 if (!(tmp & BMSR_LSTATUS)) {
1693                                         udelay(40);
1694                                         break;
1695                                 }
1696                         }
1697                         tg3_writephy(tp, MII_BMCR, bmcr);
1698                         udelay(40);
1699                 }
1700         } else {
1701                 tg3_writephy(tp, MII_BMCR,
1702                              BMCR_ANENABLE | BMCR_ANRESTART);
1703         }
1704 }
1705
1706 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1707 {
1708         int err;
1709
1710         /* Turn off tap power management. */
1711         /* Set Extended packet length bit */
1712         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1713
1714         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1715         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1716
1717         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1718         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1719
1720         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1721         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1722
1723         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1724         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1725
1726         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1727         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1728
1729         udelay(40);
1730
1731         return err;
1732 }
1733
1734 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1735 {
1736         u32 adv_reg, all_mask = 0;
1737
1738         if (mask & ADVERTISED_10baseT_Half)
1739                 all_mask |= ADVERTISE_10HALF;
1740         if (mask & ADVERTISED_10baseT_Full)
1741                 all_mask |= ADVERTISE_10FULL;
1742         if (mask & ADVERTISED_100baseT_Half)
1743                 all_mask |= ADVERTISE_100HALF;
1744         if (mask & ADVERTISED_100baseT_Full)
1745                 all_mask |= ADVERTISE_100FULL;
1746
1747         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1748                 return 0;
1749
1750         if ((adv_reg & all_mask) != all_mask)
1751                 return 0;
1752         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1753                 u32 tg3_ctrl;
1754
1755                 all_mask = 0;
1756                 if (mask & ADVERTISED_1000baseT_Half)
1757                         all_mask |= ADVERTISE_1000HALF;
1758                 if (mask & ADVERTISED_1000baseT_Full)
1759                         all_mask |= ADVERTISE_1000FULL;
1760
1761                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1762                         return 0;
1763
1764                 if ((tg3_ctrl & all_mask) != all_mask)
1765                         return 0;
1766         }
1767         return 1;
1768 }
1769
1770 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1771 {
1772         int current_link_up;
1773         u32 bmsr, dummy;
1774         u16 current_speed;
1775         u8 current_duplex;
1776         int i, err;
1777
1778         tw32(MAC_EVENT, 0);
1779
1780         tw32_f(MAC_STATUS,
1781              (MAC_STATUS_SYNC_CHANGED |
1782               MAC_STATUS_CFG_CHANGED |
1783               MAC_STATUS_MI_COMPLETION |
1784               MAC_STATUS_LNKSTATE_CHANGED));
1785         udelay(40);
1786
1787         tp->mi_mode = MAC_MI_MODE_BASE;
1788         tw32_f(MAC_MI_MODE, tp->mi_mode);
1789         udelay(80);
1790
1791         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1792
1793         /* Some third-party PHYs need to be reset on link going
1794          * down.
1795          */
1796         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1797              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1798              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1799             netif_carrier_ok(tp->dev)) {
1800                 tg3_readphy(tp, MII_BMSR, &bmsr);
1801                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1802                     !(bmsr & BMSR_LSTATUS))
1803                         force_reset = 1;
1804         }
1805         if (force_reset)
1806                 tg3_phy_reset(tp);
1807
1808         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1809                 tg3_readphy(tp, MII_BMSR, &bmsr);
1810                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1811                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1812                         bmsr = 0;
1813
1814                 if (!(bmsr & BMSR_LSTATUS)) {
1815                         err = tg3_init_5401phy_dsp(tp);
1816                         if (err)
1817                                 return err;
1818
1819                         tg3_readphy(tp, MII_BMSR, &bmsr);
1820                         for (i = 0; i < 1000; i++) {
1821                                 udelay(10);
1822                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1823                                     (bmsr & BMSR_LSTATUS)) {
1824                                         udelay(40);
1825                                         break;
1826                                 }
1827                         }
1828
1829                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1830                             !(bmsr & BMSR_LSTATUS) &&
1831                             tp->link_config.active_speed == SPEED_1000) {
1832                                 err = tg3_phy_reset(tp);
1833                                 if (!err)
1834                                         err = tg3_init_5401phy_dsp(tp);
1835                                 if (err)
1836                                         return err;
1837                         }
1838                 }
1839         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1840                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1841                 /* 5701 {A0,B0} CRC bug workaround */
1842                 tg3_writephy(tp, 0x15, 0x0a75);
1843                 tg3_writephy(tp, 0x1c, 0x8c68);
1844                 tg3_writephy(tp, 0x1c, 0x8d68);
1845                 tg3_writephy(tp, 0x1c, 0x8c68);
1846         }
1847
1848         /* Clear pending interrupts... */
1849         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1850         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1851
1852         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1853                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1854         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1855                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1856
1857         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1858             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1859                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1860                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1861                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1862                 else
1863                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1864         }
1865
1866         current_link_up = 0;
1867         current_speed = SPEED_INVALID;
1868         current_duplex = DUPLEX_INVALID;
1869
1870         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1871                 u32 val;
1872
1873                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1874                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1875                 if (!(val & (1 << 10))) {
1876                         val |= (1 << 10);
1877                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1878                         goto relink;
1879                 }
1880         }
1881
1882         bmsr = 0;
1883         for (i = 0; i < 100; i++) {
1884                 tg3_readphy(tp, MII_BMSR, &bmsr);
1885                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1886                     (bmsr & BMSR_LSTATUS))
1887                         break;
1888                 udelay(40);
1889         }
1890
1891         if (bmsr & BMSR_LSTATUS) {
1892                 u32 aux_stat, bmcr;
1893
1894                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1895                 for (i = 0; i < 2000; i++) {
1896                         udelay(10);
1897                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1898                             aux_stat)
1899                                 break;
1900                 }
1901
1902                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1903                                              &current_speed,
1904                                              &current_duplex);
1905
1906                 bmcr = 0;
1907                 for (i = 0; i < 200; i++) {
1908                         tg3_readphy(tp, MII_BMCR, &bmcr);
1909                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1910                                 continue;
1911                         if (bmcr && bmcr != 0x7fff)
1912                                 break;
1913                         udelay(10);
1914                 }
1915
1916                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1917                         if (bmcr & BMCR_ANENABLE) {
1918                                 current_link_up = 1;
1919
1920                                 /* Force autoneg restart if we are exiting
1921                                  * low power mode.
1922                                  */
1923                                 if (!tg3_copper_is_advertising_all(tp,
1924                                                 tp->link_config.advertising))
1925                                         current_link_up = 0;
1926                         } else {
1927                                 current_link_up = 0;
1928                         }
1929                 } else {
1930                         if (!(bmcr & BMCR_ANENABLE) &&
1931                             tp->link_config.speed == current_speed &&
1932                             tp->link_config.duplex == current_duplex) {
1933                                 current_link_up = 1;
1934                         } else {
1935                                 current_link_up = 0;
1936                         }
1937                 }
1938
1939                 tp->link_config.active_speed = current_speed;
1940                 tp->link_config.active_duplex = current_duplex;
1941         }
1942
1943         if (current_link_up == 1 &&
1944             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1945             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1946                 u32 local_adv, remote_adv;
1947
1948                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1949                         local_adv = 0;
1950                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1951
1952                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1953                         remote_adv = 0;
1954
1955                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1956
1957                 /* If we are not advertising full pause capability,
1958                  * something is wrong.  Bring the link down and reconfigure.
1959                  */
1960                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1961                         current_link_up = 0;
1962                 } else {
1963                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1964                 }
1965         }
1966 relink:
1967         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1968                 u32 tmp;
1969
1970                 tg3_phy_copper_begin(tp);
1971
1972                 tg3_readphy(tp, MII_BMSR, &tmp);
1973                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1974                     (tmp & BMSR_LSTATUS))
1975                         current_link_up = 1;
1976         }
1977
1978         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1979         if (current_link_up == 1) {
1980                 if (tp->link_config.active_speed == SPEED_100 ||
1981                     tp->link_config.active_speed == SPEED_10)
1982                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1983                 else
1984                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1985         } else
1986                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1987
1988         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1989         if (tp->link_config.active_duplex == DUPLEX_HALF)
1990                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1991
1992         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1993         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1994                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1995                     (current_link_up == 1 &&
1996                      tp->link_config.active_speed == SPEED_10))
1997                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1998         } else {
1999                 if (current_link_up == 1)
2000                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2001         }
2002
2003         /* ??? Without this setting Netgear GA302T PHY does not
2004          * ??? send/receive packets...
2005          */
2006         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2007             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2008                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2009                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2010                 udelay(80);
2011         }
2012
2013         tw32_f(MAC_MODE, tp->mac_mode);
2014         udelay(40);
2015
2016         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2017                 /* Polled via timer. */
2018                 tw32_f(MAC_EVENT, 0);
2019         } else {
2020                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2021         }
2022         udelay(40);
2023
2024         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2025             current_link_up == 1 &&
2026             tp->link_config.active_speed == SPEED_1000 &&
2027             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2028              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2029                 udelay(120);
2030                 tw32_f(MAC_STATUS,
2031                      (MAC_STATUS_SYNC_CHANGED |
2032                       MAC_STATUS_CFG_CHANGED));
2033                 udelay(40);
2034                 tg3_write_mem(tp,
2035                               NIC_SRAM_FIRMWARE_MBOX,
2036                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2037         }
2038
2039         if (current_link_up != netif_carrier_ok(tp->dev)) {
2040                 if (current_link_up)
2041                         netif_carrier_on(tp->dev);
2042                 else
2043                         netif_carrier_off(tp->dev);
2044                 tg3_link_report(tp);
2045         }
2046
2047         return 0;
2048 }
2049
2050 struct tg3_fiber_aneginfo {
2051         int state;
2052 #define ANEG_STATE_UNKNOWN              0
2053 #define ANEG_STATE_AN_ENABLE            1
2054 #define ANEG_STATE_RESTART_INIT         2
2055 #define ANEG_STATE_RESTART              3
2056 #define ANEG_STATE_DISABLE_LINK_OK      4
2057 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2058 #define ANEG_STATE_ABILITY_DETECT       6
2059 #define ANEG_STATE_ACK_DETECT_INIT      7
2060 #define ANEG_STATE_ACK_DETECT           8
2061 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2062 #define ANEG_STATE_COMPLETE_ACK         10
2063 #define ANEG_STATE_IDLE_DETECT_INIT     11
2064 #define ANEG_STATE_IDLE_DETECT          12
2065 #define ANEG_STATE_LINK_OK              13
2066 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2067 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2068
2069         u32 flags;
2070 #define MR_AN_ENABLE            0x00000001
2071 #define MR_RESTART_AN           0x00000002
2072 #define MR_AN_COMPLETE          0x00000004
2073 #define MR_PAGE_RX              0x00000008
2074 #define MR_NP_LOADED            0x00000010
2075 #define MR_TOGGLE_TX            0x00000020
2076 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2077 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2078 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2079 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2080 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2081 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2082 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2083 #define MR_TOGGLE_RX            0x00002000
2084 #define MR_NP_RX                0x00004000
2085
2086 #define MR_LINK_OK              0x80000000
2087
2088         unsigned long link_time, cur_time;
2089
2090         u32 ability_match_cfg;
2091         int ability_match_count;
2092
2093         char ability_match, idle_match, ack_match;
2094
2095         u32 txconfig, rxconfig;
2096 #define ANEG_CFG_NP             0x00000080
2097 #define ANEG_CFG_ACK            0x00000040
2098 #define ANEG_CFG_RF2            0x00000020
2099 #define ANEG_CFG_RF1            0x00000010
2100 #define ANEG_CFG_PS2            0x00000001
2101 #define ANEG_CFG_PS1            0x00008000
2102 #define ANEG_CFG_HD             0x00004000
2103 #define ANEG_CFG_FD             0x00002000
2104 #define ANEG_CFG_INVAL          0x00001f06
2105
2106 };
2107 #define ANEG_OK         0
2108 #define ANEG_DONE       1
2109 #define ANEG_TIMER_ENAB 2
2110 #define ANEG_FAILED     -1
2111
2112 #define ANEG_STATE_SETTLE_TIME  10000
2113
2114 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2115                                    struct tg3_fiber_aneginfo *ap)
2116 {
2117         unsigned long delta;
2118         u32 rx_cfg_reg;
2119         int ret;
2120
2121         if (ap->state == ANEG_STATE_UNKNOWN) {
2122                 ap->rxconfig = 0;
2123                 ap->link_time = 0;
2124                 ap->cur_time = 0;
2125                 ap->ability_match_cfg = 0;
2126                 ap->ability_match_count = 0;
2127                 ap->ability_match = 0;
2128                 ap->idle_match = 0;
2129                 ap->ack_match = 0;
2130         }
2131         ap->cur_time++;
2132
2133         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2134                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2135
2136                 if (rx_cfg_reg != ap->ability_match_cfg) {
2137                         ap->ability_match_cfg = rx_cfg_reg;
2138                         ap->ability_match = 0;
2139                         ap->ability_match_count = 0;
2140                 } else {
2141                         if (++ap->ability_match_count > 1) {
2142                                 ap->ability_match = 1;
2143                                 ap->ability_match_cfg = rx_cfg_reg;
2144                         }
2145                 }
2146                 if (rx_cfg_reg & ANEG_CFG_ACK)
2147                         ap->ack_match = 1;
2148                 else
2149                         ap->ack_match = 0;
2150
2151                 ap->idle_match = 0;
2152         } else {
2153                 ap->idle_match = 1;
2154                 ap->ability_match_cfg = 0;
2155                 ap->ability_match_count = 0;
2156                 ap->ability_match = 0;
2157                 ap->ack_match = 0;
2158
2159                 rx_cfg_reg = 0;
2160         }
2161
2162         ap->rxconfig = rx_cfg_reg;
2163         ret = ANEG_OK;
2164
2165         switch(ap->state) {
2166         case ANEG_STATE_UNKNOWN:
2167                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2168                         ap->state = ANEG_STATE_AN_ENABLE;
2169
2170                 /* fallthru */
2171         case ANEG_STATE_AN_ENABLE:
2172                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2173                 if (ap->flags & MR_AN_ENABLE) {
2174                         ap->link_time = 0;
2175                         ap->cur_time = 0;
2176                         ap->ability_match_cfg = 0;
2177                         ap->ability_match_count = 0;
2178                         ap->ability_match = 0;
2179                         ap->idle_match = 0;
2180                         ap->ack_match = 0;
2181
2182                         ap->state = ANEG_STATE_RESTART_INIT;
2183                 } else {
2184                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2185                 }
2186                 break;
2187
2188         case ANEG_STATE_RESTART_INIT:
2189                 ap->link_time = ap->cur_time;
2190                 ap->flags &= ~(MR_NP_LOADED);
2191                 ap->txconfig = 0;
2192                 tw32(MAC_TX_AUTO_NEG, 0);
2193                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2194                 tw32_f(MAC_MODE, tp->mac_mode);
2195                 udelay(40);
2196
2197                 ret = ANEG_TIMER_ENAB;
2198                 ap->state = ANEG_STATE_RESTART;
2199
2200                 /* fallthru */
2201         case ANEG_STATE_RESTART:
2202                 delta = ap->cur_time - ap->link_time;
2203                 if (delta > ANEG_STATE_SETTLE_TIME) {
2204                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2205                 } else {
2206                         ret = ANEG_TIMER_ENAB;
2207                 }
2208                 break;
2209
2210         case ANEG_STATE_DISABLE_LINK_OK:
2211                 ret = ANEG_DONE;
2212                 break;
2213
2214         case ANEG_STATE_ABILITY_DETECT_INIT:
2215                 ap->flags &= ~(MR_TOGGLE_TX);
2216                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2217                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2218                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2219                 tw32_f(MAC_MODE, tp->mac_mode);
2220                 udelay(40);
2221
2222                 ap->state = ANEG_STATE_ABILITY_DETECT;
2223                 break;
2224
2225         case ANEG_STATE_ABILITY_DETECT:
2226                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2227                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2228                 }
2229                 break;
2230
2231         case ANEG_STATE_ACK_DETECT_INIT:
2232                 ap->txconfig |= ANEG_CFG_ACK;
2233                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2234                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2235                 tw32_f(MAC_MODE, tp->mac_mode);
2236                 udelay(40);
2237
2238                 ap->state = ANEG_STATE_ACK_DETECT;
2239
2240                 /* fallthru */
2241         case ANEG_STATE_ACK_DETECT:
2242                 if (ap->ack_match != 0) {
2243                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2244                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2245                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2246                         } else {
2247                                 ap->state = ANEG_STATE_AN_ENABLE;
2248                         }
2249                 } else if (ap->ability_match != 0 &&
2250                            ap->rxconfig == 0) {
2251                         ap->state = ANEG_STATE_AN_ENABLE;
2252                 }
2253                 break;
2254
2255         case ANEG_STATE_COMPLETE_ACK_INIT:
2256                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2257                         ret = ANEG_FAILED;
2258                         break;
2259                 }
2260                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2261                                MR_LP_ADV_HALF_DUPLEX |
2262                                MR_LP_ADV_SYM_PAUSE |
2263                                MR_LP_ADV_ASYM_PAUSE |
2264                                MR_LP_ADV_REMOTE_FAULT1 |
2265                                MR_LP_ADV_REMOTE_FAULT2 |
2266                                MR_LP_ADV_NEXT_PAGE |
2267                                MR_TOGGLE_RX |
2268                                MR_NP_RX);
2269                 if (ap->rxconfig & ANEG_CFG_FD)
2270                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2271                 if (ap->rxconfig & ANEG_CFG_HD)
2272                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2273                 if (ap->rxconfig & ANEG_CFG_PS1)
2274                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2275                 if (ap->rxconfig & ANEG_CFG_PS2)
2276                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2277                 if (ap->rxconfig & ANEG_CFG_RF1)
2278                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2279                 if (ap->rxconfig & ANEG_CFG_RF2)
2280                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2281                 if (ap->rxconfig & ANEG_CFG_NP)
2282                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2283
2284                 ap->link_time = ap->cur_time;
2285
2286                 ap->flags ^= (MR_TOGGLE_TX);
2287                 if (ap->rxconfig & 0x0008)
2288                         ap->flags |= MR_TOGGLE_RX;
2289                 if (ap->rxconfig & ANEG_CFG_NP)
2290                         ap->flags |= MR_NP_RX;
2291                 ap->flags |= MR_PAGE_RX;
2292
2293                 ap->state = ANEG_STATE_COMPLETE_ACK;
2294                 ret = ANEG_TIMER_ENAB;
2295                 break;
2296
2297         case ANEG_STATE_COMPLETE_ACK:
2298                 if (ap->ability_match != 0 &&
2299                     ap->rxconfig == 0) {
2300                         ap->state = ANEG_STATE_AN_ENABLE;
2301                         break;
2302                 }
2303                 delta = ap->cur_time - ap->link_time;
2304                 if (delta > ANEG_STATE_SETTLE_TIME) {
2305                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2306                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2307                         } else {
2308                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2309                                     !(ap->flags & MR_NP_RX)) {
2310                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2311                                 } else {
2312                                         ret = ANEG_FAILED;
2313                                 }
2314                         }
2315                 }
2316                 break;
2317
2318         case ANEG_STATE_IDLE_DETECT_INIT:
2319                 ap->link_time = ap->cur_time;
2320                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2321                 tw32_f(MAC_MODE, tp->mac_mode);
2322                 udelay(40);
2323
2324                 ap->state = ANEG_STATE_IDLE_DETECT;
2325                 ret = ANEG_TIMER_ENAB;
2326                 break;
2327
2328         case ANEG_STATE_IDLE_DETECT:
2329                 if (ap->ability_match != 0 &&
2330                     ap->rxconfig == 0) {
2331                         ap->state = ANEG_STATE_AN_ENABLE;
2332                         break;
2333                 }
2334                 delta = ap->cur_time - ap->link_time;
2335                 if (delta > ANEG_STATE_SETTLE_TIME) {
2336                         /* XXX another gem from the Broadcom driver :( */
2337                         ap->state = ANEG_STATE_LINK_OK;
2338                 }
2339                 break;
2340
2341         case ANEG_STATE_LINK_OK:
2342                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2343                 ret = ANEG_DONE;
2344                 break;
2345
2346         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2347                 /* ??? unimplemented */
2348                 break;
2349
2350         case ANEG_STATE_NEXT_PAGE_WAIT:
2351                 /* ??? unimplemented */
2352                 break;
2353
2354         default:
2355                 ret = ANEG_FAILED;
2356                 break;
2357         };
2358
2359         return ret;
2360 }
2361
2362 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2363 {
2364         int res = 0;
2365         struct tg3_fiber_aneginfo aninfo;
2366         int status = ANEG_FAILED;
2367         unsigned int tick;
2368         u32 tmp;
2369
2370         tw32_f(MAC_TX_AUTO_NEG, 0);
2371
2372         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2373         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2374         udelay(40);
2375
2376         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2377         udelay(40);
2378
2379         memset(&aninfo, 0, sizeof(aninfo));
2380         aninfo.flags |= MR_AN_ENABLE;
2381         aninfo.state = ANEG_STATE_UNKNOWN;
2382         aninfo.cur_time = 0;
2383         tick = 0;
2384         while (++tick < 195000) {
2385                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2386                 if (status == ANEG_DONE || status == ANEG_FAILED)
2387                         break;
2388
2389                 udelay(1);
2390         }
2391
2392         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2393         tw32_f(MAC_MODE, tp->mac_mode);
2394         udelay(40);
2395
2396         *flags = aninfo.flags;
2397
2398         if (status == ANEG_DONE &&
2399             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2400                              MR_LP_ADV_FULL_DUPLEX)))
2401                 res = 1;
2402
2403         return res;
2404 }
2405
2406 static void tg3_init_bcm8002(struct tg3 *tp)
2407 {
2408         u32 mac_status = tr32(MAC_STATUS);
2409         int i;
2410
2411         /* Reset when initting first time or we have a link. */
2412         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2413             !(mac_status & MAC_STATUS_PCS_SYNCED))
2414                 return;
2415
2416         /* Set PLL lock range. */
2417         tg3_writephy(tp, 0x16, 0x8007);
2418
2419         /* SW reset */
2420         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2421
2422         /* Wait for reset to complete. */
2423         /* XXX schedule_timeout() ... */
2424         for (i = 0; i < 500; i++)
2425                 udelay(10);
2426
2427         /* Config mode; select PMA/Ch 1 regs. */
2428         tg3_writephy(tp, 0x10, 0x8411);
2429
2430         /* Enable auto-lock and comdet, select txclk for tx. */
2431         tg3_writephy(tp, 0x11, 0x0a10);
2432
2433         tg3_writephy(tp, 0x18, 0x00a0);
2434         tg3_writephy(tp, 0x16, 0x41ff);
2435
2436         /* Assert and deassert POR. */
2437         tg3_writephy(tp, 0x13, 0x0400);
2438         udelay(40);
2439         tg3_writephy(tp, 0x13, 0x0000);
2440
2441         tg3_writephy(tp, 0x11, 0x0a50);
2442         udelay(40);
2443         tg3_writephy(tp, 0x11, 0x0a10);
2444
2445         /* Wait for signal to stabilize */
2446         /* XXX schedule_timeout() ... */
2447         for (i = 0; i < 15000; i++)
2448                 udelay(10);
2449
2450         /* Deselect the channel register so we can read the PHYID
2451          * later.
2452          */
2453         tg3_writephy(tp, 0x10, 0x8011);
2454 }
2455
2456 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2457 {
2458         u32 sg_dig_ctrl, sg_dig_status;
2459         u32 serdes_cfg, expected_sg_dig_ctrl;
2460         int workaround, port_a;
2461         int current_link_up;
2462
2463         serdes_cfg = 0;
2464         expected_sg_dig_ctrl = 0;
2465         workaround = 0;
2466         port_a = 1;
2467         current_link_up = 0;
2468
2469         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2470             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2471                 workaround = 1;
2472                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2473                         port_a = 0;
2474
2475                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2476                 /* preserve bits 20-23 for voltage regulator */
2477                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2478         }
2479
2480         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2481
2482         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2483                 if (sg_dig_ctrl & (1 << 31)) {
2484                         if (workaround) {
2485                                 u32 val = serdes_cfg;
2486
2487                                 if (port_a)
2488                                         val |= 0xc010000;
2489                                 else
2490                                         val |= 0x4010000;
2491                                 tw32_f(MAC_SERDES_CFG, val);
2492                         }
2493                         tw32_f(SG_DIG_CTRL, 0x01388400);
2494                 }
2495                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2496                         tg3_setup_flow_control(tp, 0, 0);
2497                         current_link_up = 1;
2498                 }
2499                 goto out;
2500         }
2501
2502         /* Want auto-negotiation.  */
2503         expected_sg_dig_ctrl = 0x81388400;
2504
2505         /* Pause capability */
2506         expected_sg_dig_ctrl |= (1 << 11);
2507
2508         /* Asymettric pause */
2509         expected_sg_dig_ctrl |= (1 << 12);
2510
2511         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2512                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2513                     tp->serdes_counter &&
2514                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2515                                     MAC_STATUS_RCVD_CFG)) ==
2516                      MAC_STATUS_PCS_SYNCED)) {
2517                         tp->serdes_counter--;
2518                         current_link_up = 1;
2519                         goto out;
2520                 }
2521 restart_autoneg:
2522                 if (workaround)
2523                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2524                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2525                 udelay(5);
2526                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2527
2528                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2529                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2530         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2531                                  MAC_STATUS_SIGNAL_DET)) {
2532                 sg_dig_status = tr32(SG_DIG_STATUS);
2533                 mac_status = tr32(MAC_STATUS);
2534
2535                 if ((sg_dig_status & (1 << 1)) &&
2536                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2537                         u32 local_adv, remote_adv;
2538
2539                         local_adv = ADVERTISE_PAUSE_CAP;
2540                         remote_adv = 0;
2541                         if (sg_dig_status & (1 << 19))
2542                                 remote_adv |= LPA_PAUSE_CAP;
2543                         if (sg_dig_status & (1 << 20))
2544                                 remote_adv |= LPA_PAUSE_ASYM;
2545
2546                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2547                         current_link_up = 1;
2548                         tp->serdes_counter = 0;
2549                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2550                 } else if (!(sg_dig_status & (1 << 1))) {
2551                         if (tp->serdes_counter)
2552                                 tp->serdes_counter--;
2553                         else {
2554                                 if (workaround) {
2555                                         u32 val = serdes_cfg;
2556
2557                                         if (port_a)
2558                                                 val |= 0xc010000;
2559                                         else
2560                                                 val |= 0x4010000;
2561
2562                                         tw32_f(MAC_SERDES_CFG, val);
2563                                 }
2564
2565                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2566                                 udelay(40);
2567
2568                                 /* Link parallel detection - link is up */
2569                                 /* only if we have PCS_SYNC and not */
2570                                 /* receiving config code words */
2571                                 mac_status = tr32(MAC_STATUS);
2572                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2573                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2574                                         tg3_setup_flow_control(tp, 0, 0);
2575                                         current_link_up = 1;
2576                                         tp->tg3_flags2 |=
2577                                                 TG3_FLG2_PARALLEL_DETECT;
2578                                         tp->serdes_counter =
2579                                                 SERDES_PARALLEL_DET_TIMEOUT;
2580                                 } else
2581                                         goto restart_autoneg;
2582                         }
2583                 }
2584         } else {
2585                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2586                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2587         }
2588
2589 out:
2590         return current_link_up;
2591 }
2592
2593 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2594 {
2595         int current_link_up = 0;
2596
2597         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2598                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2599                 goto out;
2600         }
2601
2602         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2603                 u32 flags;
2604                 int i;
2605
2606                 if (fiber_autoneg(tp, &flags)) {
2607                         u32 local_adv, remote_adv;
2608
2609                         local_adv = ADVERTISE_PAUSE_CAP;
2610                         remote_adv = 0;
2611                         if (flags & MR_LP_ADV_SYM_PAUSE)
2612                                 remote_adv |= LPA_PAUSE_CAP;
2613                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2614                                 remote_adv |= LPA_PAUSE_ASYM;
2615
2616                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2617
2618                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2619                         current_link_up = 1;
2620                 }
2621                 for (i = 0; i < 30; i++) {
2622                         udelay(20);
2623                         tw32_f(MAC_STATUS,
2624                                (MAC_STATUS_SYNC_CHANGED |
2625                                 MAC_STATUS_CFG_CHANGED));
2626                         udelay(40);
2627                         if ((tr32(MAC_STATUS) &
2628                              (MAC_STATUS_SYNC_CHANGED |
2629                               MAC_STATUS_CFG_CHANGED)) == 0)
2630                                 break;
2631                 }
2632
2633                 mac_status = tr32(MAC_STATUS);
2634                 if (current_link_up == 0 &&
2635                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2636                     !(mac_status & MAC_STATUS_RCVD_CFG))
2637                         current_link_up = 1;
2638         } else {
2639                 /* Forcing 1000FD link up. */
2640                 current_link_up = 1;
2641                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2642
2643                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2644                 udelay(40);
2645         }
2646
2647 out:
2648         return current_link_up;
2649 }
2650
2651 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2652 {
2653         u32 orig_pause_cfg;
2654         u16 orig_active_speed;
2655         u8 orig_active_duplex;
2656         u32 mac_status;
2657         int current_link_up;
2658         int i;
2659
2660         orig_pause_cfg =
2661                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2662                                   TG3_FLAG_TX_PAUSE));
2663         orig_active_speed = tp->link_config.active_speed;
2664         orig_active_duplex = tp->link_config.active_duplex;
2665
2666         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2667             netif_carrier_ok(tp->dev) &&
2668             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2669                 mac_status = tr32(MAC_STATUS);
2670                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2671                                MAC_STATUS_SIGNAL_DET |
2672                                MAC_STATUS_CFG_CHANGED |
2673                                MAC_STATUS_RCVD_CFG);
2674                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2675                                    MAC_STATUS_SIGNAL_DET)) {
2676                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2677                                             MAC_STATUS_CFG_CHANGED));
2678                         return 0;
2679                 }
2680         }
2681
2682         tw32_f(MAC_TX_AUTO_NEG, 0);
2683
2684         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2685         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2686         tw32_f(MAC_MODE, tp->mac_mode);
2687         udelay(40);
2688
2689         if (tp->phy_id == PHY_ID_BCM8002)
2690                 tg3_init_bcm8002(tp);
2691
2692         /* Enable link change event even when serdes polling.  */
2693         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2694         udelay(40);
2695
2696         current_link_up = 0;
2697         mac_status = tr32(MAC_STATUS);
2698
2699         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2700                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2701         else
2702                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2703
2704         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2705         tw32_f(MAC_MODE, tp->mac_mode);
2706         udelay(40);
2707
2708         tp->hw_status->status =
2709                 (SD_STATUS_UPDATED |
2710                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2711
2712         for (i = 0; i < 100; i++) {
2713                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2714                                     MAC_STATUS_CFG_CHANGED));
2715                 udelay(5);
2716                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2717                                          MAC_STATUS_CFG_CHANGED |
2718                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2719                         break;
2720         }
2721
2722         mac_status = tr32(MAC_STATUS);
2723         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2724                 current_link_up = 0;
2725                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2726                     tp->serdes_counter == 0) {
2727                         tw32_f(MAC_MODE, (tp->mac_mode |
2728                                           MAC_MODE_SEND_CONFIGS));
2729                         udelay(1);
2730                         tw32_f(MAC_MODE, tp->mac_mode);
2731                 }
2732         }
2733
2734         if (current_link_up == 1) {
2735                 tp->link_config.active_speed = SPEED_1000;
2736                 tp->link_config.active_duplex = DUPLEX_FULL;
2737                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2738                                     LED_CTRL_LNKLED_OVERRIDE |
2739                                     LED_CTRL_1000MBPS_ON));
2740         } else {
2741                 tp->link_config.active_speed = SPEED_INVALID;
2742                 tp->link_config.active_duplex = DUPLEX_INVALID;
2743                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2744                                     LED_CTRL_LNKLED_OVERRIDE |
2745                                     LED_CTRL_TRAFFIC_OVERRIDE));
2746         }
2747
2748         if (current_link_up != netif_carrier_ok(tp->dev)) {
2749                 if (current_link_up)
2750                         netif_carrier_on(tp->dev);
2751                 else
2752                         netif_carrier_off(tp->dev);
2753                 tg3_link_report(tp);
2754         } else {
2755                 u32 now_pause_cfg =
2756                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2757                                          TG3_FLAG_TX_PAUSE);
2758                 if (orig_pause_cfg != now_pause_cfg ||
2759                     orig_active_speed != tp->link_config.active_speed ||
2760                     orig_active_duplex != tp->link_config.active_duplex)
2761                         tg3_link_report(tp);
2762         }
2763
2764         return 0;
2765 }
2766
2767 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2768 {
2769         int current_link_up, err = 0;
2770         u32 bmsr, bmcr;
2771         u16 current_speed;
2772         u8 current_duplex;
2773
2774         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2775         tw32_f(MAC_MODE, tp->mac_mode);
2776         udelay(40);
2777
2778         tw32(MAC_EVENT, 0);
2779
2780         tw32_f(MAC_STATUS,
2781              (MAC_STATUS_SYNC_CHANGED |
2782               MAC_STATUS_CFG_CHANGED |
2783               MAC_STATUS_MI_COMPLETION |
2784               MAC_STATUS_LNKSTATE_CHANGED));
2785         udelay(40);
2786
2787         if (force_reset)
2788                 tg3_phy_reset(tp);
2789
2790         current_link_up = 0;
2791         current_speed = SPEED_INVALID;
2792         current_duplex = DUPLEX_INVALID;
2793
2794         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2795         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2796         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2797                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2798                         bmsr |= BMSR_LSTATUS;
2799                 else
2800                         bmsr &= ~BMSR_LSTATUS;
2801         }
2802
2803         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2804
2805         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2806             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2807                 /* do nothing, just check for link up at the end */
2808         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2809                 u32 adv, new_adv;
2810
2811                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2812                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2813                                   ADVERTISE_1000XPAUSE |
2814                                   ADVERTISE_1000XPSE_ASYM |
2815                                   ADVERTISE_SLCT);
2816
2817                 /* Always advertise symmetric PAUSE just like copper */
2818                 new_adv |= ADVERTISE_1000XPAUSE;
2819
2820                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2821                         new_adv |= ADVERTISE_1000XHALF;
2822                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2823                         new_adv |= ADVERTISE_1000XFULL;
2824
2825                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2826                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2827                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2828                         tg3_writephy(tp, MII_BMCR, bmcr);
2829
2830                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2831                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2832                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2833
2834                         return err;
2835                 }
2836         } else {
2837                 u32 new_bmcr;
2838
2839                 bmcr &= ~BMCR_SPEED1000;
2840                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2841
2842                 if (tp->link_config.duplex == DUPLEX_FULL)
2843                         new_bmcr |= BMCR_FULLDPLX;
2844
2845                 if (new_bmcr != bmcr) {
2846                         /* BMCR_SPEED1000 is a reserved bit that needs
2847                          * to be set on write.
2848                          */
2849                         new_bmcr |= BMCR_SPEED1000;
2850
2851                         /* Force a linkdown */
2852                         if (netif_carrier_ok(tp->dev)) {
2853                                 u32 adv;
2854
2855                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2856                                 adv &= ~(ADVERTISE_1000XFULL |
2857                                          ADVERTISE_1000XHALF |
2858                                          ADVERTISE_SLCT);
2859                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2860                                 tg3_writephy(tp, MII_BMCR, bmcr |
2861                                                            BMCR_ANRESTART |
2862                                                            BMCR_ANENABLE);
2863                                 udelay(10);
2864                                 netif_carrier_off(tp->dev);
2865                         }
2866                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2867                         bmcr = new_bmcr;
2868                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2869                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2870                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2871                             ASIC_REV_5714) {
2872                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2873                                         bmsr |= BMSR_LSTATUS;
2874                                 else
2875                                         bmsr &= ~BMSR_LSTATUS;
2876                         }
2877                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2878                 }
2879         }
2880
2881         if (bmsr & BMSR_LSTATUS) {
2882                 current_speed = SPEED_1000;
2883                 current_link_up = 1;
2884                 if (bmcr & BMCR_FULLDPLX)
2885                         current_duplex = DUPLEX_FULL;
2886                 else
2887                         current_duplex = DUPLEX_HALF;
2888
2889                 if (bmcr & BMCR_ANENABLE) {
2890                         u32 local_adv, remote_adv, common;
2891
2892                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2893                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2894                         common = local_adv & remote_adv;
2895                         if (common & (ADVERTISE_1000XHALF |
2896                                       ADVERTISE_1000XFULL)) {
2897                                 if (common & ADVERTISE_1000XFULL)
2898                                         current_duplex = DUPLEX_FULL;
2899                                 else
2900                                         current_duplex = DUPLEX_HALF;
2901
2902                                 tg3_setup_flow_control(tp, local_adv,
2903                                                        remote_adv);
2904                         }
2905                         else
2906                                 current_link_up = 0;
2907                 }
2908         }
2909
2910         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2911         if (tp->link_config.active_duplex == DUPLEX_HALF)
2912                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2913
2914         tw32_f(MAC_MODE, tp->mac_mode);
2915         udelay(40);
2916
2917         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2918
2919         tp->link_config.active_speed = current_speed;
2920         tp->link_config.active_duplex = current_duplex;
2921
2922         if (current_link_up != netif_carrier_ok(tp->dev)) {
2923                 if (current_link_up)
2924                         netif_carrier_on(tp->dev);
2925                 else {
2926                         netif_carrier_off(tp->dev);
2927                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2928                 }
2929                 tg3_link_report(tp);
2930         }
2931         return err;
2932 }
2933
2934 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2935 {
2936         if (tp->serdes_counter) {
2937                 /* Give autoneg time to complete. */
2938                 tp->serdes_counter--;
2939                 return;
2940         }
2941         if (!netif_carrier_ok(tp->dev) &&
2942             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2943                 u32 bmcr;
2944
2945                 tg3_readphy(tp, MII_BMCR, &bmcr);
2946                 if (bmcr & BMCR_ANENABLE) {
2947                         u32 phy1, phy2;
2948
2949                         /* Select shadow register 0x1f */
2950                         tg3_writephy(tp, 0x1c, 0x7c00);
2951                         tg3_readphy(tp, 0x1c, &phy1);
2952
2953                         /* Select expansion interrupt status register */
2954                         tg3_writephy(tp, 0x17, 0x0f01);
2955                         tg3_readphy(tp, 0x15, &phy2);
2956                         tg3_readphy(tp, 0x15, &phy2);
2957
2958                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2959                                 /* We have signal detect and not receiving
2960                                  * config code words, link is up by parallel
2961                                  * detection.
2962                                  */
2963
2964                                 bmcr &= ~BMCR_ANENABLE;
2965                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2966                                 tg3_writephy(tp, MII_BMCR, bmcr);
2967                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2968                         }
2969                 }
2970         }
2971         else if (netif_carrier_ok(tp->dev) &&
2972                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2973                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2974                 u32 phy2;
2975
2976                 /* Select expansion interrupt status register */
2977                 tg3_writephy(tp, 0x17, 0x0f01);
2978                 tg3_readphy(tp, 0x15, &phy2);
2979                 if (phy2 & 0x20) {
2980                         u32 bmcr;
2981
2982                         /* Config code words received, turn on autoneg. */
2983                         tg3_readphy(tp, MII_BMCR, &bmcr);
2984                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2985
2986                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2987
2988                 }
2989         }
2990 }
2991
2992 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2993 {
2994         int err;
2995
2996         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2997                 err = tg3_setup_fiber_phy(tp, force_reset);
2998         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2999                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3000         } else {
3001                 err = tg3_setup_copper_phy(tp, force_reset);
3002         }
3003
3004         if (tp->link_config.active_speed == SPEED_1000 &&
3005             tp->link_config.active_duplex == DUPLEX_HALF)
3006                 tw32(MAC_TX_LENGTHS,
3007                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3008                       (6 << TX_LENGTHS_IPG_SHIFT) |
3009                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3010         else
3011                 tw32(MAC_TX_LENGTHS,
3012                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3013                       (6 << TX_LENGTHS_IPG_SHIFT) |
3014                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3015
3016         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3017                 if (netif_carrier_ok(tp->dev)) {
3018                         tw32(HOSTCC_STAT_COAL_TICKS,
3019                              tp->coal.stats_block_coalesce_usecs);
3020                 } else {
3021                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3022                 }
3023         }
3024
3025         return err;
3026 }
3027
3028 /* This is called whenever we suspect that the system chipset is re-
3029  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3030  * is bogus tx completions. We try to recover by setting the
3031  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3032  * in the workqueue.
3033  */
3034 static void tg3_tx_recover(struct tg3 *tp)
3035 {
3036         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3037                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3038
3039         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3040                "mapped I/O cycles to the network device, attempting to "
3041                "recover. Please report the problem to the driver maintainer "
3042                "and include system chipset information.\n", tp->dev->name);
3043
3044         spin_lock(&tp->lock);
3045         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3046         spin_unlock(&tp->lock);
3047 }
3048
3049 static inline u32 tg3_tx_avail(struct tg3 *tp)
3050 {
3051         smp_mb();
3052         return (tp->tx_pending -
3053                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3054 }
3055
3056 /* Tigon3 never reports partial packet sends.  So we do not
3057  * need special logic to handle SKBs that have not had all
3058  * of their frags sent yet, like SunGEM does.
3059  */
3060 static void tg3_tx(struct tg3 *tp)
3061 {
3062         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3063         u32 sw_idx = tp->tx_cons;
3064
3065         while (sw_idx != hw_idx) {
3066                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3067                 struct sk_buff *skb = ri->skb;
3068                 int i, tx_bug = 0;
3069
3070                 if (unlikely(skb == NULL)) {
3071                         tg3_tx_recover(tp);
3072                         return;
3073                 }
3074
3075                 pci_unmap_single(tp->pdev,
3076                                  pci_unmap_addr(ri, mapping),
3077                                  skb_headlen(skb),
3078                                  PCI_DMA_TODEVICE);
3079
3080                 ri->skb = NULL;
3081
3082                 sw_idx = NEXT_TX(sw_idx);
3083
3084                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3085                         ri = &tp->tx_buffers[sw_idx];
3086                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3087                                 tx_bug = 1;
3088
3089                         pci_unmap_page(tp->pdev,
3090                                        pci_unmap_addr(ri, mapping),
3091                                        skb_shinfo(skb)->frags[i].size,
3092                                        PCI_DMA_TODEVICE);
3093
3094                         sw_idx = NEXT_TX(sw_idx);
3095                 }
3096
3097                 dev_kfree_skb(skb);
3098
3099                 if (unlikely(tx_bug)) {
3100                         tg3_tx_recover(tp);
3101                         return;
3102                 }
3103         }
3104
3105         tp->tx_cons = sw_idx;
3106
3107         /* Need to make the tx_cons update visible to tg3_start_xmit()
3108          * before checking for netif_queue_stopped().  Without the
3109          * memory barrier, there is a small possibility that tg3_start_xmit()
3110          * will miss it and cause the queue to be stopped forever.
3111          */
3112         smp_mb();
3113
3114         if (unlikely(netif_queue_stopped(tp->dev) &&
3115                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3116                 netif_tx_lock(tp->dev);
3117                 if (netif_queue_stopped(tp->dev) &&
3118                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3119                         netif_wake_queue(tp->dev);
3120                 netif_tx_unlock(tp->dev);
3121         }
3122 }
3123
3124 /* Returns size of skb allocated or < 0 on error.
3125  *
3126  * We only need to fill in the address because the other members
3127  * of the RX descriptor are invariant, see tg3_init_rings.
3128  *
3129  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3130  * posting buffers we only dirty the first cache line of the RX
3131  * descriptor (containing the address).  Whereas for the RX status
3132  * buffers the cpu only reads the last cacheline of the RX descriptor
3133  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3134  */
3135 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3136                             int src_idx, u32 dest_idx_unmasked)
3137 {
3138         struct tg3_rx_buffer_desc *desc;
3139         struct ring_info *map, *src_map;
3140         struct sk_buff *skb;
3141         dma_addr_t mapping;
3142         int skb_size, dest_idx;
3143
3144         src_map = NULL;
3145         switch (opaque_key) {
3146         case RXD_OPAQUE_RING_STD:
3147                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3148                 desc = &tp->rx_std[dest_idx];
3149                 map = &tp->rx_std_buffers[dest_idx];
3150                 if (src_idx >= 0)
3151                         src_map = &tp->rx_std_buffers[src_idx];
3152                 skb_size = tp->rx_pkt_buf_sz;
3153                 break;
3154
3155         case RXD_OPAQUE_RING_JUMBO:
3156                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3157                 desc = &tp->rx_jumbo[dest_idx];
3158                 map = &tp->rx_jumbo_buffers[dest_idx];
3159                 if (src_idx >= 0)
3160                         src_map = &tp->rx_jumbo_buffers[src_idx];
3161                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3162                 break;
3163
3164         default:
3165                 return -EINVAL;
3166         };
3167
3168         /* Do not overwrite any of the map or rp information
3169          * until we are sure we can commit to a new buffer.
3170          *
3171          * Callers depend upon this behavior and assume that
3172          * we leave everything unchanged if we fail.
3173          */
3174         skb = netdev_alloc_skb(tp->dev, skb_size);
3175         if (skb == NULL)
3176                 return -ENOMEM;
3177
3178         skb_reserve(skb, tp->rx_offset);
3179
3180         mapping = pci_map_single(tp->pdev, skb->data,
3181                                  skb_size - tp->rx_offset,
3182                                  PCI_DMA_FROMDEVICE);
3183
3184         map->skb = skb;
3185         pci_unmap_addr_set(map, mapping, mapping);
3186
3187         if (src_map != NULL)
3188                 src_map->skb = NULL;
3189
3190         desc->addr_hi = ((u64)mapping >> 32);
3191         desc->addr_lo = ((u64)mapping & 0xffffffff);
3192
3193         return skb_size;
3194 }
3195
3196 /* We only need to move over in the address because the other
3197  * members of the RX descriptor are invariant.  See notes above
3198  * tg3_alloc_rx_skb for full details.
3199  */
3200 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3201                            int src_idx, u32 dest_idx_unmasked)
3202 {
3203         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3204         struct ring_info *src_map, *dest_map;
3205         int dest_idx;
3206
3207         switch (opaque_key) {
3208         case RXD_OPAQUE_RING_STD:
3209                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3210                 dest_desc = &tp->rx_std[dest_idx];
3211                 dest_map = &tp->rx_std_buffers[dest_idx];
3212                 src_desc = &tp->rx_std[src_idx];
3213                 src_map = &tp->rx_std_buffers[src_idx];
3214                 break;
3215
3216         case RXD_OPAQUE_RING_JUMBO:
3217                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3218                 dest_desc = &tp->rx_jumbo[dest_idx];
3219                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3220                 src_desc = &tp->rx_jumbo[src_idx];
3221                 src_map = &tp->rx_jumbo_buffers[src_idx];
3222                 break;
3223
3224         default:
3225                 return;
3226         };
3227
3228         dest_map->skb = src_map->skb;
3229         pci_unmap_addr_set(dest_map, mapping,
3230                            pci_unmap_addr(src_map, mapping));
3231         dest_desc->addr_hi = src_desc->addr_hi;
3232         dest_desc->addr_lo = src_desc->addr_lo;
3233
3234         src_map->skb = NULL;
3235 }
3236
3237 #if TG3_VLAN_TAG_USED
3238 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3239 {
3240         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3241 }
3242 #endif
3243
3244 /* The RX ring scheme is composed of multiple rings which post fresh
3245  * buffers to the chip, and one special ring the chip uses to report
3246  * status back to the host.
3247  *
3248  * The special ring reports the status of received packets to the
3249  * host.  The chip does not write into the original descriptor the
3250  * RX buffer was obtained from.  The chip simply takes the original
3251  * descriptor as provided by the host, updates the status and length
3252  * field, then writes this into the next status ring entry.
3253  *
3254  * Each ring the host uses to post buffers to the chip is described
3255  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3256  * it is first placed into the on-chip ram.  When the packet's length
3257  * is known, it walks down the TG3_BDINFO entries to select the ring.
3258  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3259  * which is within the range of the new packet's length is chosen.
3260  *
3261  * The "separate ring for rx status" scheme may sound queer, but it makes
3262  * sense from a cache coherency perspective.  If only the host writes
3263  * to the buffer post rings, and only the chip writes to the rx status
3264  * rings, then cache lines never move beyond shared-modified state.
3265  * If both the host and chip were to write into the same ring, cache line
3266  * eviction could occur since both entities want it in an exclusive state.
3267  */
3268 static int tg3_rx(struct tg3 *tp, int budget)
3269 {
3270         u32 work_mask, rx_std_posted = 0;
3271         u32 sw_idx = tp->rx_rcb_ptr;
3272         u16 hw_idx;
3273         int received;
3274
3275         hw_idx = tp->hw_status->idx[0].rx_producer;
3276         /*
3277          * We need to order the read of hw_idx and the read of
3278          * the opaque cookie.
3279          */
3280         rmb();
3281         work_mask = 0;
3282         received = 0;
3283         while (sw_idx != hw_idx && budget > 0) {
3284                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3285                 unsigned int len;
3286                 struct sk_buff *skb;
3287                 dma_addr_t dma_addr;
3288                 u32 opaque_key, desc_idx, *post_ptr;
3289
3290                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3291                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3292                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3293                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3294                                                   mapping);
3295                         skb = tp->rx_std_buffers[desc_idx].skb;
3296                         post_ptr = &tp->rx_std_ptr;
3297                         rx_std_posted++;
3298                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3299                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3300                                                   mapping);
3301                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3302                         post_ptr = &tp->rx_jumbo_ptr;
3303                 }
3304                 else {
3305                         goto next_pkt_nopost;
3306                 }
3307
3308                 work_mask |= opaque_key;
3309
3310                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3311                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3312                 drop_it:
3313                         tg3_recycle_rx(tp, opaque_key,
3314                                        desc_idx, *post_ptr);
3315                 drop_it_no_recycle:
3316                         /* Other statistics kept track of by card. */
3317                         tp->net_stats.rx_dropped++;
3318                         goto next_pkt;
3319                 }
3320
3321                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3322
3323                 if (len > RX_COPY_THRESHOLD
3324                         && tp->rx_offset == 2
3325                         /* rx_offset != 2 iff this is a 5701 card running
3326                          * in PCI-X mode [see tg3_get_invariants()] */
3327                 ) {
3328                         int skb_size;
3329
3330                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3331                                                     desc_idx, *post_ptr);
3332                         if (skb_size < 0)
3333                                 goto drop_it;
3334
3335                         pci_unmap_single(tp->pdev, dma_addr,
3336                                          skb_size - tp->rx_offset,
3337                                          PCI_DMA_FROMDEVICE);
3338
3339                         skb_put(skb, len);
3340                 } else {
3341                         struct sk_buff *copy_skb;
3342
3343                         tg3_recycle_rx(tp, opaque_key,
3344                                        desc_idx, *post_ptr);
3345
3346                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3347                         if (copy_skb == NULL)
3348                                 goto drop_it_no_recycle;
3349
3350                         skb_reserve(copy_skb, 2);
3351                         skb_put(copy_skb, len);
3352                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3353                         memcpy(copy_skb->data, skb->data, len);
3354                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3355
3356                         /* We'll reuse the original ring buffer. */
3357                         skb = copy_skb;
3358                 }
3359
3360                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3361                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3362                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3363                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3364                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3365                 else
3366                         skb->ip_summed = CHECKSUM_NONE;
3367
3368                 skb->protocol = eth_type_trans(skb, tp->dev);
3369 #if TG3_VLAN_TAG_USED
3370                 if (tp->vlgrp != NULL &&
3371                     desc->type_flags & RXD_FLAG_VLAN) {
3372                         tg3_vlan_rx(tp, skb,
3373                                     desc->err_vlan & RXD_VLAN_MASK);
3374                 } else
3375 #endif
3376                         netif_receive_skb(skb);
3377
3378                 tp->dev->last_rx = jiffies;
3379                 received++;
3380                 budget--;
3381
3382 next_pkt:
3383                 (*post_ptr)++;
3384
3385                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3386                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3387
3388                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3389                                      TG3_64BIT_REG_LOW, idx);
3390                         work_mask &= ~RXD_OPAQUE_RING_STD;
3391                         rx_std_posted = 0;
3392                 }
3393 next_pkt_nopost:
3394                 sw_idx++;
3395                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3396
3397                 /* Refresh hw_idx to see if there is new work */
3398                 if (sw_idx == hw_idx) {
3399                         hw_idx = tp->hw_status->idx[0].rx_producer;
3400                         rmb();
3401                 }
3402         }
3403
3404         /* ACK the status ring. */
3405         tp->rx_rcb_ptr = sw_idx;
3406         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3407
3408         /* Refill RX ring(s). */
3409         if (work_mask & RXD_OPAQUE_RING_STD) {
3410                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3411                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3412                              sw_idx);
3413         }
3414         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3415                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3416                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3417                              sw_idx);
3418         }
3419         mmiowb();
3420
3421         return received;
3422 }
3423
3424 static int tg3_poll(struct net_device *netdev, int *budget)
3425 {
3426         struct tg3 *tp = netdev_priv(netdev);
3427         struct tg3_hw_status *sblk = tp->hw_status;
3428         int done;
3429
3430         /* handle link change and other phy events */
3431         if (!(tp->tg3_flags &
3432               (TG3_FLAG_USE_LINKCHG_REG |
3433                TG3_FLAG_POLL_SERDES))) {
3434                 if (sblk->status & SD_STATUS_LINK_CHG) {
3435                         sblk->status = SD_STATUS_UPDATED |
3436                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3437                         spin_lock(&tp->lock);
3438                         tg3_setup_phy(tp, 0);
3439                         spin_unlock(&tp->lock);
3440                 }
3441         }
3442
3443         /* run TX completion thread */
3444         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3445                 tg3_tx(tp);
3446                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3447                         netif_rx_complete(netdev);
3448                         schedule_work(&tp->reset_task);
3449                         return 0;
3450                 }
3451         }
3452
3453         /* run RX thread, within the bounds set by NAPI.
3454          * All RX "locking" is done by ensuring outside
3455          * code synchronizes with dev->poll()
3456          */
3457         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3458                 int orig_budget = *budget;
3459                 int work_done;
3460
3461                 if (orig_budget > netdev->quota)
3462                         orig_budget = netdev->quota;
3463
3464                 work_done = tg3_rx(tp, orig_budget);
3465
3466                 *budget -= work_done;
3467                 netdev->quota -= work_done;
3468         }
3469
3470         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3471                 tp->last_tag = sblk->status_tag;
3472                 rmb();
3473         } else
3474                 sblk->status &= ~SD_STATUS_UPDATED;
3475
3476         /* if no more work, tell net stack and NIC we're done */
3477         done = !tg3_has_work(tp);
3478         if (done) {
3479                 netif_rx_complete(netdev);
3480                 tg3_restart_ints(tp);
3481         }
3482
3483         return (done ? 0 : 1);
3484 }
3485
3486 static void tg3_irq_quiesce(struct tg3 *tp)
3487 {
3488         BUG_ON(tp->irq_sync);
3489
3490         tp->irq_sync = 1;
3491         smp_mb();
3492
3493         synchronize_irq(tp->pdev->irq);
3494 }
3495
3496 static inline int tg3_irq_sync(struct tg3 *tp)
3497 {
3498         return tp->irq_sync;
3499 }
3500
3501 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3502  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3503  * with as well.  Most of the time, this is not necessary except when
3504  * shutting down the device.
3505  */
3506 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3507 {
3508         if (irq_sync)
3509                 tg3_irq_quiesce(tp);
3510         spin_lock_bh(&tp->lock);
3511 }
3512
3513 static inline void tg3_full_unlock(struct tg3 *tp)
3514 {
3515         spin_unlock_bh(&tp->lock);
3516 }
3517
3518 /* One-shot MSI handler - Chip automatically disables interrupt
3519  * after sending MSI so driver doesn't have to do it.
3520  */
3521 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3522 {
3523         struct net_device *dev = dev_id;
3524         struct tg3 *tp = netdev_priv(dev);
3525
3526         prefetch(tp->hw_status);
3527         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3528
3529         if (likely(!tg3_irq_sync(tp)))
3530                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3531
3532         return IRQ_HANDLED;
3533 }
3534
3535 /* MSI ISR - No need to check for interrupt sharing and no need to
3536  * flush status block and interrupt mailbox. PCI ordering rules
3537  * guarantee that MSI will arrive after the status block.
3538  */
3539 static irqreturn_t tg3_msi(int irq, void *dev_id)
3540 {
3541         struct net_device *dev = dev_id;
3542         struct tg3 *tp = netdev_priv(dev);
3543
3544         prefetch(tp->hw_status);
3545         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3546         /*
3547          * Writing any value to intr-mbox-0 clears PCI INTA# and
3548          * chip-internal interrupt pending events.
3549          * Writing non-zero to intr-mbox-0 additional tells the
3550          * NIC to stop sending us irqs, engaging "in-intr-handler"
3551          * event coalescing.
3552          */
3553         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3554         if (likely(!tg3_irq_sync(tp)))
3555                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3556
3557         return IRQ_RETVAL(1);
3558 }
3559
3560 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3561 {
3562         struct net_device *dev = dev_id;
3563         struct tg3 *tp = netdev_priv(dev);
3564         struct tg3_hw_status *sblk = tp->hw_status;
3565         unsigned int handled = 1;
3566
3567         /* In INTx mode, it is possible for the interrupt to arrive at
3568          * the CPU before the status block posted prior to the interrupt.
3569          * Reading the PCI State register will confirm whether the
3570          * interrupt is ours and will flush the status block.
3571          */
3572         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3573                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3574                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3575                         handled = 0;
3576                         goto out;
3577                 }
3578         }
3579
3580         /*
3581          * Writing any value to intr-mbox-0 clears PCI INTA# and
3582          * chip-internal interrupt pending events.
3583          * Writing non-zero to intr-mbox-0 additional tells the
3584          * NIC to stop sending us irqs, engaging "in-intr-handler"
3585          * event coalescing.
3586          */
3587         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3588         if (tg3_irq_sync(tp))
3589                 goto out;
3590         sblk->status &= ~SD_STATUS_UPDATED;
3591         if (likely(tg3_has_work(tp))) {
3592                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3593                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3594         } else {
3595                 /* No work, shared interrupt perhaps?  re-enable
3596                  * interrupts, and flush that PCI write
3597                  */
3598                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3599                                0x00000000);
3600         }
3601 out:
3602         return IRQ_RETVAL(handled);
3603 }
3604
3605 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3606 {
3607         struct net_device *dev = dev_id;
3608         struct tg3 *tp = netdev_priv(dev);
3609         struct tg3_hw_status *sblk = tp->hw_status;
3610         unsigned int handled = 1;
3611
3612         /* In INTx mode, it is possible for the interrupt to arrive at
3613          * the CPU before the status block posted prior to the interrupt.
3614          * Reading the PCI State register will confirm whether the
3615          * interrupt is ours and will flush the status block.
3616          */
3617         if (unlikely(sblk->status_tag == tp->last_tag)) {
3618                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3619                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3620                         handled = 0;
3621                         goto out;
3622                 }
3623         }
3624
3625         /*
3626          * writing any value to intr-mbox-0 clears PCI INTA# and
3627          * chip-internal interrupt pending events.
3628          * writing non-zero to intr-mbox-0 additional tells the
3629          * NIC to stop sending us irqs, engaging "in-intr-handler"
3630          * event coalescing.
3631          */
3632         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3633         if (tg3_irq_sync(tp))
3634                 goto out;
3635         if (netif_rx_schedule_prep(dev)) {
3636                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3637                 /* Update last_tag to mark that this status has been
3638                  * seen. Because interrupt may be shared, we may be
3639                  * racing with tg3_poll(), so only update last_tag
3640                  * if tg3_poll() is not scheduled.
3641                  */
3642                 tp->last_tag = sblk->status_tag;
3643                 __netif_rx_schedule(dev);
3644         }
3645 out:
3646         return IRQ_RETVAL(handled);
3647 }
3648
3649 /* ISR for interrupt test */
3650 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3651 {
3652         struct net_device *dev = dev_id;
3653         struct tg3 *tp = netdev_priv(dev);
3654         struct tg3_hw_status *sblk = tp->hw_status;
3655
3656         if ((sblk->status & SD_STATUS_UPDATED) ||
3657             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3658                 tg3_disable_ints(tp);
3659                 return IRQ_RETVAL(1);
3660         }
3661         return IRQ_RETVAL(0);
3662 }
3663
3664 static int tg3_init_hw(struct tg3 *, int);
3665 static int tg3_halt(struct tg3 *, int, int);
3666
3667 /* Restart hardware after configuration changes, self-test, etc.
3668  * Invoked with tp->lock held.
3669  */
3670 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3671 {
3672         int err;
3673
3674         err = tg3_init_hw(tp, reset_phy);
3675         if (err) {
3676                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3677                        "aborting.\n", tp->dev->name);
3678                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3679                 tg3_full_unlock(tp);
3680                 del_timer_sync(&tp->timer);
3681                 tp->irq_sync = 0;
3682                 netif_poll_enable(tp->dev);
3683                 dev_close(tp->dev);
3684                 tg3_full_lock(tp, 0);
3685         }
3686         return err;
3687 }
3688
3689 #ifdef CONFIG_NET_POLL_CONTROLLER
3690 static void tg3_poll_controller(struct net_device *dev)
3691 {
3692         struct tg3 *tp = netdev_priv(dev);
3693
3694         tg3_interrupt(tp->pdev->irq, dev);
3695 }
3696 #endif
3697
3698 static void tg3_reset_task(struct work_struct *work)
3699 {
3700         struct tg3 *tp = container_of(work, struct tg3, reset_task);
3701         unsigned int restart_timer;
3702
3703         tg3_full_lock(tp, 0);
3704         tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3705
3706         if (!netif_running(tp->dev)) {
3707                 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3708                 tg3_full_unlock(tp);
3709                 return;
3710         }
3711
3712         tg3_full_unlock(tp);
3713
3714         tg3_netif_stop(tp);
3715
3716         tg3_full_lock(tp, 1);
3717
3718         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3719         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3720
3721         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3722                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3723                 tp->write32_rx_mbox = tg3_write_flush_reg32;
3724                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3725                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3726         }
3727
3728         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3729         if (tg3_init_hw(tp, 1))
3730                 goto out;
3731
3732         tg3_netif_start(tp);
3733
3734         if (restart_timer)
3735                 mod_timer(&tp->timer, jiffies + 1);
3736
3737 out:
3738         tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3739
3740         tg3_full_unlock(tp);
3741 }
3742
3743 static void tg3_dump_short_state(struct tg3 *tp)
3744 {
3745         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3746                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3747         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3748                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3749 }
3750
3751 static void tg3_tx_timeout(struct net_device *dev)
3752 {
3753         struct tg3 *tp = netdev_priv(dev);
3754
3755         if (netif_msg_tx_err(tp)) {
3756                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3757                        dev->name);
3758                 tg3_dump_short_state(tp);
3759         }
3760
3761         schedule_work(&tp->reset_task);
3762 }
3763
3764 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3765 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3766 {
3767         u32 base = (u32) mapping & 0xffffffff;
3768
3769         return ((base > 0xffffdcc0) &&
3770                 (base + len + 8 < base));
3771 }
3772
3773 /* Test for DMA addresses > 40-bit */
3774 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3775                                           int len)
3776 {
3777 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3778         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3779                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3780         return 0;
3781 #else
3782         return 0;
3783 #endif
3784 }
3785
3786 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3787
3788 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3789 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3790                                        u32 last_plus_one, u32 *start,
3791                                        u32 base_flags, u32 mss)
3792 {
3793         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3794         dma_addr_t new_addr = 0;
3795         u32 entry = *start;
3796         int i, ret = 0;
3797
3798         if (!new_skb) {
3799                 ret = -1;
3800         } else {
3801                 /* New SKB is guaranteed to be linear. */
3802                 entry = *start;
3803                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3804                                           PCI_DMA_TODEVICE);
3805                 /* Make sure new skb does not cross any 4G boundaries.
3806                  * Drop the packet if it does.
3807                  */
3808                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3809                         ret = -1;
3810                         dev_kfree_skb(new_skb);
3811                         new_skb = NULL;
3812                 } else {
3813                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3814                                     base_flags, 1 | (mss << 1));
3815                         *start = NEXT_TX(entry);
3816                 }
3817         }
3818
3819         /* Now clean up the sw ring entries. */
3820         i = 0;
3821         while (entry != last_plus_one) {
3822                 int len;
3823
3824                 if (i == 0)
3825                         len = skb_headlen(skb);
3826                 else
3827                         len = skb_shinfo(skb)->frags[i-1].size;
3828                 pci_unmap_single(tp->pdev,
3829                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3830                                  len, PCI_DMA_TODEVICE);
3831                 if (i == 0) {
3832                         tp->tx_buffers[entry].skb = new_skb;
3833                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3834                 } else {
3835                         tp->tx_buffers[entry].skb = NULL;
3836                 }
3837                 entry = NEXT_TX(entry);
3838                 i++;
3839         }
3840
3841         dev_kfree_skb(skb);
3842
3843         return ret;
3844 }
3845
3846 static void tg3_set_txd(struct tg3 *tp, int entry,
3847                         dma_addr_t mapping, int len, u32 flags,
3848                         u32 mss_and_is_end)
3849 {
3850         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3851         int is_end = (mss_and_is_end & 0x1);
3852         u32 mss = (mss_and_is_end >> 1);
3853         u32 vlan_tag = 0;
3854
3855         if (is_end)
3856                 flags |= TXD_FLAG_END;
3857         if (flags & TXD_FLAG_VLAN) {
3858                 vlan_tag = flags >> 16;
3859                 flags &= 0xffff;
3860         }
3861         vlan_tag |= (mss << TXD_MSS_SHIFT);
3862
3863         txd->addr_hi = ((u64) mapping >> 32);
3864         txd->addr_lo = ((u64) mapping & 0xffffffff);
3865         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3866         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3867 }
3868
3869 /* hard_start_xmit for devices that don't have any bugs and
3870  * support TG3_FLG2_HW_TSO_2 only.
3871  */
3872 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3873 {
3874         struct tg3 *tp = netdev_priv(dev);
3875         dma_addr_t mapping;
3876         u32 len, entry, base_flags, mss;
3877
3878         len = skb_headlen(skb);
3879
3880         /* We are running in BH disabled context with netif_tx_lock
3881          * and TX reclaim runs via tp->poll inside of a software
3882          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3883          * no IRQ context deadlocks to worry about either.  Rejoice!
3884          */
3885         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3886                 if (!netif_queue_stopped(dev)) {
3887                         netif_stop_queue(dev);
3888
3889                         /* This is a hard error, log it. */
3890                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3891                                "queue awake!\n", dev->name);
3892                 }
3893                 return NETDEV_TX_BUSY;
3894         }
3895
3896         entry = tp->tx_prod;
3897         base_flags = 0;
3898         mss = 0;
3899         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3900             (mss = skb_shinfo(skb)->gso_size) != 0) {
3901                 int tcp_opt_len, ip_tcp_len;
3902
3903                 if (skb_header_cloned(skb) &&
3904                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3905                         dev_kfree_skb(skb);
3906                         goto out_unlock;
3907                 }
3908
3909                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3910                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3911                 else {
3912                         tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3913                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
3914
3915                         skb->nh.iph->check = 0;
3916                         skb->nh.iph->tot_len = htons(mss + ip_tcp_len +
3917                                                      tcp_opt_len);
3918                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
3919                 }
3920
3921                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3922                                TXD_FLAG_CPU_POST_DMA);
3923
3924                 skb->h.th->check = 0;
3925
3926         }
3927         else if (skb->ip_summed == CHECKSUM_PARTIAL)
3928                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3929 #if TG3_VLAN_TAG_USED
3930         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3931                 base_flags |= (TXD_FLAG_VLAN |
3932                                (vlan_tx_tag_get(skb) << 16));
3933 #endif
3934
3935         /* Queue skb data, a.k.a. the main skb fragment. */
3936         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3937
3938         tp->tx_buffers[entry].skb = skb;
3939         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3940
3941         tg3_set_txd(tp, entry, mapping, len, base_flags,
3942                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3943
3944         entry = NEXT_TX(entry);
3945
3946         /* Now loop through additional data fragments, and queue them. */
3947         if (skb_shinfo(skb)->nr_frags > 0) {
3948                 unsigned int i, last;
3949
3950                 last = skb_shinfo(skb)->nr_frags - 1;
3951                 for (i = 0; i <= last; i++) {
3952                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3953
3954                         len = frag->size;
3955                         mapping = pci_map_page(tp->pdev,
3956                                                frag->page,
3957                                                frag->page_offset,
3958                                                len, PCI_DMA_TODEVICE);
3959
3960                         tp->tx_buffers[entry].skb = NULL;
3961                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3962
3963                         tg3_set_txd(tp, entry, mapping, len,
3964                                     base_flags, (i == last) | (mss << 1));
3965
3966                         entry = NEXT_TX(entry);
3967                 }
3968         }
3969
3970         /* Packets are ready, update Tx producer idx local and on card. */
3971         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3972
3973         tp->tx_prod = entry;
3974         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3975                 netif_stop_queue(dev);
3976                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3977                         netif_wake_queue(tp->dev);
3978         }
3979
3980 out_unlock:
3981         mmiowb();
3982
3983         dev->trans_start = jiffies;
3984
3985         return NETDEV_TX_OK;
3986 }
3987
3988 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3989
3990 /* Use GSO to workaround a rare TSO bug that may be triggered when the
3991  * TSO header is greater than 80 bytes.
3992  */
3993 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3994 {
3995         struct sk_buff *segs, *nskb;
3996
3997         /* Estimate the number of fragments in the worst case */
3998         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
3999                 netif_stop_queue(tp->dev);
4000                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4001                         return NETDEV_TX_BUSY;
4002
4003                 netif_wake_queue(tp->dev);
4004         }
4005
4006         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4007         if (unlikely(IS_ERR(segs)))
4008                 goto tg3_tso_bug_end;
4009
4010         do {
4011                 nskb = segs;
4012                 segs = segs->next;
4013                 nskb->next = NULL;
4014                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4015         } while (segs);
4016
4017 tg3_tso_bug_end:
4018         dev_kfree_skb(skb);
4019
4020         return NETDEV_TX_OK;
4021 }
4022
4023 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4024  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4025  */
4026 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4027 {
4028         struct tg3 *tp = netdev_priv(dev);
4029         dma_addr_t mapping;
4030         u32 len, entry, base_flags, mss;
4031         int would_hit_hwbug;
4032
4033         len = skb_headlen(skb);
4034
4035         /* We are running in BH disabled context with netif_tx_lock
4036          * and TX reclaim runs via tp->poll inside of a software
4037          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4038          * no IRQ context deadlocks to worry about either.  Rejoice!
4039          */
4040         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4041                 if (!netif_queue_stopped(dev)) {
4042                         netif_stop_queue(dev);
4043
4044                         /* This is a hard error, log it. */
4045                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4046                                "queue awake!\n", dev->name);
4047                 }
4048                 return NETDEV_TX_BUSY;
4049         }
4050
4051         entry = tp->tx_prod;
4052         base_flags = 0;
4053         if (skb->ip_summed == CHECKSUM_PARTIAL)
4054                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4055         mss = 0;
4056         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
4057             (mss = skb_shinfo(skb)->gso_size) != 0) {
4058                 int tcp_opt_len, ip_tcp_len, hdr_len;
4059
4060                 if (skb_header_cloned(skb) &&
4061                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4062                         dev_kfree_skb(skb);
4063                         goto out_unlock;
4064                 }
4065
4066                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4067                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4068
4069                 hdr_len = ip_tcp_len + tcp_opt_len;
4070                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4071                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4072                         return (tg3_tso_bug(tp, skb));
4073
4074                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4075                                TXD_FLAG_CPU_POST_DMA);
4076
4077                 skb->nh.iph->check = 0;
4078                 skb->nh.iph->tot_len = htons(mss + hdr_len);
4079                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4080                         skb->h.th->check = 0;
4081                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4082                 }
4083                 else {
4084                         skb->h.th->check =
4085                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4086                                                    skb->nh.iph->daddr,
4087                                                    0, IPPROTO_TCP, 0);
4088                 }
4089
4090                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4091                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4092                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4093                                 int tsflags;
4094
4095                                 tsflags = ((skb->nh.iph->ihl - 5) +
4096                                            (tcp_opt_len >> 2));
4097                                 mss |= (tsflags << 11);
4098                         }
4099                 } else {
4100                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4101                                 int tsflags;
4102
4103                                 tsflags = ((skb->nh.iph->ihl - 5) +
4104                                            (tcp_opt_len >> 2));
4105                                 base_flags |= tsflags << 12;
4106                         }
4107                 }
4108         }
4109 #if TG3_VLAN_TAG_USED
4110         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4111                 base_flags |= (TXD_FLAG_VLAN |
4112                                (vlan_tx_tag_get(skb) << 16));
4113 #endif
4114
4115         /* Queue skb data, a.k.a. the main skb fragment. */
4116         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4117
4118         tp->tx_buffers[entry].skb = skb;
4119         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4120
4121         would_hit_hwbug = 0;
4122
4123         if (tg3_4g_overflow_test(mapping, len))
4124                 would_hit_hwbug = 1;
4125
4126         tg3_set_txd(tp, entry, mapping, len, base_flags,
4127                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4128
4129         entry = NEXT_TX(entry);
4130
4131         /* Now loop through additional data fragments, and queue them. */
4132         if (skb_shinfo(skb)->nr_frags > 0) {
4133                 unsigned int i, last;
4134
4135                 last = skb_shinfo(skb)->nr_frags - 1;
4136                 for (i = 0; i <= last; i++) {
4137                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4138
4139                         len = frag->size;
4140                         mapping = pci_map_page(tp->pdev,
4141                                                frag->page,
4142                                                frag->page_offset,
4143                                                len, PCI_DMA_TODEVICE);
4144
4145                         tp->tx_buffers[entry].skb = NULL;
4146                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4147
4148                         if (tg3_4g_overflow_test(mapping, len))
4149                                 would_hit_hwbug = 1;
4150
4151                         if (tg3_40bit_overflow_test(tp, mapping, len))
4152                                 would_hit_hwbug = 1;
4153
4154                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4155                                 tg3_set_txd(tp, entry, mapping, len,
4156                                             base_flags, (i == last)|(mss << 1));
4157                         else
4158                                 tg3_set_txd(tp, entry, mapping, len,
4159                                             base_flags, (i == last));
4160
4161                         entry = NEXT_TX(entry);
4162                 }
4163         }
4164
4165         if (would_hit_hwbug) {
4166                 u32 last_plus_one = entry;
4167                 u32 start;
4168
4169                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4170                 start &= (TG3_TX_RING_SIZE - 1);
4171
4172                 /* If the workaround fails due to memory/mapping
4173                  * failure, silently drop this packet.
4174                  */
4175                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4176                                                 &start, base_flags, mss))
4177                         goto out_unlock;
4178
4179                 entry = start;
4180         }
4181
4182         /* Packets are ready, update Tx producer idx local and on card. */
4183         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4184
4185         tp->tx_prod = entry;
4186         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4187                 netif_stop_queue(dev);
4188                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4189                         netif_wake_queue(tp->dev);
4190         }
4191
4192 out_unlock:
4193         mmiowb();
4194
4195         dev->trans_start = jiffies;
4196
4197         return NETDEV_TX_OK;
4198 }
4199
4200 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4201                                int new_mtu)
4202 {
4203         dev->mtu = new_mtu;
4204
4205         if (new_mtu > ETH_DATA_LEN) {
4206                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4207                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4208                         ethtool_op_set_tso(dev, 0);
4209                 }
4210                 else
4211                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4212         } else {
4213                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4214                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4215                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4216         }
4217 }
4218
4219 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4220 {
4221         struct tg3 *tp = netdev_priv(dev);
4222         int err;
4223
4224         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4225                 return -EINVAL;
4226
4227         if (!netif_running(dev)) {
4228                 /* We'll just catch it later when the
4229                  * device is up'd.
4230                  */
4231                 tg3_set_mtu(dev, tp, new_mtu);
4232                 return 0;
4233         }
4234
4235         tg3_netif_stop(tp);
4236
4237         tg3_full_lock(tp, 1);
4238
4239         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4240
4241         tg3_set_mtu(dev, tp, new_mtu);
4242
4243         err = tg3_restart_hw(tp, 0);
4244
4245         if (!err)
4246                 tg3_netif_start(tp);
4247
4248         tg3_full_unlock(tp);
4249
4250         return err;
4251 }
4252
4253 /* Free up pending packets in all rx/tx rings.
4254  *
4255  * The chip has been shut down and the driver detached from
4256  * the networking, so no interrupts or new tx packets will
4257  * end up in the driver.  tp->{tx,}lock is not held and we are not
4258  * in an interrupt context and thus may sleep.
4259  */
4260 static void tg3_free_rings(struct tg3 *tp)
4261 {
4262         struct ring_info *rxp;
4263         int i;
4264
4265         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4266                 rxp = &tp->rx_std_buffers[i];
4267
4268                 if (rxp->skb == NULL)
4269                         continue;
4270                 pci_unmap_single(tp->pdev,
4271                                  pci_unmap_addr(rxp, mapping),
4272                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4273                                  PCI_DMA_FROMDEVICE);
4274                 dev_kfree_skb_any(rxp->skb);
4275                 rxp->skb = NULL;
4276         }
4277
4278         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4279                 rxp = &tp->rx_jumbo_buffers[i];
4280
4281                 if (rxp->skb == NULL)
4282                         continue;
4283                 pci_unmap_single(tp->pdev,
4284                                  pci_unmap_addr(rxp, mapping),
4285                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4286                                  PCI_DMA_FROMDEVICE);
4287                 dev_kfree_skb_any(rxp->skb);
4288                 rxp->skb = NULL;
4289         }
4290
4291         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4292                 struct tx_ring_info *txp;
4293                 struct sk_buff *skb;
4294                 int j;
4295
4296                 txp = &tp->tx_buffers[i];
4297                 skb = txp->skb;
4298
4299                 if (skb == NULL) {
4300                         i++;
4301                         continue;
4302                 }
4303
4304                 pci_unmap_single(tp->pdev,
4305                                  pci_unmap_addr(txp, mapping),
4306                                  skb_headlen(skb),
4307                                  PCI_DMA_TODEVICE);
4308                 txp->skb = NULL;
4309
4310                 i++;
4311
4312                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4313                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4314                         pci_unmap_page(tp->pdev,
4315                                        pci_unmap_addr(txp, mapping),
4316                                        skb_shinfo(skb)->frags[j].size,
4317                                        PCI_DMA_TODEVICE);
4318                         i++;
4319                 }
4320
4321                 dev_kfree_skb_any(skb);
4322         }
4323 }
4324
4325 /* Initialize tx/rx rings for packet processing.
4326  *
4327  * The chip has been shut down and the driver detached from
4328  * the networking, so no interrupts or new tx packets will
4329  * end up in the driver.  tp->{tx,}lock are held and thus
4330  * we may not sleep.
4331  */
4332 static int tg3_init_rings(struct tg3 *tp)
4333 {
4334         u32 i;
4335
4336         /* Free up all the SKBs. */
4337         tg3_free_rings(tp);
4338
4339         /* Zero out all descriptors. */
4340         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4341         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4342         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4343         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4344
4345         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4346         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4347             (tp->dev->mtu > ETH_DATA_LEN))
4348                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4349
4350         /* Initialize invariants of the rings, we only set this
4351          * stuff once.  This works because the card does not
4352          * write into the rx buffer posting rings.
4353          */
4354         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4355                 struct tg3_rx_buffer_desc *rxd;
4356
4357                 rxd = &tp->rx_std[i];
4358                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4359                         << RXD_LEN_SHIFT;
4360                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4361                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4362                                (i << RXD_OPAQUE_INDEX_SHIFT));
4363         }
4364
4365         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4366                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4367                         struct tg3_rx_buffer_desc *rxd;
4368
4369                         rxd = &tp->rx_jumbo[i];
4370                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4371                                 << RXD_LEN_SHIFT;
4372                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4373                                 RXD_FLAG_JUMBO;
4374                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4375                                (i << RXD_OPAQUE_INDEX_SHIFT));
4376                 }
4377         }
4378
4379         /* Now allocate fresh SKBs for each rx ring. */
4380         for (i = 0; i < tp->rx_pending; i++) {
4381                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4382                         printk(KERN_WARNING PFX
4383                                "%s: Using a smaller RX standard ring, "
4384                                "only %d out of %d buffers were allocated "
4385                                "successfully.\n",
4386                                tp->dev->name, i, tp->rx_pending);
4387                         if (i == 0)
4388                                 return -ENOMEM;
4389                         tp->rx_pending = i;
4390                         break;
4391                 }
4392         }
4393
4394         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4395                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4396                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4397                                              -1, i) < 0) {
4398                                 printk(KERN_WARNING PFX
4399                                        "%s: Using a smaller RX jumbo ring, "
4400                                        "only %d out of %d buffers were "
4401                                        "allocated successfully.\n",
4402                                        tp->dev->name, i, tp->rx_jumbo_pending);
4403                                 if (i == 0) {
4404                                         tg3_free_rings(tp);
4405                                         return -ENOMEM;
4406                                 }
4407                                 tp->rx_jumbo_pending = i;
4408                                 break;
4409                         }
4410                 }
4411         }
4412         return 0;
4413 }
4414
4415 /*
4416  * Must not be invoked with interrupt sources disabled and
4417  * the hardware shutdown down.
4418  */
4419 static void tg3_free_consistent(struct tg3 *tp)
4420 {
4421         kfree(tp->rx_std_buffers);
4422         tp->rx_std_buffers = NULL;
4423         if (tp->rx_std) {
4424                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4425                                     tp->rx_std, tp->rx_std_mapping);
4426                 tp->rx_std = NULL;
4427         }
4428         if (tp->rx_jumbo) {
4429                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4430                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4431                 tp->rx_jumbo = NULL;
4432         }
4433         if (tp->rx_rcb) {
4434                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4435                                     tp->rx_rcb, tp->rx_rcb_mapping);
4436                 tp->rx_rcb = NULL;
4437         }
4438         if (tp->tx_ring) {
4439                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4440                         tp->tx_ring, tp->tx_desc_mapping);
4441                 tp->tx_ring = NULL;
4442         }
4443         if (tp->hw_status) {
4444                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4445                                     tp->hw_status, tp->status_mapping);
4446                 tp->hw_status = NULL;
4447         }
4448         if (tp->hw_stats) {
4449                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4450                                     tp->hw_stats, tp->stats_mapping);
4451                 tp->hw_stats = NULL;
4452         }
4453 }
4454
4455 /*
4456  * Must not be invoked with interrupt sources disabled and
4457  * the hardware shutdown down.  Can sleep.
4458  */
4459 static int tg3_alloc_consistent(struct tg3 *tp)
4460 {
4461         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4462                                       (TG3_RX_RING_SIZE +
4463                                        TG3_RX_JUMBO_RING_SIZE)) +
4464                                      (sizeof(struct tx_ring_info) *
4465                                       TG3_TX_RING_SIZE),
4466                                      GFP_KERNEL);
4467         if (!tp->rx_std_buffers)
4468                 return -ENOMEM;
4469
4470         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4471         tp->tx_buffers = (struct tx_ring_info *)
4472                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4473
4474         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4475                                           &tp->rx_std_mapping);
4476         if (!tp->rx_std)
4477                 goto err_out;
4478
4479         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4480                                             &tp->rx_jumbo_mapping);
4481
4482         if (!tp->rx_jumbo)
4483                 goto err_out;
4484
4485         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4486                                           &tp->rx_rcb_mapping);
4487         if (!tp->rx_rcb)
4488                 goto err_out;
4489
4490         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4491                                            &tp->tx_desc_mapping);
4492         if (!tp->tx_ring)
4493                 goto err_out;
4494
4495         tp->hw_status = pci_alloc_consistent(tp->pdev,
4496                                              TG3_HW_STATUS_SIZE,
4497                                              &tp->status_mapping);
4498         if (!tp->hw_status)
4499                 goto err_out;
4500
4501         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4502                                             sizeof(struct tg3_hw_stats),
4503                                             &tp->stats_mapping);
4504         if (!tp->hw_stats)
4505                 goto err_out;
4506
4507         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4508         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4509
4510         return 0;
4511
4512 err_out:
4513         tg3_free_consistent(tp);
4514         return -ENOMEM;
4515 }
4516
4517 #define MAX_WAIT_CNT 1000
4518
4519 /* To stop a block, clear the enable bit and poll till it
4520  * clears.  tp->lock is held.
4521  */
4522 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4523 {
4524         unsigned int i;
4525         u32 val;
4526
4527         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4528                 switch (ofs) {
4529                 case RCVLSC_MODE:
4530                 case DMAC_MODE:
4531                 case MBFREE_MODE:
4532                 case BUFMGR_MODE:
4533                 case MEMARB_MODE:
4534                         /* We can't enable/disable these bits of the
4535                          * 5705/5750, just say success.
4536                          */
4537                         return 0;
4538
4539                 default:
4540                         break;
4541                 };
4542         }
4543
4544         val = tr32(ofs);
4545         val &= ~enable_bit;
4546         tw32_f(ofs, val);
4547
4548         for (i = 0; i < MAX_WAIT_CNT; i++) {
4549                 udelay(100);
4550                 val = tr32(ofs);
4551                 if ((val & enable_bit) == 0)
4552                         break;
4553         }
4554
4555         if (i == MAX_WAIT_CNT && !silent) {
4556                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4557                        "ofs=%lx enable_bit=%x\n",
4558                        ofs, enable_bit);
4559                 return -ENODEV;
4560         }
4561
4562         return 0;
4563 }
4564
4565 /* tp->lock is held. */
4566 static int tg3_abort_hw(struct tg3 *tp, int silent)
4567 {
4568         int i, err;
4569
4570         tg3_disable_ints(tp);
4571
4572         tp->rx_mode &= ~RX_MODE_ENABLE;
4573         tw32_f(MAC_RX_MODE, tp->rx_mode);
4574         udelay(10);
4575
4576         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4577         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4578         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4579         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4580         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4581         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4582
4583         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4584         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4585         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4586         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4587         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4588         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4589         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4590
4591         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4592         tw32_f(MAC_MODE, tp->mac_mode);
4593         udelay(40);
4594
4595         tp->tx_mode &= ~TX_MODE_ENABLE;
4596         tw32_f(MAC_TX_MODE, tp->tx_mode);
4597
4598         for (i = 0; i < MAX_WAIT_CNT; i++) {
4599                 udelay(100);
4600                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4601                         break;
4602         }
4603         if (i >= MAX_WAIT_CNT) {
4604                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4605                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4606                        tp->dev->name, tr32(MAC_TX_MODE));
4607                 err |= -ENODEV;
4608         }
4609
4610         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4611         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4612         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4613
4614         tw32(FTQ_RESET, 0xffffffff);
4615         tw32(FTQ_RESET, 0x00000000);
4616
4617         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4618         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4619
4620         if (tp->hw_status)
4621                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4622         if (tp->hw_stats)
4623                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4624
4625         return err;
4626 }
4627
4628 /* tp->lock is held. */
4629 static int tg3_nvram_lock(struct tg3 *tp)
4630 {
4631         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4632                 int i;
4633
4634                 if (tp->nvram_lock_cnt == 0) {
4635                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4636                         for (i = 0; i < 8000; i++) {
4637                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4638                                         break;
4639                                 udelay(20);
4640                         }
4641                         if (i == 8000) {
4642                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4643                                 return -ENODEV;
4644                         }
4645                 }
4646                 tp->nvram_lock_cnt++;
4647         }
4648         return 0;
4649 }
4650
4651 /* tp->lock is held. */
4652 static void tg3_nvram_unlock(struct tg3 *tp)
4653 {
4654         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4655                 if (tp->nvram_lock_cnt > 0)
4656                         tp->nvram_lock_cnt--;
4657                 if (tp->nvram_lock_cnt == 0)
4658                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4659         }
4660 }
4661
4662 /* tp->lock is held. */
4663 static void tg3_enable_nvram_access(struct tg3 *tp)
4664 {
4665         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4666             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4667                 u32 nvaccess = tr32(NVRAM_ACCESS);
4668
4669                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4670         }
4671 }
4672
4673 /* tp->lock is held. */
4674 static void tg3_disable_nvram_access(struct tg3 *tp)
4675 {
4676         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4677             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4678                 u32 nvaccess = tr32(NVRAM_ACCESS);
4679
4680                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4681         }
4682 }
4683
4684 /* tp->lock is held. */
4685 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4686 {
4687         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4688                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4689
4690         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4691                 switch (kind) {
4692                 case RESET_KIND_INIT:
4693                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4694                                       DRV_STATE_START);
4695                         break;
4696
4697                 case RESET_KIND_SHUTDOWN:
4698                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4699                                       DRV_STATE_UNLOAD);
4700                         break;
4701
4702                 case RESET_KIND_SUSPEND:
4703                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4704                                       DRV_STATE_SUSPEND);
4705                         break;
4706
4707                 default:
4708                         break;
4709                 };
4710         }
4711 }
4712
4713 /* tp->lock is held. */
4714 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4715 {
4716         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4717                 switch (kind) {
4718                 case RESET_KIND_INIT:
4719                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4720                                       DRV_STATE_START_DONE);
4721                         break;
4722
4723                 case RESET_KIND_SHUTDOWN:
4724                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4725                                       DRV_STATE_UNLOAD_DONE);
4726                         break;
4727
4728                 default:
4729                         break;
4730                 };
4731         }
4732 }
4733
4734 /* tp->lock is held. */
4735 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4736 {
4737         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4738                 switch (kind) {
4739                 case RESET_KIND_INIT:
4740                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4741                                       DRV_STATE_START);
4742                         break;
4743
4744                 case RESET_KIND_SHUTDOWN:
4745                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4746                                       DRV_STATE_UNLOAD);
4747                         break;
4748
4749                 case RESET_KIND_SUSPEND:
4750                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4751                                       DRV_STATE_SUSPEND);
4752                         break;
4753
4754                 default:
4755                         break;
4756                 };
4757         }
4758 }
4759
4760 static int tg3_poll_fw(struct tg3 *tp)
4761 {
4762         int i;
4763         u32 val;
4764
4765         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4766                 /* Wait up to 20ms for init done. */
4767                 for (i = 0; i < 200; i++) {
4768                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4769                                 return 0;
4770                         udelay(100);
4771                 }
4772                 return -ENODEV;
4773         }
4774
4775         /* Wait for firmware initialization to complete. */
4776         for (i = 0; i < 100000; i++) {
4777                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4778                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4779                         break;
4780                 udelay(10);
4781         }
4782
4783         /* Chip might not be fitted with firmware.  Some Sun onboard
4784          * parts are configured like that.  So don't signal the timeout
4785          * of the above loop as an error, but do report the lack of
4786          * running firmware once.
4787          */
4788         if (i >= 100000 &&
4789             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4790                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4791
4792                 printk(KERN_INFO PFX "%s: No firmware running.\n",
4793                        tp->dev->name);
4794         }
4795
4796         return 0;
4797 }
4798
4799 static void tg3_stop_fw(struct tg3 *);
4800
4801 /* tp->lock is held. */
4802 static int tg3_chip_reset(struct tg3 *tp)
4803 {
4804         u32 val;
4805         void (*write_op)(struct tg3 *, u32, u32);
4806         int err;
4807
4808         tg3_nvram_lock(tp);
4809
4810         /* No matching tg3_nvram_unlock() after this because
4811          * chip reset below will undo the nvram lock.
4812          */
4813         tp->nvram_lock_cnt = 0;
4814
4815         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4816             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4817             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4818                 tw32(GRC_FASTBOOT_PC, 0);
4819
4820         /*
4821          * We must avoid the readl() that normally takes place.
4822          * It locks machines, causes machine checks, and other
4823          * fun things.  So, temporarily disable the 5701
4824          * hardware workaround, while we do the reset.
4825          */
4826         write_op = tp->write32;
4827         if (write_op == tg3_write_flush_reg32)
4828                 tp->write32 = tg3_write32;
4829
4830         /* Prevent the irq handler from reading or writing PCI registers
4831          * during chip reset when the memory enable bit in the PCI command
4832          * register may be cleared.  The chip does not generate interrupt
4833          * at this time, but the irq handler may still be called due to irq
4834          * sharing or irqpoll.
4835          */
4836         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
4837         if (tp->hw_status) {
4838                 tp->hw_status->status = 0;
4839                 tp->hw_status->status_tag = 0;
4840         }
4841         tp->last_tag = 0;
4842         smp_mb();
4843         synchronize_irq(tp->pdev->irq);
4844
4845         /* do the reset */
4846         val = GRC_MISC_CFG_CORECLK_RESET;
4847
4848         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4849                 if (tr32(0x7e2c) == 0x60) {
4850                         tw32(0x7e2c, 0x20);
4851                 }
4852                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4853                         tw32(GRC_MISC_CFG, (1 << 29));
4854                         val |= (1 << 29);
4855                 }
4856         }
4857
4858         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4859                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4860                 tw32(GRC_VCPU_EXT_CTRL,
4861                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4862         }
4863
4864         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4865                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4866         tw32(GRC_MISC_CFG, val);
4867
4868         /* restore 5701 hardware bug workaround write method */
4869         tp->write32 = write_op;
4870
4871         /* Unfortunately, we have to delay before the PCI read back.
4872          * Some 575X chips even will not respond to a PCI cfg access
4873          * when the reset command is given to the chip.
4874          *
4875          * How do these hardware designers expect things to work
4876          * properly if the PCI write is posted for a long period
4877          * of time?  It is always necessary to have some method by
4878          * which a register read back can occur to push the write
4879          * out which does the reset.
4880          *
4881          * For most tg3 variants the trick below was working.
4882          * Ho hum...
4883          */
4884         udelay(120);
4885
4886         /* Flush PCI posted writes.  The normal MMIO registers
4887          * are inaccessible at this time so this is the only
4888          * way to make this reliably (actually, this is no longer
4889          * the case, see above).  I tried to use indirect
4890          * register read/write but this upset some 5701 variants.
4891          */
4892         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4893
4894         udelay(120);
4895
4896         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4897                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4898                         int i;
4899                         u32 cfg_val;
4900
4901                         /* Wait for link training to complete.  */
4902                         for (i = 0; i < 5000; i++)
4903                                 udelay(100);
4904
4905                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4906                         pci_write_config_dword(tp->pdev, 0xc4,
4907                                                cfg_val | (1 << 15));
4908                 }
4909                 /* Set PCIE max payload size and clear error status.  */
4910                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4911         }
4912
4913         /* Re-enable indirect register accesses. */
4914         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4915                                tp->misc_host_ctrl);
4916
4917         /* Set MAX PCI retry to zero. */
4918         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4919         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4920             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4921                 val |= PCISTATE_RETRY_SAME_DMA;
4922         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4923
4924         pci_restore_state(tp->pdev);
4925
4926         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
4927
4928         /* Make sure PCI-X relaxed ordering bit is clear. */
4929         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4930         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4931         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4932
4933         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4934                 u32 val;
4935
4936                 /* Chip reset on 5780 will reset MSI enable bit,
4937                  * so need to restore it.
4938                  */
4939                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4940                         u16 ctrl;
4941
4942                         pci_read_config_word(tp->pdev,
4943                                              tp->msi_cap + PCI_MSI_FLAGS,
4944                                              &ctrl);
4945                         pci_write_config_word(tp->pdev,
4946                                               tp->msi_cap + PCI_MSI_FLAGS,
4947                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4948                         val = tr32(MSGINT_MODE);
4949                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4950                 }
4951
4952                 val = tr32(MEMARB_MODE);
4953                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4954
4955         } else
4956                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4957
4958         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4959                 tg3_stop_fw(tp);
4960                 tw32(0x5000, 0x400);
4961         }
4962
4963         tw32(GRC_MODE, tp->grc_mode);
4964
4965         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4966                 u32 val = tr32(0xc4);
4967
4968                 tw32(0xc4, val | (1 << 15));
4969         }
4970
4971         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4972             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4973                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4974                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4975                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4976                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4977         }
4978
4979         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4980                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4981                 tw32_f(MAC_MODE, tp->mac_mode);
4982         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4983                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4984                 tw32_f(MAC_MODE, tp->mac_mode);
4985         } else
4986                 tw32_f(MAC_MODE, 0);
4987         udelay(40);
4988
4989         err = tg3_poll_fw(tp);
4990         if (err)
4991                 return err;
4992
4993         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4994             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4995                 u32 val = tr32(0x7c00);
4996
4997                 tw32(0x7c00, val | (1 << 25));
4998         }
4999
5000         /* Reprobe ASF enable state.  */
5001         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5002         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5003         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5004         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5005                 u32 nic_cfg;
5006
5007                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5008                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5009                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5010                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5011                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5012                 }
5013         }
5014
5015         return 0;
5016 }
5017
5018 /* tp->lock is held. */
5019 static void tg3_stop_fw(struct tg3 *tp)
5020 {
5021         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5022                 u32 val;
5023                 int i;
5024
5025                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5026                 val = tr32(GRC_RX_CPU_EVENT);
5027                 val |= (1 << 14);
5028                 tw32(GRC_RX_CPU_EVENT, val);
5029
5030                 /* Wait for RX cpu to ACK the event.  */
5031                 for (i = 0; i < 100; i++) {
5032                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5033                                 break;
5034                         udelay(1);
5035                 }
5036         }
5037 }
5038
5039 /* tp->lock is held. */
5040 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5041 {
5042         int err;
5043
5044         tg3_stop_fw(tp);
5045
5046         tg3_write_sig_pre_reset(tp, kind);
5047
5048         tg3_abort_hw(tp, silent);
5049         err = tg3_chip_reset(tp);
5050
5051         tg3_write_sig_legacy(tp, kind);
5052         tg3_write_sig_post_reset(tp, kind);
5053
5054         if (err)
5055                 return err;
5056
5057         return 0;
5058 }
5059
5060 #define TG3_FW_RELEASE_MAJOR    0x0
5061 #define TG3_FW_RELASE_MINOR     0x0
5062 #define TG3_FW_RELEASE_FIX      0x0
5063 #define TG3_FW_START_ADDR       0x08000000
5064 #define TG3_FW_TEXT_ADDR        0x08000000
5065 #define TG3_FW_TEXT_LEN         0x9c0
5066 #define TG3_FW_RODATA_ADDR      0x080009c0
5067 #define TG3_FW_RODATA_LEN       0x60
5068 #define TG3_FW_DATA_ADDR        0x08000a40
5069 #define TG3_FW_DATA_LEN         0x20
5070 #define TG3_FW_SBSS_ADDR        0x08000a60
5071 #define TG3_FW_SBSS_LEN         0xc
5072 #define TG3_FW_BSS_ADDR         0x08000a70
5073 #define TG3_FW_BSS_LEN          0x10
5074
5075 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5076         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5077         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5078         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5079         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5080         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5081         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5082         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5083         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5084         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5085         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5086         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5087         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5088         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5089         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5090         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5091         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5092         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5093         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5094         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5095         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5096         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5097         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5098         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5099         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5100         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5101         0, 0, 0, 0, 0, 0,
5102         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5103         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5104         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5105         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5106         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5107         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5108         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5109         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5110         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5111         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5112         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5113         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5114         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5115         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5116         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5117         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5118         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5119         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5120         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5121         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5122         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5123         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5124         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5125         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5126         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5127         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5128         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5129         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5130         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5131         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5132         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5133         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5134         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5135         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5136         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5137         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5138         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5139         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5140         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5141         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5142         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5143         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5144         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5145         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5146         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5147         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5148         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5149         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5150         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5151         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5152         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5153         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5154         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5155         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5156         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5157         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5158         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5159         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5160         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5161         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5162         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5163         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5164         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5165         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5166         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5167 };
5168
5169 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5170         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5171         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5172         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5173         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5174         0x00000000
5175 };
5176
5177 #if 0 /* All zeros, don't eat up space with it. */
5178 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5179         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5180         0x00000000, 0x00000000, 0x00000000, 0x00000000
5181 };
5182 #endif
5183
5184 #define RX_CPU_SCRATCH_BASE     0x30000
5185 #define RX_CPU_SCRATCH_SIZE     0x04000
5186 #define TX_CPU_SCRATCH_BASE     0x34000
5187 #define TX_CPU_SCRATCH_SIZE     0x04000
5188
5189 /* tp->lock is held. */
5190 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5191 {
5192         int i;
5193
5194         BUG_ON(offset == TX_CPU_BASE &&
5195             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5196
5197         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5198                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5199
5200                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5201                 return 0;
5202         }
5203         if (offset == RX_CPU_BASE) {
5204                 for (i = 0; i < 10000; i++) {
5205                         tw32(offset + CPU_STATE, 0xffffffff);
5206                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5207                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5208                                 break;
5209                 }
5210
5211                 tw32(offset + CPU_STATE, 0xffffffff);
5212                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5213                 udelay(10);
5214         } else {
5215                 for (i = 0; i < 10000; i++) {
5216                         tw32(offset + CPU_STATE, 0xffffffff);
5217                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5218                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5219                                 break;
5220                 }
5221         }
5222
5223         if (i >= 10000) {
5224                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5225                        "and %s CPU\n",
5226                        tp->dev->name,
5227                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5228                 return -ENODEV;
5229         }
5230
5231         /* Clear firmware's nvram arbitration. */
5232         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5233                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5234         return 0;
5235 }
5236
5237 struct fw_info {
5238         unsigned int text_base;
5239         unsigned int text_len;
5240         const u32 *text_data;
5241         unsigned int rodata_base;
5242         unsigned int rodata_len;
5243         const u32 *rodata_data;
5244         unsigned int data_base;
5245         unsigned int data_len;
5246         const u32 *data_data;
5247 };
5248
5249 /* tp->lock is held. */
5250 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5251                                  int cpu_scratch_size, struct fw_info *info)
5252 {
5253         int err, lock_err, i;
5254         void (*write_op)(struct tg3 *, u32, u32);
5255
5256         if (cpu_base == TX_CPU_BASE &&
5257             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5258                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5259                        "TX cpu firmware on %s which is 5705.\n",
5260                        tp->dev->name);
5261                 return -EINVAL;
5262         }
5263
5264         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5265                 write_op = tg3_write_mem;
5266         else
5267                 write_op = tg3_write_indirect_reg32;
5268
5269         /* It is possible that bootcode is still loading at this point.
5270          * Get the nvram lock first before halting the cpu.
5271          */
5272         lock_err = tg3_nvram_lock(tp);
5273         err = tg3_halt_cpu(tp, cpu_base);
5274         if (!lock_err)
5275                 tg3_nvram_unlock(tp);
5276         if (err)
5277                 goto out;
5278
5279         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5280                 write_op(tp, cpu_scratch_base + i, 0);
5281         tw32(cpu_base + CPU_STATE, 0xffffffff);
5282         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5283         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5284                 write_op(tp, (cpu_scratch_base +
5285                               (info->text_base & 0xffff) +
5286                               (i * sizeof(u32))),
5287                          (info->text_data ?
5288                           info->text_data[i] : 0));
5289         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5290                 write_op(tp, (cpu_scratch_base +
5291                               (info->rodata_base & 0xffff) +
5292                               (i * sizeof(u32))),
5293                          (info->rodata_data ?
5294                           info->rodata_data[i] : 0));
5295         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5296                 write_op(tp, (cpu_scratch_base +
5297                               (info->data_base & 0xffff) +
5298                               (i * sizeof(u32))),
5299                          (info->data_data ?
5300                           info->data_data[i] : 0));
5301
5302         err = 0;
5303
5304 out:
5305         return err;
5306 }
5307
5308 /* tp->lock is held. */
5309 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5310 {
5311         struct fw_info info;
5312         int err, i;
5313
5314         info.text_base = TG3_FW_TEXT_ADDR;
5315         info.text_len = TG3_FW_TEXT_LEN;
5316         info.text_data = &tg3FwText[0];
5317         info.rodata_base = TG3_FW_RODATA_ADDR;
5318         info.rodata_len = TG3_FW_RODATA_LEN;
5319         info.rodata_data = &tg3FwRodata[0];
5320         info.data_base = TG3_FW_DATA_ADDR;
5321         info.data_len = TG3_FW_DATA_LEN;
5322         info.data_data = NULL;
5323
5324         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5325                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5326                                     &info);
5327         if (err)
5328                 return err;
5329
5330         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5331                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5332                                     &info);
5333         if (err)
5334                 return err;
5335
5336         /* Now startup only the RX cpu. */
5337         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5338         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5339
5340         for (i = 0; i < 5; i++) {
5341                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5342                         break;
5343                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5344                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5345                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5346                 udelay(1000);
5347         }
5348         if (i >= 5) {
5349                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5350                        "to set RX CPU PC, is %08x should be %08x\n",
5351                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5352                        TG3_FW_TEXT_ADDR);
5353                 return -ENODEV;
5354         }
5355         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5356         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5357
5358         return 0;
5359 }
5360
5361
5362 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5363 #define TG3_TSO_FW_RELASE_MINOR         0x6
5364 #define TG3_TSO_FW_RELEASE_FIX          0x0
5365 #define TG3_TSO_FW_START_ADDR           0x08000000
5366 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5367 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5368 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5369 #define TG3_TSO_FW_RODATA_LEN           0x60
5370 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5371 #define TG3_TSO_FW_DATA_LEN             0x30
5372 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5373 #define TG3_TSO_FW_SBSS_LEN             0x2c
5374 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5375 #define TG3_TSO_FW_BSS_LEN              0x894
5376
5377 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5378         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5379         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5380         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5381         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5382         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5383         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5384         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5385         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5386         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5387         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5388         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5389         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5390         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5391         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5392         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5393         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5394         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5395         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5396         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5397         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5398         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5399         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5400         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5401         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5402         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5403         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5404         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5405         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5406         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5407         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5408         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5409         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5410         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5411         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5412         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5413         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5414         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5415         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5416         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5417         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5418         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5419         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5420         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5421         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5422         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5423         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5424         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5425         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5426         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5427         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5428         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5429         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5430         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5431         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5432         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5433         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5434         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5435         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5436         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5437         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5438         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5439         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5440         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5441         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5442         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5443         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5444         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5445         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5446         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5447         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5448         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5449         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5450         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5451         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5452         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5453         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5454         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5455         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5456         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5457         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5458         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5459         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5460         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5461         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5462         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5463         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5464         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5465         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5466         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5467         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5468         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5469         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5470         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5471         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5472         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5473         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5474         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5475         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5476         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5477         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5478         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5479         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5480         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5481         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5482         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5483         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5484         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5485         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5486         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5487         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5488         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5489         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5490         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5491         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5492         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5493         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5494         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5495         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5496         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5497         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5498         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5499         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5500         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5501         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5502         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5503         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5504         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5505         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5506         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5507         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5508         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5509         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5510         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5511         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5512         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5513         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5514         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5515         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5516         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5517         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5518         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5519         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5520         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5521         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5522         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5523         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5524         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5525         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5526         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5527         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5528         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5529         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5530         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5531         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5532         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5533         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5534         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5535         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5536         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5537         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5538         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5539         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5540         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5541         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5542         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5543         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5544         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5545         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5546         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5547         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5548         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5549         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5550         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5551         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5552         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5553         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5554         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5555         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5556         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5557         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5558         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5559         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5560         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5561         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5562         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5563         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5564         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5565         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5566         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5567         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5568         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5569         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5570         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5571         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5572         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5573         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5574         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5575         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5576         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5577         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5578         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5579         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5580         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5581         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5582         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5583         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5584         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5585         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5586         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5587         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5588         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5589         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5590         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5591         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5592         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5593         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5594         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5595         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5596         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5597         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5598         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5599         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5600         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5601         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5602         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5603         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5604         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5605         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5606         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5607         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5608         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5609         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5610         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5611         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5612         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5613         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5614         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5615         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5616         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5617         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5618         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5619         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5620         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5621         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5622         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5623         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5624         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5625         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5626         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5627         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5628         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5629         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5630         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5631         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5632         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5633         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5634         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5635         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5636         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5637         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5638         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5639         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5640         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5641         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5642         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5643         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5644         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5645         0x00822025, 0xaf645c38, 0x8f625