33569ec9dbfcbc891acc7bf2b0921039abac845a
[linux-3.10.git] / drivers / net / s2io.c
1 /************************************************************************
2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3  * Copyright(c) 2002-2005 Neterion Inc.
4
5  * This software may be used and distributed according to the terms of
6  * the GNU General Public License (GPL), incorporated herein by reference.
7  * Drivers based on or derived from this code fall under the GPL and must
8  * retain the authorship, copyright and license notice.  This file is not
9  * a complete program and may only be used when the entire operating
10  * system is licensed under the GPL.
11  * See the file COPYING in this distribution for more information.
12  *
13  * Credits:
14  * Jeff Garzik          : For pointing out the improper error condition
15  *                        check in the s2io_xmit routine and also some
16  *                        issues in the Tx watch dog function. Also for
17  *                        patiently answering all those innumerable
18  *                        questions regaring the 2.6 porting issues.
19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
20  *                        macros available only in 2.6 Kernel.
21  * Francois Romieu      : For pointing out all code part that were
22  *                        deprecated and also styling related comments.
23  * Grant Grundler       : For helping me get rid of some Architecture
24  *                        dependent code.
25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
26  *
27  * The module loadable parameters that are supported by the driver and a brief
28  * explaination of all the variables.
29  *
30  * rx_ring_num : This can be used to program the number of receive rings used
31  * in the driver.
32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
33  *     This is also an array of size 8.
34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35  *              values are 1, 2 and 3.
36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
38  * Tx descriptors that can be associated with each corresponding FIFO.
39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40  *     1(MSI), 2(MSI_X). Default value is '0(INTA)'
41  * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42  *     Possible values '1' for enable '0' for disable. Default is '0'
43  * lro_max_pkts: This parameter defines maximum number of packets can be
44  *     aggregated as a single large packet
45  ************************************************************************/
46
47 #include <linux/module.h>
48 #include <linux/types.h>
49 #include <linux/errno.h>
50 #include <linux/ioport.h>
51 #include <linux/pci.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/kernel.h>
54 #include <linux/netdevice.h>
55 #include <linux/etherdevice.h>
56 #include <linux/skbuff.h>
57 #include <linux/init.h>
58 #include <linux/delay.h>
59 #include <linux/stddef.h>
60 #include <linux/ioctl.h>
61 #include <linux/timex.h>
62 #include <linux/sched.h>
63 #include <linux/ethtool.h>
64 #include <linux/workqueue.h>
65 #include <linux/if_vlan.h>
66 #include <linux/ip.h>
67 #include <linux/tcp.h>
68 #include <net/tcp.h>
69
70 #include <asm/system.h>
71 #include <asm/uaccess.h>
72 #include <asm/io.h>
73 #include <asm/div64.h>
74 #include <asm/irq.h>
75
76 /* local include */
77 #include "s2io.h"
78 #include "s2io-regs.h"
79
80 #define DRV_VERSION "2.0.15.2"
81
82 /* S2io Driver name & version. */
83 static char s2io_driver_name[] = "Neterion";
84 static char s2io_driver_version[] = DRV_VERSION;
85
86 static int rxd_size[4] = {32,48,48,64};
87 static int rxd_count[4] = {127,85,85,63};
88
89 static inline int RXD_IS_UP2DT(RxD_t *rxdp)
90 {
91         int ret;
92
93         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
94                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
95
96         return ret;
97 }
98
99 /*
100  * Cards with following subsystem_id have a link state indication
101  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
102  * macro below identifies these cards given the subsystem_id.
103  */
104 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
105         (dev_type == XFRAME_I_DEVICE) ?                 \
106                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
107                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
108
109 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
110                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
111 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
112 #define PANIC   1
113 #define LOW     2
114 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
115 {
116         mac_info_t *mac_control;
117
118         mac_control = &sp->mac_control;
119         if (rxb_size <= rxd_count[sp->rxd_mode])
120                 return PANIC;
121         else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
122                 return  LOW;
123         return 0;
124 }
125
126 /* Ethtool related variables and Macros. */
127 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
128         "Register test\t(offline)",
129         "Eeprom test\t(offline)",
130         "Link test\t(online)",
131         "RLDRAM test\t(offline)",
132         "BIST Test\t(offline)"
133 };
134
135 static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
136         {"tmac_frms"},
137         {"tmac_data_octets"},
138         {"tmac_drop_frms"},
139         {"tmac_mcst_frms"},
140         {"tmac_bcst_frms"},
141         {"tmac_pause_ctrl_frms"},
142         {"tmac_ttl_octets"},
143         {"tmac_ucst_frms"},
144         {"tmac_nucst_frms"},
145         {"tmac_any_err_frms"},
146         {"tmac_ttl_less_fb_octets"},
147         {"tmac_vld_ip_octets"},
148         {"tmac_vld_ip"},
149         {"tmac_drop_ip"},
150         {"tmac_icmp"},
151         {"tmac_rst_tcp"},
152         {"tmac_tcp"},
153         {"tmac_udp"},
154         {"rmac_vld_frms"},
155         {"rmac_data_octets"},
156         {"rmac_fcs_err_frms"},
157         {"rmac_drop_frms"},
158         {"rmac_vld_mcst_frms"},
159         {"rmac_vld_bcst_frms"},
160         {"rmac_in_rng_len_err_frms"},
161         {"rmac_out_rng_len_err_frms"},
162         {"rmac_long_frms"},
163         {"rmac_pause_ctrl_frms"},
164         {"rmac_unsup_ctrl_frms"},
165         {"rmac_ttl_octets"},
166         {"rmac_accepted_ucst_frms"},
167         {"rmac_accepted_nucst_frms"},
168         {"rmac_discarded_frms"},
169         {"rmac_drop_events"},
170         {"rmac_ttl_less_fb_octets"},
171         {"rmac_ttl_frms"},
172         {"rmac_usized_frms"},
173         {"rmac_osized_frms"},
174         {"rmac_frag_frms"},
175         {"rmac_jabber_frms"},
176         {"rmac_ttl_64_frms"},
177         {"rmac_ttl_65_127_frms"},
178         {"rmac_ttl_128_255_frms"},
179         {"rmac_ttl_256_511_frms"},
180         {"rmac_ttl_512_1023_frms"},
181         {"rmac_ttl_1024_1518_frms"},
182         {"rmac_ip"},
183         {"rmac_ip_octets"},
184         {"rmac_hdr_err_ip"},
185         {"rmac_drop_ip"},
186         {"rmac_icmp"},
187         {"rmac_tcp"},
188         {"rmac_udp"},
189         {"rmac_err_drp_udp"},
190         {"rmac_xgmii_err_sym"},
191         {"rmac_frms_q0"},
192         {"rmac_frms_q1"},
193         {"rmac_frms_q2"},
194         {"rmac_frms_q3"},
195         {"rmac_frms_q4"},
196         {"rmac_frms_q5"},
197         {"rmac_frms_q6"},
198         {"rmac_frms_q7"},
199         {"rmac_full_q0"},
200         {"rmac_full_q1"},
201         {"rmac_full_q2"},
202         {"rmac_full_q3"},
203         {"rmac_full_q4"},
204         {"rmac_full_q5"},
205         {"rmac_full_q6"},
206         {"rmac_full_q7"},
207         {"rmac_pause_cnt"},
208         {"rmac_xgmii_data_err_cnt"},
209         {"rmac_xgmii_ctrl_err_cnt"},
210         {"rmac_accepted_ip"},
211         {"rmac_err_tcp"},
212         {"rd_req_cnt"},
213         {"new_rd_req_cnt"},
214         {"new_rd_req_rtry_cnt"},
215         {"rd_rtry_cnt"},
216         {"wr_rtry_rd_ack_cnt"},
217         {"wr_req_cnt"},
218         {"new_wr_req_cnt"},
219         {"new_wr_req_rtry_cnt"},
220         {"wr_rtry_cnt"},
221         {"wr_disc_cnt"},
222         {"rd_rtry_wr_ack_cnt"},
223         {"txp_wr_cnt"},
224         {"txd_rd_cnt"},
225         {"txd_wr_cnt"},
226         {"rxd_rd_cnt"},
227         {"rxd_wr_cnt"},
228         {"txf_rd_cnt"},
229         {"rxf_wr_cnt"},
230         {"rmac_ttl_1519_4095_frms"},
231         {"rmac_ttl_4096_8191_frms"},
232         {"rmac_ttl_8192_max_frms"},
233         {"rmac_ttl_gt_max_frms"},
234         {"rmac_osized_alt_frms"},
235         {"rmac_jabber_alt_frms"},
236         {"rmac_gt_max_alt_frms"},
237         {"rmac_vlan_frms"},
238         {"rmac_len_discard"},
239         {"rmac_fcs_discard"},
240         {"rmac_pf_discard"},
241         {"rmac_da_discard"},
242         {"rmac_red_discard"},
243         {"rmac_rts_discard"},
244         {"rmac_ingm_full_discard"},
245         {"link_fault_cnt"},
246         {"\n DRIVER STATISTICS"},
247         {"single_bit_ecc_errs"},
248         {"double_bit_ecc_errs"},
249         {"parity_err_cnt"},
250         {"serious_err_cnt"},
251         {"soft_reset_cnt"},
252         {"fifo_full_cnt"},
253         {"ring_full_cnt"},
254         ("alarm_transceiver_temp_high"),
255         ("alarm_transceiver_temp_low"),
256         ("alarm_laser_bias_current_high"),
257         ("alarm_laser_bias_current_low"),
258         ("alarm_laser_output_power_high"),
259         ("alarm_laser_output_power_low"),
260         ("warn_transceiver_temp_high"),
261         ("warn_transceiver_temp_low"),
262         ("warn_laser_bias_current_high"),
263         ("warn_laser_bias_current_low"),
264         ("warn_laser_output_power_high"),
265         ("warn_laser_output_power_low"),
266         ("lro_aggregated_pkts"),
267         ("lro_flush_both_count"),
268         ("lro_out_of_sequence_pkts"),
269         ("lro_flush_due_to_max_pkts"),
270         ("lro_avg_aggr_pkts"),
271 };
272
273 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
274 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
275
276 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
277 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
278
279 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
280                         init_timer(&timer);                     \
281                         timer.function = handle;                \
282                         timer.data = (unsigned long) arg;       \
283                         mod_timer(&timer, (jiffies + exp))      \
284
285 /* Add the vlan */
286 static void s2io_vlan_rx_register(struct net_device *dev,
287                                         struct vlan_group *grp)
288 {
289         nic_t *nic = dev->priv;
290         unsigned long flags;
291
292         spin_lock_irqsave(&nic->tx_lock, flags);
293         nic->vlgrp = grp;
294         spin_unlock_irqrestore(&nic->tx_lock, flags);
295 }
296
297 /* Unregister the vlan */
298 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
299 {
300         nic_t *nic = dev->priv;
301         unsigned long flags;
302
303         spin_lock_irqsave(&nic->tx_lock, flags);
304         if (nic->vlgrp)
305                 nic->vlgrp->vlan_devices[vid] = NULL;
306         spin_unlock_irqrestore(&nic->tx_lock, flags);
307 }
308
309 /*
310  * Constants to be programmed into the Xena's registers, to configure
311  * the XAUI.
312  */
313
314 #define END_SIGN        0x0
315 static const u64 herc_act_dtx_cfg[] = {
316         /* Set address */
317         0x8000051536750000ULL, 0x80000515367500E0ULL,
318         /* Write data */
319         0x8000051536750004ULL, 0x80000515367500E4ULL,
320         /* Set address */
321         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
322         /* Write data */
323         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
324         /* Set address */
325         0x801205150D440000ULL, 0x801205150D4400E0ULL,
326         /* Write data */
327         0x801205150D440004ULL, 0x801205150D4400E4ULL,
328         /* Set address */
329         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
330         /* Write data */
331         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
332         /* Done */
333         END_SIGN
334 };
335
336 static const u64 xena_dtx_cfg[] = {
337         /* Set address */
338         0x8000051500000000ULL, 0x80000515000000E0ULL,
339         /* Write data */
340         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
341         /* Set address */
342         0x8001051500000000ULL, 0x80010515000000E0ULL,
343         /* Write data */
344         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
345         /* Set address */
346         0x8002051500000000ULL, 0x80020515000000E0ULL,
347         /* Write data */
348         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
349         END_SIGN
350 };
351
352 /*
353  * Constants for Fixing the MacAddress problem seen mostly on
354  * Alpha machines.
355  */
356 static const u64 fix_mac[] = {
357         0x0060000000000000ULL, 0x0060600000000000ULL,
358         0x0040600000000000ULL, 0x0000600000000000ULL,
359         0x0020600000000000ULL, 0x0060600000000000ULL,
360         0x0020600000000000ULL, 0x0060600000000000ULL,
361         0x0020600000000000ULL, 0x0060600000000000ULL,
362         0x0020600000000000ULL, 0x0060600000000000ULL,
363         0x0020600000000000ULL, 0x0060600000000000ULL,
364         0x0020600000000000ULL, 0x0060600000000000ULL,
365         0x0020600000000000ULL, 0x0060600000000000ULL,
366         0x0020600000000000ULL, 0x0060600000000000ULL,
367         0x0020600000000000ULL, 0x0060600000000000ULL,
368         0x0020600000000000ULL, 0x0060600000000000ULL,
369         0x0020600000000000ULL, 0x0000600000000000ULL,
370         0x0040600000000000ULL, 0x0060600000000000ULL,
371         END_SIGN
372 };
373
374 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
375 MODULE_LICENSE("GPL");
376 MODULE_VERSION(DRV_VERSION);
377
378
379 /* Module Loadable parameters. */
380 S2IO_PARM_INT(tx_fifo_num, 1);
381 S2IO_PARM_INT(rx_ring_num, 1);
382
383
384 S2IO_PARM_INT(rx_ring_mode, 1);
385 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
386 S2IO_PARM_INT(rmac_pause_time, 0x100);
387 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
388 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
389 S2IO_PARM_INT(shared_splits, 0);
390 S2IO_PARM_INT(tmac_util_period, 5);
391 S2IO_PARM_INT(rmac_util_period, 5);
392 S2IO_PARM_INT(bimodal, 0);
393 S2IO_PARM_INT(l3l4hdr_size, 128);
394 /* Frequency of Rx desc syncs expressed as power of 2 */
395 S2IO_PARM_INT(rxsync_frequency, 3);
396 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
397 S2IO_PARM_INT(intr_type, 0);
398 /* Large receive offload feature */
399 S2IO_PARM_INT(lro, 0);
400 /* Max pkts to be aggregated by LRO at one time. If not specified,
401  * aggregation happens until we hit max IP pkt size(64K)
402  */
403 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
404 #ifndef CONFIG_S2IO_NAPI
405 S2IO_PARM_INT(indicate_max_pkts, 0);
406 #endif
407
408 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
409     {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
410 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
411     {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
412 static unsigned int rts_frm_len[MAX_RX_RINGS] =
413     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
414
415 module_param_array(tx_fifo_len, uint, NULL, 0);
416 module_param_array(rx_ring_sz, uint, NULL, 0);
417 module_param_array(rts_frm_len, uint, NULL, 0);
418
419 /*
420  * S2IO device table.
421  * This table lists all the devices that this driver supports.
422  */
423 static struct pci_device_id s2io_tbl[] __devinitdata = {
424         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
425          PCI_ANY_ID, PCI_ANY_ID},
426         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
427          PCI_ANY_ID, PCI_ANY_ID},
428         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
429          PCI_ANY_ID, PCI_ANY_ID},
430         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
431          PCI_ANY_ID, PCI_ANY_ID},
432         {0,}
433 };
434
435 MODULE_DEVICE_TABLE(pci, s2io_tbl);
436
437 static struct pci_driver s2io_driver = {
438       .name = "S2IO",
439       .id_table = s2io_tbl,
440       .probe = s2io_init_nic,
441       .remove = __devexit_p(s2io_rem_nic),
442 };
443
444 /* A simplifier macro used both by init and free shared_mem Fns(). */
445 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
446
447 /**
448  * init_shared_mem - Allocation and Initialization of Memory
449  * @nic: Device private variable.
450  * Description: The function allocates all the memory areas shared
451  * between the NIC and the driver. This includes Tx descriptors,
452  * Rx descriptors and the statistics block.
453  */
454
455 static int init_shared_mem(struct s2io_nic *nic)
456 {
457         u32 size;
458         void *tmp_v_addr, *tmp_v_addr_next;
459         dma_addr_t tmp_p_addr, tmp_p_addr_next;
460         RxD_block_t *pre_rxd_blk = NULL;
461         int i, j, blk_cnt, rx_sz, tx_sz;
462         int lst_size, lst_per_page;
463         struct net_device *dev = nic->dev;
464         unsigned long tmp;
465         buffAdd_t *ba;
466
467         mac_info_t *mac_control;
468         struct config_param *config;
469
470         mac_control = &nic->mac_control;
471         config = &nic->config;
472
473
474         /* Allocation and initialization of TXDLs in FIOFs */
475         size = 0;
476         for (i = 0; i < config->tx_fifo_num; i++) {
477                 size += config->tx_cfg[i].fifo_len;
478         }
479         if (size > MAX_AVAILABLE_TXDS) {
480                 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
481                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
482                 return -EINVAL;
483         }
484
485         lst_size = (sizeof(TxD_t) * config->max_txds);
486         tx_sz = lst_size * size;
487         lst_per_page = PAGE_SIZE / lst_size;
488
489         for (i = 0; i < config->tx_fifo_num; i++) {
490                 int fifo_len = config->tx_cfg[i].fifo_len;
491                 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
492                 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
493                                                           GFP_KERNEL);
494                 if (!mac_control->fifos[i].list_info) {
495                         DBG_PRINT(ERR_DBG,
496                                   "Malloc failed for list_info\n");
497                         return -ENOMEM;
498                 }
499                 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
500         }
501         for (i = 0; i < config->tx_fifo_num; i++) {
502                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
503                                                 lst_per_page);
504                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
505                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
506                     config->tx_cfg[i].fifo_len - 1;
507                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
508                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
509                     config->tx_cfg[i].fifo_len - 1;
510                 mac_control->fifos[i].fifo_no = i;
511                 mac_control->fifos[i].nic = nic;
512                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
513
514                 for (j = 0; j < page_num; j++) {
515                         int k = 0;
516                         dma_addr_t tmp_p;
517                         void *tmp_v;
518                         tmp_v = pci_alloc_consistent(nic->pdev,
519                                                      PAGE_SIZE, &tmp_p);
520                         if (!tmp_v) {
521                                 DBG_PRINT(ERR_DBG,
522                                           "pci_alloc_consistent ");
523                                 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
524                                 return -ENOMEM;
525                         }
526                         /* If we got a zero DMA address(can happen on
527                          * certain platforms like PPC), reallocate.
528                          * Store virtual address of page we don't want,
529                          * to be freed later.
530                          */
531                         if (!tmp_p) {
532                                 mac_control->zerodma_virt_addr = tmp_v;
533                                 DBG_PRINT(INIT_DBG,
534                                 "%s: Zero DMA address for TxDL. ", dev->name);
535                                 DBG_PRINT(INIT_DBG,
536                                 "Virtual address %p\n", tmp_v);
537                                 tmp_v = pci_alloc_consistent(nic->pdev,
538                                                      PAGE_SIZE, &tmp_p);
539                                 if (!tmp_v) {
540                                         DBG_PRINT(ERR_DBG,
541                                           "pci_alloc_consistent ");
542                                         DBG_PRINT(ERR_DBG, "failed for TxDL\n");
543                                         return -ENOMEM;
544                                 }
545                         }
546                         while (k < lst_per_page) {
547                                 int l = (j * lst_per_page) + k;
548                                 if (l == config->tx_cfg[i].fifo_len)
549                                         break;
550                                 mac_control->fifos[i].list_info[l].list_virt_addr =
551                                     tmp_v + (k * lst_size);
552                                 mac_control->fifos[i].list_info[l].list_phy_addr =
553                                     tmp_p + (k * lst_size);
554                                 k++;
555                         }
556                 }
557         }
558
559         nic->ufo_in_band_v = kmalloc((sizeof(u64) * size), GFP_KERNEL);
560         if (!nic->ufo_in_band_v)
561                 return -ENOMEM;
562         memset(nic->ufo_in_band_v, 0, size);
563
564         /* Allocation and initialization of RXDs in Rings */
565         size = 0;
566         for (i = 0; i < config->rx_ring_num; i++) {
567                 if (config->rx_cfg[i].num_rxd %
568                     (rxd_count[nic->rxd_mode] + 1)) {
569                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
570                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
571                                   i);
572                         DBG_PRINT(ERR_DBG, "RxDs per Block");
573                         return FAILURE;
574                 }
575                 size += config->rx_cfg[i].num_rxd;
576                 mac_control->rings[i].block_count =
577                         config->rx_cfg[i].num_rxd /
578                         (rxd_count[nic->rxd_mode] + 1 );
579                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
580                         mac_control->rings[i].block_count;
581         }
582         if (nic->rxd_mode == RXD_MODE_1)
583                 size = (size * (sizeof(RxD1_t)));
584         else
585                 size = (size * (sizeof(RxD3_t)));
586         rx_sz = size;
587
588         for (i = 0; i < config->rx_ring_num; i++) {
589                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
590                 mac_control->rings[i].rx_curr_get_info.offset = 0;
591                 mac_control->rings[i].rx_curr_get_info.ring_len =
592                     config->rx_cfg[i].num_rxd - 1;
593                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
594                 mac_control->rings[i].rx_curr_put_info.offset = 0;
595                 mac_control->rings[i].rx_curr_put_info.ring_len =
596                     config->rx_cfg[i].num_rxd - 1;
597                 mac_control->rings[i].nic = nic;
598                 mac_control->rings[i].ring_no = i;
599
600                 blk_cnt = config->rx_cfg[i].num_rxd /
601                                 (rxd_count[nic->rxd_mode] + 1);
602                 /*  Allocating all the Rx blocks */
603                 for (j = 0; j < blk_cnt; j++) {
604                         rx_block_info_t *rx_blocks;
605                         int l;
606
607                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
608                         size = SIZE_OF_BLOCK; //size is always page size
609                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
610                                                           &tmp_p_addr);
611                         if (tmp_v_addr == NULL) {
612                                 /*
613                                  * In case of failure, free_shared_mem()
614                                  * is called, which should free any
615                                  * memory that was alloced till the
616                                  * failure happened.
617                                  */
618                                 rx_blocks->block_virt_addr = tmp_v_addr;
619                                 return -ENOMEM;
620                         }
621                         memset(tmp_v_addr, 0, size);
622                         rx_blocks->block_virt_addr = tmp_v_addr;
623                         rx_blocks->block_dma_addr = tmp_p_addr;
624                         rx_blocks->rxds = kmalloc(sizeof(rxd_info_t)*
625                                                   rxd_count[nic->rxd_mode],
626                                                   GFP_KERNEL);
627                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
628                                 rx_blocks->rxds[l].virt_addr =
629                                         rx_blocks->block_virt_addr +
630                                         (rxd_size[nic->rxd_mode] * l);
631                                 rx_blocks->rxds[l].dma_addr =
632                                         rx_blocks->block_dma_addr +
633                                         (rxd_size[nic->rxd_mode] * l);
634                         }
635                 }
636                 /* Interlinking all Rx Blocks */
637                 for (j = 0; j < blk_cnt; j++) {
638                         tmp_v_addr =
639                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
640                         tmp_v_addr_next =
641                                 mac_control->rings[i].rx_blocks[(j + 1) %
642                                               blk_cnt].block_virt_addr;
643                         tmp_p_addr =
644                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
645                         tmp_p_addr_next =
646                                 mac_control->rings[i].rx_blocks[(j + 1) %
647                                               blk_cnt].block_dma_addr;
648
649                         pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
650                         pre_rxd_blk->reserved_2_pNext_RxD_block =
651                             (unsigned long) tmp_v_addr_next;
652                         pre_rxd_blk->pNext_RxD_Blk_physical =
653                             (u64) tmp_p_addr_next;
654                 }
655         }
656         if (nic->rxd_mode >= RXD_MODE_3A) {
657                 /*
658                  * Allocation of Storages for buffer addresses in 2BUFF mode
659                  * and the buffers as well.
660                  */
661                 for (i = 0; i < config->rx_ring_num; i++) {
662                         blk_cnt = config->rx_cfg[i].num_rxd /
663                            (rxd_count[nic->rxd_mode]+ 1);
664                         mac_control->rings[i].ba =
665                                 kmalloc((sizeof(buffAdd_t *) * blk_cnt),
666                                      GFP_KERNEL);
667                         if (!mac_control->rings[i].ba)
668                                 return -ENOMEM;
669                         for (j = 0; j < blk_cnt; j++) {
670                                 int k = 0;
671                                 mac_control->rings[i].ba[j] =
672                                         kmalloc((sizeof(buffAdd_t) *
673                                                 (rxd_count[nic->rxd_mode] + 1)),
674                                                 GFP_KERNEL);
675                                 if (!mac_control->rings[i].ba[j])
676                                         return -ENOMEM;
677                                 while (k != rxd_count[nic->rxd_mode]) {
678                                         ba = &mac_control->rings[i].ba[j][k];
679
680                                         ba->ba_0_org = (void *) kmalloc
681                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
682                                         if (!ba->ba_0_org)
683                                                 return -ENOMEM;
684                                         tmp = (unsigned long)ba->ba_0_org;
685                                         tmp += ALIGN_SIZE;
686                                         tmp &= ~((unsigned long) ALIGN_SIZE);
687                                         ba->ba_0 = (void *) tmp;
688
689                                         ba->ba_1_org = (void *) kmalloc
690                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
691                                         if (!ba->ba_1_org)
692                                                 return -ENOMEM;
693                                         tmp = (unsigned long) ba->ba_1_org;
694                                         tmp += ALIGN_SIZE;
695                                         tmp &= ~((unsigned long) ALIGN_SIZE);
696                                         ba->ba_1 = (void *) tmp;
697                                         k++;
698                                 }
699                         }
700                 }
701         }
702
703         /* Allocation and initialization of Statistics block */
704         size = sizeof(StatInfo_t);
705         mac_control->stats_mem = pci_alloc_consistent
706             (nic->pdev, size, &mac_control->stats_mem_phy);
707
708         if (!mac_control->stats_mem) {
709                 /*
710                  * In case of failure, free_shared_mem() is called, which
711                  * should free any memory that was alloced till the
712                  * failure happened.
713                  */
714                 return -ENOMEM;
715         }
716         mac_control->stats_mem_sz = size;
717
718         tmp_v_addr = mac_control->stats_mem;
719         mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
720         memset(tmp_v_addr, 0, size);
721         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
722                   (unsigned long long) tmp_p_addr);
723
724         return SUCCESS;
725 }
726
727 /**
728  * free_shared_mem - Free the allocated Memory
729  * @nic:  Device private variable.
730  * Description: This function is to free all memory locations allocated by
731  * the init_shared_mem() function and return it to the kernel.
732  */
733
734 static void free_shared_mem(struct s2io_nic *nic)
735 {
736         int i, j, blk_cnt, size;
737         void *tmp_v_addr;
738         dma_addr_t tmp_p_addr;
739         mac_info_t *mac_control;
740         struct config_param *config;
741         int lst_size, lst_per_page;
742         struct net_device *dev = nic->dev;
743
744         if (!nic)
745                 return;
746
747         mac_control = &nic->mac_control;
748         config = &nic->config;
749
750         lst_size = (sizeof(TxD_t) * config->max_txds);
751         lst_per_page = PAGE_SIZE / lst_size;
752
753         for (i = 0; i < config->tx_fifo_num; i++) {
754                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
755                                                 lst_per_page);
756                 for (j = 0; j < page_num; j++) {
757                         int mem_blks = (j * lst_per_page);
758                         if (!mac_control->fifos[i].list_info)
759                                 return;
760                         if (!mac_control->fifos[i].list_info[mem_blks].
761                                  list_virt_addr)
762                                 break;
763                         pci_free_consistent(nic->pdev, PAGE_SIZE,
764                                             mac_control->fifos[i].
765                                             list_info[mem_blks].
766                                             list_virt_addr,
767                                             mac_control->fifos[i].
768                                             list_info[mem_blks].
769                                             list_phy_addr);
770                 }
771                 /* If we got a zero DMA address during allocation,
772                  * free the page now
773                  */
774                 if (mac_control->zerodma_virt_addr) {
775                         pci_free_consistent(nic->pdev, PAGE_SIZE,
776                                             mac_control->zerodma_virt_addr,
777                                             (dma_addr_t)0);
778                         DBG_PRINT(INIT_DBG,
779                                 "%s: Freeing TxDL with zero DMA addr. ",
780                                 dev->name);
781                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
782                                 mac_control->zerodma_virt_addr);
783                 }
784                 kfree(mac_control->fifos[i].list_info);
785         }
786
787         size = SIZE_OF_BLOCK;
788         for (i = 0; i < config->rx_ring_num; i++) {
789                 blk_cnt = mac_control->rings[i].block_count;
790                 for (j = 0; j < blk_cnt; j++) {
791                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
792                                 block_virt_addr;
793                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
794                                 block_dma_addr;
795                         if (tmp_v_addr == NULL)
796                                 break;
797                         pci_free_consistent(nic->pdev, size,
798                                             tmp_v_addr, tmp_p_addr);
799                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
800                 }
801         }
802
803         if (nic->rxd_mode >= RXD_MODE_3A) {
804                 /* Freeing buffer storage addresses in 2BUFF mode. */
805                 for (i = 0; i < config->rx_ring_num; i++) {
806                         blk_cnt = config->rx_cfg[i].num_rxd /
807                             (rxd_count[nic->rxd_mode] + 1);
808                         for (j = 0; j < blk_cnt; j++) {
809                                 int k = 0;
810                                 if (!mac_control->rings[i].ba[j])
811                                         continue;
812                                 while (k != rxd_count[nic->rxd_mode]) {
813                                         buffAdd_t *ba =
814                                                 &mac_control->rings[i].ba[j][k];
815                                         kfree(ba->ba_0_org);
816                                         kfree(ba->ba_1_org);
817                                         k++;
818                                 }
819                                 kfree(mac_control->rings[i].ba[j]);
820                         }
821                         kfree(mac_control->rings[i].ba);
822                 }
823         }
824
825         if (mac_control->stats_mem) {
826                 pci_free_consistent(nic->pdev,
827                                     mac_control->stats_mem_sz,
828                                     mac_control->stats_mem,
829                                     mac_control->stats_mem_phy);
830         }
831         if (nic->ufo_in_band_v)
832                 kfree(nic->ufo_in_band_v);
833 }
834
835 /**
836  * s2io_verify_pci_mode -
837  */
838
839 static int s2io_verify_pci_mode(nic_t *nic)
840 {
841         XENA_dev_config_t __iomem *bar0 = nic->bar0;
842         register u64 val64 = 0;
843         int     mode;
844
845         val64 = readq(&bar0->pci_mode);
846         mode = (u8)GET_PCI_MODE(val64);
847
848         if ( val64 & PCI_MODE_UNKNOWN_MODE)
849                 return -1;      /* Unknown PCI mode */
850         return mode;
851 }
852
853 #define NEC_VENID   0x1033
854 #define NEC_DEVID   0x0125
855 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
856 {
857         struct pci_dev *tdev = NULL;
858         while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
859                 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
860                         if (tdev->bus == s2io_pdev->bus->parent)
861                                 pci_dev_put(tdev);
862                                 return 1;
863                 }
864         }
865         return 0;
866 }
867
868 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
869 /**
870  * s2io_print_pci_mode -
871  */
872 static int s2io_print_pci_mode(nic_t *nic)
873 {
874         XENA_dev_config_t __iomem *bar0 = nic->bar0;
875         register u64 val64 = 0;
876         int     mode;
877         struct config_param *config = &nic->config;
878
879         val64 = readq(&bar0->pci_mode);
880         mode = (u8)GET_PCI_MODE(val64);
881
882         if ( val64 & PCI_MODE_UNKNOWN_MODE)
883                 return -1;      /* Unknown PCI mode */
884
885         config->bus_speed = bus_speed[mode];
886
887         if (s2io_on_nec_bridge(nic->pdev)) {
888                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
889                                                         nic->dev->name);
890                 return mode;
891         }
892
893         if (val64 & PCI_MODE_32_BITS) {
894                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
895         } else {
896                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
897         }
898
899         switch(mode) {
900                 case PCI_MODE_PCI_33:
901                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
902                         break;
903                 case PCI_MODE_PCI_66:
904                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
905                         break;
906                 case PCI_MODE_PCIX_M1_66:
907                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
908                         break;
909                 case PCI_MODE_PCIX_M1_100:
910                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
911                         break;
912                 case PCI_MODE_PCIX_M1_133:
913                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
914                         break;
915                 case PCI_MODE_PCIX_M2_66:
916                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
917                         break;
918                 case PCI_MODE_PCIX_M2_100:
919                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
920                         break;
921                 case PCI_MODE_PCIX_M2_133:
922                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
923                         break;
924                 default:
925                         return -1;      /* Unsupported bus speed */
926         }
927
928         return mode;
929 }
930
931 /**
932  *  init_nic - Initialization of hardware
933  *  @nic: device peivate variable
934  *  Description: The function sequentially configures every block
935  *  of the H/W from their reset values.
936  *  Return Value:  SUCCESS on success and
937  *  '-1' on failure (endian settings incorrect).
938  */
939
940 static int init_nic(struct s2io_nic *nic)
941 {
942         XENA_dev_config_t __iomem *bar0 = nic->bar0;
943         struct net_device *dev = nic->dev;
944         register u64 val64 = 0;
945         void __iomem *add;
946         u32 time;
947         int i, j;
948         mac_info_t *mac_control;
949         struct config_param *config;
950         int dtx_cnt = 0;
951         unsigned long long mem_share;
952         int mem_size;
953
954         mac_control = &nic->mac_control;
955         config = &nic->config;
956
957         /* to set the swapper controle on the card */
958         if(s2io_set_swapper(nic)) {
959                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
960                 return -1;
961         }
962
963         /*
964          * Herc requires EOI to be removed from reset before XGXS, so..
965          */
966         if (nic->device_type & XFRAME_II_DEVICE) {
967                 val64 = 0xA500000000ULL;
968                 writeq(val64, &bar0->sw_reset);
969                 msleep(500);
970                 val64 = readq(&bar0->sw_reset);
971         }
972
973         /* Remove XGXS from reset state */
974         val64 = 0;
975         writeq(val64, &bar0->sw_reset);
976         msleep(500);
977         val64 = readq(&bar0->sw_reset);
978
979         /*  Enable Receiving broadcasts */
980         add = &bar0->mac_cfg;
981         val64 = readq(&bar0->mac_cfg);
982         val64 |= MAC_RMAC_BCAST_ENABLE;
983         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
984         writel((u32) val64, add);
985         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
986         writel((u32) (val64 >> 32), (add + 4));
987
988         /* Read registers in all blocks */
989         val64 = readq(&bar0->mac_int_mask);
990         val64 = readq(&bar0->mc_int_mask);
991         val64 = readq(&bar0->xgxs_int_mask);
992
993         /*  Set MTU */
994         val64 = dev->mtu;
995         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
996
997         if (nic->device_type & XFRAME_II_DEVICE) {
998                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
999                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1000                                           &bar0->dtx_control, UF);
1001                         if (dtx_cnt & 0x1)
1002                                 msleep(1); /* Necessary!! */
1003                         dtx_cnt++;
1004                 }
1005         } else {
1006                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1007                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1008                                           &bar0->dtx_control, UF);
1009                         val64 = readq(&bar0->dtx_control);
1010                         dtx_cnt++;
1011                 }
1012         }
1013
1014         /*  Tx DMA Initialization */
1015         val64 = 0;
1016         writeq(val64, &bar0->tx_fifo_partition_0);
1017         writeq(val64, &bar0->tx_fifo_partition_1);
1018         writeq(val64, &bar0->tx_fifo_partition_2);
1019         writeq(val64, &bar0->tx_fifo_partition_3);
1020
1021
1022         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1023                 val64 |=
1024                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1025                          13) | vBIT(config->tx_cfg[i].fifo_priority,
1026                                     ((i * 32) + 5), 3);
1027
1028                 if (i == (config->tx_fifo_num - 1)) {
1029                         if (i % 2 == 0)
1030                                 i++;
1031                 }
1032
1033                 switch (i) {
1034                 case 1:
1035                         writeq(val64, &bar0->tx_fifo_partition_0);
1036                         val64 = 0;
1037                         break;
1038                 case 3:
1039                         writeq(val64, &bar0->tx_fifo_partition_1);
1040                         val64 = 0;
1041                         break;
1042                 case 5:
1043                         writeq(val64, &bar0->tx_fifo_partition_2);
1044                         val64 = 0;
1045                         break;
1046                 case 7:
1047                         writeq(val64, &bar0->tx_fifo_partition_3);
1048                         break;
1049                 }
1050         }
1051
1052         /*
1053          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1054          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1055          */
1056         if ((nic->device_type == XFRAME_I_DEVICE) &&
1057                 (get_xena_rev_id(nic->pdev) < 4))
1058                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1059
1060         val64 = readq(&bar0->tx_fifo_partition_0);
1061         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1062                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1063
1064         /*
1065          * Initialization of Tx_PA_CONFIG register to ignore packet
1066          * integrity checking.
1067          */
1068         val64 = readq(&bar0->tx_pa_cfg);
1069         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1070             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1071         writeq(val64, &bar0->tx_pa_cfg);
1072
1073         /* Rx DMA intialization. */
1074         val64 = 0;
1075         for (i = 0; i < config->rx_ring_num; i++) {
1076                 val64 |=
1077                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1078                          3);
1079         }
1080         writeq(val64, &bar0->rx_queue_priority);
1081
1082         /*
1083          * Allocating equal share of memory to all the
1084          * configured Rings.
1085          */
1086         val64 = 0;
1087         if (nic->device_type & XFRAME_II_DEVICE)
1088                 mem_size = 32;
1089         else
1090                 mem_size = 64;
1091
1092         for (i = 0; i < config->rx_ring_num; i++) {
1093                 switch (i) {
1094                 case 0:
1095                         mem_share = (mem_size / config->rx_ring_num +
1096                                      mem_size % config->rx_ring_num);
1097                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1098                         continue;
1099                 case 1:
1100                         mem_share = (mem_size / config->rx_ring_num);
1101                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1102                         continue;
1103                 case 2:
1104                         mem_share = (mem_size / config->rx_ring_num);
1105                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1106                         continue;
1107                 case 3:
1108                         mem_share = (mem_size / config->rx_ring_num);
1109                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1110                         continue;
1111                 case 4:
1112                         mem_share = (mem_size / config->rx_ring_num);
1113                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1114                         continue;
1115                 case 5:
1116                         mem_share = (mem_size / config->rx_ring_num);
1117                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1118                         continue;
1119                 case 6:
1120                         mem_share = (mem_size / config->rx_ring_num);
1121                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1122                         continue;
1123                 case 7:
1124                         mem_share = (mem_size / config->rx_ring_num);
1125                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1126                         continue;
1127                 }
1128         }
1129         writeq(val64, &bar0->rx_queue_cfg);
1130
1131         /*
1132          * Filling Tx round robin registers
1133          * as per the number of FIFOs
1134          */
1135         switch (config->tx_fifo_num) {
1136         case 1:
1137                 val64 = 0x0000000000000000ULL;
1138                 writeq(val64, &bar0->tx_w_round_robin_0);
1139                 writeq(val64, &bar0->tx_w_round_robin_1);
1140                 writeq(val64, &bar0->tx_w_round_robin_2);
1141                 writeq(val64, &bar0->tx_w_round_robin_3);
1142                 writeq(val64, &bar0->tx_w_round_robin_4);
1143                 break;
1144         case 2:
1145                 val64 = 0x0000010000010000ULL;
1146                 writeq(val64, &bar0->tx_w_round_robin_0);
1147                 val64 = 0x0100000100000100ULL;
1148                 writeq(val64, &bar0->tx_w_round_robin_1);
1149                 val64 = 0x0001000001000001ULL;
1150                 writeq(val64, &bar0->tx_w_round_robin_2);
1151                 val64 = 0x0000010000010000ULL;
1152                 writeq(val64, &bar0->tx_w_round_robin_3);
1153                 val64 = 0x0100000000000000ULL;
1154                 writeq(val64, &bar0->tx_w_round_robin_4);
1155                 break;
1156         case 3:
1157                 val64 = 0x0001000102000001ULL;
1158                 writeq(val64, &bar0->tx_w_round_robin_0);
1159                 val64 = 0x0001020000010001ULL;
1160                 writeq(val64, &bar0->tx_w_round_robin_1);
1161                 val64 = 0x0200000100010200ULL;
1162                 writeq(val64, &bar0->tx_w_round_robin_2);
1163                 val64 = 0x0001000102000001ULL;
1164                 writeq(val64, &bar0->tx_w_round_robin_3);
1165                 val64 = 0x0001020000000000ULL;
1166                 writeq(val64, &bar0->tx_w_round_robin_4);
1167                 break;
1168         case 4:
1169                 val64 = 0x0001020300010200ULL;
1170                 writeq(val64, &bar0->tx_w_round_robin_0);
1171                 val64 = 0x0100000102030001ULL;
1172                 writeq(val64, &bar0->tx_w_round_robin_1);
1173                 val64 = 0x0200010000010203ULL;
1174                 writeq(val64, &bar0->tx_w_round_robin_2);
1175                 val64 = 0x0001020001000001ULL;
1176                 writeq(val64, &bar0->tx_w_round_robin_3);
1177                 val64 = 0x0203000100000000ULL;
1178                 writeq(val64, &bar0->tx_w_round_robin_4);
1179                 break;
1180         case 5:
1181                 val64 = 0x0001000203000102ULL;
1182                 writeq(val64, &bar0->tx_w_round_robin_0);
1183                 val64 = 0x0001020001030004ULL;
1184                 writeq(val64, &bar0->tx_w_round_robin_1);
1185                 val64 = 0x0001000203000102ULL;
1186                 writeq(val64, &bar0->tx_w_round_robin_2);
1187                 val64 = 0x0001020001030004ULL;
1188                 writeq(val64, &bar0->tx_w_round_robin_3);
1189                 val64 = 0x0001000000000000ULL;
1190                 writeq(val64, &bar0->tx_w_round_robin_4);
1191                 break;
1192         case 6:
1193                 val64 = 0x0001020304000102ULL;
1194                 writeq(val64, &bar0->tx_w_round_robin_0);
1195                 val64 = 0x0304050001020001ULL;
1196                 writeq(val64, &bar0->tx_w_round_robin_1);
1197                 val64 = 0x0203000100000102ULL;
1198                 writeq(val64, &bar0->tx_w_round_robin_2);
1199                 val64 = 0x0304000102030405ULL;
1200                 writeq(val64, &bar0->tx_w_round_robin_3);
1201                 val64 = 0x0001000200000000ULL;
1202                 writeq(val64, &bar0->tx_w_round_robin_4);
1203                 break;
1204         case 7:
1205                 val64 = 0x0001020001020300ULL;
1206                 writeq(val64, &bar0->tx_w_round_robin_0);
1207                 val64 = 0x0102030400010203ULL;
1208                 writeq(val64, &bar0->tx_w_round_robin_1);
1209                 val64 = 0x0405060001020001ULL;
1210                 writeq(val64, &bar0->tx_w_round_robin_2);
1211                 val64 = 0x0304050000010200ULL;
1212                 writeq(val64, &bar0->tx_w_round_robin_3);
1213                 val64 = 0x0102030000000000ULL;
1214                 writeq(val64, &bar0->tx_w_round_robin_4);
1215                 break;
1216         case 8:
1217                 val64 = 0x0001020300040105ULL;
1218                 writeq(val64, &bar0->tx_w_round_robin_0);
1219                 val64 = 0x0200030106000204ULL;
1220                 writeq(val64, &bar0->tx_w_round_robin_1);
1221                 val64 = 0x0103000502010007ULL;
1222                 writeq(val64, &bar0->tx_w_round_robin_2);
1223                 val64 = 0x0304010002060500ULL;
1224                 writeq(val64, &bar0->tx_w_round_robin_3);
1225                 val64 = 0x0103020400000000ULL;
1226                 writeq(val64, &bar0->tx_w_round_robin_4);
1227                 break;
1228         }
1229
1230         /* Enable all configured Tx FIFO partitions */
1231         val64 = readq(&bar0->tx_fifo_partition_0);
1232         val64 |= (TX_FIFO_PARTITION_EN);
1233         writeq(val64, &bar0->tx_fifo_partition_0);
1234
1235         /* Filling the Rx round robin registers as per the
1236          * number of Rings and steering based on QoS.
1237          */
1238         switch (config->rx_ring_num) {
1239         case 1:
1240                 val64 = 0x8080808080808080ULL;
1241                 writeq(val64, &bar0->rts_qos_steering);
1242                 break;
1243         case 2:
1244                 val64 = 0x0000010000010000ULL;
1245                 writeq(val64, &bar0->rx_w_round_robin_0);
1246                 val64 = 0x0100000100000100ULL;
1247                 writeq(val64, &bar0->rx_w_round_robin_1);
1248                 val64 = 0x0001000001000001ULL;
1249                 writeq(val64, &bar0->rx_w_round_robin_2);
1250                 val64 = 0x0000010000010000ULL;
1251                 writeq(val64, &bar0->rx_w_round_robin_3);
1252                 val64 = 0x0100000000000000ULL;
1253                 writeq(val64, &bar0->rx_w_round_robin_4);
1254
1255                 val64 = 0x8080808040404040ULL;
1256                 writeq(val64, &bar0->rts_qos_steering);
1257                 break;
1258         case 3:
1259                 val64 = 0x0001000102000001ULL;
1260                 writeq(val64, &bar0->rx_w_round_robin_0);
1261                 val64 = 0x0001020000010001ULL;
1262                 writeq(val64, &bar0->rx_w_round_robin_1);
1263                 val64 = 0x0200000100010200ULL;
1264                 writeq(val64, &bar0->rx_w_round_robin_2);
1265                 val64 = 0x0001000102000001ULL;
1266                 writeq(val64, &bar0->rx_w_round_robin_3);
1267                 val64 = 0x0001020000000000ULL;
1268                 writeq(val64, &bar0->rx_w_round_robin_4);
1269
1270                 val64 = 0x8080804040402020ULL;
1271                 writeq(val64, &bar0->rts_qos_steering);
1272                 break;
1273         case 4:
1274                 val64 = 0x0001020300010200ULL;
1275                 writeq(val64, &bar0->rx_w_round_robin_0);
1276                 val64 = 0x0100000102030001ULL;
1277                 writeq(val64, &bar0->rx_w_round_robin_1);
1278                 val64 = 0x0200010000010203ULL;
1279                 writeq(val64, &bar0->rx_w_round_robin_2);
1280                 val64 = 0x0001020001000001ULL;
1281                 writeq(val64, &bar0->rx_w_round_robin_3);
1282                 val64 = 0x0203000100000000ULL;
1283                 writeq(val64, &bar0->rx_w_round_robin_4);
1284
1285                 val64 = 0x8080404020201010ULL;
1286                 writeq(val64, &bar0->rts_qos_steering);
1287                 break;
1288         case 5:
1289                 val64 = 0x0001000203000102ULL;
1290                 writeq(val64, &bar0->rx_w_round_robin_0);
1291                 val64 = 0x0001020001030004ULL;
1292                 writeq(val64, &bar0->rx_w_round_robin_1);
1293                 val64 = 0x0001000203000102ULL;
1294                 writeq(val64, &bar0->rx_w_round_robin_2);
1295                 val64 = 0x0001020001030004ULL;
1296                 writeq(val64, &bar0->rx_w_round_robin_3);
1297                 val64 = 0x0001000000000000ULL;
1298                 writeq(val64, &bar0->rx_w_round_robin_4);
1299
1300                 val64 = 0x8080404020201008ULL;
1301                 writeq(val64, &bar0->rts_qos_steering);
1302                 break;
1303         case 6:
1304                 val64 = 0x0001020304000102ULL;
1305                 writeq(val64, &bar0->rx_w_round_robin_0);
1306                 val64 = 0x0304050001020001ULL;
1307                 writeq(val64, &bar0->rx_w_round_robin_1);
1308                 val64 = 0x0203000100000102ULL;
1309                 writeq(val64, &bar0->rx_w_round_robin_2);
1310                 val64 = 0x0304000102030405ULL;
1311                 writeq(val64, &bar0->rx_w_round_robin_3);
1312                 val64 = 0x0001000200000000ULL;
1313                 writeq(val64, &bar0->rx_w_round_robin_4);
1314
1315                 val64 = 0x8080404020100804ULL;
1316                 writeq(val64, &bar0->rts_qos_steering);
1317                 break;
1318         case 7:
1319                 val64 = 0x0001020001020300ULL;
1320                 writeq(val64, &bar0->rx_w_round_robin_0);
1321                 val64 = 0x0102030400010203ULL;
1322                 writeq(val64, &bar0->rx_w_round_robin_1);
1323                 val64 = 0x0405060001020001ULL;
1324                 writeq(val64, &bar0->rx_w_round_robin_2);
1325                 val64 = 0x0304050000010200ULL;
1326                 writeq(val64, &bar0->rx_w_round_robin_3);
1327                 val64 = 0x0102030000000000ULL;
1328                 writeq(val64, &bar0->rx_w_round_robin_4);
1329
1330                 val64 = 0x8080402010080402ULL;
1331                 writeq(val64, &bar0->rts_qos_steering);
1332                 break;
1333         case 8:
1334                 val64 = 0x0001020300040105ULL;
1335                 writeq(val64, &bar0->rx_w_round_robin_0);
1336                 val64 = 0x0200030106000204ULL;
1337                 writeq(val64, &bar0->rx_w_round_robin_1);
1338                 val64 = 0x0103000502010007ULL;
1339                 writeq(val64, &bar0->rx_w_round_robin_2);
1340                 val64 = 0x0304010002060500ULL;
1341                 writeq(val64, &bar0->rx_w_round_robin_3);
1342                 val64 = 0x0103020400000000ULL;
1343                 writeq(val64, &bar0->rx_w_round_robin_4);
1344
1345                 val64 = 0x8040201008040201ULL;
1346                 writeq(val64, &bar0->rts_qos_steering);
1347                 break;
1348         }
1349
1350         /* UDP Fix */
1351         val64 = 0;
1352         for (i = 0; i < 8; i++)
1353                 writeq(val64, &bar0->rts_frm_len_n[i]);
1354
1355         /* Set the default rts frame length for the rings configured */
1356         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1357         for (i = 0 ; i < config->rx_ring_num ; i++)
1358                 writeq(val64, &bar0->rts_frm_len_n[i]);
1359
1360         /* Set the frame length for the configured rings
1361          * desired by the user
1362          */
1363         for (i = 0; i < config->rx_ring_num; i++) {
1364                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1365                  * specified frame length steering.
1366                  * If the user provides the frame length then program
1367                  * the rts_frm_len register for those values or else
1368                  * leave it as it is.
1369                  */
1370                 if (rts_frm_len[i] != 0) {
1371                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1372                                 &bar0->rts_frm_len_n[i]);
1373                 }
1374         }
1375
1376         /* Program statistics memory */
1377         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1378
1379         if (nic->device_type == XFRAME_II_DEVICE) {
1380                 val64 = STAT_BC(0x320);
1381                 writeq(val64, &bar0->stat_byte_cnt);
1382         }
1383
1384         /*
1385          * Initializing the sampling rate for the device to calculate the
1386          * bandwidth utilization.
1387          */
1388         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1389             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1390         writeq(val64, &bar0->mac_link_util);
1391
1392
1393         /*
1394          * Initializing the Transmit and Receive Traffic Interrupt
1395          * Scheme.
1396          */
1397         /*
1398          * TTI Initialization. Default Tx timer gets us about
1399          * 250 interrupts per sec. Continuous interrupts are enabled
1400          * by default.
1401          */
1402         if (nic->device_type == XFRAME_II_DEVICE) {
1403                 int count = (nic->config.bus_speed * 125)/2;
1404                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1405         } else {
1406
1407                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1408         }
1409         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1410             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1411             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1412                 if (use_continuous_tx_intrs)
1413                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1414         writeq(val64, &bar0->tti_data1_mem);
1415
1416         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1417             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1418             TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1419         writeq(val64, &bar0->tti_data2_mem);
1420
1421         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1422         writeq(val64, &bar0->tti_command_mem);
1423
1424         /*
1425          * Once the operation completes, the Strobe bit of the command
1426          * register will be reset. We poll for this particular condition
1427          * We wait for a maximum of 500ms for the operation to complete,
1428          * if it's not complete by then we return error.
1429          */
1430         time = 0;
1431         while (TRUE) {
1432                 val64 = readq(&bar0->tti_command_mem);
1433                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1434                         break;
1435                 }
1436                 if (time > 10) {
1437                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1438                                   dev->name);
1439                         return -1;
1440                 }
1441                 msleep(50);
1442                 time++;
1443         }
1444
1445         if (nic->config.bimodal) {
1446                 int k = 0;
1447                 for (k = 0; k < config->rx_ring_num; k++) {
1448                         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1449                         val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1450                         writeq(val64, &bar0->tti_command_mem);
1451
1452                 /*
1453                  * Once the operation completes, the Strobe bit of the command
1454                  * register will be reset. We poll for this particular condition
1455                  * We wait for a maximum of 500ms for the operation to complete,
1456                  * if it's not complete by then we return error.
1457                 */
1458                         time = 0;
1459                         while (TRUE) {
1460                                 val64 = readq(&bar0->tti_command_mem);
1461                                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1462                                         break;
1463                                 }
1464                                 if (time > 10) {
1465                                         DBG_PRINT(ERR_DBG,
1466                                                 "%s: TTI init Failed\n",
1467                                         dev->name);
1468                                         return -1;
1469                                 }
1470                                 time++;
1471                                 msleep(50);
1472                         }
1473                 }
1474         } else {
1475
1476                 /* RTI Initialization */
1477                 if (nic->device_type == XFRAME_II_DEVICE) {
1478                         /*
1479                          * Programmed to generate Apprx 500 Intrs per
1480                          * second
1481                          */
1482                         int count = (nic->config.bus_speed * 125)/4;
1483                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1484                 } else {
1485                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1486                 }
1487                 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1488                     RTI_DATA1_MEM_RX_URNG_B(0x10) |
1489                     RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1490
1491                 writeq(val64, &bar0->rti_data1_mem);
1492
1493                 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1494                     RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1495                 if (nic->intr_type == MSI_X)
1496                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1497                                 RTI_DATA2_MEM_RX_UFC_D(0x40));
1498                 else
1499                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1500                                 RTI_DATA2_MEM_RX_UFC_D(0x80));
1501                 writeq(val64, &bar0->rti_data2_mem);
1502
1503                 for (i = 0; i < config->rx_ring_num; i++) {
1504                         val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1505                                         | RTI_CMD_MEM_OFFSET(i);
1506                         writeq(val64, &bar0->rti_command_mem);
1507
1508                         /*
1509                          * Once the operation completes, the Strobe bit of the
1510                          * command register will be reset. We poll for this
1511                          * particular condition. We wait for a maximum of 500ms
1512                          * for the operation to complete, if it's not complete
1513                          * by then we return error.
1514                          */
1515                         time = 0;
1516                         while (TRUE) {
1517                                 val64 = readq(&bar0->rti_command_mem);
1518                                 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1519                                         break;
1520                                 }
1521                                 if (time > 10) {
1522                                         DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1523                                                   dev->name);
1524                                         return -1;
1525                                 }
1526                                 time++;
1527                                 msleep(50);
1528                         }
1529                 }
1530         }
1531
1532         /*
1533          * Initializing proper values as Pause threshold into all
1534          * the 8 Queues on Rx side.
1535          */
1536         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1537         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1538
1539         /* Disable RMAC PAD STRIPPING */
1540         add = &bar0->mac_cfg;
1541         val64 = readq(&bar0->mac_cfg);
1542         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1543         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1544         writel((u32) (val64), add);
1545         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1546         writel((u32) (val64 >> 32), (add + 4));
1547         val64 = readq(&bar0->mac_cfg);
1548
1549         /* Enable FCS stripping by adapter */
1550         add = &bar0->mac_cfg;
1551         val64 = readq(&bar0->mac_cfg);
1552         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1553         if (nic->device_type == XFRAME_II_DEVICE)
1554                 writeq(val64, &bar0->mac_cfg);
1555         else {
1556                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1557                 writel((u32) (val64), add);
1558                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1559                 writel((u32) (val64 >> 32), (add + 4));
1560         }
1561
1562         /*
1563          * Set the time value to be inserted in the pause frame
1564          * generated by xena.
1565          */
1566         val64 = readq(&bar0->rmac_pause_cfg);
1567         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1568         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1569         writeq(val64, &bar0->rmac_pause_cfg);
1570
1571         /*
1572          * Set the Threshold Limit for Generating the pause frame
1573          * If the amount of data in any Queue exceeds ratio of
1574          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1575          * pause frame is generated
1576          */
1577         val64 = 0;
1578         for (i = 0; i < 4; i++) {
1579                 val64 |=
1580                     (((u64) 0xFF00 | nic->mac_control.
1581                       mc_pause_threshold_q0q3)
1582                      << (i * 2 * 8));
1583         }
1584         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1585
1586         val64 = 0;
1587         for (i = 0; i < 4; i++) {
1588                 val64 |=
1589                     (((u64) 0xFF00 | nic->mac_control.
1590                       mc_pause_threshold_q4q7)
1591                      << (i * 2 * 8));
1592         }
1593         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1594
1595         /*
1596          * TxDMA will stop Read request if the number of read split has
1597          * exceeded the limit pointed by shared_splits
1598          */
1599         val64 = readq(&bar0->pic_control);
1600         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1601         writeq(val64, &bar0->pic_control);
1602
1603         if (nic->config.bus_speed == 266) {
1604                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1605                 writeq(0x0, &bar0->read_retry_delay);
1606                 writeq(0x0, &bar0->write_retry_delay);
1607         }
1608
1609         /*
1610          * Programming the Herc to split every write transaction
1611          * that does not start on an ADB to reduce disconnects.
1612          */
1613         if (nic->device_type == XFRAME_II_DEVICE) {
1614                 val64 = EXT_REQ_EN | MISC_LINK_STABILITY_PRD(3);
1615                 writeq(val64, &bar0->misc_control);
1616                 val64 = readq(&bar0->pic_control2);
1617                 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1618                 writeq(val64, &bar0->pic_control2);
1619         }
1620         if (strstr(nic->product_name, "CX4")) {
1621                 val64 = TMAC_AVG_IPG(0x17);
1622                 writeq(val64, &bar0->tmac_avg_ipg);
1623         }
1624
1625         return SUCCESS;
1626 }
1627 #define LINK_UP_DOWN_INTERRUPT          1
1628 #define MAC_RMAC_ERR_TIMER              2
1629
1630 static int s2io_link_fault_indication(nic_t *nic)
1631 {
1632         if (nic->intr_type != INTA)
1633                 return MAC_RMAC_ERR_TIMER;
1634         if (nic->device_type == XFRAME_II_DEVICE)
1635                 return LINK_UP_DOWN_INTERRUPT;
1636         else
1637                 return MAC_RMAC_ERR_TIMER;
1638 }
1639
1640 /**
1641  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1642  *  @nic: device private variable,
1643  *  @mask: A mask indicating which Intr block must be modified and,
1644  *  @flag: A flag indicating whether to enable or disable the Intrs.
1645  *  Description: This function will either disable or enable the interrupts
1646  *  depending on the flag argument. The mask argument can be used to
1647  *  enable/disable any Intr block.
1648  *  Return Value: NONE.
1649  */
1650
1651 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1652 {
1653         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1654         register u64 val64 = 0, temp64 = 0;
1655
1656         /*  Top level interrupt classification */
1657         /*  PIC Interrupts */
1658         if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1659                 /*  Enable PIC Intrs in the general intr mask register */
1660                 val64 = TXPIC_INT_M | PIC_RX_INT_M;
1661                 if (flag == ENABLE_INTRS) {
1662                         temp64 = readq(&bar0->general_int_mask);
1663                         temp64 &= ~((u64) val64);
1664                         writeq(temp64, &bar0->general_int_mask);
1665                         /*
1666                          * If Hercules adapter enable GPIO otherwise
1667                          * disable all PCIX, Flash, MDIO, IIC and GPIO
1668                          * interrupts for now.
1669                          * TODO
1670                          */
1671                         if (s2io_link_fault_indication(nic) ==
1672                                         LINK_UP_DOWN_INTERRUPT ) {
1673                                 temp64 = readq(&bar0->pic_int_mask);
1674                                 temp64 &= ~((u64) PIC_INT_GPIO);
1675                                 writeq(temp64, &bar0->pic_int_mask);
1676                                 temp64 = readq(&bar0->gpio_int_mask);
1677                                 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1678                                 writeq(temp64, &bar0->gpio_int_mask);
1679                         } else {
1680                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1681                         }
1682                         /*
1683                          * No MSI Support is available presently, so TTI and
1684                          * RTI interrupts are also disabled.
1685                          */
1686                 } else if (flag == DISABLE_INTRS) {
1687                         /*
1688                          * Disable PIC Intrs in the general
1689                          * intr mask register
1690                          */
1691                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1692                         temp64 = readq(&bar0->general_int_mask);
1693                         val64 |= temp64;
1694                         writeq(val64, &bar0->general_int_mask);
1695                 }
1696         }
1697
1698         /*  DMA Interrupts */
1699         /*  Enabling/Disabling Tx DMA interrupts */
1700         if (mask & TX_DMA_INTR) {
1701                 /* Enable TxDMA Intrs in the general intr mask register */
1702                 val64 = TXDMA_INT_M;
1703                 if (flag == ENABLE_INTRS) {
1704                         temp64 = readq(&bar0->general_int_mask);
1705                         temp64 &= ~((u64) val64);
1706                         writeq(temp64, &bar0->general_int_mask);
1707                         /*
1708                          * Keep all interrupts other than PFC interrupt
1709                          * and PCC interrupt disabled in DMA level.
1710                          */
1711                         val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1712                                                       TXDMA_PCC_INT_M);
1713                         writeq(val64, &bar0->txdma_int_mask);
1714                         /*
1715                          * Enable only the MISC error 1 interrupt in PFC block
1716                          */
1717                         val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1718                         writeq(val64, &bar0->pfc_err_mask);
1719                         /*
1720                          * Enable only the FB_ECC error interrupt in PCC block
1721                          */
1722                         val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1723                         writeq(val64, &bar0->pcc_err_mask);
1724                 } else if (flag == DISABLE_INTRS) {
1725                         /*
1726                          * Disable TxDMA Intrs in the general intr mask
1727                          * register
1728                          */
1729                         writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1730                         writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
1731                         temp64 = readq(&bar0->general_int_mask);
1732                         val64 |= temp64;
1733                         writeq(val64, &bar0->general_int_mask);
1734                 }
1735         }
1736
1737         /*  Enabling/Disabling Rx DMA interrupts */
1738         if (mask & RX_DMA_INTR) {
1739                 /*  Enable RxDMA Intrs in the general intr mask register */
1740                 val64 = RXDMA_INT_M;
1741                 if (flag == ENABLE_INTRS) {
1742                         temp64 = readq(&bar0->general_int_mask);
1743                         temp64 &= ~((u64) val64);
1744                         writeq(temp64, &bar0->general_int_mask);
1745                         /*
1746                          * All RxDMA block interrupts are disabled for now
1747                          * TODO
1748                          */
1749                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1750                 } else if (flag == DISABLE_INTRS) {
1751                         /*
1752                          * Disable RxDMA Intrs in the general intr mask
1753                          * register
1754                          */
1755                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1756                         temp64 = readq(&bar0->general_int_mask);
1757                         val64 |= temp64;
1758                         writeq(val64, &bar0->general_int_mask);
1759                 }
1760         }
1761
1762         /*  MAC Interrupts */
1763         /*  Enabling/Disabling MAC interrupts */
1764         if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1765                 val64 = TXMAC_INT_M | RXMAC_INT_M;
1766                 if (flag == ENABLE_INTRS) {
1767                         temp64 = readq(&bar0->general_int_mask);
1768                         temp64 &= ~((u64) val64);
1769                         writeq(temp64, &bar0->general_int_mask);
1770                         /*
1771                          * All MAC block error interrupts are disabled for now
1772                          * TODO
1773                          */
1774                 } else if (flag == DISABLE_INTRS) {
1775                         /*
1776                          * Disable MAC Intrs in the general intr mask register
1777                          */
1778                         writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1779                         writeq(DISABLE_ALL_INTRS,
1780                                &bar0->mac_rmac_err_mask);
1781
1782                         temp64 = readq(&bar0->general_int_mask);
1783                         val64 |= temp64;
1784                         writeq(val64, &bar0->general_int_mask);
1785                 }
1786         }
1787
1788         /*  XGXS Interrupts */
1789         if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
1790                 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
1791                 if (flag == ENABLE_INTRS) {
1792                         temp64 = readq(&bar0->general_int_mask);
1793                         temp64 &= ~((u64) val64);
1794                         writeq(temp64, &bar0->general_int_mask);
1795                         /*
1796                          * All XGXS block error interrupts are disabled for now
1797                          * TODO
1798                          */
1799                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1800                 } else if (flag == DISABLE_INTRS) {
1801                         /*
1802                          * Disable MC Intrs in the general intr mask register
1803                          */
1804                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1805                         temp64 = readq(&bar0->general_int_mask);
1806                         val64 |= temp64;
1807                         writeq(val64, &bar0->general_int_mask);
1808                 }
1809         }
1810
1811         /*  Memory Controller(MC) interrupts */
1812         if (mask & MC_INTR) {
1813                 val64 = MC_INT_M;
1814                 if (flag == ENABLE_INTRS) {
1815                         temp64 = readq(&bar0->general_int_mask);
1816                         temp64 &= ~((u64) val64);
1817                         writeq(temp64, &bar0->general_int_mask);
1818                         /*
1819                          * Enable all MC Intrs.
1820                          */
1821                         writeq(0x0, &bar0->mc_int_mask);
1822                         writeq(0x0, &bar0->mc_err_mask);
1823                 } else if (flag == DISABLE_INTRS) {
1824                         /*
1825                          * Disable MC Intrs in the general intr mask register
1826                          */
1827                         writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1828                         temp64 = readq(&bar0->general_int_mask);
1829                         val64 |= temp64;
1830                         writeq(val64, &bar0->general_int_mask);
1831                 }
1832         }
1833
1834
1835         /*  Tx traffic interrupts */
1836         if (mask & TX_TRAFFIC_INTR) {
1837                 val64 = TXTRAFFIC_INT_M;
1838                 if (flag == ENABLE_INTRS) {
1839                         temp64 = readq(&bar0->general_int_mask);
1840                         temp64 &= ~((u64) val64);
1841                         writeq(temp64, &bar0->general_int_mask);
1842                         /*
1843                          * Enable all the Tx side interrupts
1844                          * writing 0 Enables all 64 TX interrupt levels
1845                          */
1846                         writeq(0x0, &bar0->tx_traffic_mask);
1847                 } else if (flag == DISABLE_INTRS) {
1848                         /*
1849                          * Disable Tx Traffic Intrs in the general intr mask
1850                          * register.
1851                          */
1852                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1853                         temp64 = readq(&bar0->general_int_mask);
1854                         val64 |= temp64;
1855                         writeq(val64, &bar0->general_int_mask);
1856                 }
1857         }
1858
1859         /*  Rx traffic interrupts */
1860         if (mask & RX_TRAFFIC_INTR) {
1861                 val64 = RXTRAFFIC_INT_M;
1862                 if (flag == ENABLE_INTRS) {
1863                         temp64 = readq(&bar0->general_int_mask);
1864                         temp64 &= ~((u64) val64);
1865                         writeq(temp64, &bar0->general_int_mask);
1866                         /* writing 0 Enables all 8 RX interrupt levels */
1867                         writeq(0x0, &bar0->rx_traffic_mask);
1868                 } else if (flag == DISABLE_INTRS) {
1869                         /*
1870                          * Disable Rx Traffic Intrs in the general intr mask
1871                          * register.
1872                          */
1873                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1874                         temp64 = readq(&bar0->general_int_mask);
1875                         val64 |= temp64;
1876                         writeq(val64, &bar0->general_int_mask);
1877                 }
1878         }
1879 }
1880
1881 static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
1882 {
1883         int ret = 0;
1884
1885         if (flag == FALSE) {
1886                 if ((!herc && (rev_id >= 4)) || herc) {
1887                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1888                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1889                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1890                                 ret = 1;
1891                         }
1892                 }else {
1893                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1894                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1895                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1896                                 ret = 1;
1897                         }
1898                 }
1899         } else {
1900                 if ((!herc && (rev_id >= 4)) || herc) {
1901                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1902                              ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1903                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1904                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1905                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1906                                 ret = 1;
1907                         }
1908                 } else {
1909                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1910                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1911                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1912                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1913                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1914                                 ret = 1;
1915                         }
1916                 }
1917         }
1918
1919         return ret;
1920 }
1921 /**
1922  *  verify_xena_quiescence - Checks whether the H/W is ready
1923  *  @val64 :  Value read from adapter status register.
1924  *  @flag : indicates if the adapter enable bit was ever written once
1925  *  before.
1926  *  Description: Returns whether the H/W is ready to go or not. Depending
1927  *  on whether adapter enable bit was written or not the comparison
1928  *  differs and the calling function passes the input argument flag to
1929  *  indicate this.
1930  *  Return: 1 If xena is quiescence
1931  *          0 If Xena is not quiescence
1932  */
1933
1934 static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
1935 {
1936         int ret = 0, herc;
1937         u64 tmp64 = ~((u64) val64);
1938         int rev_id = get_xena_rev_id(sp->pdev);
1939
1940         herc = (sp->device_type == XFRAME_II_DEVICE);
1941         if (!
1942             (tmp64 &
1943              (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
1944               ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY |
1945               ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
1946               ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
1947               ADAPTER_STATUS_P_PLL_LOCK))) {
1948                 ret = check_prc_pcc_state(val64, flag, rev_id, herc);
1949         }
1950
1951         return ret;
1952 }
1953
1954 /**
1955  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
1956  * @sp: Pointer to device specifc structure
1957  * Description :
1958  * New procedure to clear mac address reading  problems on Alpha platforms
1959  *
1960  */
1961
1962 static void fix_mac_address(nic_t * sp)
1963 {
1964         XENA_dev_config_t __iomem *bar0 = sp->bar0;
1965         u64 val64;
1966         int i = 0;
1967
1968         while (fix_mac[i] != END_SIGN) {
1969                 writeq(fix_mac[i++], &bar0->gpio_control);
1970                 udelay(10);
1971                 val64 = readq(&bar0->gpio_control);
1972         }
1973 }
1974
1975 /**
1976  *  start_nic - Turns the device on
1977  *  @nic : device private variable.
1978  *  Description:
1979  *  This function actually turns the device on. Before this  function is
1980  *  called,all Registers are configured from their reset states
1981  *  and shared memory is allocated but the NIC is still quiescent. On
1982  *  calling this function, the device interrupts are cleared and the NIC is
1983  *  literally switched on by writing into the adapter control register.
1984  *  Return Value:
1985  *  SUCCESS on success and -1 on failure.
1986  */
1987
1988 static int start_nic(struct s2io_nic *nic)
1989 {
1990         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1991         struct net_device *dev = nic->dev;
1992         register u64 val64 = 0;
1993         u16 subid, i;
1994         mac_info_t *mac_control;
1995         struct config_param *config;
1996
1997         mac_control = &nic->mac_control;
1998         config = &nic->config;
1999
2000         /*  PRC Initialization and configuration */
2001         for (i = 0; i < config->rx_ring_num; i++) {
2002                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2003                        &bar0->prc_rxd0_n[i]);
2004
2005                 val64 = readq(&bar0->prc_ctrl_n[i]);
2006                 if (nic->config.bimodal)
2007                         val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
2008                 if (nic->rxd_mode == RXD_MODE_1)
2009                         val64 |= PRC_CTRL_RC_ENABLED;
2010                 else
2011                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2012                 if (nic->device_type == XFRAME_II_DEVICE)
2013                         val64 |= PRC_CTRL_GROUP_READS;
2014                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2015                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2016                 writeq(val64, &bar0->prc_ctrl_n[i]);
2017         }
2018
2019         if (nic->rxd_mode == RXD_MODE_3B) {
2020                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2021                 val64 = readq(&bar0->rx_pa_cfg);
2022                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2023                 writeq(val64, &bar0->rx_pa_cfg);
2024         }
2025
2026         /*
2027          * Enabling MC-RLDRAM. After enabling the device, we timeout
2028          * for around 100ms, which is approximately the time required
2029          * for the device to be ready for operation.
2030          */
2031         val64 = readq(&bar0->mc_rldram_mrs);
2032         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2033         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2034         val64 = readq(&bar0->mc_rldram_mrs);
2035
2036         msleep(100);    /* Delay by around 100 ms. */
2037
2038         /* Enabling ECC Protection. */
2039         val64 = readq(&bar0->adapter_control);
2040         val64 &= ~ADAPTER_ECC_EN;
2041         writeq(val64, &bar0->adapter_control);
2042
2043         /*
2044          * Clearing any possible Link state change interrupts that
2045          * could have popped up just before Enabling the card.
2046          */
2047         val64 = readq(&bar0->mac_rmac_err_reg);
2048         if (val64)
2049                 writeq(val64, &bar0->mac_rmac_err_reg);
2050
2051         /*
2052          * Verify if the device is ready to be enabled, if so enable
2053          * it.
2054          */
2055         val64 = readq(&bar0->adapter_status);
2056         if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
2057                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2058                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2059                           (unsigned long long) val64);
2060                 return FAILURE;
2061         }
2062
2063         /*
2064          * With some switches, link might be already up at this point.
2065          * Because of this weird behavior, when we enable laser,
2066          * we may not get link. We need to handle this. We cannot
2067          * figure out which switch is misbehaving. So we are forced to
2068          * make a global change.
2069          */
2070
2071         /* Enabling Laser. */
2072         val64 = readq(&bar0->adapter_control);
2073         val64 |= ADAPTER_EOI_TX_ON;
2074         writeq(val64, &bar0->adapter_control);
2075
2076         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2077                 /*
2078                  * Dont see link state interrupts initally on some switches,
2079                  * so directly scheduling the link state task here.
2080                  */
2081                 schedule_work(&nic->set_link_task);
2082         }
2083         /* SXE-002: Initialize link and activity LED */
2084         subid = nic->pdev->subsystem_device;
2085         if (((subid & 0xFF) >= 0x07) &&
2086             (nic->device_type == XFRAME_I_DEVICE)) {
2087                 val64 = readq(&bar0->gpio_control);
2088                 val64 |= 0x0000800000000000ULL;
2089                 writeq(val64, &bar0->gpio_control);
2090                 val64 = 0x0411040400000000ULL;
2091                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2092         }
2093
2094         return SUCCESS;
2095 }
2096 /**
2097  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2098  */
2099 static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, int get_off)
2100 {
2101         nic_t *nic = fifo_data->nic;
2102         struct sk_buff *skb;
2103         TxD_t *txds;
2104         u16 j, frg_cnt;
2105
2106         txds = txdlp;
2107         if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2108                 pci_unmap_single(nic->pdev, (dma_addr_t)
2109                         txds->Buffer_Pointer, sizeof(u64),
2110                         PCI_DMA_TODEVICE);
2111                 txds++;
2112         }
2113
2114         skb = (struct sk_buff *) ((unsigned long)
2115                         txds->Host_Control);
2116         if (!skb) {
2117                 memset(txdlp, 0, (sizeof(TxD_t) * fifo_data->max_txds));
2118                 return NULL;
2119         }
2120         pci_unmap_single(nic->pdev, (dma_addr_t)
2121                          txds->Buffer_Pointer,
2122                          skb->len - skb->data_len,
2123                          PCI_DMA_TODEVICE);
2124         frg_cnt = skb_shinfo(skb)->nr_frags;
2125         if (frg_cnt) {
2126                 txds++;
2127                 for (j = 0; j < frg_cnt; j++, txds++) {
2128                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2129                         if (!txds->Buffer_Pointer)
2130                                 break;
2131                         pci_unmap_page(nic->pdev, (dma_addr_t)
2132                                         txds->Buffer_Pointer,
2133                                        frag->size, PCI_DMA_TODEVICE);
2134                 }
2135         }
2136         memset(txdlp,0, (sizeof(TxD_t) * fifo_data->max_txds));
2137         return(skb);
2138 }
2139
2140 /**
2141  *  free_tx_buffers - Free all queued Tx buffers
2142  *  @nic : device private variable.
2143  *  Description:
2144  *  Free all queued Tx buffers.
2145  *  Return Value: void
2146 */
2147
2148 static void free_tx_buffers(struct s2io_nic *nic)
2149 {
2150         struct net_device *dev = nic->dev;
2151         struct sk_buff *skb;
2152         TxD_t *txdp;
2153         int i, j;
2154         mac_info_t *mac_control;
2155         struct config_param *config;
2156         int cnt = 0;
2157
2158         mac_control = &nic->mac_control;
2159         config = &nic->config;
2160
2161         for (i = 0; i < config->tx_fifo_num; i++) {
2162                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2163                         txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
2164                             list_virt_addr;
2165                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2166                         if (skb) {
2167                                 dev_kfree_skb(skb);
2168                                 cnt++;
2169                         }
2170                 }
2171                 DBG_PRINT(INTR_DBG,
2172                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2173                           dev->name, cnt, i);
2174                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2175                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2176         }
2177 }
2178
2179 /**
2180  *   stop_nic -  To stop the nic
2181  *   @nic ; device private variable.
2182  *   Description:
2183  *   This function does exactly the opposite of what the start_nic()
2184  *   function does. This function is called to stop the device.
2185  *   Return Value:
2186  *   void.
2187  */
2188
2189 static void stop_nic(struct s2io_nic *nic)
2190 {
2191         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2192         register u64 val64 = 0;
2193         u16 interruptible;
2194         mac_info_t *mac_control;
2195         struct config_param *config;
2196
2197         mac_control = &nic->mac_control;
2198         config = &nic->config;
2199
2200         /*  Disable all interrupts */
2201         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2202         interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2203         interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2204         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2205
2206         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2207         val64 = readq(&bar0->adapter_control);
2208         val64 &= ~(ADAPTER_CNTL_EN);
2209         writeq(val64, &bar0->adapter_control);
2210 }
2211
2212 static int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
2213 {
2214         struct net_device *dev = nic->dev;
2215         struct sk_buff *frag_list;
2216         void *tmp;
2217
2218         /* Buffer-1 receives L3/L4 headers */
2219         ((RxD3_t*)rxdp)->Buffer1_ptr = pci_map_single
2220                         (nic->pdev, skb->data, l3l4hdr_size + 4,
2221                         PCI_DMA_FROMDEVICE);
2222
2223         /* skb_shinfo(skb)->frag_list will have L4 data payload */
2224         skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2225         if (skb_shinfo(skb)->frag_list == NULL) {
2226                 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2227                 return -ENOMEM ;
2228         }
2229         frag_list = skb_shinfo(skb)->frag_list;
2230         frag_list->next = NULL;
2231         tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2232         frag_list->data = tmp;
2233         frag_list->tail = tmp;
2234
2235         /* Buffer-2 receives L4 data payload */
2236         ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2237                                 frag_list->data, dev->mtu,
2238                                 PCI_DMA_FROMDEVICE);
2239         rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2240         rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2241
2242         return SUCCESS;
2243 }
2244
2245 /**
2246  *  fill_rx_buffers - Allocates the Rx side skbs
2247  *  @nic:  device private variable
2248  *  @ring_no: ring number
2249  *  Description:
2250  *  The function allocates Rx side skbs and puts the physical
2251  *  address of these buffers into the RxD buffer pointers, so that the NIC
2252  *  can DMA the received frame into these locations.
2253  *  The NIC supports 3 receive modes, viz
2254  *  1. single buffer,
2255  *  2. three buffer and
2256  *  3. Five buffer modes.
2257  *  Each mode defines how many fragments the received frame will be split
2258  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2259  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2260  *  is split into 3 fragments. As of now only single buffer mode is
2261  *  supported.
2262  *   Return Value:
2263  *  SUCCESS on success or an appropriate -ve value on failure.
2264  */
2265
2266 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2267 {
2268         struct net_device *dev = nic->dev;
2269         struct sk_buff *skb;
2270         RxD_t *rxdp;
2271         int off, off1, size, block_no, block_no1;
2272         u32 alloc_tab = 0;
2273         u32 alloc_cnt;
2274         mac_info_t *mac_control;
2275         struct config_param *config;
2276         u64 tmp;
2277         buffAdd_t *ba;
2278 #ifndef CONFIG_S2IO_NAPI
2279         unsigned long flags;
2280 #endif
2281         RxD_t *first_rxdp = NULL;
2282
2283         mac_control = &nic->mac_control;
2284         config = &nic->config;
2285         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2286             atomic_read(&nic->rx_bufs_left[ring_no]);
2287
2288         block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2289         off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2290         while (alloc_tab < alloc_cnt) {
2291                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2292                     block_index;
2293                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2294
2295                 rxdp = mac_control->rings[ring_no].
2296                                 rx_blocks[block_no].rxds[off].virt_addr;
2297
2298                 if ((block_no == block_no1) && (off == off1) &&
2299                                         (rxdp->Host_Control)) {
2300                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2301                                   dev->name);
2302                         DBG_PRINT(INTR_DBG, " info equated\n");
2303                         goto end;
2304                 }
2305                 if (off && (off == rxd_count[nic->rxd_mode])) {
2306                         mac_control->rings[ring_no].rx_curr_put_info.
2307                             block_index++;
2308                         if (mac_control->rings[ring_no].rx_curr_put_info.
2309                             block_index == mac_control->rings[ring_no].
2310                                         block_count)
2311                                 mac_control->rings[ring_no].rx_curr_put_info.
2312                                         block_index = 0;
2313                         block_no = mac_control->rings[ring_no].
2314                                         rx_curr_put_info.block_index;
2315                         if (off == rxd_count[nic->rxd_mode])
2316                                 off = 0;
2317                         mac_control->rings[ring_no].rx_curr_put_info.
2318                                 offset = off;
2319                         rxdp = mac_control->rings[ring_no].
2320                                 rx_blocks[block_no].block_virt_addr;
2321                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2322                                   dev->name, rxdp);
2323                 }
2324 #ifndef CONFIG_S2IO_NAPI
2325                 spin_lock_irqsave(&nic->put_lock, flags);
2326                 mac_control->rings[ring_no].put_pos =
2327                     (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2328                 spin_unlock_irqrestore(&nic->put_lock, flags);
2329 #endif
2330                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2331                         ((nic->rxd_mode >= RXD_MODE_3A) &&
2332                                 (rxdp->Control_2 & BIT(0)))) {
2333                         mac_control->rings[ring_no].rx_curr_put_info.
2334                                         offset = off;
2335                         goto end;
2336                 }
2337                 /* calculate size of skb based on ring mode */
2338                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2339                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2340                 if (nic->rxd_mode == RXD_MODE_1)
2341                         size += NET_IP_ALIGN;
2342                 else if (nic->rxd_mode == RXD_MODE_3B)
2343                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2344                 else
2345                         size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
2346
2347                 /* allocate skb */
2348                 skb = dev_alloc_skb(size);
2349                 if(!skb) {
2350                         DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2351                         DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
2352                         if (first_rxdp) {
2353                                 wmb();
2354                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2355                         }
2356                         return -ENOMEM ;
2357                 }
2358                 if (nic->rxd_mode == RXD_MODE_1) {
2359                         /* 1 buffer mode - normal operation mode */
2360                         memset(rxdp, 0, sizeof(RxD1_t));
2361                         skb_reserve(skb, NET_IP_ALIGN);
2362                         ((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single
2363                             (nic->pdev, skb->data, size - NET_IP_ALIGN,
2364                                 PCI_DMA_FROMDEVICE);
2365                         rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2366
2367                 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2368                         /*
2369                          * 2 or 3 buffer mode -
2370                          * Both 2 buffer mode and 3 buffer mode provides 128
2371                          * byte aligned receive buffers.
2372                          *
2373                          * 3 buffer mode provides header separation where in
2374                          * skb->data will have L3/L4 headers where as
2375                          * skb_shinfo(skb)->frag_list will have the L4 data
2376                          * payload
2377                          */
2378
2379                         memset(rxdp, 0, sizeof(RxD3_t));
2380                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2381                         skb_reserve(skb, BUF0_LEN);
2382                         tmp = (u64)(unsigned long) skb->data;
2383                         tmp += ALIGN_SIZE;
2384                         tmp &= ~ALIGN_SIZE;
2385                         skb->data = (void *) (unsigned long)tmp;
2386                         skb->tail = (void *) (unsigned long)tmp;
2387
2388                         if (!(((RxD3_t*)rxdp)->Buffer0_ptr))
2389                                 ((RxD3_t*)rxdp)->Buffer0_ptr =
2390                                    pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2391                                            PCI_DMA_FROMDEVICE);
2392                         else
2393                                 pci_dma_sync_single_for_device(nic->pdev,
2394                                     (dma_addr_t) ((RxD3_t*)rxdp)->Buffer0_ptr,
2395                                     BUF0_LEN, PCI_DMA_FROMDEVICE);
2396                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2397                         if (nic->rxd_mode == RXD_MODE_3B) {
2398                                 /* Two buffer mode */
2399
2400                                 /*
2401                                  * Buffer2 will have L3/L4 header plus
2402                                  * L4 payload
2403                                  */
2404                                 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single
2405                                 (nic->pdev, skb->data, dev->mtu + 4,
2406                                                 PCI_DMA_FROMDEVICE);
2407
2408                                 /* Buffer-1 will be dummy buffer. Not used */
2409                                 if (!(((RxD3_t*)rxdp)->Buffer1_ptr)) {
2410                                         ((RxD3_t*)rxdp)->Buffer1_ptr =
2411                                                 pci_map_single(nic->pdev,
2412                                                 ba->ba_1, BUF1_LEN,
2413                                                 PCI_DMA_FROMDEVICE);
2414                                 }
2415                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2416                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2417                                                                 (dev->mtu + 4);
2418                         } else {
2419                                 /* 3 buffer mode */
2420                                 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2421                                         dev_kfree_skb_irq(skb);
2422                                         if (first_rxdp) {
2423                                                 wmb();
2424                                                 first_rxdp->Control_1 |=
2425                                                         RXD_OWN_XENA;
2426                                         }
2427                                         return -ENOMEM ;
2428                                 }
2429                         }
2430                         rxdp->Control_2 |= BIT(0);
2431                 }
2432                 rxdp->Host_Control = (unsigned long) (skb);
2433                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2434                         rxdp->Control_1 |= RXD_OWN_XENA;
2435                 off++;
2436                 if (off == (rxd_count[nic->rxd_mode] + 1))
2437                         off = 0;
2438                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2439
2440                 rxdp->Control_2 |= SET_RXD_MARKER;
2441                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2442                         if (first_rxdp) {
2443                                 wmb();
2444                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2445                         }
2446                         first_rxdp = rxdp;
2447                 }
2448                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2449                 alloc_tab++;
2450         }
2451
2452       end:
2453         /* Transfer ownership of first descriptor to adapter just before
2454          * exiting. Before that, use memory barrier so that ownership
2455          * and other fields are seen by adapter correctly.
2456          */
2457         if (first_rxdp) {
2458                 wmb();
2459                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2460         }
2461
2462         return SUCCESS;
2463 }
2464
2465 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2466 {
2467         struct net_device *dev = sp->dev;
2468         int j;
2469         struct sk_buff *skb;
2470         RxD_t *rxdp;
2471         mac_info_t *mac_control;
2472         buffAdd_t *ba;
2473
2474         mac_control = &sp->mac_control;
2475         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2476                 rxdp = mac_control->rings[ring_no].
2477                                 rx_blocks[blk].rxds[j].virt_addr;
2478                 skb = (struct sk_buff *)
2479                         ((unsigned long) rxdp->Host_Control);
2480                 if (!skb) {
2481                         continue;
2482                 }
2483                 if (sp->rxd_mode == RXD_MODE_1) {
2484                         pci_unmap_single(sp->pdev, (dma_addr_t)
2485                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2486                                  dev->mtu +
2487                                  HEADER_ETHERNET_II_802_3_SIZE
2488                                  + HEADER_802_2_SIZE +
2489                                  HEADER_SNAP_SIZE,
2490                                  PCI_DMA_FROMDEVICE);
2491                         memset(rxdp, 0, sizeof(RxD1_t));
2492                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2493                         ba = &mac_control->rings[ring_no].
2494                                 ba[blk][j];
2495                         pci_unmap_single(sp->pdev, (dma_addr_t)
2496                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2497                                  BUF0_LEN,
2498                                  PCI_DMA_FROMDEVICE);
2499                         pci_unmap_single(sp->pdev, (dma_addr_t)
2500                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2501                                  BUF1_LEN,
2502                                  PCI_DMA_FROMDEVICE);
2503                         pci_unmap_single(sp->pdev, (dma_addr_t)
2504                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2505                                  dev->mtu + 4,
2506                                  PCI_DMA_FROMDEVICE);
2507                         memset(rxdp, 0, sizeof(RxD3_t));
2508                 } else {
2509                         pci_unmap_single(sp->pdev, (dma_addr_t)
2510                                 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2511                                 PCI_DMA_FROMDEVICE);
2512                         pci_unmap_single(sp->pdev, (dma_addr_t)
2513                                 ((RxD3_t*)rxdp)->Buffer1_ptr,
2514                                 l3l4hdr_size + 4,
2515                                 PCI_DMA_FROMDEVICE);
2516                         pci_unmap_single(sp->pdev, (dma_addr_t)
2517                                 ((RxD3_t*)rxdp)->Buffer2_ptr, dev->mtu,
2518                                 PCI_DMA_FROMDEVICE);
2519                         memset(rxdp, 0, sizeof(RxD3_t));
2520                 }
2521                 dev_kfree_skb(skb);
2522                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2523         }
2524 }
2525
2526 /**
2527  *  free_rx_buffers - Frees all Rx buffers
2528  *  @sp: device private variable.
2529  *  Description:
2530  *  This function will free all Rx buffers allocated by host.
2531  *  Return Value:
2532  *  NONE.
2533  */
2534
2535 static void free_rx_buffers(struct s2io_nic *sp)
2536 {
2537         struct net_device *dev = sp->dev;
2538         int i, blk = 0, buf_cnt = 0;
2539         mac_info_t *mac_control;
2540         struct config_param *config;
2541
2542         mac_control = &sp->mac_control;
2543         config = &sp->config;
2544
2545         for (i = 0; i < config->rx_ring_num; i++) {
2546                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2547                         free_rxd_blk(sp,i,blk);
2548
2549                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2550                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2551                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2552                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2553                 atomic_set(&sp->rx_bufs_left[i], 0);
2554                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2555                           dev->name, buf_cnt, i);
2556         }
2557 }
2558
2559 /**
2560  * s2io_poll - Rx interrupt handler for NAPI support
2561  * @dev : pointer to the device structure.
2562  * @budget : The number of packets that were budgeted to be processed
2563  * during  one pass through the 'Poll" function.
2564  * Description:
2565  * Comes into picture only if NAPI support has been incorporated. It does
2566  * the same thing that rx_intr_handler does, but not in a interrupt context
2567  * also It will process only a given number of packets.
2568  * Return value:
2569  * 0 on success and 1 if there are No Rx packets to be processed.
2570  */
2571
2572 #if defined(CONFIG_S2IO_NAPI)
2573 static int s2io_poll(struct net_device *dev, int *budget)
2574 {
2575         nic_t *nic = dev->priv;
2576         int pkt_cnt = 0, org_pkts_to_process;
2577         mac_info_t *mac_control;
2578         struct config_param *config;
2579         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2580         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2581         int i;
2582
2583         atomic_inc(&nic->isr_cnt);
2584         mac_control = &nic->mac_control;
2585         config = &nic->config;
2586
2587         nic->pkts_to_process = *budget;
2588         if (nic->pkts_to_process > dev->quota)
2589                 nic->pkts_to_process = dev->quota;
2590         org_pkts_to_process = nic->pkts_to_process;
2591
2592         writeq(val64, &bar0->rx_traffic_int);
2593         val64 = readl(&bar0->rx_traffic_int);
2594
2595         for (i = 0; i < config->rx_ring_num; i++) {
2596                 rx_intr_handler(&mac_control->rings[i]);
2597                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2598                 if (!nic->pkts_to_process) {
2599                         /* Quota for the current iteration has been met */
2600                         goto no_rx;
2601                 }
2602         }
2603         if (!pkt_cnt)
2604                 pkt_cnt = 1;
2605
2606         dev->quota -= pkt_cnt;
2607         *budget -= pkt_cnt;
2608         netif_rx_complete(dev);
2609
2610         for (i = 0; i < config->rx_ring_num; i++) {
2611                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2612                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2613                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2614                         break;
2615                 }
2616         }
2617         /* Re enable the Rx interrupts. */
2618         writeq(0x0, &bar0->rx_traffic_mask);
2619         val64 = readl(&bar0->rx_traffic_mask);
2620         atomic_dec(&nic->isr_cnt);
2621         return 0;
2622
2623 no_rx:
2624         dev->quota -= pkt_cnt;
2625         *budget -= pkt_cnt;
2626
2627         for (i = 0; i < config->rx_ring_num; i++) {
2628                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2629                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2630                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2631                         break;
2632                 }
2633         }
2634         atomic_dec(&nic->isr_cnt);
2635         return 1;
2636 }
2637 #endif
2638
2639 #ifdef CONFIG_NET_POLL_CONTROLLER
2640 /**
2641  * s2io_netpoll - netpoll event handler entry point
2642  * @dev : pointer to the device structure.
2643  * Description:
2644  *      This function will be called by upper layer to check for events on the
2645  * interface in situations where interrupts are disabled. It is used for
2646  * specific in-kernel networking tasks, such as remote consoles and kernel
2647  * debugging over the network (example netdump in RedHat).
2648  */
2649 static void s2io_netpoll(struct net_device *dev)
2650 {
2651         nic_t *nic = dev->priv;
2652         mac_info_t *mac_control;
2653         struct config_param *config;
2654         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2655         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2656         int i;
2657
2658         disable_irq(dev->irq);
2659
2660         atomic_inc(&nic->isr_cnt);
2661         mac_control = &nic->mac_control;
2662         config = &nic->config;
2663
2664         writeq(val64, &bar0->rx_traffic_int);
2665         writeq(val64, &bar0->tx_traffic_int);
2666
2667         /* we need to free up the transmitted skbufs or else netpoll will
2668          * run out of skbs and will fail and eventually netpoll application such
2669          * as netdump will fail.
2670          */
2671         for (i = 0; i < config->tx_fifo_num; i++)
2672                 tx_intr_handler(&mac_control->fifos[i]);
2673
2674         /* check for received packet and indicate up to network */
2675         for (i = 0; i < config->rx_ring_num; i++)
2676                 rx_intr_handler(&mac_control->rings[i]);
2677
2678         for (i = 0; i < config->rx_ring_num; i++) {
2679                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2680                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2681                         DBG_PRINT(ERR_DBG, " in Rx Netpoll!!\n");
2682                         break;
2683                 }
2684         }
2685         atomic_dec(&nic->isr_cnt);
2686         enable_irq(dev->irq);
2687         return;
2688 }
2689 #endif
2690
2691 /**
2692  *  rx_intr_handler - Rx interrupt handler
2693  *  @nic: device private variable.
2694  *  Description:
2695  *  If the interrupt is because of a received frame or if the
2696  *  receive ring contains fresh as yet un-processed frames,this function is
2697  *  called. It picks out the RxD at which place the last Rx processing had
2698  *  stopped and sends the skb to the OSM's Rx handler and then increments
2699  *  the offset.
2700  *  Return Value:
2701  *  NONE.
2702  */
2703 static void rx_intr_handler(ring_info_t *ring_data)
2704 {
2705         nic_t *nic = ring_data->nic;
2706         struct net_device *dev = (struct net_device *) nic->dev;
2707         int get_block, put_block, put_offset;
2708         rx_curr_get_info_t get_info, put_info;
2709         RxD_t *rxdp;
2710         struct sk_buff *skb;
2711 #ifndef CONFIG_S2IO_NAPI
2712         int pkt_cnt = 0;
2713 #endif
2714         int i;
2715
2716         spin_lock(&nic->rx_lock);
2717         if (atomic_read(&nic->card_state) == CARD_DOWN) {
2718                 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2719                           __FUNCTION__, dev->name);
2720                 spin_unlock(&nic->rx_lock);
2721                 return;
2722         }
2723
2724         get_info = ring_data->rx_curr_get_info;
2725         get_block = get_info.block_index;
2726         put_info = ring_data->rx_curr_put_info;
2727         put_block = put_info.block_index;
2728         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2729 #ifndef CONFIG_S2IO_NAPI
2730         spin_lock(&nic->put_lock);
2731         put_offset = ring_data->put_pos;
2732         spin_unlock(&nic->put_lock);
2733 #else
2734         put_offset = (put_block * (rxd_count[nic->rxd_mode] + 1)) +
2735                 put_info.offset;
2736 #endif
2737         while (RXD_IS_UP2DT(rxdp)) {
2738                 /* If your are next to put index then it's FIFO full condition */
2739                 if ((get_block == put_block) &&
2740                     (get_info.offset + 1) == put_info.offset) {
2741                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
2742                         break;
2743                 }
2744                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2745                 if (skb == NULL) {
2746                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2747                                   dev->name);
2748                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2749                         spin_unlock(&nic->rx_lock);
2750                         return;
2751                 }
2752                 if (nic->rxd_mode == RXD_MODE_1) {
2753                         pci_unmap_single(nic->pdev, (dma_addr_t)
2754                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2755                                  dev->mtu +
2756                                  HEADER_ETHERNET_II_802_3_SIZE +
2757                                  HEADER_802_2_SIZE +
2758                                  HEADER_SNAP_SIZE,
2759                                  PCI_DMA_FROMDEVICE);
2760                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2761                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2762                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2763                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
2764                         pci_unmap_single(nic->pdev, (dma_addr_t)
2765                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2766                                  dev->mtu + 4,
2767                                  PCI_DMA_FROMDEVICE);
2768                 } else {
2769                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2770                                          ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2771                                          PCI_DMA_FROMDEVICE);
2772                         pci_unmap_single(nic->pdev, (dma_addr_t)
2773                                          ((RxD3_t*)rxdp)->Buffer1_ptr,
2774                                          l3l4hdr_size + 4,
2775                                          PCI_DMA_FROMDEVICE);
2776                         pci_unmap_single(nic->pdev, (dma_addr_t)
2777                                          ((RxD3_t*)rxdp)->Buffer2_ptr,
2778                                          dev->mtu, PCI_DMA_FROMDEVICE);
2779                 }
2780                 prefetch(skb->data);
2781                 rx_osm_handler(ring_data, rxdp);
2782                 get_info.offset++;
2783                 ring_data->rx_curr_get_info.offset = get_info.offset;
2784                 rxdp = ring_data->rx_blocks[get_block].
2785                                 rxds[get_info.offset].virt_addr;
2786                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2787                         get_info.offset = 0;
2788                         ring_data->rx_curr_get_info.offset = get_info.offset;
2789                         get_block++;
2790                         if (get_block == ring_data->block_count)
2791                                 get_block = 0;
2792                         ring_data->rx_curr_get_info.block_index = get_block;
2793                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2794                 }
2795
2796 #ifdef CONFIG_S2IO_NAPI
2797                 nic->pkts_to_process -= 1;
2798                 if (!nic->pkts_to_process)
2799                         break;
2800 #else
2801                 pkt_cnt++;
2802                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2803                         break;
2804 #endif
2805         }
2806         if (nic->lro) {
2807                 /* Clear all LRO sessions before exiting */
2808                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2809                         lro_t *lro = &nic->lro0_n[i];
2810                         if (lro->in_use) {
2811                                 update_L3L4_header(nic, lro);
2812                                 queue_rx_frame(lro->parent);
2813                                 clear_lro_session(lro);
2814                         }
2815                 }
2816         }
2817
2818         spin_unlock(&nic->rx_lock);
2819 }
2820
2821 /**
2822  *  tx_intr_handler - Transmit interrupt handler
2823  *  @nic : device private variable
2824  *  Description:
2825  *  If an interrupt was raised to indicate DMA complete of the
2826  *  Tx packet, this function is called. It identifies the last TxD
2827  *  whose buffer was freed and frees all skbs whose data have already
2828  *  DMA'ed into the NICs internal memory.
2829  *  Return Value:
2830  *  NONE
2831  */
2832
2833 static void tx_intr_handler(fifo_info_t *fifo_data)
2834 {
2835         nic_t *nic = fifo_data->nic;
2836         struct net_device *dev = (struct net_device *) nic->dev;
2837         tx_curr_get_info_t get_info, put_info;
2838         struct sk_buff *skb;
2839         TxD_t *txdlp;
2840
2841         get_info = fifo_data->tx_curr_get_info;
2842         put_info = fifo_data->tx_curr_put_info;
2843         txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2844             list_virt_addr;
2845         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2846                (get_info.offset != put_info.offset) &&
2847                (txdlp->Host_Control)) {
2848                 /* Check for TxD errors */
2849                 if (txdlp->Control_1 & TXD_T_CODE) {
2850                         unsigned long long err;
2851                         err = txdlp->Control_1 & TXD_T_CODE;
2852                         if (err & 0x1) {
2853                                 nic->mac_control.stats_info->sw_stat.
2854                                                 parity_err_cnt++;
2855                         }
2856                         if ((err >> 48) == 0xA) {
2857                                 DBG_PRINT(TX_DBG, "TxD returned due \
2858 to loss of link\n");
2859                         }
2860                         else {
2861                                 DBG_PRINT(ERR_DBG, "***TxD error \
2862 %llx\n", err);
2863                         }
2864                 }
2865
2866                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2867                 if (skb == NULL) {
2868                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
2869                         __FUNCTION__);
2870                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2871                         return;
2872                 }
2873
2874                 /* Updating the statistics block */
2875                 nic->stats.tx_bytes += skb->len;
2876                 dev_kfree_skb_irq(skb);
2877
2878                 get_info.offset++;
2879                 if (get_info.offset == get_info.fifo_len + 1)
2880                         get_info.offset = 0;
2881                 txdlp = (TxD_t *) fifo_data->list_info
2882                     [get_info.offset].list_virt_addr;
2883                 fifo_data->tx_curr_get_info.offset =
2884                     get_info.offset;
2885         }
2886
2887         spin_lock(&nic->tx_lock);
2888         if (netif_queue_stopped(dev))
2889                 netif_wake_queue(dev);
2890         spin_unlock(&nic->tx_lock);
2891 }
2892
2893 /**
2894  *  s2io_mdio_write - Function to write in to MDIO registers
2895  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2896  *  @addr     : address value
2897  *  @value    : data value
2898  *  @dev      : pointer to net_device structure
2899  *  Description:
2900  *  This function is used to write values to the MDIO registers
2901  *  NONE
2902  */
2903 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2904 {
2905         u64 val64 = 0x0;
2906         nic_t *sp = dev->priv;
2907         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2908
2909         //address transaction
2910         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2911                         | MDIO_MMD_DEV_ADDR(mmd_type)
2912                         | MDIO_MMS_PRT_ADDR(0x0);
2913         writeq(val64, &bar0->mdio_control);
2914         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2915         writeq(val64, &bar0->mdio_control);
2916         udelay(100);
2917
2918         //Data transaction
2919         val64 = 0x0;
2920         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2921                         | MDIO_MMD_DEV_ADDR(mmd_type)
2922                         | MDIO_MMS_PRT_ADDR(0x0)
2923                         | MDIO_MDIO_DATA(value)
2924                         | MDIO_OP(MDIO_OP_WRITE_TRANS);
2925         writeq(val64, &bar0->mdio_control);
2926         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2927         writeq(val64, &bar0->mdio_control);
2928         udelay(100);
2929
2930         val64 = 0x0;
2931         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2932         | MDIO_MMD_DEV_ADDR(mmd_type)
2933         | MDIO_MMS_PRT_ADDR(0x0)
2934         | MDIO_OP(MDIO_OP_READ_TRANS);
2935         writeq(val64, &bar0->mdio_control);
2936         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2937         writeq(val64, &bar0->mdio_control);
2938         udelay(100);
2939
2940 }
2941
2942 /**
2943  *  s2io_mdio_read - Function to write in to MDIO registers
2944  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2945  *  @addr     : address value
2946  *  @dev      : pointer to net_device structure
2947  *  Description:
2948  *  This function is used to read values to the MDIO registers
2949  *  NONE
2950  */
2951 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
2952 {
2953         u64 val64 = 0x0;
2954         u64 rval64 = 0x0;
2955         nic_t *sp = dev->priv;
2956         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2957
2958         /* address transaction */
2959         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2960                         | MDIO_MMD_DEV_ADDR(mmd_type)
2961                         | MDIO_MMS_PRT_ADDR(0x0);
2962         writeq(val64, &bar0->mdio_control);
2963         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2964         writeq(val64, &bar0->mdio_control);
2965         udelay(100);
2966
2967         /* Data transaction */
2968         val64 = 0x0;
2969         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2970                         | MDIO_MMD_DEV_ADDR(mmd_type)
2971                         | MDIO_MMS_PRT_ADDR(0x0)
2972                         | MDIO_OP(MDIO_OP_READ_TRANS);
2973         writeq(val64, &bar0->mdio_control);
2974         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2975         writeq(val64, &bar0->mdio_control);
2976         udelay(100);
2977
2978         /* Read the value from regs */
2979         rval64 = readq(&bar0->mdio_control);
2980         rval64 = rval64 & 0xFFFF0000;
2981         rval64 = rval64 >> 16;
2982         return rval64;
2983 }
2984 /**
2985  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
2986  *  @counter      : couter value to be updated
2987  *  @flag         : flag to indicate the status
2988  *  @type         : counter type
2989  *  Description:
2990  *  This function is to check the status of the xpak counters value
2991  *  NONE
2992  */
2993
2994 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
2995 {
2996         u64 mask = 0x3;
2997         u64 val64;
2998         int i;
2999         for(i = 0; i <index; i++)
3000                 mask = mask << 0x2;
3001
3002         if(flag > 0)
3003         {
3004                 *counter = *counter + 1;
3005                 val64 = *regs_stat & mask;
3006                 val64 = val64 >> (index * 0x2);
3007                 val64 = val64 + 1;
3008                 if(val64 == 3)
3009                 {
3010                         switch(type)
3011                         {
3012                         case 1:
3013                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3014                                           "service. Excessive temperatures may "
3015                                           "result in premature transceiver "
3016                                           "failure \n");
3017                         break;
3018                         case 2:
3019                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3020                                           "service Excessive bias currents may "
3021                                           "indicate imminent laser diode "
3022                                           "failure \n");
3023                         break;
3024                         case 3:
3025                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3026                                           "service Excessive laser output "
3027                                           "power may saturate far-end "
3028                                           "receiver\n");
3029                         break;
3030                         default:
3031                                 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3032                                           "type \n");
3033                         }
3034                         val64 = 0x0;
3035                 }
3036                 val64 = val64 << (index * 0x2);
3037                 *regs_stat = (*regs_stat & (~mask)) | (val64);
3038
3039         } else {
3040                 *regs_stat = *regs_stat & (~mask);
3041         }
3042 }
3043
3044 /**
3045  *  s2io_updt_xpak_counter - Function to update the xpak counters
3046  *  @dev         : pointer to net_device struct
3047  *  Description:
3048  *  This function is to upate the status of the xpak counters value
3049  *  NONE
3050  */
3051 static void s2io_updt_xpak_counter(struct net_device *dev)
3052 {
3053         u16 flag  = 0x0;
3054         u16 type  = 0x0;
3055         u16 val16 = 0x0;
3056         u64 val64 = 0x0;
3057         u64 addr  = 0x0;
3058
3059         nic_t *sp = dev->priv;
3060         StatInfo_t *stat_info = sp->mac_control.stats_info;
3061
3062         /* Check the communication with the MDIO slave */
3063         addr = 0x0000;
3064         val64 = 0x0;
3065         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3066         if((val64 == 0xFFFF) || (val64 == 0x0000))
3067         {
3068                 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3069                           "Returned %llx\n", (unsigned long long)val64);
3070                 return;
3071         }
3072
3073         /* Check for the expecte value of 2040 at PMA address 0x0000 */
3074         if(val64 != 0x2040)
3075         {
3076                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3077                 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3078                           (unsigned long long)val64);
3079                 return;
3080         }
3081
3082         /* Loading the DOM register to MDIO register */
3083         addr = 0xA100;
3084         s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3085         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3086
3087         /* Reading the Alarm flags */
3088         addr = 0xA070;
3089         val64 = 0x0;
3090         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3091
3092         flag = CHECKBIT(val64, 0x7);
3093         type = 1;
3094         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3095                                 &stat_info->xpak_stat.xpak_regs_stat,
3096                                 0x0, flag, type);
3097
3098         if(CHECKBIT(val64, 0x6))
3099                 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3100
3101         flag = CHECKBIT(val64, 0x3);
3102         type = 2;
3103         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3104                                 &stat_info->xpak_stat.xpak_regs_stat,
3105                                 0x2, flag, type);
3106
3107         if(CHECKBIT(val64, 0x2))
3108                 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3109
3110         flag = CHECKBIT(val64, 0x1);
3111         type = 3;
3112         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3113                                 &stat_info->xpak_stat.xpak_regs_stat,
3114                                 0x4, flag, type);
3115
3116         if(CHECKBIT(val64, 0x0))
3117                 stat_info->xpak_stat.alarm_laser_output_power_low++;
3118
3119         /* Reading the Warning flags */
3120         addr = 0xA074;
3121         val64 = 0x0;
3122         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3123
3124         if(CHECKBIT(val64, 0x7))
3125                 stat_info->xpak_stat.warn_transceiver_temp_high++;
3126
3127         if(CHECKBIT(val64, 0x6))
3128                 stat_info->xpak_stat.warn_transceiver_temp_low++;
3129
3130         if(CHECKBIT(val64, 0x3))
3131                 stat_info->xpak_stat.warn_laser_bias_current_high++;
3132
3133         if(CHECKBIT(val64, 0x2))
3134                 stat_info->xpak_stat.warn_laser_bias_current_low++;
3135
3136         if(CHECKBIT(val64, 0x1))
3137                 stat_info->xpak_stat.warn_laser_output_power_high++;
3138
3139         if(CHECKBIT(val64, 0x0))
3140                 stat_info->xpak_stat.warn_laser_output_power_low++;
3141 }
3142
3143 /**
3144  *  alarm_intr_handler - Alarm Interrrupt handler
3145  *  @nic: device private variable
3146  *  Description: If the interrupt was neither because of Rx packet or Tx
3147  *  complete, this function is called. If the interrupt was to indicate
3148  *  a loss of link, the OSM link status handler is invoked for any other
3149  *  alarm interrupt the block that raised the interrupt is displayed
3150  *  and a H/W reset is issued.
3151  *  Return Value:
3152  *  NONE
3153 */
3154
3155 static void alarm_intr_handler(struct s2io_nic *nic)
3156 {
3157         struct net_device *dev = (struct net_device *) nic->dev;
3158         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3159         register u64 val64 = 0, err_reg = 0;
3160         u64 cnt;
3161         int i;
3162         nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3163         /* Handling the XPAK counters update */
3164         if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3165                 /* waiting for an hour */
3166                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3167         } else {
3168                 s2io_updt_xpak_counter(dev);
3169                 /* reset the count to zero */
3170                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3171         }
3172
3173         /* Handling link status change error Intr */
3174         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3175                 err_reg = readq(&bar0->mac_rmac_err_reg);
3176                 writeq(err_reg, &bar0->mac_rmac_err_reg);
3177                 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3178                         schedule_work(&nic->set_link_task);
3179                 }
3180         }
3181
3182         /* Handling Ecc errors */
3183         val64 = readq(&bar0->mc_err_reg);
3184         writeq(val64, &bar0->mc_err_reg);
3185         if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
3186                 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
3187                         nic->mac_control.stats_info->sw_stat.
3188                                 double_ecc_errs++;
3189                         DBG_PRINT(INIT_DBG, "%s: Device indicates ",
3190                                   dev->name);
3191                         DBG_PRINT(INIT_DBG, "double ECC error!!\n");
3192                         if (nic->device_type != XFRAME_II_DEVICE) {
3193                                 /* Reset XframeI only if critical error */
3194                                 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
3195                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
3196                                         netif_stop_queue(dev);
3197                                         schedule_work(&nic->rst_timer_task);
3198                                         nic->mac_control.stats_info->sw_stat.
3199                                                         soft_reset_cnt++;
3200                                 }
3201                         }
3202                 } else {
3203                         nic->mac_control.stats_info->sw_stat.
3204                                 single_ecc_errs++;
3205                 }
3206         }
3207
3208         /* In case of a serious error, the device will be Reset. */
3209         val64 = readq(&bar0->serr_source);
3210         if (val64 & SERR_SOURCE_ANY) {
3211                 nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
3212                 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
3213                 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
3214                           (unsigned long long)val64);
3215                 netif_stop_queue(dev);
3216                 schedule_work(&nic->rst_timer_task);
3217                 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3218         }
3219
3220         /*
3221          * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3222          * Error occurs, the adapter will be recycled by disabling the
3223          * adapter enable bit and enabling it again after the device
3224          * becomes Quiescent.
3225          */
3226         val64 = readq(&bar0->pcc_err_reg);
3227         writeq(val64, &bar0->pcc_err_reg);
3228         if (val64 & PCC_FB_ECC_DB_ERR) {
3229                 u64 ac = readq(&bar0->adapter_control);
3230                 ac &= ~(ADAPTER_CNTL_EN);
3231                 writeq(ac, &bar0->adapter_control);
3232                 ac = readq(&bar0->adapter_control);
3233                 schedule_work(&nic->set_link_task);
3234         }
3235         /* Check for data parity error */
3236         val64 = readq(&bar0->pic_int_status);
3237         if (val64 & PIC_INT_GPIO) {
3238                 val64 = readq(&bar0->gpio_int_reg);
3239                 if (val64 & GPIO_INT_REG_DP_ERR_INT) {
3240                         nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
3241                         schedule_work(&nic->rst_timer_task);
3242                         nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3243                 }
3244         }
3245
3246         /* Check for ring full counter */
3247         if (nic->device_type & XFRAME_II_DEVICE) {
3248                 val64 = readq(&bar0->ring_bump_counter1);
3249                 for (i=0; i<4; i++) {
3250                         cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3251                         cnt >>= 64 - ((i+1)*16);
3252                         nic->mac_control.stats_info->sw_stat.ring_full_cnt
3253                                 += cnt;
3254                 }
3255
3256                 val64 = readq(&bar0->ring_bump_counter2);
3257                 for (i=0; i<4; i++) {
3258                         cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3259                         cnt >>= 64 - ((i+1)*16);
3260                         nic->mac_control.stats_info->sw_stat.ring_full_cnt
3261                                 += cnt;
3262                 }
3263         }
3264
3265         /* Other type of interrupts are not being handled now,  TODO */
3266 }
3267
3268 /**
3269  *  wait_for_cmd_complete - waits for a command to complete.
3270  *  @sp : private member of the device structure, which is a pointer to the
3271  *  s2io_nic structure.
3272  *  Description: Function that waits for a command to Write into RMAC
3273  *  ADDR DATA registers to be completed and returns either success or
3274  *  error depending on whether the command was complete or not.
3275  *  Return value:
3276  *   SUCCESS on success and FAILURE on failure.
3277  */
3278
3279 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit)
3280 {
3281         int ret = FAILURE, cnt = 0;
3282         u64 val64;
3283
3284         while (TRUE) {
3285                 val64 = readq(addr);
3286                 if (!(val64 & busy_bit)) {
3287                         ret = SUCCESS;
3288                         break;
3289                 }
3290
3291                 if(in_interrupt())
3292                         mdelay(50);
3293                 else
3294                         msleep(50);
3295
3296                 if (cnt++ > 10)
3297                         break;
3298         }
3299         return ret;
3300 }
3301
3302 /**
3303  *  s2io_reset - Resets the card.
3304  *  @sp : private member of the device structure.
3305  *  Description: Function to Reset the card. This function then also
3306  *  restores the previously saved PCI configuration space registers as
3307  *  the card reset also resets the configuration space.
3308  *  Return value:
3309  *  void.
3310  */
3311
3312 static void s2io_reset(nic_t * sp)
3313 {
3314         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3315         u64 val64;
3316         u16 subid, pci_cmd;
3317
3318         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3319         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3320
3321         val64 = SW_RESET_ALL;
3322         writeq(val64, &bar0->sw_reset);
3323
3324         /*
3325          * At this stage, if the PCI write is indeed completed, the
3326          * card is reset and so is the PCI Config space of the device.
3327          * So a read cannot be issued at this stage on any of the
3328          * registers to ensure the write into "sw_reset" register
3329          * has gone through.
3330          * Question: Is there any system call that will explicitly force
3331          * all the write commands still pending on the bus to be pushed
3332          * through?
3333          * As of now I'am just giving a 250ms delay and hoping that the
3334          * PCI write to sw_reset register is done by this time.
3335          */
3336         msleep(250);
3337         if (strstr(sp->product_name, "CX4")) {
3338                 msleep(750);
3339         }
3340
3341         /* Restore the PCI state saved during initialization. */
3342         pci_restore_state(sp->pdev);
3343         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
3344                                      pci_cmd);
3345         s2io_init_pci(sp);
3346
3347         msleep(250);
3348
3349         /* Set swapper to enable I/O register access */
3350         s2io_set_swapper(sp);
3351
3352         /* Restore the MSIX table entries from local variables */
3353         restore_xmsi_data(sp);
3354
3355         /* Clear certain PCI/PCI-X fields after reset */
3356         if (sp->device_type == XFRAME_II_DEVICE) {
3357                 /* Clear "detected parity error" bit */
3358                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3359
3360                 /* Clearing PCIX Ecc status register */
3361                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3362
3363                 /* Clearing PCI_STATUS error reflected here */
3364                 writeq(BIT(62), &bar0->txpic_int_reg);
3365         }
3366
3367         /* Reset device statistics maintained by OS */
3368         memset(&sp->stats, 0, sizeof (struct net_device_stats));
3369
3370         /* SXE-002: Configure link and activity LED to turn it off */
3371         subid = sp->pdev->subsystem_device;
3372         if (((subid & 0xFF) >= 0x07) &&
3373             (sp->device_type == XFRAME_I_DEVICE)) {
3374                 val64 = readq(&bar0->gpio_control);
3375                 val64 |= 0x0000800000000000ULL;
3376                 writeq(val64, &bar0->gpio_control);
3377                 val64 = 0x0411040400000000ULL;
3378                 writeq(val64, (void __iomem *)bar0 + 0x2700);
3379         }
3380
3381         /*
3382          * Clear spurious ECC interrupts that would have occured on
3383          * XFRAME II cards after reset.
3384          */
3385         if (sp->device_type == XFRAME_II_DEVICE) {
3386                 val64 = readq(&bar0->pcc_err_reg);
3387                 writeq(val64, &bar0->pcc_err_reg);
3388         }
3389
3390         sp->device_enabled_once = FALSE;
3391 }
3392
3393 /**
3394  *  s2io_set_swapper - to set the swapper controle on the card
3395  *  @sp : private member of the device structure,
3396  *  pointer to the s2io_nic structure.
3397  *  Description: Function to set the swapper control on the card
3398  *  correctly depending on the 'endianness' of the system.
3399  *  Return value:
3400  *  SUCCESS on success and FAILURE on failure.
3401  */
3402
3403 static int s2io_set_swapper(nic_t * sp)
3404 {
3405         struct net_device *dev = sp->dev;
3406         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3407         u64 val64, valt, valr;
3408
3409         /*
3410          * Set proper endian settings and verify the same by reading
3411          * the PIF Feed-back register.
3412          */
3413
3414         val64 = readq(&bar0->pif_rd_swapper_fb);
3415         if (val64 != 0x0123456789ABCDEFULL) {
3416                 int i = 0;
3417                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
3418                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
3419                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
3420                                 0};                     /* FE=0, SE=0 */
3421
3422                 while(i<4) {
3423                         writeq(value[i], &bar0->swapper_ctrl);
3424                         val64 = readq(&bar0->pif_rd_swapper_fb);
3425                         if (val64 == 0x0123456789ABCDEFULL)
3426                                 break;
3427                         i++;
3428                 }
3429                 if (i == 4) {
3430                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3431                                 dev->name);
3432                         DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3433                                 (unsigned long long) val64);
3434                         return FAILURE;
3435                 }
3436                 valr = value[i];
3437         } else {
3438                 valr = readq(&bar0->swapper_ctrl);
3439         }
3440
3441         valt = 0x0123456789ABCDEFULL;
3442         writeq(valt, &bar0->xmsi_address);
3443         val64 = readq(&bar0->xmsi_address);
3444
3445         if(val64 != valt) {
3446                 int i = 0;
3447                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3448                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
3449                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
3450                                 0};                     /* FE=0, SE=0 */
3451
3452                 while(i<4) {
3453                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3454                         writeq(valt, &bar0->xmsi_address);
3455                         val64 = readq(&bar0->xmsi_address);
3456                         if(val64 == valt)
3457                                 break;
3458                         i++;
3459                 }
3460                 if(i == 4) {
3461                         unsigned long long x = val64;
3462                         DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3463                         DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3464                         return FAILURE;
3465                 }
3466         }
3467         val64 = readq(&bar0->swapper_ctrl);
3468         val64 &= 0xFFFF000000000000ULL;
3469
3470 #ifdef  __BIG_ENDIAN
3471         /*
3472          * The device by default set to a big endian format, so a
3473          * big endian driver need not set anything.
3474          */
3475         val64 |= (SWAPPER_CTRL_TXP_FE |
3476                  SWAPPER_CTRL_TXP_SE |
3477                  SWAPPER_CTRL_TXD_R_FE |
3478                  SWAPPER_CTRL_TXD_W_FE |
3479                  SWAPPER_CTRL_TXF_R_FE |
3480                  SWAPPER_CTRL_RXD_R_FE |
3481                  SWAPPER_CTRL_RXD_W_FE |
3482                  SWAPPER_CTRL_RXF_W_FE |
3483                  SWAPPER_CTRL_XMSI_FE |
3484                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3485         if (sp->intr_type == INTA)
3486                 val64 |= SWAPPER_CTRL_XMSI_SE;
3487         writeq(val64, &bar0->swapper_ctrl);
3488 #else
3489         /*
3490          * Initially we enable all bits to make it accessible by the
3491          * driver, then we selectively enable only those bits that
3492          * we want to set.
3493          */
3494         val64 |= (SWAPPER_CTRL_TXP_FE |
3495                  SWAPPER_CTRL_TXP_SE |
3496                  SWAPPER_CTRL_TXD_R_FE |
3497                  SWAPPER_CTRL_TXD_R_SE |
3498                  SWAPPER_CTRL_TXD_W_FE |
3499                  SWAPPER_CTRL_TXD_W_SE |
3500                  SWAPPER_CTRL_TXF_R_FE |
3501                  SWAPPER_CTRL_RXD_R_FE |
3502                  SWAPPER_CTRL_RXD_R_SE |
3503                  SWAPPER_CTRL_RXD_W_FE |
3504                  SWAPPER_CTRL_RXD_W_SE |
3505                  SWAPPER_CTRL_RXF_W_FE |
3506                  SWAPPER_CTRL_XMSI_FE |
3507                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3508         if (sp->intr_type == INTA)
3509                 val64 |= SWAPPER_CTRL_XMSI_SE;
3510         writeq(val64, &bar0->swapper_ctrl);
3511 #endif
3512         val64 = readq(&bar0->swapper_ctrl);
3513
3514         /*
3515          * Verifying if endian settings are accurate by reading a
3516          * feedback register.
3517          */
3518         val64 = readq(&bar0->pif_rd_swapper_fb);
3519         if (val64 != 0x0123456789ABCDEFULL) {
3520                 /* Endian settings are incorrect, calls for another dekko. */
3521                 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3522                           dev->name);
3523                 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3524                           (unsigned long long) val64);
3525                 return FAILURE;
3526         }
3527
3528         return SUCCESS;
3529 }
3530
3531 static int wait_for_msix_trans(nic_t *nic, int i)
3532 {
3533         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3534         u64 val64;
3535         int ret = 0, cnt = 0;
3536
3537         do {
3538                 val64 = readq(&bar0->xmsi_access);
3539                 if (!(val64 & BIT(15)))
3540                         break;
3541                 mdelay(1);
3542                 cnt++;
3543         } while(cnt < 5);
3544         if (cnt == 5) {
3545                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3546                 ret = 1;
3547         }
3548
3549         return ret;
3550 }
3551
3552 static void restore_xmsi_data(nic_t *nic)
3553 {
3554         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3555         u64 val64;
3556         int i;
3557
3558         for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3559                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3560                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3561                 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3562                 writeq(val64, &bar0->xmsi_access);
3563                 if (wait_for_msix_trans(nic, i)) {
3564                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3565                         continue;
3566                 }
3567         }
3568 }
3569
3570 static void store_xmsi_data(nic_t *nic)
3571 {
3572         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3573         u64 val64, addr, data;
3574         int i;
3575
3576         /* Store and display */
3577         for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3578                 val64 = (BIT(15) | vBIT(i, 26, 6));
3579                 writeq(val64, &bar0->xmsi_access);
3580                 if (wait_for_msix_trans(nic, i)) {
3581                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3582                         continue;
3583                 }
3584                 addr = readq(&bar0->xmsi_address);
3585                 data = readq(&bar0->xmsi_data);
3586                 if (addr && data) {
3587                         nic->msix_info[i].addr = addr;
3588                         nic->msix_info[i].data = data;
3589                 }
3590         }
3591 }
3592
3593 int s2io_enable_msi(nic_t *nic)
3594 {
3595         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3596         u16 msi_ctrl, msg_val;
3597         struct config_param *config = &nic->config;
3598         struct net_device *dev = nic->dev;
3599         u64 val64, tx_mat, rx_mat;
3600         int i, err;
3601
3602         val64 = readq(&bar0->pic_control);
3603         val64 &= ~BIT(1);
3604         writeq(val64, &bar0->pic_control);
3605
3606         err = pci_enable_msi(nic->pdev);
3607         if (err) {
3608                 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3609                           nic->dev->name);
3610                 return err;
3611         }
3612
3613         /*
3614          * Enable MSI and use MSI-1 in stead of the standard MSI-0
3615          * for interrupt handling.
3616          */
3617         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3618         msg_val ^= 0x1;
3619         pci_write_config_word(nic->pdev, 0x4c, msg_val);
3620         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3621
3622         pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3623         msi_ctrl |= 0x10;
3624         pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3625
3626         /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3627         tx_mat = readq(&bar0->tx_mat0_n[0]);
3628         for (i=0; i<config->tx_fifo_num; i++) {
3629                 tx_mat |= TX_MAT_SET(i, 1);
3630         }
3631         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3632
3633         rx_mat = readq(&bar0->rx_mat);
3634         for (i=0; i<config->rx_ring_num; i++) {
3635                 rx_mat |= RX_MAT_SET(i, 1);
3636         }
3637         writeq(rx_mat, &bar0->rx_mat);
3638
3639         dev->irq = nic->pdev->irq;
3640         return 0;
3641 }
3642
3643 static int s2io_enable_msi_x(nic_t *nic)
3644 {
3645         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3646         u64 tx_mat, rx_mat;
3647         u16 msi_control; /* Temp variable */
3648         int ret, i, j, msix_indx = 1;
3649
3650         nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3651                                GFP_KERNEL);
3652         if (nic->entries == NULL) {
3653                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3654                 return -ENOMEM;
3655         }
3656         memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3657
3658         nic->s2io_entries =
3659                 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3660                                    GFP_KERNEL);
3661         if (nic->s2io_entries == NULL) {
3662                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3663                 kfree(nic->entries);
3664                 return -ENOMEM;
3665         }
3666         memset(nic->s2io_entries, 0,
3667                MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3668
3669         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3670                 nic->entries[i].entry = i;
3671                 nic->s2io_entries[i].entry = i;
3672                 nic->s2io_entries[i].arg = NULL;
3673                 nic->s2io_entries[i].in_use = 0;
3674         }
3675
3676         tx_mat = readq(&bar0->tx_mat0_n[0]);
3677         for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3678                 tx_mat |= TX_MAT_SET(i, msix_indx);
3679                 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3680                 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3681                 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3682         }
3683         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3684
3685         if (!nic->config.bimodal) {
3686                 rx_mat = readq(&bar0->rx_mat);
3687                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3688                         rx_mat |= RX_MAT_SET(j, msix_indx);
3689                         nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3690                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3691                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3692                 }
3693                 writeq(rx_mat, &bar0->rx_mat);
3694         } else {
3695                 tx_mat = readq(&bar0->tx_mat0_n[7]);
3696                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3697                         tx_mat |= TX_MAT_SET(i, msix_indx);
3698                         nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3699                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3700                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3701                 }
3702                 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3703         }
3704
3705         nic->avail_msix_vectors = 0;
3706         ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3707         /* We fail init if error or we get less vectors than min required */
3708         if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3709                 nic->avail_msix_vectors = ret;
3710                 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3711         }
3712         if (ret) {
3713                 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3714                 kfree(nic->entries);
3715                 kfree(nic->s2io_entries);
3716                 nic->entries = NULL;
3717                 nic->s2io_entries = NULL;
3718                 nic->avail_msix_vectors = 0;
3719                 return -ENOMEM;
3720         }
3721         if (!nic->avail_msix_vectors)
3722                 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
3723
3724         /*
3725          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3726          * in the herc NIC. (Temp change, needs to be removed later)
3727          */
3728         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3729         msi_control |= 0x1; /* Enable MSI */
3730         pci_write_config_word(nic->pdev, 0x42, msi_control);
3731
3732         return 0;
3733 }
3734
3735 /* ********************************************************* *
3736  * Functions defined below concern the OS part of the driver *
3737  * ********************************************************* */
3738
3739 /**
3740  *  s2io_open - open entry point of the driver
3741  *  @dev : pointer to the device structure.
3742  *  Description:
3743  *  This function is the open entry point of the driver. It mainly calls a
3744  *  function to allocate Rx buffers and inserts them into the buffer
3745  *  descriptors and then enables the Rx part of the NIC.
3746  *  Return value:
3747  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3748  *   file on failure.
3749  */
3750
3751 static int s2io_open(struct net_device *dev)
3752 {
3753         nic_t *sp = dev->priv;
3754         int err = 0;
3755
3756         /*
3757          * Make sure you have link off by default every time
3758          * Nic is initialized
3759          */
3760         netif_carrier_off(dev);
3761         sp->last_link_state = 0;
3762
3763         /* Initialize H/W and enable interrupts */
3764         err = s2io_card_up(sp);
3765         if (err) {
3766                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3767                           dev->name);
3768                 goto hw_init_failed;
3769         }
3770
3771         if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3772                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3773                 s2io_card_down(sp);
3774                 err = -ENODEV;
3775                 goto hw_init_failed;
3776         }
3777
3778         netif_start_queue(dev);
3779         return 0;
3780
3781 hw_init_failed:
3782         if (sp->intr_type == MSI_X) {
3783                 if (sp->entries)
3784                         kfree(sp->entries);
3785                 if (sp->s2io_entries)
3786                         kfree(sp->s2io_entries);
3787         }
3788         return err;
3789 }
3790
3791 /**
3792  *  s2io_close -close entry point of the driver
3793  *  @dev : device pointer.
3794  *  Description:
3795  *  This is the stop entry point of the driver. It needs to undo exactly
3796  *  whatever was done by the open entry point,thus it's usually referred to
3797  *  as the close function.Among other things this function mainly stops the
3798  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3799  *  Return value:
3800  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3801  *  file on failure.
3802  */
3803
3804 static int s2io_close(struct net_device *dev)
3805 {
3806         nic_t *sp = dev->priv;
3807
3808         flush_scheduled_work();
3809         netif_stop_queue(dev);
3810         /* Reset card, kill tasklet and free Tx and Rx buffers. */
3811         s2io_card_down(sp);
3812
3813         sp->device_close_flag = TRUE;   /* Device is shut down. */
3814         return 0;
3815 }
3816
3817 /**
3818  *  s2io_xmit - Tx entry point of te driver
3819  *  @skb : the socket buffer containing the Tx data.
3820  *  @dev : device pointer.
3821  *  Description :
3822  *  This function is the Tx entry point of the driver. S2IO NIC supports
3823  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
3824  *  NOTE: when device cant queue the pkt,just the trans_start variable will
3825  *  not be upadted.
3826  *  Return value:
3827  *  0 on success & 1 on failure.
3828  */
3829
3830 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3831 {
3832         nic_t *sp = dev->priv;
3833         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3834         register u64 val64;
3835         TxD_t *txdp;
3836         TxFIFO_element_t __iomem *tx_fifo;
3837         unsigned long flags;
3838         u16 vlan_tag = 0;
3839         int vlan_priority = 0;
3840         mac_info_t *mac_control;
3841         struct config_param *config;
3842         int offload_type;
3843
3844         mac_control = &sp->mac_control;
3845         config = &sp->config;
3846
3847         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
3848         spin_lock_irqsave(&sp->tx_lock, flags);
3849         if (atomic_read(&sp->card_state) == CARD_DOWN) {
3850                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
3851                           dev->name);
3852                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3853                 dev_kfree_skb(skb);
3854                 return 0;
3855         }
3856
3857         queue = 0;
3858
3859         /* Get Fifo number to Transmit based on vlan priority */
3860         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3861                 vlan_tag = vlan_tx_tag_get(skb);
3862                 vlan_priority = vlan_tag >> 13;
3863                 queue = config->fifo_mapping[vlan_priority];
3864         }
3865
3866         put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3867         get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
3868         txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off].
3869                 list_virt_addr;
3870
3871         queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
3872         /* Avoid "put" pointer going beyond "get" pointer */
3873         if (txdp->Host_Control ||
3874                    ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
3875                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3876                 netif_stop_queue(dev);
3877                 dev_kfree_skb(skb);
3878                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3879                 return 0;
3880         }
3881
3882         /* A buffer with no data will be dropped */
3883         if (!skb->len) {
3884                 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3885                 dev_kfree_skb(skb);
3886                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3887                 return 0;
3888         }
3889
3890         offload_type = s2io_offload_type(skb);
3891 #ifdef NETIF_F_TSO
3892         if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3893                 txdp->Control_1 |= TXD_TCP_LSO_EN;
3894                 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
3895         }
3896 #endif
3897         if (skb->ip_summed == CHECKSUM_PARTIAL) {
3898                 txdp->Control_2 |=
3899                     (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3900                      TXD_TX_CKO_UDP_EN);
3901         }
3902         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
3903         txdp->Control_1 |= TXD_LIST_OWN_XENA;
3904         txdp->Control_2 |= config->tx_intr_type;
3905
3906         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3907                 txdp->Control_2 |= TXD_VLAN_ENABLE;
3908                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3909         }
3910
3911         frg_len = skb->len - skb->data_len;
3912         if (offload_type == SKB_GSO_UDP) {
3913                 int ufo_size;
3914
3915                 ufo_size = s2io_udp_mss(skb);
3916                 ufo_size &= ~7;
3917                 txdp->Control_1 |= TXD_UFO_EN;
3918                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
3919                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
3920 #ifdef __BIG_ENDIAN
3921                 sp->ufo_in_band_v[put_off] =
3922                                 (u64)skb_shinfo(skb)->ip6_frag_id;
3923 #else
3924                 sp->ufo_in_band_v[put_off] =
3925                                 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
3926 #endif
3927                 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
3928                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
3929                                         sp->ufo_in_band_v,
3930                                         sizeof(u64), PCI_DMA_TODEVICE);
3931                 txdp++;
3932         }
3933
3934         txdp->Buffer_Pointer = pci_map_single
3935             (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
3936         txdp->Host_Control = (unsigned long) skb;
3937         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
3938         if (offload_type == SKB_GSO_UDP)
3939                 txdp->Control_1 |= TXD_UFO_EN;
3940
3941         frg_cnt = skb_shinfo(skb)->nr_frags;
3942         /* For fragmented SKB. */
3943         for (i = 0; i < frg_cnt; i++) {
3944                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3945                 /* A '0' length fragment will be ignored */
3946                 if (!frag->size)
3947                         continue;
3948                 txdp++;
3949                 txdp->Buffer_Pointer = (u64) pci_map_page
3950                     (sp->pdev, frag->page, frag->page_offset,
3951                      frag->size, PCI_DMA_TODEVICE);
3952                 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
3953                 if (offload_type == SKB_GSO_UDP)
3954                         txdp->Control_1 |= TXD_UFO_EN;
3955         }
3956         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
3957
3958         if (offload_type == SKB_GSO_UDP)
3959                 frg_cnt++; /* as Txd0 was used for inband header */
3960
3961         tx_fifo = mac_control->tx_FIFO_start[queue];
3962         val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
3963         writeq(val64, &tx_fifo->TxDL_Pointer);
3964
3965         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
3966                  TX_FIFO_LAST_LIST);
3967         if (offload_type)
3968                 val64 |= TX_FIFO_SPECIAL_FUNC;
3969
3970         writeq(val64, &tx_fifo->List_Control);
3971
3972         mmiowb();
3973
3974         put_off++;
3975         if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
3976                 put_off = 0;
3977         mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
3978
3979         /* Avoid "put" pointer going beyond "get" pointer */
3980         if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
3981                 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
3982                 DBG_PRINT(TX_DBG,
3983                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
3984                           put_off, get_off);
3985                 netif_stop_queue(dev);
3986         }
3987
3988         dev->trans_start = jiffies;
3989         spin_unlock_irqrestore(&sp->tx_lock, flags);
3990
3991         return 0;
3992 }
3993
3994 static void
3995 s2io_alarm_handle(unsigned long data)
3996 {
3997         nic_t *sp = (nic_t *)data;
3998
3999         alarm_intr_handler(sp);
4000         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4001 }
4002
4003 static int s2io_chk_rx_buffers(nic_t *sp, int rng_n)
4004 {
4005         int rxb_size, level;
4006
4007         if (!sp->lro) {
4008                 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4009                 level = rx_buffer_level(sp, rxb_size, rng_n);
4010
4011                 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4012                         int ret;
4013                         DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4014                         DBG_PRINT(INTR_DBG, "PANIC levels\n");
4015                         if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
4016                                 DBG_PRINT(ERR_DBG, "Out of memory in %s",
4017                                           __FUNCTION__);
4018                                 clear_bit(0, (&sp->tasklet_status));
4019                                 return -1;
4020                         }
4021                         clear_bit(0, (&sp->tasklet_status));
4022                 } else if (level == LOW)
4023                         tasklet_schedule(&sp->task);
4024
4025         } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4026                         DBG_PRINT(ERR_DBG, "%s:Out of memory", sp->dev->name);
4027                         DBG_PRINT(ERR_DBG, " in Rx Intr!!\n");
4028         }
4029         return 0;
4030 }
4031
4032 static irqreturn_t s2io_msi_handle(int irq, void *dev_id)
4033 {
4034         struct net_device *dev = (struct net_device *) dev_id;
4035         nic_t *sp = dev->priv;
4036         int i;
4037         mac_info_t *mac_control;
4038         struct config_param *config;
4039
4040         atomic_inc(&sp->isr_cnt);
4041         mac_control = &sp->mac_control;
4042         config = &sp->config;
4043         DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
4044
4045         /* If Intr is because of Rx Traffic */
4046         for (i = 0; i < config->rx_ring_num; i++)
4047                 rx_intr_handler(&mac_control->rings[i]);
4048
4049         /* If Intr is because of Tx Traffic */
4050         for (i = 0; i < config->tx_fifo_num; i++)
4051                 tx_intr_handler(&mac_control->fifos[i]);
4052
4053         /*
4054          * If the Rx buffer count is below the panic threshold then
4055          * reallocate the buffers from the interrupt handler itself,
4056          * else schedule a tasklet to reallocate the buffers.
4057          */
4058         for (i = 0; i < config->rx_ring_num; i++)
4059                 s2io_chk_rx_buffers(sp, i);
4060
4061         atomic_dec(&sp->isr_cnt);
4062         return IRQ_HANDLED;
4063 }
4064
4065 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4066 {
4067         ring_info_t *ring = (ring_info_t *)dev_id;
4068         nic_t *sp = ring->nic;
4069
4070         atomic_inc(&sp->isr_cnt);
4071
4072         rx_intr_handler(ring);
4073         s2io_chk_rx_buffers(sp, ring->ring_no);
4074
4075         atomic_dec(&sp->isr_cnt);
4076         return IRQ_HANDLED;
4077 }
4078
4079 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4080 {
4081         fifo_info_t *fifo = (fifo_info_t *)dev_id;
4082         nic_t *sp = fifo->nic;
4083
4084         atomic_inc(&sp->isr_cnt);
4085         tx_intr_handler(fifo);
4086         atomic_dec(&sp->isr_cnt);
4087         return IRQ_HANDLED;
4088 }
4089 static void s2io_txpic_intr_handle(nic_t *sp)
4090 {
4091         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4092         u64 val64;
4093
4094         val64 = readq(&bar0->pic_int_status);
4095         if (val64 & PIC_INT_GPIO) {
4096                 val64 = readq(&bar0->gpio_int_reg);
4097                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4098                     (val64 & GPIO_INT_REG_LINK_UP)) {
4099                         /*
4100                          * This is unstable state so clear both up/down
4101                          * interrupt and adapter to re-evaluate the link state.
4102                          */
4103                         val64 |=  GPIO_INT_REG_LINK_DOWN;
4104                         val64 |= GPIO_INT_REG_LINK_UP;
4105                         writeq(val64, &bar0->gpio_int_reg);
4106                         val64 = readq(&bar0->gpio_int_mask);
4107                         val64 &= ~(GPIO_INT_MASK_LINK_UP |
4108                                    GPIO_INT_MASK_LINK_DOWN);
4109                         writeq(val64, &bar0->gpio_int_mask);
4110                 }
4111                 else if (val64 & GPIO_INT_REG_LINK_UP) {
4112                         val64 = readq(&bar0->adapter_status);
4113                         if (verify_xena_quiescence(sp, val64,
4114                                                    sp->device_enabled_once)) {
4115                                 /* Enable Adapter */
4116                                 val64 = readq(&bar0->adapter_control);
4117                                 val64 |= ADAPTER_CNTL_EN;
4118                                 writeq(val64, &bar0->adapter_control);
4119                                 val64 |= ADAPTER_LED_ON;
4120                                 writeq(val64, &bar0->adapter_control);
4121                                 if (!sp->device_enabled_once)
4122                                         sp->device_enabled_once = 1;
4123
4124                                 s2io_link(sp, LINK_UP);
4125                                 /*
4126                                  * unmask link down interrupt and mask link-up
4127                                  * intr
4128                                  */
4129                                 val64 = readq(&bar0->gpio_int_mask);
4130                                 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4131                                 val64 |= GPIO_INT_MASK_LINK_UP;
4132                                 writeq(val64, &bar0->gpio_int_mask);
4133
4134                         }
4135                 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4136                         val64 = readq(&bar0->adapter_status);
4137                         if (verify_xena_quiescence(sp, val64,
4138                                                    sp->device_enabled_once)) {
4139                                 s2io_link(sp, LINK_DOWN);
4140                                 /* Link is down so unmaks link up interrupt */
4141                                 val64 = readq(&bar0->gpio_int_mask);
4142                                 val64 &= ~GPIO_INT_MASK_LINK_UP;
4143                                 val64 |= GPIO_INT_MASK_LINK_DOWN;
4144                                 writeq(val64, &bar0->gpio_int_mask);
4145                         }
4146                 }
4147         }
4148         val64 = readq(&bar0->gpio_int_mask);
4149 }
4150
4151 /**
4152  *  s2io_isr - ISR handler of the device .
4153  *  @irq: the irq of the device.
4154  *  @dev_id: a void pointer to the dev structure of the NIC.
4155  *  Description:  This function is the ISR handler of the device. It
4156  *  identifies the reason for the interrupt and calls the relevant
4157  *  service routines. As a contongency measure, this ISR allocates the
4158  *  recv buffers, if their numbers are below the panic value which is
4159  *  presently set to 25% of the original number of rcv buffers allocated.
4160  *  Return value:
4161  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
4162  *   IRQ_NONE: will be returned if interrupt is not from our device
4163  */
4164 static irqreturn_t s2io_isr(int irq, void *dev_id)
4165 {
4166         struct net_device *dev = (struct net_device *) dev_id;
4167         nic_t *sp = dev->priv;
4168         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4169         int i;
4170         u64 reason = 0, val64, org_mask;
4171         mac_info_t *mac_control;
4172         struct config_param *config;
4173
4174         atomic_inc(&sp->isr_cnt);
4175         mac_control = &sp->mac_control;
4176         config = &sp->config;
4177
4178         /*
4179          * Identify the cause for interrupt and call the appropriate
4180          * interrupt handler. Causes for the interrupt could be;
4181          * 1. Rx of packet.
4182          * 2. Tx complete.
4183          * 3. Link down.
4184          * 4. Error in any functional blocks of the NIC.
4185          */
4186         reason = readq(&bar0->general_int_status);
4187
4188         if (!reason) {
4189                 /* The interrupt was not raised by Xena. */
4190                 atomic_dec(&sp->isr_cnt);
4191                 return IRQ_NONE;
4192         }
4193
4194         val64 = 0xFFFFFFFFFFFFFFFFULL;
4195         /* Store current mask before masking all interrupts */
4196         org_mask = readq(&bar0->general_int_mask);
4197         writeq(val64, &bar0->general_int_mask);
4198
4199 #ifdef CONFIG_S2IO_NAPI
4200         if (reason & GEN_INTR_RXTRAFFIC) {
4201                 if (netif_rx_schedule_prep(dev)) {
4202                         writeq(val64, &bar0->rx_traffic_mask);
4203                         __netif_rx_schedule(dev);
4204                 }
4205         }
4206 #else
4207         /*
4208          * Rx handler is called by default, without checking for the
4209          * cause of interrupt.
4210          * rx_traffic_int reg is an R1 register, writing all 1's
4211          * will ensure that the actual interrupt causing bit get's
4212          * cleared and hence a read can be avoided.
4213          */
4214         writeq(val64, &bar0->rx_traffic_int);
4215         for (i = 0; i < config->rx_ring_num; i++) {
4216                 rx_intr_handler(&mac_control->rings[i]);
4217         }
4218 #endif
4219
4220         /*
4221          * tx_traffic_int reg is an R1 register, writing all 1's
4222          * will ensure that the actual interrupt causing bit get's
4223          * cleared and hence a read can be avoided.
4224          */
4225         writeq(val64, &bar0->tx_traffic_int);
4226
4227         for (i = 0; i < config->tx_fifo_num; i++)
4228                 tx_intr_handler(&mac_control->fifos[i]);
4229
4230         if (reason & GEN_INTR_TXPIC)
4231                 s2io_txpic_intr_handle(sp);
4232         /*
4233          * If the Rx buffer count is below the panic threshold then
4234          * reallocate the buffers from the interrupt handler itself,
4235          * else schedule a tasklet to reallocate the buffers.
4236          */
4237 #ifndef CONFIG_S2IO_NAPI
4238         for (i = 0; i < config->rx_ring_num; i++)
4239                 s2io_chk_rx_buffers(sp, i);
4240 #endif
4241         writeq(org_mask, &bar0->general_int_mask);
4242         atomic_dec(&sp->isr_cnt);
4243         return IRQ_HANDLED;
4244 }
4245
4246 /**
4247  * s2io_updt_stats -
4248  */
4249 static void s2io_updt_stats(nic_t *sp)
4250 {
4251         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4252         u64 val64;
4253         int cnt = 0;
4254
4255         if (atomic_read(&sp->card_state) == CARD_UP) {
4256                 /* Apprx 30us on a 133 MHz bus */
4257                 val64 = SET_UPDT_CLICKS(10) |
4258                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4259                 writeq(val64, &bar0->stat_cfg);
4260                 do {
4261                         udelay(100);
4262                         val64 = readq(&bar0->stat_cfg);
4263                         if (!(val64 & BIT(0)))
4264                                 break;
4265                         cnt++;
4266                         if (cnt == 5)
4267                                 break; /* Updt failed */
4268                 } while(1);
4269         } else {
4270                 memset(sp->mac_control.stats_info, 0, sizeof(StatInfo_t));
4271         }
4272 }
4273
4274 /**
4275  *  s2io_get_stats - Updates the device statistics structure.
4276  *  @dev : pointer to the device structure.
4277  *  Description:
4278  *  This function updates the device statistics structure in the s2io_nic
4279  *  structure and returns a pointer to the same.
4280  *  Return value:
4281  *  pointer to the updated net_device_stats structure.
4282  */
4283
4284 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4285 {
4286         nic_t *sp = dev->priv;
4287         mac_info_t *mac_control;
4288         struct config_param *config;
4289
4290
4291         mac_control = &sp->mac_control;
4292         config = &sp->config;
4293
4294         /* Configure Stats for immediate updt */
4295         s2io_updt_stats(sp);
4296
4297         sp->stats.tx_packets =
4298                 le32_to_cpu(mac_control->stats_info->tmac_frms);
4299         sp->stats.tx_errors =
4300                 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4301         sp->stats.rx_errors =
4302                 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
4303         sp->stats.multicast =
4304                 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4305         sp->stats.rx_length_errors =
4306                 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
4307
4308         return (&sp->stats);
4309 }
4310
4311 /**
4312  *  s2io_set_multicast - entry point for multicast address enable/disable.
4313  *  @dev : pointer to the device structure
4314  *  Description:
4315  *  This function is a driver entry point which gets called by the kernel
4316  *  whenever multicast addresses must be enabled/disabled. This also gets
4317  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4318  *  determine, if multicast address must be enabled or if promiscuous mode
4319  *  is to be disabled etc.
4320  *  Return value:
4321  *  void.
4322  */
4323
4324 static void s2io_set_multicast(struct net_device *dev)
4325 {
4326         int i, j, prev_cnt;
4327         struct dev_mc_list *mclist;
4328         nic_t *sp = dev->priv;
4329         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4330         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4331             0xfeffffffffffULL;
4332         u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4333         void __iomem *add;
4334
4335         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4336                 /*  Enable all Multicast addresses */
4337                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4338                        &bar0->rmac_addr_data0_mem);
4339                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4340                        &bar0->rmac_addr_data1_mem);
4341                 val64 = RMAC_ADDR_CMD_MEM_WE |
4342                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4343                     RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4344                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4345                 /* Wait till command completes */
4346                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4347                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
4348
4349                 sp->m_cast_flg = 1;
4350                 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4351         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4352                 /*  Disable all Multicast addresses */
4353                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4354                        &bar0->rmac_addr_data0_mem);
4355                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4356                        &bar0->rmac_addr_data1_mem);
4357                 val64 = RMAC_ADDR_CMD_MEM_WE |
4358                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4359                     RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4360                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4361                 /* Wait till command completes */
4362                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4363                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
4364
4365                 sp->m_cast_flg = 0;
4366                 sp->all_multi_pos = 0;
4367         }
4368
4369         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4370                 /*  Put the NIC into promiscuous mode */
4371                 add = &bar0->mac_cfg;
4372                 val64 = readq(&bar0->mac_cfg);
4373                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4374
4375                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4376                 writel((u32) val64, add);
4377                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4378                 writel((u32) (val64 >> 32), (add + 4));
4379
4380                 val64 = readq(&bar0->mac_cfg);
4381                 sp->promisc_flg = 1;
4382                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4383                           dev->name);
4384         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4385                 /*  Remove the NIC from promiscuous mode */
4386                 add = &bar0->mac_cfg;
4387                 val64 = readq(&bar0->mac_cfg);
4388                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4389
4390                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4391                 writel((u32) val64, add);
4392                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4393                 writel((u32) (val64 >> 32), (add + 4));
4394
4395                 val64 = readq(&bar0->mac_cfg);
4396                 sp->promisc_flg = 0;
4397                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
4398                           dev->name);
4399         }
4400
4401         /*  Update individual M_CAST address list */
4402         if ((!sp->m_cast_flg) && dev->mc_count) {
4403                 if (dev->mc_count >
4404                     (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4405                         DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4406                                   dev->name);
4407                         DBG_PRINT(ERR_DBG, "can be added, please enable ");
4408                         DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4409                         return;
4410                 }
4411
4412                 prev_cnt = sp->mc_addr_count;
4413                 sp->mc_addr_count = dev->mc_count;
4414
4415                 /* Clear out the previous list of Mc in the H/W. */
4416                 for (i = 0; i < prev_cnt; i++) {
4417                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4418                                &bar0->rmac_addr_data0_mem);
4419                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4420                                 &bar0->rmac_addr_data1_mem);
4421                         val64 = RMAC_ADDR_CMD_MEM_WE |
4422                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4423                             RMAC_ADDR_CMD_MEM_OFFSET
4424                             (MAC_MC_ADDR_START_OFFSET + i);
4425                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4426
4427                         /* Wait for command completes */
4428                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4429                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4430                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4431                                           dev->name);
4432                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4433                                 return;
4434                         }
4435                 }
4436
4437                 /* Create the new Rx filter list and update the same in H/W. */
4438                 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4439                      i++, mclist = mclist->next) {
4440                         memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4441                                ETH_ALEN);
4442                         mac_addr = 0;
4443                         for (j = 0; j < ETH_ALEN; j++) {
4444                                 mac_addr |= mclist->dmi_addr[j];
4445                                 mac_addr <<= 8;
4446                         }
4447                         mac_addr >>= 8;
4448                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4449                                &bar0->rmac_addr_data0_mem);
4450                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4451                                 &bar0->rmac_addr_data1_mem);
4452                         val64 = RMAC_ADDR_CMD_MEM_WE |
4453                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4454                             RMAC_ADDR_CMD_MEM_OFFSET
4455                             (i + MAC_MC_ADDR_START_OFFSET);
4456                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4457
4458                         /* Wait for command completes */
4459                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4460                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4461                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4462                                           dev->name);
4463                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4464                                 return;
4465                         }
4466                 }
4467         }
4468 }
4469
4470 /**
4471  *  s2io_set_mac_addr - Programs the Xframe mac address
4472  *  @dev : pointer to the device structure.
4473  *  @addr: a uchar pointer to the new mac address which is to be set.
4474  *  Description : This procedure will program the Xframe to receive
4475  *  frames with new Mac Address
4476  *  Return value: SUCCESS on success and an appropriate (-)ve integer
4477  *  as defined in errno.h file on failure.
4478  */
4479
4480 static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4481 {
4482         nic_t *sp = dev->priv;
4483         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4484         register u64 val64, mac_addr = 0;
4485         int i;
4486
4487         /*
4488          * Set the new MAC address as the new unicast filter and reflect this
4489          * change on the device address registered with the OS. It will be
4490          * at offset 0.
4491          */
4492         for (i = 0; i < ETH_ALEN; i++) {
4493                 mac_addr <<= 8;
4494                 mac_addr |= addr[i];
4495         }
4496
4497         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4498                &bar0->rmac_addr_data0_mem);
4499
4500         val64 =
4501             RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4502             RMAC_ADDR_CMD_MEM_OFFSET(0);
4503         writeq(val64, &bar0->rmac_addr_cmd_mem);
4504         /* Wait till command completes */
4505         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4506                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4507                 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4508                 return FAILURE;
4509         }
4510
4511         return SUCCESS;
4512 }
4513
4514 /**
4515  * s2io_ethtool_sset - Sets different link parameters.
4516  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
4517  * @info: pointer to the structure with parameters given by ethtool to set
4518  * link information.
4519  * Description:
4520  * The function sets different link parameters provided by the user onto
4521  * the NIC.
4522  * Return value:
4523  * 0 on success.
4524 */
4525
4526 static int s2io_ethtool_sset(struct net_device *dev,
4527                              struct ethtool_cmd *info)
4528 {
4529         nic_t *sp = dev->priv;
4530         if ((info->autoneg == AUTONEG_ENABLE) ||
4531             (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4532                 return -EINVAL;
4533         else {
4534                 s2io_close(sp->dev);
4535                 s2io_open(sp->dev);
4536         }
4537
4538         return 0;
4539 }
4540
4541 /**
4542  * s2io_ethtol_gset - Return link specific information.
4543  * @sp : private member of the device structure, pointer to the
4544  *      s2io_nic structure.
4545  * @info : pointer to the structure with parameters given by ethtool
4546  * to return link information.
4547  * Description:
4548  * Returns link specific information like speed, duplex etc.. to ethtool.
4549  * Return value :
4550  * return 0 on success.
4551  */
4552
4553 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4554 {
4555         nic_t *sp = dev->priv;
4556         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4557         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4558         info->port = PORT_FIBRE;
4559         /* info->transceiver?? TODO */
4560
4561         if (netif_carrier_ok(sp->dev)) {
4562                 info->speed = 10000;
4563                 info->duplex = DUPLEX_FULL;
4564         } else {
4565                 info->speed = -1;
4566                 info->duplex = -1;
4567         }
4568
4569         info->autoneg = AUTONEG_DISABLE;
4570         return 0;
4571 }
4572
4573 /**
4574  * s2io_ethtool_gdrvinfo - Returns driver specific information.
4575  * @sp : private member of the device structure, which is a pointer to the
4576  * s2io_nic structure.
4577  * @info : pointer to the structure with parameters given by ethtool to
4578  * return driver information.
4579  * Description:
4580  * Returns driver specefic information like name, version etc.. to ethtool.
4581  * Return value:
4582  *  void
4583  */
4584
4585 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4586                                   struct ethtool_drvinfo *info)
4587 {
4588         nic_t *sp = dev->priv;
4589
4590         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4591         strncpy(info->version, s2io_driver_version, sizeof(info->version));
4592         strncpy(info->fw_version, "", sizeof(info->fw_version));
4593         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
4594         info->regdump_len = XENA_REG_SPACE;
4595         info->eedump_len = XENA_EEPROM_SPACE;
4596         info->testinfo_len = S2IO_TEST_LEN;
4597         info->n_stats = S2IO_STAT_LEN;
4598 }
4599
4600 /**
4601  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
4602  *  @sp: private member of the device structure, which is a pointer to the
4603  *  s2io_nic structure.
4604  *  @regs : pointer to the structure with parameters given by ethtool for
4605  *  dumping the registers.
4606  *  @reg_space: The input argumnet into which all the registers are dumped.
4607  *  Description:
4608  *  Dumps the entire register space of xFrame NIC into the user given
4609  *  buffer area.
4610  * Return value :
4611  * void .
4612 */
4613
4614 static void s2io_ethtool_gregs(struct net_device *dev,
4615                                struct ethtool_regs *regs, void *space)
4616 {
4617         int i;
4618         u64 reg;
4619         u8 *reg_space = (u8 *) space;
4620         nic_t *sp = dev->priv;
4621
4622         regs->len = XENA_REG_SPACE;
4623         regs->version = sp->pdev->subsystem_device;
4624
4625         for (i = 0; i < regs->len; i += 8) {
4626                 reg = readq(sp->bar0 + i);
4627                 memcpy((reg_space + i), &reg, 8);
4628         }
4629 }
4630
4631 /**
4632  *  s2io_phy_id  - timer function that alternates adapter LED.
4633  *  @data : address of the private member of the device structure, which
4634  *  is a pointer to the s2io_nic structure, provided as an u32.
4635  * Description: This is actually the timer function that alternates the
4636  * adapter LED bit of the adapter control bit to set/reset every time on
4637  * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
4638  *  once every second.
4639 */
4640 static void s2io_phy_id(unsigned long data)
4641 {
4642         nic_t *sp = (nic_t *) data;
4643         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4644         u64 val64 = 0;
4645         u16 subid;
4646
4647         subid = sp->pdev->subsystem_device;
4648         if ((sp->device_type == XFRAME_II_DEVICE) ||
4649                    ((subid & 0xFF) >= 0x07)) {
4650                 val64 = readq(&bar0->gpio_control);
4651                 val64 ^= GPIO_CTRL_GPIO_0;
4652                 writeq(val64, &bar0->gpio_control);
4653         } else {
4654                 val64 = readq(&bar0->adapter_control);
4655                 val64 ^= ADAPTER_LED_ON;
4656                 writeq(val64, &bar0->adapter_control);
4657         }
4658
4659         mod_timer(&sp->id_timer, jiffies + HZ / 2);
4660 }
4661
4662 /**
4663  * s2io_ethtool_idnic - To physically identify the nic on the system.
4664  * @sp : private member of the device structure, which is a pointer to the
4665  * s2io_nic structure.
4666  * @id : pointer to the structure with identification parameters given by
4667  * ethtool.
4668  * Description: Used to physically identify the NIC on the system.
4669  * The Link LED will blink for a time specified by the user for
4670  * identification.
4671  * NOTE: The Link has to be Up to be able to blink the LED. Hence
4672  * identification is possible only if it's link is up.
4673  * Return value:
4674  * int , returns 0 on success
4675  */
4676
4677 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4678 {
4679         u64 val64 = 0, last_gpio_ctrl_val;
4680         nic_t *sp = dev->priv;
4681         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4682         u16 subid;
4683
4684         subid = sp->pdev->subsystem_device;
4685         last_gpio_ctrl_val = readq(&bar0->gpio_control);
4686         if ((sp->device_type == XFRAME_I_DEVICE) &&
4687                 ((subid & 0xFF) < 0x07)) {
4688                 val64 = readq(&bar0->adapter_control);
4689                 if (!(val64 & ADAPTER_CNTL_EN)) {
4690                         printk(KERN_ERR
4691                                "Adapter Link down, cannot blink LED\n");
4692                         return -EFAULT;
4693                 }
4694         }
4695         if (sp->id_timer.function == NULL) {
4696                 init_timer(&sp->id_timer);
4697                 sp->id_timer.function = s2io_phy_id;
4698                 sp->id_timer.data = (unsigned long) sp;
4699         }
4700         mod_timer(&sp->id_timer, jiffies);
4701         if (data)
4702                 msleep_interruptible(data * HZ);
4703         else
4704                 msleep_interruptible(MAX_FLICKER_TIME);
4705         del_timer_sync(&sp->id_timer);
4706
4707         if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
4708                 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4709                 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4710         }
4711
4712         return 0;
4713 }
4714
4715 /**
4716  * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
4717  * @sp : private member of the device structure, which is a pointer to the
4718  *      s2io_nic structure.
4719  * @ep : pointer to the structure with pause parameters given by ethtool.
4720  * Description:
4721  * Returns the Pause frame generation and reception capability of the NIC.
4722  * Return value:
4723  *  void
4724  */
4725 static void s2io_ethtool_getpause_data(struct net_device *dev,
4726                                        struct ethtool_pauseparam *ep)
4727 {
4728         u64 val64;
4729         nic_t *sp = dev->priv;
4730         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4731
4732         val64 = readq(&bar0->rmac_pause_cfg);
4733         if (val64 & RMAC_PAUSE_GEN_ENABLE)
4734                 ep->tx_pause = TRUE;
4735         if (val64 & RMAC_PAUSE_RX_ENABLE)
4736                 ep->rx_pause = TRUE;
4737         ep->autoneg = FALSE;
4738 }
4739
4740 /**
4741  * s2io_ethtool_setpause_data -  set/reset pause frame generation.
4742  * @sp : private member of the device structure, which is a pointer to the
4743  *      s2io_nic structure.
4744  * @ep : pointer to the structure with pause parameters given by ethtool.
4745  * Description:
4746  * It can be used to set or reset Pause frame generation or reception
4747  * support of the NIC.
4748  * Return value:
4749  * int, returns 0 on Success
4750  */
4751
4752 static int s2io_ethtool_setpause_data(struct net_device *dev,
4753                                struct ethtool_pauseparam *ep)
4754 {
4755         u64 val64;
4756         nic_t *sp = dev->priv;
4757         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4758
4759         val64 = readq(&bar0->rmac_pause_cfg);
4760         if (ep->tx_pause)
4761                 val64 |= RMAC_PAUSE_GEN_ENABLE;
4762         else
4763                 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4764         if (ep->rx_pause)
4765                 val64 |= RMAC_PAUSE_RX_ENABLE;
4766         else
4767                 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4768         writeq(val64, &bar0->rmac_pause_cfg);
4769         return 0;
4770 }
4771
4772 /**
4773  * read_eeprom - reads 4 bytes of data from user given offset.
4774  * @sp : private member of the device structure, which is a pointer to the
4775  *      s2io_nic structure.
4776  * @off : offset at which the data must be written
4777  * @data : Its an output parameter where the data read at the given
4778  *      offset is stored.
4779  * Description:
4780  * Will read 4 bytes of data from the user given offset and return the
4781  * read data.
4782  * NOTE: Will allow to read only part of the EEPROM visible through the
4783  *   I2C bus.
4784  * Return value:
4785  *  -1 on failure and 0 on success.
4786  */
4787
4788 #define S2IO_DEV_ID             5
4789 static int read_eeprom(nic_t * sp, int off, u64 * data)
4790 {
4791         int ret = -1;
4792         u32 exit_cnt = 0;
4793         u64 val64;
4794         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4795
4796         if (sp->device_type == XFRAME_I_DEVICE) {
4797                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4798                     I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4799                     I2C_CONTROL_CNTL_START;
4800                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4801
4802                 while (exit_cnt < 5) {
4803                         val64 = readq(&bar0->i2c_control);
4804                         if (I2C_CONTROL_CNTL_END(val64)) {
4805                                 *data = I2C_CONTROL_GET_DATA(val64);
4806                                 ret = 0;
4807                                 break;
4808                         }
4809                         msleep(50);
4810                         exit_cnt++;
4811                 }
4812         }
4813
4814         if (sp->device_type == XFRAME_II_DEVICE) {
4815                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4816                         SPI_CONTROL_BYTECNT(0x3) |
4817                         SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4818                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4819                 val64 |= SPI_CONTROL_REQ;
4820                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4821                 while (exit_cnt < 5) {
4822                         val64 = readq(&bar0->spi_control);
4823                         if (val64 & SPI_CONTROL_NACK) {
4824                                 ret = 1;
4825                                 break;
4826                         } else if (val64 & SPI_CONTROL_DONE) {
4827                                 *data = readq(&bar0->spi_data);
4828                                 *data &= 0xffffff;
4829                                 ret = 0;
4830                                 break;
4831                         }
4832                         msleep(50);
4833                         exit_cnt++;
4834                 }
4835         }
4836         return ret;
4837 }
4838
4839 /**
4840  *  write_eeprom - actually writes the relevant part of the data value.
4841  *  @sp : private member of the device structure, which is a pointer to the
4842  *       s2io_nic structure.
4843  *  @off : offset at which the data must be written
4844  *  @data : The data that is to be written
4845  *  @cnt : Number of bytes of the data that are actually to be written into
4846  *  the Eeprom. (max of 3)
4847  * Description:
4848  *  Actually writes the relevant part of the data value into the Eeprom
4849  *  through the I2C bus.
4850  * Return value:
4851  *  0 on success, -1 on failure.
4852  */
4853
4854 static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
4855 {
4856         int exit_cnt = 0, ret = -1;
4857         u64 val64;
4858         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4859
4860         if (sp->device_type == XFRAME_I_DEVICE) {
4861                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4862                     I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
4863                     I2C_CONTROL_CNTL_START;
4864                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4865
4866                 while (exit_cnt < 5) {
4867                         val64 = readq(&bar0->i2c_control);
4868                         if (I2C_CONTROL_CNTL_END(val64)) {
4869                                 if (!(val64 & I2C_CONTROL_NACK))
4870                                         ret = 0;
4871                                 break;
4872                         }
4873                         msleep(50);
4874                         exit_cnt++;
4875                 }
4876         }
4877
4878         if (sp->device_type == XFRAME_II_DEVICE) {
4879                 int write_cnt = (cnt == 8) ? 0 : cnt;
4880                 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
4881
4882                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4883                         SPI_CONTROL_BYTECNT(write_cnt) |
4884                         SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
4885                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4886                 val64 |= SPI_CONTROL_REQ;
4887                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4888                 while (exit_cnt < 5) {
4889                         val64 = readq(&bar0->spi_control);
4890                         if (val64 & SPI_CONTROL_NACK) {
4891                                 ret = 1;
4892                                 break;
4893                         } else if (val64 & SPI_CONTROL_DONE) {
4894                                 ret = 0;
4895                                 break;
4896                         }
4897                         msleep(50);
4898                         exit_cnt++;
4899                 }
4900         }
4901         return ret;
4902 }
4903 static void s2io_vpd_read(nic_t *nic)
4904 {
4905         u8 *vpd_data;
4906         u8 data;
4907         int i=0, cnt, fail = 0;
4908         int vpd_addr = 0x80;
4909
4910         if (nic->device_type == XFRAME_II_DEVICE) {
4911                 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
4912                 vpd_addr = 0x80;
4913         }
4914         else {
4915                 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
4916                 vpd_addr = 0x50;
4917         }
4918
4919         vpd_data = kmalloc(256, GFP_KERNEL);
4920         if (!vpd_data)
4921                 return;
4922
4923         for (i = 0; i < 256; i +=4 ) {
4924                 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
4925                 pci_read_config_byte(nic->pdev,  (vpd_addr + 2), &data);
4926                 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
4927                 for (cnt = 0; cnt <5; cnt++) {
4928                         msleep(2);
4929                         pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
4930                         if (data == 0x80)
4931                                 break;
4932                 }
4933                 if (cnt >= 5) {
4934                         DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
4935                         fail = 1;
4936                         break;
4937                 }
4938                 pci_read_config_dword(nic->pdev,  (vpd_addr + 4),
4939                                       (u32 *)&vpd_data[i]);
4940         }
4941         if ((!fail) && (vpd_data[1] < VPD_PRODUCT_NAME_LEN)) {
4942                 memset(nic->product_name, 0, vpd_data[1]);
4943                 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
4944         }
4945         kfree(vpd_data);
4946 }
4947
4948 /**
4949  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
4950  *  @sp : private member of the device structure, which is a pointer to the *       s2io_nic structure.
4951  *  @eeprom : pointer to the user level structure provided by ethtool,
4952  *  containing all relevant information.
4953  *  @data_buf : user defined value to be written into Eeprom.
4954  *  Description: Reads the values stored in the Eeprom at given offset
4955  *  for a given length. Stores these values int the input argument data
4956  *  buffer 'data_buf' and returns these to the caller (ethtool.)
4957  *  Return value:
4958  *  int  0 on success
4959  */
4960
4961 static int s2io_ethtool_geeprom(struct net_device *dev,
4962                          struct ethtool_eeprom *eeprom, u8 * data_buf)
4963 {
4964         u32 i, valid;
4965         u64 data;
4966         nic_t *sp = dev->priv;
4967
4968         eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
4969
4970         if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
4971                 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
4972
4973         for (i = 0; i < eeprom->len; i += 4) {
4974                 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
4975                         DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
4976                         return -EFAULT;
4977                 }
4978                 valid = INV(data);
4979                 memcpy((data_buf + i), &valid, 4);
4980         }
4981         return 0;
4982 }
4983
4984 /**
4985  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
4986  *  @sp : private member of the device structure, which is a pointer to the
4987  *  s2io_nic structure.
4988  *  @eeprom : pointer to the user level structure provided by ethtool,
4989  *  containing all relevant information.
4990  *  @data_buf ; user defined value to be written into Eeprom.
4991  *  Description:
4992  *  Tries to write the user provided value in the Eeprom, at the offset
4993  *  given by the user.
4994  *  Return value:
4995  *  0 on success, -EFAULT on failure.
4996  */
4997
4998 static int s2io_ethtool_seeprom(struct net_device *dev,
4999                                 struct ethtool_eeprom *eeprom,
5000                                 u8 * data_buf)
5001 {
5002         int len = eeprom->len, cnt = 0;
5003         u64 valid = 0, data;
5004         nic_t *sp = dev->priv;
5005
5006         if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5007                 DBG_PRINT(ERR_DBG,
5008                           "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5009                 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5010                           eeprom->magic);
5011                 return -EFAULT;
5012         }
5013
5014         while (len) {
5015                 data = (u32) data_buf[cnt] & 0x000000FF;
5016                 if (data) {
5017                         valid = (u32) (data << 24);
5018                 } else
5019                         valid = data;
5020
5021                 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5022                         DBG_PRINT(ERR_DBG,
5023                                   "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5024                         DBG_PRINT(ERR_DBG,
5025                                   "write into the specified offset\n");
5026                         return -EFAULT;
5027                 }
5028                 cnt++;
5029                 len--;
5030         }
5031
5032         return 0;
5033 }
5034
5035 /**
5036  * s2io_register_test - reads and writes into all clock domains.
5037  * @sp : private member of the device structure, which is a pointer to the
5038  * s2io_nic structure.
5039  * @data : variable that returns the result of each of the test conducted b
5040  * by the driver.
5041  * Description:
5042  * Read and write into all clock domains. The NIC has 3 clock domains,
5043  * see that registers in all the three regions are accessible.
5044  * Return value:
5045  * 0 on success.
5046  */
5047
5048 static int s2io_register_test(nic_t * sp, uint64_t * data)
5049 {
5050         XENA_dev_config_t __iomem *bar0 = sp->bar0;
5051         u64 val64 = 0, exp_val;
5052         int fail = 0;
5053
5054         val64 = readq(&bar0->pif_rd_swapper_fb);
5055         if (val64 != 0x123456789abcdefULL) {
5056                 fail = 1;
5057                 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5058         }
5059
5060         val64 = readq(&bar0->rmac_pause_cfg);
5061         if (val64 != 0xc000ffff00000000ULL) {
5062                 fail = 1;
5063                 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5064         }
5065
5066         val64 = readq(&bar0->rx_queue_cfg);
5067         if (sp->device_type == XFRAME_II_DEVICE)
5068                 exp_val = 0x0404040404040404ULL;
5069         else
5070                 exp_val = 0x0808080808080808ULL;
5071         if (val64 != exp_val) {
5072                 fail = 1;
5073                 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5074         }
5075
5076         val64 = readq(&bar0->xgxs_efifo_cfg);
5077         if (val64 != 0x000000001923141EULL) {
5078                 fail = 1;
5079                 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5080         }
5081
5082         val64 = 0x5A5A5A5A5A5A5A5AULL;
5083         writeq(val64, &bar0->xmsi_data);
5084         val64 = readq(&bar0->xmsi_data);
5085         if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5086                 fail = 1;
5087                 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5088         }
5089
5090         val64 = 0xA5A5A5A5A5A5A5A5ULL;
5091         writeq(val64, &bar0->xmsi_data);
5092         val64 = readq(&bar0->xmsi_data);
5093         if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5094                 fail = 1;
5095                 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5096         }
5097
5098         *data = fail;
5099         return fail;
5100 }
5101
5102 /**
5103  * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5104  * @sp : private member of the device structure, which is a pointer to the
5105  * s2io_nic structure.
5106  * @data:variable that returns the result of each of the test conducted by
5107  * the driver.
5108  * Description:
5109  * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5110  * register.
5111  * Return value:
5112  * 0 on success.
5113  */
5114
5115 static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
5116 {
5117         int fail = 0;
5118         u64 ret_data, org_4F0, org_7F0;
5119         u8 saved_4F0 = 0, saved_7F0 = 0;
5120         struct net_device *dev = sp->dev;
5121
5122         /* Test Write Error at offset 0 */
5123         /* Note that SPI interface allows write access to all areas
5124          * of EEPROM. Hence doing all negative testing only for Xframe I.
5125          */
5126         if (sp->device_type == XFRAME_I_DEVICE)
5127                 if (!write_eeprom(sp, 0, 0, 3))
5128                         fail = 1;
5129
5130         /* Save current values at offsets 0x4F0 and 0x7F0 */
5131         if (!read_eeprom(sp, 0x4F0, &org_4F0))
5132                 saved_4F0 = 1;
5133         if (!read_eeprom(sp, 0x7F0, &org_7F0))
5134                 saved_7F0 = 1;
5135
5136         /* Test Write at offset 4f0 */
5137         if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5138                 fail = 1;
5139         if (read_eeprom(sp, 0x4F0, &ret_data))
5140                 fail = 1;
5141
5142         if (ret_data != 0x012345) {
5143                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5144                         "Data written %llx Data read %llx\n",
5145                         dev->name, (unsigned long long)0x12345,
5146                         (unsigned long long)ret_data);
5147                 fail = 1;
5148         }
5149
5150         /* Reset the EEPROM data go FFFF */
5151         write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
5152
5153         /* Test Write Request Error at offset 0x7c */
5154         if (sp->device_type == XFRAME_I_DEVICE)
5155                 if (!write_eeprom(sp, 0x07C, 0, 3))
5156                         fail = 1;
5157
5158         /* Test Write Request at offset 0x7f0 */
5159         if (write_eeprom(sp, 0x7F0, 0x012345, 3))
5160                 fail = 1;
5161         if (read_eeprom(sp, 0x7F0, &ret_data))
5162                 fail = 1;
5163
5164         if (ret_data != 0x012345) {
5165                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5166                         "Data written %llx Data read %llx\n",
5167                         dev->name, (unsigned long long)0x12345,
5168                         (unsigned long long)ret_data);
5169                 fail = 1;
5170         }
5171
5172         /* Reset the EEPROM data go FFFF */
5173         write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
5174
5175         if (sp->device_type == XFRAME_I_DEVICE) {
5176                 /* Test Write Error at offset 0x80 */
5177                 if (!write_eeprom(sp, 0x080, 0, 3))
5178                         fail = 1;
5179
5180                 /* Test Write Error at offset 0xfc */
5181                 if (!write_eeprom(sp, 0x0FC, 0, 3))
5182                         fail = 1;
5183
5184                 /* Test Write Error at offset 0x100 */
5185                 if (!write_eeprom(sp, 0x100, 0, 3))
5186                         fail = 1;
5187
5188                 /* Test Write Error at offset 4ec */
5189                 if (!write_eeprom(sp, 0x4EC, 0, 3))
5190                         fail = 1;
5191         }
5192
5193         /* Restore values at offsets 0x4F0 and 0x7F0 */
5194         if (saved_4F0)
5195                 write_eeprom(sp, 0x4F0, org_4F0, 3);
5196         if (saved_7F0)
5197                 write_eeprom(sp, 0x7F0, org_7F0, 3);
5198
5199         *data = fail;
5200         return fail;
5201 }
5202
5203 /**
5204  * s2io_bist_test - invokes the MemBist test of the card .
5205  * @sp : private member of the device structure, which is a pointer to the
5206  * s2io_nic structure.
5207  * @data:variable that returns the result of each of the test conducted by
5208  * the driver.
5209  * Description:
5210  * This invokes the MemBist test of the card. We give around
5211  * 2 secs time for the Test to complete. If it's still not complete
5212  * within this peiod, we consider that the test failed.
5213  * Return value:
5214  * 0 on success and -1 on failure.
5215  */
5216
5217 static int s2io_bist_test(nic_t * sp, uint64_t * data)
5218 {
5219         u8 bist = 0;
5220         int cnt = 0, ret = -1;
5221
5222         pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5223         bist |= PCI_BIST_START;
5224         pci_write_config_word(sp->pdev, PCI_BIST, bist);
5225
5226         while (cnt < 20) {
5227                 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5228                 if (!(bist & PCI_BIST_START)) {
5229                         *data = (bist & PCI_BIST_CODE_MASK);
5230                         ret = 0;
5231                         break;
5232                 }
5233                 msleep(100);
5234                 cnt++;
5235         }
5236
5237         return ret;
5238 }
5239
5240 /**
5241  * s2io-link_test - verifies the link state of the nic
5242  * @sp ; private member of the device structure, which is a pointer to the
5243  * s2io_nic structure.
5244  * @data: variable that returns the result of each of the test conducted by
5245  * the driver.
5246  * Description:
5247  * The function verifies the link state of the NIC and updates the input
5248  * argument 'data' appropriately.
5249  * Return value:
5250  * 0 on success.
5251  */
5252
5253 static int s2io_link_test(nic_t * sp, uint64_t * data)
5254 {
5255         XENA_dev_config_t __iomem *bar0 = sp->bar0;
5256         u64 val64;
5257
5258         val64 = readq(&bar0->adapter_status);
5259         if(!(LINK_IS_UP(val64)))
5260                 *data = 1;
5261         else
5262                 *data = 0;
5263
5264         return *data;
5265 }
5266
5267 /**
5268  * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5269  * @sp - private member of the device structure, which is a pointer to the
5270  * s2io_nic structure.
5271  * @data - variable that returns the result of each of the test
5272  * conducted by the driver.
5273  * Description:
5274  *  This is one of the offline test that tests the read and write
5275  *  access to the RldRam chip on the NIC.
5276  * Return value:
5277  *  0 on success.
5278  */
5279
5280 static int s2io_rldram_test(nic_t * sp, uint64_t * data)
5281 {
5282         XENA_dev_config_t __iomem *bar0 = sp->bar0;
5283         u64 val64;
5284         int cnt, iteration = 0, test_fail = 0;
5285
5286         val64 = readq(&bar0->adapter_control);
5287         val64 &= ~ADAPTER_ECC_EN;
5288         writeq(val64, &bar0->adapter_control);
5289
5290         val64 = readq(&bar0->mc_rldram_test_ctrl);
5291         val64 |= MC_RLDRAM_TEST_MODE;
5292         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5293
5294         val64 = readq(&bar0->mc_rldram_mrs);
5295         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5296         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5297
5298         val64 |= MC_RLDRAM_MRS_ENABLE;
5299         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5300
5301         while (iteration < 2) {
5302                 val64 = 0x55555555aaaa0000ULL;
5303                 if (iteration == 1) {
5304                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5305                 }
5306                 writeq(val64, &bar0->mc_rldram_test_d0);
5307
5308                 val64 = 0xaaaa5a5555550000ULL;
5309                 if (iteration == 1) {
5310                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5311                 }
5312                 writeq(val64, &bar0->mc_rldram_test_d1);
5313
5314                 val64 = 0x55aaaaaaaa5a0000ULL;
5315                 if (iteration == 1) {
5316                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5317                 }
5318                 writeq(val64, &bar0->mc_rldram_test_d2);
5319
5320                 val64 = (u64) (0x0000003ffffe0100ULL);
5321                 writeq(val64, &bar0->mc_rldram_test_add);
5322
5323                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5324                         MC_RLDRAM_TEST_GO;
5325                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5326
5327                 for (cnt = 0; cnt < 5; cnt++) {
5328                         val64 = readq(&bar0->mc_rldram_test_ctrl);
5329                         if (val64 & MC_RLDRAM_TEST_DONE)
5330                                 break;
5331                         msleep(200);
5332                 }
5333
5334                 if (cnt == 5)
5335                         break;
5336
5337                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5338                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5339
5340                 for (cnt = 0; cnt < 5; cnt++) {
5341                         val64 = readq(&bar0->mc_rldram_test_ctrl);
5342                         if (val64 & MC_RLDRAM_TEST_DONE)
5343                                 break;
5344                         msleep(500);
5345                 }
5346
5347                 if (cnt == 5)
5348                         break;
5349
5350                 val64 = readq(&bar0->mc_rldram_test_ctrl);
5351                 if (!(val64 & MC_RLDRAM_TEST_PASS))
5352                         test_fail = 1;
5353
5354                 iteration++;
5355         }
5356
5357         *data = test_fail;
5358
5359         /* Bring the adapter out of test mode */
5360         SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5361
5362         return test_fail;
5363 }
5364
5365 /**
5366  *  s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5367  *  @sp : private member of the device structure, which is a pointer to the
5368  *  s2io_nic structure.
5369  *  @ethtest : pointer to a ethtool command specific structure that will be
5370  *  returned to the user.
5371  *  @data : variable that returns the result of each of the test
5372  * conducted by the driver.
5373  * Description:
5374  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
5375  *  the health of the card.
5376  * Return value:
5377  *  void
5378  */
5379
5380 static void s2io_ethtool_test(struct net_device *dev,
5381                               struct ethtool_test *ethtest,
5382                               uint64_t * data)
5383 {
5384         nic_t *sp = dev->priv;
5385         int orig_state = netif_running(sp->dev);
5386
5387         if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5388                 /* Offline Tests. */
5389                 if (orig_state)
5390                         s2io_close(sp->dev);
5391
5392                 if (s2io_register_test(sp, &data[0]))
5393                         ethtest->flags |= ETH_TEST_FL_FAILED;
5394
5395                 s2io_reset(sp);
5396
5397                 if (s2io_rldram_test(sp, &data[3]))
5398                         ethtest->flags |= ETH_TEST_FL_FAILED;
5399
5400                 s2io_reset(sp);
5401
5402                 if (s2io_eeprom_test(sp, &data[1]))
5403                         ethtest->flags |= ETH_TEST_FL_FAILED;
5404
5405                 if (s2io_bist_test(sp, &data[4]))
5406                         ethtest->flags |= ETH_TEST_FL_FAILED;
5407
5408                 if (orig_state)
5409                         s2io_open(sp->dev);
5410
5411                 data[2] = 0;
5412         } else {
5413                 /* Online Tests. */
5414                 if (!orig_state) {
5415                         DBG_PRINT(ERR_DBG,
5416                                   "%s: is not up, cannot run test\n",
5417                                   dev->name);
5418                         data[0] = -1;
5419                         data[1] = -1;
5420                         data[2] = -1;
5421                         data[3] = -1;
5422                         data[4] = -1;
5423                 }
5424
5425                 if (s2io_link_test(sp, &data[2]))
5426                         ethtest->flags |= ETH_TEST_FL_FAILED;
5427
5428                 data[0] = 0;
5429                 data[1] = 0;
5430                 data[3] = 0;
5431                 data[4] = 0;
5432         }
5433 }
5434
5435 static void s2io_get_ethtool_stats(struct net_device *dev,
5436                                    struct ethtool_stats *estats,
5437                                    u64 * tmp_stats)
5438 {
5439         int i = 0;
5440         nic_t *sp = dev->priv;
5441         StatInfo_t *stat_info = sp->mac_control.stats_info;
5442
5443         s2io_updt_stats(sp);
5444         tmp_stats[i++] =
5445                 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32  |
5446                 le32_to_cpu(stat_info->tmac_frms);
5447         tmp_stats[i++] =
5448                 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5449                 le32_to_cpu(stat_info->tmac_data_octets);
5450         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
5451         tmp_stats[i++] =
5452                 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5453                 le32_to_cpu(stat_info->tmac_mcst_frms);
5454         tmp_stats[i++] =
5455                 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5456                 le32_to_cpu(stat_info->tmac_bcst_frms);
5457         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
5458         tmp_stats[i++] =
5459                 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5460                 le32_to_cpu(stat_info->tmac_ttl_octets);
5461         tmp_stats[i++] =
5462                 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5463                 le32_to_cpu(stat_info->tmac_ucst_frms);
5464         tmp_stats[i++] =
5465                 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5466                 le32_to_cpu(stat_info->tmac_nucst_frms);
5467         tmp_stats[i++] =
5468                 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5469                 le32_to_cpu(stat_info->tmac_any_err_frms);
5470         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
5471         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
5472         tmp_stats[i++] =
5473                 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5474                 le32_to_cpu(stat_info->tmac_vld_ip);
5475         tmp_stats[i++] =
5476                 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5477                 le32_to_cpu(stat_info->tmac_drop_ip);
5478         tmp_stats[i++] =
5479                 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5480                 le32_to_cpu(stat_info->tmac_icmp);
5481         tmp_stats[i++] =
5482                 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5483                 le32_to_cpu(stat_info->tmac_rst_tcp);
5484         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
5485         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5486                 le32_to_cpu(stat_info->tmac_udp);
5487         tmp_stats[i++] =
5488                 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5489                 le32_to_cpu(stat_info->rmac_vld_frms);
5490         tmp_stats[i++] =
5491                 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5492                 le32_to_cpu(stat_info->rmac_data_octets);
5493         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5494         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
5495         tmp_stats[i++] =
5496                 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5497                 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5498         tmp_stats[i++] =
5499                 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5500                 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
5501         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
5502         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
5503         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5504         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
5505         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
5506         tmp_stats[i++] =
5507                 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
5508                 le32_to_cpu(stat_info->rmac_ttl_octets);
5509         tmp_stats[i++] =
5510                 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
5511                 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
5512         tmp_stats[i++] =
5513                 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
5514                  << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
5515         tmp_stats[i++] =
5516                 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5517                 le32_to_cpu(stat_info->rmac_discarded_frms);
5518         tmp_stats[i++] =
5519                 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
5520                  << 32 | le32_to_cpu(stat_info->rmac_drop_events);
5521         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
5522         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
5523         tmp_stats[i++] =
5524                 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5525                 le32_to_cpu(stat_info->rmac_usized_frms);
5526         tmp_stats[i++] =
5527                 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5528                 le32_to_cpu(stat_info->rmac_osized_frms);
5529         tmp_stats[i++] =
5530                 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5531                 le32_to_cpu(stat_info->rmac_frag_frms);
5532         tmp_stats[i++] =
5533                 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5534                 le32_to_cpu(stat_info->rmac_jabber_frms);
5535         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
5536         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
5537         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
5538         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
5539         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
5540         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
5541         tmp_stats[i++] =
5542                 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
5543                 le32_to_cpu(stat_info->rmac_ip);
5544         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5545         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
5546         tmp_stats[i++] =
5547                 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
5548                 le32_to_cpu(stat_info->rmac_drop_ip);
5549         tmp_stats[i++] =
5550                 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
5551                 le32_to_cpu(stat_info->rmac_icmp);
5552         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
5553         tmp_stats[i++] =
5554                 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
5555                 le32_to_cpu(stat_info->rmac_udp);
5556         tmp_stats[i++] =
5557                 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5558                 le32_to_cpu(stat_info->rmac_err_drp_udp);
5559         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
5560         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
5561         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
5562         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
5563         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
5564         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
5565         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
5566         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
5567         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
5568         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
5569         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
5570         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
5571         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
5572         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
5573         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
5574         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
5575         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
5576         tmp_stats[i++] =
5577                 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5578                 le32_to_cpu(stat_info->rmac_pause_cnt);
5579         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_dat