dma-mapping: replace all DMA_64BIT_MASK macro with DMA_BIT_MASK(64)
[linux-3.10.git] / drivers / net / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3   Intel 10 Gigabit PCI Express Linux driver
4   Copyright(c) 1999 - 2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/ipv6.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
42
43 #include "ixgbe.h"
44 #include "ixgbe_common.h"
45
46 char ixgbe_driver_name[] = "ixgbe";
47 static const char ixgbe_driver_string[] =
48                               "Intel(R) 10 Gigabit PCI Express Network Driver";
49
50 #define DRV_VERSION "2.0.8-k2"
51 const char ixgbe_driver_version[] = DRV_VERSION;
52 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
53
54 static const struct ixgbe_info *ixgbe_info_tbl[] = {
55         [board_82598] = &ixgbe_82598_info,
56         [board_82599] = &ixgbe_82599_info,
57 };
58
59 /* ixgbe_pci_tbl - PCI Device ID Table
60  *
61  * Wildcard entries (PCI_ANY_ID) should come last
62  * Last entry must be all 0s
63  *
64  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
65  *   Class, Class Mask, private data (not used) }
66  */
67 static struct pci_device_id ixgbe_pci_tbl[] = {
68         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
69          board_82598 },
70         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
71          board_82598 },
72         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
73          board_82598 },
74         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
75          board_82598 },
76         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
77          board_82598 },
78         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
79          board_82598 },
80         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
81          board_82598 },
82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
83          board_82598 },
84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
85          board_82598 },
86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
87          board_82598 },
88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
89          board_82598 },
90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
91          board_82599 },
92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
93          board_82599 },
94
95         /* required last entry */
96         {0, }
97 };
98 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
99
100 #ifdef CONFIG_IXGBE_DCA
101 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
102                             void *p);
103 static struct notifier_block dca_notifier = {
104         .notifier_call = ixgbe_notify_dca,
105         .next          = NULL,
106         .priority      = 0
107 };
108 #endif
109
110 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
111 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
112 MODULE_LICENSE("GPL");
113 MODULE_VERSION(DRV_VERSION);
114
115 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
116
117 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
118 {
119         u32 ctrl_ext;
120
121         /* Let firmware take over control of h/w */
122         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
123         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
124                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
125 }
126
127 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
128 {
129         u32 ctrl_ext;
130
131         /* Let firmware know the driver has taken over */
132         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
133         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
134                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
135 }
136
137 /*
138  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
139  * @adapter: pointer to adapter struct
140  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
141  * @queue: queue to map the corresponding interrupt to
142  * @msix_vector: the vector to map to the corresponding queue
143  *
144  */
145 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
146                            u8 queue, u8 msix_vector)
147 {
148         u32 ivar, index;
149         struct ixgbe_hw *hw = &adapter->hw;
150         switch (hw->mac.type) {
151         case ixgbe_mac_82598EB:
152                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
153                 if (direction == -1)
154                         direction = 0;
155                 index = (((direction * 64) + queue) >> 2) & 0x1F;
156                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
157                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
158                 ivar |= (msix_vector << (8 * (queue & 0x3)));
159                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
160                 break;
161         case ixgbe_mac_82599EB:
162                 if (direction == -1) {
163                         /* other causes */
164                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
165                         index = ((queue & 1) * 8);
166                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
167                         ivar &= ~(0xFF << index);
168                         ivar |= (msix_vector << index);
169                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
170                         break;
171                 } else {
172                         /* tx or rx causes */
173                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
174                         index = ((16 * (queue & 1)) + (8 * direction));
175                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
176                         ivar &= ~(0xFF << index);
177                         ivar |= (msix_vector << index);
178                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
179                         break;
180                 }
181         default:
182                 break;
183         }
184 }
185
186 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
187                                              struct ixgbe_tx_buffer
188                                              *tx_buffer_info)
189 {
190         tx_buffer_info->dma = 0;
191         if (tx_buffer_info->skb) {
192                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
193                               DMA_TO_DEVICE);
194                 dev_kfree_skb_any(tx_buffer_info->skb);
195                 tx_buffer_info->skb = NULL;
196         }
197         tx_buffer_info->time_stamp = 0;
198         /* tx_buffer_info must be completely set up in the transmit path */
199 }
200
201 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
202                                        struct ixgbe_ring *tx_ring,
203                                        unsigned int eop)
204 {
205         struct ixgbe_hw *hw = &adapter->hw;
206
207         /* Detect a transmit hang in hardware, this serializes the
208          * check with the clearing of time_stamp and movement of eop */
209         adapter->detect_tx_hung = false;
210         if (tx_ring->tx_buffer_info[eop].time_stamp &&
211             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
212             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
213                 /* detected Tx unit hang */
214                 union ixgbe_adv_tx_desc *tx_desc;
215                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
216                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
217                         "  Tx Queue             <%d>\n"
218                         "  TDH, TDT             <%x>, <%x>\n"
219                         "  next_to_use          <%x>\n"
220                         "  next_to_clean        <%x>\n"
221                         "tx_buffer_info[next_to_clean]\n"
222                         "  time_stamp           <%lx>\n"
223                         "  jiffies              <%lx>\n",
224                         tx_ring->queue_index,
225                         IXGBE_READ_REG(hw, tx_ring->head),
226                         IXGBE_READ_REG(hw, tx_ring->tail),
227                         tx_ring->next_to_use, eop,
228                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
229                 return true;
230         }
231
232         return false;
233 }
234
235 #define IXGBE_MAX_TXD_PWR       14
236 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
237
238 /* Tx Descriptors needed, worst case */
239 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
240                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
241 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
242         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
243
244 static void ixgbe_tx_timeout(struct net_device *netdev);
245
246 /**
247  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
248  * @adapter: board private structure
249  * @tx_ring: tx ring to clean
250  *
251  * returns true if transmit work is done
252  **/
253 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
254                                struct ixgbe_ring *tx_ring)
255 {
256         struct net_device *netdev = adapter->netdev;
257         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
258         struct ixgbe_tx_buffer *tx_buffer_info;
259         unsigned int i, eop, count = 0;
260         unsigned int total_bytes = 0, total_packets = 0;
261
262         i = tx_ring->next_to_clean;
263         eop = tx_ring->tx_buffer_info[i].next_to_watch;
264         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
265
266         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
267                (count < tx_ring->work_limit)) {
268                 bool cleaned = false;
269                 for ( ; !cleaned; count++) {
270                         struct sk_buff *skb;
271                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
272                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
273                         cleaned = (i == eop);
274                         skb = tx_buffer_info->skb;
275
276                         if (cleaned && skb) {
277                                 unsigned int segs, bytecount;
278
279                                 /* gso_segs is currently only valid for tcp */
280                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
281                                 /* multiply data chunks by size of headers */
282                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
283                                             skb->len;
284                                 total_packets += segs;
285                                 total_bytes += bytecount;
286                         }
287
288                         ixgbe_unmap_and_free_tx_resource(adapter,
289                                                          tx_buffer_info);
290
291                         tx_desc->wb.status = 0;
292
293                         i++;
294                         if (i == tx_ring->count)
295                                 i = 0;
296                 }
297
298                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
299                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
300         }
301
302         tx_ring->next_to_clean = i;
303
304 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
305         if (unlikely(count && netif_carrier_ok(netdev) &&
306                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
307                 /* Make sure that anybody stopping the queue after this
308                  * sees the new next_to_clean.
309                  */
310                 smp_mb();
311                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
312                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
313                         netif_wake_subqueue(netdev, tx_ring->queue_index);
314                         ++adapter->restart_queue;
315                 }
316         }
317
318         if (adapter->detect_tx_hung) {
319                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
320                         /* schedule immediate reset if we believe we hung */
321                         DPRINTK(PROBE, INFO,
322                                 "tx hang %d detected, resetting adapter\n",
323                                 adapter->tx_timeout_count + 1);
324                         ixgbe_tx_timeout(adapter->netdev);
325                 }
326         }
327
328         /* re-arm the interrupt */
329         if (count >= tx_ring->work_limit)
330                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
331
332         tx_ring->total_bytes += total_bytes;
333         tx_ring->total_packets += total_packets;
334         tx_ring->stats.packets += total_packets;
335         tx_ring->stats.bytes += total_bytes;
336         adapter->net_stats.tx_bytes += total_bytes;
337         adapter->net_stats.tx_packets += total_packets;
338         return (count < tx_ring->work_limit);
339 }
340
341 #ifdef CONFIG_IXGBE_DCA
342 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
343                                 struct ixgbe_ring *rx_ring)
344 {
345         u32 rxctrl;
346         int cpu = get_cpu();
347         int q = rx_ring - adapter->rx_ring;
348
349         if (rx_ring->cpu != cpu) {
350                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
351                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
352                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
353                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
354                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
355                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
356                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
357                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
358                 }
359                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
360                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
361                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
362                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
363                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
364                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
365                 rx_ring->cpu = cpu;
366         }
367         put_cpu();
368 }
369
370 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
371                                 struct ixgbe_ring *tx_ring)
372 {
373         u32 txctrl;
374         int cpu = get_cpu();
375         int q = tx_ring - adapter->tx_ring;
376
377         if (tx_ring->cpu != cpu) {
378                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
379                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
380                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
381                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
382                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
383                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
384                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
385                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
386                 }
387                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
388                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
389                 tx_ring->cpu = cpu;
390         }
391         put_cpu();
392 }
393
394 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
395 {
396         int i;
397
398         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
399                 return;
400
401         for (i = 0; i < adapter->num_tx_queues; i++) {
402                 adapter->tx_ring[i].cpu = -1;
403                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
404         }
405         for (i = 0; i < adapter->num_rx_queues; i++) {
406                 adapter->rx_ring[i].cpu = -1;
407                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
408         }
409 }
410
411 static int __ixgbe_notify_dca(struct device *dev, void *data)
412 {
413         struct net_device *netdev = dev_get_drvdata(dev);
414         struct ixgbe_adapter *adapter = netdev_priv(netdev);
415         unsigned long event = *(unsigned long *)data;
416
417         switch (event) {
418         case DCA_PROVIDER_ADD:
419                 /* if we're already enabled, don't do it again */
420                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
421                         break;
422                 /* Always use CB2 mode, difference is masked
423                  * in the CB driver. */
424                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
425                 if (dca_add_requester(dev) == 0) {
426                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
427                         ixgbe_setup_dca(adapter);
428                         break;
429                 }
430                 /* Fall Through since DCA is disabled. */
431         case DCA_PROVIDER_REMOVE:
432                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
433                         dca_remove_requester(dev);
434                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
435                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
436                 }
437                 break;
438         }
439
440         return 0;
441 }
442
443 #endif /* CONFIG_IXGBE_DCA */
444 /**
445  * ixgbe_receive_skb - Send a completed packet up the stack
446  * @adapter: board private structure
447  * @skb: packet to send up
448  * @status: hardware indication of status of receive
449  * @rx_ring: rx descriptor ring (for a specific queue) to setup
450  * @rx_desc: rx descriptor
451  **/
452 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
453                               struct sk_buff *skb, u8 status,
454                               union ixgbe_adv_rx_desc *rx_desc)
455 {
456         struct ixgbe_adapter *adapter = q_vector->adapter;
457         struct napi_struct *napi = &q_vector->napi;
458         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
459         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
460
461         skb_record_rx_queue(skb, q_vector - &adapter->q_vector[0]);
462         if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
463                 if (adapter->vlgrp && is_vlan && (tag != 0))
464                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
465                 else
466                         napi_gro_receive(napi, skb);
467         } else {
468                 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
469                         if (adapter->vlgrp && is_vlan && (tag != 0))
470                                 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
471                         else
472                                 netif_receive_skb(skb);
473                 } else {
474                         if (adapter->vlgrp && is_vlan && (tag != 0))
475                                 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
476                         else
477                                 netif_rx(skb);
478                 }
479         }
480 }
481
482 /**
483  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
484  * @adapter: address of board private structure
485  * @status_err: hardware indication of status of receive
486  * @skb: skb currently being received and modified
487  **/
488 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
489                                      u32 status_err, struct sk_buff *skb)
490 {
491         skb->ip_summed = CHECKSUM_NONE;
492
493         /* Rx csum disabled */
494         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
495                 return;
496
497         /* if IP and error */
498         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
499             (status_err & IXGBE_RXDADV_ERR_IPE)) {
500                 adapter->hw_csum_rx_error++;
501                 return;
502         }
503
504         if (!(status_err & IXGBE_RXD_STAT_L4CS))
505                 return;
506
507         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
508                 adapter->hw_csum_rx_error++;
509                 return;
510         }
511
512         /* It must be a TCP or UDP packet with a valid checksum */
513         skb->ip_summed = CHECKSUM_UNNECESSARY;
514         adapter->hw_csum_rx_good++;
515 }
516
517 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
518                                          struct ixgbe_ring *rx_ring, u32 val)
519 {
520         /*
521          * Force memory writes to complete before letting h/w
522          * know there are new descriptors to fetch.  (Only
523          * applicable for weak-ordered memory model archs,
524          * such as IA-64).
525          */
526         wmb();
527         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
528 }
529
530 /**
531  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
532  * @adapter: address of board private structure
533  **/
534 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
535                                    struct ixgbe_ring *rx_ring,
536                                    int cleaned_count)
537 {
538         struct pci_dev *pdev = adapter->pdev;
539         union ixgbe_adv_rx_desc *rx_desc;
540         struct ixgbe_rx_buffer *bi;
541         unsigned int i;
542         unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
543
544         i = rx_ring->next_to_use;
545         bi = &rx_ring->rx_buffer_info[i];
546
547         while (cleaned_count--) {
548                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
549
550                 if (!bi->page_dma &&
551                     (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
552                         if (!bi->page) {
553                                 bi->page = alloc_page(GFP_ATOMIC);
554                                 if (!bi->page) {
555                                         adapter->alloc_rx_page_failed++;
556                                         goto no_buffers;
557                                 }
558                                 bi->page_offset = 0;
559                         } else {
560                                 /* use a half page if we're re-using */
561                                 bi->page_offset ^= (PAGE_SIZE / 2);
562                         }
563
564                         bi->page_dma = pci_map_page(pdev, bi->page,
565                                                     bi->page_offset,
566                                                     (PAGE_SIZE / 2),
567                                                     PCI_DMA_FROMDEVICE);
568                 }
569
570                 if (!bi->skb) {
571                         struct sk_buff *skb;
572                         skb = netdev_alloc_skb(adapter->netdev, bufsz);
573
574                         if (!skb) {
575                                 adapter->alloc_rx_buff_failed++;
576                                 goto no_buffers;
577                         }
578
579                         /*
580                          * Make buffer alignment 2 beyond a 16 byte boundary
581                          * this will result in a 16 byte aligned IP header after
582                          * the 14 byte MAC header is removed
583                          */
584                         skb_reserve(skb, NET_IP_ALIGN);
585
586                         bi->skb = skb;
587                         bi->dma = pci_map_single(pdev, skb->data, bufsz,
588                                                  PCI_DMA_FROMDEVICE);
589                 }
590                 /* Refresh the desc even if buffer_addrs didn't change because
591                  * each write-back erases this info. */
592                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
593                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
594                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
595                 } else {
596                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
597                 }
598
599                 i++;
600                 if (i == rx_ring->count)
601                         i = 0;
602                 bi = &rx_ring->rx_buffer_info[i];
603         }
604
605 no_buffers:
606         if (rx_ring->next_to_use != i) {
607                 rx_ring->next_to_use = i;
608                 if (i-- == 0)
609                         i = (rx_ring->count - 1);
610
611                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
612         }
613 }
614
615 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
616 {
617         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
618 }
619
620 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
621 {
622         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
623 }
624
625 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
626                                struct ixgbe_ring *rx_ring,
627                                int *work_done, int work_to_do)
628 {
629         struct ixgbe_adapter *adapter = q_vector->adapter;
630         struct pci_dev *pdev = adapter->pdev;
631         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
632         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
633         struct sk_buff *skb;
634         unsigned int i;
635         u32 len, staterr;
636         u16 hdr_info;
637         bool cleaned = false;
638         int cleaned_count = 0;
639         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
640
641         i = rx_ring->next_to_clean;
642         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
643         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
644         rx_buffer_info = &rx_ring->rx_buffer_info[i];
645
646         while (staterr & IXGBE_RXD_STAT_DD) {
647                 u32 upper_len = 0;
648                 if (*work_done >= work_to_do)
649                         break;
650                 (*work_done)++;
651
652                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
653                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
654                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
655                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
656                         if (hdr_info & IXGBE_RXDADV_SPH)
657                                 adapter->rx_hdr_split++;
658                         if (len > IXGBE_RX_HDR_SIZE)
659                                 len = IXGBE_RX_HDR_SIZE;
660                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
661                 } else {
662                         len = le16_to_cpu(rx_desc->wb.upper.length);
663                 }
664
665                 cleaned = true;
666                 skb = rx_buffer_info->skb;
667                 prefetch(skb->data - NET_IP_ALIGN);
668                 rx_buffer_info->skb = NULL;
669
670                 if (len && !skb_shinfo(skb)->nr_frags) {
671                         pci_unmap_single(pdev, rx_buffer_info->dma,
672                                          rx_ring->rx_buf_len,
673                                          PCI_DMA_FROMDEVICE);
674                         skb_put(skb, len);
675                 }
676
677                 if (upper_len) {
678                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
679                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
680                         rx_buffer_info->page_dma = 0;
681                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
682                                            rx_buffer_info->page,
683                                            rx_buffer_info->page_offset,
684                                            upper_len);
685
686                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
687                             (page_count(rx_buffer_info->page) != 1))
688                                 rx_buffer_info->page = NULL;
689                         else
690                                 get_page(rx_buffer_info->page);
691
692                         skb->len += upper_len;
693                         skb->data_len += upper_len;
694                         skb->truesize += upper_len;
695                 }
696
697                 i++;
698                 if (i == rx_ring->count)
699                         i = 0;
700                 next_buffer = &rx_ring->rx_buffer_info[i];
701
702                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
703                 prefetch(next_rxd);
704
705                 cleaned_count++;
706                 if (staterr & IXGBE_RXD_STAT_EOP) {
707                         rx_ring->stats.packets++;
708                         rx_ring->stats.bytes += skb->len;
709                 } else {
710                         rx_buffer_info->skb = next_buffer->skb;
711                         rx_buffer_info->dma = next_buffer->dma;
712                         next_buffer->skb = skb;
713                         next_buffer->dma = 0;
714                         adapter->non_eop_descs++;
715                         goto next_desc;
716                 }
717
718                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
719                         dev_kfree_skb_irq(skb);
720                         goto next_desc;
721                 }
722
723                 ixgbe_rx_checksum(adapter, staterr, skb);
724
725                 /* probably a little skewed due to removing CRC */
726                 total_rx_bytes += skb->len;
727                 total_rx_packets++;
728
729                 skb->protocol = eth_type_trans(skb, adapter->netdev);
730                 ixgbe_receive_skb(q_vector, skb, staterr, rx_desc);
731
732 next_desc:
733                 rx_desc->wb.upper.status_error = 0;
734
735                 /* return some buffers to hardware, one at a time is too slow */
736                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
737                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
738                         cleaned_count = 0;
739                 }
740
741                 /* use prefetched values */
742                 rx_desc = next_rxd;
743                 rx_buffer_info = next_buffer;
744
745                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
746         }
747
748         rx_ring->next_to_clean = i;
749         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
750
751         if (cleaned_count)
752                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
753
754         rx_ring->total_packets += total_rx_packets;
755         rx_ring->total_bytes += total_rx_bytes;
756         adapter->net_stats.rx_bytes += total_rx_bytes;
757         adapter->net_stats.rx_packets += total_rx_packets;
758
759         return cleaned;
760 }
761
762 static int ixgbe_clean_rxonly(struct napi_struct *, int);
763 /**
764  * ixgbe_configure_msix - Configure MSI-X hardware
765  * @adapter: board private structure
766  *
767  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
768  * interrupts.
769  **/
770 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
771 {
772         struct ixgbe_q_vector *q_vector;
773         int i, j, q_vectors, v_idx, r_idx;
774         u32 mask;
775
776         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
777
778         /*
779          * Populate the IVAR table and set the ITR values to the
780          * corresponding register.
781          */
782         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
783                 q_vector = &adapter->q_vector[v_idx];
784                 /* XXX for_each_bit(...) */
785                 r_idx = find_first_bit(q_vector->rxr_idx,
786                                        adapter->num_rx_queues);
787
788                 for (i = 0; i < q_vector->rxr_count; i++) {
789                         j = adapter->rx_ring[r_idx].reg_idx;
790                         ixgbe_set_ivar(adapter, 0, j, v_idx);
791                         r_idx = find_next_bit(q_vector->rxr_idx,
792                                               adapter->num_rx_queues,
793                                               r_idx + 1);
794                 }
795                 r_idx = find_first_bit(q_vector->txr_idx,
796                                        adapter->num_tx_queues);
797
798                 for (i = 0; i < q_vector->txr_count; i++) {
799                         j = adapter->tx_ring[r_idx].reg_idx;
800                         ixgbe_set_ivar(adapter, 1, j, v_idx);
801                         r_idx = find_next_bit(q_vector->txr_idx,
802                                               adapter->num_tx_queues,
803                                               r_idx + 1);
804                 }
805
806                 /* if this is a tx only vector halve the interrupt rate */
807                 if (q_vector->txr_count && !q_vector->rxr_count)
808                         q_vector->eitr = (adapter->eitr_param >> 1);
809                 else if (q_vector->rxr_count)
810                         /* rx only */
811                         q_vector->eitr = adapter->eitr_param;
812
813                 /*
814                  * since this is initial set up don't need to call
815                  * ixgbe_write_eitr helper
816                  */
817                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
818                                 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
819         }
820
821         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
822                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
823                                v_idx);
824         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
825                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
826         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
827
828         /* set up to autoclear timer, and the vectors */
829         mask = IXGBE_EIMS_ENABLE_MASK;
830         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
831         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
832 }
833
834 enum latency_range {
835         lowest_latency = 0,
836         low_latency = 1,
837         bulk_latency = 2,
838         latency_invalid = 255
839 };
840
841 /**
842  * ixgbe_update_itr - update the dynamic ITR value based on statistics
843  * @adapter: pointer to adapter
844  * @eitr: eitr setting (ints per sec) to give last timeslice
845  * @itr_setting: current throttle rate in ints/second
846  * @packets: the number of packets during this measurement interval
847  * @bytes: the number of bytes during this measurement interval
848  *
849  *      Stores a new ITR value based on packets and byte
850  *      counts during the last interrupt.  The advantage of per interrupt
851  *      computation is faster updates and more accurate ITR for the current
852  *      traffic pattern.  Constants in this function were computed
853  *      based on theoretical maximum wire speed and thresholds were set based
854  *      on testing data as well as attempting to minimize response time
855  *      while increasing bulk throughput.
856  *      this functionality is controlled by the InterruptThrottleRate module
857  *      parameter (see ixgbe_param.c)
858  **/
859 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
860                            u32 eitr, u8 itr_setting,
861                            int packets, int bytes)
862 {
863         unsigned int retval = itr_setting;
864         u32 timepassed_us;
865         u64 bytes_perint;
866
867         if (packets == 0)
868                 goto update_itr_done;
869
870
871         /* simple throttlerate management
872          *    0-20MB/s lowest (100000 ints/s)
873          *   20-100MB/s low   (20000 ints/s)
874          *  100-1249MB/s bulk (8000 ints/s)
875          */
876         /* what was last interrupt timeslice? */
877         timepassed_us = 1000000/eitr;
878         bytes_perint = bytes / timepassed_us; /* bytes/usec */
879
880         switch (itr_setting) {
881         case lowest_latency:
882                 if (bytes_perint > adapter->eitr_low)
883                         retval = low_latency;
884                 break;
885         case low_latency:
886                 if (bytes_perint > adapter->eitr_high)
887                         retval = bulk_latency;
888                 else if (bytes_perint <= adapter->eitr_low)
889                         retval = lowest_latency;
890                 break;
891         case bulk_latency:
892                 if (bytes_perint <= adapter->eitr_high)
893                         retval = low_latency;
894                 break;
895         }
896
897 update_itr_done:
898         return retval;
899 }
900
901 /**
902  * ixgbe_write_eitr - write EITR register in hardware specific way
903  * @adapter: pointer to adapter struct
904  * @v_idx: vector index into q_vector array
905  * @itr_reg: new value to be written in *register* format, not ints/s
906  *
907  * This function is made to be called by ethtool and by the driver
908  * when it needs to update EITR registers at runtime.  Hardware
909  * specific quirks/differences are taken care of here.
910  */
911 void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
912 {
913         struct ixgbe_hw *hw = &adapter->hw;
914         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
915                 /* must write high and low 16 bits to reset counter */
916                 itr_reg |= (itr_reg << 16);
917         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
918                 /*
919                  * set the WDIS bit to not clear the timer bits and cause an
920                  * immediate assertion of the interrupt
921                  */
922                 itr_reg |= IXGBE_EITR_CNT_WDIS;
923         }
924         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
925 }
926
927 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
928 {
929         struct ixgbe_adapter *adapter = q_vector->adapter;
930         u32 new_itr;
931         u8 current_itr, ret_itr;
932         int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
933                                sizeof(struct ixgbe_q_vector);
934         struct ixgbe_ring *rx_ring, *tx_ring;
935
936         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
937         for (i = 0; i < q_vector->txr_count; i++) {
938                 tx_ring = &(adapter->tx_ring[r_idx]);
939                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
940                                            q_vector->tx_itr,
941                                            tx_ring->total_packets,
942                                            tx_ring->total_bytes);
943                 /* if the result for this queue would decrease interrupt
944                  * rate for this vector then use that result */
945                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
946                                     q_vector->tx_itr - 1 : ret_itr);
947                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
948                                       r_idx + 1);
949         }
950
951         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
952         for (i = 0; i < q_vector->rxr_count; i++) {
953                 rx_ring = &(adapter->rx_ring[r_idx]);
954                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
955                                            q_vector->rx_itr,
956                                            rx_ring->total_packets,
957                                            rx_ring->total_bytes);
958                 /* if the result for this queue would decrease interrupt
959                  * rate for this vector then use that result */
960                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
961                                     q_vector->rx_itr - 1 : ret_itr);
962                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
963                                       r_idx + 1);
964         }
965
966         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
967
968         switch (current_itr) {
969         /* counts and packets in update_itr are dependent on these numbers */
970         case lowest_latency:
971                 new_itr = 100000;
972                 break;
973         case low_latency:
974                 new_itr = 20000; /* aka hwitr = ~200 */
975                 break;
976         case bulk_latency:
977         default:
978                 new_itr = 8000;
979                 break;
980         }
981
982         if (new_itr != q_vector->eitr) {
983                 u32 itr_reg;
984
985                 /* save the algorithm value here, not the smoothed one */
986                 q_vector->eitr = new_itr;
987                 /* do an exponential smoothing */
988                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
989                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
990                 ixgbe_write_eitr(adapter, v_idx, itr_reg);
991         }
992
993         return;
994 }
995
996 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
997 {
998         struct ixgbe_hw *hw = &adapter->hw;
999
1000         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1001             (eicr & IXGBE_EICR_GPI_SDP1)) {
1002                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1003                 /* write to clear the interrupt */
1004                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1005         }
1006 }
1007
1008 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1009 {
1010         struct ixgbe_hw *hw = &adapter->hw;
1011
1012         if (eicr & IXGBE_EICR_GPI_SDP1) {
1013                 /* Clear the interrupt */
1014                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1015                 schedule_work(&adapter->multispeed_fiber_task);
1016         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1017                 /* Clear the interrupt */
1018                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1019                 schedule_work(&adapter->sfp_config_module_task);
1020         } else {
1021                 /* Interrupt isn't for us... */
1022                 return;
1023         }
1024 }
1025
1026 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1027 {
1028         struct ixgbe_hw *hw = &adapter->hw;
1029
1030         adapter->lsc_int++;
1031         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1032         adapter->link_check_timeout = jiffies;
1033         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1034                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1035                 schedule_work(&adapter->watchdog_task);
1036         }
1037 }
1038
1039 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1040 {
1041         struct net_device *netdev = data;
1042         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1043         struct ixgbe_hw *hw = &adapter->hw;
1044         u32 eicr;
1045
1046         /*
1047          * Workaround for Silicon errata.  Use clear-by-write instead
1048          * of clear-by-read.  Reading with EICS will return the
1049          * interrupt causes without clearing, which later be done
1050          * with the write to EICR.
1051          */
1052         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1053         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1054
1055         if (eicr & IXGBE_EICR_LSC)
1056                 ixgbe_check_lsc(adapter);
1057
1058         if (hw->mac.type == ixgbe_mac_82598EB)
1059                 ixgbe_check_fan_failure(adapter, eicr);
1060
1061         if (hw->mac.type == ixgbe_mac_82599EB)
1062                 ixgbe_check_sfp_event(adapter, eicr);
1063         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1064                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1065
1066         return IRQ_HANDLED;
1067 }
1068
1069 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1070 {
1071         struct ixgbe_q_vector *q_vector = data;
1072         struct ixgbe_adapter  *adapter = q_vector->adapter;
1073         struct ixgbe_ring     *tx_ring;
1074         int i, r_idx;
1075
1076         if (!q_vector->txr_count)
1077                 return IRQ_HANDLED;
1078
1079         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1080         for (i = 0; i < q_vector->txr_count; i++) {
1081                 tx_ring = &(adapter->tx_ring[r_idx]);
1082 #ifdef CONFIG_IXGBE_DCA
1083                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1084                         ixgbe_update_tx_dca(adapter, tx_ring);
1085 #endif
1086                 tx_ring->total_bytes = 0;
1087                 tx_ring->total_packets = 0;
1088                 ixgbe_clean_tx_irq(adapter, tx_ring);
1089                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1090                                       r_idx + 1);
1091         }
1092
1093         return IRQ_HANDLED;
1094 }
1095
1096 /**
1097  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1098  * @irq: unused
1099  * @data: pointer to our q_vector struct for this interrupt vector
1100  **/
1101 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1102 {
1103         struct ixgbe_q_vector *q_vector = data;
1104         struct ixgbe_adapter  *adapter = q_vector->adapter;
1105         struct ixgbe_ring  *rx_ring;
1106         int r_idx;
1107         int i;
1108
1109         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1110         for (i = 0;  i < q_vector->rxr_count; i++) {
1111                 rx_ring = &(adapter->rx_ring[r_idx]);
1112                 rx_ring->total_bytes = 0;
1113                 rx_ring->total_packets = 0;
1114                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1115                                       r_idx + 1);
1116         }
1117
1118         if (!q_vector->rxr_count)
1119                 return IRQ_HANDLED;
1120
1121         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1122         rx_ring = &(adapter->rx_ring[r_idx]);
1123         /* disable interrupts on this vector only */
1124         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1125         napi_schedule(&q_vector->napi);
1126
1127         return IRQ_HANDLED;
1128 }
1129
1130 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1131 {
1132         ixgbe_msix_clean_rx(irq, data);
1133         ixgbe_msix_clean_tx(irq, data);
1134
1135         return IRQ_HANDLED;
1136 }
1137
1138 /**
1139  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1140  * @napi: napi struct with our devices info in it
1141  * @budget: amount of work driver is allowed to do this pass, in packets
1142  *
1143  * This function is optimized for cleaning one queue only on a single
1144  * q_vector!!!
1145  **/
1146 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1147 {
1148         struct ixgbe_q_vector *q_vector =
1149                                container_of(napi, struct ixgbe_q_vector, napi);
1150         struct ixgbe_adapter *adapter = q_vector->adapter;
1151         struct ixgbe_ring *rx_ring = NULL;
1152         int work_done = 0;
1153         long r_idx;
1154
1155         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1156         rx_ring = &(adapter->rx_ring[r_idx]);
1157 #ifdef CONFIG_IXGBE_DCA
1158         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1159                 ixgbe_update_rx_dca(adapter, rx_ring);
1160 #endif
1161
1162         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1163
1164         /* If all Rx work done, exit the polling mode */
1165         if (work_done < budget) {
1166                 napi_complete(napi);
1167                 if (adapter->itr_setting & 1)
1168                         ixgbe_set_itr_msix(q_vector);
1169                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1170                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
1171         }
1172
1173         return work_done;
1174 }
1175
1176 /**
1177  * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1178  * @napi: napi struct with our devices info in it
1179  * @budget: amount of work driver is allowed to do this pass, in packets
1180  *
1181  * This function will clean more than one rx queue associated with a
1182  * q_vector.
1183  **/
1184 static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1185 {
1186         struct ixgbe_q_vector *q_vector =
1187                                container_of(napi, struct ixgbe_q_vector, napi);
1188         struct ixgbe_adapter *adapter = q_vector->adapter;
1189         struct ixgbe_ring *rx_ring = NULL;
1190         int work_done = 0, i;
1191         long r_idx;
1192         u16 enable_mask = 0;
1193
1194         /* attempt to distribute budget to each queue fairly, but don't allow
1195          * the budget to go below 1 because we'll exit polling */
1196         budget /= (q_vector->rxr_count ?: 1);
1197         budget = max(budget, 1);
1198         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1199         for (i = 0; i < q_vector->rxr_count; i++) {
1200                 rx_ring = &(adapter->rx_ring[r_idx]);
1201 #ifdef CONFIG_IXGBE_DCA
1202                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1203                         ixgbe_update_rx_dca(adapter, rx_ring);
1204 #endif
1205                 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1206                 enable_mask |= rx_ring->v_idx;
1207                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1208                                       r_idx + 1);
1209         }
1210
1211         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1212         rx_ring = &(adapter->rx_ring[r_idx]);
1213         /* If all Rx work done, exit the polling mode */
1214         if (work_done < budget) {
1215                 napi_complete(napi);
1216                 if (adapter->itr_setting & 1)
1217                         ixgbe_set_itr_msix(q_vector);
1218                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1219                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1220                 return 0;
1221         }
1222
1223         return work_done;
1224 }
1225 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1226                                      int r_idx)
1227 {
1228         a->q_vector[v_idx].adapter = a;
1229         set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1230         a->q_vector[v_idx].rxr_count++;
1231         a->rx_ring[r_idx].v_idx = 1 << v_idx;
1232 }
1233
1234 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1235                                      int r_idx)
1236 {
1237         a->q_vector[v_idx].adapter = a;
1238         set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1239         a->q_vector[v_idx].txr_count++;
1240         a->tx_ring[r_idx].v_idx = 1 << v_idx;
1241 }
1242
1243 /**
1244  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1245  * @adapter: board private structure to initialize
1246  * @vectors: allotted vector count for descriptor rings
1247  *
1248  * This function maps descriptor rings to the queue-specific vectors
1249  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1250  * one vector per ring/queue, but on a constrained vector budget, we
1251  * group the rings as "efficiently" as possible.  You would add new
1252  * mapping configurations in here.
1253  **/
1254 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1255                                       int vectors)
1256 {
1257         int v_start = 0;
1258         int rxr_idx = 0, txr_idx = 0;
1259         int rxr_remaining = adapter->num_rx_queues;
1260         int txr_remaining = adapter->num_tx_queues;
1261         int i, j;
1262         int rqpv, tqpv;
1263         int err = 0;
1264
1265         /* No mapping required if MSI-X is disabled. */
1266         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1267                 goto out;
1268
1269         /*
1270          * The ideal configuration...
1271          * We have enough vectors to map one per queue.
1272          */
1273         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1274                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1275                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1276
1277                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1278                         map_vector_to_txq(adapter, v_start, txr_idx);
1279
1280                 goto out;
1281         }
1282
1283         /*
1284          * If we don't have enough vectors for a 1-to-1
1285          * mapping, we'll have to group them so there are
1286          * multiple queues per vector.
1287          */
1288         /* Re-adjusting *qpv takes care of the remainder. */
1289         for (i = v_start; i < vectors; i++) {
1290                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1291                 for (j = 0; j < rqpv; j++) {
1292                         map_vector_to_rxq(adapter, i, rxr_idx);
1293                         rxr_idx++;
1294                         rxr_remaining--;
1295                 }
1296         }
1297         for (i = v_start; i < vectors; i++) {
1298                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1299                 for (j = 0; j < tqpv; j++) {
1300                         map_vector_to_txq(adapter, i, txr_idx);
1301                         txr_idx++;
1302                         txr_remaining--;
1303                 }
1304         }
1305
1306 out:
1307         return err;
1308 }
1309
1310 /**
1311  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1312  * @adapter: board private structure
1313  *
1314  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1315  * interrupts from the kernel.
1316  **/
1317 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1318 {
1319         struct net_device *netdev = adapter->netdev;
1320         irqreturn_t (*handler)(int, void *);
1321         int i, vector, q_vectors, err;
1322         int ri=0, ti=0;
1323
1324         /* Decrement for Other and TCP Timer vectors */
1325         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1326
1327         /* Map the Tx/Rx rings to the vectors we were allotted. */
1328         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1329         if (err)
1330                 goto out;
1331
1332 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1333                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1334                          &ixgbe_msix_clean_many)
1335         for (vector = 0; vector < q_vectors; vector++) {
1336                 handler = SET_HANDLER(&adapter->q_vector[vector]);
1337
1338                 if(handler == &ixgbe_msix_clean_rx) {
1339                         sprintf(adapter->name[vector], "%s-%s-%d",
1340                                 netdev->name, "rx", ri++);
1341                 }
1342                 else if(handler == &ixgbe_msix_clean_tx) {
1343                         sprintf(adapter->name[vector], "%s-%s-%d",
1344                                 netdev->name, "tx", ti++);
1345                 }
1346                 else
1347                         sprintf(adapter->name[vector], "%s-%s-%d",
1348                                 netdev->name, "TxRx", vector);
1349
1350                 err = request_irq(adapter->msix_entries[vector].vector,
1351                                   handler, 0, adapter->name[vector],
1352                                   &(adapter->q_vector[vector]));
1353                 if (err) {
1354                         DPRINTK(PROBE, ERR,
1355                                 "request_irq failed for MSIX interrupt "
1356                                 "Error: %d\n", err);
1357                         goto free_queue_irqs;
1358                 }
1359         }
1360
1361         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1362         err = request_irq(adapter->msix_entries[vector].vector,
1363                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1364         if (err) {
1365                 DPRINTK(PROBE, ERR,
1366                         "request_irq for msix_lsc failed: %d\n", err);
1367                 goto free_queue_irqs;
1368         }
1369
1370         return 0;
1371
1372 free_queue_irqs:
1373         for (i = vector - 1; i >= 0; i--)
1374                 free_irq(adapter->msix_entries[--vector].vector,
1375                          &(adapter->q_vector[i]));
1376         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1377         pci_disable_msix(adapter->pdev);
1378         kfree(adapter->msix_entries);
1379         adapter->msix_entries = NULL;
1380 out:
1381         return err;
1382 }
1383
1384 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1385 {
1386         struct ixgbe_q_vector *q_vector = adapter->q_vector;
1387         u8 current_itr;
1388         u32 new_itr = q_vector->eitr;
1389         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1390         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1391
1392         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1393                                             q_vector->tx_itr,
1394                                             tx_ring->total_packets,
1395                                             tx_ring->total_bytes);
1396         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1397                                             q_vector->rx_itr,
1398                                             rx_ring->total_packets,
1399                                             rx_ring->total_bytes);
1400
1401         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1402
1403         switch (current_itr) {
1404         /* counts and packets in update_itr are dependent on these numbers */
1405         case lowest_latency:
1406                 new_itr = 100000;
1407                 break;
1408         case low_latency:
1409                 new_itr = 20000; /* aka hwitr = ~200 */
1410                 break;
1411         case bulk_latency:
1412                 new_itr = 8000;
1413                 break;
1414         default:
1415                 break;
1416         }
1417
1418         if (new_itr != q_vector->eitr) {
1419                 u32 itr_reg;
1420
1421                 /* save the algorithm value here, not the smoothed one */
1422                 q_vector->eitr = new_itr;
1423                 /* do an exponential smoothing */
1424                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1425                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1426                 ixgbe_write_eitr(adapter, 0, itr_reg);
1427         }
1428
1429         return;
1430 }
1431
1432 /**
1433  * ixgbe_irq_enable - Enable default interrupt generation settings
1434  * @adapter: board private structure
1435  **/
1436 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1437 {
1438         u32 mask;
1439         mask = IXGBE_EIMS_ENABLE_MASK;
1440         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1441                 mask |= IXGBE_EIMS_GPI_SDP1;
1442         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1443                 mask |= IXGBE_EIMS_ECC;
1444                 mask |= IXGBE_EIMS_GPI_SDP1;
1445                 mask |= IXGBE_EIMS_GPI_SDP2;
1446         }
1447
1448         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1449         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1450                 /* enable the rest of the queue vectors */
1451                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1),
1452                                 (IXGBE_EIMS_RTX_QUEUE << 16));
1453                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(2),
1454                                 ((IXGBE_EIMS_RTX_QUEUE << 16) |
1455                                   IXGBE_EIMS_RTX_QUEUE));
1456         }
1457         IXGBE_WRITE_FLUSH(&adapter->hw);
1458 }
1459
1460 /**
1461  * ixgbe_intr - legacy mode Interrupt Handler
1462  * @irq: interrupt number
1463  * @data: pointer to a network interface device structure
1464  **/
1465 static irqreturn_t ixgbe_intr(int irq, void *data)
1466 {
1467         struct net_device *netdev = data;
1468         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1469         struct ixgbe_hw *hw = &adapter->hw;
1470         u32 eicr;
1471
1472         /*
1473          * Workaround for silicon errata.  Mask the interrupts
1474          * before the read of EICR.
1475          */
1476         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1477
1478         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1479          * therefore no explict interrupt disable is necessary */
1480         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1481         if (!eicr) {
1482                 /* shared interrupt alert!
1483                  * make sure interrupts are enabled because the read will
1484                  * have disabled interrupts due to EIAM */
1485                 ixgbe_irq_enable(adapter);
1486                 return IRQ_NONE;        /* Not our interrupt */
1487         }
1488
1489         if (eicr & IXGBE_EICR_LSC)
1490                 ixgbe_check_lsc(adapter);
1491
1492         if (hw->mac.type == ixgbe_mac_82599EB)
1493                 ixgbe_check_sfp_event(adapter, eicr);
1494
1495         ixgbe_check_fan_failure(adapter, eicr);
1496
1497         if (napi_schedule_prep(&adapter->q_vector[0].napi)) {
1498                 adapter->tx_ring[0].total_packets = 0;
1499                 adapter->tx_ring[0].total_bytes = 0;
1500                 adapter->rx_ring[0].total_packets = 0;
1501                 adapter->rx_ring[0].total_bytes = 0;
1502                 /* would disable interrupts here but EIAM disabled it */
1503                 __napi_schedule(&adapter->q_vector[0].napi);
1504         }
1505
1506         return IRQ_HANDLED;
1507 }
1508
1509 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1510 {
1511         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1512
1513         for (i = 0; i < q_vectors; i++) {
1514                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1515                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1516                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1517                 q_vector->rxr_count = 0;
1518                 q_vector->txr_count = 0;
1519         }
1520 }
1521
1522 /**
1523  * ixgbe_request_irq - initialize interrupts
1524  * @adapter: board private structure
1525  *
1526  * Attempts to configure interrupts using the best available
1527  * capabilities of the hardware and kernel.
1528  **/
1529 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1530 {
1531         struct net_device *netdev = adapter->netdev;
1532         int err;
1533
1534         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1535                 err = ixgbe_request_msix_irqs(adapter);
1536         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1537                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1538                                   netdev->name, netdev);
1539         } else {
1540                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1541                                   netdev->name, netdev);
1542         }
1543
1544         if (err)
1545                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1546
1547         return err;
1548 }
1549
1550 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1551 {
1552         struct net_device *netdev = adapter->netdev;
1553
1554         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1555                 int i, q_vectors;
1556
1557                 q_vectors = adapter->num_msix_vectors;
1558
1559                 i = q_vectors - 1;
1560                 free_irq(adapter->msix_entries[i].vector, netdev);
1561
1562                 i--;
1563                 for (; i >= 0; i--) {
1564                         free_irq(adapter->msix_entries[i].vector,
1565                                  &(adapter->q_vector[i]));
1566                 }
1567
1568                 ixgbe_reset_q_vectors(adapter);
1569         } else {
1570                 free_irq(adapter->pdev->irq, netdev);
1571         }
1572 }
1573
1574 /**
1575  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1576  * @adapter: board private structure
1577  **/
1578 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1579 {
1580         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1581         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1582                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1583                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(2), ~0);
1584         }
1585         IXGBE_WRITE_FLUSH(&adapter->hw);
1586         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1587                 int i;
1588                 for (i = 0; i < adapter->num_msix_vectors; i++)
1589                         synchronize_irq(adapter->msix_entries[i].vector);
1590         } else {
1591                 synchronize_irq(adapter->pdev->irq);
1592         }
1593 }
1594
1595 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter)
1596 {
1597         u32 mask = IXGBE_EIMS_RTX_QUEUE;
1598         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1599         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1600                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask << 16);
1601                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(2),
1602                                 (mask << 16 | mask));
1603         }
1604         /* skip the flush */
1605 }
1606
1607 /**
1608  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1609  *
1610  **/
1611 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1612 {
1613         struct ixgbe_hw *hw = &adapter->hw;
1614
1615         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1616                         EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1617
1618         ixgbe_set_ivar(adapter, 0, 0, 0);
1619         ixgbe_set_ivar(adapter, 1, 0, 0);
1620
1621         map_vector_to_rxq(adapter, 0, 0);
1622         map_vector_to_txq(adapter, 0, 0);
1623
1624         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1625 }
1626
1627 /**
1628  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1629  * @adapter: board private structure
1630  *
1631  * Configure the Tx unit of the MAC after a reset.
1632  **/
1633 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1634 {
1635         u64 tdba;
1636         struct ixgbe_hw *hw = &adapter->hw;
1637         u32 i, j, tdlen, txctrl;
1638
1639         /* Setup the HW Tx Head and Tail descriptor pointers */
1640         for (i = 0; i < adapter->num_tx_queues; i++) {
1641                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1642                 j = ring->reg_idx;
1643                 tdba = ring->dma;
1644                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1645                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1646                                 (tdba & DMA_32BIT_MASK));
1647                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1648                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1649                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1650                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1651                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1652                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1653                 /* Disable Tx Head Writeback RO bit, since this hoses
1654                  * bookkeeping if things aren't delivered in order.
1655                  */
1656                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1657                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1658                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1659         }
1660         if (hw->mac.type == ixgbe_mac_82599EB) {
1661                 /* We enable 8 traffic classes, DCB only */
1662                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1663                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1664                                         IXGBE_MTQC_8TC_8TQ));
1665         }
1666 }
1667
1668 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1669
1670 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1671 {
1672         struct ixgbe_ring *rx_ring;
1673         u32 srrctl;
1674         int queue0 = 0;
1675         unsigned long mask;
1676
1677         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1678                 queue0 = index;
1679         } else {
1680                 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1681                 queue0 = index & mask;
1682                 index = index & mask;
1683         }
1684
1685         rx_ring = &adapter->rx_ring[queue0];
1686
1687         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1688
1689         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1690         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1691
1692         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1693                 u16 bufsz = IXGBE_RXBUFFER_2048;
1694                 /* grow the amount we can receive on large page machines */
1695                 if (bufsz < (PAGE_SIZE / 2))
1696                         bufsz = (PAGE_SIZE / 2);
1697                 /* cap the bufsz at our largest descriptor size */
1698                 bufsz = min((u16)IXGBE_MAX_RXBUFFER, bufsz);
1699
1700                 srrctl |= bufsz >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1701                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1702                 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1703                             IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1704                            IXGBE_SRRCTL_BSIZEHDR_MASK);
1705         } else {
1706                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1707
1708                 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1709                         srrctl |= IXGBE_RXBUFFER_2048 >>
1710                                   IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1711                 else
1712                         srrctl |= rx_ring->rx_buf_len >>
1713                                   IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1714         }
1715
1716         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1717 }
1718
1719 /**
1720  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1721  * @adapter: board private structure
1722  *
1723  * Configure the Rx unit of the MAC after a reset.
1724  **/
1725 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1726 {
1727         u64 rdba;
1728         struct ixgbe_hw *hw = &adapter->hw;
1729         struct net_device *netdev = adapter->netdev;
1730         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1731         int i, j;
1732         u32 rdlen, rxctrl, rxcsum;
1733         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1734                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1735                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
1736         u32 fctrl, hlreg0;
1737         u32 reta = 0, mrqc = 0;
1738         u32 rdrxctl;
1739         int rx_buf_len;
1740
1741         /* Decide whether to use packet split mode or not */
1742         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1743
1744         /* Set the RX buffer length according to the mode */
1745         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1746                 rx_buf_len = IXGBE_RX_HDR_SIZE;
1747                 if (hw->mac.type == ixgbe_mac_82599EB) {
1748                         /* PSRTYPE must be initialized in 82599 */
1749                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1750                                       IXGBE_PSRTYPE_UDPHDR |
1751                                       IXGBE_PSRTYPE_IPV4HDR |
1752                                       IXGBE_PSRTYPE_IPV6HDR;
1753                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1754                 }
1755         } else {
1756                 if (netdev->mtu <= ETH_DATA_LEN)
1757                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1758                 else
1759                         rx_buf_len = ALIGN(max_frame, 1024);
1760         }
1761
1762         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1763         fctrl |= IXGBE_FCTRL_BAM;
1764         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
1765         fctrl |= IXGBE_FCTRL_PMCF;
1766         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1767
1768         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1769         if (adapter->netdev->mtu <= ETH_DATA_LEN)
1770                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1771         else
1772                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1773         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1774
1775         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1776         /* disable receives while setting up the descriptors */
1777         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1778         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1779
1780         /* Setup the HW Rx Head and Tail Descriptor Pointers and
1781          * the Base and Length of the Rx Descriptor Ring */
1782         for (i = 0; i < adapter->num_rx_queues; i++) {
1783                 rdba = adapter->rx_ring[i].dma;
1784                 j = adapter->rx_ring[i].reg_idx;
1785                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1786                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1787                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1788                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1789                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1790                 adapter->rx_ring[i].head = IXGBE_RDH(j);
1791                 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1792                 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1793
1794                 ixgbe_configure_srrctl(adapter, j);
1795         }
1796
1797         if (hw->mac.type == ixgbe_mac_82598EB) {
1798                 /*
1799                  * For VMDq support of different descriptor types or
1800                  * buffer sizes through the use of multiple SRRCTL
1801                  * registers, RDRXCTL.MVMEN must be set to 1
1802                  *
1803                  * also, the manual doesn't mention it clearly but DCA hints
1804                  * will only use queue 0's tags unless this bit is set.  Side
1805                  * effects of setting this bit are only that SRRCTL must be
1806                  * fully programmed [0..15]
1807                  */
1808                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1809                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1810                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1811         }
1812
1813         /* Program MRQC for the distribution of queues */
1814         if (hw->mac.type == ixgbe_mac_82599EB) {
1815                 int mask = adapter->flags & (
1816                                 IXGBE_FLAG_RSS_ENABLED
1817                                 | IXGBE_FLAG_DCB_ENABLED
1818                                 );
1819
1820                 switch (mask) {
1821                 case (IXGBE_FLAG_RSS_ENABLED):
1822                         mrqc = IXGBE_MRQC_RSSEN;
1823                         break;
1824                 case (IXGBE_FLAG_DCB_ENABLED):
1825                         mrqc = IXGBE_MRQC_RT8TCEN;
1826                         break;
1827                 default:
1828                         break;
1829                 }
1830         }
1831         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1832                 /* Fill out redirection table */
1833                 for (i = 0, j = 0; i < 128; i++, j++) {
1834                         if (j == adapter->ring_feature[RING_F_RSS].indices)
1835                                 j = 0;
1836                         /* reta = 4-byte sliding window of
1837                          * 0x00..(indices-1)(indices-1)00..etc. */
1838                         reta = (reta << 8) | (j * 0x11);
1839                         if ((i & 3) == 3)
1840                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
1841                 }
1842
1843                 /* Fill out hash function seeds */
1844                 for (i = 0; i < 10; i++)
1845                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
1846
1847                 if (hw->mac.type == ixgbe_mac_82598EB)
1848                         mrqc |= IXGBE_MRQC_RSSEN;
1849                     /* Perform hash on these packet types */
1850                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1851                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1852                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1853                       | IXGBE_MRQC_RSS_FIELD_IPV6
1854                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1855                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
1856         }
1857         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1858
1859         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1860
1861         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1862             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1863                 /* Disable indicating checksum in descriptor, enables
1864                  * RSS hash */
1865                 rxcsum |= IXGBE_RXCSUM_PCSD;
1866         }
1867         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1868                 /* Enable IPv4 payload checksum for UDP fragments
1869                  * if PCSD is not set */
1870                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1871         }
1872
1873         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
1874
1875         if (hw->mac.type == ixgbe_mac_82599EB) {
1876                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1877                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
1878                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1879         }
1880 }
1881
1882 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1883 {
1884         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1885         struct ixgbe_hw *hw = &adapter->hw;
1886
1887         /* add VID to filter table */
1888         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1889 }
1890
1891 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1892 {
1893         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1894         struct ixgbe_hw *hw = &adapter->hw;
1895
1896         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1897                 ixgbe_irq_disable(adapter);
1898
1899         vlan_group_set_device(adapter->vlgrp, vid, NULL);
1900
1901         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1902                 ixgbe_irq_enable(adapter);
1903
1904         /* remove VID from filter table */
1905         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
1906 }
1907
1908 static void ixgbe_vlan_rx_register(struct net_device *netdev,
1909                                    struct vlan_group *grp)
1910 {
1911         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1912         u32 ctrl;
1913         int i, j;
1914
1915         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1916                 ixgbe_irq_disable(adapter);
1917         adapter->vlgrp = grp;
1918
1919         /*
1920          * For a DCB driver, always enable VLAN tag stripping so we can
1921          * still receive traffic from a DCB-enabled host even if we're
1922          * not in DCB mode.
1923          */
1924         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1925         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1926                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
1927                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1928                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1929         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1930                 ctrl |= IXGBE_VLNCTRL_VFE;
1931                 /* enable VLAN tag insert/strip */
1932                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1933                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1934                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1935                 for (i = 0; i < adapter->num_rx_queues; i++) {
1936                         j = adapter->rx_ring[i].reg_idx;
1937                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
1938                         ctrl |= IXGBE_RXDCTL_VME;
1939                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
1940                 }
1941         }
1942         ixgbe_vlan_rx_add_vid(netdev, 0);
1943
1944         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1945                 ixgbe_irq_enable(adapter);
1946 }
1947
1948 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1949 {
1950         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1951
1952         if (adapter->vlgrp) {
1953                 u16 vid;
1954                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1955                         if (!vlan_group_get_device(adapter->vlgrp, vid))
1956                                 continue;
1957                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1958                 }
1959         }
1960 }
1961
1962 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1963 {
1964         struct dev_mc_list *mc_ptr;
1965         u8 *addr = *mc_addr_ptr;
1966         *vmdq = 0;
1967
1968         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1969         if (mc_ptr->next)
1970                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1971         else
1972                 *mc_addr_ptr = NULL;
1973
1974         return addr;
1975 }
1976
1977 /**
1978  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
1979  * @netdev: network interface device structure
1980  *
1981  * The set_rx_method entry point is called whenever the unicast/multicast
1982  * address list or the network interface flags are updated.  This routine is
1983  * responsible for configuring the hardware for proper unicast, multicast and
1984  * promiscuous mode.
1985  **/
1986 static void ixgbe_set_rx_mode(struct net_device *netdev)
1987 {
1988         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1989         struct ixgbe_hw *hw = &adapter->hw;
1990         u32 fctrl, vlnctrl;
1991         u8 *addr_list = NULL;
1992         int addr_count = 0;
1993
1994         /* Check for Promiscuous and All Multicast modes */
1995
1996         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1997         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1998
1999         if (netdev->flags & IFF_PROMISC) {
2000                 hw->addr_ctrl.user_set_promisc = 1;
2001                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2002                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2003         } else {
2004                 if (netdev->flags & IFF_ALLMULTI) {
2005                         fctrl |= IXGBE_FCTRL_MPE;
2006                         fctrl &= ~IXGBE_FCTRL_UPE;
2007                 } else {
2008                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2009                 }
2010                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2011                 hw->addr_ctrl.user_set_promisc = 0;
2012         }
2013
2014         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2015         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2016
2017         /* reprogram secondary unicast list */
2018         addr_count = netdev->uc_count;
2019         if (addr_count)
2020                 addr_list = netdev->uc_list->dmi_addr;
2021         hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2022                                           ixgbe_addr_list_itr);
2023
2024         /* reprogram multicast list */
2025         addr_count = netdev->mc_count;
2026         if (addr_count)
2027                 addr_list = netdev->mc_list->dmi_addr;
2028         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2029                                         ixgbe_addr_list_itr);
2030 }
2031
2032 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2033 {
2034         int q_idx;
2035         struct ixgbe_q_vector *q_vector;
2036         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2037
2038         /* legacy and MSI only use one vector */
2039         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2040                 q_vectors = 1;
2041
2042         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2043                 struct napi_struct *napi;
2044                 q_vector = &adapter->q_vector[q_idx];
2045                 if (!q_vector->rxr_count)
2046                         continue;
2047                 napi = &q_vector->napi;
2048                 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2049                     (q_vector->rxr_count > 1))
2050                         napi->poll = &ixgbe_clean_rxonly_many;
2051
2052                 napi_enable(napi);
2053         }
2054 }
2055
2056 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2057 {
2058         int q_idx;
2059         struct ixgbe_q_vector *q_vector;
2060         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2061
2062         /* legacy and MSI only use one vector */
2063         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2064                 q_vectors = 1;
2065
2066         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2067                 q_vector = &adapter->q_vector[q_idx];
2068                 if (!q_vector->rxr_count)
2069                         continue;
2070                 napi_disable(&q_vector->napi);
2071         }
2072 }
2073
2074 #ifdef CONFIG_IXGBE_DCB
2075 /*
2076  * ixgbe_configure_dcb - Configure DCB hardware
2077  * @adapter: ixgbe adapter struct
2078  *
2079  * This is called by the driver on open to configure the DCB hardware.
2080  * This is also called by the gennetlink interface when reconfiguring
2081  * the DCB state.
2082  */
2083 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2084 {
2085         struct ixgbe_hw *hw = &adapter->hw;
2086         u32 txdctl, vlnctrl;
2087         int i, j;
2088
2089         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2090         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2091         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2092
2093         /* reconfigure the hardware */
2094         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2095
2096         for (i = 0; i < adapter->num_tx_queues; i++) {
2097                 j = adapter->tx_ring[i].reg_idx;
2098                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2099                 /* PThresh workaround for Tx hang with DFP enabled. */
2100                 txdctl |= 32;
2101                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2102         }
2103         /* Enable VLAN tag insert/strip */
2104         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2105         if (hw->mac.type == ixgbe_mac_82598EB) {
2106                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2107                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2108                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2109         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2110                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2111                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2112                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2113                 for (i = 0; i < adapter->num_rx_queues; i++) {
2114                         j = adapter->rx_ring[i].reg_idx;
2115                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2116                         vlnctrl |= IXGBE_RXDCTL_VME;
2117                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2118                 }
2119         }
2120         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2121 }
2122
2123 #endif
2124 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2125 {
2126         struct net_device *netdev = adapter->netdev;
2127         int i;
2128
2129         ixgbe_set_rx_mode(netdev);
2130
2131         ixgbe_restore_vlan(adapter);
2132 #ifdef CONFIG_IXGBE_DCB
2133         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2134                 netif_set_gso_max_size(netdev, 32768);
2135                 ixgbe_configure_dcb(adapter);
2136         } else {
2137                 netif_set_gso_max_size(netdev, 65536);
2138         }
2139 #else
2140         netif_set_gso_max_size(netdev, 65536);
2141 #endif
2142
2143         ixgbe_configure_tx(adapter);
2144         ixgbe_configure_rx(adapter);
2145         for (i = 0; i < adapter->num_rx_queues; i++)
2146                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2147                                        (adapter->rx_ring[i].count - 1));
2148 }
2149
2150 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2151 {
2152         switch (hw->phy.type) {
2153         case ixgbe_phy_sfp_avago:
2154         case ixgbe_phy_sfp_ftl:
2155         case ixgbe_phy_sfp_intel:
2156         case ixgbe_phy_sfp_unknown:
2157         case ixgbe_phy_tw_tyco:
2158         case ixgbe_phy_tw_unknown:
2159                 return true;
2160         default:
2161                 return false;
2162         }
2163 }
2164
2165 /**
2166  * ixgbe_sfp_link_config - set up SFP+ link
2167  * @adapter: pointer to private adapter struct
2168  **/
2169 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2170 {
2171         struct ixgbe_hw *hw = &adapter->hw;
2172
2173                 if (hw->phy.multispeed_fiber) {
2174                         /*
2175                          * In multispeed fiber setups, the device may not have
2176                          * had a physical connection when the driver loaded.
2177                          * If that's the case, the initial link configuration
2178                          * couldn't get the MAC into 10G or 1G mode, so we'll
2179                          * never have a link status change interrupt fire.
2180                          * We need to try and force an autonegotiation
2181                          * session, then bring up link.
2182                          */
2183                         hw->mac.ops.setup_sfp(hw);
2184                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2185                                 schedule_work(&adapter->multispeed_fiber_task);
2186                 } else {
2187                         /*
2188                          * Direct Attach Cu and non-multispeed fiber modules
2189                          * still need to be configured properly prior to
2190                          * attempting link.
2191                          */
2192                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2193                                 schedule_work(&adapter->sfp_config_module_task);
2194                 }
2195 }
2196
2197 /**
2198  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2199  * @hw: pointer to private hardware struct
2200  *
2201  * Returns 0 on success, negative on failure
2202  **/
2203 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2204 {
2205         u32 autoneg;
2206         bool link_up = false;
2207         u32 ret = IXGBE_ERR_LINK_SETUP;
2208
2209         if (hw->mac.ops.check_link)
2210                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2211
2212         if (ret)
2213                 goto link_cfg_out;
2214
2215         if (hw->mac.ops.get_link_capabilities)
2216                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2217                                                         &hw->mac.autoneg);
2218         if (ret)
2219                 goto link_cfg_out;
2220
2221         if (hw->mac.ops.setup_link_speed)
2222                 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
2223 link_cfg_out:
2224         return ret;
2225 }
2226
2227 #define IXGBE_MAX_RX_DESC_POLL 10
2228 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2229                                               int rxr)
2230 {
2231         int j = adapter->rx_ring[rxr].reg_idx;
2232         int k;
2233
2234         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2235                 if (IXGBE_READ_REG(&adapter->hw,
2236                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2237                         break;
2238                 else
2239                         msleep(1);
2240         }
2241         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2242                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2243                         "not set within the polling period\n", rxr);
2244         }
2245         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2246                               (adapter->rx_ring[rxr].count - 1));
2247 }
2248
2249 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2250 {
2251         struct net_device *netdev = adapter->netdev;
2252         struct ixgbe_hw *hw = &adapter->hw;
2253         int i, j = 0;
2254         int num_rx_rings = adapter->num_rx_queues;
2255         int err;
2256         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2257         u32 txdctl, rxdctl, mhadd;
2258         u32 dmatxctl;
2259         u32 gpie;
2260
2261         ixgbe_get_hw_control(adapter);
2262
2263         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2264             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2265                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2266                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2267                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2268                 } else {
2269                         /* MSI only */
2270                         gpie = 0;
2271                 }
2272                 /* XXX: to interrupt immediately for EICS writes, enable this */
2273                 /* gpie |= IXGBE_GPIE_EIMEN; */
2274                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2275         }
2276
2277         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2278                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2279                  * specifically only auto mask tx and rx interrupts */
2280                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2281         }
2282
2283         /* Enable fan failure interrupt if media type is copper */
2284         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2285                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2286                 gpie |= IXGBE_SDP1_GPIEN;
2287                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2288         }
2289
2290         if (hw->mac.type == ixgbe_mac_82599EB) {
2291                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2292                 gpie |= IXGBE_SDP1_GPIEN;
2293                 gpie |= IXGBE_SDP2_GPIEN;
2294                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2295         }
2296
2297         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2298         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2299                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2300                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2301
2302                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2303         }
2304
2305         for (i = 0; i < adapter->num_tx_queues; i++) {
2306                 j = adapter->tx_ring[i].reg_idx;
2307                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2308                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2309                 txdctl |= (8 << 16);
2310                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2311         }
2312
2313         if (hw->mac.type == ixgbe_mac_82599EB) {
2314                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2315                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2316                 dmatxctl |= IXGBE_DMATXCTL_TE;
2317                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2318         }
2319         for (i = 0; i < adapter->num_tx_queues; i++) {
2320                 j = adapter->tx_ring[i].reg_idx;
2321                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2322                 txdctl |= IXGBE_TXDCTL_ENABLE;
2323                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2324         }
2325
2326         for (i = 0; i < num_rx_rings; i++) {
2327                 j = adapter->rx_ring[i].reg_idx;
2328                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2329                 /* enable PTHRESH=32 descriptors (half the internal cache)
2330                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2331                  * this also removes a pesky rx_no_buffer_count increment */
2332                 rxdctl |= 0x0020;
2333                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2334                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2335                 if (hw->mac.type == ixgbe_mac_82599EB)
2336                         ixgbe_rx_desc_queue_enable(adapter, i);
2337         }
2338         /* enable all receives */
2339         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2340         if (hw->mac.type == ixgbe_mac_82598EB)
2341                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2342         else
2343                 rxdctl |= IXGBE_RXCTRL_RXEN;
2344         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2345
2346         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2347                 ixgbe_configure_msix(adapter);
2348         else
2349                 ixgbe_configure_msi_and_legacy(adapter);
2350
2351         clear_bit(__IXGBE_DOWN, &adapter->state);
2352         ixgbe_napi_enable_all(adapter);
2353
2354         /* clear any pending interrupts, may auto mask */
2355         IXGBE_READ_REG(hw, IXGBE_EICR);
2356
2357         ixgbe_irq_enable(adapter);
2358
2359         /*
2360          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2361          * arrived before interrupts were enabled.  We need to kick off
2362          * the SFP+ module setup first, then try to bring up link.
2363          * If we're not hot-pluggable SFP+, we just need to configure link
2364          * and bring it up.
2365          */
2366         err = hw->phy.ops.identify(hw);
2367         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2368                 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2369                 ixgbe_down(adapter);
2370                 return err;
2371         }
2372
2373         if (ixgbe_is_sfp(hw)) {
2374                 ixgbe_sfp_link_config(adapter);
2375         } else {
2376                 err = ixgbe_non_sfp_link_config(hw);
2377                 if (err)
2378                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2379         }
2380
2381         /* enable transmits */
2382         netif_tx_start_all_queues(netdev);
2383
2384         /* bring the link up in the watchdog, this could race with our first
2385          * link up interrupt but shouldn't be a problem */
2386         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2387         adapter->link_check_timeout = jiffies;
2388         mod_timer(&adapter->watchdog_timer, jiffies);
2389         return 0;
2390 }
2391
2392 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2393 {
2394         WARN_ON(in_interrupt());
2395         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2396                 msleep(1);
2397         ixgbe_down(adapter);
2398         ixgbe_up(adapter);
2399         clear_bit(__IXGBE_RESETTING, &adapter->state);
2400 }
2401
2402 int ixgbe_up(struct ixgbe_adapter *adapter)
2403 {
2404         /* hardware has been reset, we need to reload some things */
2405         ixgbe_configure(adapter);
2406
2407         ixgbe_napi_add_all(adapter);
2408
2409         return ixgbe_up_complete(adapter);
2410 }
2411
2412 void ixgbe_reset(struct ixgbe_adapter *adapter)
2413 {
2414         struct ixgbe_hw *hw = &adapter->hw;
2415         if (hw->mac.ops.init_hw(hw))
2416                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
2417
2418         /* reprogram the RAR[0] in case user changed it. */
2419         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2420
2421 }
2422
2423 /**
2424  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2425  * @adapter: board private structure
2426  * @rx_ring: ring to free buffers from
2427  **/
2428 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2429                                 struct ixgbe_ring *rx_ring)
2430 {
2431         struct pci_dev *pdev = adapter->pdev;
2432         unsigned long size;
2433         unsigned int i;
2434
2435         /* Free all the Rx ring sk_buffs */
2436
2437         for (i = 0; i < rx_ring->count; i++) {
2438                 struct ixgbe_rx_buffer *rx_buffer_info;
2439
2440                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2441                 if (rx_buffer_info->dma) {
2442                         pci_unmap_single(pdev, rx_buffer_info->dma,
2443                                          rx_ring->rx_buf_len,
2444                                          PCI_DMA_FROMDEVICE);
2445                         rx_buffer_info->dma = 0;
2446                 }
2447                 if (rx_buffer_info->skb) {
2448                         dev_kfree_skb(rx_buffer_info->skb);
2449                         rx_buffer_info->skb = NULL;
2450                 }
2451                 if (!rx_buffer_info->page)
2452                         continue;
2453                 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2454                                PCI_DMA_FROMDEVICE);
2455                 rx_buffer_info->page_dma = 0;
2456                 put_page(rx_buffer_info->page);
2457                 rx_buffer_info->page = NULL;
2458                 rx_buffer_info->page_offset = 0;
2459         }
2460
2461         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2462         memset(rx_ring->rx_buffer_info, 0, size);
2463
2464         /* Zero out the descriptor ring */
2465         memset(rx_ring->desc, 0, rx_ring->size);
2466
2467         rx_ring->next_to_clean = 0;
2468         rx_ring->next_to_use = 0;
2469
2470         if (rx_ring->head)
2471                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2472         if (rx_ring->tail)
2473                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2474 }
2475
2476 /**
2477  * ixgbe_clean_tx_ring - Free Tx Buffers
2478  * @adapter: board private structure
2479  * @tx_ring: ring to be cleaned
2480  **/
2481 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2482                                 struct ixgbe_ring *tx_ring)
2483 {
2484         struct ixgbe_tx_buffer *tx_buffer_info;
2485         unsigned long size;
2486         unsigned int i;
2487
2488         /* Free all the Tx ring sk_buffs */
2489
2490         for (i = 0; i < tx_ring->count; i++) {
2491                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2492                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2493         }
2494
2495         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2496         memset(tx_ring->tx_buffer_info, 0, size);
2497
2498         /* Zero out the descriptor ring */
2499         memset(tx_ring->desc, 0, tx_ring->size);
2500
2501         tx_ring->next_to_use = 0;
2502         tx_ring->next_to_clean = 0;
2503
2504         if (tx_ring->head)
2505                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2506         if (tx_ring->tail)
2507                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2508 }
2509
2510 /**
2511  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2512  * @adapter: board private structure
2513  **/
2514 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2515 {
2516         int i;
2517
2518         for (i = 0; i < adapter->num_rx_queues; i++)
2519                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2520 }
2521
2522 /**
2523  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2524  * @adapter: board private structure
2525  **/
2526 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2527 {
2528         int i;
2529
2530         for (i = 0; i < adapter->num_tx_queues; i++)
2531                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2532 }
2533
2534 void ixgbe_down(struct ixgbe_adapter *adapter)
2535 {
2536         struct net_device *netdev = adapter->netdev;
2537         struct ixgbe_hw *hw = &adapter->hw;
2538         u32 rxctrl;
2539         u32 txdctl;
2540         int i, j;
2541
2542         /* signal that we are down to the interrupt handler */
2543         set_bit(__IXGBE_DOWN, &adapter->state);
2544
2545         /* disable receives */
2546         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2547         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2548
2549         netif_tx_disable(netdev);
2550
2551         IXGBE_WRITE_FLUSH(hw);
2552         msleep(10);
2553
2554         netif_tx_stop_all_queues(netdev);
2555
2556         ixgbe_irq_disable(adapter);
2557
2558         ixgbe_napi_disable_all(adapter);
2559
2560         del_timer_sync(&adapter->watchdog_timer);
2561         cancel_work_sync(&adapter->watchdog_task);
2562
2563         /* disable transmits in the hardware now that interrupts are off */
2564         for (i = 0; i < adapter->num_tx_queues; i++) {
2565                 j = adapter->tx_ring[i].reg_idx;
2566                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2567                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2568                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2569         }
2570         /* Disable the Tx DMA engine on 82599 */
2571         if (hw->mac.type == ixgbe_mac_82599EB)
2572                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2573                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2574                                  ~IXGBE_DMATXCTL_TE));
2575
2576         netif_carrier_off(netdev);
2577
2578 #ifdef CONFIG_IXGBE_DCA
2579         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2580                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2581                 dca_remove_requester(&adapter->pdev->dev);
2582         }
2583
2584 #endif
2585         if (!pci_channel_offline(adapter->pdev))
2586                 ixgbe_reset(adapter);
2587         ixgbe_clean_all_tx_rings(adapter);
2588         ixgbe_clean_all_rx_rings(adapter);
2589
2590 #ifdef CONFIG_IXGBE_DCA
2591         /* since we reset the hardware DCA settings were cleared */
2592         if (dca_add_requester(&adapter->pdev->dev) == 0) {
2593                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2594                 /* always use CB2 mode, difference is masked
2595                  * in the CB driver */
2596                 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
2597                 ixgbe_setup_dca(adapter);
2598         }
2599 #endif
2600 }
2601
2602 /**
2603  * ixgbe_poll - NAPI Rx polling callback
2604  * @napi: structure for representing this polling device
2605  * @budget: how many packets driver is allowed to clean
2606  *
2607  * This function is used for legacy and MSI, NAPI mode
2608  **/
2609 static int ixgbe_poll(struct napi_struct *napi, int budget)
2610 {
2611         struct ixgbe_q_vector *q_vector =
2612                                 container_of(napi, struct ixgbe_q_vector, napi);
2613         struct ixgbe_adapter *adapter = q_vector->adapter;
2614         int tx_clean_complete, work_done = 0;
2615
2616 #ifdef CONFIG_IXGBE_DCA
2617         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2618                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2619                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2620         }
2621 #endif
2622
2623         tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
2624         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2625
2626         if (!tx_clean_complete)
2627                 work_done = budget;
2628
2629         /* If budget not fully consumed, exit the polling mode */
2630         if (work_done < budget) {
2631                 napi_complete(napi);
2632                 if (adapter->itr_setting & 1)
2633                         ixgbe_set_itr(adapter);
2634                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2635                         ixgbe_irq_enable_queues(adapter);
2636         }
2637         return work_done;
2638 }
2639
2640 /**
2641  * ixgbe_tx_timeout - Respond to a Tx Hang
2642  * @netdev: network interface device structure
2643  **/
2644 static void ixgbe_tx_timeout(struct net_device *netdev)
2645 {
2646         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2647
2648         /* Do the reset outside of interrupt context */
2649         schedule_work(&adapter->reset_task);
2650 }
2651
2652 static void ixgbe_reset_task(struct work_struct *work)
2653 {
2654         struct ixgbe_adapter *adapter;
2655         adapter = container_of(work, struct ixgbe_adapter, reset_task);
2656
2657         /* If we're already down or resetting, just bail */
2658         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2659             test_bit(__IXGBE_RESETTING, &adapter->state))
2660                 return;
2661
2662         adapter->tx_timeout_count++;
2663
2664         ixgbe_reinit_locked(adapter);
2665 }
2666
2667 #ifdef CONFIG_IXGBE_DCB
2668 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
2669 {
2670         bool ret = false;
2671
2672         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2673                 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2674                 adapter->num_rx_queues =
2675                                       adapter->ring_feature[RING_F_DCB].indices;
2676                 adapter->num_tx_queues =
2677                                       adapter->ring_feature[RING_F_DCB].indices;
2678                 ret = true;
2679         } else {
2680                 ret = false;
2681         }
2682
2683         return ret;
2684 }
2685 #endif
2686
2687 /**
2688  * ixgbe_set_rss_queues: Allocate queues for RSS
2689  * @adapter: board private structure to initialize
2690  *
2691  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
2692  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2693  *
2694  **/
2695 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2696 {
2697         bool ret = false;
2698
2699         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2700                 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2701                 adapter->num_rx_queues =
2702                                       adapter->ring_feature[RING_F_RSS].indices;
2703                 adapter->num_tx_queues =
2704                                       adapter->ring_feature[RING_F_RSS].indices;
2705                 ret = true;
2706         } else {
2707                 ret = false;
2708         }
2709
2710         return ret;
2711 }
2712
2713 /*
2714  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2715  * @adapter: board private structure to initialize
2716  *
2717  * This is the top level queue allocation routine.  The order here is very
2718  * important, starting with the "most" number of features turned on at once,
2719  * and ending with the smallest set of features.  This way large combinations
2720  * can be allocated if they're turned on, and smaller combinations are the
2721  * fallthrough conditions.
2722  *
2723  **/
2724 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2725 {
2726         /* Start with base case */
2727         adapter->num_rx_queues = 1;
2728         adapter->num_tx_queues = 1;
2729
2730 #ifdef CONFIG_IXGBE_DCB
2731         if (ixgbe_set_dcb_queues(adapter))
2732                 return;
2733
2734 #endif
2735         if (ixgbe_set_rss_queues(adapter))
2736                 return;
2737 }
2738
2739 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2740                                        int vectors)
2741 {
2742         int err, vector_threshold;
2743
2744         /* We'll want at least 3 (vector_threshold):
2745          * 1) TxQ[0] Cleanup
2746          * 2) RxQ[0] Cleanup
2747          * 3) Other (Link Status Change, etc.)
2748          * 4) TCP Timer (optional)
2749          */
2750         vector_threshold = MIN_MSIX_COUNT;
2751
2752         /* The more we get, the more we will assign to Tx/Rx Cleanup
2753          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2754          * Right now, we simply care about how many we'll get; we'll
2755          * set them up later while requesting irq's.
2756          */
2757         while (vectors >= vector_threshold) {
2758                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2759                                       vectors);
2760                 if (!err) /* Success in acquiring all requested vectors. */
2761                         break;
2762                 else if (err < 0)
2763                         vectors = 0; /* Nasty failure, quit now */
2764                 else /* err == number of vectors we should try again with */
2765                         vectors = err;
2766         }
2767
2768         if (vectors < vector_threshold) {
2769                 /* Can't allocate enough MSI-X interrupts?  Oh well.
2770                  * This just means we'll go with either a single MSI
2771                  * vector or fall back to legacy interrupts.
2772                  */
2773                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2774                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2775                 kfree(adapter->msix_entries);
2776                 adapter->msix_entries = NULL;
2777                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2778                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2779                 ixgbe_set_num_queues(adapter);
2780         } else {
2781                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2782                 /*
2783                  * Adjust for only the vectors we'll use, which is minimum
2784                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2785                  * vectors we were allocated.
2786                  */
2787                 adapter->num_msix_vectors = min(vectors,
2788                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
2789         }
2790 }
2791
2792 /**
2793  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
2794  * @adapter: board private structure to initialize
2795  *
2796  * Cache the descriptor ring offsets for RSS to the assigned rings.
2797  *
2798  **/
2799 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
2800 {
2801         int i;
2802         bool ret = false;
2803
2804         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2805                 for (i = 0; i < adapter->num_rx_queues; i++)
2806                         adapter->rx_ring[i].reg_idx = i;
2807                 for (i = 0; i < adapter->num_tx_queues; i++)
2808                         adapter->tx_ring[i].reg_idx = i;
2809                 ret = true;
2810         } else {
2811                 ret = false;
2812         }
2813
2814         return ret;
2815 }
2816
2817 #ifdef CONFIG_IXGBE_DCB
2818 /**
2819  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2820  * @adapter: board private structure to initialize
2821  *
2822  * Cache the descriptor ring offsets for DCB to the assigned rings.
2823  *
2824  **/
2825 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2826 {
2827         int i;
2828         bool ret = false;
2829         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2830
2831         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2832                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2833                         /* the number of queues is assumed to be symmetric */
2834                         for (i = 0; i < dcb_i; i++) {
2835                                 adapter->rx_ring[i].reg_idx = i << 3;
2836                                 adapter->tx_ring[i].reg_idx = i << 2;
2837                         }
2838                         ret = true;
2839                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2840                         for (i = 0; i < dcb_i; i++) {
2841                                 adapter->rx_ring[i].reg_idx = i << 4;
2842                                 adapter->tx_ring[i].reg_idx = i << 4;
2843                         }
2844                         ret = true;
2845                 } else {
2846                         ret = false;
2847                 }
2848         } else {
2849                 ret = false;
2850         }
2851
2852         return ret;
2853 }
2854 #endif
2855
2856 /**
2857  * ixgbe_cache_ring_register - Descriptor ring to register mapping
2858  * @adapter: board private structure to initialize
2859  *
2860  * Once we know the feature-set enabled for the device, we'll cache
2861  * the register offset the descriptor ring is assigned to.
2862  *
2863  * Note, the order the various feature calls is important.  It must start with
2864  * the "most" features enabled at the same time, then trickle down to the
2865  * least amount of features turned on at once.
2866  **/
2867 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2868 {
2869         /* start with default case */
2870         adapter->rx_ring[0].reg_idx = 0;
2871         adapter->tx_ring[0].reg_idx = 0;
2872
2873 #ifdef CONFIG_IXGBE_DCB
2874         if (ixgbe_cache_ring_dcb(adapter))
2875                 return;
2876
2877 #endif
2878         if (ixgbe_cache_ring_rss(adapter))
2879                 return;
2880 }
2881
2882 /**
2883  * ixgbe_alloc_queues - Allocate memory for all rings
2884  * @adapter: board private structure to initialize
2885  *
2886  * We allocate one ring per queue at run-time since we don't know the
2887  * number of queues at compile-time.  The polling_netdev array is
2888  * intended for Multiqueue, but should work fine with a single queue.
2889  **/
2890 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2891 {
2892         int i;
2893
2894         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
2895                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
2896         if (!adapter->tx_ring)
2897                 goto err_tx_ring_allocation;
2898
2899         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
2900                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
2901         if (!adapter->rx_ring)
2902                 goto err_rx_ring_allocation;
2903
2904         for (i = 0; i < adapter->num_tx_queues; i++) {
2905                 adapter->tx_ring[i].count = adapter->tx_ring_count;
2906                 adapter->tx_ring[i].queue_index = i;
2907         }
2908
2909         for (i = 0; i < adapter->num_rx_queues; i++) {
2910                 adapter->rx_ring[i].count = adapter->rx_ring_count;
2911                 adapter->rx_ring[i].queue_index = i;
2912         }
2913
2914         ixgbe_cache_ring_register(adapter);
2915
2916         return 0;
2917
2918 err_rx_ring_allocation:
2919         kfree(adapter->tx_ring);
2920 err_tx_ring_allocation:
2921         return -ENOMEM;
2922 }
2923
2924 /**
2925  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2926  * @adapter: board private structure to initialize
2927  *
2928  * Attempt to configure the interrupts using the best available
2929  * capabilities of the hardware and the kernel.
2930  **/
2931 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
2932 {
2933         struct ixgbe_hw *hw = &adapter->hw;
2934         int err = 0;
2935         int vector, v_budget;
2936
2937         /*
2938          * It's easy to be greedy for MSI-X vectors, but it really
2939          * doesn't do us much good if we have a lot more vectors
2940          * than CPU's.  So let's be conservative and only ask for
2941          * (roughly) twice the number of vectors as there are CPU's.
2942          */
2943         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2944                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2945
2946         /*
2947          * At the same time, hardware can only support a maximum of
2948          * hw.mac->max_msix_vectors vectors.  With features
2949          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
2950          * descriptor queues supported by our device.  Thus, we cap it off in
2951          * those rare cases where the cpu count also exceeds our vector limit.
2952          */
2953         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
2954
2955         /* A failure in MSI-X entry allocation isn't fatal, but it does
2956          * mean we disable MSI-X capabilities of the adapter. */
2957         adapter->msix_entries = kcalloc(v_budget,
2958                                         sizeof(struct msix_entry), GFP_KERNEL);
2959         if (!adapter->msix_entries) {
2960                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2961                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2962                 ixgbe_set_num_queues(adapter);
2963                 kfree(adapter->tx_ring);
2964                 kfree(adapter->rx_ring);
2965                 err = ixgbe_alloc_queues(adapter);
2966                 if (err) {
2967                         DPRINTK(PROBE, ERR, "Unable to allocate memory "
2968                                 "for queues\n");
2969                         goto out;
2970                 }
2971
2972                 goto try_msi;
2973         }
2974
2975         for (vector = 0; vector < v_budget; vector++)
2976                 adapter->msix_entries[vector].entry = vector;
2977
2978         ixgbe_acquire_msix_vectors(adapter, v_budget);
2979
2980         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2981                 goto out;
2982
2983 try_msi:
2984         err = pci_enable_msi(adapter->pdev);
2985         if (!err) {
2986                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2987         } else {
2988                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
2989                         "falling back to legacy.  Error: %d\n", err);
2990                 /* reset err */
2991                 err = 0;
2992         }
2993
2994 out:
2995         /* Notify the stack of the (possibly) reduced Tx Queue count. */
2996         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
2997
2998         return err;
2999 }
3000
3001 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3002 {
3003         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3004                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3005                 pci_disable_msix(adapter->pdev);
3006                 kfree(adapter->msix_entries);
3007                 adapter->msix_entries = NULL;
3008         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3009                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3010                 pci_disable_msi(adapter->pdev);
3011         }
3012         return;
3013 }
3014
3015 /**
3016  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3017  * @adapter: board private structure to initialize
3018  *
3019  * We determine which interrupt scheme to use based on...
3020  * - Kernel support (MSI, MSI-X)
3021  *   - which can be user-defined (via MODULE_PARAM)
3022  * - Hardware queue count (num_*_queues)
3023  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3024  **/
3025 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3026 {
3027         int err;
3028
3029         /* Number of supported queues */
3030         ixgbe_set_num_queues(adapter);
3031
3032         err = ixgbe_alloc_queues(adapter);
3033         if (err) {
3034                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3035                 goto err_alloc_queues;
3036         }
3037
3038         err = ixgbe_set_interrupt_capability(adapter);
3039         if (err) {
3040                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3041                 goto err_set_interrupt;
3042         }
3043
3044         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3045                 "Tx Queue count = %u\n",
3046                 (adapter->num_rx_queues > 1) ? "Enabled" :
3047                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3048
3049         set_bit(__IXGBE_DOWN, &adapter->state);
3050
3051         return 0;
3052
3053 err_set_interrupt:
3054         kfree(adapter->tx_ring);
3055         kfree(adapter->rx_ring);
3056 err_alloc_queues:
3057         return err;
3058 }
3059
3060 /**
3061  * ixgbe_sfp_timer - worker thread to find a missing module
3062  * @data: pointer to our adapter struct
3063  **/
3064 static void ixgbe_sfp_timer(unsigned long data)
3065 {
3066         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3067
3068         /*
3069          * Do the sfp_timer outside of interrupt context due to the
3070          * delays that sfp+ detection requires
3071          */
3072         schedule_work(&adapter->sfp_task);
3073 }
3074
3075 /**
3076  * ixgbe_sfp_task - worker thread to find a missing module
3077  * @work: pointer to work_struct containing our data
3078  **/
3079 static void ixgbe_sfp_task(struct work_struct *work)
3080 {
3081         struct ixgbe_adapter *adapter = container_of(work,
3082                                                      struct ixgbe_adapter,
3083                                                      sfp_task);
3084         struct ixgbe_hw *hw = &adapter->hw;
3085
3086         if ((hw->phy.type == ixgbe_phy_nl) &&
3087             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3088                 s32 ret = hw->phy.ops.identify_sfp(hw);
3089                 if (ret)
3090                         goto reschedule;
3091                 ret = hw->phy.ops.reset(hw);
3092                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3093                         DPRINTK(PROBE, ERR, "failed to initialize because an "
3094                                 "unsupported SFP+ module type was detected.\n"
3095                                 "Reload the driver after installing a "
3096                                 "supported module.\n");
3097                         unregister_netdev(adapter->netdev);
3098                 } else {
3099                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3100                                 hw->phy.sfp_type);
3101                 }
3102                 /* don't need this routine any more */
3103                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3104         }
3105         return;
3106 reschedule:
3107         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3108                 mod_timer(&adapter->sfp_timer,
3109                           round_jiffies(jiffies + (2 * HZ)));
3110 }
3111
3112 /**
3113  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3114  * @adapter: board private structure to initialize
3115  *
3116  * ixgbe_sw_init initializes the Adapter private data structure.
3117  * Fields are initialized based on PCI device information and
3118  * OS network device settings (MTU size).
3119  **/
3120 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3121 {
3122         struct ixgbe_hw *hw = &adapter->hw;
3123         struct pci_dev *pdev = adapter->pdev;
3124         unsigned int rss;
3125 #ifdef CONFIG_IXGBE_DCB
3126         int j;
3127         struct tc_configuration *tc;
3128 #endif
3129
3130         /* PCI config space info */
3131
3132         hw->vendor_id = pdev->vendor;
3133         hw->device_id = pdev->device;
3134         hw->revision_id = pdev->revision;
3135         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3136         hw->subsystem_device_id = pdev->subsystem_device;
3137
3138         /* Set capability flags */
3139         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3140         adapter->ring_feature[RING_F_RSS].indices = rss;
3141         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3142         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3143         if (hw->mac.type == ixgbe_mac_82598EB)
3144                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3145         else if (hw->mac.type == ixgbe_mac_82599EB)
3146                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3147
3148 #ifdef CONFIG_IXGBE_DCB
3149         /* Configure DCB traffic classes */
3150         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3151                 tc = &adapter->dcb_cfg.tc_config[j];
3152                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3153                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3154                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3155                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3156                 tc->dcb_pfc = pfc_disabled;
3157         }
3158         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3159         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3160         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3161         adapter->dcb_cfg.round_robin_enable = false;
3162         adapter->dcb_set_bitmap = 0x00;
3163         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3164                            adapter->ring_feature[RING_F_DCB].indices);
3165
3166 #endif
3167
3168         /* default flow control settings */
3169         hw->fc.requested_mode = ixgbe_fc_full;
3170         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3171         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3172         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3173         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3174         hw->fc.send_xon = true;
3175         hw->fc.disable_fc_autoneg = false;
3176
3177         /* enable itr by default in dynamic mode */
3178         adapter->itr_setting = 1;
3179         adapter->eitr_param = 20000;
3180
3181         /* set defaults for eitr in MegaBytes */
3182         adapter->eitr_low = 10;
3183         adapter->eitr_high = 20;
3184
3185         /* set default ring sizes */
3186         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3187         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3188
3189         /* initialize eeprom parameters */
3190         if (ixgbe_init_eeprom_params_generic(hw)) {
3191                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3192                 return -EIO;
3193         }
3194
3195         /* enable rx csum by default */
3196         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3197
3198         set_bit(__IXGBE_DOWN, &adapter->state);
3199
3200         return 0;
3201 }
3202
3203 /**
3204  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3205  * @adapter: board private structure
3206  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
3207  *
3208  * Return 0 on success, negative on failure
3209  **/
3210 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3211                              struct ixgbe_ring *tx_ring)
3212 {
3213         struct pci_dev *pdev = adapter->pdev;
3214         int size;
3215
3216         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3217         tx_ring->tx_buffer_info = vmalloc(size);
3218         if (!tx_ring->tx_buffer_info)
3219                 goto err;
3220         memset(tx_ring->tx_buffer_info, 0, size);
3221
3222         /* round up to nearest 4K */
3223         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3224         tx_ring->size = ALIGN(tx_ring->size, 4096);
3225
3226         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3227                                              &tx_ring->dma);
3228         if (!tx_ring->desc)
3229                 goto err;
3230
3231         tx_ring->next_to_use = 0;
3232         tx_ring->next_to_clean = 0;
3233         tx_ring->work_limit = tx_ring->count;
3234         return 0;
3235
3236 err:
3237         vfree(tx_ring->tx_buffer_info);
3238         tx_ring->tx_buffer_info = NULL;
3239         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3240                             "descriptor ring\n");
3241         return -ENOMEM;
3242 }
3243
3244 /**
3245  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3246  * @adapter: board private structure
3247  *
3248  * If this function returns with an error, then it's possible one or
3249  * more of the rings is populated (while the rest are not).  It is the
3250  * callers duty to clean those orphaned rings.
3251  *
3252  * Return 0 on success, negative on failure
3253  **/
3254 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3255 {
3256         int i, err = 0;
3257
3258         for (i = 0; i < adapter->num_tx_queues; i++) {
3259                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3260                 if (!err)
3261                         continue;
3262                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3263                 break;
3264         }
3265
3266         return err;
3267 }
3268
3269 /**
3270  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3271  * @adapter: board private structure
3272  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
3273  *
3274  * Returns 0 on success, negative on failure
3275  **/
3276 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3277                              struct ixgbe_ring *rx_ring)
3278 {
3279         struct pci_dev *pdev = adapter->pdev;
3280         int size;
3281
3282         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3283         rx_ring->rx_buffer_info = vmalloc(size);
3284         if (!rx_ring->rx_buffer_info) {
3285                 DPRINTK(PROBE, ERR,
3286                         "vmalloc allocation failed for the rx desc ring\n");
3287                 goto alloc_failed;
3288         }
3289         memset(rx_ring->rx_buffer_info, 0, size);
3290
3291         /* Round up to nearest 4K */
3292         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3293         rx_ring->size = ALIGN(rx_ring->size, 4096);
3294
3295         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
3296
3297         if (!rx_ring->desc) {
3298                 DPRINTK(PROBE, ERR,
3299                         "Memory allocation failed for the rx desc ring\n");
3300                 vfree(rx_ring->rx_buffer_info);
3301                 goto alloc_failed;
3302         }
3303
3304         rx_ring->next_to_clean = 0;
3305         rx_ring->next_to_use = 0;
3306
3307         return 0;
3308
3309 alloc_failed:
3310         return -ENOMEM;
3311 }
3312
3313 /**
3314  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3315  * @adapter: board private structure
3316  *
3317  * If this function returns with an error, then it's possible one or
3318  * more of the rings is populated (while the rest are not).  It is the
3319  * callers duty to clean those orphaned rings.
3320  *
3321  * Return 0 on success, negative on failure
3322  **/
3323
3324 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3325 {
3326         int i, err = 0;
3327
3328         for (i = 0; i < adapter->num_rx_queues; i++) {
3329                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3330                 if (!err)
3331                         continue;
3332                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3333                 break;
3334         }
3335
3336         return err;
3337 }
3338
3339 /**
3340  * ixgbe_free_tx_resources - Free Tx Resources per Queue
3341  * @adapter: board private structure
3342  * @tx_ring: Tx descriptor ring for a specific queue
3343  *
3344  * Free all transmit software resources
3345  **/
3346 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3347                              struct ixgbe_ring *tx_ring)
3348 {
3349         struct pci_dev *pdev = adapter->pdev;
3350
3351         ixgbe_clean_tx_ring(adapter, tx_ring);
3352
3353         vfree(tx_ring->tx_buffer_info);
3354         tx_ring->tx_buffer_info = NULL;
3355
3356         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3357
3358         tx_ring->desc = NULL;
3359 }
3360
3361 /**
3362  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3363  * @adapter: board private structure
3364  *
3365  * Free all transmit software resources
3366  **/
3367 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3368 {
3369         int i;
3370
3371         for (i = 0; i < adapter->num_tx_queues; i++)
3372                 if (adapter->tx_ring[i].desc)
3373                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
3374 }
3375
3376 /**
3377  * ixgbe_free_rx_resources - Free Rx Resources
3378  * @adapter: board private structure
3379  * @rx_ring: ring to clean the resources from
3380  *
3381  * Free all receive software resources
3382  **/
3383 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3384                              struct ixgbe_ring *rx_ring)
3385 {
3386         struct pci_dev *pdev = adapter->pdev;
3387
3388         ixgbe_clean_rx_ring(adapter, rx_ring);
3389
3390         vfree(rx_ring->rx_buffer_info);
3391         rx_ring->rx_buffer_info = NULL;
3392
3393         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3394
3395         rx_ring->desc = NULL;
3396 }
3397
3398 /**
3399  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3400  * @adapter: board private structure
3401  *
3402  * Free all receive software resources
3403  **/
3404 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3405 {
3406         int i;
3407
3408         for (i = 0; i < adapter->num_rx_queues; i++)
3409                 if (adapter->rx_ring[i].desc)
3410                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
3411 }
3412
3413 /**
3414  * ixgbe_change_mtu - Change the Maximum Transfer Unit
3415  * @netdev: network interface device structure
3416  * @new_mtu: new value for maximum frame size
3417  *
3418  * Returns 0 on success, negative on failure
3419  **/
3420 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3421 {
3422         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3423         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3424
3425         /* MTU < 68 is an error and causes problems on some kernels */
3426         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
3427                 return -EINVAL;
3428
3429         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
3430                 netdev->mtu, new_mtu);
3431         /* must set new MTU before calling down or up */
3432         netdev->mtu = new_mtu;
3433
3434         if (netif_running(netdev))
3435                 ixgbe_reinit_locked(adapter);
3436
3437         return 0;
3438 }
3439
3440 /**
3441  * ixgbe_open - Called when a network interface is made active
3442  * @netdev: network interface device structure
3443  *
3444  * Returns 0 on success, negative value on failure
3445  *
3446  * The open entry point is called when a network interface is made
3447  * active by the system (IFF_UP).  At this point all resources needed
3448  * for transmit and receive operations are allocated, the interrupt
3449  * handler is registered with the OS, the watchdog timer is started,
3450  * and the stack is notified that the interface is ready.
3451  **/
3452 static int ixgbe_open(struct net_device *netdev)
3453 {
3454         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3455         int err;
3456
3457         /* disallow open during test */
3458         if (test_bit(__IXGBE_TESTING, &adapter->state))
3459                 return -EBUSY;
3460
3461         /* allocate transmit descriptors */
3462         err = ixgbe_setup_all_tx_resources(adapter);
3463         if (err)
3464                 goto err_setup_tx;
3465
3466         /* allocate receive descriptors */
3467         err = ixgbe_setup_all_rx_resources(adapter);
3468         if (err)
3469                 goto err_setup_rx;
3470
3471         ixgbe_configure(adapter);
3472
3473         ixgbe_napi_add_all(adapter);
3474
3475         err = ixgbe_request_irq(adapter);
3476         if (err)
3477                 goto err_req_irq;
3478
3479         err = ixgbe_up_complete(adapter);
3480         if (err)
3481                 goto err_up;
3482
3483         netif_tx_start_all_queues(netdev);
3484
3485         return 0;
3486
3487 err_up:
3488         ixgbe_release_hw_control(adapter);
3489         ixgbe_free_irq(adapter);
3490 err_req_irq:
3491 err_setup_rx:
3492         ixgbe_free_all_rx_resources(adapter);
3493 err_setup_tx:
3494         ixgbe_free_all_tx_resources(adapter);
3495         ixgbe_reset(adapter);
3496
3497         return err;
3498 }
3499
3500 /**
3501  * ixgbe_close - Disables a network interface
3502  * @netdev: network interface device structure
3503  *
3504  * Returns 0, this is not allowed to fail
3505  *
3506  * The close entry point is called when an interface is de-activated
3507  * by the OS.  The hardware is still under the drivers control, but
3508  * needs to be disabled.  A global MAC reset is issued to stop the
3509  * hardware, and all transmit and receive resources are freed.
3510  **/
3511 static int ixgbe_close(struct net_device *netdev)
3512 {
3513         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3514
3515         ixgbe_down(adapter);
3516         ixgbe_free_irq(adapter);
3517
3518         ixgbe_free_all_tx_resources(adapter);
3519         ixgbe_free_all_rx_resources(adapter);
3520
3521         ixgbe_release_hw_control(adapter);
3522
3523         return 0;
3524 }
3525
3526 /**
3527  * ixgbe_napi_add_all - prep napi structs for use
3528  * @adapter: private struct
3529  *
3530  * helper function to napi_add each possible q_vector->napi
3531  */
3532 void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3533 {
3534         int q_idx, q_vectors;
3535         struct net_device *netdev = adapter->netdev;
3536         int (*poll)(struct napi_struct *, int);
3537
3538         /* check if we already have our netdev->napi_list populated */
3539         if (&netdev->napi_list != netdev->napi_list.next)
3540                 return;
3541
3542         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3543                 poll = &ixgbe_clean_rxonly;
3544                 /* Only enable as many vectors as we have rx queues. */
3545                 q_vectors = adapter->num_rx_queues;
3546         } else {
3547                 poll = &ixgbe_poll;
3548                 /* only one q_vector for legacy modes */
3549                 q_vectors = 1;
3550         }
3551
3552         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3553                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3554                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3555         }
3556 }
3557
3558 void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
3559 {
3560         int q_idx;
3561         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3562
3563         /* legacy and MSI only use one vector */
3564         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3565                 q_vectors = 1;
3566
3567         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3568                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3569                 if (!q_vector->rxr_count)
3570                         continue;
3571                 netif_napi_del(&q_vector->napi);
3572         }
3573 }
3574
3575 #ifdef CONFIG_PM
3576 static int ixgbe_resume(struct pci_dev *pdev)
3577 {
3578         struct net_device *netdev = pci_get_drvdata(pdev);
3579         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3580         u32 err;
3581
3582         pci_set_power_state(pdev, PCI_D0);
3583         pci_restore_state(pdev);
3584         err = pci_enable_device(pdev);
3585         if (err) {
3586                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
3587                                 "suspend\n");
3588                 return err;
3589         }
3590         pci_set_master(pdev);
3591
3592         pci_enable_wake(pdev, PCI_D3hot, 0);
3593         pci_enable_wake(pdev, PCI_D3cold, 0);
3594
3595         err = ixgbe_init_interrupt_scheme(adapter);
3596         if (err) {
3597                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3598                                 "device\n");
3599                 return err;
3600         }
3601
3602         ixgbe_reset(adapter);
3603
3604         if (netif_running(netdev)) {
3605                 err = ixgbe_open(adapter->netdev);
3606                 if (err)
3607                         return err;
3608         }
3609
3610         netif_device_attach(netdev);
3611
3612         return 0;
3613 }
3614
3615 #endif /* CONFIG_PM */
3616 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3617 {
3618         struct net_device *netdev = pci_get_drvdata(pdev);
3619         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3620         struct ixgbe_hw *hw = &adapter->hw;
3621         u32 ctrl, fctrl;
3622         u32 wufc = adapter->wol;
3623 #ifdef CONFIG_PM
3624         int retval = 0;
3625 #endif
3626
3627         netif_device_detach(netdev);
3628
3629         if (netif_running(netdev)) {
3630                 ixgbe_down(adapter);
3631                 ixgbe_free_irq(adapter);
3632                 ixgbe_free_all_tx_resources(adapter);
3633                 ixgbe_free_all_rx_resources(adapter);
3634         }
3635         ixgbe_reset_interrupt_capability(adapter);
3636         ixgbe_napi_del_all(adapter);
3637         INIT_LIST_HEAD(&netdev->napi_list);
3638         kfree(adapter->tx_ring);
3639         kfree(adapter->rx_ring);
3640
3641 #ifdef CONFIG_PM
3642         retval = pci_save_state(pdev);
3643         if (retval)
3644                 return retval;
3645
3646 #endif
3647         if (wufc) {
3648                 ixgbe_set_rx_mode(netdev);
3649
3650                 /* turn on all-multi mode if wake on multicast is enabled */
3651                 if (wufc & IXGBE_WUFC_MC) {
3652                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3653                         fctrl |= IXGBE_FCTRL_MPE;
3654                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3655                 }
3656
3657                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3658                 ctrl |= IXGBE_CTRL_GIO_DIS;
3659                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3660
3661                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
3662         } else {
3663                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
3664                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
3665         }
3666
3667         if (wufc && hw->mac.type == ixgbe_mac_82599EB) {
3668                 pci_enable_wake(pdev, PCI_D3hot, 1);
3669                 pci_enable_wake(pdev, PCI_D3cold, 1);
3670         } else {
3671                 pci_enable_wake(pdev, PCI_D3hot, 0);
3672                 pci_enable_wake(pdev, PCI_D3cold, 0);
3673         }
3674
3675         ixgbe_release_hw_control(adapter);
3676
3677         pci_disable_device(pdev);
3678
3679         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3680
3681         return 0;
3682 }
3683
3684 static void ixgbe_shutdown(struct pci_dev *pdev)
3685 {
3686         ixgbe_suspend(pdev, PMSG_SUSPEND);
3687 }
3688
3689 /**
3690  * ixgbe_update_stats - Update the board statistics counters.
3691  * @adapter: board private structure
3692  **/
3693 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3694 {
3695         struct ixgbe_hw *hw = &adapter->hw;
3696         u64 total_mpc = 0;
3697         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
3698
3699         if (hw->mac.type == ixgbe_mac_82599EB) {
3700                 for (i = 0; i < 16; i++)
3701                         adapter->hw_rx_no_dma_resources +=
3702                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3703         }
3704
3705         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3706         for (i = 0; i < 8; i++) {
3707                 /* for packet buffers not used, the register should read 0 */
3708                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3709                 missed_rx += mpc;
3710                 adapter->stats.mpc[i] += mpc;
3711                 total_mpc += adapter->stats.mpc[i];
3712                 if (hw->mac.type == ixgbe_mac_82598EB)
3713                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3714                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3715                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3716                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3717                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
3718                 if (hw->mac.type == ixgbe_mac_82599EB) {
3719                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3720                                                             IXGBE_PXONRXCNT(i));
3721                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3722                                                            IXGBE_PXOFFRXCNT(i));
3723                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3724                 } else {
3725                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3726                                                               IXGBE_PXONRXC(i));
3727                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3728                                                              IXGBE_PXOFFRXC(i));
3729                 }
3730                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3731                                                             IXGBE_PXONTXC(i));
3732                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
3733                                                              IXGBE_PXOFFTXC(i));
3734         }
3735         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3736         /* work around hardware counting issue */
3737         adapter->stats.gprc -= missed_rx;
3738
3739         /* 82598 hardware only has a 32 bit counter in the high register */
3740         if (hw->mac.type == ixgbe_mac_82599EB) {
3741                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3742                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
3743                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3744                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
3745                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3746                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
3747                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3748                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3749         } else {
3750                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3751                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3752                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3753                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3754                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3755         }
3756         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3757         adapter->stats.bprc += bprc;
3758         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3759         if (hw->mac.type == ixgbe_mac_82598EB)
3760                 adapter->stats.mprc -= bprc;
3761         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3762         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3763         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3764         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3765         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3766         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3767         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3768         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3769         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3770         adapter->stats.lxontxc += lxon;
3771         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3772         adapter->stats.lxofftxc += lxoff;
3773         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3774         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
3775         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3776         /*
3777          * 82598 errata - tx of flow control packets is included in tx counters
3778          */
3779         xon_off_tot = lxon + lxoff;
3780         adapter->stats.gptc -= xon_off_tot;
3781         adapter->stats.mptc -= xon_off_tot;
3782         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
3783         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3784         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3785         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3786         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3787         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3788         adapter->stats.ptc64 -= xon_off_tot;
3789         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3790         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3791         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3792         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3793         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3794         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3795
3796         /* Fill out the OS statistics structure */
3797         adapter->net_stats.multicast = adapter->stats.mprc;
3798
3799         /* Rx Errors */
3800         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
3801                                        adapter->stats.rlec;
3802         adapter->net_stats.rx_dropped = 0;
3803         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3804         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3805         adapter->net_stats.rx_missed_errors = total_mpc;
3806 }
3807
3808 /**
3809  * ixgbe_watchdog - Timer Call-back
3810  * @data: pointer to adapter cast into an unsigned long
3811  **/
3812 static void ixgbe_watchdog(unsigned long data)
3813 {
3814         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3815         struct ixgbe_hw *hw = &adapter->hw;
3816
3817         /* Do the watchdog outside of interrupt context due to the lovely
3818          * delays that some of the newer hardware requires */
3819         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3820                 u64 eics = 0;
3821                 int i;
3822
3823                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++)
3824                         eics |= (1 << i);
3825
3826                 /* Cause software interrupt to ensure rx rings are cleaned */
3827                 switch (hw->mac.type) {
3828                 case ixgbe_mac_82598EB:
3829                         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3830                                 IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics);
3831                         } else {
3832                                 /*
3833                                  * for legacy and MSI interrupts don't set any
3834                                  * bits that are enabled for EIAM, because this
3835                                  * operation would set *both* EIMS and EICS for
3836                                  * any bit in EIAM
3837                                  */
3838                                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3839                                      (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3840                         }
3841                         break;
3842                 case ixgbe_mac_82599EB:
3843                         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3844                                 /*
3845                                  * EICS(0..15) first 0-15 q vectors
3846                                  * EICS[1] (16..31) q vectors 16-31
3847                                  * EICS[2] (0..31) q vectors 32-63
3848                                  */
3849                                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3850                                                 (u32)(eics & 0xFFFF));
3851                                 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1),
3852                                                 (u32)(eics & 0xFFFF0000));
3853                                 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(2),
3854                                                 (u32)(eics >> 32));
3855                         } else {
3856                                 /*
3857                                  * for legacy and MSI interrupts don't set any
3858                                  * bits that are enabled for EIAM, because this
3859                                  * operation would set *both* EIMS and EICS for
3860                                  * any bit in EIAM
3861                                  */
3862                                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3863                                      (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3864                         }
3865                         break;
3866                 default:
3867                         break;
3868                 }
3869                 /* Reset the timer */
3870                 mod_timer(&adapter->watchdog_timer,
3871                           round_jiffies(jiffies + 2 * HZ));
3872         }
3873
3874         schedule_work(&adapter->watchdog_task);
3875 }
3876
3877 /**
3878  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
3879  * @work: pointer to work_struct containing our data
3880  **/
3881 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
3882 {
3883         struct ixgbe_adapter *adapter = container_of(work,
3884                                                      struct ixgbe_adapter,
3885                                                      multispeed_fiber_task);
3886         struct ixgbe_hw *hw = &adapter->hw;
3887         u32 autoneg;
3888
3889         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
3890         if (hw->mac.ops.get_link_capabilities)
3891                 hw->mac.ops.get_link_capabilities(hw, &autoneg,
3892                                                   &hw->mac.autoneg);
3893         if (hw->mac.ops.setup_link_speed)
3894                 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
3895         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3896         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
3897 }
3898
3899 /**
3900  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
3901  * @work: pointer to work_struct containing our data
3902  **/
3903 static void ixgbe_sfp_config_module_task(struct work_struct *work)
3904 {
3905         struct ixgbe_adapter *adapter = container_of(work,
3906                                                      struct ixgbe_adapter,
3907                                                      sfp_config_module_task);
3908         struct ixgbe_hw *hw = &adapter->hw;
3909         u32 err;
3910
3911         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
3912         err = hw->phy.ops.identify_sfp(hw);
3913         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3914                 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
3915                 ixgbe_down(adapter);
3916                 return;
3917         }
3918         hw->mac.ops.setup_sfp(hw);
3919
3920         if (!adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)
3921                 /* This will also work for DA Twinax connections */
3922                 schedule_work(&adapter->multispeed_fiber_task);
3923         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
3924 }
3925
3926 /**
3927  * ixgbe_watchdog_task - worker thread to bring link up
3928  * @work: pointer to work_struct containing our data
3929  **/
3930 static void ixgbe_watchdog_task(struct work_struct *work)
3931 {
3932         struct ixgbe_adapter *adapter = container_of(work,
3933                                                      struct ixgbe_adapter,
3934                                                      watchdog_task);
3935         struct net_device *netdev = adapter->netdev;
3936         struct ixgbe_hw *hw = &adapter->hw;
3937         u32 link_speed = adapter->link_speed;
3938         bool link_up = adapter->link_up;
3939
3940         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3941
3942         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3943                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3944                 if (link_up ||
3945                     time_after(jiffies, (adapter->link_check_timeout +
3946                                          IXGBE_TRY_LINK_TIMEOUT))) {
3947                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3948                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3949                 }
3950                 adapter->link_up = link_up;
3951                 adapter->link_speed = link_speed;
3952         }
3953
3954         if (link_up) {
3955                 if (!netif_carrier_ok(netdev)) {
3956                         bool flow_rx, flow_tx;
3957
3958                         if (hw->mac.type == ixgbe_mac_82599EB) {
3959                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3960                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3961                                 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
3962                                 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
3963                         } else {
3964                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3965                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
3966                                 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
3967                                 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
3968                         }
3969
3970                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
3971                                "Flow Control: %s\n",
3972                                netdev->name,
3973                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3974                                 "10 Gbps" :
3975                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3976                                  "1 Gbps" : "unknown speed")),
3977                                ((flow_rx && flow_tx) ? "RX/TX" :
3978                                 (flow_rx ? "RX" :
3979                                 (flow_tx ? "TX" : "None"))));
3980
3981                         netif_carrier_on(netdev);
3982                 } else {
3983                         /* Force detection of hung controller */
3984                         adapter->detect_tx_hung = true;
3985                 }
3986         } else {
3987                 adapter->link_up = false;
3988                 adapter->link_speed = 0;
3989                 if (netif_carrier_ok(netdev)) {
3990                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
3991                                netdev->name);
3992                         netif_carrier_off(netdev);
3993                 }
3994         }
3995
3996         ixgbe_update_stats(adapter);
3997         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
3998 }
3999
4000 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4001                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4002                      u32 tx_flags, u8 *hdr_len)
4003 {
4004         struct ixgbe_adv_tx_context_desc *context_desc;
4005         unsigned int i;
4006         int err;
4007         struct ixgbe_tx_buffer *tx_buffer_info;
4008         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4009         u32 mss_l4len_idx, l4len;
4010
4011         if (skb_is_gso(skb)) {
4012                 if (skb_header_cloned(skb)) {
4013                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4014                         if (err)
4015                                 return err;
4016                 }
4017                 l4len = tcp_hdrlen(skb);
4018                 *hdr_len += l4len;
4019
4020                 if (skb->protocol == htons(ETH_P_IP)) {
4021                         struct iphdr *iph = ip_hdr(skb);
4022                         iph->tot_len = 0;
4023                         iph->check = 0;
4024                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4025                                                                  iph->daddr, 0,
4026                                                                  IPPROTO_TCP,
4027                                                                  0);
4028                         adapter->hw_tso_ctxt++;
4029                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4030                         ipv6_hdr(skb)->payload_len = 0;
4031                         tcp_hdr(skb)->check =
4032                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4033                                              &ipv6_hdr(skb)->daddr,
4034                                              0, IPPROTO_TCP, 0);
4035                         adapter->hw_tso6_ctxt++;
4036                 }
4037
4038                 i = tx_ring->next_to_use;
4039
4040                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4041                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4042
4043                 /* VLAN MACLEN IPLEN */
4044                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4045                         vlan_macip_lens |=
4046                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4047                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4048                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4049                 *hdr_len += skb_network_offset(skb);
4050                 vlan_macip_lens |=
4051                     (skb_transport_header(skb) - skb_network_header(skb));
4052                 *hdr_len +=
4053                     (skb_transport_header(skb) - skb_network_header(skb));
4054                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4055                 context_desc->seqnum_seed = 0;
4056
4057                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4058                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4059                                    IXGBE_ADVTXD_DTYP_CTXT);
4060
4061                 if (skb->protocol == htons(ETH_P_IP))
4062                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4063                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4064                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4065
4066                 /* MSS L4LEN IDX */
4067                 mss_l4len_idx =
4068                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4069                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4070                 /* use index 1 for TSO */
4071                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4072                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4073
4074                 tx_buffer_info->time_stamp = jiffies;
4075                 tx_buffer_info->next_to_watch = i;
4076
4077                 i++;
4078                 if (i == tx_ring->count)
4079                         i = 0;
4080                 tx_ring->next_to_use = i;
4081
4082                 return true;
4083         }
4084         return false;
4085 }
4086
4087 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4088                           struct ixgbe_ring *tx_ring,
4089                           struct sk_buff *skb, u32 tx_flags)
4090 {
4091         struct ixgbe_adv_tx_context_desc *context_desc;
4092         unsigned int i;
4093         struct ixgbe_tx_buffer *tx_buffer_info;
4094         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4095
4096         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4097             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4098                 i = tx_ring->next_to_use;
4099                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4100                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4101
4102                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4103                         vlan_macip_lens |=
4104                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4105                 vlan_macip_lens |= (skb_network_offset(skb) <<
4106                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4107                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4108                         vlan_macip_lens |= (skb_transport_header(skb) -
4109                                             skb_network_header(skb));
4110
4111                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4112                 context_desc->seqnum_seed = 0;
4113
4114                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4115                                     IXGBE_ADVTXD_DTYP_CTXT);
4116
4117                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4118                         switch (skb->protocol) {
4119                         case cpu_to_be16(ETH_P_IP):
4120                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4121                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4122                                         type_tucmd_mlhl |=
4123                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4124                                 break;
4125                         case cpu_to_be16(ETH_P_IPV6):
4126                                 /* XXX what about other V6 headers?? */
4127                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4128                                         type_tucmd_mlhl |=
4129                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4130                                 break;
4131                         default:
4132                                 if (unlikely(net_ratelimit())) {
4133                                         DPRINTK(PROBE, WARNING,
4134                                          "partial checksum but proto=%x!\n",
4135                                          skb->protocol);
4136                                 }
4137                                 break;
4138                         }
4139                 }
4140
4141                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4142                 /* use index zero for tx checksum offload */
4143                 context_desc->mss_l4len_idx = 0;
4144
4145                 tx_buffer_info->time_stamp = jiffies;
4146                 tx_buffer_info->next_to_watch = i;
4147
4148                 adapter->hw_csum_tx_good++;
4149                 i++;
4150                 if (i == tx_ring->count)
4151                         i = 0;
4152                 tx_ring->next_to_use = i;
4153
4154                 return true;
4155         }
4156
4157         return false;
4158 }
4159
4160 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4161                         struct ixgbe_ring *tx_ring,
4162                         struct sk_buff *skb, unsigned int first)
4163 {
4164         struct ixgbe_tx_buffer *tx_buffer_info;
4165         unsigned int len = skb_headlen(skb);
4166         unsigned int offset = 0, size, count = 0, i;
4167         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4168         unsigned int f;
4169         dma_addr_t *map;
4170
4171         i = tx_ring->next_to_use;
4172
4173         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4174                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4175                 return 0;
4176         }
4177
4178         map = skb_shinfo(skb)->dma_maps;
4179
4180         while (len) {
4181                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4182                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4183
4184                 tx_buffer_info->length = size;
4185                 tx_buffer_info->dma = map[0] + offset;
4186                 tx_buffer_info->time_stamp = jiffies;
4187                 tx_buffer_info->next_to_watch = i;
4188
4189                 len -= size;
4190                 offset += size;
4191                 count++;
4192
4193                 if (len) {
4194                         i++;
4195                         if (i == tx_ring->count)
4196                                 i = 0;
4197                 }
4198         }
4199
4200         for (f = 0; f < nr_frags; f++) {
4201                 struct skb_frag_struct *frag;
4202
4203                 frag = &skb_shinfo(skb)->frags[f];
4204                 len = frag->size;
4205                 offset = 0;
4206
4207                 while (len) {
4208                         i++;
4209                         if (i == tx_ring->count)
4210                                 i = 0;
4211
4212                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
4213                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4214
4215                         tx_buffer_info->length = size;
4216                         tx_buffer_info->dma = map[f + 1] + offset;
4217                         tx_buffer_info->time_stamp = jiffies;
4218                         tx_buffer_info->next_to_watch = i;
4219
4220                         len -= size;
4221                         offset += size;
4222                         count++;
4223                 }
4224         }
4225
4226         tx_ring->tx_buffer_info[i].skb = skb;
4227         tx_ring->tx_buffer_info[first].next_to_watch = i;
4228
4229         return count;
4230 }
4231
4232 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
4233                            struct ixgbe_ring *tx_ring,
4234                            int tx_flags, int count, u32 paylen, u8 hdr_len)
4235 {
4236         union ixgbe_adv_tx_desc *tx_desc = NULL;
4237         struct ixgbe_tx_buffer *tx_buffer_info;
4238         u32 olinfo_status = 0, cmd_type_len = 0;
4239         unsigned int i;
4240         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4241
4242         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4243
4244         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4245
4246         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4247                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4248
4249         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4250                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4251
4252                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4253                                  IXGBE_ADVTXD_POPTS_SHIFT;
4254
4255                 /* use index 1 context for tso */
4256                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4257                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4258                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
4259                                          IXGBE_ADVTXD_POPTS_SHIFT;
4260
4261         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4262                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4263                                  IXGBE_ADVTXD_POPTS_SHIFT;
4264
4265         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4266
4267         i = tx_ring->next_to_use;
4268         while (count--) {
4269                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4270                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4271                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4272                 tx_desc->read.cmd_type_len =
4273                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
4274                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4275                 i++;
4276                 if (i == tx_ring->count)
4277                         i = 0;
4278         }
4279
4280         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4281
4282         /*
4283          * Force memory writes to complete before letting h/w
4284          * know there are new descriptors to fetch.  (Only
4285          * applicable for weak-ordered memory model archs,
4286          * such as IA-64).
4287          */
4288         wmb();
4289
4290         tx_ring->next_to_use = i;
4291         writel(i, adapter->hw.hw_addr + tx_ring->tail);
4292 }
4293
4294 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
4295                                  struct ixgbe_ring *tx_ring, int size)
4296 {
4297         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4298
4299         netif_stop_subqueue(netdev, tx_ring->queue_index);
4300         /* Herbert's original patch had:
4301          *  smp_mb__after_netif_stop_queue();
4302          * but since that doesn't exist yet, just open code it. */
4303         smp_mb();
4304
4305         /* We need to check again in a case another CPU has just
4306          * made room available. */
4307         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4308                 return -EBUSY;
4309
4310         /* A reprieve! - use start_queue because it doesn't call schedule */
4311         netif_start_subqueue(netdev, tx_ring->queue_index);
4312         ++adapter->restart_queue;
4313         return 0;
4314 }
4315
4316 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
4317                               struct ixgbe_ring *tx_ring, int size)
4318 {
4319         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4320                 return 0;
4321         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4322 }
4323
4324 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
4325 {
4326         struct ixgbe_adapter *adapter = netdev_priv(dev);
4327
4328         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4329                 return 0;  /* All traffic should default to class 0 */
4330
4331         return skb_tx_hash(dev, skb);
4332 }
4333
4334 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4335 {
4336         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4337         struct ixgbe_ring *tx_ring;
4338         unsigned int first;
4339         unsigned int tx_flags = 0;
4340         u8 hdr_len = 0;
4341         int r_idx = 0, tso;
4342         int count = 0;
4343         unsigned int f;
4344
4345         r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
4346         tx_ring = &adapter->tx_ring[r_idx];
4347
4348         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4349                 tx_flags |= vlan_tx_tag_get(skb);
4350                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4351                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4352                         tx_flags |= (skb->queue_mapping << 13);
4353                 }
4354                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4355                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4356         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4357                 tx_flags |= (skb->queue_mapping << 13);
4358                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4359                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4360         }
4361         /* three things can cause us to need a context descriptor */
4362         if (skb_is_gso(skb) ||
4363             (skb->ip_summed == CHECKSUM_PARTIAL) ||
4364             (tx_flags & IXGBE_TX_FLAGS_VLAN))
4365                 count++;
4366
4367         count += TXD_USE_COUNT(skb_headlen(skb));
4368         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4369                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4370
4371         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
4372                 adapter->tx_busy++;
4373                 return NETDEV_TX_BUSY;
4374         }
4375
4376         if (skb->protocol == htons(ETH_P_IP))
4377                 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4378         first = tx_ring->next_to_use;
4379         tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4380         if (tso < 0) {
4381                 dev_kfree_skb_any(skb);
4382                 return NETDEV_TX_OK;
4383         }
4384
4385         if (tso)
4386                 tx_flags |= IXGBE_TX_FLAGS_TSO;
4387         else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
4388                  (skb->ip_summed == CHECKSUM_PARTIAL))
4389                 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4390
4391         count = ixgbe_tx_map(adapter, tx_ring, skb, first);
4392
4393         if (count) {
4394                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
4395                                hdr_len);
4396                 netdev->trans_start = jiffies;
4397                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
4398
4399         } else {
4400                 dev_kfree_skb_any(skb);
4401                 tx_ring->tx_buffer_info[first].time_stamp = 0;
4402                 tx_ring->next_to_use = first;
4403         }
4404
4405         return NETDEV_TX_OK;
4406 }
4407
4408 /**
4409  * ixgbe_get_stats - Get System Network Statistics
4410  * @netdev: network interface device structure
4411  *
4412  * Returns the address of the device statistics structure.
4413  * The statistics are actually updated from the timer callback.
4414  **/
4415 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4416 {
4417         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4418
4419         /* only return the current stats */
4420         return &adapter->net_stats;
4421 }
4422
4423 /**
4424  * ixgbe_set_mac - Change the Ethernet Address of the NIC
4425  * @netdev: network interface device structure
4426  * @p: pointer to an address structure
4427  *
4428  * Returns 0 on success, negative on failure
4429  **/
4430 static int ixgbe_set_mac(struct net_device *netdev, void *p)
4431 {
4432         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4433         struct ixgbe_hw *hw = &adapter->hw;
4434         struct sockaddr *addr = p;
4435
4436         if (!is_valid_ether_addr(addr->sa_data))
4437                 return -EADDRNOTAVAIL;
4438
4439         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4440         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
4441
4442         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
4443
4444         return 0;
4445 }
4446
4447 #ifdef CONFIG_NET_POLL_CONTROLLER
4448 /*
4449  * Polling 'interrupt' - used by things like netconsole to send skbs
4450  * without having to re-enable interrupts. It's not called while
4451  * the interrupt routine is executing.
4452  */
4453 static void ixgbe_netpoll(struct net_device *netdev)
4454 {
4455         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4456
4457         disable_irq(adapter->pdev->irq);
4458         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
4459         ixgbe_intr(adapter->pdev->irq, netdev);
4460         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
4461         enable_irq(adapter->pdev->irq);
4462 }
4463 #endif
4464
4465 static const struct net_device_ops ixgbe_netdev_ops = {
4466         .ndo_open               = ixgbe_open,
4467         .ndo_stop               = ixgbe_close,
4468         .ndo_start_xmit         = ixgbe_xmit_frame,
4469         .ndo_select_queue       = ixgbe_select_queue,
4470         .ndo_get_stats          = ixgbe_get_stats,
4471         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
4472         .ndo_set_multicast_list = ixgbe_set_rx_mode,
4473         .ndo_validate_addr      = eth_validate_addr,
4474         .ndo_set_mac_address    = ixgbe_set_mac,
4475         .ndo_change_mtu         = ixgbe_change_mtu,
4476         .ndo_tx_timeout         = ixgbe_tx_timeout,
4477         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
4478         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
4479         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
4480 #ifdef CONFIG_NET_POLL_CONTROLLER
4481         .ndo_poll_controller    = ixgbe_netpoll,
4482 #endif
4483 };
4484
4485 /**
4486  * ixgbe_probe - Device Initialization Routine
4487  * @pdev: PCI device information struct
4488  * @ent: entry in ixgbe_pci_tbl
4489  *
4490  * Returns 0 on success, negative on failure
4491  *
4492  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
4493  * The OS initialization, configuring of the adapter private structure,
4494  * and a hardware reset occur.
4495  **/
4496 static int __devinit ixgbe_probe(struct pci_dev *pdev,
4497                                  const struct pci_device_id *ent)
4498 {
4499         struct net_device *netdev;
4500         struct ixgbe_adapter *adapter = NULL;
4501         struct ixgbe_hw *hw;
4502         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
4503         static int cards_found;
4504         int i, err, pci_using_dac;
4505         u16 pm_value = 0;
4506         u32 part_num, eec;
4507
4508         err = pci_enable_device(pdev);
4509         if (err)
4510                 return err;
4511
4512         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
4513             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
4514                 pci_using_dac = 1;
4515         } else {
4516                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4517                 if (err) {
4518                         err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
4519                         if (err) {
4520                                 dev_err(&pdev->dev, "No usable DMA "
4521                                         "configuration, aborting\n");
4522                                 goto err_dma;
4523                         }
4524                 }
4525                 pci_using_dac = 0;
4526         }
4527
4528         err = pci_request_regions(pdev, ixgbe_driver_name);
4529         if (err) {
4530                 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
4531                 goto err_pci_reg;
4532         }
4533
4534         err = pci_enable_pcie_error_reporting(pdev);
4535         if (err) {
4536                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4537                                     "0x%x\n", err);
4538                 /* non-fatal, continue */
4539         }
4540
4541         pci_set_master(pdev);
4542         pci_save_state(pdev);
4543
4544         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
4545         if (!netdev) {
4546                 err = -ENOMEM;
4547                 goto err_alloc_etherdev;
4548         }
4549
4550         SET_NETDEV_DEV(netdev, &pdev->dev);
4551
4552         pci_set_drvdata(pdev, netdev);
4553         adapter = netdev_priv(netdev);
4554
4555         adapter->netdev = netdev;
4556         adapter->pdev = pdev;
4557         hw = &adapter->hw;
4558         hw->back = adapter;
4559         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4560
4561         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4562                               pci_resource_len(pdev, 0));
4563         if (!hw->hw_addr) {
4564                 err = -EIO;
4565                 goto err_ioremap;
4566         }
4567
4568         for (i = 1; i <= 5; i++) {
4569                 if (pci_resource_len(pdev, i) == 0)
4570                         continue;
4571         }
4572
4573         netdev->netdev_ops = &ixgbe_netdev_ops;
4574         ixgbe_set_ethtool_ops(netdev);
4575         netdev->watchdog_timeo = 5 * HZ;
4576         strcpy(netdev->name, pci_name(pdev));
4577
4578         adapter->bd_number = cards_found;
4579
4580         /* Setup hw api */
4581         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
4582         hw->mac.type  = ii->mac;
4583
4584         /* EEPROM */
4585         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4586         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4587         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4588         if (!(eec & (1 << 8)))
4589                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4590
4591         /* PHY */
4592         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
4593         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4594
4595         /* set up this timer and work struct before calling get_invariants
4596          * which might start the timer
4597          */
4598         init_timer(&adapter->sfp_timer);
4599         adapter->sfp_timer.function = &ixgbe_sfp_timer;
4600         adapter->sfp_timer.data = (unsigned long) adapter;
4601
4602         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
4603
4604         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
4605         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
4606
4607         /* a new SFP+ module arrival, called from GPI SDP2 context */
4608         INIT_WORK(&adapter->sfp_config_module_task,
4609                   ixgbe_sfp_config_module_task);
4610
4611         err = ii->get_invariants(hw);
4612         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4613                 /* start a kernel thread to watch for a module to arrive */
4614                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4615                 mod_timer(&adapter->sfp_timer,
4616                           round_jiffies(jiffies + (2 * HZ)));
4617                 err = 0;
4618         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4619                 DPRINTK(PROBE, ERR, "failed to load because an "
4620                         "unsupported SFP+ module type was detected.\n");
4621                 goto err_hw_init;
4622         } else if (err) {
4623                 goto err_hw_init;
4624         }
4625
4626         /* setup the private structure */
4627         err = ixgbe_sw_init(adapter);
4628         if (err)
4629                 goto err_sw_init;
4630
4631         /* reset_hw fills in the perm_addr as well */
4632         err = hw->mac.ops.reset_hw(hw);
4633         if (err) {
4634                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4635                 goto err_sw_init;
4636         }
4637
4638         netdev->features = NETIF_F_SG |
4639                            NETIF_F_IP_CSUM |
4640                            NETIF_F_HW_VLAN_TX |
4641                            NETIF_F_HW_VLAN_RX |
4642                            NETIF_F_HW_VLAN_FILTER;
4643
4644         netdev->features |= NETIF_F_IPV6_CSUM;
4645         netdev->features |= NETIF_F_TSO;
4646         netdev->features |= NETIF_F_TSO6;
4647         netdev->features |= NETIF_F_GRO;
4648
4649         netdev->vlan_features |= NETIF_F_TSO;
4650         netdev->vlan_features |= NETIF_F_TSO6;
4651         netdev->vlan_features |= NETIF_F_IP_CSUM;
4652         netdev->vlan_features |= NETIF_F_SG;
4653
4654         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4655                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4656
4657 #ifdef CONFIG_IXGBE_DCB
4658         netdev->dcbnl_ops = &dcbnl_ops;
4659 #endif
4660
4661         if (pci_using_dac)
4662                 netdev->features |= NETIF_F_HIGHDMA;
4663
4664         /* make sure the EEPROM is good */
4665         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
4666                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4667                 err = -EIO;
4668                 goto err_eeprom;
4669         }
4670
4671         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4672         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4673
4674         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4675                 dev_err(&pdev->dev, "invalid MAC address\n");
4676                 err = -EIO;
4677                 goto err_eeprom;
4678         }
4679
4680         init_timer(&adapter->watchdog_timer);
4681         adapter->watchdog_timer.function = &ixgbe_watchdog;
4682         adapter->watchdog_timer.data = (unsigned long)adapter;
4683
4684         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
4685         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
4686
4687         err = ixgbe_init_interrupt_scheme(adapter);
4688         if (err)
4689                 goto err_sw_init;
4690
4691         switch (pdev->device) {
4692         case IXGBE_DEV_ID_82599_KX4:
4693 #define IXGBE_PCIE_PMCSR 0x44
4694                 adapter->wol = IXGBE_WUFC_MAG;
4695                 pci_read_config_word(pdev, IXGBE_PCIE_PMCSR, &pm_value);
4696                 pci_write_config_word(pdev, IXGBE_PCIE_PMCSR,
4697                                       (pm_value | (1 << 8)));
4698                 break;
4699         default:
4700                 adapter->wol = 0;
4701                 break;
4702         }
4703         device_init_wakeup(&adapter->pdev->dev, true);
4704         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
4705
4706         /* print bus type/speed/width info */
4707         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
4708                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
4709                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
4710                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
4711                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
4712                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
4713                  "Unknown"),
4714                 netdev->dev_addr);
4715         ixgbe_read_pba_num_generic(hw, &part_num);
4716         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
4717                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
4718                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
4719                          (part_num >> 8), (part_num & 0xff));
4720         else
4721                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
4722                          hw->mac.type, hw->phy.type,
4723                          (part_num >> 8), (part_num & 0xff));
4724
4725         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
4726                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
4727                          "this card is not sufficient for optimal "
4728                          "performance.\n");
4729                 dev_warn(&pdev->dev, "For optimal performance a x8 "
4730                          "PCI-Express slot is required.\n");
4731         }
4732
4733         /* save off EEPROM version number */
4734         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
4735
4736         /* reset the hardware with the new settings */
4737         hw->mac.ops.start_hw(hw);
4738
4739         netif_carrier_off(netdev);
4740
4741         strcpy(netdev->name, "eth%d");
4742         err = register_netdev(netdev);
4743         if (err)
4744                 goto err_register;
4745
4746 #ifdef CONFIG_IXGBE_DCA
4747         if (dca_add_requester(&pdev->dev) == 0) {
4748                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
4749                 /* always use CB2 mode, difference is masked
4750                  * in the CB driver */
4751                 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
4752                 ixgbe_setup_dca(adapter);
4753         }
4754 #endif
4755
4756         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
4757         cards_found++;
4758         return 0;
4759
4760 err_register:
4761         ixgbe_release_hw_control(adapter);
4762 err_hw_init:
4763 err_sw_init:
4764         ixgbe_reset_interrupt_capability(adapter);
4765 err_eeprom:
4766         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4767         del_timer_sync(&adapter->sfp_timer);
4768         cancel_work_sync(&adapter->sfp_task);
4769         cancel_work_sync(&adapter->multispeed_fiber_task);
4770         cancel_work_sync(&adapter->sfp_config_module_task);
4771         iounmap(hw->hw_addr);
4772 err_ioremap:
4773         free_netdev(netdev);
4774 err_alloc_etherdev:
4775         pci_release_regions(pdev);
4776 err_pci_reg:
4777 err_dma:
4778         pci_disable_device(pdev);
4779         return err;
4780 }
4781
4782 /**
4783  * ixgbe_remove - Device Removal Routine
4784  * @pdev: PCI device information struct
4785  *
4786  * ixgbe_remove is called by the PCI subsystem to alert the driver
4787  * that it should release a PCI device.  The could be caused by a
4788  * Hot-Plug event, or because the driver is going to be removed from
4789  * memory.
4790  **/
4791 static void __devexit ixgbe_remove(struct pci_dev *pdev)
4792 {
4793         struct net_device *netdev = pci_get_drvdata(pdev);
4794         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4795         int err;
4796
4797         set_bit(__IXGBE_DOWN, &adapter->state);
4798         /* clear the module not found bit to make sure the worker won't
4799          * reschedule
4800          */
4801         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4802         del_timer_sync(&adapter->watchdog_timer);
4803
4804         del_timer_sync(&adapter->sfp_timer);
4805         cancel_work_sync(&adapter->watchdog_task);
4806         cancel_work_sync(&adapter->sfp_task);
4807         cancel_work_sync(&adapter->multispeed_fiber_task);
4808         cancel_work_sync(&adapter->sfp_config_module_task);
4809         flush_scheduled_work();
4810
4811 #ifdef CONFIG_IXGBE_DCA
4812         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4813                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
4814                 dca_remove_requester(&pdev->dev);
4815                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
4816         }
4817
4818 #endif
4819         if (netdev->reg_state == NETREG_REGISTERED)
4820                 unregister_netdev(netdev);
4821
4822         ixgbe_reset_interrupt_capability(adapter);
4823
4824         ixgbe_release_hw_control(adapter);
4825
4826         iounmap(adapter->hw.hw_addr);
4827         pci_release_regions(pdev);
4828
4829         DPRINTK(PROBE, INFO, "complete\n");
4830         kfree(adapter->tx_ring);
4831         kfree(adapter->rx_ring);
4832
4833         free_netdev(netdev);
4834
4835         err = pci_disable_pcie_error_reporting(pdev);
4836         if (err)
4837                 dev_err(&pdev->dev,
4838                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
4839
4840         pci_disable_device(pdev);
4841 }
4842
4843 /**
4844  * ixgbe_io_error_detected - called when PCI error is detected
4845  * @pdev: Pointer to PCI device
4846  * @state: The current pci connection state
4847  *
4848  * This function is called after a PCI bus error affecting
4849  * this device has been detected.
4850  */
4851 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
4852                                                 pci_channel_state_t state)
4853 {
4854         struct net_device *netdev = pci_get_drvdata(pdev);
4855         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4856
4857         netif_device_detach(netdev);
4858
4859         if (netif_running(netdev))
4860                 ixgbe_down(adapter);
4861         pci_disable_device(pdev);
4862
4863         /* Request a slot reset. */
4864         return PCI_ERS_RESULT_NEED_RESET;
4865 }
4866
4867 /**
4868  * ixgbe_io_slot_reset - called after the pci bus has been reset.
4869  * @pdev: Pointer to PCI device
4870  *
4871  * Restart the card from scratch, as if from a cold-boot.
4872  */
4873 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4874 {
4875         struct net_device *netdev = pci_get_drvdata(pdev);
4876         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4877         pci_ers_result_t result;
4878         int err;
4879
4880         if (pci_enable_device(pdev)) {
4881                 DPRINTK(PROBE, ERR,
4882                         "Cannot re-enable PCI device after reset.\n");
4883                 result = PCI_ERS_RESULT_DISCONNECT;
4884         } else {
4885                 pci_set_master(pdev);
4886                 pci_restore_state(pdev);
4887
4888                 pci_enable_wake(pdev, PCI_D3hot, 0);
4889                 pci_enable_wake(pdev, PCI_D3cold, 0);
4890
4891                 ixgbe_reset(adapter);
4892                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4893                 result = PCI_ERS_RESULT_RECOVERED;
4894         }
4895
4896         err = pci_cleanup_aer_uncorrect_error_status(pdev);
4897         if (err) {
4898                 dev_err(&pdev->dev,
4899                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
4900                 /* non-fatal, continue */
4901         }
4902
4903         return result;
4904 }
4905
4906 /**
4907  * ixgbe_io_resume - called when traffic can start flowing again.
4908  * @pdev: Pointer to PCI device
4909  *
4910  * This callback is called when the error recovery driver tells us that
4911  * its OK to resume normal operation.
4912  */
4913 static void ixgbe_io_resume(struct pci_dev *pdev)
4914 {
4915         struct net_device *netdev = pci_get_drvdata(pdev);
4916         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4917
4918         if (netif_running(netdev)) {
4919                 if (ixgbe_up(adapter)) {
4920                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4921                         return;
4922                 }
4923         }
4924
4925         netif_device_attach(netdev);
4926 }
4927
4928 static struct pci_error_handlers ixgbe_err_handler = {
4929         .error_detected = ixgbe_io_error_detected,
4930         .slot_reset = ixgbe_io_slot_reset,
4931         .resume = ixgbe_io_resume,
4932 };
4933
4934 static struct pci_driver ixgbe_driver = {
4935         .name     = ixgbe_driver_name,
4936         .id_table = ixgbe_pci_tbl,
4937         .probe    = ixgbe_probe,
4938         .remove   = __devexit_p(ixgbe_remove),
4939 #ifdef CONFIG_PM
4940         .suspend  = ixgbe_suspend,
4941         .resume   = ixgbe_resume,
4942 #endif
4943         .shutdown = ixgbe_shutdown,
4944         .err_handler = &ixgbe_err_handler
4945 };
4946
4947 /**
4948  * ixgbe_init_module - Driver Registration Routine
4949  *
4950  * ixgbe_init_module is the first routine called when the driver is
4951  * loaded. All it does is register with the PCI subsystem.
4952  **/
4953 static int __init ixgbe_init_module(void)
4954 {
4955         int ret;
4956         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4957                ixgbe_driver_string, ixgbe_driver_version);
4958
4959         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4960
4961 #ifdef CONFIG_IXGBE_DCA
4962         dca_register_notify(&dca_notifier);
4963 #endif
4964
4965         ret = pci_register_driver(&ixgbe_driver);
4966         return ret;
4967 }
4968
4969 module_init(ixgbe_init_module);
4970
4971 /**
4972  * ixgbe_exit_module - Driver Exit Cleanup Routine
4973  *
4974  * ixgbe_exit_module is called just before the driver is removed
4975  * from memory.
4976  **/
4977 static void __exit ixgbe_exit_module(void)
4978 {
4979 #ifdef CONFIG_IXGBE_DCA
4980         dca_unregister_notify(&dca_notifier);
4981 #endif
4982         pci_unregister_driver(&ixgbe_driver);
4983 }
4984
4985 #ifdef CONFIG_IXGBE_DCA
4986 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
4987                             void *p)
4988 {
4989         int ret_val;
4990
4991         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
4992                                          __ixgbe_notify_dca);
4993
4994         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4995 }
4996
4997 #endif /* CONFIG_IXGBE_DCA */
4998 #ifdef DEBUG
4999 /**
5000  * ixgbe_get_hw_dev_name - return device name string
5001  * used by hardware layer to print debugging information
5002  **/
5003 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5004 {
5005         struct ixgbe_adapter *adapter = hw->back;
5006         return adapter->netdev->name;
5007 }
5008
5009 #endif
5010 module_exit(ixgbe_exit_module);
5011
5012 /* ixgbe_main.c */