e25343588fc77466380039a46728ba4bfd8ecd34
[linux-3.10.git] / drivers / net / igb / igb_main.c
1 /*******************************************************************************
2
3   Intel(R) Gigabit Ethernet Linux driver
4   Copyright(c) 2007-2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pagemap.h>
33 #include <linux/netdevice.h>
34 #include <linux/ipv6.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/pci.h>
42 #include <linux/pci-aspm.h>
43 #include <linux/delay.h>
44 #include <linux/interrupt.h>
45 #include <linux/if_ether.h>
46 #include <linux/aer.h>
47 #ifdef CONFIG_IGB_DCA
48 #include <linux/dca.h>
49 #endif
50 #include "igb.h"
51
52 #define DRV_VERSION "1.3.16-k2"
53 char igb_driver_name[] = "igb";
54 char igb_driver_version[] = DRV_VERSION;
55 static const char igb_driver_string[] =
56                                 "Intel(R) Gigabit Ethernet Network Driver";
57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
58
59 static const struct e1000_info *igb_info_tbl[] = {
60         [board_82575] = &e1000_82575_info,
61 };
62
63 static struct pci_device_id igb_pci_tbl[] = {
64         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
65         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
66         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
67         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
68         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
69         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
70         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
71         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
72         /* required last entry */
73         {0, }
74 };
75
76 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
77
78 void igb_reset(struct igb_adapter *);
79 static int igb_setup_all_tx_resources(struct igb_adapter *);
80 static int igb_setup_all_rx_resources(struct igb_adapter *);
81 static void igb_free_all_tx_resources(struct igb_adapter *);
82 static void igb_free_all_rx_resources(struct igb_adapter *);
83 void igb_update_stats(struct igb_adapter *);
84 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
85 static void __devexit igb_remove(struct pci_dev *pdev);
86 static int igb_sw_init(struct igb_adapter *);
87 static int igb_open(struct net_device *);
88 static int igb_close(struct net_device *);
89 static void igb_configure_tx(struct igb_adapter *);
90 static void igb_configure_rx(struct igb_adapter *);
91 static void igb_setup_rctl(struct igb_adapter *);
92 static void igb_clean_all_tx_rings(struct igb_adapter *);
93 static void igb_clean_all_rx_rings(struct igb_adapter *);
94 static void igb_clean_tx_ring(struct igb_ring *);
95 static void igb_clean_rx_ring(struct igb_ring *);
96 static void igb_set_multi(struct net_device *);
97 static void igb_update_phy_info(unsigned long);
98 static void igb_watchdog(unsigned long);
99 static void igb_watchdog_task(struct work_struct *);
100 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
101                                   struct igb_ring *);
102 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
103 static struct net_device_stats *igb_get_stats(struct net_device *);
104 static int igb_change_mtu(struct net_device *, int);
105 static int igb_set_mac(struct net_device *, void *);
106 static irqreturn_t igb_intr(int irq, void *);
107 static irqreturn_t igb_intr_msi(int irq, void *);
108 static irqreturn_t igb_msix_other(int irq, void *);
109 static irqreturn_t igb_msix_rx(int irq, void *);
110 static irqreturn_t igb_msix_tx(int irq, void *);
111 #ifdef CONFIG_IGB_DCA
112 static void igb_update_rx_dca(struct igb_ring *);
113 static void igb_update_tx_dca(struct igb_ring *);
114 static void igb_setup_dca(struct igb_adapter *);
115 #endif /* CONFIG_IGB_DCA */
116 static bool igb_clean_tx_irq(struct igb_ring *);
117 static int igb_poll(struct napi_struct *, int);
118 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
119 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
120 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
121 static void igb_tx_timeout(struct net_device *);
122 static void igb_reset_task(struct work_struct *);
123 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
124 static void igb_vlan_rx_add_vid(struct net_device *, u16);
125 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
126 static void igb_restore_vlan(struct igb_adapter *);
127 static void igb_ping_all_vfs(struct igb_adapter *);
128 static void igb_msg_task(struct igb_adapter *);
129 static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
130 static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
131 static void igb_set_mc_list_pools(struct igb_adapter *, int, u16);
132 static void igb_vmm_control(struct igb_adapter *);
133 static inline void igb_set_vmolr(struct e1000_hw *, int);
134 static inline int igb_set_vf_rlpml(struct igb_adapter *, int, int);
135 static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
136 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
137
138 #ifdef CONFIG_PM
139 static int igb_suspend(struct pci_dev *, pm_message_t);
140 static int igb_resume(struct pci_dev *);
141 #endif
142 static void igb_shutdown(struct pci_dev *);
143 #ifdef CONFIG_IGB_DCA
144 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
145 static struct notifier_block dca_notifier = {
146         .notifier_call  = igb_notify_dca,
147         .next           = NULL,
148         .priority       = 0
149 };
150 #endif
151 #ifdef CONFIG_NET_POLL_CONTROLLER
152 /* for netdump / net console */
153 static void igb_netpoll(struct net_device *);
154 #endif
155 #ifdef CONFIG_PCI_IOV
156 static unsigned int max_vfs = 0;
157 module_param(max_vfs, uint, 0);
158 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
159                  "per physical function");
160 #endif /* CONFIG_PCI_IOV */
161
162 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
163                      pci_channel_state_t);
164 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
165 static void igb_io_resume(struct pci_dev *);
166
167 static struct pci_error_handlers igb_err_handler = {
168         .error_detected = igb_io_error_detected,
169         .slot_reset = igb_io_slot_reset,
170         .resume = igb_io_resume,
171 };
172
173
174 static struct pci_driver igb_driver = {
175         .name     = igb_driver_name,
176         .id_table = igb_pci_tbl,
177         .probe    = igb_probe,
178         .remove   = __devexit_p(igb_remove),
179 #ifdef CONFIG_PM
180         /* Power Managment Hooks */
181         .suspend  = igb_suspend,
182         .resume   = igb_resume,
183 #endif
184         .shutdown = igb_shutdown,
185         .err_handler = &igb_err_handler
186 };
187
188 static int global_quad_port_a; /* global quad port a indication */
189
190 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
191 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
192 MODULE_LICENSE("GPL");
193 MODULE_VERSION(DRV_VERSION);
194
195 /**
196  * Scale the NIC clock cycle by a large factor so that
197  * relatively small clock corrections can be added or
198  * substracted at each clock tick. The drawbacks of a
199  * large factor are a) that the clock register overflows
200  * more quickly (not such a big deal) and b) that the
201  * increment per tick has to fit into 24 bits.
202  *
203  * Note that
204  *   TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
205  *             IGB_TSYNC_SCALE
206  *   TIMINCA += TIMINCA * adjustment [ppm] / 1e9
207  *
208  * The base scale factor is intentionally a power of two
209  * so that the division in %struct timecounter can be done with
210  * a shift.
211  */
212 #define IGB_TSYNC_SHIFT (19)
213 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
214
215 /**
216  * The duration of one clock cycle of the NIC.
217  *
218  * @todo This hard-coded value is part of the specification and might change
219  * in future hardware revisions. Add revision check.
220  */
221 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
222
223 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
224 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
225 #endif
226
227 /**
228  * igb_read_clock - read raw cycle counter (to be used by time counter)
229  */
230 static cycle_t igb_read_clock(const struct cyclecounter *tc)
231 {
232         struct igb_adapter *adapter =
233                 container_of(tc, struct igb_adapter, cycles);
234         struct e1000_hw *hw = &adapter->hw;
235         u64 stamp;
236
237         stamp =  rd32(E1000_SYSTIML);
238         stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
239
240         return stamp;
241 }
242
243 #ifdef DEBUG
244 /**
245  * igb_get_hw_dev_name - return device name string
246  * used by hardware layer to print debugging information
247  **/
248 char *igb_get_hw_dev_name(struct e1000_hw *hw)
249 {
250         struct igb_adapter *adapter = hw->back;
251         return adapter->netdev->name;
252 }
253
254 /**
255  * igb_get_time_str - format current NIC and system time as string
256  */
257 static char *igb_get_time_str(struct igb_adapter *adapter,
258                               char buffer[160])
259 {
260         cycle_t hw = adapter->cycles.read(&adapter->cycles);
261         struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
262         struct timespec sys;
263         struct timespec delta;
264         getnstimeofday(&sys);
265
266         delta = timespec_sub(nic, sys);
267
268         sprintf(buffer,
269                 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
270                 hw,
271                 (long)nic.tv_sec, nic.tv_nsec,
272                 (long)sys.tv_sec, sys.tv_nsec,
273                 (long)delta.tv_sec, delta.tv_nsec);
274
275         return buffer;
276 }
277 #endif
278
279 /**
280  * igb_desc_unused - calculate if we have unused descriptors
281  **/
282 static int igb_desc_unused(struct igb_ring *ring)
283 {
284         if (ring->next_to_clean > ring->next_to_use)
285                 return ring->next_to_clean - ring->next_to_use - 1;
286
287         return ring->count + ring->next_to_clean - ring->next_to_use - 1;
288 }
289
290 /**
291  * igb_init_module - Driver Registration Routine
292  *
293  * igb_init_module is the first routine called when the driver is
294  * loaded. All it does is register with the PCI subsystem.
295  **/
296 static int __init igb_init_module(void)
297 {
298         int ret;
299         printk(KERN_INFO "%s - version %s\n",
300                igb_driver_string, igb_driver_version);
301
302         printk(KERN_INFO "%s\n", igb_copyright);
303
304         global_quad_port_a = 0;
305
306 #ifdef CONFIG_IGB_DCA
307         dca_register_notify(&dca_notifier);
308 #endif
309
310         ret = pci_register_driver(&igb_driver);
311         return ret;
312 }
313
314 module_init(igb_init_module);
315
316 /**
317  * igb_exit_module - Driver Exit Cleanup Routine
318  *
319  * igb_exit_module is called just before the driver is removed
320  * from memory.
321  **/
322 static void __exit igb_exit_module(void)
323 {
324 #ifdef CONFIG_IGB_DCA
325         dca_unregister_notify(&dca_notifier);
326 #endif
327         pci_unregister_driver(&igb_driver);
328 }
329
330 module_exit(igb_exit_module);
331
332 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
333 /**
334  * igb_cache_ring_register - Descriptor ring to register mapping
335  * @adapter: board private structure to initialize
336  *
337  * Once we know the feature-set enabled for the device, we'll cache
338  * the register offset the descriptor ring is assigned to.
339  **/
340 static void igb_cache_ring_register(struct igb_adapter *adapter)
341 {
342         int i;
343         unsigned int rbase_offset = adapter->vfs_allocated_count;
344
345         switch (adapter->hw.mac.type) {
346         case e1000_82576:
347                 /* The queues are allocated for virtualization such that VF 0
348                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
349                  * In order to avoid collision we start at the first free queue
350                  * and continue consuming queues in the same sequence
351                  */
352                 for (i = 0; i < adapter->num_rx_queues; i++)
353                         adapter->rx_ring[i].reg_idx = rbase_offset +
354                                                       Q_IDX_82576(i);
355                 for (i = 0; i < adapter->num_tx_queues; i++)
356                         adapter->tx_ring[i].reg_idx = rbase_offset +
357                                                       Q_IDX_82576(i);
358                 break;
359         case e1000_82575:
360         default:
361                 for (i = 0; i < adapter->num_rx_queues; i++)
362                         adapter->rx_ring[i].reg_idx = i;
363                 for (i = 0; i < adapter->num_tx_queues; i++)
364                         adapter->tx_ring[i].reg_idx = i;
365                 break;
366         }
367 }
368
369 /**
370  * igb_alloc_queues - Allocate memory for all rings
371  * @adapter: board private structure to initialize
372  *
373  * We allocate one ring per queue at run-time since we don't know the
374  * number of queues at compile-time.
375  **/
376 static int igb_alloc_queues(struct igb_adapter *adapter)
377 {
378         int i;
379
380         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
381                                    sizeof(struct igb_ring), GFP_KERNEL);
382         if (!adapter->tx_ring)
383                 return -ENOMEM;
384
385         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
386                                    sizeof(struct igb_ring), GFP_KERNEL);
387         if (!adapter->rx_ring) {
388                 kfree(adapter->tx_ring);
389                 return -ENOMEM;
390         }
391
392         adapter->rx_ring->buddy = adapter->tx_ring;
393
394         for (i = 0; i < adapter->num_tx_queues; i++) {
395                 struct igb_ring *ring = &(adapter->tx_ring[i]);
396                 ring->count = adapter->tx_ring_count;
397                 ring->adapter = adapter;
398                 ring->queue_index = i;
399         }
400         for (i = 0; i < adapter->num_rx_queues; i++) {
401                 struct igb_ring *ring = &(adapter->rx_ring[i]);
402                 ring->count = adapter->rx_ring_count;
403                 ring->adapter = adapter;
404                 ring->queue_index = i;
405                 ring->itr_register = E1000_ITR;
406
407                 /* set a default napi handler for each rx_ring */
408                 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
409         }
410
411         igb_cache_ring_register(adapter);
412         return 0;
413 }
414
415 static void igb_free_queues(struct igb_adapter *adapter)
416 {
417         int i;
418
419         for (i = 0; i < adapter->num_rx_queues; i++)
420                 netif_napi_del(&adapter->rx_ring[i].napi);
421
422         adapter->num_rx_queues = 0;
423         adapter->num_tx_queues = 0;
424
425         kfree(adapter->tx_ring);
426         kfree(adapter->rx_ring);
427 }
428
429 #define IGB_N0_QUEUE -1
430 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
431                               int tx_queue, int msix_vector)
432 {
433         u32 msixbm = 0;
434         struct e1000_hw *hw = &adapter->hw;
435         u32 ivar, index;
436
437         switch (hw->mac.type) {
438         case e1000_82575:
439                 /* The 82575 assigns vectors using a bitmask, which matches the
440                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
441                    or more queues to a vector, we write the appropriate bits
442                    into the MSIXBM register for that vector. */
443                 if (rx_queue > IGB_N0_QUEUE) {
444                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
445                         adapter->rx_ring[rx_queue].eims_value = msixbm;
446                 }
447                 if (tx_queue > IGB_N0_QUEUE) {
448                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
449                         adapter->tx_ring[tx_queue].eims_value =
450                                   E1000_EICR_TX_QUEUE0 << tx_queue;
451                 }
452                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
453                 break;
454         case e1000_82576:
455                 /* 82576 uses a table-based method for assigning vectors.
456                    Each queue has a single entry in the table to which we write
457                    a vector number along with a "valid" bit.  Sadly, the layout
458                    of the table is somewhat counterintuitive. */
459                 if (rx_queue > IGB_N0_QUEUE) {
460                         index = (rx_queue >> 1) + adapter->vfs_allocated_count;
461                         ivar = array_rd32(E1000_IVAR0, index);
462                         if (rx_queue & 0x1) {
463                                 /* vector goes into third byte of register */
464                                 ivar = ivar & 0xFF00FFFF;
465                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
466                         } else {
467                                 /* vector goes into low byte of register */
468                                 ivar = ivar & 0xFFFFFF00;
469                                 ivar |= msix_vector | E1000_IVAR_VALID;
470                         }
471                         adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
472                         array_wr32(E1000_IVAR0, index, ivar);
473                 }
474                 if (tx_queue > IGB_N0_QUEUE) {
475                         index = (tx_queue >> 1) + adapter->vfs_allocated_count;
476                         ivar = array_rd32(E1000_IVAR0, index);
477                         if (tx_queue & 0x1) {
478                                 /* vector goes into high byte of register */
479                                 ivar = ivar & 0x00FFFFFF;
480                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
481                         } else {
482                                 /* vector goes into second byte of register */
483                                 ivar = ivar & 0xFFFF00FF;
484                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
485                         }
486                         adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
487                         array_wr32(E1000_IVAR0, index, ivar);
488                 }
489                 break;
490         default:
491                 BUG();
492                 break;
493         }
494 }
495
496 /**
497  * igb_configure_msix - Configure MSI-X hardware
498  *
499  * igb_configure_msix sets up the hardware to properly
500  * generate MSI-X interrupts.
501  **/
502 static void igb_configure_msix(struct igb_adapter *adapter)
503 {
504         u32 tmp;
505         int i, vector = 0;
506         struct e1000_hw *hw = &adapter->hw;
507
508         adapter->eims_enable_mask = 0;
509         if (hw->mac.type == e1000_82576)
510                 /* Turn on MSI-X capability first, or our settings
511                  * won't stick.  And it will take days to debug. */
512                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
513                                    E1000_GPIE_PBA | E1000_GPIE_EIAME |
514                                    E1000_GPIE_NSICR);
515
516         for (i = 0; i < adapter->num_tx_queues; i++) {
517                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
518                 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
519                 adapter->eims_enable_mask |= tx_ring->eims_value;
520                 if (tx_ring->itr_val)
521                         writel(tx_ring->itr_val,
522                                hw->hw_addr + tx_ring->itr_register);
523                 else
524                         writel(1, hw->hw_addr + tx_ring->itr_register);
525         }
526
527         for (i = 0; i < adapter->num_rx_queues; i++) {
528                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
529                 rx_ring->buddy = NULL;
530                 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
531                 adapter->eims_enable_mask |= rx_ring->eims_value;
532                 if (rx_ring->itr_val)
533                         writel(rx_ring->itr_val,
534                                hw->hw_addr + rx_ring->itr_register);
535                 else
536                         writel(1, hw->hw_addr + rx_ring->itr_register);
537         }
538
539
540         /* set vector for other causes, i.e. link changes */
541         switch (hw->mac.type) {
542         case e1000_82575:
543                 array_wr32(E1000_MSIXBM(0), vector++,
544                                       E1000_EIMS_OTHER);
545
546                 tmp = rd32(E1000_CTRL_EXT);
547                 /* enable MSI-X PBA support*/
548                 tmp |= E1000_CTRL_EXT_PBA_CLR;
549
550                 /* Auto-Mask interrupts upon ICR read. */
551                 tmp |= E1000_CTRL_EXT_EIAME;
552                 tmp |= E1000_CTRL_EXT_IRCA;
553
554                 wr32(E1000_CTRL_EXT, tmp);
555                 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
556                 adapter->eims_other = E1000_EIMS_OTHER;
557
558                 break;
559
560         case e1000_82576:
561                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
562                 wr32(E1000_IVAR_MISC, tmp);
563
564                 adapter->eims_enable_mask = (1 << (vector)) - 1;
565                 adapter->eims_other = 1 << (vector - 1);
566                 break;
567         default:
568                 /* do nothing, since nothing else supports MSI-X */
569                 break;
570         } /* switch (hw->mac.type) */
571         wrfl();
572 }
573
574 /**
575  * igb_request_msix - Initialize MSI-X interrupts
576  *
577  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
578  * kernel.
579  **/
580 static int igb_request_msix(struct igb_adapter *adapter)
581 {
582         struct net_device *netdev = adapter->netdev;
583         int i, err = 0, vector = 0;
584
585         vector = 0;
586
587         for (i = 0; i < adapter->num_tx_queues; i++) {
588                 struct igb_ring *ring = &(adapter->tx_ring[i]);
589                 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
590                 err = request_irq(adapter->msix_entries[vector].vector,
591                                   &igb_msix_tx, 0, ring->name,
592                                   &(adapter->tx_ring[i]));
593                 if (err)
594                         goto out;
595                 ring->itr_register = E1000_EITR(0) + (vector << 2);
596                 ring->itr_val = 976; /* ~4000 ints/sec */
597                 vector++;
598         }
599         for (i = 0; i < adapter->num_rx_queues; i++) {
600                 struct igb_ring *ring = &(adapter->rx_ring[i]);
601                 if (strlen(netdev->name) < (IFNAMSIZ - 5))
602                         sprintf(ring->name, "%s-rx-%d", netdev->name, i);
603                 else
604                         memcpy(ring->name, netdev->name, IFNAMSIZ);
605                 err = request_irq(adapter->msix_entries[vector].vector,
606                                   &igb_msix_rx, 0, ring->name,
607                                   &(adapter->rx_ring[i]));
608                 if (err)
609                         goto out;
610                 ring->itr_register = E1000_EITR(0) + (vector << 2);
611                 ring->itr_val = adapter->itr;
612                 vector++;
613         }
614
615         err = request_irq(adapter->msix_entries[vector].vector,
616                           &igb_msix_other, 0, netdev->name, netdev);
617         if (err)
618                 goto out;
619
620         igb_configure_msix(adapter);
621         return 0;
622 out:
623         return err;
624 }
625
626 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
627 {
628         if (adapter->msix_entries) {
629                 pci_disable_msix(adapter->pdev);
630                 kfree(adapter->msix_entries);
631                 adapter->msix_entries = NULL;
632         } else if (adapter->flags & IGB_FLAG_HAS_MSI)
633                 pci_disable_msi(adapter->pdev);
634         return;
635 }
636
637
638 /**
639  * igb_set_interrupt_capability - set MSI or MSI-X if supported
640  *
641  * Attempt to configure interrupts using the best available
642  * capabilities of the hardware and kernel.
643  **/
644 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
645 {
646         int err;
647         int numvecs, i;
648
649         /* Number of supported queues. */
650         /* Having more queues than CPUs doesn't make sense. */
651         adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
652         adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
653
654         numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
655         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
656                                         GFP_KERNEL);
657         if (!adapter->msix_entries)
658                 goto msi_only;
659
660         for (i = 0; i < numvecs; i++)
661                 adapter->msix_entries[i].entry = i;
662
663         err = pci_enable_msix(adapter->pdev,
664                               adapter->msix_entries,
665                               numvecs);
666         if (err == 0)
667                 goto out;
668
669         igb_reset_interrupt_capability(adapter);
670
671         /* If we can't do MSI-X, try MSI */
672 msi_only:
673 #ifdef CONFIG_PCI_IOV
674         /* disable SR-IOV for non MSI-X configurations */
675         if (adapter->vf_data) {
676                 struct e1000_hw *hw = &adapter->hw;
677                 /* disable iov and allow time for transactions to clear */
678                 pci_disable_sriov(adapter->pdev);
679                 msleep(500);
680
681                 kfree(adapter->vf_data);
682                 adapter->vf_data = NULL;
683                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
684                 msleep(100);
685                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
686         }
687 #endif
688         adapter->num_rx_queues = 1;
689         adapter->num_tx_queues = 1;
690         if (!pci_enable_msi(adapter->pdev))
691                 adapter->flags |= IGB_FLAG_HAS_MSI;
692 out:
693         /* Notify the stack of the (possibly) reduced Tx Queue count. */
694         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
695         return;
696 }
697
698 /**
699  * igb_request_irq - initialize interrupts
700  *
701  * Attempts to configure interrupts using the best available
702  * capabilities of the hardware and kernel.
703  **/
704 static int igb_request_irq(struct igb_adapter *adapter)
705 {
706         struct net_device *netdev = adapter->netdev;
707         struct e1000_hw *hw = &adapter->hw;
708         int err = 0;
709
710         if (adapter->msix_entries) {
711                 err = igb_request_msix(adapter);
712                 if (!err)
713                         goto request_done;
714                 /* fall back to MSI */
715                 igb_reset_interrupt_capability(adapter);
716                 if (!pci_enable_msi(adapter->pdev))
717                         adapter->flags |= IGB_FLAG_HAS_MSI;
718                 igb_free_all_tx_resources(adapter);
719                 igb_free_all_rx_resources(adapter);
720                 adapter->num_rx_queues = 1;
721                 igb_alloc_queues(adapter);
722         } else {
723                 switch (hw->mac.type) {
724                 case e1000_82575:
725                         wr32(E1000_MSIXBM(0),
726                              (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
727                         break;
728                 case e1000_82576:
729                         wr32(E1000_IVAR0, E1000_IVAR_VALID);
730                         break;
731                 default:
732                         break;
733                 }
734         }
735
736         if (adapter->flags & IGB_FLAG_HAS_MSI) {
737                 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
738                                   netdev->name, netdev);
739                 if (!err)
740                         goto request_done;
741                 /* fall back to legacy interrupts */
742                 igb_reset_interrupt_capability(adapter);
743                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
744         }
745
746         err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
747                           netdev->name, netdev);
748
749         if (err)
750                 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
751                         err);
752
753 request_done:
754         return err;
755 }
756
757 static void igb_free_irq(struct igb_adapter *adapter)
758 {
759         struct net_device *netdev = adapter->netdev;
760
761         if (adapter->msix_entries) {
762                 int vector = 0, i;
763
764                 for (i = 0; i < adapter->num_tx_queues; i++)
765                         free_irq(adapter->msix_entries[vector++].vector,
766                                 &(adapter->tx_ring[i]));
767                 for (i = 0; i < adapter->num_rx_queues; i++)
768                         free_irq(adapter->msix_entries[vector++].vector,
769                                 &(adapter->rx_ring[i]));
770
771                 free_irq(adapter->msix_entries[vector++].vector, netdev);
772                 return;
773         }
774
775         free_irq(adapter->pdev->irq, netdev);
776 }
777
778 /**
779  * igb_irq_disable - Mask off interrupt generation on the NIC
780  * @adapter: board private structure
781  **/
782 static void igb_irq_disable(struct igb_adapter *adapter)
783 {
784         struct e1000_hw *hw = &adapter->hw;
785
786         if (adapter->msix_entries) {
787                 wr32(E1000_EIAM, 0);
788                 wr32(E1000_EIMC, ~0);
789                 wr32(E1000_EIAC, 0);
790         }
791
792         wr32(E1000_IAM, 0);
793         wr32(E1000_IMC, ~0);
794         wrfl();
795         synchronize_irq(adapter->pdev->irq);
796 }
797
798 /**
799  * igb_irq_enable - Enable default interrupt generation settings
800  * @adapter: board private structure
801  **/
802 static void igb_irq_enable(struct igb_adapter *adapter)
803 {
804         struct e1000_hw *hw = &adapter->hw;
805
806         if (adapter->msix_entries) {
807                 wr32(E1000_EIAC, adapter->eims_enable_mask);
808                 wr32(E1000_EIAM, adapter->eims_enable_mask);
809                 wr32(E1000_EIMS, adapter->eims_enable_mask);
810                 if (adapter->vfs_allocated_count)
811                         wr32(E1000_MBVFIMR, 0xFF);
812                 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
813                                  E1000_IMS_DOUTSYNC));
814         } else {
815                 wr32(E1000_IMS, IMS_ENABLE_MASK);
816                 wr32(E1000_IAM, IMS_ENABLE_MASK);
817         }
818 }
819
820 static void igb_update_mng_vlan(struct igb_adapter *adapter)
821 {
822         struct net_device *netdev = adapter->netdev;
823         u16 vid = adapter->hw.mng_cookie.vlan_id;
824         u16 old_vid = adapter->mng_vlan_id;
825         if (adapter->vlgrp) {
826                 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
827                         if (adapter->hw.mng_cookie.status &
828                                 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
829                                 igb_vlan_rx_add_vid(netdev, vid);
830                                 adapter->mng_vlan_id = vid;
831                         } else
832                                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
833
834                         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
835                                         (vid != old_vid) &&
836                             !vlan_group_get_device(adapter->vlgrp, old_vid))
837                                 igb_vlan_rx_kill_vid(netdev, old_vid);
838                 } else
839                         adapter->mng_vlan_id = vid;
840         }
841 }
842
843 /**
844  * igb_release_hw_control - release control of the h/w to f/w
845  * @adapter: address of board private structure
846  *
847  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
848  * For ASF and Pass Through versions of f/w this means that the
849  * driver is no longer loaded.
850  *
851  **/
852 static void igb_release_hw_control(struct igb_adapter *adapter)
853 {
854         struct e1000_hw *hw = &adapter->hw;
855         u32 ctrl_ext;
856
857         /* Let firmware take over control of h/w */
858         ctrl_ext = rd32(E1000_CTRL_EXT);
859         wr32(E1000_CTRL_EXT,
860                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
861 }
862
863
864 /**
865  * igb_get_hw_control - get control of the h/w from f/w
866  * @adapter: address of board private structure
867  *
868  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
869  * For ASF and Pass Through versions of f/w this means that
870  * the driver is loaded.
871  *
872  **/
873 static void igb_get_hw_control(struct igb_adapter *adapter)
874 {
875         struct e1000_hw *hw = &adapter->hw;
876         u32 ctrl_ext;
877
878         /* Let firmware know the driver has taken over */
879         ctrl_ext = rd32(E1000_CTRL_EXT);
880         wr32(E1000_CTRL_EXT,
881                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
882 }
883
884 /**
885  * igb_configure - configure the hardware for RX and TX
886  * @adapter: private board structure
887  **/
888 static void igb_configure(struct igb_adapter *adapter)
889 {
890         struct net_device *netdev = adapter->netdev;
891         int i;
892
893         igb_get_hw_control(adapter);
894         igb_set_multi(netdev);
895
896         igb_restore_vlan(adapter);
897
898         igb_configure_tx(adapter);
899         igb_setup_rctl(adapter);
900         igb_configure_rx(adapter);
901
902         igb_rx_fifo_flush_82575(&adapter->hw);
903
904         /* call igb_desc_unused which always leaves
905          * at least 1 descriptor unused to make sure
906          * next_to_use != next_to_clean */
907         for (i = 0; i < adapter->num_rx_queues; i++) {
908                 struct igb_ring *ring = &adapter->rx_ring[i];
909                 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
910         }
911
912
913         adapter->tx_queue_len = netdev->tx_queue_len;
914 }
915
916
917 /**
918  * igb_up - Open the interface and prepare it to handle traffic
919  * @adapter: board private structure
920  **/
921
922 int igb_up(struct igb_adapter *adapter)
923 {
924         struct e1000_hw *hw = &adapter->hw;
925         int i;
926
927         /* hardware has been reset, we need to reload some things */
928         igb_configure(adapter);
929
930         clear_bit(__IGB_DOWN, &adapter->state);
931
932         for (i = 0; i < adapter->num_rx_queues; i++)
933                 napi_enable(&adapter->rx_ring[i].napi);
934         if (adapter->msix_entries)
935                 igb_configure_msix(adapter);
936
937         igb_vmm_control(adapter);
938         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
939         igb_set_vmolr(hw, adapter->vfs_allocated_count);
940
941         /* Clear any pending interrupts. */
942         rd32(E1000_ICR);
943         igb_irq_enable(adapter);
944
945         /* Fire a link change interrupt to start the watchdog. */
946         wr32(E1000_ICS, E1000_ICS_LSC);
947         return 0;
948 }
949
950 void igb_down(struct igb_adapter *adapter)
951 {
952         struct e1000_hw *hw = &adapter->hw;
953         struct net_device *netdev = adapter->netdev;
954         u32 tctl, rctl;
955         int i;
956
957         /* signal that we're down so the interrupt handler does not
958          * reschedule our watchdog timer */
959         set_bit(__IGB_DOWN, &adapter->state);
960
961         /* disable receives in the hardware */
962         rctl = rd32(E1000_RCTL);
963         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
964         /* flush and sleep below */
965
966         netif_tx_stop_all_queues(netdev);
967
968         /* disable transmits in the hardware */
969         tctl = rd32(E1000_TCTL);
970         tctl &= ~E1000_TCTL_EN;
971         wr32(E1000_TCTL, tctl);
972         /* flush both disables and wait for them to finish */
973         wrfl();
974         msleep(10);
975
976         for (i = 0; i < adapter->num_rx_queues; i++)
977                 napi_disable(&adapter->rx_ring[i].napi);
978
979         igb_irq_disable(adapter);
980
981         del_timer_sync(&adapter->watchdog_timer);
982         del_timer_sync(&adapter->phy_info_timer);
983
984         netdev->tx_queue_len = adapter->tx_queue_len;
985         netif_carrier_off(netdev);
986
987         /* record the stats before reset*/
988         igb_update_stats(adapter);
989
990         adapter->link_speed = 0;
991         adapter->link_duplex = 0;
992
993         if (!pci_channel_offline(adapter->pdev))
994                 igb_reset(adapter);
995         igb_clean_all_tx_rings(adapter);
996         igb_clean_all_rx_rings(adapter);
997 }
998
999 void igb_reinit_locked(struct igb_adapter *adapter)
1000 {
1001         WARN_ON(in_interrupt());
1002         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1003                 msleep(1);
1004         igb_down(adapter);
1005         igb_up(adapter);
1006         clear_bit(__IGB_RESETTING, &adapter->state);
1007 }
1008
1009 void igb_reset(struct igb_adapter *adapter)
1010 {
1011         struct e1000_hw *hw = &adapter->hw;
1012         struct e1000_mac_info *mac = &hw->mac;
1013         struct e1000_fc_info *fc = &hw->fc;
1014         u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1015         u16 hwm;
1016
1017         /* Repartition Pba for greater than 9k mtu
1018          * To take effect CTRL.RST is required.
1019          */
1020         switch (mac->type) {
1021         case e1000_82576:
1022                 pba = E1000_PBA_64K;
1023                 break;
1024         case e1000_82575:
1025         default:
1026                 pba = E1000_PBA_34K;
1027                 break;
1028         }
1029
1030         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1031             (mac->type < e1000_82576)) {
1032                 /* adjust PBA for jumbo frames */
1033                 wr32(E1000_PBA, pba);
1034
1035                 /* To maintain wire speed transmits, the Tx FIFO should be
1036                  * large enough to accommodate two full transmit packets,
1037                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1038                  * the Rx FIFO should be large enough to accommodate at least
1039                  * one full receive packet and is similarly rounded up and
1040                  * expressed in KB. */
1041                 pba = rd32(E1000_PBA);
1042                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1043                 tx_space = pba >> 16;
1044                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1045                 pba &= 0xffff;
1046                 /* the tx fifo also stores 16 bytes of information about the tx
1047                  * but don't include ethernet FCS because hardware appends it */
1048                 min_tx_space = (adapter->max_frame_size +
1049                                 sizeof(union e1000_adv_tx_desc) -
1050                                 ETH_FCS_LEN) * 2;
1051                 min_tx_space = ALIGN(min_tx_space, 1024);
1052                 min_tx_space >>= 10;
1053                 /* software strips receive CRC, so leave room for it */
1054                 min_rx_space = adapter->max_frame_size;
1055                 min_rx_space = ALIGN(min_rx_space, 1024);
1056                 min_rx_space >>= 10;
1057
1058                 /* If current Tx allocation is less than the min Tx FIFO size,
1059                  * and the min Tx FIFO size is less than the current Rx FIFO
1060                  * allocation, take space away from current Rx allocation */
1061                 if (tx_space < min_tx_space &&
1062                     ((min_tx_space - tx_space) < pba)) {
1063                         pba = pba - (min_tx_space - tx_space);
1064
1065                         /* if short on rx space, rx wins and must trump tx
1066                          * adjustment */
1067                         if (pba < min_rx_space)
1068                                 pba = min_rx_space;
1069                 }
1070                 wr32(E1000_PBA, pba);
1071         }
1072
1073         /* flow control settings */
1074         /* The high water mark must be low enough to fit one full frame
1075          * (or the size used for early receive) above it in the Rx FIFO.
1076          * Set it to the lower of:
1077          * - 90% of the Rx FIFO size, or
1078          * - the full Rx FIFO size minus one full frame */
1079         hwm = min(((pba << 10) * 9 / 10),
1080                         ((pba << 10) - 2 * adapter->max_frame_size));
1081
1082         if (mac->type < e1000_82576) {
1083                 fc->high_water = hwm & 0xFFF8;  /* 8-byte granularity */
1084                 fc->low_water = fc->high_water - 8;
1085         } else {
1086                 fc->high_water = hwm & 0xFFF0;  /* 16-byte granularity */
1087                 fc->low_water = fc->high_water - 16;
1088         }
1089         fc->pause_time = 0xFFFF;
1090         fc->send_xon = 1;
1091         fc->type = fc->original_type;
1092
1093         /* disable receive for all VFs and wait one second */
1094         if (adapter->vfs_allocated_count) {
1095                 int i;
1096                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1097                         adapter->vf_data[i].clear_to_send = false;
1098
1099                 /* ping all the active vfs to let them know we are going down */
1100                         igb_ping_all_vfs(adapter);
1101
1102                 /* disable transmits and receives */
1103                 wr32(E1000_VFRE, 0);
1104                 wr32(E1000_VFTE, 0);
1105         }
1106
1107         /* Allow time for pending master requests to run */
1108         adapter->hw.mac.ops.reset_hw(&adapter->hw);
1109         wr32(E1000_WUC, 0);
1110
1111         if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1112                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1113
1114         igb_update_mng_vlan(adapter);
1115
1116         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1117         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1118
1119         igb_reset_adaptive(&adapter->hw);
1120         igb_get_phy_info(&adapter->hw);
1121 }
1122
1123 static const struct net_device_ops igb_netdev_ops = {
1124         .ndo_open               = igb_open,
1125         .ndo_stop               = igb_close,
1126         .ndo_start_xmit         = igb_xmit_frame_adv,
1127         .ndo_get_stats          = igb_get_stats,
1128         .ndo_set_multicast_list = igb_set_multi,
1129         .ndo_set_mac_address    = igb_set_mac,
1130         .ndo_change_mtu         = igb_change_mtu,
1131         .ndo_do_ioctl           = igb_ioctl,
1132         .ndo_tx_timeout         = igb_tx_timeout,
1133         .ndo_validate_addr      = eth_validate_addr,
1134         .ndo_vlan_rx_register   = igb_vlan_rx_register,
1135         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1136         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1137 #ifdef CONFIG_NET_POLL_CONTROLLER
1138         .ndo_poll_controller    = igb_netpoll,
1139 #endif
1140 };
1141
1142 /**
1143  * igb_probe - Device Initialization Routine
1144  * @pdev: PCI device information struct
1145  * @ent: entry in igb_pci_tbl
1146  *
1147  * Returns 0 on success, negative on failure
1148  *
1149  * igb_probe initializes an adapter identified by a pci_dev structure.
1150  * The OS initialization, configuring of the adapter private structure,
1151  * and a hardware reset occur.
1152  **/
1153 static int __devinit igb_probe(struct pci_dev *pdev,
1154                                const struct pci_device_id *ent)
1155 {
1156         struct net_device *netdev;
1157         struct igb_adapter *adapter;
1158         struct e1000_hw *hw;
1159         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1160         unsigned long mmio_start, mmio_len;
1161         int err, pci_using_dac;
1162         u16 eeprom_data = 0;
1163         u16 eeprom_apme_mask = IGB_EEPROM_APME;
1164         u32 part_num;
1165
1166         err = pci_enable_device_mem(pdev);
1167         if (err)
1168                 return err;
1169
1170         pci_using_dac = 0;
1171         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1172         if (!err) {
1173                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1174                 if (!err)
1175                         pci_using_dac = 1;
1176         } else {
1177                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1178                 if (err) {
1179                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1180                         if (err) {
1181                                 dev_err(&pdev->dev, "No usable DMA "
1182                                         "configuration, aborting\n");
1183                                 goto err_dma;
1184                         }
1185                 }
1186         }
1187
1188         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1189                                            IORESOURCE_MEM),
1190                                            igb_driver_name);
1191         if (err)
1192                 goto err_pci_reg;
1193
1194         err = pci_enable_pcie_error_reporting(pdev);
1195         if (err) {
1196                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1197                         "0x%x\n", err);
1198                 /* non-fatal, continue */
1199         }
1200
1201         pci_set_master(pdev);
1202         pci_save_state(pdev);
1203
1204         err = -ENOMEM;
1205         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1206                                    IGB_ABS_MAX_TX_QUEUES);
1207         if (!netdev)
1208                 goto err_alloc_etherdev;
1209
1210         SET_NETDEV_DEV(netdev, &pdev->dev);
1211
1212         pci_set_drvdata(pdev, netdev);
1213         adapter = netdev_priv(netdev);
1214         adapter->netdev = netdev;
1215         adapter->pdev = pdev;
1216         hw = &adapter->hw;
1217         hw->back = adapter;
1218         adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1219
1220         mmio_start = pci_resource_start(pdev, 0);
1221         mmio_len = pci_resource_len(pdev, 0);
1222
1223         err = -EIO;
1224         hw->hw_addr = ioremap(mmio_start, mmio_len);
1225         if (!hw->hw_addr)
1226                 goto err_ioremap;
1227
1228         netdev->netdev_ops = &igb_netdev_ops;
1229         igb_set_ethtool_ops(netdev);
1230         netdev->watchdog_timeo = 5 * HZ;
1231
1232         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1233
1234         netdev->mem_start = mmio_start;
1235         netdev->mem_end = mmio_start + mmio_len;
1236
1237         /* PCI config space info */
1238         hw->vendor_id = pdev->vendor;
1239         hw->device_id = pdev->device;
1240         hw->revision_id = pdev->revision;
1241         hw->subsystem_vendor_id = pdev->subsystem_vendor;
1242         hw->subsystem_device_id = pdev->subsystem_device;
1243
1244         /* setup the private structure */
1245         hw->back = adapter;
1246         /* Copy the default MAC, PHY and NVM function pointers */
1247         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1248         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1249         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1250         /* Initialize skew-specific constants */
1251         err = ei->get_invariants(hw);
1252         if (err)
1253                 goto err_sw_init;
1254
1255 #ifdef CONFIG_PCI_IOV
1256         /* since iov functionality isn't critical to base device function we
1257          * can accept failure.  If it fails we don't allow iov to be enabled */
1258         if (hw->mac.type == e1000_82576) {
1259                 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1260                 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1261                 int i;
1262                 unsigned char mac_addr[ETH_ALEN];
1263
1264                 if (num_vfs) {
1265                         adapter->vf_data = kcalloc(num_vfs,
1266                                                 sizeof(struct vf_data_storage),
1267                                                 GFP_KERNEL);
1268                         if (!adapter->vf_data) {
1269                                 dev_err(&pdev->dev,
1270                                         "Could not allocate VF private data - "
1271                                         "IOV enable failed\n");
1272                         } else {
1273                                 err = pci_enable_sriov(pdev, num_vfs);
1274                                 if (!err) {
1275                                         adapter->vfs_allocated_count = num_vfs;
1276                                         dev_info(&pdev->dev,
1277                                                  "%d vfs allocated\n",
1278                                                  num_vfs);
1279                                         for (i = 0;
1280                                              i < adapter->vfs_allocated_count;
1281                                              i++) {
1282                                                 random_ether_addr(mac_addr);
1283                                                 igb_set_vf_mac(adapter, i,
1284                                                                mac_addr);
1285                                         }
1286                                 } else {
1287                                         kfree(adapter->vf_data);
1288                                         adapter->vf_data = NULL;
1289                                 }
1290                         }
1291                 }
1292         }
1293
1294 #endif
1295         /* setup the private structure */
1296         err = igb_sw_init(adapter);
1297         if (err)
1298                 goto err_sw_init;
1299
1300         igb_get_bus_info_pcie(hw);
1301
1302         /* set flags */
1303         switch (hw->mac.type) {
1304         case e1000_82575:
1305                 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1306                 break;
1307         case e1000_82576:
1308         default:
1309                 break;
1310         }
1311
1312         hw->phy.autoneg_wait_to_complete = false;
1313         hw->mac.adaptive_ifs = true;
1314
1315         /* Copper options */
1316         if (hw->phy.media_type == e1000_media_type_copper) {
1317                 hw->phy.mdix = AUTO_ALL_MODES;
1318                 hw->phy.disable_polarity_correction = false;
1319                 hw->phy.ms_type = e1000_ms_hw_default;
1320         }
1321
1322         if (igb_check_reset_block(hw))
1323                 dev_info(&pdev->dev,
1324                         "PHY reset is blocked due to SOL/IDER session.\n");
1325
1326         netdev->features = NETIF_F_SG |
1327                            NETIF_F_IP_CSUM |
1328                            NETIF_F_HW_VLAN_TX |
1329                            NETIF_F_HW_VLAN_RX |
1330                            NETIF_F_HW_VLAN_FILTER;
1331
1332         netdev->features |= NETIF_F_IPV6_CSUM;
1333         netdev->features |= NETIF_F_TSO;
1334         netdev->features |= NETIF_F_TSO6;
1335
1336         netdev->features |= NETIF_F_GRO;
1337
1338         netdev->vlan_features |= NETIF_F_TSO;
1339         netdev->vlan_features |= NETIF_F_TSO6;
1340         netdev->vlan_features |= NETIF_F_IP_CSUM;
1341         netdev->vlan_features |= NETIF_F_SG;
1342
1343         if (pci_using_dac)
1344                 netdev->features |= NETIF_F_HIGHDMA;
1345
1346         adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1347
1348         /* before reading the NVM, reset the controller to put the device in a
1349          * known good starting state */
1350         hw->mac.ops.reset_hw(hw);
1351
1352         /* make sure the NVM is good */
1353         if (igb_validate_nvm_checksum(hw) < 0) {
1354                 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1355                 err = -EIO;
1356                 goto err_eeprom;
1357         }
1358
1359         /* copy the MAC address out of the NVM */
1360         if (hw->mac.ops.read_mac_addr(hw))
1361                 dev_err(&pdev->dev, "NVM Read Error\n");
1362
1363         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1364         memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1365
1366         if (!is_valid_ether_addr(netdev->perm_addr)) {
1367                 dev_err(&pdev->dev, "Invalid MAC Address\n");
1368                 err = -EIO;
1369                 goto err_eeprom;
1370         }
1371
1372         setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1373                     (unsigned long) adapter);
1374         setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1375                     (unsigned long) adapter);
1376
1377         INIT_WORK(&adapter->reset_task, igb_reset_task);
1378         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1379
1380         /* Initialize link properties that are user-changeable */
1381         adapter->fc_autoneg = true;
1382         hw->mac.autoneg = true;
1383         hw->phy.autoneg_advertised = 0x2f;
1384
1385         hw->fc.original_type = e1000_fc_default;
1386         hw->fc.type = e1000_fc_default;
1387
1388         adapter->itr_setting = IGB_DEFAULT_ITR;
1389         adapter->itr = IGB_START_ITR;
1390
1391         igb_validate_mdi_setting(hw);
1392
1393         adapter->rx_csum = 1;
1394
1395         /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1396          * enable the ACPI Magic Packet filter
1397          */
1398
1399         if (hw->bus.func == 0)
1400                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1401         else if (hw->bus.func == 1)
1402                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1403
1404         if (eeprom_data & eeprom_apme_mask)
1405                 adapter->eeprom_wol |= E1000_WUFC_MAG;
1406
1407         /* now that we have the eeprom settings, apply the special cases where
1408          * the eeprom may be wrong or the board simply won't support wake on
1409          * lan on a particular port */
1410         switch (pdev->device) {
1411         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1412                 adapter->eeprom_wol = 0;
1413                 break;
1414         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1415         case E1000_DEV_ID_82576_FIBER:
1416         case E1000_DEV_ID_82576_SERDES:
1417                 /* Wake events only supported on port A for dual fiber
1418                  * regardless of eeprom setting */
1419                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1420                         adapter->eeprom_wol = 0;
1421                 break;
1422         case E1000_DEV_ID_82576_QUAD_COPPER:
1423                 /* if quad port adapter, disable WoL on all but port A */
1424                 if (global_quad_port_a != 0)
1425                         adapter->eeprom_wol = 0;
1426                 else
1427                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1428                 /* Reset for multiple quad port adapters */
1429                 if (++global_quad_port_a == 4)
1430                         global_quad_port_a = 0;
1431                 break;
1432         }
1433
1434         /* initialize the wol settings based on the eeprom settings */
1435         adapter->wol = adapter->eeprom_wol;
1436         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1437
1438         /* reset the hardware with the new settings */
1439         igb_reset(adapter);
1440
1441         /* let the f/w know that the h/w is now under the control of the
1442          * driver. */
1443         igb_get_hw_control(adapter);
1444
1445         /* tell the stack to leave us alone until igb_open() is called */
1446         netif_carrier_off(netdev);
1447         netif_tx_stop_all_queues(netdev);
1448
1449         strcpy(netdev->name, "eth%d");
1450         err = register_netdev(netdev);
1451         if (err)
1452                 goto err_register;
1453
1454 #ifdef CONFIG_IGB_DCA
1455         if (dca_add_requester(&pdev->dev) == 0) {
1456                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1457                 dev_info(&pdev->dev, "DCA enabled\n");
1458                 /* Always use CB2 mode, difference is masked
1459                  * in the CB driver. */
1460                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
1461                 igb_setup_dca(adapter);
1462         }
1463 #endif
1464
1465         /*
1466          * Initialize hardware timer: we keep it running just in case
1467          * that some program needs it later on.
1468          */
1469         memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1470         adapter->cycles.read = igb_read_clock;
1471         adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1472         adapter->cycles.mult = 1;
1473         adapter->cycles.shift = IGB_TSYNC_SHIFT;
1474         wr32(E1000_TIMINCA,
1475              (1<<24) |
1476              IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1477 #if 0
1478         /*
1479          * Avoid rollover while we initialize by resetting the time counter.
1480          */
1481         wr32(E1000_SYSTIML, 0x00000000);
1482         wr32(E1000_SYSTIMH, 0x00000000);
1483 #else
1484         /*
1485          * Set registers so that rollover occurs soon to test this.
1486          */
1487         wr32(E1000_SYSTIML, 0x00000000);
1488         wr32(E1000_SYSTIMH, 0xFF800000);
1489 #endif
1490         wrfl();
1491         timecounter_init(&adapter->clock,
1492                          &adapter->cycles,
1493                          ktime_to_ns(ktime_get_real()));
1494
1495         /*
1496          * Synchronize our NIC clock against system wall clock. NIC
1497          * time stamp reading requires ~3us per sample, each sample
1498          * was pretty stable even under load => only require 10
1499          * samples for each offset comparison.
1500          */
1501         memset(&adapter->compare, 0, sizeof(adapter->compare));
1502         adapter->compare.source = &adapter->clock;
1503         adapter->compare.target = ktime_get_real;
1504         adapter->compare.num_samples = 10;
1505         timecompare_update(&adapter->compare, 0);
1506
1507 #ifdef DEBUG
1508         {
1509                 char buffer[160];
1510                 printk(KERN_DEBUG
1511                         "igb: %s: hw %p initialized timer\n",
1512                         igb_get_time_str(adapter, buffer),
1513                         &adapter->hw);
1514         }
1515 #endif
1516
1517         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1518         /* print bus type/speed/width info */
1519         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1520                  netdev->name,
1521                  ((hw->bus.speed == e1000_bus_speed_2500)
1522                   ? "2.5Gb/s" : "unknown"),
1523                  ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1524                   (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1525                   (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1526                    "unknown"),
1527                  netdev->dev_addr);
1528
1529         igb_read_part_num(hw, &part_num);
1530         dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1531                 (part_num >> 8), (part_num & 0xff));
1532
1533         dev_info(&pdev->dev,
1534                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1535                 adapter->msix_entries ? "MSI-X" :
1536                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1537                 adapter->num_rx_queues, adapter->num_tx_queues);
1538
1539         return 0;
1540
1541 err_register:
1542         igb_release_hw_control(adapter);
1543 err_eeprom:
1544         if (!igb_check_reset_block(hw))
1545                 igb_reset_phy(hw);
1546
1547         if (hw->flash_address)
1548                 iounmap(hw->flash_address);
1549
1550         igb_free_queues(adapter);
1551 err_sw_init:
1552         iounmap(hw->hw_addr);
1553 err_ioremap:
1554         free_netdev(netdev);
1555 err_alloc_etherdev:
1556         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1557                                      IORESOURCE_MEM));
1558 err_pci_reg:
1559 err_dma:
1560         pci_disable_device(pdev);
1561         return err;
1562 }
1563
1564 /**
1565  * igb_remove - Device Removal Routine
1566  * @pdev: PCI device information struct
1567  *
1568  * igb_remove is called by the PCI subsystem to alert the driver
1569  * that it should release a PCI device.  The could be caused by a
1570  * Hot-Plug event, or because the driver is going to be removed from
1571  * memory.
1572  **/
1573 static void __devexit igb_remove(struct pci_dev *pdev)
1574 {
1575         struct net_device *netdev = pci_get_drvdata(pdev);
1576         struct igb_adapter *adapter = netdev_priv(netdev);
1577         struct e1000_hw *hw = &adapter->hw;
1578         int err;
1579
1580         /* flush_scheduled work may reschedule our watchdog task, so
1581          * explicitly disable watchdog tasks from being rescheduled  */
1582         set_bit(__IGB_DOWN, &adapter->state);
1583         del_timer_sync(&adapter->watchdog_timer);
1584         del_timer_sync(&adapter->phy_info_timer);
1585
1586         flush_scheduled_work();
1587
1588 #ifdef CONFIG_IGB_DCA
1589         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1590                 dev_info(&pdev->dev, "DCA disabled\n");
1591                 dca_remove_requester(&pdev->dev);
1592                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1593                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
1594         }
1595 #endif
1596
1597         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
1598          * would have already happened in close and is redundant. */
1599         igb_release_hw_control(adapter);
1600
1601         unregister_netdev(netdev);
1602
1603         if (!igb_check_reset_block(&adapter->hw))
1604                 igb_reset_phy(&adapter->hw);
1605
1606         igb_reset_interrupt_capability(adapter);
1607
1608         igb_free_queues(adapter);
1609
1610 #ifdef CONFIG_PCI_IOV
1611         /* reclaim resources allocated to VFs */
1612         if (adapter->vf_data) {
1613                 /* disable iov and allow time for transactions to clear */
1614                 pci_disable_sriov(pdev);
1615                 msleep(500);
1616
1617                 kfree(adapter->vf_data);
1618                 adapter->vf_data = NULL;
1619                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1620                 msleep(100);
1621                 dev_info(&pdev->dev, "IOV Disabled\n");
1622         }
1623 #endif
1624         iounmap(hw->hw_addr);
1625         if (hw->flash_address)
1626                 iounmap(hw->flash_address);
1627         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1628                                      IORESOURCE_MEM));
1629
1630         free_netdev(netdev);
1631
1632         err = pci_disable_pcie_error_reporting(pdev);
1633         if (err)
1634                 dev_err(&pdev->dev,
1635                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1636
1637         pci_disable_device(pdev);
1638 }
1639
1640 /**
1641  * igb_sw_init - Initialize general software structures (struct igb_adapter)
1642  * @adapter: board private structure to initialize
1643  *
1644  * igb_sw_init initializes the Adapter private data structure.
1645  * Fields are initialized based on PCI device information and
1646  * OS network device settings (MTU size).
1647  **/
1648 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1649 {
1650         struct e1000_hw *hw = &adapter->hw;
1651         struct net_device *netdev = adapter->netdev;
1652         struct pci_dev *pdev = adapter->pdev;
1653
1654         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1655
1656         adapter->tx_ring_count = IGB_DEFAULT_TXD;
1657         adapter->rx_ring_count = IGB_DEFAULT_RXD;
1658         adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1659         adapter->rx_ps_hdr_size = 0; /* disable packet split */
1660         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1661         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1662
1663         /* This call may decrease the number of queues depending on
1664          * interrupt mode. */
1665         igb_set_interrupt_capability(adapter);
1666
1667         if (igb_alloc_queues(adapter)) {
1668                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1669                 return -ENOMEM;
1670         }
1671
1672         /* Explicitly disable IRQ since the NIC can be in any state. */
1673         igb_irq_disable(adapter);
1674
1675         set_bit(__IGB_DOWN, &adapter->state);
1676         return 0;
1677 }
1678
1679 /**
1680  * igb_open - Called when a network interface is made active
1681  * @netdev: network interface device structure
1682  *
1683  * Returns 0 on success, negative value on failure
1684  *
1685  * The open entry point is called when a network interface is made
1686  * active by the system (IFF_UP).  At this point all resources needed
1687  * for transmit and receive operations are allocated, the interrupt
1688  * handler is registered with the OS, the watchdog timer is started,
1689  * and the stack is notified that the interface is ready.
1690  **/
1691 static int igb_open(struct net_device *netdev)
1692 {
1693         struct igb_adapter *adapter = netdev_priv(netdev);
1694         struct e1000_hw *hw = &adapter->hw;
1695         int err;
1696         int i;
1697
1698         /* disallow open during test */
1699         if (test_bit(__IGB_TESTING, &adapter->state))
1700                 return -EBUSY;
1701
1702         /* allocate transmit descriptors */
1703         err = igb_setup_all_tx_resources(adapter);
1704         if (err)
1705                 goto err_setup_tx;
1706
1707         /* allocate receive descriptors */
1708         err = igb_setup_all_rx_resources(adapter);
1709         if (err)
1710                 goto err_setup_rx;
1711
1712         /* e1000_power_up_phy(adapter); */
1713
1714         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1715         if ((adapter->hw.mng_cookie.status &
1716              E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1717                 igb_update_mng_vlan(adapter);
1718
1719         /* before we allocate an interrupt, we must be ready to handle it.
1720          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1721          * as soon as we call pci_request_irq, so we have to setup our
1722          * clean_rx handler before we do so.  */
1723         igb_configure(adapter);
1724
1725         igb_vmm_control(adapter);
1726         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1727         igb_set_vmolr(hw, adapter->vfs_allocated_count);
1728
1729         err = igb_request_irq(adapter);
1730         if (err)
1731                 goto err_req_irq;
1732
1733         /* From here on the code is the same as igb_up() */
1734         clear_bit(__IGB_DOWN, &adapter->state);
1735
1736         for (i = 0; i < adapter->num_rx_queues; i++)
1737                 napi_enable(&adapter->rx_ring[i].napi);
1738
1739         /* Clear any pending interrupts. */
1740         rd32(E1000_ICR);
1741
1742         igb_irq_enable(adapter);
1743
1744         netif_tx_start_all_queues(netdev);
1745
1746         /* Fire a link status change interrupt to start the watchdog. */
1747         wr32(E1000_ICS, E1000_ICS_LSC);
1748
1749         return 0;
1750
1751 err_req_irq:
1752         igb_release_hw_control(adapter);
1753         /* e1000_power_down_phy(adapter); */
1754         igb_free_all_rx_resources(adapter);
1755 err_setup_rx:
1756         igb_free_all_tx_resources(adapter);
1757 err_setup_tx:
1758         igb_reset(adapter);
1759
1760         return err;
1761 }
1762
1763 /**
1764  * igb_close - Disables a network interface
1765  * @netdev: network interface device structure
1766  *
1767  * Returns 0, this is not allowed to fail
1768  *
1769  * The close entry point is called when an interface is de-activated
1770  * by the OS.  The hardware is still under the driver's control, but
1771  * needs to be disabled.  A global MAC reset is issued to stop the
1772  * hardware, and all transmit and receive resources are freed.
1773  **/
1774 static int igb_close(struct net_device *netdev)
1775 {
1776         struct igb_adapter *adapter = netdev_priv(netdev);
1777
1778         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1779         igb_down(adapter);
1780
1781         igb_free_irq(adapter);
1782
1783         igb_free_all_tx_resources(adapter);
1784         igb_free_all_rx_resources(adapter);
1785
1786         /* kill manageability vlan ID if supported, but not if a vlan with
1787          * the same ID is registered on the host OS (let 8021q kill it) */
1788         if ((adapter->hw.mng_cookie.status &
1789                           E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1790              !(adapter->vlgrp &&
1791                vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1792                 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1793
1794         return 0;
1795 }
1796
1797 /**
1798  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1799  * @adapter: board private structure
1800  * @tx_ring: tx descriptor ring (for a specific queue) to setup
1801  *
1802  * Return 0 on success, negative on failure
1803  **/
1804 int igb_setup_tx_resources(struct igb_adapter *adapter,
1805                            struct igb_ring *tx_ring)
1806 {
1807         struct pci_dev *pdev = adapter->pdev;
1808         int size;
1809
1810         size = sizeof(struct igb_buffer) * tx_ring->count;
1811         tx_ring->buffer_info = vmalloc(size);
1812         if (!tx_ring->buffer_info)
1813                 goto err;
1814         memset(tx_ring->buffer_info, 0, size);
1815
1816         /* round up to nearest 4K */
1817         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1818         tx_ring->size = ALIGN(tx_ring->size, 4096);
1819
1820         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1821                                              &tx_ring->dma);
1822
1823         if (!tx_ring->desc)
1824                 goto err;
1825
1826         tx_ring->adapter = adapter;
1827         tx_ring->next_to_use = 0;
1828         tx_ring->next_to_clean = 0;
1829         return 0;
1830
1831 err:
1832         vfree(tx_ring->buffer_info);
1833         dev_err(&adapter->pdev->dev,
1834                 "Unable to allocate memory for the transmit descriptor ring\n");
1835         return -ENOMEM;
1836 }
1837
1838 /**
1839  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1840  *                                (Descriptors) for all queues
1841  * @adapter: board private structure
1842  *
1843  * Return 0 on success, negative on failure
1844  **/
1845 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1846 {
1847         int i, err = 0;
1848         int r_idx;
1849
1850         for (i = 0; i < adapter->num_tx_queues; i++) {
1851                 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1852                 if (err) {
1853                         dev_err(&adapter->pdev->dev,
1854                                 "Allocation for Tx Queue %u failed\n", i);
1855                         for (i--; i >= 0; i--)
1856                                 igb_free_tx_resources(&adapter->tx_ring[i]);
1857                         break;
1858                 }
1859         }
1860
1861         for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1862                 r_idx = i % adapter->num_tx_queues;
1863                 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1864         }
1865         return err;
1866 }
1867
1868 /**
1869  * igb_configure_tx - Configure transmit Unit after Reset
1870  * @adapter: board private structure
1871  *
1872  * Configure the Tx unit of the MAC after a reset.
1873  **/
1874 static void igb_configure_tx(struct igb_adapter *adapter)
1875 {
1876         u64 tdba;
1877         struct e1000_hw *hw = &adapter->hw;
1878         u32 tctl;
1879         u32 txdctl, txctrl;
1880         int i, j;
1881
1882         for (i = 0; i < adapter->num_tx_queues; i++) {
1883                 struct igb_ring *ring = &adapter->tx_ring[i];
1884                 j = ring->reg_idx;
1885                 wr32(E1000_TDLEN(j),
1886                      ring->count * sizeof(union e1000_adv_tx_desc));
1887                 tdba = ring->dma;
1888                 wr32(E1000_TDBAL(j),
1889                      tdba & 0x00000000ffffffffULL);
1890                 wr32(E1000_TDBAH(j), tdba >> 32);
1891
1892                 ring->head = E1000_TDH(j);
1893                 ring->tail = E1000_TDT(j);
1894                 writel(0, hw->hw_addr + ring->tail);
1895                 writel(0, hw->hw_addr + ring->head);
1896                 txdctl = rd32(E1000_TXDCTL(j));
1897                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1898                 wr32(E1000_TXDCTL(j), txdctl);
1899
1900                 /* Turn off Relaxed Ordering on head write-backs.  The
1901                  * writebacks MUST be delivered in order or it will
1902                  * completely screw up our bookeeping.
1903                  */
1904                 txctrl = rd32(E1000_DCA_TXCTRL(j));
1905                 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1906                 wr32(E1000_DCA_TXCTRL(j), txctrl);
1907         }
1908
1909         /* disable queue 0 to prevent tail bump w/o re-configuration */
1910         if (adapter->vfs_allocated_count)
1911                 wr32(E1000_TXDCTL(0), 0);
1912
1913         /* Program the Transmit Control Register */
1914         tctl = rd32(E1000_TCTL);
1915         tctl &= ~E1000_TCTL_CT;
1916         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1917                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1918
1919         igb_config_collision_dist(hw);
1920
1921         /* Setup Transmit Descriptor Settings for eop descriptor */
1922         adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1923
1924         /* Enable transmits */
1925         tctl |= E1000_TCTL_EN;
1926
1927         wr32(E1000_TCTL, tctl);
1928 }
1929
1930 /**
1931  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1932  * @adapter: board private structure
1933  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
1934  *
1935  * Returns 0 on success, negative on failure
1936  **/
1937 int igb_setup_rx_resources(struct igb_adapter *adapter,
1938                            struct igb_ring *rx_ring)
1939 {
1940         struct pci_dev *pdev = adapter->pdev;
1941         int size, desc_len;
1942
1943         size = sizeof(struct igb_buffer) * rx_ring->count;
1944         rx_ring->buffer_info = vmalloc(size);
1945         if (!rx_ring->buffer_info)
1946                 goto err;
1947         memset(rx_ring->buffer_info, 0, size);
1948
1949         desc_len = sizeof(union e1000_adv_rx_desc);
1950
1951         /* Round up to nearest 4K */
1952         rx_ring->size = rx_ring->count * desc_len;
1953         rx_ring->size = ALIGN(rx_ring->size, 4096);
1954
1955         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1956                                              &rx_ring->dma);
1957
1958         if (!rx_ring->desc)
1959                 goto err;
1960
1961         rx_ring->next_to_clean = 0;
1962         rx_ring->next_to_use = 0;
1963
1964         rx_ring->adapter = adapter;
1965
1966         return 0;
1967
1968 err:
1969         vfree(rx_ring->buffer_info);
1970         dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1971                 "the receive descriptor ring\n");
1972         return -ENOMEM;
1973 }
1974
1975 /**
1976  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1977  *                                (Descriptors) for all queues
1978  * @adapter: board private structure
1979  *
1980  * Return 0 on success, negative on failure
1981  **/
1982 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1983 {
1984         int i, err = 0;
1985
1986         for (i = 0; i < adapter->num_rx_queues; i++) {
1987                 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1988                 if (err) {
1989                         dev_err(&adapter->pdev->dev,
1990                                 "Allocation for Rx Queue %u failed\n", i);
1991                         for (i--; i >= 0; i--)
1992                                 igb_free_rx_resources(&adapter->rx_ring[i]);
1993                         break;
1994                 }
1995         }
1996
1997         return err;
1998 }
1999
2000 /**
2001  * igb_setup_rctl - configure the receive control registers
2002  * @adapter: Board private structure
2003  **/
2004 static void igb_setup_rctl(struct igb_adapter *adapter)
2005 {
2006         struct e1000_hw *hw = &adapter->hw;
2007         u32 rctl;
2008         u32 srrctl = 0;
2009         int i;
2010
2011         rctl = rd32(E1000_RCTL);
2012
2013         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2014         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2015
2016         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2017                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2018
2019         /*
2020          * enable stripping of CRC. It's unlikely this will break BMC
2021          * redirection as it did with e1000. Newer features require
2022          * that the HW strips the CRC.
2023          */
2024         rctl |= E1000_RCTL_SECRC;
2025
2026         /*
2027          * disable store bad packets and clear size bits.
2028          */
2029         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2030
2031         /* enable LPE when to prevent packets larger than max_frame_size */
2032                 rctl |= E1000_RCTL_LPE;
2033
2034         /* Setup buffer sizes */
2035         switch (adapter->rx_buffer_len) {
2036         case IGB_RXBUFFER_256:
2037                 rctl |= E1000_RCTL_SZ_256;
2038                 break;
2039         case IGB_RXBUFFER_512:
2040                 rctl |= E1000_RCTL_SZ_512;
2041                 break;
2042         default:
2043                 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2044                          >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2045                 break;
2046         }
2047
2048         /* 82575 and greater support packet-split where the protocol
2049          * header is placed in skb->data and the packet data is
2050          * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2051          * In the case of a non-split, skb->data is linearly filled,
2052          * followed by the page buffers.  Therefore, skb->data is
2053          * sized to hold the largest protocol header.
2054          */
2055         /* allocations using alloc_page take too long for regular MTU
2056          * so only enable packet split for jumbo frames */
2057         if (adapter->netdev->mtu > ETH_DATA_LEN) {
2058                 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
2059                 srrctl |= adapter->rx_ps_hdr_size <<
2060                          E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2061                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2062         } else {
2063                 adapter->rx_ps_hdr_size = 0;
2064                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2065         }
2066
2067         /* Attention!!!  For SR-IOV PF driver operations you must enable
2068          * queue drop for all VF and PF queues to prevent head of line blocking
2069          * if an un-trusted VF does not provide descriptors to hardware.
2070          */
2071         if (adapter->vfs_allocated_count) {
2072                 u32 vmolr;
2073
2074                 /* set all queue drop enable bits */
2075                 wr32(E1000_QDE, ALL_QUEUES);
2076                 srrctl |= E1000_SRRCTL_DROP_EN;
2077
2078                 /* disable queue 0 to prevent tail write w/o re-config */
2079                 wr32(E1000_RXDCTL(0), 0);
2080
2081                 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
2082                 if (rctl & E1000_RCTL_LPE)
2083                         vmolr |= E1000_VMOLR_LPE;
2084                 if (adapter->num_rx_queues > 1)
2085                         vmolr |= E1000_VMOLR_RSSE;
2086                 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
2087         }
2088
2089         for (i = 0; i < adapter->num_rx_queues; i++) {
2090                 int j = adapter->rx_ring[i].reg_idx;
2091                 wr32(E1000_SRRCTL(j), srrctl);
2092         }
2093
2094         wr32(E1000_RCTL, rctl);
2095 }
2096
2097 /**
2098  * igb_rlpml_set - set maximum receive packet size
2099  * @adapter: board private structure
2100  *
2101  * Configure maximum receivable packet size.
2102  **/
2103 static void igb_rlpml_set(struct igb_adapter *adapter)
2104 {
2105         u32 max_frame_size = adapter->max_frame_size;
2106         struct e1000_hw *hw = &adapter->hw;
2107         u16 pf_id = adapter->vfs_allocated_count;
2108
2109         if (adapter->vlgrp)
2110                 max_frame_size += VLAN_TAG_SIZE;
2111
2112         /* if vfs are enabled we set RLPML to the largest possible request
2113          * size and set the VMOLR RLPML to the size we need */
2114         if (pf_id) {
2115                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2116                 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2117         }
2118
2119         wr32(E1000_RLPML, max_frame_size);
2120 }
2121
2122 /**
2123  * igb_configure_vt_default_pool - Configure VT default pool
2124  * @adapter: board private structure
2125  *
2126  * Configure the default pool
2127  **/
2128 static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2129 {
2130         struct e1000_hw *hw = &adapter->hw;
2131         u16 pf_id = adapter->vfs_allocated_count;
2132         u32 vtctl;
2133
2134         /* not in sr-iov mode - do nothing */
2135         if (!pf_id)
2136                 return;
2137
2138         vtctl = rd32(E1000_VT_CTL);
2139         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2140                    E1000_VT_CTL_DISABLE_DEF_POOL);
2141         vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2142         wr32(E1000_VT_CTL, vtctl);
2143 }
2144
2145 /**
2146  * igb_configure_rx - Configure receive Unit after Reset
2147  * @adapter: board private structure
2148  *
2149  * Configure the Rx unit of the MAC after a reset.
2150  **/
2151 static void igb_configure_rx(struct igb_adapter *adapter)
2152 {
2153         u64 rdba;
2154         struct e1000_hw *hw = &adapter->hw;
2155         u32 rctl, rxcsum;
2156         u32 rxdctl;
2157         int i;
2158
2159         /* disable receives while setting up the descriptors */
2160         rctl = rd32(E1000_RCTL);
2161         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2162         wrfl();
2163         mdelay(10);
2164
2165         if (adapter->itr_setting > 3)
2166                 wr32(E1000_ITR, adapter->itr);
2167
2168         /* Setup the HW Rx Head and Tail Descriptor Pointers and
2169          * the Base and Length of the Rx Descriptor Ring */
2170         for (i = 0; i < adapter->num_rx_queues; i++) {
2171                 struct igb_ring *ring = &adapter->rx_ring[i];
2172                 int j = ring->reg_idx;
2173                 rdba = ring->dma;
2174                 wr32(E1000_RDBAL(j),
2175                      rdba & 0x00000000ffffffffULL);
2176                 wr32(E1000_RDBAH(j), rdba >> 32);
2177                 wr32(E1000_RDLEN(j),
2178                      ring->count * sizeof(union e1000_adv_rx_desc));
2179
2180                 ring->head = E1000_RDH(j);
2181                 ring->tail = E1000_RDT(j);
2182                 writel(0, hw->hw_addr + ring->tail);
2183                 writel(0, hw->hw_addr + ring->head);
2184
2185                 rxdctl = rd32(E1000_RXDCTL(j));
2186                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2187                 rxdctl &= 0xFFF00000;
2188                 rxdctl |= IGB_RX_PTHRESH;
2189                 rxdctl |= IGB_RX_HTHRESH << 8;
2190                 rxdctl |= IGB_RX_WTHRESH << 16;
2191                 wr32(E1000_RXDCTL(j), rxdctl);
2192         }
2193
2194         if (adapter->num_rx_queues > 1) {
2195                 u32 random[10];
2196                 u32 mrqc;
2197                 u32 j, shift;
2198                 union e1000_reta {
2199                         u32 dword;
2200                         u8  bytes[4];
2201                 } reta;
2202
2203                 get_random_bytes(&random[0], 40);
2204
2205                 if (hw->mac.type >= e1000_82576)
2206                         shift = 0;
2207                 else
2208                         shift = 6;
2209                 for (j = 0; j < (32 * 4); j++) {
2210                         reta.bytes[j & 3] =
2211                                 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
2212                         if ((j & 3) == 3)
2213                                 writel(reta.dword,
2214                                        hw->hw_addr + E1000_RETA(0) + (j & ~3));
2215                 }
2216                 if (adapter->vfs_allocated_count)
2217                         mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2218                 else
2219                         mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2220
2221                 /* Fill out hash function seeds */
2222                 for (j = 0; j < 10; j++)
2223                         array_wr32(E1000_RSSRK(0), j, random[j]);
2224
2225                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2226                          E1000_MRQC_RSS_FIELD_IPV4_TCP);
2227                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2228                          E1000_MRQC_RSS_FIELD_IPV6_TCP);
2229                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2230                          E1000_MRQC_RSS_FIELD_IPV6_UDP);
2231                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2232                          E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2233
2234
2235                 wr32(E1000_MRQC, mrqc);
2236
2237                 /* Multiqueue and raw packet checksumming are mutually
2238                  * exclusive.  Note that this not the same as TCP/IP
2239                  * checksumming, which works fine. */
2240                 rxcsum = rd32(E1000_RXCSUM);
2241                 rxcsum |= E1000_RXCSUM_PCSD;
2242                 wr32(E1000_RXCSUM, rxcsum);
2243         } else {
2244                 /* Enable multi-queue for sr-iov */
2245                 if (adapter->vfs_allocated_count)
2246                         wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
2247                 /* Enable Receive Checksum Offload for TCP and UDP */
2248                 rxcsum = rd32(E1000_RXCSUM);
2249                 if (adapter->rx_csum)
2250                         rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE;
2251                 else
2252                         rxcsum &= ~(E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE);
2253
2254                 wr32(E1000_RXCSUM, rxcsum);
2255         }
2256
2257         /* Set the default pool for the PF's first queue */
2258         igb_configure_vt_default_pool(adapter);
2259
2260         igb_rlpml_set(adapter);
2261
2262         /* Enable Receives */
2263         wr32(E1000_RCTL, rctl);
2264 }
2265
2266 /**
2267  * igb_free_tx_resources - Free Tx Resources per Queue
2268  * @tx_ring: Tx descriptor ring for a specific queue
2269  *
2270  * Free all transmit software resources
2271  **/
2272 void igb_free_tx_resources(struct igb_ring *tx_ring)
2273 {
2274         struct pci_dev *pdev = tx_ring->adapter->pdev;
2275
2276         igb_clean_tx_ring(tx_ring);
2277
2278         vfree(tx_ring->buffer_info);
2279         tx_ring->buffer_info = NULL;
2280
2281         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2282
2283         tx_ring->desc = NULL;
2284 }
2285
2286 /**
2287  * igb_free_all_tx_resources - Free Tx Resources for All Queues
2288  * @adapter: board private structure
2289  *
2290  * Free all transmit software resources
2291  **/
2292 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2293 {
2294         int i;
2295
2296         for (i = 0; i < adapter->num_tx_queues; i++)
2297                 igb_free_tx_resources(&adapter->tx_ring[i]);
2298 }
2299
2300 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2301                                            struct igb_buffer *buffer_info)
2302 {
2303         buffer_info->dma = 0;
2304         if (buffer_info->skb) {
2305                 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2306                               DMA_TO_DEVICE);
2307                 dev_kfree_skb_any(buffer_info->skb);
2308                 buffer_info->skb = NULL;
2309         }
2310         buffer_info->time_stamp = 0;
2311         /* buffer_info must be completely set up in the transmit path */
2312 }
2313
2314 /**
2315  * igb_clean_tx_ring - Free Tx Buffers
2316  * @tx_ring: ring to be cleaned
2317  **/
2318 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2319 {
2320         struct igb_adapter *adapter = tx_ring->adapter;
2321         struct igb_buffer *buffer_info;
2322         unsigned long size;
2323         unsigned int i;
2324
2325         if (!tx_ring->buffer_info)
2326                 return;
2327         /* Free all the Tx ring sk_buffs */
2328
2329         for (i = 0; i < tx_ring->count; i++) {
2330                 buffer_info = &tx_ring->buffer_info[i];
2331                 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2332         }
2333
2334         size = sizeof(struct igb_buffer) * tx_ring->count;
2335         memset(tx_ring->buffer_info, 0, size);
2336
2337         /* Zero out the descriptor ring */
2338
2339         memset(tx_ring->desc, 0, tx_ring->size);
2340
2341         tx_ring->next_to_use = 0;
2342         tx_ring->next_to_clean = 0;
2343
2344         writel(0, adapter->hw.hw_addr + tx_ring->head);
2345         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2346 }
2347
2348 /**
2349  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2350  * @adapter: board private structure
2351  **/
2352 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2353 {
2354         int i;
2355
2356         for (i = 0; i < adapter->num_tx_queues; i++)
2357                 igb_clean_tx_ring(&adapter->tx_ring[i]);
2358 }
2359
2360 /**
2361  * igb_free_rx_resources - Free Rx Resources
2362  * @rx_ring: ring to clean the resources from
2363  *
2364  * Free all receive software resources
2365  **/
2366 void igb_free_rx_resources(struct igb_ring *rx_ring)
2367 {
2368         struct pci_dev *pdev = rx_ring->adapter->pdev;
2369
2370         igb_clean_rx_ring(rx_ring);
2371
2372         vfree(rx_ring->buffer_info);
2373         rx_ring->buffer_info = NULL;
2374
2375         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2376
2377         rx_ring->desc = NULL;
2378 }
2379
2380 /**
2381  * igb_free_all_rx_resources - Free Rx Resources for All Queues
2382  * @adapter: board private structure
2383  *
2384  * Free all receive software resources
2385  **/
2386 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2387 {
2388         int i;
2389
2390         for (i = 0; i < adapter->num_rx_queues; i++)
2391                 igb_free_rx_resources(&adapter->rx_ring[i]);
2392 }
2393
2394 /**
2395  * igb_clean_rx_ring - Free Rx Buffers per Queue
2396  * @rx_ring: ring to free buffers from
2397  **/
2398 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2399 {
2400         struct igb_adapter *adapter = rx_ring->adapter;
2401         struct igb_buffer *buffer_info;
2402         struct pci_dev *pdev = adapter->pdev;
2403         unsigned long size;
2404         unsigned int i;
2405
2406         if (!rx_ring->buffer_info)
2407                 return;
2408         /* Free all the Rx ring sk_buffs */
2409         for (i = 0; i < rx_ring->count; i++) {
2410                 buffer_info = &rx_ring->buffer_info[i];
2411                 if (buffer_info->dma) {
2412                         if (adapter->rx_ps_hdr_size)
2413                                 pci_unmap_single(pdev, buffer_info->dma,
2414                                                  adapter->rx_ps_hdr_size,
2415                                                  PCI_DMA_FROMDEVICE);
2416                         else
2417                                 pci_unmap_single(pdev, buffer_info->dma,
2418                                                  adapter->rx_buffer_len,
2419                                                  PCI_DMA_FROMDEVICE);
2420                         buffer_info->dma = 0;
2421                 }
2422
2423                 if (buffer_info->skb) {
2424                         dev_kfree_skb(buffer_info->skb);
2425                         buffer_info->skb = NULL;
2426                 }
2427                 if (buffer_info->page) {
2428                         if (buffer_info->page_dma)
2429                                 pci_unmap_page(pdev, buffer_info->page_dma,
2430                                                PAGE_SIZE / 2,
2431                                                PCI_DMA_FROMDEVICE);
2432                         put_page(buffer_info->page);
2433                         buffer_info->page = NULL;
2434                         buffer_info->page_dma = 0;
2435                         buffer_info->page_offset = 0;
2436                 }
2437         }
2438
2439         size = sizeof(struct igb_buffer) * rx_ring->count;
2440         memset(rx_ring->buffer_info, 0, size);
2441
2442         /* Zero out the descriptor ring */
2443         memset(rx_ring->desc, 0, rx_ring->size);
2444
2445         rx_ring->next_to_clean = 0;
2446         rx_ring->next_to_use = 0;
2447
2448         writel(0, adapter->hw.hw_addr + rx_ring->head);
2449         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2450 }
2451
2452 /**
2453  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2454  * @adapter: board private structure
2455  **/
2456 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2457 {
2458         int i;
2459
2460         for (i = 0; i < adapter->num_rx_queues; i++)
2461                 igb_clean_rx_ring(&adapter->rx_ring[i]);
2462 }
2463
2464 /**
2465  * igb_set_mac - Change the Ethernet Address of the NIC
2466  * @netdev: network interface device structure
2467  * @p: pointer to an address structure
2468  *
2469  * Returns 0 on success, negative on failure
2470  **/
2471 static int igb_set_mac(struct net_device *netdev, void *p)
2472 {
2473         struct igb_adapter *adapter = netdev_priv(netdev);
2474         struct e1000_hw *hw = &adapter->hw;
2475         struct sockaddr *addr = p;
2476
2477         if (!is_valid_ether_addr(addr->sa_data))
2478                 return -EADDRNOTAVAIL;
2479
2480         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2481         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2482
2483         hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
2484
2485         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2486
2487         return 0;
2488 }
2489
2490 /**
2491  * igb_set_multi - Multicast and Promiscuous mode set
2492  * @netdev: network interface device structure
2493  *
2494  * The set_multi entry point is called whenever the multicast address
2495  * list or the network interface flags are updated.  This routine is
2496  * responsible for configuring the hardware for proper multicast,
2497  * promiscuous mode, and all-multi behavior.
2498  **/
2499 static void igb_set_multi(struct net_device *netdev)
2500 {
2501         struct igb_adapter *adapter = netdev_priv(netdev);
2502         struct e1000_hw *hw = &adapter->hw;
2503         struct e1000_mac_info *mac = &hw->mac;
2504         struct dev_mc_list *mc_ptr;
2505         u8  *mta_list = NULL;
2506         u32 rctl;
2507         int i;
2508
2509         /* Check for Promiscuous and All Multicast modes */
2510
2511         rctl = rd32(E1000_RCTL);
2512
2513         if (netdev->flags & IFF_PROMISC) {
2514                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2515                 rctl &= ~E1000_RCTL_VFE;
2516         } else {
2517                 if (netdev->flags & IFF_ALLMULTI) {
2518                         rctl |= E1000_RCTL_MPE;
2519                         rctl &= ~E1000_RCTL_UPE;
2520                 } else
2521                         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2522                 rctl |= E1000_RCTL_VFE;
2523         }
2524         wr32(E1000_RCTL, rctl);
2525
2526         if (netdev->mc_count) {
2527                 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2528                 if (!mta_list) {
2529                         dev_err(&adapter->pdev->dev,
2530                                 "failed to allocate multicast filter list\n");
2531                         return;
2532                 }
2533         }
2534
2535         /* The shared function expects a packed array of only addresses. */
2536         mc_ptr = netdev->mc_list;
2537
2538         for (i = 0; i < netdev->mc_count; i++) {
2539                 if (!mc_ptr)
2540                         break;
2541                 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2542                 mc_ptr = mc_ptr->next;
2543         }
2544         igb_update_mc_addr_list(hw, mta_list, i,
2545                                 adapter->vfs_allocated_count + 1,
2546                                 mac->rar_entry_count);
2547
2548         igb_set_mc_list_pools(adapter, i, mac->rar_entry_count);
2549         igb_restore_vf_multicasts(adapter);
2550
2551         kfree(mta_list);
2552 }
2553
2554 /* Need to wait a few seconds after link up to get diagnostic information from
2555  * the phy */
2556 static void igb_update_phy_info(unsigned long data)
2557 {
2558         struct igb_adapter *adapter = (struct igb_adapter *) data;
2559         igb_get_phy_info(&adapter->hw);
2560 }
2561
2562 /**
2563  * igb_has_link - check shared code for link and determine up/down
2564  * @adapter: pointer to driver private info
2565  **/
2566 static bool igb_has_link(struct igb_adapter *adapter)
2567 {
2568         struct e1000_hw *hw = &adapter->hw;
2569         bool link_active = false;
2570         s32 ret_val = 0;
2571
2572         /* get_link_status is set on LSC (link status) interrupt or
2573          * rx sequence error interrupt.  get_link_status will stay
2574          * false until the e1000_check_for_link establishes link
2575          * for copper adapters ONLY
2576          */
2577         switch (hw->phy.media_type) {
2578         case e1000_media_type_copper:
2579                 if (hw->mac.get_link_status) {
2580                         ret_val = hw->mac.ops.check_for_link(hw);
2581                         link_active = !hw->mac.get_link_status;
2582                 } else {
2583                         link_active = true;
2584                 }
2585                 break;
2586         case e1000_media_type_fiber:
2587                 ret_val = hw->mac.ops.check_for_link(hw);
2588                 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2589                 break;
2590         case e1000_media_type_internal_serdes:
2591                 ret_val = hw->mac.ops.check_for_link(hw);
2592                 link_active = hw->mac.serdes_has_link;
2593                 break;
2594         default:
2595         case e1000_media_type_unknown:
2596                 break;
2597         }
2598
2599         return link_active;
2600 }
2601
2602 /**
2603  * igb_watchdog - Timer Call-back
2604  * @data: pointer to adapter cast into an unsigned long
2605  **/
2606 static void igb_watchdog(unsigned long data)
2607 {
2608         struct igb_adapter *adapter = (struct igb_adapter *)data;
2609         /* Do the rest outside of interrupt context */
2610         schedule_work(&adapter->watchdog_task);
2611 }
2612
2613 static void igb_watchdog_task(struct work_struct *work)
2614 {
2615         struct igb_adapter *adapter = container_of(work,
2616                                         struct igb_adapter, watchdog_task);
2617         struct e1000_hw *hw = &adapter->hw;
2618         struct net_device *netdev = adapter->netdev;
2619         struct igb_ring *tx_ring = adapter->tx_ring;
2620         u32 link;
2621         u32 eics = 0;
2622         int i;
2623
2624         link = igb_has_link(adapter);
2625         if ((netif_carrier_ok(netdev)) && link)
2626                 goto link_up;
2627
2628         if (link) {
2629                 if (!netif_carrier_ok(netdev)) {
2630                         u32 ctrl;
2631                         hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2632                                                    &adapter->link_speed,
2633                                                    &adapter->link_duplex);
2634
2635                         ctrl = rd32(E1000_CTRL);
2636                         /* Links status message must follow this format */
2637                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2638                                  "Flow Control: %s\n",
2639                                  netdev->name,
2640                                  adapter->link_speed,
2641                                  adapter->link_duplex == FULL_DUPLEX ?
2642                                  "Full Duplex" : "Half Duplex",
2643                                  ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2644                                  E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2645                                  E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2646                                  E1000_CTRL_TFCE) ? "TX" : "None")));
2647
2648                         /* tweak tx_queue_len according to speed/duplex and
2649                          * adjust the timeout factor */
2650                         netdev->tx_queue_len = adapter->tx_queue_len;
2651                         adapter->tx_timeout_factor = 1;
2652                         switch (adapter->link_speed) {
2653                         case SPEED_10:
2654                                 netdev->tx_queue_len = 10;
2655                                 adapter->tx_timeout_factor = 14;
2656                                 break;
2657                         case SPEED_100:
2658                                 netdev->tx_queue_len = 100;
2659                                 /* maybe add some timeout factor ? */
2660                                 break;
2661                         }
2662
2663                         netif_carrier_on(netdev);
2664                         netif_tx_wake_all_queues(netdev);
2665
2666                         igb_ping_all_vfs(adapter);
2667
2668                         /* link state has changed, schedule phy info update */
2669                         if (!test_bit(__IGB_DOWN, &adapter->state))
2670                                 mod_timer(&adapter->phy_info_timer,
2671                                           round_jiffies(jiffies + 2 * HZ));
2672                 }
2673         } else {
2674                 if (netif_carrier_ok(netdev)) {
2675                         adapter->link_speed = 0;
2676                         adapter->link_duplex = 0;
2677                         /* Links status message must follow this format */
2678                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
2679                                netdev->name);
2680                         netif_carrier_off(netdev);
2681                         netif_tx_stop_all_queues(netdev);
2682
2683                         igb_ping_all_vfs(adapter);
2684
2685                         /* link state has changed, schedule phy info update */
2686                         if (!test_bit(__IGB_DOWN, &adapter->state))
2687                                 mod_timer(&adapter->phy_info_timer,
2688                                           round_jiffies(jiffies + 2 * HZ));
2689                 }
2690         }
2691
2692 link_up:
2693         igb_update_stats(adapter);
2694
2695         hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2696         adapter->tpt_old = adapter->stats.tpt;
2697         hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2698         adapter->colc_old = adapter->stats.colc;
2699
2700         adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2701         adapter->gorc_old = adapter->stats.gorc;
2702         adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2703         adapter->gotc_old = adapter->stats.gotc;
2704
2705         igb_update_adaptive(&adapter->hw);
2706
2707         if (!netif_carrier_ok(netdev)) {
2708                 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
2709                         /* We've lost link, so the controller stops DMA,
2710                          * but we've got queued Tx work that's never going
2711                          * to get done, so reset controller to flush Tx.
2712                          * (Do the reset outside of interrupt context). */
2713                         adapter->tx_timeout_count++;
2714                         schedule_work(&adapter->reset_task);
2715                 }
2716         }
2717
2718         /* Cause software interrupt to ensure rx ring is cleaned */
2719         if (adapter->msix_entries) {
2720                 for (i = 0; i < adapter->num_rx_queues; i++)
2721                         eics |= adapter->rx_ring[i].eims_value;
2722                 wr32(E1000_EICS, eics);
2723         } else {
2724                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2725         }
2726
2727         /* Force detection of hung controller every watchdog period */
2728         tx_ring->detect_tx_hung = true;
2729
2730         /* Reset the timer */
2731         if (!test_bit(__IGB_DOWN, &adapter->state))
2732                 mod_timer(&adapter->watchdog_timer,
2733                           round_jiffies(jiffies + 2 * HZ));
2734 }
2735
2736 enum latency_range {
2737         lowest_latency = 0,
2738         low_latency = 1,
2739         bulk_latency = 2,
2740         latency_invalid = 255
2741 };
2742
2743
2744 /**
2745  * igb_update_ring_itr - update the dynamic ITR value based on packet size
2746  *
2747  *      Stores a new ITR value based on strictly on packet size.  This
2748  *      algorithm is less sophisticated than that used in igb_update_itr,
2749  *      due to the difficulty of synchronizing statistics across multiple
2750  *      receive rings.  The divisors and thresholds used by this fuction
2751  *      were determined based on theoretical maximum wire speed and testing
2752  *      data, in order to minimize response time while increasing bulk
2753  *      throughput.
2754  *      This functionality is controlled by the InterruptThrottleRate module
2755  *      parameter (see igb_param.c)
2756  *      NOTE:  This function is called only when operating in a multiqueue
2757  *             receive environment.
2758  * @rx_ring: pointer to ring
2759  **/
2760 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2761 {
2762         int new_val = rx_ring->itr_val;
2763         int avg_wire_size = 0;
2764         struct igb_adapter *adapter = rx_ring->adapter;
2765
2766         if (!rx_ring->total_packets)
2767                 goto clear_counts; /* no packets, so don't do anything */
2768
2769         /* For non-gigabit speeds, just fix the interrupt rate at 4000
2770          * ints/sec - ITR timer value of 120 ticks.
2771          */
2772         if (adapter->link_speed != SPEED_1000) {
2773                 new_val = 120;
2774                 goto set_itr_val;
2775         }
2776         avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2777
2778         /* Add 24 bytes to size to account for CRC, preamble, and gap */
2779         avg_wire_size += 24;
2780
2781         /* Don't starve jumbo frames */
2782         avg_wire_size = min(avg_wire_size, 3000);
2783
2784         /* Give a little boost to mid-size frames */
2785         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2786                 new_val = avg_wire_size / 3;
2787         else
2788                 new_val = avg_wire_size / 2;
2789
2790 set_itr_val:
2791         if (new_val != rx_ring->itr_val) {
2792                 rx_ring->itr_val = new_val;
2793                 rx_ring->set_itr = 1;
2794         }
2795 clear_counts:
2796         rx_ring->total_bytes = 0;
2797         rx_ring->total_packets = 0;
2798 }
2799
2800 /**
2801  * igb_update_itr - update the dynamic ITR value based on statistics
2802  *      Stores a new ITR value based on packets and byte
2803  *      counts during the last interrupt.  The advantage of per interrupt
2804  *      computation is faster updates and more accurate ITR for the current
2805  *      traffic pattern.  Constants in this function were computed
2806  *      based on theoretical maximum wire speed and thresholds were set based
2807  *      on testing data as well as attempting to minimize response time
2808  *      while increasing bulk throughput.
2809  *      this functionality is controlled by the InterruptThrottleRate module
2810  *      parameter (see igb_param.c)
2811  *      NOTE:  These calculations are only valid when operating in a single-
2812  *             queue environment.
2813  * @adapter: pointer to adapter
2814  * @itr_setting: current adapter->itr
2815  * @packets: the number of packets during this measurement interval
2816  * @bytes: the number of bytes during this measurement interval
2817  **/
2818 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2819                                    int packets, int bytes)
2820 {
2821         unsigned int retval = itr_setting;
2822
2823         if (packets == 0)
2824                 goto update_itr_done;
2825
2826         switch (itr_setting) {
2827         case lowest_latency:
2828                 /* handle TSO and jumbo frames */
2829                 if (bytes/packets > 8000)
2830                         retval = bulk_latency;
2831                 else if ((packets < 5) && (bytes > 512))
2832                         retval = low_latency;
2833                 break;
2834         case low_latency:  /* 50 usec aka 20000 ints/s */
2835                 if (bytes > 10000) {
2836                         /* this if handles the TSO accounting */
2837                         if (bytes/packets > 8000) {
2838                                 retval = bulk_latency;
2839                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2840                                 retval = bulk_latency;
2841                         } else if ((packets > 35)) {
2842                                 retval = lowest_latency;
2843                         }
2844                 } else if (bytes/packets > 2000) {
2845                         retval = bulk_latency;
2846                 } else if (packets <= 2 && bytes < 512) {
2847                         retval = lowest_latency;
2848                 }
2849                 break;
2850         case bulk_latency: /* 250 usec aka 4000 ints/s */
2851                 if (bytes > 25000) {
2852                         if (packets > 35)
2853                                 retval = low_latency;
2854                 } else if (bytes < 1500) {
2855                         retval = low_latency;
2856                 }
2857                 break;
2858         }
2859
2860 update_itr_done:
2861         return retval;
2862 }
2863
2864 static void igb_set_itr(struct igb_adapter *adapter)
2865 {
2866         u16 current_itr;
2867         u32 new_itr = adapter->itr;
2868
2869         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2870         if (adapter->link_speed != SPEED_1000) {
2871                 current_itr = 0;
2872                 new_itr = 4000;
2873                 goto set_itr_now;
2874         }
2875
2876         adapter->rx_itr = igb_update_itr(adapter,
2877                                     adapter->rx_itr,
2878                                     adapter->rx_ring->total_packets,
2879                                     adapter->rx_ring->total_bytes);
2880
2881         if (adapter->rx_ring->buddy) {
2882                 adapter->tx_itr = igb_update_itr(adapter,
2883                                             adapter->tx_itr,
2884                                             adapter->tx_ring->total_packets,
2885                                             adapter->tx_ring->total_bytes);
2886                 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2887         } else {
2888                 current_itr = adapter->rx_itr;
2889         }
2890
2891         /* conservative mode (itr 3) eliminates the lowest_latency setting */
2892         if (adapter->itr_setting == 3 && current_itr == lowest_latency)
2893                 current_itr = low_latency;
2894
2895         switch (current_itr) {
2896         /* counts and packets in update_itr are dependent on these numbers */
2897         case lowest_latency:
2898                 new_itr = 70000;
2899                 break;
2900         case low_latency:
2901                 new_itr = 20000; /* aka hwitr = ~200 */
2902                 break;
2903         case bulk_latency:
2904                 new_itr = 4000;
2905                 break;
2906         default:
2907                 break;
2908         }
2909
2910 set_itr_now:
2911         adapter->rx_ring->total_bytes = 0;
2912         adapter->rx_ring->total_packets = 0;
2913         if (adapter->rx_ring->buddy) {
2914                 adapter->rx_ring->buddy->total_bytes = 0;
2915                 adapter->rx_ring->buddy->total_packets = 0;
2916         }
2917
2918         if (new_itr != adapter->itr) {
2919                 /* this attempts to bias the interrupt rate towards Bulk
2920                  * by adding intermediate steps when interrupt rate is
2921                  * increasing */
2922                 new_itr = new_itr > adapter->itr ?
2923                              min(adapter->itr + (new_itr >> 2), new_itr) :
2924                              new_itr;
2925                 /* Don't write the value here; it resets the adapter's
2926                  * internal timer, and causes us to delay far longer than
2927                  * we should between interrupts.  Instead, we write the ITR
2928                  * value at the beginning of the next interrupt so the timing
2929                  * ends up being correct.
2930                  */
2931                 adapter->itr = new_itr;
2932                 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2933                 adapter->rx_ring->set_itr = 1;
2934         }
2935
2936         return;
2937 }
2938
2939
2940 #define IGB_TX_FLAGS_CSUM               0x00000001
2941 #define IGB_TX_FLAGS_VLAN               0x00000002
2942 #define IGB_TX_FLAGS_TSO                0x00000004
2943 #define IGB_TX_FLAGS_IPV4               0x00000008
2944 #define IGB_TX_FLAGS_TSTAMP             0x00000010
2945 #define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
2946 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2947
2948 static inline int igb_tso_adv(struct igb_adapter *adapter,
2949                               struct igb_ring *tx_ring,
2950                               struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2951 {
2952         struct e1000_adv_tx_context_desc *context_desc;
2953         unsigned int i;
2954         int err;
2955         struct igb_buffer *buffer_info;
2956         u32 info = 0, tu_cmd = 0;
2957         u32 mss_l4len_idx, l4len;
2958         *hdr_len = 0;
2959
2960         if (skb_header_cloned(skb)) {
2961                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2962                 if (err)
2963                         return err;
2964         }
2965
2966         l4len = tcp_hdrlen(skb);
2967         *hdr_len += l4len;
2968
2969         if (skb->protocol == htons(ETH_P_IP)) {
2970                 struct iphdr *iph = ip_hdr(skb);
2971                 iph->tot_len = 0;
2972                 iph->check = 0;
2973                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2974                                                          iph->daddr, 0,
2975                                                          IPPROTO_TCP,
2976                                                          0);
2977         } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2978                 ipv6_hdr(skb)->payload_len = 0;
2979                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2980                                                        &ipv6_hdr(skb)->daddr,
2981                                                        0, IPPROTO_TCP, 0);
2982         }
2983
2984         i = tx_ring->next_to_use;
2985
2986         buffer_info = &tx_ring->buffer_info[i];
2987         context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2988         /* VLAN MACLEN IPLEN */
2989         if (tx_flags & IGB_TX_FLAGS_VLAN)
2990                 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2991         info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2992         *hdr_len += skb_network_offset(skb);
2993         info |= skb_network_header_len(skb);
2994         *hdr_len += skb_network_header_len(skb);
2995         context_desc->vlan_macip_lens = cpu_to_le32(info);
2996
2997         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2998         tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2999
3000         if (skb->protocol == htons(ETH_P_IP))
3001                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3002         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3003
3004         context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3005
3006         /* MSS L4LEN IDX */
3007         mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3008         mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3009
3010         /* For 82575, context index must be unique per ring. */
3011         if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3012                 mss_l4len_idx |= tx_ring->queue_index << 4;
3013
3014         context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3015         context_desc->seqnum_seed = 0;
3016
3017         buffer_info->time_stamp = jiffies;
3018         buffer_info->next_to_watch = i;
3019         buffer_info->dma = 0;
3020         i++;
3021         if (i == tx_ring->count)
3022                 i = 0;
3023
3024         tx_ring->next_to_use = i;
3025
3026         return true;
3027 }
3028
3029 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3030                                         struct igb_ring *tx_ring,
3031                                         struct sk_buff *skb, u32 tx_flags)
3032 {
3033         struct e1000_adv_tx_context_desc *context_desc;
3034         unsigned int i;
3035         struct igb_buffer *buffer_info;
3036         u32 info = 0, tu_cmd = 0;
3037
3038         if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3039             (tx_flags & IGB_TX_FLAGS_VLAN)) {
3040                 i = tx_ring->next_to_use;
3041                 buffer_info = &tx_ring->buffer_info[i];
3042                 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3043
3044                 if (tx_flags & IGB_TX_FLAGS_VLAN)
3045                         info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3046                 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3047                 if (skb->ip_summed == CHECKSUM_PARTIAL)
3048                         info |= skb_network_header_len(skb);
3049
3050                 context_desc->vlan_macip_lens = cpu_to_le32(info);
3051
3052                 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3053
3054                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3055                         __be16 protocol;
3056
3057                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3058                                 const struct vlan_ethhdr *vhdr =
3059                                           (const struct vlan_ethhdr*)skb->data;
3060
3061                                 protocol = vhdr->h_vlan_encapsulated_proto;
3062                         } else {
3063                                 protocol = skb->protocol;
3064                         }
3065
3066                         switch (protocol) {
3067                         case cpu_to_be16(ETH_P_IP):
3068                                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3069                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3070                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3071                                 break;
3072                         case cpu_to_be16(ETH_P_IPV6):
3073                                 /* XXX what about other V6 headers?? */
3074                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3075                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3076                                 break;
3077                         default:
3078                                 if (unlikely(net_ratelimit()))
3079                                         dev_warn(&adapter->pdev->dev,
3080                                             "partial checksum but proto=%x!\n",
3081                                             skb->protocol);
3082                                 break;
3083                         }
3084                 }
3085
3086                 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3087                 context_desc->seqnum_seed = 0;
3088                 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3089                         context_desc->mss_l4len_idx =
3090                                 cpu_to_le32(tx_ring->queue_index << 4);
3091                 else
3092                         context_desc->mss_l4len_idx = 0;
3093
3094                 buffer_info->time_stamp = jiffies;
3095                 buffer_info->next_to_watch = i;
3096                 buffer_info->dma = 0;
3097
3098                 i++;
3099                 if (i == tx_ring->count)
3100                         i = 0;
3101                 tx_ring->next_to_use = i;
3102
3103                 return true;
3104         }
3105         return false;
3106 }
3107
3108 #define IGB_MAX_TXD_PWR 16
3109 #define IGB_MAX_DATA_PER_TXD    (1<<IGB_MAX_TXD_PWR)
3110
3111 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
3112                                  struct igb_ring *tx_ring, struct sk_buff *skb,
3113                                  unsigned int first)
3114 {
3115         struct igb_buffer *buffer_info;
3116         unsigned int len = skb_headlen(skb);
3117         unsigned int count = 0, i;
3118         unsigned int f;
3119         dma_addr_t *map;
3120
3121         i = tx_ring->next_to_use;
3122
3123         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3124                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3125                 return 0;
3126         }
3127
3128         map = skb_shinfo(skb)->dma_maps;
3129
3130         buffer_info = &tx_ring->buffer_info[i];
3131         BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3132         buffer_info->length = len;
3133         /* set time_stamp *before* dma to help avoid a possible race */
3134         buffer_info->time_stamp = jiffies;
3135         buffer_info->next_to_watch = i;
3136         buffer_info->dma = map[count];
3137         count++;
3138
3139         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3140                 struct skb_frag_struct *frag;
3141
3142                 i++;
3143                 if (i == tx_ring->count)
3144                         i = 0;
3145
3146                 frag = &skb_shinfo(skb)->frags[f];
3147                 len = frag->size;
3148
3149                 buffer_info = &tx_ring->buffer_info[i];
3150                 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3151                 buffer_info->length = len;
3152                 buffer_info->time_stamp = jiffies;
3153                 buffer_info->next_to_watch = i;
3154                 buffer_info->dma = map[count];
3155                 count++;
3156         }
3157
3158         tx_ring->buffer_info[i].skb = skb;
3159         tx_ring->buffer_info[first].next_to_watch = i;
3160
3161         return count;
3162 }
3163
3164 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3165                                     struct igb_ring *tx_ring,
3166                                     int tx_flags, int count, u32 paylen,
3167                                     u8 hdr_len)
3168 {
3169         union e1000_adv_tx_desc *tx_desc = NULL;
3170         struct igb_buffer *buffer_info;
3171         u32 olinfo_status = 0, cmd_type_len;
3172         unsigned int i;
3173
3174         cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3175                         E1000_ADVTXD_DCMD_DEXT);
3176
3177         if (tx_flags & IGB_TX_FLAGS_VLAN)
3178                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3179
3180         if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3181                 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3182
3183         if (tx_flags & IGB_TX_FLAGS_TSO) {
3184                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3185
3186                 /* insert tcp checksum */
3187                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3188
3189                 /* insert ip checksum */
3190                 if (tx_flags & IGB_TX_FLAGS_IPV4)
3191                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3192
3193         } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3194                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3195         }
3196
3197         if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3198             (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3199                          IGB_TX_FLAGS_VLAN)))
3200                 olinfo_status |= tx_ring->queue_index << 4;
3201
3202         olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3203
3204         i = tx_ring->next_to_use;
3205         while (count--) {
3206                 buffer_info = &tx_ring->buffer_info[i];
3207                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3208                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3209                 tx_desc->read.cmd_type_len =
3210                         cpu_to_le32(cmd_type_len | buffer_info->length);
3211                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3212                 i++;
3213                 if (i == tx_ring->count)
3214                         i = 0;
3215         }
3216
3217         tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3218         /* Force memory writes to complete before letting h/w
3219          * know there are new descriptors to fetch.  (Only
3220          * applicable for weak-ordered memory model archs,
3221          * such as IA-64). */
3222         wmb();
3223
3224         tx_ring->next_to_use = i;
3225         writel(i, adapter->hw.hw_addr + tx_ring->tail);
3226         /* we need this if more than one processor can write to our tail
3227          * at a time, it syncronizes IO on IA64/Altix systems */
3228         mmiowb();
3229 }
3230
3231 static int __igb_maybe_stop_tx(struct net_device *netdev,
3232                                struct igb_ring *tx_ring, int size)
3233 {
3234         struct igb_adapter *adapter = netdev_priv(netdev);
3235
3236         netif_stop_subqueue(netdev, tx_ring->queue_index);
3237
3238         /* Herbert's original patch had:
3239          *  smp_mb__after_netif_stop_queue();
3240          * but since that doesn't exist yet, just open code it. */
3241         smp_mb();
3242
3243         /* We need to check again in a case another CPU has just
3244          * made room available. */
3245         if (igb_desc_unused(tx_ring) < size)
3246                 return -EBUSY;
3247
3248         /* A reprieve! */
3249         netif_wake_subqueue(netdev, tx_ring->queue_index);
3250         ++adapter->restart_queue;
3251         return 0;
3252 }
3253
3254 static int igb_maybe_stop_tx(struct net_device *netdev,
3255                              struct igb_ring *tx_ring, int size)
3256 {
3257         if (igb_desc_unused(tx_ring) >= size)
3258                 return 0;
3259         return __igb_maybe_stop_tx(netdev, tx_ring, size);
3260 }
3261
3262 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3263                                    struct net_device *netdev,
3264                                    struct igb_ring *tx_ring)
3265 {
3266         struct igb_adapter *adapter = netdev_priv(netdev);
3267         unsigned int first;
3268         unsigned int tx_flags = 0;
3269         u8 hdr_len = 0;
3270         int count = 0;
3271         int tso = 0;
3272         union skb_shared_tx *shtx;
3273
3274         if (test_bit(__IGB_DOWN, &adapter->state)) {
3275                 dev_kfree_skb_any(skb);
3276                 return NETDEV_TX_OK;
3277         }
3278
3279         if (skb->len <= 0) {
3280                 dev_kfree_skb_any(skb);
3281                 return NETDEV_TX_OK;
3282         }
3283
3284         /* need: 1 descriptor per page,
3285          *       + 2 desc gap to keep tail from touching head,
3286          *       + 1 desc for skb->data,
3287          *       + 1 desc for context descriptor,
3288          * otherwise try next time */
3289         if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3290                 /* this is a hard error */
3291                 return NETDEV_TX_BUSY;
3292         }
3293
3294         /*
3295          * TODO: check that there currently is no other packet with
3296          * time stamping in the queue
3297          *
3298          * When doing time stamping, keep the connection to the socket
3299          * a while longer: it is still needed by skb_hwtstamp_tx(),
3300          * called either in igb_tx_hwtstamp() or by our caller when
3301          * doing software time stamping.
3302          */
3303         shtx = skb_tx(skb);
3304         if (unlikely(shtx->hardware)) {
3305                 shtx->in_progress = 1;
3306                 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3307         }
3308
3309         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3310                 tx_flags |= IGB_TX_FLAGS_VLAN;
3311                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3312         }
3313
3314         if (skb->protocol == htons(ETH_P_IP))
3315                 tx_flags |= IGB_TX_FLAGS_IPV4;
3316
3317         first = tx_ring->next_to_use;
3318         tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3319                                               &hdr_len) : 0;
3320
3321         if (tso < 0) {
3322                 dev_kfree_skb_any(skb);
3323                 return NETDEV_TX_OK;
3324         }
3325
3326         if (tso)
3327                 tx_flags |= IGB_TX_FLAGS_TSO;
3328         else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3329                  (skb->ip_summed == CHECKSUM_PARTIAL))
3330                 tx_flags |= IGB_TX_FLAGS_CSUM;
3331
3332         /*
3333          * count reflects descriptors mapped, if 0 then mapping error
3334          * has occured and we need to rewind the descriptor queue
3335          */
3336         count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3337
3338         if (count) {
3339                 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3340                                  skb->len, hdr_len);
3341                 netdev->trans_start = jiffies;
3342                 /* Make sure there is space in the ring for the next send. */
3343                 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3344         } else {
3345                 dev_kfree_skb_any(skb);
3346                 tx_ring->buffer_info[first].time_stamp = 0;
3347                 tx_ring->next_to_use = first;
3348         }
3349
3350         return NETDEV_TX_OK;
3351 }
3352
3353 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3354 {
3355         struct igb_adapter *adapter = netdev_priv(netdev);
3356         struct igb_ring *tx_ring;
3357
3358         int r_idx = 0;
3359         r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
3360         tx_ring = adapter->multi_tx_table[r_idx];
3361
3362         /* This goes back to the question of how to logically map a tx queue
3363          * to a flow.  Right now, performance is impacted slightly negatively
3364          * if using multiple tx queues.  If the stack breaks away from a
3365          * single qdisc implementation, we can look at this again. */
3366         return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3367 }
3368
3369 /**
3370  * igb_tx_timeout - Respond to a Tx Hang
3371  * @netdev: network interface device structure
3372  **/
3373 static void igb_tx_timeout(struct net_device *netdev)
3374 {
3375         struct igb_adapter *adapter = netdev_priv(netdev);
3376         struct e1000_hw *hw = &adapter->hw;
3377
3378         /* Do the reset outside of interrupt context */
3379         adapter->tx_timeout_count++;
3380         schedule_work(&adapter->reset_task);
3381         wr32(E1000_EICS,
3382              (adapter->eims_enable_mask & ~adapter->eims_other));
3383 }
3384
3385 static void igb_reset_task(struct work_struct *work)
3386 {
3387         struct igb_adapter *adapter;
3388         adapter = container_of(work, struct igb_adapter, reset_task);
3389
3390         igb_reinit_locked(adapter);
3391 }
3392
3393 /**
3394  * igb_get_stats - Get System Network Statistics
3395  * @netdev: network interface device structure
3396  *
3397  * Returns the address of the device statistics structure.
3398  * The statistics are actually updated from the timer callback.
3399  **/
3400 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3401 {
3402         struct igb_adapter *adapter = netdev_priv(netdev);
3403
3404         /* only return the current stats */
3405         return &adapter->net_stats;
3406 }
3407
3408 /**
3409  * igb_change_mtu - Change the Maximum Transfer Unit
3410  * @netdev: network interface device structure
3411  * @new_mtu: new value for maximum frame size
3412  *
3413  * Returns 0 on success, negative on failure
3414  **/
3415 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3416 {
3417         struct igb_adapter *adapter = netdev_priv(netdev);
3418         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3419
3420         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3421             (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3422                 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3423                 return -EINVAL;
3424         }
3425
3426         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3427                 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3428                 return -EINVAL;
3429         }
3430
3431         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3432                 msleep(1);
3433
3434         /* igb_down has a dependency on max_frame_size */
3435         adapter->max_frame_size = max_frame;
3436         if (netif_running(netdev))
3437                 igb_down(adapter);
3438
3439         /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3440          * means we reserve 2 more, this pushes us to allocate from the next
3441          * larger slab size.
3442          * i.e. RXBUFFER_2048 --> size-4096 slab
3443          */
3444
3445         if (max_frame <= IGB_RXBUFFER_256)
3446                 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3447         else if (max_frame <= IGB_RXBUFFER_512)
3448                 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3449         else if (max_frame <= IGB_RXBUFFER_1024)
3450                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3451         else if (max_frame <= IGB_RXBUFFER_2048)
3452                 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3453         else
3454 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3455                 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3456 #else
3457                 adapter->rx_buffer_len = PAGE_SIZE / 2;
3458 #endif
3459
3460         /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3461         if (adapter->vfs_allocated_count &&
3462             (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3463                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3464
3465         /* adjust allocation if LPE protects us, and we aren't using SBP */
3466         if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3467              (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3468                 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3469
3470         dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3471                  netdev->mtu, new_mtu);
3472         netdev->mtu = new_mtu;
3473
3474         if (netif_running(netdev))
3475                 igb_up(adapter);
3476         else
3477                 igb_reset(adapter);
3478
3479         clear_bit(__IGB_RESETTING, &adapter->state);
3480
3481         return 0;
3482 }
3483
3484 /**
3485  * igb_update_stats - Update the board statistics counters
3486  * @adapter: board private structure
3487  **/
3488
3489 void igb_update_stats(struct igb_adapter *adapter)
3490 {
3491         struct e1000_hw *hw = &adapter->hw;
3492         struct pci_dev *pdev = adapter->pdev;
3493         u16 phy_tmp;
3494
3495 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3496
3497         /*
3498          * Prevent stats update while adapter is being reset, or if the pci
3499          * connection is down.
3500          */
3501         if (adapter->link_speed == 0)
3502                 return;
3503         if (pci_channel_offline(pdev))
3504                 return;
3505
3506         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3507         adapter->stats.gprc += rd32(E1000_GPRC);
3508         adapter->stats.gorc += rd32(E1000_GORCL);
3509         rd32(E1000_GORCH); /* clear GORCL */
3510         adapter->stats.bprc += rd32(E1000_BPRC);
3511         adapter->stats.mprc += rd32(E1000_MPRC);
3512         adapter->stats.roc += rd32(E1000_ROC);
3513
3514         adapter->stats.prc64 += rd32(E1000_PRC64);
3515         adapter->stats.prc127 += rd32(E1000_PRC127);
3516         adapter->stats.prc255 += rd32(E1000_PRC255);
3517         adapter->stats.prc511 += rd32(E1000_PRC511);
3518         adapter->stats.prc1023 += rd32(E1000_PRC1023);
3519         adapter->stats.prc1522 += rd32(E1000_PRC1522);
3520         adapter->stats.symerrs += rd32(E1000_SYMERRS);
3521         adapter->stats.sec += rd32(E1000_SEC);
3522
3523         adapter->stats.mpc += rd32(E1000_MPC);
3524         adapter->stats.scc += rd32(E1000_SCC);
3525         adapter->stats.ecol += rd32(E1000_ECOL);
3526         adapter->stats.mcc += rd32(E1000_MCC);
3527         adapter->stats.latecol += rd32(E1000_LATECOL);
3528         adapter->stats.dc += rd32(E1000_DC);
3529         adapter->stats.rlec += rd32(E1000_RLEC);
3530         adapter->stats.xonrxc += rd32(E1000_XONRXC);
3531         adapter->stats.xontxc += rd32(E1000_XONTXC);
3532         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3533         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3534         adapter->stats.fcruc += rd32(E1000_FCRUC);
3535         adapter->stats.gptc += rd32(E1000_GPTC);
3536         adapter->stats.gotc += rd32(E1000_GOTCL);
3537         rd32(E1000_GOTCH); /* clear GOTCL */
3538         adapter->stats.rnbc += rd32(E1000_RNBC);
3539         adapter->stats.ruc += rd32(E1000_RUC);
3540         adapter->stats.rfc += rd32(E1000_RFC);
3541         adapter->stats.rjc += rd32(E1000_RJC);
3542         adapter->stats.tor += rd32(E1000_TORH);
3543         adapter->stats.tot += rd32(E1000_TOTH);
3544         adapter->stats.tpr += rd32(E1000_TPR);
3545
3546         adapter->stats.ptc64 += rd32(E1000_PTC64);
3547         adapter->stats.ptc127 += rd32(E1000_PTC127);
3548         adapter->stats.ptc255 += rd32(E1000_PTC255);
3549         adapter->stats.ptc511 += rd32(E1000_PTC511);
3550         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3551         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3552
3553         adapter->stats.mptc += rd32(E1000_MPTC);
3554         adapter->stats.bptc += rd32(E1000_BPTC);
3555
3556         /* used for adaptive IFS */
3557
3558         hw->mac.tx_packet_delta = rd32(E1000_TPT);
3559         adapter->stats.tpt += hw->mac.tx_packet_delta;
3560         hw->mac.collision_delta = rd32(E1000_COLC);
3561         adapter->stats.colc += hw->mac.collision_delta;
3562
3563         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3564         adapter->stats.rxerrc += rd32(E1000_RXERRC);
3565         adapter->stats.tncrs += rd32(E1000_TNCRS);
3566         adapter->stats.tsctc += rd32(E1000_TSCTC);
3567         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3568
3569         adapter->stats.iac += rd32(E1000_IAC);
3570         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3571         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3572         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3573         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3574         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3575         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3576         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3577         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3578
3579         /* Fill out the OS statistics structure */
3580         adapter->net_stats.multicast = adapter->stats.mprc;
3581         adapter->net_stats.collisions = adapter->stats.colc;
3582
3583         /* Rx Errors */
3584
3585         /* RLEC on some newer hardware can be incorrect so build
3586         * our own version based on RUC and ROC */
3587         adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3588                 adapter->stats.crcerrs + adapter->stats.algnerrc +
3589                 adapter->stats.ruc + adapter->stats.roc +
3590                 adapter->stats.cexterr;
3591         adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3592                                               adapter->stats.roc;
3593         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3594         adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3595         adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3596
3597         /* Tx Errors */
3598         adapter->net_stats.tx_errors = adapter->stats.ecol +
3599                                        adapter->stats.latecol;
3600         adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3601         adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3602         adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3603
3604         /* Tx Dropped needs to be maintained elsewhere */
3605
3606         /* Phy Stats */
3607         if (hw->phy.media_type == e1000_media_type_copper) {
3608                 if ((adapter->link_speed == SPEED_1000) &&
3609                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3610                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3611                         adapter->phy_stats.idle_errors += phy_tmp;
3612                 }
3613         }
3614
3615         /* Management Stats */
3616         adapter->stats.mgptc += rd32(E1000_MGTPTC);
3617         adapter->stats.mgprc += rd32(E1000_MGTPRC);
3618         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3619 }
3620
3621 static irqreturn_t igb_msix_other(int irq, void *data)
3622 {
3623         struct net_device *netdev = data;
3624         struct igb_adapter *adapter = netdev_priv(netdev);
3625         struct e1000_hw *hw = &adapter->hw;
3626         u32 icr = rd32(E1000_ICR);
3627
3628         /* reading ICR causes bit 31 of EICR to be cleared */
3629
3630         if(icr & E1000_ICR_DOUTSYNC) {
3631                 /* HW is reporting DMA is out of sync */
3632                 adapter->stats.doosync++;
3633         }
3634
3635         /* Check for a mailbox event */
3636         if (icr & E1000_ICR_VMMB)
3637                 igb_msg_task(adapter);
3638
3639         if (icr & E1000_ICR_LSC) {
3640                 hw->mac.get_link_status = 1;
3641                 /* guard against interrupt when we're going down */
3642                 if (!test_bit(__IGB_DOWN, &adapter->state))
3643                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3644         }
3645
3646         wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
3647         wr32(E1000_EIMS, adapter->eims_other);
3648
3649         return IRQ_HANDLED;
3650 }
3651
3652 static irqreturn_t igb_msix_tx(int irq, void *data)
3653 {
3654         struct igb_ring *tx_ring = data;
3655         struct igb_adapter *adapter = tx_ring->adapter;
3656         struct e1000_hw *hw = &adapter->hw;
3657
3658 #ifdef CONFIG_IGB_DCA
3659         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3660                 igb_update_tx_dca(tx_ring);
3661 #endif
3662
3663         tx_ring->total_bytes = 0;
3664         tx_ring->total_packets = 0;
3665
3666         /* auto mask will automatically reenable the interrupt when we write
3667          * EICS */
3668         if (!igb_clean_tx_irq(tx_ring))
3669                 /* Ring was not completely cleaned, so fire another interrupt */
3670                 wr32(E1000_EICS, tx_ring->eims_value);
3671         else
3672                 wr32(E1000_EIMS, tx_ring->eims_value);
3673
3674         return IRQ_HANDLED;
3675 }
3676
3677 static void igb_write_itr(struct igb_ring *ring)
3678 {
3679         struct e1000_hw *hw = &ring->adapter->hw;
3680         if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3681                 switch (hw->mac.type) {
3682                 case e1000_82576:
3683                         wr32(ring->itr_register, ring->itr_val |
3684                              0x80000000);
3685                         break;
3686                 default:
3687                         wr32(ring->itr_register, ring->itr_val |
3688                              (ring->itr_val << 16));
3689                         break;
3690                 }
3691                 ring->set_itr = 0;
3692         }
3693 }
3694
3695 static irqreturn_t igb_msix_rx(int irq, void *data)
3696 {
3697         struct igb_ring *rx_ring = data;
3698
3699         /* Write the ITR value calculated at the end of the
3700          * previous interrupt.
3701          */
3702
3703         igb_write_itr(rx_ring);
3704
3705         if (napi_schedule_prep(&rx_ring->napi))
3706                 __napi_schedule(&rx_ring->napi);
3707
3708 #ifdef CONFIG_IGB_DCA
3709         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3710                 igb_update_rx_dca(rx_ring);
3711 #endif
3712                 return IRQ_HANDLED;
3713 }
3714
3715 #ifdef CONFIG_IGB_DCA
3716 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3717 {
3718         u32 dca_rxctrl;
3719         struct igb_adapter *adapter = rx_ring->adapter;
3720         struct e1000_hw *hw = &adapter->hw;
3721         int cpu = get_cpu();
3722         int q = rx_ring->reg_idx;
3723
3724         if (rx_ring->cpu != cpu) {
3725                 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3726                 if (hw->mac.type == e1000_82576) {
3727                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3728                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3729                                       E1000_DCA_RXCTRL_CPUID_SHIFT;
3730                 } else {
3731                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3732                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3733                 }
3734                 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3735                 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3736                 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3737                 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3738                 rx_ring->cpu = cpu;
3739         }
3740         put_cpu();
3741 }
3742
3743 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3744 {
3745         u32 dca_txctrl;
3746         struct igb_adapter *adapter = tx_ring->adapter;
3747         struct e1000_hw *hw = &adapter->hw;
3748         int cpu = get_cpu();
3749         int q = tx_ring->reg_idx;
3750
3751         if (tx_ring->cpu != cpu) {
3752                 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3753                 if (hw->mac.type == e1000_82576) {
3754                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3755                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3756                                       E1000_DCA_TXCTRL_CPUID_SHIFT;
3757                 } else {
3758                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3759                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3760                 }
3761                 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3762                 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3763                 tx_ring->cpu = cpu;
3764         }
3765         put_cpu();
3766 }
3767
3768 static void igb_setup_dca(struct igb_adapter *adapter)
3769 {
3770         int i;
3771
3772         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3773                 return;
3774
3775         for (i = 0; i < adapter->num_tx_queues; i++) {
3776                 adapter->tx_ring[i].cpu = -1;
3777                 igb_update_tx_dca(&adapter->tx_ring[i]);
3778         }
3779         for (i = 0; i < adapter->num_rx_queues; i++) {
3780                 adapter->rx_ring[i].cpu = -1;
3781                 igb_update_rx_dca(&adapter->rx_ring[i]);
3782         }
3783 }
3784
3785 static int __igb_notify_dca(struct device *dev, void *data)
3786 {
3787         struct net_device *netdev = dev_get_drvdata(dev);
3788         struct igb_adapter *adapter = netdev_priv(netdev);
3789         struct e1000_hw *hw = &adapter->hw;
3790         unsigned long event = *(unsigned long *)data;
3791
3792         switch (event) {
3793         case DCA_PROVIDER_ADD:
3794                 /* if already enabled, don't do it again */
3795                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3796                         break;
3797                 /* Always use CB2 mode, difference is masked
3798                  * in the CB driver. */
3799                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3800                 if (dca_add_requester(dev) == 0) {
3801                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
3802                         dev_info(&adapter->pdev->dev, "DCA enabled\n");
3803                         igb_setup_dca(adapter);
3804                         break;
3805                 }
3806                 /* Fall Through since DCA is disabled. */
3807         case DCA_PROVIDER_REMOVE:
3808                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3809                         /* without this a class_device is left
3810                          * hanging around in the sysfs model */
3811                         dca_remove_requester(dev);
3812                         dev_info(&adapter->pdev->dev, "DCA disabled\n");
3813                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3814                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3815                 }
3816                 break;
3817         }
3818
3819         return 0;
3820 }
3821
3822 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3823                           void *p)
3824 {
3825         int ret_val;
3826
3827         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3828                                          __igb_notify_dca);
3829
3830         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3831 }
3832 #endif /* CONFIG_IGB_DCA */
3833
3834 static void igb_ping_all_vfs(struct igb_adapter *adapter)
3835 {
3836         struct e1000_hw *hw = &adapter->hw;
3837         u32 ping;
3838         int i;
3839
3840         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3841                 ping = E1000_PF_CONTROL_MSG;
3842                 if (adapter->vf_data[i].clear_to_send)
3843                         ping |= E1000_VT_MSGTYPE_CTS;
3844                 igb_write_mbx(hw, &ping, 1, i);
3845         }
3846 }
3847
3848 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3849                                   u32 *msgbuf, u32 vf)
3850 {
3851         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3852         u16 *hash_list = (u16 *)&msgbuf[1];
3853         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3854         int i;
3855
3856         /* only up to 30 hash values supported */
3857         if (n > 30)
3858                 n = 30;
3859
3860         /* salt away the number of multi cast addresses assigned
3861          * to this VF for later use to restore when the PF multi cast
3862          * list changes
3863          */
3864         vf_data->num_vf_mc_hashes = n;
3865
3866         /* VFs are limited to using the MTA hash table for their multicast
3867          * addresses */
3868         for (i = 0; i < n; i++)
3869                 vf_data->vf_mc_hashes[i] = hash_list[i];;
3870
3871         /* Flush and reset the mta with the new values */
3872         igb_set_multi(adapter->netdev);
3873
3874         return 0;
3875 }
3876
3877 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3878 {
3879         struct e1000_hw *hw = &adapter->hw;
3880         struct vf_data_storage *vf_data;
3881         int i, j;
3882
3883         for (i = 0; i < adapter->vfs_allocated_count; i++) {
3884                 vf_data = &adapter->vf_data[i];
3885                 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
3886                         igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3887         }
3888 }
3889
3890 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3891 {
3892         struct e1000_hw *hw = &adapter->hw;
3893         u32 pool_mask, reg, vid;
3894         int i;
3895
3896         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3897
3898         /* Find the vlan filter for this id */
3899         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3900                 reg = rd32(E1000_VLVF(i));
3901
3902                 /* remove the vf from the pool */
3903                 reg &= ~pool_mask;
3904
3905                 /* if pool is empty then remove entry from vfta */
3906                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3907                     (reg & E1000_VLVF_VLANID_ENABLE)) {
3908                         reg = 0;
3909                         vid = reg & E1000_VLVF_VLANID_MASK;
3910                         igb_vfta_set(hw, vid, false);
3911                 }
3912
3913                 wr32(E1000_VLVF(i), reg);
3914         }
3915 }
3916
3917 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
3918 {
3919         struct e1000_hw *hw = &adapter->hw;
3920         u32 reg, i;
3921
3922         /* It is an error to call this function when VFs are not enabled */
3923         if (!adapter->vfs_allocated_count)
3924                 return -1;
3925
3926         /* Find the vlan filter for this id */
3927         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3928                 reg = rd32(E1000_VLVF(i));
3929                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
3930                     vid == (reg & E1000_VLVF_VLANID_MASK))
3931                         break;
3932         }
3933
3934         if (add) {
3935                 if (i == E1000_VLVF_ARRAY_SIZE) {
3936                         /* Did not find a matching VLAN ID entry that was
3937                          * enabled.  Search for a free filter entry, i.e.
3938                          * one without the enable bit set
3939                          */
3940                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3941                                 reg = rd32(E1000_VLVF(i));
3942                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
3943                                         break;
3944                         }
3945                 }
3946                 if (i < E1000_VLVF_ARRAY_SIZE) {
3947                         /* Found an enabled/available entry */
3948                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3949
3950                         /* if !enabled we need to set this up in vfta */
3951                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
3952                                 /* add VID to filter table, if bit already set
3953                                  * PF must have added it outside of table */
3954                                 if (igb_vfta_set(hw, vid, true))
3955                                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
3956                                                 adapter->vfs_allocated_count);
3957                                 reg |= E1000_VLVF_VLANID_ENABLE;
3958                         }
3959                         reg &= ~E1000_VLVF_VLANID_MASK;
3960                         reg |= vid;
3961
3962                         wr32(E1000_VLVF(i), reg);
3963                         return 0;
3964                 }
3965         } else {
3966                 if (i < E1000_VLVF_ARRAY_SIZE) {
3967                         /* remove vf from the pool */
3968                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
3969                         /* if pool is empty then remove entry from vfta */
3970                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
3971                                 reg = 0;
3972                                 igb_vfta_set(hw, vid, false);
3973                         }
3974                         wr32(E1000_VLVF(i), reg);
3975                         return 0;
3976                 }
3977         }
3978         return -1;
3979 }
3980
3981 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
3982 {
3983         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3984         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
3985
3986         return igb_vlvf_set(adapter, vid, add, vf);
3987 }
3988
3989 static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
3990 {
3991         struct e1000_hw *hw = &adapter->hw;
3992
3993         /* disable mailbox functionality for vf */
3994         adapter->vf_data[vf].clear_to_send = false;
3995
3996         /* reset offloads to defaults */
3997         igb_set_vmolr(hw, vf);
3998
3999         /* reset vlans for device */
4000         igb_clear_vf_vfta(adapter, vf);
4001
4002         /* reset multicast table array for vf */
4003         adapter->vf_data[vf].num_vf_mc_hashes = 0;
4004
4005         /* Flush and reset the mta with the new values */
4006         igb_set_multi(adapter->netdev);
4007 }
4008
4009 static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4010 {
4011         struct e1000_hw *hw = &adapter->hw;
4012         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4013         u32 reg, msgbuf[3];
4014         u8 *addr = (u8 *)(&msgbuf[1]);
4015
4016         /* process all the same items cleared in a function level reset */
4017         igb_vf_reset_event(adapter, vf);
4018
4019         /* set vf mac address */
4020         igb_rar_set(hw, vf_mac, vf + 1);
4021         igb_set_rah_pool(hw, vf, vf + 1);
4022
4023         /* enable transmit and receive for vf */
4024         reg = rd32(E1000_VFTE);
4025         wr32(E1000_VFTE, reg | (1 << vf));
4026         reg = rd32(E1000_VFRE);
4027         wr32(E1000_VFRE, reg | (1 << vf));
4028
4029         /* enable mailbox functionality for vf */
4030         adapter->vf_data[vf].clear_to_send = true;
4031
4032         /* reply to reset with ack and vf mac address */
4033         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4034         memcpy(addr, vf_mac, 6);
4035         igb_write_mbx(hw, msgbuf, 3, vf);
4036 }
4037
4038 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4039 {
4040                 unsigned char *addr = (char *)&msg[1];
4041                 int err = -1;
4042
4043                 if (is_valid_ether_addr(addr))
4044                         err = igb_set_vf_mac(adapter, vf, addr);
4045
4046                 return err;
4047
4048 }
4049
4050 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4051 {
4052         struct e1000_hw *hw = &adapter->hw;
4053         u32 msg = E1000_VT_MSGTYPE_NACK;
4054
4055         /* if device isn't clear to send it shouldn't be reading either */
4056         if (!adapter->vf_data[vf].clear_to_send)
4057                 igb_write_mbx(hw, &msg, 1, vf);
4058 }
4059
4060
4061 static void igb_msg_task(struct igb_adapter *adapter)
4062 {
4063         struct e1000_hw *hw = &adapter->hw;
4064         u32 vf;
4065
4066         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4067                 /* process any reset requests */
4068                 if (!igb_check_for_rst(hw, vf)) {
4069                         adapter->vf_data[vf].clear_to_send = false;
4070                         igb_vf_reset_event(adapter, vf);
4071                 }
4072
4073                 /* process any messages pending */
4074                 if (!igb_check_for_msg(hw, vf))
4075                         igb_rcv_msg_from_vf(adapter, vf);
4076
4077                 /* process any acks */
4078                 if (!igb_check_for_ack(hw, vf))
4079                         igb_rcv_ack_from_vf(adapter, vf);
4080
4081         }
4082 }
4083
4084 static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4085 {
4086         u32 mbx_size = E1000_VFMAILBOX_SIZE;
4087         u32 msgbuf[mbx_size];
4088         struct e1000_hw *hw = &adapter->hw;
4089         s32 retval;
4090
4091         retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4092
4093         if (retval)
4094                 dev_err(&adapter->pdev->dev,
4095                         "Error receiving message from VF\n");
4096
4097         /* this is a message we already processed, do nothing */
4098         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4099                 return retval;
4100
4101         /*
4102          * until the vf completes a reset it should not be
4103          * allowed to start any configuration.
4104          */
4105
4106         if (msgbuf[0] == E1000_VF_RESET) {
4107                 igb_vf_reset_msg(adapter, vf);
4108
4109                 return retval;
4110         }
4111
4112         if (!adapter->vf_data[vf].clear_to_send) {
4113                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4114                 igb_write_mbx(hw, msgbuf, 1, vf);
4115                 return retval;
4116         }
4117
4118         switch ((msgbuf[0] & 0xFFFF)) {
4119         case E1000_VF_SET_MAC_ADDR:
4120                 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4121                 break;
4122         case E1000_VF_SET_MULTICAST:
4123                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4124                 break;
4125         case E1000_VF_SET_LPE:
4126                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4127                 break;
4128         case E1000_VF_SET_VLAN:
4129                 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4130                 break;
4131         default:
4132                 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4133                 retval = -1;
4134                 break;
4135         }
4136
4137         /* notify the VF of the results of what it sent us */
4138         if (retval)
4139                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4140         else
4141                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4142
4143         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4144
4145         igb_write_mbx(hw, msgbuf, 1, vf);
4146
4147         return retval;
4148 }
4149
4150 /**
4151  * igb_intr_msi - Interrupt Handler
4152  * @irq: interrupt number
4153  * @data: pointer to a network interface device structure
4154  **/
4155 static irqreturn_t igb_intr_msi(int irq, void *data)
4156 {
4157         struct net_device *netdev = data;
4158         struct igb_adapter *adapter = netdev_priv(netdev);
4159         struct e1000_hw *hw = &adapter->hw;
4160         /* read ICR disables interrupts using IAM */
4161         u32 icr = rd32(E1000_ICR);
4162
4163         igb_write_itr(adapter->rx_ring);
4164
4165         if(icr & E1000_ICR_DOUTSYNC) {
4166                 /* HW is reporting DMA is out of sync */
4167                 adapter->stats.doosync++;
4168         }
4169
4170         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4171                 hw->mac.get_link_status = 1;
4172                 if (!test_bit(__IGB_DOWN, &adapter->state))
4173                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4174         }
4175
4176         napi_schedule(&adapter->rx_ring[0].napi);
4177
4178         return IRQ_HANDLED;
4179 }
4180
4181 /**
4182  * igb_intr - Legacy Interrupt Handler
4183  * @irq: interrupt number
4184  * @data: pointer to a network interface device structure
4185  **/
4186 static irqreturn_t igb_intr(int irq, void *data)
4187 {
4188         struct net_device *netdev = data;
4189         struct igb_adapter *adapter = netdev_priv(netdev);
4190         struct e1000_hw *hw = &adapter->hw;
4191         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
4192          * need for the IMC write */
4193         u32 icr = rd32(E1000_ICR);
4194         if (!icr)
4195                 return IRQ_NONE;  /* Not our interrupt */
4196
4197         igb_write_itr(adapter->rx_ring);
4198
4199         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4200          * not set, then the adapter didn't send an interrupt */
4201         if (!(icr & E1000_ICR_INT_ASSERTED))
4202                 return IRQ_NONE;
4203
4204         if(icr & E1000_ICR_DOUTSYNC) {
4205                 /* HW is reporting DMA is out of sync */
4206                 adapter->stats.doosync++;
4207         }
4208
4209         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4210                 hw->mac.get_link_status = 1;
4211                 /* guard against interrupt when we're going down */
4212                 if (!test_bit(__IGB_DOWN, &adapter->state))
4213                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4214         }
4215
4216         napi_schedule(&adapter->rx_ring[0].napi);
4217
4218         return IRQ_HANDLED;
4219 }
4220
4221 static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
4222 {
4223         struct igb_adapter *adapter = rx_ring->adapter;
4224         struct e1000_hw *hw = &adapter->hw;
4225
4226         if (adapter->itr_setting & 3) {
4227                 if (adapter->num_rx_queues == 1)
4228                         igb_set_itr(adapter);
4229                 else
4230                         igb_update_ring_itr(rx_ring);
4231         }
4232
4233         if (!test_bit(__IGB_DOWN, &adapter->state)) {
4234                 if (adapter->msix_entries)
4235                         wr32(E1000_EIMS, rx_ring->eims_value);
4236                 else
4237                         igb_irq_enable(adapter);
4238         }
4239 }
4240
4241 /**
4242  * igb_poll - NAPI Rx polling callback
4243  * @napi: napi polling structure
4244  * @budget: count of how many packets we should handle
4245  **/
4246 static int igb_poll(struct napi_struct *napi, int budget)
4247 {
4248         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
4249         int work_done = 0;
4250
4251 #ifdef CONFIG_IGB_DCA
4252         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4253                 igb_update_rx_dca(rx_ring);
4254 #endif
4255         igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
4256
4257         if (rx_ring->buddy) {
4258 #ifdef CONFIG_IGB_DCA
4259                 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4260                         igb_update_tx_dca(rx_ring->buddy);
4261 #endif
4262                 if (!igb_clean_tx_irq(rx_ring->buddy))
4263                         work_done = budget;
4264         }
4265
4266         /* If not enough Rx work done, exit the polling mode */
4267         if (work_done < budget) {
4268                 napi_complete(napi);
4269                 igb_rx_irq_enable(rx_ring);
4270         }
4271
4272         return work_done;
4273 }
4274
4275 /**
4276  * igb_hwtstamp - utility function which checks for TX time stamp
4277  * @adapter: board private structure
4278  * @skb: packet that was just sent
4279  *
4280  * If we were asked to do hardware stamping and such a time stamp is
4281  * available, then it must have been for this skb here because we only
4282  * allow only one such packet into the queue.
4283  */
4284 static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4285 {
4286         union skb_shared_tx *shtx = skb_tx(skb);
4287         struct e1000_hw *hw = &adapter->hw;
4288
4289         if (unlikely(shtx->hardware)) {
4290                 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4291                 if (valid) {
4292                         u64 regval = rd32(E1000_TXSTMPL);
4293                         u64 ns;
4294                         struct skb_shared_hwtstamps shhwtstamps;
4295
4296                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4297                         regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4298                         ns = timecounter_cyc2time(&adapter->clock,
4299                                                   regval);
4300                         timecompare_update(&adapter->compare, ns);
4301                         shhwtstamps.hwtstamp = ns_to_ktime(ns);
4302                         shhwtstamps.syststamp =
4303                                 timecompare_transform(&adapter->compare, ns);
4304                         skb_tstamp_tx(skb, &shhwtstamps);
4305                 }
4306         }
4307 }
4308
4309 /**
4310  * igb_clean_tx_irq - Reclaim resources after transmit completes
4311  * @adapter: board private structure
4312  * returns true if ring is completely cleaned
4313  **/
4314 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
4315 {
4316         struct igb_adapter *adapter = tx_ring->adapter;
4317         struct net_device *netdev = adapter->netdev;
4318         struct e1000_hw *hw = &adapter->hw;
4319         struct igb_buffer *buffer_info;
4320         struct sk_buff *skb;
4321         union e1000_adv_tx_desc *tx_desc, *eop_desc;
4322         unsigned int total_bytes = 0, total_packets = 0;
4323         unsigned int i, eop, count = 0;
4324         bool cleaned = false;
4325
4326         i = tx_ring->next_to_clean;
4327         eop = tx_ring->buffer_info[i].next_to_watch;
4328         eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4329
4330         while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4331                (count < tx_ring->count)) {
4332                 for (cleaned = false; !cleaned; count++) {
4333                         tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4334                         buffer_info = &tx_ring->buffer_info[i];
4335                         cleaned = (i == eop);
4336                         skb = buffer_info->skb;
4337
4338                         if (skb) {
4339                                 unsigned int segs, bytecount;
4340                                 /* gso_segs is currently only valid for tcp */
4341                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
4342                                 /* multiply data chunks by size of headers */
4343                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
4344                                             skb->len;
4345                                 total_packets += segs;
4346                                 total_bytes += bytecount;
4347
4348                                 igb_tx_hwtstamp(adapter, skb);
4349                         }
4350
4351                         igb_unmap_and_free_tx_resource(adapter, buffer_info);
4352                         tx_desc->wb.status = 0;
4353
4354                         i++;
4355                         if (i == tx_ring->count)
4356                                 i = 0;
4357                 }
4358                 eop = tx_ring->buffer_info[i].next_to_watch;
4359                 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4360         }
4361
4362         tx_ring->next_to_clean = i;
4363
4364         if (unlikely(count &&
4365                      netif_carrier_ok(netdev) &&
4366                      igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4367                 /* Make sure that anybody stopping the queue after this
4368                  * sees the new next_to_clean.
4369                  */
4370                 smp_mb();
4371                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4372                     !(test_bit(__IGB_DOWN, &adapter->state))) {
4373                         netif_wake_subqueue(netdev, tx_ring->queue_index);
4374                         ++adapter->restart_queue;
4375                 }
4376         }
4377
4378         if (tx_ring->detect_tx_hung) {
4379                 /* Detect a transmit hang in hardware, this serializes the
4380                  * check with the clearing of time_stamp and movement of i */
4381                 tx_ring->detect_tx_hung = false;
4382                 if (tx_ring->buffer_info[i].time_stamp &&
4383                     time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4384                                (adapter->tx_timeout_factor * HZ))
4385                     && !(rd32(E1000_STATUS) &
4386                          E1000_STATUS_TXOFF)) {
4387
4388                         /* detected Tx unit hang */
4389                         dev_err(&adapter->pdev->dev,
4390                                 "Detected Tx Unit Hang\n"
4391                                 "  Tx Queue             <%d>\n"
4392                                 "  TDH                  <%x>\n"
4393                                 "  TDT                  <%x>\n"
4394                                 "  next_to_use          <%x>\n"
4395                                 "  next_to_clean        <%x>\n"
4396                                 "buffer_info[next_to_clean]\n"
4397                                 "  time_stamp           <%lx>\n"
4398                                 "  next_to_watch        <%x>\n"
4399                                 "  jiffies              <%lx>\n"
4400                                 "  desc.status          <%x>\n",
4401                                 tx_ring->queue_index,
4402                                 readl(adapter->hw.hw_addr + tx_ring->head),
4403                                 readl(adapter->hw.hw_addr + tx_ring->tail),
4404                                 tx_ring->next_to_use,
4405                                 tx_ring->next_to_clean,
4406                                 tx_ring->buffer_info[i].time_stamp,
4407                                 eop,
4408                                 jiffies,
4409                                 eop_desc->wb.status);
4410                         netif_stop_subqueue(netdev, tx_ring->queue_index);
4411                 }
4412         }
4413         tx_ring->total_bytes += total_bytes;
4414         tx_ring->total_packets += total_packets;
4415         tx_ring->tx_stats.bytes += total_bytes;
4416         tx_ring->tx_stats.packets += total_packets;
4417         adapter->net_stats.tx_bytes += total_bytes;
4418         adapter->net_stats.tx_packets += total_packets;
4419         return (count < tx_ring->count);
4420 }
4421
4422 /**
4423  * igb_receive_skb - helper function to handle rx indications
4424  * @ring: pointer to receive ring receving this packet
4425  * @status: descriptor status field as written by hardware
4426  * @rx_desc: receive descriptor containing vlan and type information.
4427  * @skb: pointer to sk_buff to be indicated to stack
4428  **/
4429 static void igb_receive_skb(struct igb_ring *ring, u8 status,
4430                             union e1000_adv_rx_desc * rx_desc,
4431                             struct sk_buff *skb)
4432 {
4433         struct igb_adapter * adapter = ring->adapter;
4434         bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4435
4436         skb_record_rx_queue(skb, ring->queue_index);
4437         if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
4438                 if (vlan_extracted)
4439                         vlan_gro_receive(&ring->napi, adapter->vlgrp,
4440                                          le16_to_cpu(rx_desc->wb.upper.vlan),
4441                                          skb);
4442                 else
4443                         napi_gro_receive(&ring->napi, skb);
4444         } else {
4445                 if (vlan_extracted)
4446                         vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
4447                                           le16_to_cpu(rx_desc->wb.upper.vlan));
4448                 else
4449                         netif_receive_skb(skb);
4450         }
4451 }
4452
4453 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4454                                        u32 status_err, struct sk_buff *skb)
4455 {
4456         skb->ip_summed = CHECKSUM_NONE;
4457
4458         /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4459         if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
4460                 return;
4461         /* TCP/UDP checksum error bit is set */
4462         if (status_err &
4463             (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4464                 /* let the stack verify checksum errors */
4465                 adapter->hw_csum_err++;
4466                 return;
4467         }
4468         /* It must be a TCP or UDP packet with a valid checksum */
4469         if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4470                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4471
4472         adapter->hw_csum_good++;
4473 }
4474
4475 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4476                                  int *work_done, int budget)
4477 {
4478         struct igb_adapter *adapter = rx_ring->adapter;
4479         struct net_device *netdev = adapter->netdev;
4480         struct e1000_hw *hw = &adapter->hw;
4481         struct pci_dev *pdev = adapter->pdev;
4482         union e1000_adv_rx_desc *rx_desc , *next_rxd;
4483         struct igb_buffer *buffer_info , *next_buffer;
4484         struct sk_buff *skb;
4485         bool cleaned = false;
4486         int cleaned_count = 0;
4487         unsigned int total_bytes = 0, total_packets = 0;
4488         unsigned int i;
4489         u32 length, hlen, staterr;
4490
4491         i = rx_ring->next_to_clean;
4492         buffer_info = &rx_ring->buffer_info[i];
4493         rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4494         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4495
4496         while (staterr & E1000_RXD_STAT_DD) {
4497                 if (*work_done >= budget)
4498                         break;
4499                 (*work_done)++;
4500
4501                 skb = buffer_info->skb;
4502                 prefetch(skb->data - NET_IP_ALIGN);
4503                 buffer_info->skb = NULL;
4504
4505                 i++;
4506                 if (i == rx_ring->count)
4507                         i = 0;
4508                 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4509                 prefetch(next_rxd);
4510                 next_buffer = &rx_ring->buffer_info[i];
4511
4512                 length = le16_to_cpu(rx_desc->wb.upper.length);
4513                 cleaned = true;
4514                 cleaned_count++;
4515
4516                 if (!adapter->rx_ps_hdr_size) {
4517                         pci_unmap_single(pdev, buffer_info->dma,
4518                                          adapter->rx_buffer_len +
4519                                            NET_IP_ALIGN,
4520                                          PCI_DMA_FROMDEVICE);
4521                         skb_put(skb, length);
4522                         goto send_up;
4523                 }
4524
4525                 /* HW will not DMA in data larger than the given buffer, even
4526                  * if it parses the (NFS, of course) header to be larger.  In
4527                  * that case, it fills the header buffer and spills the rest
4528                  * into the page.
4529                  */
4530                 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4531                   E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4532                 if (hlen > adapter->rx_ps_hdr_size)
4533                         hlen = adapter->rx_ps_hdr_size;
4534
4535                 if (!skb_shinfo(skb)->nr_frags) {
4536                         pci_unmap_single(pdev, buffer_info->dma,
4537                                          adapter->rx_ps_hdr_size + NET_IP_ALIGN,
4538                                          PCI_DMA_FROMDEVICE);
4539                         skb_put(skb, hlen);
4540                 }
4541
4542                 if (length) {
4543                         pci_unmap_page(pdev, buffer_info->page_dma,
4544                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
4545                         buffer_info->page_dma = 0;
4546
4547                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4548                                                 buffer_info->page,
4549                                                 buffer_info->page_offset,
4550                                                 length);
4551
4552                         if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4553                             (page_count(buffer_info->page) != 1))
4554                                 buffer_info->page = NULL;
4555                         else
4556                                 get_page(buffer_info->page);
4557
4558                         skb->len += length;
4559                         skb->data_len += length;
4560
4561                         skb->truesize += length;
4562                 }
4563
4564                 if (!(staterr & E1000_RXD_STAT_EOP)) {
4565                         buffer_info->skb = next_buffer->skb;
4566                         buffer_info->dma = next_buffer->dma;
4567                         next_buffer->skb = skb;
4568                         next_buffer->dma = 0;
4569                         goto next_desc;
4570                 }
4571 send_up:
4572                 /*
4573                  * If this bit is set, then the RX registers contain
4574                  * the time stamp. No other packet will be time
4575                  * stamped until we read these registers, so read the
4576                  * registers to make them available again. Because
4577                  * only one packet can be time stamped at a time, we
4578                  * know that the register values must belong to this
4579                  * one here and therefore we don't need to compare
4580                  * any of the additional attributes stored for it.
4581                  *
4582                  * If nothing went wrong, then it should have a
4583                  * skb_shared_tx that we can turn into a
4584                  * skb_shared_hwtstamps.
4585                  *
4586                  * TODO: can time stamping be triggered (thus locking
4587                  * the registers) without the packet reaching this point
4588                  * here? In that case RX time stamping would get stuck.
4589                  *
4590                  * TODO: in "time stamp all packets" mode this bit is
4591                  * not set. Need a global flag for this mode and then
4592                  * always read the registers. Cannot be done without
4593                  * a race condition.
4594                  */
4595                 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4596                         u64 regval;
4597                         u64 ns;
4598                         struct skb_shared_hwtstamps *shhwtstamps =
4599                                 skb_hwtstamps(skb);
4600
4601                         WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4602                              "igb: no RX time stamp available for time stamped packet");
4603                         regval = rd32(E1000_RXSTMPL);
4604                         regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4605                         ns = timecounter_cyc2time(&adapter->clock, regval);
4606                         timecompare_update(&adapter->compare, ns);
4607                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4608                         shhwtstamps->hwtstamp = ns_to_ktime(ns);
4609                         shhwtstamps->syststamp =
4610                                 timecompare_transform(&adapter->compare, ns);
4611                 }
4612
4613                 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4614                         dev_kfree_skb_irq(skb);
4615                         goto next_desc;
4616                 }
4617
4618                 total_bytes += skb->len;
4619                 total_packets++;
4620
4621                 igb_rx_checksum_adv(adapter, staterr, skb);
4622
4623                 skb->protocol = eth_type_trans(skb, netdev);
4624
4625                 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
4626
4627 next_desc:
4628                 rx_desc->wb.upper.status_error = 0;
4629
4630                 /* return some buffers to hardware, one at a time is too slow */
4631                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
4632                         igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4633                         cleaned_count = 0;
4634                 }
4635
4636                 /* use prefetched values */
4637                 rx_desc = next_rxd;
4638                 buffer_info = next_buffer;
4639                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4640         }
4641
4642         rx_ring->next_to_clean = i;
4643         cleaned_count = igb_desc_unused(rx_ring);
4644
4645         if (cleaned_count)
4646                 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4647
4648         rx_ring->total_packets += total_packets;
4649         rx_ring->total_bytes += total_bytes;
4650         rx_ring->rx_stats.packets += total_packets;
4651         rx_ring->rx_stats.bytes += total_bytes;
4652         adapter->net_stats.rx_bytes += total_bytes;
4653         adapter->net_stats.rx_packets += total_packets;
4654         return cleaned;
4655 }
4656
4657 /**
4658  * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4659  * @adapter: address of board private structure
4660  **/
4661 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4662                                      int cleaned_count)
4663 {
4664         struct igb_adapter *adapter = rx_ring->adapter;
4665         struct net_device *netdev = adapter->netdev;
4666         struct pci_dev *pdev = adapter->pdev;
4667         union e1000_adv_rx_desc *rx_desc;
4668         struct igb_buffer *buffer_info;
4669         struct sk_buff *skb;
4670         unsigned int i;
4671         int bufsz;
4672
4673         i = rx_ring->next_to_use;
4674         buffer_info = &rx_ring->buffer_info[i];
4675
4676         if (adapter->rx_ps_hdr_size)
4677                 bufsz = adapter->rx_ps_hdr_size;
4678         else
4679                 bufsz = adapter->rx_buffer_len;
4680         bufsz += NET_IP_ALIGN;
4681
4682         while (cleaned_count--) {
4683                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4684
4685                 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4686                         if (!buffer_info->page) {
4687                                 buffer_info->page = alloc_page(GFP_ATOMIC);
4688                                 if (!buffer_info->page) {
4689                                         adapter->alloc_rx_buff_failed++;
4690                                         goto no_buffers;
4691                                 }
4692                                 buffer_info->page_offset = 0;
4693                         } else {
4694                                 buffer_info->page_offset ^= PAGE_SIZE / 2;
4695                         }
4696                         buffer_info->page_dma =
4697                                 pci_map_page(pdev, buffer_info->page,
4698                                              buffer_info->page_offset,
4699                                              PAGE_SIZE / 2,
4700                                              PCI_DMA_FROMDEVICE);
4701                 }
4702
4703                 if (!buffer_info->skb) {
4704                         skb = netdev_alloc_skb(netdev, bufsz);
4705                         if (!skb) {
4706                                 adapter->alloc_rx_buff_failed++;
4707                                 goto no_buffers;
4708                         }
4709
4710                         /* Make buffer alignment 2 beyond a 16 byte boundary
4711                          * this will result in a 16 byte aligned IP header after
4712                          * the 14 byte MAC header is removed
4713                          */
4714                         skb_reserve(skb, NET_IP_ALIGN);
4715
4716                         buffer_info->skb = skb;
4717                         buffer_info->dma = pci_map_single(pdev, skb->data,
4718                                                           bufsz,
4719                                                           PCI_DMA_FROMDEVICE);
4720                 }
4721                 /* Refresh the desc even if buffer_addrs didn't change because
4722                  * each write-back erases this info. */
4723                 if (adapter->rx_ps_hdr_size) {
4724                         rx_desc->read.pkt_addr =
4725                              cpu_to_le64(buffer_info->page_dma);
4726                         rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4727                 } else {
4728                         rx_desc->read.pkt_addr =
4729                              cpu_to_le64(buffer_info->dma);
4730                         rx_desc->read.hdr_addr = 0;
4731                 }
4732
4733                 i++;
4734                 if (i == rx_ring->count)
4735                         i = 0;
4736                 buffer_info = &rx_ring->buffer_info[i];
4737         }
4738
4739 no_buffers:
4740         if (rx_ring->next_to_use != i) {
4741                 rx_ring->next_to_use = i;
4742                 if (i == 0)
4743                         i = (rx_ring->count - 1);
4744                 else
4745                         i--;
4746
4747                 /* Force memory writes to complete before letting h/w
4748                  * know there are new descriptors to fetch.  (Only
4749                  * applicable for weak-ordered memory model archs,
4750                  * such as IA-64). */
4751                 wmb();
4752                 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4753         }
4754 }
4755
4756 /**
4757  * igb_mii_ioctl -
4758  * @netdev:
4759  * @ifreq:
4760  * @cmd:
4761  **/
4762 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4763 {
4764         struct igb_adapter *adapter = netdev_priv(netdev);
4765         struct mii_ioctl_data *data = if_mii(ifr);
4766
4767         if (adapter->hw.phy.media_type != e1000_media_type_copper)
4768                 return -EOPNOTSUPP;
4769
4770         switch (cmd) {
4771         case SIOCGMIIPHY:
4772                 data->phy_id = adapter->hw.phy.addr;
4773                 break;
4774         case SIOCGMIIREG:
4775                 if (!capable(CAP_NET_ADMIN))
4776                         return -EPERM;
4777                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4778                                      &data->val_out))
4779                         return -EIO;
4780                 break;
4781         case SIOCSMIIREG:
4782         default:
4783                 return -EOPNOTSUPP;
4784         }
4785         return 0;
4786 }
4787
4788 /**
4789  * igb_hwtstamp_ioctl - control hardware time stamping
4790  * @netdev:
4791  * @ifreq:
4792  * @cmd:
4793  *
4794  * Outgoing time stamping can be enabled and disabled. Play nice and
4795  * disable it when requested, although it shouldn't case any overhead
4796  * when no packet needs it. At most one packet in the queue may be
4797  * marked for time stamping, otherwise it would be impossible to tell
4798  * for sure to which packet the hardware time stamp belongs.
4799  *
4800  * Incoming time stamping has to be configured via the hardware
4801  * filters. Not all combinations are supported, in particular event
4802  * type has to be specified. Matching the kind of event packet is
4803  * not supported, with the exception of "all V2 events regardless of
4804  * level 2 or 4".
4805  *
4806  **/
4807 static int igb_hwtstamp_ioctl(struct net_device *netdev,
4808                               struct ifreq *ifr, int cmd)
4809 {
4810         struct igb_adapter *adapter = netdev_priv(netdev);
4811         struct e1000_hw *hw = &adapter->hw;
4812         struct hwtstamp_config config;
4813         u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4814         u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4815         u32 tsync_rx_ctl_type = 0;
4816         u32 tsync_rx_cfg = 0;
4817         int is_l4 = 0;
4818         int is_l2 = 0;
4819         short port = 319; /* PTP */
4820         u32 regval;
4821
4822         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4823                 return -EFAULT;
4824
4825         /* reserved for future extensions */
4826         if (config.flags)
4827                 return -EINVAL;
4828
4829         switch (config.tx_type) {
4830         case HWTSTAMP_TX_OFF:
4831                 tsync_tx_ctl_bit = 0;
4832                 break;
4833         case HWTSTAMP_TX_ON:
4834                 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4835                 break;
4836         default:
4837                 return -ERANGE;
4838         }
4839
4840         switch (config.rx_filter) {
4841         case HWTSTAMP_FILTER_NONE:
4842                 tsync_rx_ctl_bit = 0;
4843                 break;
4844         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4845         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4846         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4847         case HWTSTAMP_FILTER_ALL:
4848                 /*
4849                  * register TSYNCRXCFG must be set, therefore it is not
4850                  * possible to time stamp both Sync and Delay_Req messages
4851                  * => fall back to time stamping all packets
4852                  */
4853                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4854                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4855                 break;
4856         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4857                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4858                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4859                 is_l4 = 1;
4860                 break;
4861         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4862                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4863                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4864                 is_l4 = 1;
4865                 break;
4866         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4867         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4868                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4869                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4870                 is_l2 = 1;
4871                 is_l4 = 1;
4872                 config.rx_filter = HWTSTAMP_FILTER_SOME;
4873                 break;
4874         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4875         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4876                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4877                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4878                 is_l2 = 1;
4879                 is_l4 = 1;
4880                 config.rx_filter = HWTSTAMP_FILTER_SOME;
4881                 break;
4882         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4883         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4884         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4885                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4886                 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4887                 is_l2 = 1;
4888                 break;
4889         default:
4890                 return -ERANGE;
4891         }
4892
4893         /* enable/disable TX */
4894         regval = rd32(E1000_TSYNCTXCTL);
4895         regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4896         wr32(E1000_TSYNCTXCTL, regval);
4897
4898         /* enable/disable RX, define which PTP packets are time stamped */
4899         regval = rd32(E1000_TSYNCRXCTL);
4900         regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4901         regval = (regval & ~0xE) | tsync_rx_ctl_type;
4902         wr32(E1000_TSYNCRXCTL, regval);
4903         wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4904
4905         /*
4906          * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4907          *                                          (Ethertype to filter on)
4908          * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4909          * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4910          */
4911         wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4912
4913         /* L4 Queue Filter[0]: only filter by source and destination port */
4914         wr32(E1000_SPQF0, htons(port));
4915         wr32(E1000_IMIREXT(0), is_l4 ?
4916              ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4917         wr32(E1000_IMIR(0), is_l4 ?
4918              (htons(port)
4919               | (0<<16) /* immediate interrupt disabled */
4920               | 0 /* (1<<17) bit cleared: do not bypass
4921                      destination port check */)
4922                 : 0);
4923         wr32(E1000_FTQF0, is_l4 ?
4924              (0x11 /* UDP */
4925               | (1<<15) /* VF not compared */
4926               | (1<<27) /* Enable Timestamping */
4927               | (7<<28) /* only source port filter enabled,
4928                            source/target address and protocol
4929                            masked */)
4930              : ((1<<15) | (15<<28) /* all mask bits set = filter not
4931                                       enabled */));
4932
4933         wrfl();
4934
4935         adapter->hwtstamp_config = config;
4936
4937         /* clear TX/RX time stamp registers, just to be sure */
4938         regval = rd32(E1000_TXSTMPH);
4939         regval = rd32(E1000_RXSTMPH);
4940
4941         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
4942                 -EFAULT : 0;
4943 }
4944
4945 /**
4946  * igb_ioctl -
4947  * @netdev:
4948  * @ifreq:
4949  * @cmd:
4950  **/
4951 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4952 {
4953         switch (cmd) {
4954         case SIOCGMIIPHY:
4955         case SIOCGMIIREG:
4956         case SIOCSMIIREG:
4957                 return igb_mii_ioctl(netdev, ifr, cmd);
4958         case SIOCSHWTSTAMP:
4959                 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
4960         default:
4961                 return -EOPNOTSUPP;
4962         }
4963 }
4964
4965 static void igb_vlan_rx_register(struct net_device *netdev,
4966                                  struct vlan_group *grp)
4967 {
4968         struct igb_adapter *adapter = netdev_priv(netdev);
4969         struct e1000_hw *hw = &adapter->hw;
4970         u32 ctrl, rctl;
4971
4972         igb_irq_disable(adapter);
4973         adapter->vlgrp = grp;
4974
4975         if (grp) {
4976                 /* enable VLAN tag insert/strip */
4977                 ctrl = rd32(E1000_CTRL);
4978                 ctrl |= E1000_CTRL_VME;
4979                 wr32(E1000_CTRL, ctrl);
4980
4981                 /* enable VLAN receive filtering */
4982                 rctl = rd32(E1000_RCTL);
4983                 rctl &= ~E1000_RCTL_CFIEN;
4984                 wr32(E1000_RCTL, rctl);
4985                 igb_update_mng_vlan(adapter);
4986         } else {
4987                 /* disable VLAN tag insert/strip */
4988                 ctrl = rd32(E1000_CTRL);
4989                 ctrl &= ~E1000_CTRL_VME;
4990                 wr32(E1000_CTRL, ctrl);
4991
4992                 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4993                         igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4994                         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4995                 }
4996         }
4997
4998         igb_rlpml_set(adapter);
4999
5000         if (!test_bit(__IGB_DOWN, &adapter->state))
5001                 igb_irq_enable(adapter);
5002 }
5003
5004 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5005 {
5006         struct igb_adapter *adapter = netdev_priv(netdev);
5007         struct e1000_hw *hw = &adapter->hw;
5008         int pf_id = adapter->vfs_allocated_count;
5009
5010         if ((hw->mng_cookie.status &
5011              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5012             (vid == adapter->mng_vlan_id))
5013                 return;
5014
5015         /* add vid to vlvf if sr-iov is enabled,
5016          * if that fails add directly to filter table */
5017         if (igb_vlvf_set(adapter, vid, true, pf_id))
5018                 igb_vfta_set(hw, vid, true);
5019
5020 }
5021
5022 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5023 {
5024         struct igb_adapter *adapter = netdev_priv(netdev);
5025         struct e1000_hw *hw = &adapter->hw;
5026         int pf_id = adapter->vfs_allocated_count;
5027
5028         igb_irq_disable(adapter);
5029         vlan_group_set_device(adapter->vlgrp, vid, NULL);
5030
5031         if (!test_bit(__IGB_DOWN, &adapter->state))
5032                 igb_irq_enable(adapter);
5033
5034         if ((adapter->hw.mng_cookie.status &
5035              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5036             (vid == adapter->mng_vlan_id)) {
5037                 /* release control to f/w */
5038                 igb_release_hw_control(adapter);
5039                 return;
5040         }
5041
5042         /* remove vid from vlvf if sr-iov is enabled,
5043          * if not in vlvf remove from vfta */
5044         if (igb_vlvf_set(adapter, vid, false, pf_id))
5045                 igb_vfta_set(hw, vid, false);
5046 }
5047
5048 static void igb_restore_vlan(struct igb_adapter *adapter)
5049 {
5050         igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5051
5052         if (adapter->vlgrp) {
5053                 u16 vid;
5054                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5055                         if (!vlan_group_get_device(adapter->vlgrp, vid))
5056                                 continue;
5057                         igb_vlan_rx_add_vid(adapter->netdev, vid);
5058                 }
5059         }
5060 }
5061
5062 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5063 {
5064         struct e1000_mac_info *mac = &adapter->hw.mac;
5065
5066         mac->autoneg = 0;
5067
5068         /* Fiber NICs only allow 1000 gbps Full duplex */
5069         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
5070                 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5071                 dev_err(&adapter->pdev->dev,
5072                         "Unsupported Speed/Duplex configuration\n");
5073                 return -EINVAL;
5074         }
5075
5076         switch (spddplx) {
5077         case SPEED_10 + DUPLEX_HALF:
5078                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5079                 break;
5080         case SPEED_10 + DUPLEX_FULL:
5081                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5082                 break;
5083         case SPEED_100 + DUPLEX_HALF:
5084                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5085                 break;
5086         case SPEED_100 + DUPLEX_FULL:
5087                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5088                 break;
5089         case SPEED_1000 + DUPLEX_FULL:
5090                 mac->autoneg = 1;
5091                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5092                 break;
5093         case SPEED_1000 + DUPLEX_HALF: /* not supported */
5094         default:
5095                 dev_err(&adapter->pdev->dev,
5096                         "Unsupported Speed/Duplex configuration\n");
5097                 return -EINVAL;
5098         }
5099         return 0;
5100 }
5101
5102 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
5103 {
5104         struct net_device *netdev = pci_get_drvdata(pdev);
5105         struct igb_adapter *adapter = netdev_priv(netdev);
5106         struct e1000_hw *hw = &adapter->hw;
5107         u32 ctrl, rctl, status;
5108         u32 wufc = adapter->wol;
5109 #ifdef CONFIG_PM
5110         int retval = 0;
5111 #endif
5112
5113         netif_device_detach(netdev);
5114
5115         if (netif_running(netdev))
5116                 igb_close(netdev);
5117
5118         igb_reset_interrupt_capability(adapter);
5119
5120         igb_free_queues(adapter);
5121
5122 #ifdef CONFIG_PM
5123         retval = pci_save_state(pdev);
5124         if (retval)
5125                 return retval;
5126 #endif
5127
5128         status = rd32(E1000_STATUS);
5129         if (status & E1000_STATUS_LU)
5130                 wufc &= ~E1000_WUFC_LNKC;
5131
5132         if (wufc) {
5133                 igb_setup_rctl(adapter);
5134                 igb_set_multi(netdev);
5135
5136                 /* turn on all-multi mode if wake on multicast is enabled */
5137                 if (wufc & E1000_WUFC_MC) {
5138                         rctl = rd32(E1000_RCTL);
5139                         rctl |= E1000_RCTL_MPE;
5140                         wr32(E1000_RCTL, rctl);
5141                 }
5142
5143                 ctrl = rd32(E1000_CTRL);
5144                 /* advertise wake from D3Cold */
5145                 #define E1000_CTRL_ADVD3WUC 0x00100000
5146                 /* phy power management enable */
5147                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5148                 ctrl |= E1000_CTRL_ADVD3WUC;
5149                 wr32(E1000_CTRL, ctrl);
5150
5151                 /* Allow time for pending master requests to run */
5152                 igb_disable_pcie_master(&adapter->hw);
5153
5154                 wr32(E1000_WUC, E1000_WUC_PME_EN);
5155                 wr32(E1000_WUFC, wufc);
5156         } else {
5157                 wr32(E1000_WUC, 0);
5158                 wr32(E1000_WUFC, 0);
5159         }
5160
5161         *enable_wake = wufc || adapter->en_mng_pt;
5162         if (!*enable_wake)
5163                 igb_shutdown_fiber_serdes_link_82575(hw);
5164
5165         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
5166          * would have already happened in close and is redundant. */
5167         igb_release_hw_control(adapter);
5168
5169         pci_disable_device(pdev);
5170
5171         return 0;
5172 }
5173
5174 #ifdef CONFIG_PM
5175 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5176 {
5177         int retval;
5178         bool wake;
5179
5180         retval = __igb_shutdown(pdev, &wake);
5181         if (retval)
5182                 return retval;
5183
5184         if (wake) {
5185                 pci_prepare_to_sleep(pdev);
5186         } else {
5187                 pci_wake_from_d3(pdev, false);
5188                 pci_set_power_state(pdev, PCI_D3hot);
5189         }
5190
5191         return 0;
5192 }
5193
5194 static int igb_resume(struct pci_dev *pdev)
5195 {
5196         struct net_device *netdev = pci_get_drvdata(pdev);
5197         struct igb_adapter *adapter = netdev_priv(netdev);
5198         struct e1000_hw *hw = &adapter->hw;
5199         u32 err;
5200
5201         pci_set_power_state(pdev, PCI_D0);
5202         pci_restore_state(pdev);
5203
5204         err = pci_enable_device_mem(pdev);
5205         if (err) {
5206                 dev_err(&pdev->dev,
5207                         "igb: Cannot enable PCI device from suspend\n");
5208                 return err;
5209         }
5210         pci_set_master(pdev);
5211
5212         pci_enable_wake(pdev, PCI_D3hot, 0);
5213         pci_enable_wake(pdev, PCI_D3cold, 0);
5214
5215         igb_set_interrupt_capability(adapter);
5216
5217         if (igb_alloc_queues(adapter)) {
5218                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5219                 return -ENOMEM;
5220         }
5221
5222         /* e1000_power_up_phy(adapter); */
5223
5224         igb_reset(adapter);
5225
5226         /* let the f/w know that the h/w is now under the control of the
5227          * driver. */
5228         igb_get_hw_control(adapter);
5229
5230         wr32(E1000_WUS, ~0);
5231
5232         if (netif_running(netdev)) {
5233                 err = igb_open(netdev);
5234                 if (err)
5235                         return err;
5236         }
5237
5238         netif_device_attach(netdev);
5239
5240         return 0;
5241 }
5242 #endif
5243
5244 static void igb_shutdown(struct pci_dev *pdev)
5245 {
5246         bool wake;
5247
5248         __igb_shutdown(pdev, &wake);
5249
5250         if (system_state == SYSTEM_POWER_OFF) {
5251                 pci_wake_from_d3(pdev, wake);
5252                 pci_set_power_state(pdev, PCI_D3hot);
5253         }
5254 }
5255
5256 #ifdef CONFIG_NET_POLL_CONTROLLER
5257 /*
5258  * Polling 'interrupt' - used by things like netconsole to send skbs
5259  * without having to re-enable interrupts. It's not called while
5260  * the interrupt routine is executing.
5261  */
5262 static void igb_netpoll(struct net_device *netdev)
5263 {
5264         struct igb_adapter *adapter = netdev_priv(netdev);
5265         struct e1000_hw *hw = &adapter->hw;
5266         int i;
5267
5268         if (!adapter->msix_entries) {
5269                 igb_irq_disable(adapter);
5270                 napi_schedule(&adapter->rx_ring[0].napi);
5271                 return;
5272         }
5273
5274         for (i = 0; i < adapter->num_tx_queues; i++) {
5275                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5276                 wr32(E1000_EIMC, tx_ring->eims_value);
5277                 igb_clean_tx_irq(tx_ring);
5278                 wr32(E1000_EIMS, tx_ring->eims_value);
5279         }
5280
5281         for (i = 0; i < adapter->num_rx_queues; i++) {
5282                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5283                 wr32(E1000_EIMC, rx_ring->eims_value);
5284                 napi_schedule(&rx_ring->napi);
5285         }
5286 }
5287 #endif /* CONFIG_NET_POLL_CONTROLLER */
5288
5289 /**
5290  * igb_io_error_detected - called when PCI error is detected
5291  * @pdev: Pointer to PCI device
5292  * @state: The current pci connection state
5293  *
5294  * This function is called after a PCI bus error affecting
5295  * this device has been detected.
5296  */
5297 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5298                                               pci_channel_state_t state)
5299 {
5300         struct net_device *netdev = pci_get_drvdata(pdev);
5301         struct igb_adapter *adapter = netdev_priv(netdev);
5302
5303         netif_device_detach(netdev);
5304
5305         if (netif_running(netdev))
5306                 igb_down(adapter);
5307         pci_disable_device(pdev);
5308
5309         /* Request a slot slot reset. */
5310         return PCI_ERS_RESULT_NEED_RESET;
5311 }
5312
5313 /**
5314  * igb_io_slot_reset - called after the pci bus has been reset.
5315  * @pdev: Pointer to PCI device
5316  *
5317  * Restart the card from scratch, as if from a cold-boot. Implementation
5318  * resembles the first-half of the igb_resume routine.
5319  */
5320 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5321 {
5322         struct net_device *netdev = pci_get_drvdata(pdev);
5323         struct igb_adapter *adapter = netdev_priv(netdev);
5324         struct e1000_hw *hw = &adapter->hw;
5325         pci_ers_result_t result;
5326         int err;
5327
5328         if (pci_enable_device_mem(pdev)) {
5329                 dev_err(&pdev->dev,
5330                         "Cannot re-enable PCI device after reset.\n");
5331                 result = PCI_ERS_RESULT_DISCONNECT;
5332         } else {
5333                 pci_set_master(pdev);
5334                 pci_restore_state(pdev);
5335
5336                 pci_enable_wake(pdev, PCI_D3hot, 0);
5337                 pci_enable_wake(pdev, PCI_D3cold, 0);
5338
5339                 igb_reset(adapter);
5340                 wr32(E1000_WUS, ~0);
5341                 result = PCI_ERS_RESULT_RECOVERED;
5342         }
5343
5344         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5345         if (err) {
5346                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5347                         "failed 0x%0x\n", err);
5348                 /* non-fatal, continue */
5349         }
5350
5351         return result;
5352 }
5353
5354 /**
5355  * igb_io_resume - called when traffic can start flowing again.
5356  * @pdev: Pointer to PCI device
5357  *
5358  * This callback is called when the error recovery driver tells us that
5359  * its OK to resume normal operation. Implementation resembles the
5360  * second-half of the igb_resume routine.
5361  */
5362 static void igb_io_resume(struct pci_dev *pdev)
5363 {
5364         struct net_device *netdev = pci_get_drvdata(pdev);
5365         struct igb_adapter *adapter = netdev_priv(netdev);
5366
5367         if (netif_running(netdev)) {
5368                 if (igb_up(adapter)) {
5369                         dev_err(&pdev->dev, "igb_up failed after reset\n");
5370                         return;
5371                 }
5372         }
5373
5374         netif_device_attach(netdev);
5375
5376         /* let the f/w know that the h/w is now under the control of the
5377          * driver. */
5378         igb_get_hw_control(adapter);
5379 }
5380
5381 static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
5382 {
5383         u32 reg_data;
5384
5385         reg_data = rd32(E1000_VMOLR(vfn));
5386         reg_data |= E1000_VMOLR_BAM |    /* Accept broadcast */
5387                     E1000_VMOLR_ROPE |   /* Accept packets matched in UTA */
5388                     E1000_VMOLR_ROMPE |  /* Accept packets matched in MTA */
5389                     E1000_VMOLR_AUPE |   /* Accept untagged packets */
5390                     E1000_VMOLR_STRVLAN; /* Strip vlan tags */
5391         wr32(E1000_VMOLR(vfn), reg_data);
5392 }
5393
5394 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
5395                                  int vfn)
5396 {
5397         struct e1000_hw *hw = &adapter->hw;
5398         u32 vmolr;
5399
5400         vmolr = rd32(E1000_VMOLR(vfn));
5401         vmolr &= ~E1000_VMOLR_RLPML_MASK;
5402         vmolr |= size | E1000_VMOLR_LPE;
5403         wr32(E1000_VMOLR(vfn), vmolr);
5404
5405         return 0;
5406 }
5407
5408 static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
5409 {
5410         u32 reg_data;
5411
5412         reg_data = rd32(E1000_RAH(entry));
5413         reg_data &= ~E1000_RAH_POOL_MASK;
5414         reg_data |= E1000_RAH_POOL_1 << pool;;
5415         wr32(E1000_RAH(entry), reg_data);
5416 }
5417
5418 static void igb_set_mc_list_pools(struct igb_adapter *adapter,
5419                                   int entry_count, u16 total_rar_filters)
5420 {
5421         struct e1000_hw *hw = &adapter->hw;
5422         int i = adapter->vfs_allocated_count + 1;
5423
5424         if ((i + entry_count) < total_rar_filters)
5425                 total_rar_filters = i + entry_count;
5426
5427         for (; i < total_rar_filters; i++)
5428                 igb_set_rah_pool(hw, adapter->vfs_allocated_count, i);
5429 }
5430
5431 static int igb_set_vf_mac(struct igb_adapter *adapter,
5432                           int vf, unsigned char *mac_addr)
5433 {
5434         struct e1000_hw *hw = &adapter->hw;
5435         int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */
5436
5437         igb_rar_set(hw, mac_addr, rar_entry);
5438
5439         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
5440
5441         igb_set_rah_pool(hw, vf, rar_entry);
5442
5443         return 0;
5444 }
5445
5446 static void igb_vmm_control(struct igb_adapter *adapter)
5447 {
5448         struct e1000_hw *hw = &adapter->hw;
5449         u32 reg_data;
5450
5451         if (!adapter->vfs_allocated_count)
5452                 return;
5453
5454         /* VF's need PF reset indication before they
5455          * can send/receive mail */
5456         reg_data = rd32(E1000_CTRL_EXT);
5457         reg_data |= E1000_CTRL_EXT_PFRSTD;
5458         wr32(E1000_CTRL_EXT, reg_data);
5459
5460         igb_vmdq_set_loopback_pf(hw, true);
5461         igb_vmdq_set_replication_pf(hw, true);
5462 }
5463
5464 /* igb_main.c */