2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,5,6 NVIDIA Corporation
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 * 0.01: 05 Oct 2003: First release that compiles without warnings.
34 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
35 * Check all PCI BARs for the register window.
36 * udelay added to mii_rw.
37 * 0.03: 06 Oct 2003: Initialize dev->irq.
38 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
39 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
40 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
42 * 0.07: 14 Oct 2003: Further irq mask updates.
43 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
44 * added into irq handler, NULL check for drain_ring.
45 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
46 * requested interrupt sources.
47 * 0.10: 20 Oct 2003: First cleanup for release.
48 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
49 * MAC Address init fix, set_multicast cleanup.
50 * 0.12: 23 Oct 2003: Cleanups for release.
51 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
52 * Set link speed correctly. start rx before starting
53 * tx (nv_start_rx sets the link speed).
54 * 0.14: 25 Oct 2003: Nic dependant irq mask.
55 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
57 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
58 * increased to 1628 bytes.
59 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
61 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
62 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
63 * addresses, really stop rx if already running
64 * in nv_start_rx, clean up a bit.
65 * 0.20: 07 Dec 2003: alloc fixes
66 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
67 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
69 * 0.23: 26 Jan 2004: various small cleanups
70 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
71 * 0.25: 09 Mar 2004: wol support
72 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
73 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
74 * added CK804/MCP04 device IDs, code fixes
75 * for registers, link status and other minor fixes.
76 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
77 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
78 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
79 * into nv_close, otherwise reenabling for wol can
80 * cause DMA to kfree'd memory.
81 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
83 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
84 * 0.33: 16 May 2005: Support for MCP51 added.
85 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
86 * 0.35: 26 Jun 2005: Support for MCP55 added.
87 * 0.36: 28 Jun 2005: Add jumbo frame support.
88 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
89 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
91 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
92 * 0.40: 19 Jul 2005: Add support for mac address change.
93 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
95 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
96 * in the second (and later) nv_open call
97 * 0.43: 10 Aug 2005: Add support for tx checksum.
98 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
99 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
100 * 0.46: 20 Oct 2005: Add irq optimization modes.
101 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
102 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
103 * 0.49: 10 Dec 2005: Fix tso for large buffers.
104 * 0.50: 20 Jan 2006: Add 8021pq tagging support.
105 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
106 * 0.52: 20 Jan 2006: Add MSI/MSIX support.
107 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
108 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
109 * 0.55: 22 Mar 2006: Add flow control (pause frame).
110 * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
111 * 0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
112 * 0.58: 30 Oct 2006: Added support for sideband management unit.
113 * 0.59: 30 Oct 2006: Added support for recoverable error.
116 * We suspect that on some hardware no TX done interrupts are generated.
117 * This means recovery from netif_stop_queue only happens if the hw timer
118 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
119 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
120 * If your hardware reliably generates tx done interrupts, then you can remove
121 * DEV_NEED_TIMERIRQ from the driver_data flags.
122 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
123 * superfluous timer interrupts from the nic.
125 #ifdef CONFIG_FORCEDETH_NAPI
126 #define DRIVERNAPI "-NAPI"
130 #define FORCEDETH_VERSION "0.59"
131 #define DRV_NAME "forcedeth"
133 #include <linux/module.h>
134 #include <linux/types.h>
135 #include <linux/pci.h>
136 #include <linux/interrupt.h>
137 #include <linux/netdevice.h>
138 #include <linux/etherdevice.h>
139 #include <linux/delay.h>
140 #include <linux/spinlock.h>
141 #include <linux/ethtool.h>
142 #include <linux/timer.h>
143 #include <linux/skbuff.h>
144 #include <linux/mii.h>
145 #include <linux/random.h>
146 #include <linux/init.h>
147 #include <linux/if_vlan.h>
148 #include <linux/dma-mapping.h>
152 #include <asm/uaccess.h>
153 #include <asm/system.h>
156 #define dprintk printk
158 #define dprintk(x...) do { } while (0)
166 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
167 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
168 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
169 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
170 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
171 #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */
172 #define DEV_HAS_MSI 0x0040 /* device supports MSI */
173 #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
174 #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
175 #define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
176 #define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */
177 #define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */
178 #define DEV_HAS_MGMT_UNIT 0x1000 /* device supports management unit */
181 NvRegIrqStatus = 0x000,
182 #define NVREG_IRQSTAT_MIIEVENT 0x040
183 #define NVREG_IRQSTAT_MASK 0x81ff
184 NvRegIrqMask = 0x004,
185 #define NVREG_IRQ_RX_ERROR 0x0001
186 #define NVREG_IRQ_RX 0x0002
187 #define NVREG_IRQ_RX_NOBUF 0x0004
188 #define NVREG_IRQ_TX_ERR 0x0008
189 #define NVREG_IRQ_TX_OK 0x0010
190 #define NVREG_IRQ_TIMER 0x0020
191 #define NVREG_IRQ_LINK 0x0040
192 #define NVREG_IRQ_RX_FORCED 0x0080
193 #define NVREG_IRQ_TX_FORCED 0x0100
194 #define NVREG_IRQ_RECOVER_ERROR 0x8000
195 #define NVREG_IRQMASK_THROUGHPUT 0x00df
196 #define NVREG_IRQMASK_CPU 0x0040
197 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
198 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
199 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
201 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
202 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
203 NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
205 NvRegUnknownSetupReg6 = 0x008,
206 #define NVREG_UNKSETUP6_VAL 3
209 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
210 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
212 NvRegPollingInterval = 0x00c,
213 #define NVREG_POLL_DEFAULT_THROUGHPUT 970 /* backup tx cleanup if loop max reached */
214 #define NVREG_POLL_DEFAULT_CPU 13
215 NvRegMSIMap0 = 0x020,
216 NvRegMSIMap1 = 0x024,
217 NvRegMSIIrqMask = 0x030,
218 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
220 #define NVREG_MISC1_PAUSE_TX 0x01
221 #define NVREG_MISC1_HD 0x02
222 #define NVREG_MISC1_FORCE 0x3b0f3c
224 NvRegMacReset = 0x3c,
225 #define NVREG_MAC_RESET_ASSERT 0x0F3
226 NvRegTransmitterControl = 0x084,
227 #define NVREG_XMITCTL_START 0x01
228 #define NVREG_XMITCTL_MGMT_ST 0x40000000
229 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
230 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
231 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
232 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
233 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
234 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
235 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
236 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
237 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
238 NvRegTransmitterStatus = 0x088,
239 #define NVREG_XMITSTAT_BUSY 0x01
241 NvRegPacketFilterFlags = 0x8c,
242 #define NVREG_PFF_PAUSE_RX 0x08
243 #define NVREG_PFF_ALWAYS 0x7F0000
244 #define NVREG_PFF_PROMISC 0x80
245 #define NVREG_PFF_MYADDR 0x20
246 #define NVREG_PFF_LOOPBACK 0x10
248 NvRegOffloadConfig = 0x90,
249 #define NVREG_OFFLOAD_HOMEPHY 0x601
250 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
251 NvRegReceiverControl = 0x094,
252 #define NVREG_RCVCTL_START 0x01
253 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
254 NvRegReceiverStatus = 0x98,
255 #define NVREG_RCVSTAT_BUSY 0x01
257 NvRegRandomSeed = 0x9c,
258 #define NVREG_RNDSEED_MASK 0x00ff
259 #define NVREG_RNDSEED_FORCE 0x7f00
260 #define NVREG_RNDSEED_FORCE2 0x2d00
261 #define NVREG_RNDSEED_FORCE3 0x7400
263 NvRegTxDeferral = 0xA0,
264 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
265 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
266 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
267 NvRegRxDeferral = 0xA4,
268 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
269 NvRegMacAddrA = 0xA8,
270 NvRegMacAddrB = 0xAC,
271 NvRegMulticastAddrA = 0xB0,
272 #define NVREG_MCASTADDRA_FORCE 0x01
273 NvRegMulticastAddrB = 0xB4,
274 NvRegMulticastMaskA = 0xB8,
275 NvRegMulticastMaskB = 0xBC,
277 NvRegPhyInterface = 0xC0,
278 #define PHY_RGMII 0x10000000
280 NvRegTxRingPhysAddr = 0x100,
281 NvRegRxRingPhysAddr = 0x104,
282 NvRegRingSizes = 0x108,
283 #define NVREG_RINGSZ_TXSHIFT 0
284 #define NVREG_RINGSZ_RXSHIFT 16
285 NvRegTransmitPoll = 0x10c,
286 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
287 NvRegLinkSpeed = 0x110,
288 #define NVREG_LINKSPEED_FORCE 0x10000
289 #define NVREG_LINKSPEED_10 1000
290 #define NVREG_LINKSPEED_100 100
291 #define NVREG_LINKSPEED_1000 50
292 #define NVREG_LINKSPEED_MASK (0xFFF)
293 NvRegUnknownSetupReg5 = 0x130,
294 #define NVREG_UNKSETUP5_BIT31 (1<<31)
295 NvRegTxWatermark = 0x13c,
296 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
297 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
298 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
299 NvRegTxRxControl = 0x144,
300 #define NVREG_TXRXCTL_KICK 0x0001
301 #define NVREG_TXRXCTL_BIT1 0x0002
302 #define NVREG_TXRXCTL_BIT2 0x0004
303 #define NVREG_TXRXCTL_IDLE 0x0008
304 #define NVREG_TXRXCTL_RESET 0x0010
305 #define NVREG_TXRXCTL_RXCHECK 0x0400
306 #define NVREG_TXRXCTL_DESC_1 0
307 #define NVREG_TXRXCTL_DESC_2 0x002100
308 #define NVREG_TXRXCTL_DESC_3 0xc02200
309 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
310 #define NVREG_TXRXCTL_VLANINS 0x00080
311 NvRegTxRingPhysAddrHigh = 0x148,
312 NvRegRxRingPhysAddrHigh = 0x14C,
313 NvRegTxPauseFrame = 0x170,
314 #define NVREG_TX_PAUSEFRAME_DISABLE 0x1ff0080
315 #define NVREG_TX_PAUSEFRAME_ENABLE 0x0c00030
316 NvRegMIIStatus = 0x180,
317 #define NVREG_MIISTAT_ERROR 0x0001
318 #define NVREG_MIISTAT_LINKCHANGE 0x0008
319 #define NVREG_MIISTAT_MASK 0x000f
320 #define NVREG_MIISTAT_MASK2 0x000f
321 NvRegMIIMask = 0x184,
322 #define NVREG_MII_LINKCHANGE 0x0008
324 NvRegAdapterControl = 0x188,
325 #define NVREG_ADAPTCTL_START 0x02
326 #define NVREG_ADAPTCTL_LINKUP 0x04
327 #define NVREG_ADAPTCTL_PHYVALID 0x40000
328 #define NVREG_ADAPTCTL_RUNNING 0x100000
329 #define NVREG_ADAPTCTL_PHYSHIFT 24
330 NvRegMIISpeed = 0x18c,
331 #define NVREG_MIISPEED_BIT8 (1<<8)
332 #define NVREG_MIIDELAY 5
333 NvRegMIIControl = 0x190,
334 #define NVREG_MIICTL_INUSE 0x08000
335 #define NVREG_MIICTL_WRITE 0x00400
336 #define NVREG_MIICTL_ADDRSHIFT 5
337 NvRegMIIData = 0x194,
338 NvRegWakeUpFlags = 0x200,
339 #define NVREG_WAKEUPFLAGS_VAL 0x7770
340 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
341 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
342 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
343 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
344 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
345 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
346 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
347 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
348 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
349 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
351 NvRegPatternCRC = 0x204,
352 NvRegPatternMask = 0x208,
353 NvRegPowerCap = 0x268,
354 #define NVREG_POWERCAP_D3SUPP (1<<30)
355 #define NVREG_POWERCAP_D2SUPP (1<<26)
356 #define NVREG_POWERCAP_D1SUPP (1<<25)
357 NvRegPowerState = 0x26c,
358 #define NVREG_POWERSTATE_POWEREDUP 0x8000
359 #define NVREG_POWERSTATE_VALID 0x0100
360 #define NVREG_POWERSTATE_MASK 0x0003
361 #define NVREG_POWERSTATE_D0 0x0000
362 #define NVREG_POWERSTATE_D1 0x0001
363 #define NVREG_POWERSTATE_D2 0x0002
364 #define NVREG_POWERSTATE_D3 0x0003
366 NvRegTxZeroReXmt = 0x284,
367 NvRegTxOneReXmt = 0x288,
368 NvRegTxManyReXmt = 0x28c,
369 NvRegTxLateCol = 0x290,
370 NvRegTxUnderflow = 0x294,
371 NvRegTxLossCarrier = 0x298,
372 NvRegTxExcessDef = 0x29c,
373 NvRegTxRetryErr = 0x2a0,
374 NvRegRxFrameErr = 0x2a4,
375 NvRegRxExtraByte = 0x2a8,
376 NvRegRxLateCol = 0x2ac,
378 NvRegRxFrameTooLong = 0x2b4,
379 NvRegRxOverflow = 0x2b8,
380 NvRegRxFCSErr = 0x2bc,
381 NvRegRxFrameAlignErr = 0x2c0,
382 NvRegRxLenErr = 0x2c4,
383 NvRegRxUnicast = 0x2c8,
384 NvRegRxMulticast = 0x2cc,
385 NvRegRxBroadcast = 0x2d0,
387 NvRegTxFrame = 0x2d8,
389 NvRegTxPause = 0x2e0,
390 NvRegRxPause = 0x2e4,
391 NvRegRxDropFrame = 0x2e8,
392 NvRegVlanControl = 0x300,
393 #define NVREG_VLANCONTROL_ENABLE 0x2000
394 NvRegMSIXMap0 = 0x3e0,
395 NvRegMSIXMap1 = 0x3e4,
396 NvRegMSIXIrqStatus = 0x3f0,
398 NvRegPowerState2 = 0x600,
399 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
400 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
403 /* Big endian: should work, but is untested */
409 struct ring_desc_ex {
417 struct ring_desc* orig;
418 struct ring_desc_ex* ex;
421 #define FLAG_MASK_V1 0xffff0000
422 #define FLAG_MASK_V2 0xffffc000
423 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
424 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
426 #define NV_TX_LASTPACKET (1<<16)
427 #define NV_TX_RETRYERROR (1<<19)
428 #define NV_TX_FORCED_INTERRUPT (1<<24)
429 #define NV_TX_DEFERRED (1<<26)
430 #define NV_TX_CARRIERLOST (1<<27)
431 #define NV_TX_LATECOLLISION (1<<28)
432 #define NV_TX_UNDERFLOW (1<<29)
433 #define NV_TX_ERROR (1<<30)
434 #define NV_TX_VALID (1<<31)
436 #define NV_TX2_LASTPACKET (1<<29)
437 #define NV_TX2_RETRYERROR (1<<18)
438 #define NV_TX2_FORCED_INTERRUPT (1<<30)
439 #define NV_TX2_DEFERRED (1<<25)
440 #define NV_TX2_CARRIERLOST (1<<26)
441 #define NV_TX2_LATECOLLISION (1<<27)
442 #define NV_TX2_UNDERFLOW (1<<28)
443 /* error and valid are the same for both */
444 #define NV_TX2_ERROR (1<<30)
445 #define NV_TX2_VALID (1<<31)
446 #define NV_TX2_TSO (1<<28)
447 #define NV_TX2_TSO_SHIFT 14
448 #define NV_TX2_TSO_MAX_SHIFT 14
449 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
450 #define NV_TX2_CHECKSUM_L3 (1<<27)
451 #define NV_TX2_CHECKSUM_L4 (1<<26)
453 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
455 #define NV_RX_DESCRIPTORVALID (1<<16)
456 #define NV_RX_MISSEDFRAME (1<<17)
457 #define NV_RX_SUBSTRACT1 (1<<18)
458 #define NV_RX_ERROR1 (1<<23)
459 #define NV_RX_ERROR2 (1<<24)
460 #define NV_RX_ERROR3 (1<<25)
461 #define NV_RX_ERROR4 (1<<26)
462 #define NV_RX_CRCERR (1<<27)
463 #define NV_RX_OVERFLOW (1<<28)
464 #define NV_RX_FRAMINGERR (1<<29)
465 #define NV_RX_ERROR (1<<30)
466 #define NV_RX_AVAIL (1<<31)
468 #define NV_RX2_CHECKSUMMASK (0x1C000000)
469 #define NV_RX2_CHECKSUMOK1 (0x10000000)
470 #define NV_RX2_CHECKSUMOK2 (0x14000000)
471 #define NV_RX2_CHECKSUMOK3 (0x18000000)
472 #define NV_RX2_DESCRIPTORVALID (1<<29)
473 #define NV_RX2_SUBSTRACT1 (1<<25)
474 #define NV_RX2_ERROR1 (1<<18)
475 #define NV_RX2_ERROR2 (1<<19)
476 #define NV_RX2_ERROR3 (1<<20)
477 #define NV_RX2_ERROR4 (1<<21)
478 #define NV_RX2_CRCERR (1<<22)
479 #define NV_RX2_OVERFLOW (1<<23)
480 #define NV_RX2_FRAMINGERR (1<<24)
481 /* error and avail are the same for both */
482 #define NV_RX2_ERROR (1<<30)
483 #define NV_RX2_AVAIL (1<<31)
485 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
486 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
488 /* Miscelaneous hardware related defines: */
489 #define NV_PCI_REGSZ_VER1 0x270
490 #define NV_PCI_REGSZ_VER2 0x604
492 /* various timeout delays: all in usec */
493 #define NV_TXRX_RESET_DELAY 4
494 #define NV_TXSTOP_DELAY1 10
495 #define NV_TXSTOP_DELAY1MAX 500000
496 #define NV_TXSTOP_DELAY2 100
497 #define NV_RXSTOP_DELAY1 10
498 #define NV_RXSTOP_DELAY1MAX 500000
499 #define NV_RXSTOP_DELAY2 100
500 #define NV_SETUP5_DELAY 5
501 #define NV_SETUP5_DELAYMAX 50000
502 #define NV_POWERUP_DELAY 5
503 #define NV_POWERUP_DELAYMAX 5000
504 #define NV_MIIBUSY_DELAY 50
505 #define NV_MIIPHY_DELAY 10
506 #define NV_MIIPHY_DELAYMAX 10000
507 #define NV_MAC_RESET_DELAY 64
509 #define NV_WAKEUPPATTERNS 5
510 #define NV_WAKEUPMASKENTRIES 4
512 /* General driver defaults */
513 #define NV_WATCHDOG_TIMEO (5*HZ)
515 #define RX_RING_DEFAULT 128
516 #define TX_RING_DEFAULT 256
517 #define RX_RING_MIN 128
518 #define TX_RING_MIN 64
519 #define RING_MAX_DESC_VER_1 1024
520 #define RING_MAX_DESC_VER_2_3 16384
522 /* rx/tx mac addr + type + vlan + align + slack*/
523 #define NV_RX_HEADERS (64)
524 /* even more slack. */
525 #define NV_RX_ALLOC_PAD (64)
527 /* maximum mtu size */
528 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
529 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
531 #define OOM_REFILL (1+HZ/20)
532 #define POLL_WAIT (1+HZ/100)
533 #define LINK_TIMEOUT (3*HZ)
534 #define STATS_INTERVAL (10*HZ)
538 * The nic supports three different descriptor types:
539 * - DESC_VER_1: Original
540 * - DESC_VER_2: support for jumbo frames.
541 * - DESC_VER_3: 64-bit format.
548 #define PHY_OUI_MARVELL 0x5043
549 #define PHY_OUI_CICADA 0x03f1
550 #define PHYID1_OUI_MASK 0x03ff
551 #define PHYID1_OUI_SHFT 6
552 #define PHYID2_OUI_MASK 0xfc00
553 #define PHYID2_OUI_SHFT 10
554 #define PHYID2_MODEL_MASK 0x03f0
555 #define PHY_MODEL_MARVELL_E3016 0x220
556 #define PHY_MARVELL_E3016_INITMASK 0x0300
557 #define PHY_INIT1 0x0f000
558 #define PHY_INIT2 0x0e00
559 #define PHY_INIT3 0x01000
560 #define PHY_INIT4 0x0200
561 #define PHY_INIT5 0x0004
562 #define PHY_INIT6 0x02000
563 #define PHY_GIGABIT 0x0100
565 #define PHY_TIMEOUT 0x1
566 #define PHY_ERROR 0x2
570 #define PHY_HALF 0x100
572 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
573 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
574 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
575 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
576 #define NV_PAUSEFRAME_RX_REQ 0x0010
577 #define NV_PAUSEFRAME_TX_REQ 0x0020
578 #define NV_PAUSEFRAME_AUTONEG 0x0040
580 /* MSI/MSI-X defines */
581 #define NV_MSI_X_MAX_VECTORS 8
582 #define NV_MSI_X_VECTORS_MASK 0x000f
583 #define NV_MSI_CAPABLE 0x0010
584 #define NV_MSI_X_CAPABLE 0x0020
585 #define NV_MSI_ENABLED 0x0040
586 #define NV_MSI_X_ENABLED 0x0080
588 #define NV_MSI_X_VECTOR_ALL 0x0
589 #define NV_MSI_X_VECTOR_RX 0x0
590 #define NV_MSI_X_VECTOR_TX 0x1
591 #define NV_MSI_X_VECTOR_OTHER 0x2
594 struct nv_ethtool_str {
595 char name[ETH_GSTRING_LEN];
598 static const struct nv_ethtool_str nv_estats_str[] = {
603 { "tx_late_collision" },
604 { "tx_fifo_errors" },
605 { "tx_carrier_errors" },
606 { "tx_excess_deferral" },
607 { "tx_retry_error" },
611 { "rx_frame_error" },
613 { "rx_late_collision" },
615 { "rx_frame_too_long" },
616 { "rx_over_errors" },
618 { "rx_frame_align_error" },
619 { "rx_length_error" },
627 { "rx_errors_total" }
630 struct nv_ethtool_stats {
635 u64 tx_late_collision;
637 u64 tx_carrier_errors;
638 u64 tx_excess_deferral;
645 u64 rx_late_collision;
647 u64 rx_frame_too_long;
650 u64 rx_frame_align_error;
663 #define NV_TEST_COUNT_BASE 3
664 #define NV_TEST_COUNT_EXTENDED 4
666 static const struct nv_ethtool_str nv_etests_str[] = {
667 { "link (online/offline)" },
668 { "register (offline) " },
669 { "interrupt (offline) " },
670 { "loopback (offline) " }
673 struct register_test {
678 static const struct register_test nv_registers_test[] = {
679 { NvRegUnknownSetupReg6, 0x01 },
680 { NvRegMisc1, 0x03c },
681 { NvRegOffloadConfig, 0x03ff },
682 { NvRegMulticastAddrA, 0xffffffff },
683 { NvRegTxWatermark, 0x0ff },
684 { NvRegWakeUpFlags, 0x07777 },
691 unsigned int dma_len;
696 * All hardware access under dev->priv->lock, except the performance
698 * - rx is (pseudo-) lockless: it relies on the single-threading provided
699 * by the arch code for interrupts.
700 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
701 * needs dev->priv->lock :-(
702 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
705 /* in dev: base, irq */
710 * Locking: spin_lock(&np->lock); */
711 struct net_device_stats stats;
712 struct nv_ethtool_stats estats;
720 unsigned int phy_oui;
721 unsigned int phy_model;
726 /* General data: RO fields */
727 dma_addr_t ring_addr;
728 struct pci_dev *pci_dev;
741 /* rx specific fields.
742 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
744 union ring_type get_rx, put_rx, first_rx, last_rx;
745 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
746 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
747 struct nv_skb_map *rx_skb;
749 union ring_type rx_ring;
750 unsigned int rx_buf_sz;
751 unsigned int pkt_limit;
752 struct timer_list oom_kick;
753 struct timer_list nic_poll;
754 struct timer_list stats_poll;
758 /* media detection workaround.
759 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
762 unsigned long link_timeout;
764 * tx specific fields.
766 union ring_type get_tx, put_tx, first_tx, last_tx;
767 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
768 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
769 struct nv_skb_map *tx_skb;
771 union ring_type tx_ring;
777 struct vlan_group *vlangrp;
779 /* msi/msi-x fields */
781 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
788 * Maximum number of loops until we assume that a bit in the irq mask
789 * is stuck. Overridable with module param.
791 static int max_interrupt_work = 5;
794 * Optimization can be either throuput mode or cpu mode
796 * Throughput Mode: Every tx and rx packet will generate an interrupt.
797 * CPU Mode: Interrupts are controlled by a timer.
800 NV_OPTIMIZATION_MODE_THROUGHPUT,
801 NV_OPTIMIZATION_MODE_CPU
803 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
806 * Poll interval for timer irq
808 * This interval determines how frequent an interrupt is generated.
809 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
810 * Min = 0, and Max = 65535
812 static int poll_interval = -1;
821 static int msi = NV_MSI_INT_ENABLED;
827 NV_MSIX_INT_DISABLED,
830 static int msix = NV_MSIX_INT_ENABLED;
836 NV_DMA_64BIT_DISABLED,
839 static int dma_64bit = NV_DMA_64BIT_ENABLED;
841 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
843 return netdev_priv(dev);
846 static inline u8 __iomem *get_hwbase(struct net_device *dev)
848 return ((struct fe_priv *)netdev_priv(dev))->base;
851 static inline void pci_push(u8 __iomem *base)
853 /* force out pending posted writes */
857 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
859 return le32_to_cpu(prd->flaglen)
860 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
863 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
865 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
868 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
869 int delay, int delaymax, const char *msg)
871 u8 __iomem *base = get_hwbase(dev);
882 } while ((readl(base + offset) & mask) != target);
886 #define NV_SETUP_RX_RING 0x01
887 #define NV_SETUP_TX_RING 0x02
889 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
891 struct fe_priv *np = get_nvpriv(dev);
892 u8 __iomem *base = get_hwbase(dev);
894 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
895 if (rxtx_flags & NV_SETUP_RX_RING) {
896 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
898 if (rxtx_flags & NV_SETUP_TX_RING) {
899 writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
902 if (rxtx_flags & NV_SETUP_RX_RING) {
903 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
904 writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
906 if (rxtx_flags & NV_SETUP_TX_RING) {
907 writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
908 writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
913 static void free_rings(struct net_device *dev)
915 struct fe_priv *np = get_nvpriv(dev);
917 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
918 if (np->rx_ring.orig)
919 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
920 np->rx_ring.orig, np->ring_addr);
923 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
924 np->rx_ring.ex, np->ring_addr);
932 static int using_multi_irqs(struct net_device *dev)
934 struct fe_priv *np = get_nvpriv(dev);
936 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
937 ((np->msi_flags & NV_MSI_X_ENABLED) &&
938 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
944 static void nv_enable_irq(struct net_device *dev)
946 struct fe_priv *np = get_nvpriv(dev);
948 if (!using_multi_irqs(dev)) {
949 if (np->msi_flags & NV_MSI_X_ENABLED)
950 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
952 enable_irq(dev->irq);
954 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
955 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
956 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
960 static void nv_disable_irq(struct net_device *dev)
962 struct fe_priv *np = get_nvpriv(dev);
964 if (!using_multi_irqs(dev)) {
965 if (np->msi_flags & NV_MSI_X_ENABLED)
966 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
968 disable_irq(dev->irq);
970 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
971 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
972 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
976 /* In MSIX mode, a write to irqmask behaves as XOR */
977 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
979 u8 __iomem *base = get_hwbase(dev);
981 writel(mask, base + NvRegIrqMask);
984 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
986 struct fe_priv *np = get_nvpriv(dev);
987 u8 __iomem *base = get_hwbase(dev);
989 if (np->msi_flags & NV_MSI_X_ENABLED) {
990 writel(mask, base + NvRegIrqMask);
992 if (np->msi_flags & NV_MSI_ENABLED)
993 writel(0, base + NvRegMSIIrqMask);
994 writel(0, base + NvRegIrqMask);
998 #define MII_READ (-1)
999 /* mii_rw: read/write a register on the PHY.
1001 * Caller must guarantee serialization
1003 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1005 u8 __iomem *base = get_hwbase(dev);
1009 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1011 reg = readl(base + NvRegMIIControl);
1012 if (reg & NVREG_MIICTL_INUSE) {
1013 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1014 udelay(NV_MIIBUSY_DELAY);
1017 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1018 if (value != MII_READ) {
1019 writel(value, base + NvRegMIIData);
1020 reg |= NVREG_MIICTL_WRITE;
1022 writel(reg, base + NvRegMIIControl);
1024 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1025 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1026 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1027 dev->name, miireg, addr);
1029 } else if (value != MII_READ) {
1030 /* it was a write operation - fewer failures are detectable */
1031 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1032 dev->name, value, miireg, addr);
1034 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1035 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1036 dev->name, miireg, addr);
1039 retval = readl(base + NvRegMIIData);
1040 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1041 dev->name, miireg, addr, retval);
1047 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1049 struct fe_priv *np = netdev_priv(dev);
1051 unsigned int tries = 0;
1053 miicontrol = BMCR_RESET | bmcr_setup;
1054 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1058 /* wait for 500ms */
1061 /* must wait till reset is deasserted */
1062 while (miicontrol & BMCR_RESET) {
1064 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1065 /* FIXME: 100 tries seem excessive */
1072 static int phy_init(struct net_device *dev)
1074 struct fe_priv *np = get_nvpriv(dev);
1075 u8 __iomem *base = get_hwbase(dev);
1076 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1078 /* phy errata for E3016 phy */
1079 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1080 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1081 reg &= ~PHY_MARVELL_E3016_INITMASK;
1082 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1083 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1088 /* set advertise register */
1089 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1090 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1091 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1092 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1096 /* get phy interface type */
1097 phyinterface = readl(base + NvRegPhyInterface);
1099 /* see if gigabit phy */
1100 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1101 if (mii_status & PHY_GIGABIT) {
1102 np->gigabit = PHY_GIGABIT;
1103 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1104 mii_control_1000 &= ~ADVERTISE_1000HALF;
1105 if (phyinterface & PHY_RGMII)
1106 mii_control_1000 |= ADVERTISE_1000FULL;
1108 mii_control_1000 &= ~ADVERTISE_1000FULL;
1110 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1111 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1118 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1119 mii_control |= BMCR_ANENABLE;
1122 * (certain phys need bmcr to be setup with reset)
1124 if (phy_reset(dev, mii_control)) {
1125 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1129 /* phy vendor specific configuration */
1130 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1131 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1132 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1133 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1134 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1135 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1138 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1139 phy_reserved |= PHY_INIT5;
1140 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1141 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1145 if (np->phy_oui == PHY_OUI_CICADA) {
1146 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1147 phy_reserved |= PHY_INIT6;
1148 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1149 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1153 /* some phys clear out pause advertisment on reset, set it back */
1154 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1156 /* restart auto negotiation */
1157 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1158 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1159 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1166 static void nv_start_rx(struct net_device *dev)
1168 struct fe_priv *np = netdev_priv(dev);
1169 u8 __iomem *base = get_hwbase(dev);
1170 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1172 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1173 /* Already running? Stop it. */
1174 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1175 rx_ctrl &= ~NVREG_RCVCTL_START;
1176 writel(rx_ctrl, base + NvRegReceiverControl);
1179 writel(np->linkspeed, base + NvRegLinkSpeed);
1181 rx_ctrl |= NVREG_RCVCTL_START;
1183 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1184 writel(rx_ctrl, base + NvRegReceiverControl);
1185 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1186 dev->name, np->duplex, np->linkspeed);
1190 static void nv_stop_rx(struct net_device *dev)
1192 struct fe_priv *np = netdev_priv(dev);
1193 u8 __iomem *base = get_hwbase(dev);
1194 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1196 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1197 if (!np->mac_in_use)
1198 rx_ctrl &= ~NVREG_RCVCTL_START;
1200 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1201 writel(rx_ctrl, base + NvRegReceiverControl);
1202 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1203 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1204 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1206 udelay(NV_RXSTOP_DELAY2);
1207 if (!np->mac_in_use)
1208 writel(0, base + NvRegLinkSpeed);
1211 static void nv_start_tx(struct net_device *dev)
1213 struct fe_priv *np = netdev_priv(dev);
1214 u8 __iomem *base = get_hwbase(dev);
1215 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1217 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1218 tx_ctrl |= NVREG_XMITCTL_START;
1220 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1221 writel(tx_ctrl, base + NvRegTransmitterControl);
1225 static void nv_stop_tx(struct net_device *dev)
1227 struct fe_priv *np = netdev_priv(dev);
1228 u8 __iomem *base = get_hwbase(dev);
1229 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1231 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1232 if (!np->mac_in_use)
1233 tx_ctrl &= ~NVREG_XMITCTL_START;
1235 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1236 writel(tx_ctrl, base + NvRegTransmitterControl);
1237 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1238 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1239 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1241 udelay(NV_TXSTOP_DELAY2);
1242 if (!np->mac_in_use)
1243 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1244 base + NvRegTransmitPoll);
1247 static void nv_txrx_reset(struct net_device *dev)
1249 struct fe_priv *np = netdev_priv(dev);
1250 u8 __iomem *base = get_hwbase(dev);
1252 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1253 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1255 udelay(NV_TXRX_RESET_DELAY);
1256 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1260 static void nv_mac_reset(struct net_device *dev)
1262 struct fe_priv *np = netdev_priv(dev);
1263 u8 __iomem *base = get_hwbase(dev);
1265 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1266 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1268 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1270 udelay(NV_MAC_RESET_DELAY);
1271 writel(0, base + NvRegMacReset);
1273 udelay(NV_MAC_RESET_DELAY);
1274 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1279 * nv_get_stats: dev->get_stats function
1280 * Get latest stats value from the nic.
1281 * Called with read_lock(&dev_base_lock) held for read -
1282 * only synchronized against unregister_netdevice.
1284 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1286 struct fe_priv *np = netdev_priv(dev);
1288 /* It seems that the nic always generates interrupts and doesn't
1289 * accumulate errors internally. Thus the current values in np->stats
1290 * are already up to date.
1296 * nv_alloc_rx: fill rx ring entries.
1297 * Return 1 if the allocations for the skbs failed and the
1298 * rx engine is without Available descriptors
1300 static int nv_alloc_rx(struct net_device *dev)
1302 struct fe_priv *np = netdev_priv(dev);
1303 struct ring_desc* less_rx;
1305 less_rx = np->get_rx.orig;
1306 if (less_rx-- == np->first_rx.orig)
1307 less_rx = np->last_rx.orig;
1309 while (np->put_rx.orig != less_rx) {
1310 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1313 np->put_rx_ctx->skb = skb;
1314 np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data,
1315 skb->end-skb->data, PCI_DMA_FROMDEVICE);
1316 np->put_rx_ctx->dma_len = skb->end-skb->data;
1317 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1319 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1320 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1321 np->put_rx.orig = np->first_rx.orig;
1322 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1323 np->put_rx_ctx = np->first_rx_ctx;
1331 static int nv_alloc_rx_optimized(struct net_device *dev)
1333 struct fe_priv *np = netdev_priv(dev);
1334 struct ring_desc_ex* less_rx;
1336 less_rx = np->get_rx.ex;
1337 if (less_rx-- == np->first_rx.ex)
1338 less_rx = np->last_rx.ex;
1340 while (np->put_rx.ex != less_rx) {
1341 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1344 np->put_rx_ctx->skb = skb;
1345 np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data,
1346 skb->end-skb->data, PCI_DMA_FROMDEVICE);
1347 np->put_rx_ctx->dma_len = skb->end-skb->data;
1348 np->put_rx.ex->bufhigh = cpu_to_le64(np->put_rx_ctx->dma) >> 32;
1349 np->put_rx.ex->buflow = cpu_to_le64(np->put_rx_ctx->dma) & 0x0FFFFFFFF;
1351 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1352 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1353 np->put_rx.ex = np->first_rx.ex;
1354 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1355 np->put_rx_ctx = np->first_rx_ctx;
1363 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1364 #ifdef CONFIG_FORCEDETH_NAPI
1365 static void nv_do_rx_refill(unsigned long data)
1367 struct net_device *dev = (struct net_device *) data;
1369 /* Just reschedule NAPI rx processing */
1370 netif_rx_schedule(dev);
1373 static void nv_do_rx_refill(unsigned long data)
1375 struct net_device *dev = (struct net_device *) data;
1376 struct fe_priv *np = netdev_priv(dev);
1379 if (!using_multi_irqs(dev)) {
1380 if (np->msi_flags & NV_MSI_X_ENABLED)
1381 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1383 disable_irq(dev->irq);
1385 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1387 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1388 retcode = nv_alloc_rx(dev);
1390 retcode = nv_alloc_rx_optimized(dev);
1392 spin_lock_irq(&np->lock);
1393 if (!np->in_shutdown)
1394 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1395 spin_unlock_irq(&np->lock);
1397 if (!using_multi_irqs(dev)) {
1398 if (np->msi_flags & NV_MSI_X_ENABLED)
1399 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1401 enable_irq(dev->irq);
1403 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1408 static void nv_init_rx(struct net_device *dev)
1410 struct fe_priv *np = netdev_priv(dev);
1412 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1413 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1414 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1416 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1417 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1418 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1420 for (i = 0; i < np->rx_ring_size; i++) {
1421 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1422 np->rx_ring.orig[i].flaglen = 0;
1423 np->rx_ring.orig[i].buf = 0;
1425 np->rx_ring.ex[i].flaglen = 0;
1426 np->rx_ring.ex[i].txvlan = 0;
1427 np->rx_ring.ex[i].bufhigh = 0;
1428 np->rx_ring.ex[i].buflow = 0;
1430 np->rx_skb[i].skb = NULL;
1431 np->rx_skb[i].dma = 0;
1435 static void nv_init_tx(struct net_device *dev)
1437 struct fe_priv *np = netdev_priv(dev);
1439 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1440 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1441 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1443 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1444 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1445 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1447 for (i = 0; i < np->tx_ring_size; i++) {
1448 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1449 np->tx_ring.orig[i].flaglen = 0;
1450 np->tx_ring.orig[i].buf = 0;
1452 np->tx_ring.ex[i].flaglen = 0;
1453 np->tx_ring.ex[i].txvlan = 0;
1454 np->tx_ring.ex[i].bufhigh = 0;
1455 np->tx_ring.ex[i].buflow = 0;
1457 np->tx_skb[i].skb = NULL;
1458 np->tx_skb[i].dma = 0;
1462 static int nv_init_ring(struct net_device *dev)
1464 struct fe_priv *np = netdev_priv(dev);
1468 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1469 return nv_alloc_rx(dev);
1471 return nv_alloc_rx_optimized(dev);
1474 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1476 struct fe_priv *np = netdev_priv(dev);
1479 pci_unmap_page(np->pci_dev, tx_skb->dma,
1485 dev_kfree_skb_any(tx_skb->skb);
1493 static void nv_drain_tx(struct net_device *dev)
1495 struct fe_priv *np = netdev_priv(dev);
1498 for (i = 0; i < np->tx_ring_size; i++) {
1499 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1500 np->tx_ring.orig[i].flaglen = 0;
1501 np->tx_ring.orig[i].buf = 0;
1503 np->tx_ring.ex[i].flaglen = 0;
1504 np->tx_ring.ex[i].txvlan = 0;
1505 np->tx_ring.ex[i].bufhigh = 0;
1506 np->tx_ring.ex[i].buflow = 0;
1508 if (nv_release_txskb(dev, &np->tx_skb[i]))
1509 np->stats.tx_dropped++;
1513 static void nv_drain_rx(struct net_device *dev)
1515 struct fe_priv *np = netdev_priv(dev);
1518 for (i = 0; i < np->rx_ring_size; i++) {
1519 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1520 np->rx_ring.orig[i].flaglen = 0;
1521 np->rx_ring.orig[i].buf = 0;
1523 np->rx_ring.ex[i].flaglen = 0;
1524 np->rx_ring.ex[i].txvlan = 0;
1525 np->rx_ring.ex[i].bufhigh = 0;
1526 np->rx_ring.ex[i].buflow = 0;
1529 if (np->rx_skb[i].skb) {
1530 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1531 np->rx_skb[i].skb->end-np->rx_skb[i].skb->data,
1532 PCI_DMA_FROMDEVICE);
1533 dev_kfree_skb(np->rx_skb[i].skb);
1534 np->rx_skb[i].skb = NULL;
1539 static void drain_ring(struct net_device *dev)
1545 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1547 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1551 * nv_start_xmit: dev->hard_start_xmit function
1552 * Called with netif_tx_lock held.
1554 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1556 struct fe_priv *np = netdev_priv(dev);
1558 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1559 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1563 u32 size = skb->len-skb->data_len;
1564 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1566 struct ring_desc* put_tx;
1567 struct ring_desc* start_tx;
1568 struct ring_desc* prev_tx;
1569 struct nv_skb_map* prev_tx_ctx;
1571 /* add fragments to entries count */
1572 for (i = 0; i < fragments; i++) {
1573 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1574 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1577 empty_slots = nv_get_empty_tx_slots(np);
1578 if (unlikely(empty_slots <= entries)) {
1579 spin_lock_irq(&np->lock);
1580 netif_stop_queue(dev);
1582 spin_unlock_irq(&np->lock);
1583 return NETDEV_TX_BUSY;
1586 start_tx = put_tx = np->put_tx.orig;
1588 /* setup the header buffer */
1591 prev_tx_ctx = np->put_tx_ctx;
1592 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1593 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1595 np->put_tx_ctx->dma_len = bcnt;
1596 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1597 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1599 tx_flags = np->tx_flags;
1602 if (unlikely(put_tx++ == np->last_tx.orig))
1603 put_tx = np->first_tx.orig;
1604 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1605 np->put_tx_ctx = np->first_tx_ctx;
1608 /* setup the fragments */
1609 for (i = 0; i < fragments; i++) {
1610 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1611 u32 size = frag->size;
1616 prev_tx_ctx = np->put_tx_ctx;
1617 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1618 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1620 np->put_tx_ctx->dma_len = bcnt;
1621 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1622 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1626 if (unlikely(put_tx++ == np->last_tx.orig))
1627 put_tx = np->first_tx.orig;
1628 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1629 np->put_tx_ctx = np->first_tx_ctx;
1633 /* set last fragment flag */
1634 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
1636 /* save skb in this slot's context area */
1637 prev_tx_ctx->skb = skb;
1639 if (skb_is_gso(skb))
1640 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1642 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1643 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1645 spin_lock_irq(&np->lock);
1648 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1649 np->put_tx.orig = put_tx;
1651 spin_unlock_irq(&np->lock);
1653 dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
1654 dev->name, entries, tx_flags_extra);
1657 for (j=0; j<64; j++) {
1659 dprintk("\n%03x:", j);
1660 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1665 dev->trans_start = jiffies;
1666 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1667 return NETDEV_TX_OK;
1670 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
1672 struct fe_priv *np = netdev_priv(dev);
1675 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1679 u32 size = skb->len-skb->data_len;
1680 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1682 struct ring_desc_ex* put_tx;
1683 struct ring_desc_ex* start_tx;
1684 struct ring_desc_ex* prev_tx;
1685 struct nv_skb_map* prev_tx_ctx;
1687 /* add fragments to entries count */
1688 for (i = 0; i < fragments; i++) {
1689 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1690 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1693 empty_slots = nv_get_empty_tx_slots(np);
1694 if (unlikely(empty_slots <= entries)) {
1695 spin_lock_irq(&np->lock);
1696 netif_stop_queue(dev);
1698 spin_unlock_irq(&np->lock);
1699 return NETDEV_TX_BUSY;
1702 start_tx = put_tx = np->put_tx.ex;
1704 /* setup the header buffer */
1707 prev_tx_ctx = np->put_tx_ctx;
1708 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1709 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1711 np->put_tx_ctx->dma_len = bcnt;
1712 put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1713 put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1714 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1716 tx_flags = NV_TX2_VALID;
1719 if (unlikely(put_tx++ == np->last_tx.ex))
1720 put_tx = np->first_tx.ex;
1721 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1722 np->put_tx_ctx = np->first_tx_ctx;
1725 /* setup the fragments */
1726 for (i = 0; i < fragments; i++) {
1727 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1728 u32 size = frag->size;
1733 prev_tx_ctx = np->put_tx_ctx;
1734 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1735 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1737 np->put_tx_ctx->dma_len = bcnt;
1738 put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1739 put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1740 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1744 if (unlikely(put_tx++ == np->last_tx.ex))
1745 put_tx = np->first_tx.ex;
1746 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1747 np->put_tx_ctx = np->first_tx_ctx;
1751 /* set last fragment flag */
1752 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
1754 /* save skb in this slot's context area */
1755 prev_tx_ctx->skb = skb;
1757 if (skb_is_gso(skb))
1758 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1760 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1761 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1764 if (likely(!np->vlangrp)) {
1765 start_tx->txvlan = 0;
1767 if (vlan_tx_tag_present(skb))
1768 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
1770 start_tx->txvlan = 0;
1773 spin_lock_irq(&np->lock);
1776 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1777 np->put_tx.ex = put_tx;
1779 spin_unlock_irq(&np->lock);
1781 dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
1782 dev->name, entries, tx_flags_extra);
1785 for (j=0; j<64; j++) {
1787 dprintk("\n%03x:", j);
1788 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1793 dev->trans_start = jiffies;
1794 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1795 return NETDEV_TX_OK;
1799 * nv_tx_done: check for completed packets, release the skbs.
1801 * Caller must own np->lock.
1803 static void nv_tx_done(struct net_device *dev)
1805 struct fe_priv *np = netdev_priv(dev);
1807 struct ring_desc* orig_get_tx = np->get_tx.orig;
1809 while ((np->get_tx.orig != np->put_tx.orig) &&
1810 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
1812 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
1815 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
1816 np->get_tx_ctx->dma_len,
1818 np->get_tx_ctx->dma = 0;
1820 if (np->desc_ver == DESC_VER_1) {
1821 if (flags & NV_TX_LASTPACKET) {
1822 if (flags & NV_TX_ERROR) {
1823 if (flags & NV_TX_UNDERFLOW)
1824 np->stats.tx_fifo_errors++;
1825 if (flags & NV_TX_CARRIERLOST)
1826 np->stats.tx_carrier_errors++;
1827 np->stats.tx_errors++;
1829 np->stats.tx_packets++;
1830 np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1832 dev_kfree_skb_any(np->get_tx_ctx->skb);
1833 np->get_tx_ctx->skb = NULL;
1836 if (flags & NV_TX2_LASTPACKET) {
1837 if (flags & NV_TX2_ERROR) {
1838 if (flags & NV_TX2_UNDERFLOW)
1839 np->stats.tx_fifo_errors++;
1840 if (flags & NV_TX2_CARRIERLOST)
1841 np->stats.tx_carrier_errors++;
1842 np->stats.tx_errors++;
1844 np->stats.tx_packets++;
1845 np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1847 dev_kfree_skb_any(np->get_tx_ctx->skb);
1848 np->get_tx_ctx->skb = NULL;
1851 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
1852 np->get_tx.orig = np->first_tx.orig;
1853 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
1854 np->get_tx_ctx = np->first_tx_ctx;
1856 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
1858 netif_wake_queue(dev);
1862 static void nv_tx_done_optimized(struct net_device *dev, int limit)
1864 struct fe_priv *np = netdev_priv(dev);
1866 struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
1868 while ((np->get_tx.ex != np->put_tx.ex) &&
1869 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
1872 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
1875 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
1876 np->get_tx_ctx->dma_len,
1878 np->get_tx_ctx->dma = 0;
1880 if (flags & NV_TX2_LASTPACKET) {
1881 if (flags & NV_TX2_ERROR) {
1882 if (flags & NV_TX2_UNDERFLOW)
1883 np->stats.tx_fifo_errors++;
1884 if (flags & NV_TX2_CARRIERLOST)
1885 np->stats.tx_carrier_errors++;
1886 np->stats.tx_errors++;
1888 np->stats.tx_packets++;
1889 np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1891 dev_kfree_skb_any(np->get_tx_ctx->skb);
1892 np->get_tx_ctx->skb = NULL;
1894 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
1895 np->get_tx.ex = np->first_tx.ex;
1896 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
1897 np->get_tx_ctx = np->first_tx_ctx;
1899 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
1901 netif_wake_queue(dev);
1906 * nv_tx_timeout: dev->tx_timeout function
1907 * Called with netif_tx_lock held.
1909 static void nv_tx_timeout(struct net_device *dev)
1911 struct fe_priv *np = netdev_priv(dev);
1912 u8 __iomem *base = get_hwbase(dev);
1915 if (np->msi_flags & NV_MSI_X_ENABLED)
1916 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1918 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1920 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1925 printk(KERN_INFO "%s: Ring at %lx\n",
1926 dev->name, (unsigned long)np->ring_addr);
1927 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1928 for (i=0;i<=np->register_size;i+= 32) {
1929 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1931 readl(base + i + 0), readl(base + i + 4),
1932 readl(base + i + 8), readl(base + i + 12),
1933 readl(base + i + 16), readl(base + i + 20),
1934 readl(base + i + 24), readl(base + i + 28));
1936 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1937 for (i=0;i<np->tx_ring_size;i+= 4) {
1938 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1939 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1941 le32_to_cpu(np->tx_ring.orig[i].buf),
1942 le32_to_cpu(np->tx_ring.orig[i].flaglen),
1943 le32_to_cpu(np->tx_ring.orig[i+1].buf),
1944 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
1945 le32_to_cpu(np->tx_ring.orig[i+2].buf),
1946 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
1947 le32_to_cpu(np->tx_ring.orig[i+3].buf),
1948 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
1950 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1952 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
1953 le32_to_cpu(np->tx_ring.ex[i].buflow),
1954 le32_to_cpu(np->tx_ring.ex[i].flaglen),
1955 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
1956 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
1957 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
1958 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
1959 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
1960 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
1961 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
1962 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
1963 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
1968 spin_lock_irq(&np->lock);
1970 /* 1) stop tx engine */
1973 /* 2) check that the packets were not sent already: */
1974 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1977 nv_tx_done_optimized(dev, np->tx_ring_size);
1979 /* 3) if there are dead entries: clear everything */
1980 if (np->get_tx_ctx != np->put_tx_ctx) {
1981 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1984 setup_hw_rings(dev, NV_SETUP_TX_RING);
1985 netif_wake_queue(dev);
1988 /* 4) restart tx engine */
1990 spin_unlock_irq(&np->lock);
1994 * Called when the nic notices a mismatch between the actual data len on the
1995 * wire and the len indicated in the 802 header
1997 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1999 int hdrlen; /* length of the 802 header */
2000 int protolen; /* length as stored in the proto field */
2002 /* 1) calculate len according to header */
2003 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2004 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2007 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2010 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2011 dev->name, datalen, protolen, hdrlen);
2012 if (protolen > ETH_DATA_LEN)
2013 return datalen; /* Value in proto field not a len, no checks possible */
2016 /* consistency checks: */
2017 if (datalen > ETH_ZLEN) {
2018 if (datalen >= protolen) {
2019 /* more data on wire than in 802 header, trim of
2022 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2023 dev->name, protolen);
2026 /* less data on wire than mentioned in header.
2027 * Discard the packet.
2029 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2034 /* short packet. Accept only if 802 values are also short */
2035 if (protolen > ETH_ZLEN) {
2036 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2040 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2041 dev->name, datalen);
2046 static int nv_rx_process(struct net_device *dev, int limit)
2048 struct fe_priv *np = netdev_priv(dev);
2050 u32 rx_processed_cnt = 0;
2051 struct sk_buff *skb;
2054 while((np->get_rx.orig != np->put_rx.orig) &&
2055 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2056 (rx_processed_cnt++ < limit)) {
2058 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2062 * the packet is for us - immediately tear down the pci mapping.
2063 * TODO: check if a prefetch of the first cacheline improves
2066 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2067 np->get_rx_ctx->dma_len,
2068 PCI_DMA_FROMDEVICE);
2069 skb = np->get_rx_ctx->skb;
2070 np->get_rx_ctx->skb = NULL;
2074 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2075 for (j=0; j<64; j++) {
2077 dprintk("\n%03x:", j);
2078 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2082 /* look at what we actually got: */
2083 if (np->desc_ver == DESC_VER_1) {
2084 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2085 len = flags & LEN_MASK_V1;
2086 if (unlikely(flags & NV_RX_ERROR)) {
2087 if (flags & NV_RX_ERROR4) {
2088 len = nv_getlen(dev, skb->data, len);
2090 np->stats.rx_errors++;
2095 /* framing errors are soft errors */
2096 else if (flags & NV_RX_FRAMINGERR) {
2097 if (flags & NV_RX_SUBSTRACT1) {
2101 /* the rest are hard errors */
2103 if (flags & NV_RX_MISSEDFRAME)
2104 np->stats.rx_missed_errors++;
2105 if (flags & NV_RX_CRCERR)
2106 np->stats.rx_crc_errors++;
2107 if (flags & NV_RX_OVERFLOW)
2108 np->stats.rx_over_errors++;
2109 np->stats.rx_errors++;
2119 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2120 len = flags & LEN_MASK_V2;
2121 if (unlikely(flags & NV_RX2_ERROR)) {
2122 if (flags & NV_RX2_ERROR4) {
2123 len = nv_getlen(dev, skb->data, len);
2125 np->stats.rx_errors++;
2130 /* framing errors are soft errors */
2131 else if (flags & NV_RX2_FRAMINGERR) {
2132 if (flags & NV_RX2_SUBSTRACT1) {
2136 /* the rest are hard errors */
2138 if (flags & NV_RX2_CRCERR)
2139 np->stats.rx_crc_errors++;
2140 if (flags & NV_RX2_OVERFLOW)
2141 np->stats.rx_over_errors++;
2142 np->stats.rx_errors++;
2147 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ {
2148 skb->ip_summed = CHECKSUM_UNNECESSARY;
2150 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 ||
2151 (flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) {
2152 skb->ip_summed = CHECKSUM_UNNECESSARY;
2160 /* got a valid packet - forward it to the network core */
2162 skb->protocol = eth_type_trans(skb, dev);
2163 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2164 dev->name, len, skb->protocol);
2165 #ifdef CONFIG_FORCEDETH_NAPI
2166 netif_receive_skb(skb);
2170 dev->last_rx = jiffies;
2171 np->stats.rx_packets++;
2172 np->stats.rx_bytes += len;
2174 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2175 np->get_rx.orig = np->first_rx.orig;
2176 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2177 np->get_rx_ctx = np->first_rx_ctx;
2180 return rx_processed_cnt;
2183 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2185 struct fe_priv *np = netdev_priv(dev);
2188 u32 rx_processed_cnt = 0;
2189 struct sk_buff *skb;
2192 while((np->get_rx.ex != np->put_rx.ex) &&
2193 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2194 (rx_processed_cnt++ < limit)) {
2196 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2200 * the packet is for us - immediately tear down the pci mapping.
2201 * TODO: check if a prefetch of the first cacheline improves
2204 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2205 np->get_rx_ctx->dma_len,
2206 PCI_DMA_FROMDEVICE);
2207 skb = np->get_rx_ctx->skb;
2208 np->get_rx_ctx->skb = NULL;
2212 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2213 for (j=0; j<64; j++) {
2215 dprintk("\n%03x:", j);
2216 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2220 /* look at what we actually got: */
2221 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2222 len = flags & LEN_MASK_V2;
2223 if (unlikely(flags & NV_RX2_ERROR)) {
2224 if (flags & NV_RX2_ERROR4) {
2225 len = nv_getlen(dev, skb->data, len);
2227 np->stats.rx_errors++;
2232 /* framing errors are soft errors */
2233 else if (flags & NV_RX2_FRAMINGERR) {
2234 if (flags & NV_RX2_SUBSTRACT1) {
2238 /* the rest are hard errors */
2240 if (flags & NV_RX2_CRCERR)
2241 np->stats.rx_crc_errors++;
2242 if (flags & NV_RX2_OVERFLOW)
2243 np->stats.rx_over_errors++;
2244 np->stats.rx_errors++;
2250 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ {
2251 skb->ip_summed = CHECKSUM_UNNECESSARY;
2253 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 ||
2254 (flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) {
2255 skb->ip_summed = CHECKSUM_UNNECESSARY;
2259 /* got a valid packet - forward it to the network core */
2261 skb->protocol = eth_type_trans(skb, dev);
2262 prefetch(skb->data);
2264 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2265 dev->name, len, skb->protocol);
2267 if (likely(!np->vlangrp)) {
2268 #ifdef CONFIG_FORCEDETH_NAPI
2269 netif_receive_skb(skb);
2274 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2275 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2276 #ifdef CONFIG_FORCEDETH_NAPI
2277 vlan_hwaccel_receive_skb(skb, np->vlangrp,
2278 vlanflags & NV_RX3_VLAN_TAG_MASK);
2280 vlan_hwaccel_rx(skb, np->vlangrp,
2281 vlanflags & NV_RX3_VLAN_TAG_MASK);
2284 #ifdef CONFIG_FORCEDETH_NAPI
2285 netif_receive_skb(skb);
2292 dev->last_rx = jiffies;
2293 np->stats.rx_packets++;
2294 np->stats.rx_bytes += len;
2299 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2300 np->get_rx.ex = np->first_rx.ex;
2301 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2302 np->get_rx_ctx = np->first_rx_ctx;
2305 return rx_processed_cnt;
2308 static void set_bufsize(struct net_device *dev)
2310 struct fe_priv *np = netdev_priv(dev);
2312 if (dev->mtu <= ETH_DATA_LEN)
2313 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2315 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2319 * nv_change_mtu: dev->change_mtu function
2320 * Called with dev_base_lock held for read.
2322 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2324 struct fe_priv *np = netdev_priv(dev);
2327 if (new_mtu < 64 || new_mtu > np->pkt_limit)
2333 /* return early if the buffer sizes will not change */
2334 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2336 if (old_mtu == new_mtu)
2339 /* synchronized against open : rtnl_lock() held by caller */
2340 if (netif_running(dev)) {
2341 u8 __iomem *base = get_hwbase(dev);
2343 * It seems that the nic preloads valid ring entries into an
2344 * internal buffer. The procedure for flushing everything is
2345 * guessed, there is probably a simpler approach.
2346 * Changing the MTU is a rare event, it shouldn't matter.
2348 nv_disable_irq(dev);
2349 netif_tx_lock_bh(dev);
2350 spin_lock(&np->lock);
2355 /* drain rx queue */
2358 /* reinit driver view of the rx queue */
2360 if (nv_init_ring(dev)) {
2361 if (!np->in_shutdown)
2362 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2364 /* reinit nic view of the rx queue */
2365 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2366 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2367 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2368 base + NvRegRingSizes);
2370 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2373 /* restart rx engine */
2376 spin_unlock(&np->lock);
2377 netif_tx_unlock_bh(dev);
2383 static void nv_copy_mac_to_hw(struct net_device *dev)
2385 u8 __iomem *base = get_hwbase(dev);
2388 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2389 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2390 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2392 writel(mac[0], base + NvRegMacAddrA);
2393 writel(mac[1], base + NvRegMacAddrB);
2397 * nv_set_mac_address: dev->set_mac_address function
2398 * Called with rtnl_lock() held.
2400 static int nv_set_mac_address(struct net_device *dev, void *addr)
2402 struct fe_priv *np = netdev_priv(dev);
2403 struct sockaddr *macaddr = (struct sockaddr*)addr;
2405 if (!is_valid_ether_addr(macaddr->sa_data))
2406 return -EADDRNOTAVAIL;
2408 /* synchronized against open : rtnl_lock() held by caller */
2409 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2411 if (netif_running(dev)) {
2412 netif_tx_lock_bh(dev);
2413 spin_lock_irq(&np->lock);
2415 /* stop rx engine */
2418 /* set mac address */
2419 nv_copy_mac_to_hw(dev);
2421 /* restart rx engine */
2423 spin_unlock_irq(&np->lock);
2424 netif_tx_unlock_bh(dev);
2426 nv_copy_mac_to_hw(dev);
2432 * nv_set_multicast: dev->set_multicast function
2433 * Called with netif_tx_lock held.
2435 static void nv_set_multicast(struct net_device *dev)
2437 struct fe_priv *np = netdev_priv(dev);
2438 u8 __iomem *base = get_hwbase(dev);
2441 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2443 memset(addr, 0, sizeof(addr));
2444 memset(mask, 0, sizeof(mask));
2446 if (dev->flags & IFF_PROMISC) {
2447 pff |= NVREG_PFF_PROMISC;
2449 pff |= NVREG_PFF_MYADDR;
2451 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2455 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2456 if (dev->flags & IFF_ALLMULTI) {
2457 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2459 struct dev_mc_list *walk;
2461 walk = dev->mc_list;
2462 while (walk != NULL) {
2464 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2465 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2473 addr[0] = alwaysOn[0];
2474 addr[1] = alwaysOn[1];
2475 mask[0] = alwaysOn[0] | alwaysOff[0];
2476 mask[1] = alwaysOn[1] | alwaysOff[1];
2479 addr[0] |= NVREG_MCASTADDRA_FORCE;
2480 pff |= NVREG_PFF_ALWAYS;
2481 spin_lock_irq(&np->lock);
2483 writel(addr[0], base + NvRegMulticastAddrA);
2484 writel(addr[1], base + NvRegMulticastAddrB);
2485 writel(mask[0], base + NvRegMulticastMaskA);
2486 writel(mask[1], base + NvRegMulticastMaskB);
2487 writel(pff, base + NvRegPacketFilterFlags);
2488 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2491 spin_unlock_irq(&np->lock);
2494 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2496 struct fe_priv *np = netdev_priv(dev);
2497 u8 __iomem *base = get_hwbase(dev);
2499 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2501 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2502 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2503 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2504 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2505 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2507 writel(pff, base + NvRegPacketFilterFlags);
2510 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2511 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2512 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2513 writel(NVREG_TX_PAUSEFRAME_ENABLE, base + NvRegTxPauseFrame);
2514 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2515 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2517 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
2518 writel(regmisc, base + NvRegMisc1);
2524 * nv_update_linkspeed: Setup the MAC according to the link partner
2525 * @dev: Network device to be configured
2527 * The function queries the PHY and checks if there is a link partner.
2528 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2529 * set to 10 MBit HD.
2531 * The function returns 0 if there is no link partner and 1 if there is
2532 * a good link partner.
2534 static int nv_update_linkspeed(struct net_device *dev)
2536 struct fe_priv *np = netdev_priv(dev);
2537 u8 __iomem *base = get_hwbase(dev);
2540 int adv_lpa, adv_pause, lpa_pause;
2541 int newls = np->linkspeed;
2542 int newdup = np->duplex;
2545 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2547 /* BMSR_LSTATUS is latched, read it twice:
2548 * we want the current value.
2550 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2551 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2553 if (!(mii_status & BMSR_LSTATUS)) {
2554 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2556 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2562 if (np->autoneg == 0) {
2563 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2564 dev->name, np->fixed_mode);
2565 if (np->fixed_mode & LPA_100FULL) {
2566 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2568 } else if (np->fixed_mode & LPA_100HALF) {
2569 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2571 } else if (np->fixed_mode & LPA_10FULL) {
2572 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2575 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2581 /* check auto negotiation is complete */
2582 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2583 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2584 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2587 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2591 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2592 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2593 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2594 dev->name, adv, lpa);
2597 if (np->gigabit == PHY_GIGABIT) {
2598 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2599 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2601 if ((control_1000 & ADVERTISE_1000FULL) &&
2602 (status_1000 & LPA_1000FULL)) {
2603 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2605 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2611 /* FIXME: handle parallel detection properly */
2612 adv_lpa = lpa & adv;
2613 if (adv_lpa & LPA_100FULL) {
2614 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2616 } else if (adv_lpa & LPA_100HALF) {
2617 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2619 } else if (adv_lpa & LPA_10FULL) {
2620 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2622 } else if (adv_lpa & LPA_10HALF) {
2623 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2626 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2627 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2632 if (np->duplex == newdup && np->linkspeed == newls)
2635 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2636 dev->name, np->linkspeed, np->duplex, newls, newdup);
2638 np->duplex = newdup;
2639 np->linkspeed = newls;
2641 if (np->gigabit == PHY_GIGABIT) {
2642 phyreg = readl(base + NvRegRandomSeed);
2643 phyreg &= ~(0x3FF00);
2644 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2645 phyreg |= NVREG_RNDSEED_FORCE3;
2646 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2647 phyreg |= NVREG_RNDSEED_FORCE2;
2648 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2649 phyreg |= NVREG_RNDSEED_FORCE;
2650 writel(phyreg, base + NvRegRandomSeed);
2653 phyreg = readl(base + NvRegPhyInterface);
2654 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2655 if (np->duplex == 0)
2657 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2659 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2661 writel(phyreg, base + NvRegPhyInterface);
2663 if (phyreg & PHY_RGMII) {
2664 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2665 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2667 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2669 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2671 writel(txreg, base + NvRegTxDeferral);
2673 if (np->desc_ver == DESC_VER_1) {
2674 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2676 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2677 txreg = NVREG_TX_WM_DESC2_3_1000;
2679 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2681 writel(txreg, base + NvRegTxWatermark);
2683 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2686 writel(np->linkspeed, base + NvRegLinkSpeed);
2690 /* setup pause frame */
2691 if (np->duplex != 0) {
2692 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2693 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2694 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2696 switch (adv_pause) {
2697 case ADVERTISE_PAUSE_CAP:
2698 if (lpa_pause & LPA_PAUSE_CAP) {
2699 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2700 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2701 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2704 case ADVERTISE_PAUSE_ASYM:
2705 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2707 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2710 case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2711 if (lpa_pause & LPA_PAUSE_CAP)
2713 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2714 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2715 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2717 if (lpa_pause == LPA_PAUSE_ASYM)
2719 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2724 pause_flags = np->pause_flags;
2727 nv_update_pause(dev, pause_flags);
2732 static void nv_linkchange(struct net_device *dev)
2734 if (nv_update_linkspeed(dev)) {
2735 if (!netif_carrier_ok(dev)) {
2736 netif_carrier_on(dev);
2737 printk(KERN_INFO "%s: link up.\n", dev->name);
2741 if (netif_carrier_ok(dev)) {
2742 netif_carrier_off(dev);
2743 printk(KERN_INFO "%s: link down.\n", dev->name);
2749 static void nv_link_irq(struct net_device *dev)
2751 u8 __iomem *base = get_hwbase(dev);
2754 miistat = readl(base + NvRegMIIStatus);
2755 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2756 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2758 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2760 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2763 static irqreturn_t nv_nic_irq(int foo, void *data)
2765 struct net_device *dev = (struct net_device *) data;
2766 struct fe_priv *np = netdev_priv(dev);
2767 u8 __iomem *base = get_hwbase(dev);
2771 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2774 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2775 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2776 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2778 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2779 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2781 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2782 if (!(events & np->irqmask))
2785 spin_lock(&np->lock);
2787 spin_unlock(&np->lock);
2789 #ifdef CONFIG_FORCEDETH_NAPI
2790 if (events & NVREG_IRQ_RX_ALL) {
2791 netif_rx_schedule(dev);
2793 /* Disable furthur receive irq's */
2794 spin_lock(&np->lock);
2795 np->irqmask &= ~NVREG_IRQ_RX_ALL;
2797 if (np->msi_flags & NV_MSI_X_ENABLED)
2798 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2800 writel(np->irqmask, base + NvRegIrqMask);
2801 spin_unlock(&np->lock);
2804 if (nv_rx_process(dev, dev->weight)) {
2805 if (unlikely(nv_alloc_rx(dev))) {
2806 spin_lock(&np->lock);
2807 if (!np->in_shutdown)
2808 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2809 spin_unlock(&np->lock);
2813 if (unlikely(events & NVREG_IRQ_LINK)) {
2814 spin_lock(&np->lock);
2816 spin_unlock(&np->lock);
2818 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
2819 spin_lock(&np->lock);
2821 spin_unlock(&np->lock);
2822 np->link_timeout = jiffies + LINK_TIMEOUT;
2824 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
2825 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2828 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
2829 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2832 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
2833 spin_lock(&np->lock);
2834 /* disable interrupts on the nic */
2835 if (!(np->msi_flags & NV_MSI_X_ENABLED))
2836 writel(0, base + NvRegIrqMask);
2838 writel(np->irqmask, base + NvRegIrqMask);
2841 if (!np->in_shutdown) {
2842 np->nic_poll_irq = np->irqmask;
2843 np->recover_error = 1;
2844 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2846 spin_unlock(&np->lock);
2849 if (unlikely(i > max_interrupt_work)) {
2850 spin_lock(&np->lock);
2851 /* disable interrupts on the nic */
2852 if (!(np->msi_flags & NV_MSI_X_ENABLED))
2853 writel(0, base + NvRegIrqMask);
2855 writel(np->irqmask, base + NvRegIrqMask);
2858 if (!np->in_shutdown) {
2859 np->nic_poll_irq = np->irqmask;
2860 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2862 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2863 spin_unlock(&np->lock);
2868 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2870 return IRQ_RETVAL(i);
2873 #define TX_WORK_PER_LOOP 64
2874 #define RX_WORK_PER_LOOP 64
2876 * All _optimized functions are used to help increase performance
2877 * (reduce CPU and increase throughput). They use descripter version 3,
2878 * compiler directives, and reduce memory accesses.
2880 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
2882 struct net_device *dev = (struct net_device *) data;
2883 struct fe_priv *np = netdev_priv(dev);
2884 u8 __iomem *base = get_hwbase(dev);
2888 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
2891 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2892 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2893 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2895 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2896 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2898 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2899 if (!(events & np->irqmask))
2902 spin_lock(&np->lock);
2903 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
2904 spin_unlock(&np->lock);
2906 #ifdef CONFIG_FORCEDETH_NAPI
2907 if (events & NVREG_IRQ_RX_ALL) {
2908 netif_rx_schedule(dev);
2910 /* Disable furthur receive irq's */
2911 spin_lock(&np->lock);
2912 np->irqmask &= ~NVREG_IRQ_RX_ALL;
2914 if (np->msi_flags & NV_MSI_X_ENABLED)
2915 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2917 writel(np->irqmask, base + NvRegIrqMask);
2918 spin_unlock(&np->lock);
2921 if (nv_rx_process_optimized(dev, dev->weight)) {
2922 if (unlikely(nv_alloc_rx_optimized(dev))) {
2923 spin_lock(&np->lock);
2924 if (!np->in_shutdown)
2925 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2926 spin_unlock(&np->lock);
2930 if (unlikely(events & NVREG_IRQ_LINK)) {
2931 spin_lock(&np->lock);
2933 spin_unlock(&np->lock);
2935 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
2936 spin_lock(&np->lock);
2938 spin_unlock(&np->lock);
2939 np->link_timeout = jiffies + LINK_TIMEOUT;
2941 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
2942 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2945 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
2946 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2949 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
2950 spin_lock(&np->lock);
2951 /* disable interrupts on the nic */
2952 if (!(np->msi_flags & NV_MSI_X_ENABLED))
2953 writel(0, base + NvRegIrqMask);
2955 writel(np->irqmask, base + NvRegIrqMask);
2958 if (!np->in_shutdown) {
2959 np->nic_poll_irq = np->irqmask;
2960 np->recover_error = 1;
2961 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2963 spin_unlock(&np->lock);
2967 if (unlikely(i > max_interrupt_work)) {
2968 spin_lock(&np->lock);
2969 /* disable interrupts on the nic */
2970 if (!(np->msi_flags & NV_MSI_X_ENABLED))
2971 writel(0, base + NvRegIrqMask);
2973 writel(np->irqmask, base + NvRegIrqMask);
2976 if (!np->in_shutdown) {
2977 np->nic_poll_irq = np->irqmask;
2978 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2980 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2981 spin_unlock(&np->lock);
2986 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
2988 return IRQ_RETVAL(i);
2991 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
2993 struct net_device *dev = (struct net_device *) data;
2994 struct fe_priv *np = netdev_priv(dev);
2995 u8 __iomem *base = get_hwbase(dev);
2998 unsigned long flags;
3000 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3003 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3004 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3005 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3006 if (!(events & np->irqmask))
3009 spin_lock_irqsave(&np->lock, flags);
3010 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3011 spin_unlock_irqrestore(&np->lock, flags);
3013 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3014 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3017 if (unlikely(i > max_interrupt_work)) {
3018 spin_lock_irqsave(&np->lock, flags);
3019 /* disable interrupts on the nic */
3020 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3023 if (!np->in_shutdown) {
3024 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3025 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3027 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3028 spin_unlock_irqrestore(&np->lock, flags);
3033 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3035 return IRQ_RETVAL(i);
3038 #ifdef CONFIG_FORCEDETH_NAPI
3039 static int nv_napi_poll(struct net_device *dev, int *budget)
3041 int pkts, limit = min(*budget, dev->quota);
3042 struct fe_priv *np = netdev_priv(dev);
3043 u8 __iomem *base = get_hwbase(dev);
3044 unsigned long flags;
3046 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
3047 pkts = nv_rx_process(dev, limit);
3049 pkts = nv_rx_process_optimized(dev, limit);
3051 if (nv_alloc_rx(dev)) {
3052 spin_lock_irqsave(&np->lock, flags);
3053 if (!np->in_shutdown)
3054 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3055 spin_unlock_irqrestore(&np->lock, flags);
3059 /* all done, no more packets present */
3060 netif_rx_complete(dev);
3062 /* re-enable receive interrupts */
3063 spin_lock_irqsave(&np->lock, flags);
3065 np->irqmask |= NVREG_IRQ_RX_ALL;
3066 if (np->msi_flags & NV_MSI_X_ENABLED)
3067 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3069 writel(np->irqmask, base + NvRegIrqMask);
3071 spin_unlock_irqrestore(&np->lock, flags);
3074 /* used up our quantum, so reschedule */
3082 #ifdef CONFIG_FORCEDETH_NAPI
3083 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3085 struct net_device *dev = (struct net_device *) data;
3086 u8 __iomem *base = get_hwbase(dev);
3089 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3090 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3093 netif_rx_schedule(dev);
3094 /* disable receive interrupts on the nic */
3095 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3101 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3103 struct net_device *dev = (struct net_device *) data;
3104 struct fe_priv *np = netdev_priv(dev);
3105 u8 __iomem *base = get_hwbase(dev);
3108 unsigned long flags;
3110 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3113 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3114 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3115 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3116 if (!(events & np->irqmask))
3119 if (nv_rx_process_optimized(dev, dev->weight)) {
3120 if (unlikely(nv_alloc_rx_optimized(dev))) {
3121 spin_lock_irqsave(&np->lock, flags);
3122 if (!np->in_shutdown)
3123 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3124 spin_unlock_irqrestore(&np->lock, flags);
3128 if (unlikely(i > max_interrupt_work)) {
3129 spin_lock_irqsave(&np->lock, flags);
3130 /* disable interrupts on the nic */
3131 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3134 if (!np->in_shutdown) {
3135 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3136 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3138 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3139 spin_unlock_irqrestore(&np->lock, flags);
3143 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3145 return IRQ_RETVAL(i);
3149 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3151 struct net_device *dev = (struct net_device *) data;
3152 struct fe_priv *np = netdev_priv(dev);
3153 u8 __iomem *base = get_hwbase(dev);
3156 unsigned long flags;
3158 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3161 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3162 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3163 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3164 if (!(events & np->irqmask))
3167 /* check tx in case we reached max loop limit in tx isr */
3168 spin_lock_irqsave(&np->lock, flags);
3169 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3170 spin_unlock_irqrestore(&np->lock, flags);
3172 if (events & NVREG_IRQ_LINK) {
3173 spin_lock_irqsave(&np->lock, flags);
3175 spin_unlock_irqrestore(&np->lock, flags);
3177 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3178 spin_lock_irqsave(&np->lock, flags);
3180 spin_unlock_irqrestore(&np->lock, flags);
3181 np->link_timeout = jiffies + LINK_TIMEOUT;
3183 if (events & NVREG_IRQ_RECOVER_ERROR) {
3184 spin_lock_irq(&np->lock);
3185 /* disable interrupts on the nic */
3186 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3189 if (!np->in_shutdown) {
3190 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3191 np->recover_error = 1;
3192 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3194 spin_unlock_irq(&np->lock);
3197 if (events & (NVREG_IRQ_UNKNOWN)) {
3198 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3201 if (unlikely(i > max_interrupt_work)) {
3202 spin_lock_irqsave(&np->lock, flags);
3203 /* disable interrupts on the nic */
3204 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3207 if (!np->in_shutdown) {
3208 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3209 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3211 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3212 spin_unlock_irqrestore(&np->lock, flags);
3217 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3219 return IRQ_RETVAL(i);
3222 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3224 struct net_device *dev = (struct net_device *) data;
3225 struct fe_priv *np = netdev_priv(dev);
3226 u8 __iomem *base = get_hwbase(dev);
3229 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3231 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3232 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3233 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3235 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3236 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3239 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3240 if (!(events & NVREG_IRQ_TIMER))
3241 return IRQ_RETVAL(0);
3243 spin_lock(&np->lock);
3245 spin_unlock(&np->lock);
3247 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3249 return IRQ_RETVAL(1);
3252 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3254 u8 __iomem *base = get_hwbase(dev);
3258 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3259 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3260 * the remaining 8 interrupts.
3262 for (i = 0; i < 8; i++) {
3263 if ((irqmask >> i) & 0x1) {
3264 msixmap |= vector << (i << 2);
3267 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3270 for (i = 0; i < 8; i++) {
3271 if ((irqmask >> (i + 8)) & 0x1) {
3272 msixmap |= vector << (i << 2);
3275 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3278 static int nv_request_irq(struct net_device *dev, int intr_test)
3280 struct fe_priv *np = get_nvpriv(dev);
3281 u8 __iomem *base = get_hwbase(dev);
3284 irqreturn_t (*handler)(int foo, void *data);
3287 handler = nv_nic_irq_test;
3289 if (np->desc_ver == DESC_VER_3)
3290 handler = nv_nic_irq_optimized;
3292 handler = nv_nic_irq;
3295 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3296 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3297 np->msi_x_entry[i].entry = i;
3299 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3300 np->msi_flags |= NV_MSI_X_ENABLED;
3301 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3302 /* Request irq for rx handling */
3303 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
3304 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3305 pci_disable_msix(np->pci_dev);
3306 np->msi_flags &= ~NV_MSI_X_ENABLED;
3309 /* Request irq for tx handling */
3310 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
3311 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3312 pci_disable_msix(np->pci_dev);
3313 np->msi_flags &= ~NV_MSI_X_ENABLED;
3316 /* Request irq for link and timer handling */
3317 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
3318 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3319 pci_disable_msix(np->pci_dev);
3320 np->msi_flags &= ~NV_MSI_X_ENABLED;
3323 /* map interrupts to their respective vector */
3324 writel(0, base + NvRegMSIXMap0);
3325 writel(0, base + NvRegMSIXMap1);
3326 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3327 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3328 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3330 /* Request irq for all interrupts */
3331 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3332 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3333 pci_disable_msix(np->pci_dev);
3334 np->msi_flags &= ~NV_MSI_X_ENABLED;
3338 /* map interrupts to vector 0 */
3339 writel(0, base + NvRegMSIXMap0);
3340 writel(0, base + NvRegMSIXMap1);
3344 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3345 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3346 np->msi_flags |= NV_MSI_ENABLED;
3347 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3348 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3349 pci_disable_msi(np->pci_dev);
3350 np->msi_flags &= ~NV_MSI_ENABLED;
3354 /* map interrupts to vector 0 */
3355 writel(0, base + NvRegMSIMap0);
3356 writel(0, base + NvRegMSIMap1);
3357 /* enable msi vector 0 */
3358 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3362 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3369 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3371 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3376 static void nv_free_irq(struct net_device *dev)
3378 struct fe_priv *np = get_nvpriv(dev);
3381 if (np->msi_flags & NV_MSI_X_ENABLED) {
3382 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3383 free_irq(np->msi_x_entry[i].vector, dev);
3385 pci_disable_msix(np->pci_dev);
3386 np->msi_flags &= ~NV_MSI_X_ENABLED;
3388 free_irq(np->pci_dev->irq, dev);
3389 if (np->msi_flags & NV_MSI_ENABLED) {
3390 pci_disable_msi(np->pci_dev);
3391 np->msi_flags &= ~NV_MSI_ENABLED;
3396 static void nv_do_nic_poll(unsigned long data)
3398 struct net_device *dev = (struct net_device *) data;
3399 struct fe_priv *np = netdev_priv(dev);
3400 u8 __iomem *base = get_hwbase(dev);
3404 * First disable irq(s) and then
3405 * reenable interrupts on the nic, we have to do this before calling
3406 * nv_nic_irq because that may decide to do otherwise
3409 if (!using_multi_irqs(dev)) {
3410 if (np->msi_flags & NV_MSI_X_ENABLED)
3411 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3413 disable_irq_lockdep(dev->irq);
3416 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3417 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3418 mask |= NVREG_IRQ_RX_ALL;
3420 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3421 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3422 mask |= NVREG_IRQ_TX_ALL;
3424 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3425 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3426 mask |= NVREG_IRQ_OTHER;
3429 np->nic_poll_irq = 0;
3431 if (np->recover_error) {
3432 np->recover_error = 0;
3433 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3434 if (netif_running(dev)) {
3435 netif_tx_lock_bh(dev);
3436 spin_lock(&np->lock);
3441 /* drain rx queue */
3444 /* reinit driver view of the rx queue */
3446 if (nv_init_ring(dev)) {
3447 if (!np->in_shutdown)
3448 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3450 /* reinit nic view of the rx queue */
3451 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3452 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3453 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3454 base + NvRegRingSizes);
3456 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3459 /* restart rx engine */
3462 spin_unlock(&np->lock);
3463 netif_tx_unlock_bh(dev);
3467 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
3469 writel(mask, base + NvRegIrqMask);
3472 if (!using_multi_irqs(dev)) {
3474 if (np->msi_flags & NV_MSI_X_ENABLED)
3475 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3477 enable_irq_lockdep(dev->irq);
3479 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3480 nv_nic_irq_rx(0, dev);
3481 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3483 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3484 nv_nic_irq_tx(0, dev);
3485 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3487 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3488 nv_nic_irq_other(0, dev);
3489 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3494 #ifdef CONFIG_NET_POLL_CONTROLLER
3495 static void nv_poll_controller(struct net_device *dev)
3497 nv_do_nic_poll((unsigned long) dev);
3501 static void nv_do_stats_poll(unsigned long data)
3503 struct net_device *dev = (struct net_device *) data;
3504 struct fe_priv *np = netdev_priv(dev);
3505 u8 __iomem *base = get_hwbase(dev);
3507 np->estats.tx_bytes += readl(base + NvRegTxCnt);
3508 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
3509 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
3510 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
3511 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
3512 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
3513 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
3514 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
3515 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
3516 np->estats.tx_deferral += readl(base + NvRegTxDef);
3517 np->estats.tx_packets += readl(base + NvRegTxFrame);
3518 np->estats.tx_pause += readl(base + NvRegTxPause);
3519 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
3520 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
3521 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
3522 np->estats.rx_runt += readl(base + NvRegRxRunt);
3523 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
3524 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
3525 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
3526 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
3527 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
3528 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
3529 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
3530 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
3531 np->estats.rx_bytes += readl(base + NvRegRxCnt);
3532 np->estats.rx_pause += readl(base + NvRegRxPause);
3533 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
3534 np->estats.rx_packets =
3535 np->estats.rx_unicast +
3536 np->estats.rx_multicast +
3537 np->estats.rx_broadcast;
3538 np->estats.rx_errors_total =
3539 np->estats.rx_crc_errors +
3540 np->estats.rx_over_errors +
3541 np->estats.rx_frame_error +
3542 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
3543 np->estats.rx_late_collision +
3544 np->estats.rx_runt +
3545 np->estats.rx_frame_too_long;
3547 if (!np->in_shutdown)
3548 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
3551 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3553 struct fe_priv *np = netdev_priv(dev);
3554 strcpy(info->driver, "forcedeth");
3555 strcpy(info->version, FORCEDETH_VERSION);
3556 strcpy(info->bus_info, pci_name(np->pci_dev));
3559 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3561 struct fe_priv *np = netdev_priv(dev);
3562 wolinfo->supported = WAKE_MAGIC;
3564 spin_lock_irq(&np->lock);
3566 wolinfo->wolopts = WAKE_MAGIC;
3567 spin_unlock_irq(&np->lock);
3570 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3572 struct fe_priv *np = netdev_priv(dev);
3573 u8 __iomem *base = get_hwbase(dev);
3576 if (wolinfo->wolopts == 0) {
3578 } else if (wolinfo->wolopts & WAKE_MAGIC) {
3580 flags = NVREG_WAKEUPFLAGS_ENABLE;
3582 if (netif_running(dev)) {
3583 spin_lock_irq(&np->lock);
3584 writel(flags, base + NvRegWakeUpFlags);
3585 spin_unlock_irq(&np->lock);
3590 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3592 struct fe_priv *np = netdev_priv(dev);
3595 spin_lock_irq(&np->lock);
3596 ecmd->port = PORT_MII;
3597 if (!netif_running(dev)) {
3598 /* We do not track link speed / duplex setting if the
3599 * interface is disabled. Force a link check */
3600 if (nv_update_linkspeed(dev)) {
3601 if (!netif_carrier_ok(dev))
3602 netif_carrier_on(dev);
3604 if (netif_carrier_ok(dev))
3605 netif_carrier_off(dev);
3609 if (netif_carrier_ok(dev)) {
3610 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3611 case NVREG_LINKSPEED_10:
3612 ecmd->speed = SPEED_10;
3614 case NVREG_LINKSPEED_100:
3615 ecmd->speed = SPEED_100;
3617 case NVREG_LINKSPEED_1000:
3618 ecmd->speed = SPEED_1000;
3621 ecmd->duplex = DUPLEX_HALF;
3623 ecmd->duplex = DUPLEX_FULL;
3629 ecmd->autoneg = np->autoneg;
3631 ecmd->advertising = ADVERTISED_MII;
3633 ecmd->advertising |= ADVERTISED_Autoneg;
3634 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3635 if (adv & ADVERTISE_10HALF)
3636 ecmd->advertising |= ADVERTISED_10baseT_Half;
3637 if (adv & ADVERTISE_10FULL)
3638 ecmd->advertising |= ADVERTISED_10baseT_Full;
3639 if (adv & ADVERTISE_100HALF)
3640 ecmd->advertising |= ADVERTISED_100baseT_Half;
3641 if (adv & ADVERTISE_100FULL)
3642 ecmd->advertising |= ADVERTISED_100baseT_Full;
3643 if (np->gigabit == PHY_GIGABIT) {
3644 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3645 if (adv & ADVERTISE_1000FULL)
3646 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3649 ecmd->supported = (SUPPORTED_Autoneg |
3650 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3651 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3653 if (np->gigabit == PHY_GIGABIT)
3654 ecmd->supported |= SUPPORTED_1000baseT_Full;
3656 ecmd->phy_address = np->phyaddr;
3657 ecmd->transceiver = XCVR_EXTERNAL;
3659 /* ignore maxtxpkt, maxrxpkt for now */
3660 spin_unlock_irq(&np->lock);
3664 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3666 struct fe_priv *np = netdev_priv(dev);
3668 if (ecmd->port != PORT_MII)
3670 if (ecmd->transceiver != XCVR_EXTERNAL)
3672 if (ecmd->phy_address != np->phyaddr) {
3673 /* TODO: support switching between multiple phys. Should be
3674 * trivial, but not enabled due to lack of test hardware. */
3677 if (ecmd->autoneg == AUTONEG_ENABLE) {
3680 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3681 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3682 if (np->gigabit == PHY_GIGABIT)
3683 mask |= ADVERTISED_1000baseT_Full;
3685 if ((ecmd->advertising & mask) == 0)
3688 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3689 /* Note: autonegotiation disable, speed 1000 intentionally
3690 * forbidden - noone should need that. */
3692 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3694 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3700 netif_carrier_off(dev);
3701 if (netif_running(dev)) {
3702 nv_disable_irq(dev);
3703 netif_tx_lock_bh(dev);
3704 spin_lock(&np->lock);
3708 spin_unlock(&np->lock);
3709 netif_tx_unlock_bh(dev);
3712 if (ecmd->autoneg == AUTONEG_ENABLE) {
3717 /* advertise only what has been requested */
3718 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3719 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3720 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3721 adv |= ADVERTISE_10HALF;
3722 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3723 adv |= ADVERTISE_10FULL;
3724 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3725 adv |= ADVERTISE_100HALF;
3726 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3727 adv |= ADVERTISE_100FULL;
3728 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3729 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3730 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3731 adv |= ADVERTISE_PAUSE_ASYM;
3732 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3734 if (np->gigabit == PHY_GIGABIT) {
3735 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3736 adv &= ~ADVERTISE_1000FULL;
3737 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3738 adv |= ADVERTISE_1000FULL;
3739 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3742 if (netif_running(dev))
3743 printk(KERN_INFO "%s: link down.\n", dev->name);
3744 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3745 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3746 bmcr |= BMCR_ANENABLE;
3747 /* reset the phy in order for settings to stick,
3748 * and cause autoneg to start */
3749 if (phy_reset(dev, bmcr)) {
3750 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3754 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3755 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3762 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3763 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3764 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3765 adv |= ADVERTISE_10HALF;
3766 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3767 adv |= ADVERTISE_10FULL;
3768 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3769 adv |= ADVERTISE_100HALF;
3770 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3771 adv |= ADVERTISE_100FULL;
3772 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3773 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3774 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3775 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3777 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3778 adv |= ADVERTISE_PAUSE_ASYM;
3779 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3781 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3782 np->fixed_mode = adv;
3784 if (np->gigabit == PHY_GIGABIT) {
3785 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3786 adv &= ~ADVERTISE_1000FULL;
3787 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3790 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3791 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3792 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3793 bmcr |= BMCR_FULLDPLX;
3794 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3795 bmcr |= BMCR_SPEED100;
3796 if (np->phy_oui == PHY_OUI_MARVELL) {
3797 /* reset the phy in order for forced mode settings to stick */
3798 if (phy_reset(dev, bmcr)) {
3799 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3803 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3804 if (netif_running(dev)) {
3805 /* Wait a bit and then reconfigure the nic. */
3812 if (netif_running(dev)) {
3821 #define FORCEDETH_REGS_VER 1
3823 static int nv_get_regs_len(struct net_device *dev)
3825 struct fe_priv *np = netdev_priv(dev);
3826 return np->register_size;
3829 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3831 struct fe_priv *np = netdev_priv(dev);
3832 u8 __iomem *base = get_hwbase(dev);
3836 regs->version = FORCEDETH_REGS_VER;
3837 spin_lock_irq(&np->lock);
3838 for (i = 0;i <= np->register_size/sizeof(u32); i++)
3839 rbuf[i] = readl(base + i*sizeof(u32));
3840 spin_unlock_irq(&np->lock);
3843 static int nv_nway_reset(struct net_device *dev)
3845 struct fe_priv *np = netdev_priv(dev);
3851 netif_carrier_off(dev);
3852 if (netif_running(dev)) {
3853 nv_disable_irq(dev);
3854 netif_tx_lock_bh(dev);
3855 spin_lock(&np->lock);
3859 spin_unlock(&np->lock);
3860 netif_tx_unlock_bh(dev);
3861 printk(KERN_INFO "%s: link down.\n", dev->name);
3864 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3865 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3866 bmcr |= BMCR_ANENABLE;
3867 /* reset the phy in order for settings to stick*/
3868 if (phy_reset(dev, bmcr)) {
3869 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3873 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3874 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3877 if (netif_running(dev)) {
3890 static int nv_set_tso(struct net_device *dev, u32 value)
3892 struct fe_priv *np = netdev_priv(dev);
3894 if ((np->driver_data & DEV_HAS_CHECKSUM))
3895 return ethtool_op_set_tso(dev, value);
3900 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3902 struct fe_priv *np = netdev_priv(dev);
3904 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3905 ring->rx_mini_max_pending = 0;
3906 ring->rx_jumbo_max_pending = 0;
3907 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3909 ring->rx_pending = np->rx_ring_size;
3910 ring->rx_mini_pending = 0;
3911 ring->rx_jumbo_pending = 0;
3912 ring->tx_pending = np->tx_ring_size;
3915 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3917 struct fe_priv *np = netdev_priv(dev);
3918 u8 __iomem *base = get_hwbase(dev);
3919 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
3920 dma_addr_t ring_addr;
3922 if (ring->rx_pending < RX_RING_MIN ||
3923 ring->tx_pending < TX_RING_MIN ||
3924 ring->rx_mini_pending != 0 ||
3925 ring->rx_jumbo_pending != 0 ||
3926 (np->desc_ver == DESC_VER_1 &&
3927 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3928 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3929 (np->desc_ver != DESC_VER_1 &&
3930 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3931 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3935 /* allocate new rings */
3936 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3937 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3938 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3941 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3942 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3945 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
3946 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
3947 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
3948 /* fall back to old rings */
3949 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3951 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3952 rxtx_ring, ring_addr);
3955 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3956 rxtx_ring, ring_addr);
3965 if (netif_running(dev)) {
3966 nv_disable_irq(dev);
3967 netif_tx_lock_bh(dev);
3968 spin_lock(&np->lock);
3980 /* set new values */
3981 np->rx_ring_size = ring->rx_pending;
3982 np->tx_ring_size = ring->tx_pending;
3983 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3984 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
3985 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3987 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
3988 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3990 np->rx_skb = (struct nv_skb_map*)rx_skbuff;
3991 np->tx_skb = (struct nv_skb_map*)tx_skbuff;
3992 np->ring_addr = ring_addr;
3994 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
3995 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
3997 if (netif_running(dev)) {
3998 /* reinit driver view of the queues */
4000 if (nv_init_ring(dev)) {
4001 if (!np->in_shutdown)
4002 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4005 /* reinit nic view of the queues */
4006 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4007 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4008 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4009 base + NvRegRingSizes);
4011 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4014 /* restart engines */
4017 spin_unlock(&np->lock);
4018 netif_tx_unlock_bh(dev);
4026 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4028 struct fe_priv *np = netdev_priv(dev);
4030 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4031 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4032 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4035 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4037 struct fe_priv *np = netdev_priv(dev);
4040 if ((!np->autoneg && np->duplex == 0) ||
4041 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4042 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4046 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4047 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4051 netif_carrier_off(dev);
4052 if (netif_running(dev)) {
4053 nv_disable_irq(dev);
4054 netif_tx_lock_bh(dev);
4055 spin_lock(&np->lock);
4059 spin_unlock(&np->lock);
4060 netif_tx_unlock_bh(dev);
4063 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4064 if (pause->rx_pause)
4065 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4066 if (pause->tx_pause)
4067 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4069 if (np->autoneg && pause->autoneg) {
4070 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4072 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4073 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4074 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4075 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4076 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4077 adv |= ADVERTISE_PAUSE_ASYM;
4078 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4080 if (netif_running(dev))
4081 printk(KERN_INFO "%s: link down.\n", dev->name);
4082 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4083 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4084 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4086 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4087 if (pause->rx_pause)
4088 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4089 if (pause->tx_pause)
4090 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4092 if (!netif_running(dev))
4093 nv_update_linkspeed(dev);
4095 nv_update_pause(dev, np->pause_flags);
4098 if (netif_running(dev)) {
4106 static u32 nv_get_rx_csum(struct net_device *dev)
4108 struct fe_priv *np = netdev_priv(dev);
4109 return (np->rx_csum) != 0;
4112 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4114 struct fe_priv *np = netdev_priv(dev);
4115 u8 __iomem *base = get_hwbase(dev);
4118 if (np->driver_data & DEV_HAS_CHECKSUM) {
4121 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4124 /* vlan is dependent on rx checksum offload */
4125 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4126 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4128 if (netif_running(dev)) {
4129 spin_lock_irq(&np->lock);
4130 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4131 spin_unlock_irq(&np->lock);
4140 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4142 struct fe_priv *np = netdev_priv(dev);
4144 if (np->driver_data & DEV_HAS_CHECKSUM)
4145 return ethtool_op_set_tx_hw_csum(dev, data);
4150 static int nv_set_sg(struct net_device *dev, u32 data)
4152 struct fe_priv *np = netdev_priv(dev);
4154 if (np->driver_data & DEV_HAS_CHECKSUM)
4155 return ethtool_op_set_sg(dev, data);
4160 static int nv_get_stats_count(struct net_device *dev)
4162 struct fe_priv *np = netdev_priv(dev);
4164 if (np->driver_data & DEV_HAS_STATISTICS)
4165 return sizeof(struct nv_ethtool_stats)/sizeof(u64);
4170 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4172 struct fe_priv *np = netdev_priv(dev);
4175 nv_do_stats_poll((unsigned long)dev);
4177 memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
4180 static int nv_self_test_count(struct net_device *dev)
4182 struct fe_priv *np = netdev_priv(dev);
4184 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4185 return NV_TEST_COUNT_EXTENDED;
4187 return NV_TEST_COUNT_BASE;
4190 static int nv_link_test(struct net_device *dev)
4192 struct fe_priv *np = netdev_priv(dev);
4195 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4196 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4198 /* check phy link status */
4199 if (!(mii_status & BMSR_LSTATUS))
4205 static int nv_register_test(struct net_device *dev)
4207 u8 __iomem *base = get_hwbase(dev);
4209 u32 orig_read, new_read;
4212 orig_read = readl(base + nv_registers_test[i].reg);
4214 /* xor with mask to toggle bits */
4215 orig_read ^= nv_registers_test[i].mask;
4217 writel(orig_read, base + nv_registers_test[i].reg);
4219 new_read = readl(base + nv_registers_test[i].reg);
4221 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4224 /* restore original value */
4225 orig_read ^= nv_registers_test[i].mask;
4226 writel(orig_read, base + nv_registers_test[i].reg);
4228 } while (nv_registers_test[++i].reg != 0);
4233 static int nv_interrupt_test(struct net_device *dev)
4235 struct fe_priv *np = netdev_priv(dev);
4236 u8 __iomem *base = get_hwbase(dev);
4239 u32 save_msi_flags, save_poll_interval = 0;
4241 if (netif_running(dev)) {
4242 /* free current irq */
4244 save_poll_interval = readl(base+NvRegPollingInterval);
4247 /* flag to test interrupt handler */
4250 /* setup test irq */
4251 save_msi_flags = np->msi_flags;
4252 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4253 np->msi_flags |= 0x001; /* setup 1 vector */
4254 if (nv_request_irq(dev, 1))
4257 /* setup timer interrupt */
4258 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4259 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4261 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4263 /* wait for at least one interrupt */
4266 spin_lock_irq(&np->lock);
4268 /* flag should be set within ISR */
4269 testcnt = np->intr_test;
4273 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4274 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4275 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4277 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4279 spin_unlock_irq(&np->lock);
4283 np->msi_flags = save_msi_flags;
4285 if (netif_running(dev)) {
4286 writel(save_poll_interval, base + NvRegPollingInterval);
4287 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4288 /* restore original irq */
4289 if (nv_request_irq(dev, 0))
4296 static int nv_loopback_test(struct net_device *dev)
4298 struct fe_priv *np = netdev_priv(dev);
4299 u8 __iomem *base = get_hwbase(dev);
4300 struct sk_buff *tx_skb, *rx_skb;
4301 dma_addr_t test_dma_addr;
4302 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4304 int len, i, pkt_len;
4306 u32 filter_flags = 0;
4307 u32 misc1_flags = 0;
4310 if (netif_running(dev)) {
4311 nv_disable_irq(dev);
4312 filter_flags = readl(base + NvRegPacketFilterFlags);
4313 misc1_flags = readl(base + NvRegMisc1);
4318 /* reinit driver view of the rx queue */
4322 /* setup hardware for loopback */
4323 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4324 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4326 /* reinit nic view of the rx queue */
4327 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4328 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4329 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4330 base + NvRegRingSizes);
4333 /* restart rx engine */
4337 /* setup packet for tx */
4338 pkt_len = ETH_DATA_LEN;
4339 tx_skb = dev_alloc_skb(pkt_len);
4341 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4342 " of %s\n", dev->name);
4346 pkt_data = skb_put(tx_skb, pkt_len);
4347 for (i = 0; i < pkt_len; i++)
4348 pkt_data[i] = (u8)(i & 0xff);
4349 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4350 tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
4352 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4353 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4354 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4356 np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
4357 np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
4358 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4360 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4361 pci_push(get_hwbase(dev));
4365 /* check for rx of the packet */
4366 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4367 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4368 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4371 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4372 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4375 if (flags & NV_RX_AVAIL) {
4377 } else if (np->desc_ver == DESC_VER_1) {
4378 if (flags & NV_RX_ERROR)
4381 if (flags & NV_RX2_ERROR) {
4387 if (len != pkt_len) {
4389 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4390 dev->name, len, pkt_len);
4392 rx_skb = np->rx_skb[0].skb;
4393 for (i = 0; i < pkt_len; i++) {
4394 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4396 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4403 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4406 pci_unmap_page(np->pci_dev, test_dma_addr,
4407 tx_skb->end-tx_skb->data,
4409 dev_kfree_skb_any(tx_skb);
4415 /* drain rx queue */
4419 if (netif_running(dev)) {
4420 writel(misc1_flags, base + NvRegMisc1);
4421 writel(filter_flags, base + NvRegPacketFilterFlags);
4428 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4430 struct fe_priv *np = netdev_priv(dev);
4431 u8 __iomem *base = get_hwbase(dev);
4433 memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
4435 if (!nv_link_test(dev)) {
4436 test->flags |= ETH_TEST_FL_FAILED;
4440 if (test->flags & ETH_TEST_FL_OFFLINE) {
4441 if (netif_running(dev)) {
4442 netif_stop_queue(dev);
4443 netif_poll_disable(dev);
4444 netif_tx_lock_bh(dev);
4445 spin_lock_irq(&np->lock);
4446 nv_disable_hw_interrupts(dev, np->irqmask);
4447 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4448 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4450 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4456 /* drain rx queue */
4459 spin_unlock_irq(&np->lock);
4460 netif_tx_unlock_bh(dev);
4463 if (!nv_register_test(dev)) {
4464 test->flags |= ETH_TEST_FL_FAILED;
4468 result = nv_interrupt_test(dev);
4470 test->flags |= ETH_TEST_FL_FAILED;
4478 if (!nv_loopback_test(dev)) {
4479 test->flags |= ETH_TEST_FL_FAILED;
4483 if (netif_running(dev)) {
4484 /* reinit driver view of the rx queue */
4486 if (nv_init_ring(dev)) {
4487 if (!np->in_shutdown)
4488 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4490 /* reinit nic view of the rx queue */
4491 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4492 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4493 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4494 base + NvRegRingSizes);
4496 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4498 /* restart rx engine */
4501 netif_start_queue(dev);
4502 netif_poll_enable(dev);
4503 nv_enable_hw_interrupts(dev, np->irqmask);
4508 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4510 switch (stringset) {
4512 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
4515 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
4520 static const struct ethtool_ops ops = {
4521 .get_drvinfo = nv_get_drvinfo,
4522 .get_link = ethtool_op_get_link,
4523 .get_wol = nv_get_wol,
4524 .set_wol = nv_set_wol,
4525 .get_settings = nv_get_settings,
4526 .set_settings = nv_set_settings,
4527 .get_regs_len = nv_get_regs_len,
4528 .get_regs = nv_get_regs,
4529 .nway_reset = nv_nway_reset,
4530 .get_perm_addr = ethtool_op_get_perm_addr,
4531 .get_tso = ethtool_op_get_tso,
4532 .set_tso = nv_set_tso,
4533 .get_ringparam = nv_get_ringparam,
4534 .set_ringparam = nv_set_ringparam,
4535 .get_pauseparam = nv_get_pauseparam,
4536 .set_pauseparam = nv_set_pauseparam,
4537 .get_rx_csum = nv_get_rx_csum,
4538 .set_rx_csum = nv_set_rx_csum,
4539 .get_tx_csum = ethtool_op_get_tx_csum,
4540 .set_tx_csum = nv_set_tx_csum,
4541 .get_sg = ethtool_op_get_sg,
4542 .set_sg = nv_set_sg,
4543 .get_strings = nv_get_strings,
4544 .get_stats_count = nv_get_stats_count,
4545 .get_ethtool_stats = nv_get_ethtool_stats,
4546 .self_test_count = nv_self_test_count,
4547 .self_test = nv_self_test,
4550 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4552 struct fe_priv *np = get_nvpriv(dev);
4554 spin_lock_irq(&np->lock);
4556 /* save vlan group */
4560 /* enable vlan on MAC */
4561 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4563 /* disable vlan on MAC */
4564 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4565 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4568 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4570 spin_unlock_irq(&np->lock);
4573 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
4578 /* The mgmt unit and driver use a semaphore to access the phy during init */
4579 static int nv_mgmt_acquire_sema(struct net_device *dev)
4581 u8 __iomem *base = get_hwbase(dev);
4583 u32 tx_ctrl, mgmt_sema;
4585 for (i = 0; i < 10; i++) {
4586 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4587 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4592 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4595 for (i = 0; i < 2; i++) {
4596 tx_ctrl = readl(base + NvRegTransmitterControl);
4597 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4598 writel(tx_ctrl, base + NvRegTransmitterControl);
4600 /* verify that semaphore was acquired */
4601 tx_ctrl = readl(base + NvRegTransmitterControl);
4602 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4603 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4612 static int nv_open(struct net_device *dev)
4614 struct fe_priv *np = netdev_priv(dev);
4615 u8 __iomem *base = get_hwbase(dev);
4619 dprintk(KERN_DEBUG "nv_open: begin\n");
4621 /* erase previous misconfiguration */
4622 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4624 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4625 writel(0, base + NvRegMulticastAddrB);
4626 writel(0, base + NvRegMulticastMaskA);
4627 writel(0, base + NvRegMulticastMaskB);
4628 writel(0, base + NvRegPacketFilterFlags);
4630 writel(0, base + NvRegTransmitterControl);
4631 writel(0, base + NvRegReceiverControl);
4633 writel(0, base + NvRegAdapterControl);
4635 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4636 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
4638 /* initialize descriptor rings */
4640 oom = nv_init_ring(dev);
4642 writel(0, base + NvRegLinkSpeed);
4643 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4645 writel(0, base + NvRegUnknownSetupReg6);
4647 np->in_shutdown = 0;
4650 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4651 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4652 base + NvRegRingSizes);
4654 writel(np->linkspeed, base + NvRegLinkSpeed);
4655 if (np->desc_ver == DESC_VER_1)
4656 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4658 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4659 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4660 writel(np->vlanctl_bits, base + NvRegVlanControl);
4662 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4663 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4664 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4665 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4667 writel(0, base + NvRegMIIMask);
4668 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4669 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4671 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4672 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4673 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4674 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4676 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4677 get_random_bytes(&i, sizeof(i));
4678 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4679 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4680 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4681 if (poll_interval == -1) {
4682 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4683 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4685 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4688 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
4689 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4690 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4691 base + NvRegAdapterControl);
4692 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4693 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
4695 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4697 i = readl(base + NvRegPowerState);
4698 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
4699 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
4703 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
4705 nv_disable_hw_interrupts(dev, np->irqmask);
4707 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4708 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4711 if (nv_request_irq(dev, 0)) {
4715 /* ask for interrupts */
4716 nv_enable_hw_interrupts(dev, np->irqmask);
4718 spin_lock_irq(&np->lock);
4719 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4720 writel(0, base + NvRegMulticastAddrB);
4721 writel(0, base + NvRegMulticastMaskA);
4722 writel(0, base + NvRegMulticastMaskB);
4723 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4724 /* One manual link speed update: Interrupts are enabled, future link
4725 * speed changes cause interrupts and are handled by nv_link_irq().
4729 miistat = readl(base + NvRegMIIStatus);
4730 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4731 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4733 /* set linkspeed to invalid value, thus force nv_update_linkspeed
4736 ret = nv_update_linkspeed(dev);
4739 netif_start_queue(dev);
4740 netif_poll_enable(dev);
4743 netif_carrier_on(dev);
4745 printk("%s: no link during initialization.\n", dev->name);
4746 netif_carrier_off(dev);
4749 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4751 /* start statistics timer */
4752 if (np->driver_data & DEV_HAS_STATISTICS)
4753 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4755 spin_unlock_irq(&np->lock);
4763 static int nv_close(struct net_device *dev)
4765 struct fe_priv *np = netdev_priv(dev);
4768 spin_lock_irq(&np->lock);
4769 np->in_shutdown = 1;
4770 spin_unlock_irq(&np->lock);
4771 netif_poll_disable(dev);
4772 synchronize_irq(dev->irq);
4774 del_timer_sync(&np->oom_kick);
4775 del_timer_sync(&np->nic_poll);
4776 del_timer_sync(&np->stats_poll);
4778 netif_stop_queue(dev);
4779 spin_lock_irq(&np->lock);
4784 /* disable interrupts on the nic or we will lock up */
4785 base = get_hwbase(dev);
4786 nv_disable_hw_interrupts(dev, np->irqmask);
4788 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4790 spin_unlock_irq(&np->lock);
4799 /* FIXME: power down nic */
4804 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4806 struct net_device *dev;
4811 u32 powerstate, txreg;
4812 u32 phystate_orig = 0, phystate;
4813 int phyinitialized = 0;
4815 dev = alloc_etherdev(sizeof(struct fe_priv));
4820 np = netdev_priv(dev);
4821 np->pci_dev = pci_dev;
4822 spin_lock_init(&np->lock);
4823 SET_MODULE_OWNER(dev);
4824 SET_NETDEV_DEV(dev, &pci_dev->dev);
4826 init_timer(&np->oom_kick);
4827 np->oom_kick.data = (unsigned long) dev;
4828 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
4829 init_timer(&np->nic_poll);
4830 np->nic_poll.data = (unsigned long) dev;
4831 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
4832 init_timer(&np->stats_poll);
4833 np->stats_poll.data = (unsigned long) dev;
4834 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
4836 err = pci_enable_device(pci_dev);
4838 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4839 err, pci_name(pci_dev));
4843 pci_set_master(pci_dev);
4845 err = pci_request_regions(pci_dev, DRV_NAME);
4849 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
4850 np->register_size = NV_PCI_REGSZ_VER2;
4852 np->register_size = NV_PCI_REGSZ_VER1;
4856 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4857 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4858 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4859 pci_resource_len(pci_dev, i),
4860 pci_resource_flags(pci_dev, i));
4861 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4862 pci_resource_len(pci_dev, i) >= np->register_size) {
4863 addr = pci_resource_start(pci_dev, i);
4867 if (i == DEVICE_COUNT_RESOURCE) {
4868 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4873 /* copy of driver data */
4874 np->driver_data = id->driver_data;
4876 /* handle different descriptor versions */
4877 if (id->driver_data & DEV_HAS_HIGH_DMA) {
4878 /* packet format 3: supports 40-bit addressing */
4879 np->desc_ver = DESC_VER_3;
4880 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4882 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4883 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4886 dev->features |= NETIF_F_HIGHDMA;
4887 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4889 if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4890 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4894 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4895 /* packet format 2: supports jumbo frames */
4896 np->desc_ver = DESC_VER_2;
4897 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4899 /* original packet format */
4900 np->desc_ver = DESC_VER_1;
4901 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4904 np->pkt_limit = NV_PKTLIMIT_1;
4905 if (id->driver_data & DEV_HAS_LARGEDESC)
4906 np->pkt_limit = NV_PKTLIMIT_2;
4908 if (id->driver_data & DEV_HAS_CHECKSUM) {
4910 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4911 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4912 dev->features |= NETIF_F_TSO;
4915 np->vlanctl_bits = 0;
4916 if (id->driver_data & DEV_HAS_VLAN) {
4917 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4918 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4919 dev->vlan_rx_register = nv_vlan_rx_register;
4920 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4924 if ((id->driver_data & DEV_HAS_MSI) && msi) {
4925 np->msi_flags |= NV_MSI_CAPABLE;
4927 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4928 np->msi_flags |= NV_MSI_X_CAPABLE;
4931 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4932 if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4933 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4938 np->base = ioremap(addr, np->register_size);
4941 dev->base_addr = (unsigned long)np->base;
4943 dev->irq = pci_dev->irq;
4945 np->rx_ring_size = RX_RING_DEFAULT;
4946 np->tx_ring_size = TX_RING_DEFAULT;
4948 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4949 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4950 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4952 if (!np->rx_ring.orig)
4954 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4956 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4957 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4959 if (!np->rx_ring.ex)
4961 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4963 np->rx_skb = kmalloc(sizeof(struct nv_skb_map) * np->rx_ring_size, GFP_KERNEL);
4964 np->tx_skb = kmalloc(sizeof(struct nv_skb_map) * np->tx_ring_size, GFP_KERNEL);
4965 if (!np->rx_skb || !np->tx_skb)
4967 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4968 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4970 dev->open = nv_open;
4971 dev->stop = nv_close;
4972 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
4973 dev->hard_start_xmit = nv_start_xmit;
4975 dev->hard_start_xmit = nv_start_xmit_optimized;
4976 dev->get_stats = nv_get_stats;
4977 dev->change_mtu = nv_change_mtu;
4978 dev->set_mac_address = nv_set_mac_address;
4979 dev->set_multicast_list = nv_set_multicast;
4980 #ifdef CONFIG_NET_POLL_CONTROLLER
4981 dev->poll_controller = nv_poll_controller;
4983 dev->weight = RX_WORK_PER_LOOP;
4984 #ifdef CONFIG_FORCEDETH_NAPI
4985 dev->poll = nv_napi_poll;
4987 SET_ETHTOOL_OPS(dev, &ops);
4988 dev->tx_timeout = nv_tx_timeout;
4989 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
4991 pci_set_drvdata(pci_dev, dev);
4993 /* read the mac address */
4994 base = get_hwbase(dev);
4995 np->orig_mac[0] = readl(base + NvRegMacAddrA);
4996 np->orig_mac[1] = readl(base + NvRegMacAddrB);
4998 /* check the workaround bit for correct mac address order */
4999 txreg = readl(base + NvRegTransmitPoll);
5000 if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5001 /* mac address is already in correct order */
5002 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5003 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5004 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5005 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5006 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5007 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5009 /* need to reverse mac address to correct order */
5010 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5011 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5012 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5013 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5014 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5015 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5016 /* set permanent address to be correct aswell */
5017 np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
5018 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
5019 np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
5020 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5022 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5024 if (!is_valid_ether_addr(dev->perm_addr)) {
5026 * Bad mac address. At least one bios sets the mac address
5027 * to 01:23:45:67:89:ab
5029 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
5031 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
5032 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
5033 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
5034 dev->dev_addr[0] = 0x00;
5035 dev->dev_addr[1] = 0x00;
5036 dev->dev_addr[2] = 0x6c;
5037 get_random_bytes(&dev->dev_addr[3], 3);
5040 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
5041 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
5042 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
5044 /* set mac address */
5045 nv_copy_mac_to_hw(dev);
5048 writel(0, base + NvRegWakeUpFlags);
5051 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5053 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
5055 /* take phy and nic out of low power mode */
5056 powerstate = readl(base + NvRegPowerState2);
5057 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5058 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5059 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5060 revision_id >= 0xA3)
5061 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5062 writel(powerstate, base + NvRegPowerState2);
5065 if (np->desc_ver == DESC_VER_1) {
5066 np->tx_flags = NV_TX_VALID;
5068 np->tx_flags = NV_TX2_VALID;
5070 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
5071 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5072 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5073 np->msi_flags |= 0x0003;
5075 np->irqmask = NVREG_IRQMASK_CPU;
5076 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5077 np->msi_flags |= 0x0001;
5080 if (id->driver_data & DEV_NEED_TIMERIRQ)
5081 np->irqmask |= NVREG_IRQ_TIMER;
5082 if (id->driver_data & DEV_NEED_LINKTIMER) {
5083 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5084 np->need_linktimer = 1;
5085 np->link_timeout = jiffies + LINK_TIMEOUT;
5087 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5088 np->need_linktimer = 0;
5091 /* clear phy state and temporarily halt phy interrupts */
5092 writel(0, base + NvRegMIIMask);
5093 phystate = readl(base + NvRegAdapterControl);
5094 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5096 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5097 writel(phystate, base + NvRegAdapterControl);
5099 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
5101 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5102 /* management unit running on the mac? */
5103 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
5104 np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
5105 dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
5106 for (i = 0; i < 5000; i++) {
5108 if (nv_mgmt_acquire_sema(dev)) {
5109 /* management unit setup the phy already? */
5110 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5111 NVREG_XMITCTL_SYNC_PHY_INIT) {
5112 /* phy is inited by mgmt unit */
5114 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5116 /* we need to init the phy */
5124 /* find a suitable phy */
5125 for (i = 1; i <= 32; i++) {
5127 int phyaddr = i & 0x1F;
5129 spin_lock_irq(&np->lock);
5130 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5131 spin_unlock_irq(&np->lock);
5132 if (id1 < 0 || id1 == 0xffff)
5134 spin_lock_irq(&np->lock);
5135 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5136 spin_unlock_irq(&np->lock);
5137 if (id2 < 0 || id2 == 0xffff)
5140 np->phy_model = id2 & PHYID2_MODEL_MASK;
5141 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5142 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5143 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5144 pci_name(pci_dev), id1, id2, phyaddr);
5145 np->phyaddr = phyaddr;
5146 np->phy_oui = id1 | id2;
5150 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
5155 if (!phyinitialized) {
5159 /* see if it is a gigabit phy */
5160 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5161 if (mii_status & PHY_GIGABIT) {
5162 np->gigabit = PHY_GIGABIT;
5166 /* set default link speed settings */
5167 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5171 err = register_netdev(dev);
5173 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
5176 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
5177 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
5184 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5185 pci_set_drvdata(pci_dev, NULL);
5189 iounmap(get_hwbase(dev));
5191 pci_release_regions(pci_dev);
5193 pci_disable_device(pci_dev);
5200 static void __devexit nv_remove(struct pci_dev *pci_dev)
5202 struct net_device *dev = pci_get_drvdata(pci_dev);
5203 struct fe_priv *np = netdev_priv(dev);
5204 u8 __iomem *base = get_hwbase(dev);
5206 unregister_netdev(dev);
5208 /* special op: write back the misordered MAC address - otherwise
5209 * the next nv_probe would see a wrong address.
5211 writel(np->orig_mac[0], base + NvRegMacAddrA);
5212 writel(np->orig_mac[1], base + NvRegMacAddrB);
5214 /* free all structures */
5216 iounmap(get_hwbase(dev));
5217 pci_release_regions(pci_dev);
5218 pci_disable_device(pci_dev);
5220 pci_set_drvdata(pci_dev, NULL);
5224 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5226 struct net_device *dev = pci_get_drvdata(pdev);
5227 struct fe_priv *np = netdev_priv(dev);
5229 if (!netif_running(dev))
5232 netif_device_detach(dev);
5237 pci_save_state(pdev);
5238 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5239 pci_set_power_state(pdev, pci_choose_state(pdev, state));
5244 static int nv_resume(struct pci_dev *pdev)
5246 struct net_device *dev = pci_get_drvdata(pdev);
5249 if (!netif_running(dev))
5252 netif_device_attach(dev);
5254 pci_set_power_state(pdev, PCI_D0);
5255 pci_restore_state(pdev);
5256 pci_enable_wake(pdev, PCI_D0, 0);
5263 #define nv_suspend NULL
5264 #define nv_resume NULL
5265 #endif /* CONFIG_PM */
5267 static struct pci_device_id pci_tbl[] = {
5268 { /* nForce Ethernet Controller */
5269 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
5270 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5272 { /* nForce2 Ethernet Controller */
5273 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
5274 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5276 { /* nForce3 Ethernet Controller */
5277 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
5278 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5280 { /* nForce3 Ethernet Controller */
5281 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
5282 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5284 { /* nForce3 Ethernet Controller */
5285 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
5286 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5288 { /* nForce3 Ethernet Controller */
5289 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
5290 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5292 { /* nForce3 Ethernet Controller */
5293 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
5294 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5296 { /* CK804 Ethernet Controller */
5297 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
5298 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
5300 { /* CK804 Ethernet Controller */
5301 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
5302 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
5304 { /* MCP04 Ethernet Controller */
5305 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
5306 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
5308 { /* MCP04 Ethernet Controller */
5309 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
5310 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
5312 { /* MCP51 Ethernet Controller */
5313 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
5314 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
5316 { /* MCP51 Ethernet Controller */
5317 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
5318 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
5320 { /* MCP55 Ethernet Controller */
5321 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
5322 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5324 { /* MCP55 Ethernet Controller */
5325 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
5326 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5328 { /* MCP61 Ethernet Controller */
5329 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
5330 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5332 { /* MCP61 Ethernet Controller */
5333 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
5334 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5336 { /* MCP61 Ethernet Controller */
5337 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
5338 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5340 { /* MCP61 Ethernet Controller */
5341 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
5342 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5344 { /* MCP65 Ethernet Controller */
5345 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
5346 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5348 { /* MCP65 Ethernet Controller */
5349 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
5350 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5352 { /* MCP65 Ethernet Controller */
5353 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
5354 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5356 { /* MCP65 Ethernet Controller */
5357 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
5358 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5360 { /* MCP67 Ethernet Controller */
5361 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
5362 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5364 { /* MCP67 Ethernet Controller */
5365 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
5366 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5368 { /* MCP67 Ethernet Controller */
5369 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
5370 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5372 { /* MCP67 Ethernet Controller */
5373 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
5374 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5379 static struct pci_driver driver = {
5380 .name = "forcedeth",
5381 .id_table = pci_tbl,
5383 .remove = __devexit_p(nv_remove),
5384 .suspend = nv_suspend,
5385 .resume = nv_resume,
5388 static int __init init_nic(void)
5390 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
5391 return pci_register_driver(&driver);
5394 static void __exit exit_nic(void)
5396 pci_unregister_driver(&driver);
5399 module_param(max_interrupt_work, int, 0);
5400 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
5401 module_param(optimization_mode, int, 0);
5402 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
5403 module_param(poll_interval, int, 0);
5404 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
5405 module_param(msi, int, 0);
5406 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5407 module_param(msix, int, 0);
5408 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5409 module_param(dma_64bit, int, 0);
5410 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
5412 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
5413 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
5414 MODULE_LICENSE("GPL");
5416 MODULE_DEVICE_TABLE(pci, pci_tbl);
5418 module_init(init_nic);
5419 module_exit(exit_nic);