1 /*******************************************************************************
2 STMMAC Common Header File
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23 *******************************************************************************/
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/phy.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
31 #define STMMAC_VLAN_TAG_USED
32 #include <linux/if_vlan.h>
38 #undef CHIP_DEBUG_PRINT
39 /* Turn-on extra printk debug for MAC core, dma and descriptors */
40 /* #define CHIP_DEBUG_PRINT */
42 #ifdef CHIP_DEBUG_PRINT
43 #define CHIP_DBG(fmt, args...) printk(fmt, ## args)
45 #define CHIP_DBG(fmt, args...) do { } while (0)
48 #undef FRAME_FILTER_DEBUG
49 /* #define FRAME_FILTER_DEBUG */
51 struct stmmac_extra_stats {
53 unsigned long tx_underflow ____cacheline_aligned;
54 unsigned long tx_carrier;
55 unsigned long tx_losscarrier;
56 unsigned long vlan_tag;
57 unsigned long tx_deferred;
58 unsigned long tx_vlan;
59 unsigned long tx_jabber;
60 unsigned long tx_frame_flushed;
61 unsigned long tx_payload_error;
62 unsigned long tx_ip_header_error;
64 unsigned long rx_desc;
65 unsigned long sa_filter_fail;
66 unsigned long overflow_error;
67 unsigned long ipc_csum_error;
68 unsigned long rx_collision;
70 unsigned long dribbling_bit;
71 unsigned long rx_length;
73 unsigned long rx_multicast;
74 unsigned long rx_gmac_overflow;
75 unsigned long rx_watchdog;
76 unsigned long da_rx_filter_fail;
77 unsigned long sa_rx_filter_fail;
78 unsigned long rx_missed_cntr;
79 unsigned long rx_overflow_cntr;
80 unsigned long rx_vlan;
81 /* Tx/Rx IRQ errors */
82 unsigned long tx_undeflow_irq;
83 unsigned long tx_process_stopped_irq;
84 unsigned long tx_jabber_irq;
85 unsigned long rx_overflow_irq;
86 unsigned long rx_buf_unav_irq;
87 unsigned long rx_process_stopped_irq;
88 unsigned long rx_watchdog_irq;
89 unsigned long tx_early_irq;
90 unsigned long fatal_bus_error_irq;
92 unsigned long threshold;
93 unsigned long tx_pkt_n;
94 unsigned long rx_pkt_n;
96 unsigned long sched_timer_n;
97 unsigned long normal_irq_n;
98 unsigned long mmc_tx_irq_n;
99 unsigned long mmc_rx_irq_n;
100 unsigned long mmc_rx_csum_offload_irq_n;
102 unsigned long irq_receive_pmt_irq_n;
103 unsigned long irq_tx_path_in_lpi_mode_n;
104 unsigned long irq_tx_path_exit_lpi_mode_n;
105 unsigned long irq_rx_path_in_lpi_mode_n;
106 unsigned long irq_rx_path_exit_lpi_mode_n;
107 unsigned long phy_eee_wakeup_error_n;
110 /* CSR Frequency Access Defines*/
111 #define CSR_F_35M 35000000
112 #define CSR_F_60M 60000000
113 #define CSR_F_100M 100000000
114 #define CSR_F_150M 150000000
115 #define CSR_F_250M 250000000
116 #define CSR_F_300M 300000000
118 #define MAC_CSR_H_FRQ_MASK 0x20
120 #define HASH_TABLE_SIZE 64
121 #define PAUSE_TIME 0x200
123 /* Flow Control defines */
127 #define FLOW_AUTO (FLOW_TX | FLOW_RX)
129 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
131 /* DAM HW feature register fields */
132 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
133 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
134 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
135 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
136 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
137 #define DMA_HW_FEAT_ADDMACADRSEL 0x00000020 /* Multiple MAC Addr Reg */
138 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
139 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
140 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
141 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
142 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
143 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
144 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 Timestamp */
145 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 Adv Timestamp */
146 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
147 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
148 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
149 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP csum Offload(Type 1) in Rx */
150 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP csum Offload(Type 2) in Rx */
151 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
152 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. of additional Rx Channels */
153 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. of additional Tx Channels */
154 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate (Enhanced Descriptor) */
155 #define DMA_HW_FEAT_INTTSEN 0x02000000 /* Timestamping with Internal
157 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
158 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN Insertion */
159 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY interface */
160 #define DEFAULT_DMA_PBL 8
162 enum rx_frame_status { /* IPC status */
169 enum tx_dma_irq_status {
171 tx_hard_error_bump_tc = 2,
175 enum core_specific_irq_mask {
178 core_mmc_rx_csum_offload_irq = 4,
179 core_irq_receive_pmt_irq = 8,
180 core_irq_tx_path_in_lpi_mode = 16,
181 core_irq_tx_path_exit_lpi_mode = 32,
182 core_irq_rx_path_in_lpi_mode = 64,
183 core_irq_rx_path_exit_lpi_mode = 128,
186 /* DMA HW capabilities */
187 struct dma_features {
188 unsigned int mbps_10_100;
189 unsigned int mbps_1000;
190 unsigned int half_duplex;
191 unsigned int hash_filter;
192 unsigned int multi_addr;
194 unsigned int sma_mdio;
195 unsigned int pmt_remote_wake_up;
196 unsigned int pmt_magic_frame;
199 unsigned int time_stamp;
201 unsigned int atime_stamp;
202 /* 802.3az - Energy-Efficient Ethernet (EEE) */
207 unsigned int rx_coe_type1;
208 unsigned int rx_coe_type2;
209 unsigned int rxfifo_over_2048;
210 /* TX and RX number of channels */
211 unsigned int number_rx_channel;
212 unsigned int number_tx_channel;
213 /* Alternate (enhanced) DESC mode*/
214 unsigned int enh_desc;
217 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
218 #define BUF_SIZE_16KiB 16384
219 #define BUF_SIZE_8KiB 8192
220 #define BUF_SIZE_4KiB 4096
221 #define BUF_SIZE_2KiB 2048
223 /* Power Down and WOL */
224 #define PMT_NOT_SUPPORTED 0
225 #define PMT_SUPPORTED 1
227 /* Common MAC defines */
228 #define MAC_CTRL_REG 0x00000000 /* MAC Control */
229 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
230 #define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
232 /* Default LPI timers */
233 #define STMMAC_DEFAULT_LIT_LS_TIMER 0x3E8
234 #define STMMAC_DEFAULT_TWT_LS_TIMER 0x0
236 struct stmmac_desc_ops {
237 /* DMA RX descriptor ring initialization */
238 void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size,
240 /* DMA TX descriptor ring initialization */
241 void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size);
243 /* Invoked by the xmit function to prepare the tx descriptor */
244 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
246 /* Set/get the owner of the descriptor */
247 void (*set_tx_owner) (struct dma_desc *p);
248 int (*get_tx_owner) (struct dma_desc *p);
249 /* Invoked by the xmit function to close the tx descriptor */
250 void (*close_tx_desc) (struct dma_desc *p);
251 /* Clean the tx descriptor as soon as the tx irq is received */
252 void (*release_tx_desc) (struct dma_desc *p);
253 /* Clear interrupt on tx frame completion. When this bit is
254 * set an interrupt happens as soon as the frame is transmitted */
255 void (*clear_tx_ic) (struct dma_desc *p);
256 /* Last tx segment reports the transmit status */
257 int (*get_tx_ls) (struct dma_desc *p);
258 /* Return the transmit status looking at the TDES1 */
259 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
260 struct dma_desc *p, void __iomem *ioaddr);
261 /* Get the buffer size from the descriptor */
262 int (*get_tx_len) (struct dma_desc *p);
263 /* Handle extra events on specific interrupts hw dependent */
264 int (*get_rx_owner) (struct dma_desc *p);
265 void (*set_rx_owner) (struct dma_desc *p);
266 /* Get the receive frame size */
267 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
268 /* Return the reception status looking at the RDES1 */
269 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
273 struct stmmac_dma_ops {
274 /* DMA core initialization */
275 int (*init) (void __iomem *ioaddr, int pbl, int fb, int mb,
276 int burst_len, u32 dma_tx, u32 dma_rx);
277 /* Dump DMA registers */
278 void (*dump_regs) (void __iomem *ioaddr);
279 /* Set tx/rx threshold in the csr6 register
280 * An invalid value enables the store-and-forward mode */
281 void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);
282 /* To track extra statistic (if supported) */
283 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
284 void __iomem *ioaddr);
285 void (*enable_dma_transmission) (void __iomem *ioaddr);
286 void (*enable_dma_irq) (void __iomem *ioaddr);
287 void (*disable_dma_irq) (void __iomem *ioaddr);
288 void (*start_tx) (void __iomem *ioaddr);
289 void (*stop_tx) (void __iomem *ioaddr);
290 void (*start_rx) (void __iomem *ioaddr);
291 void (*stop_rx) (void __iomem *ioaddr);
292 int (*dma_interrupt) (void __iomem *ioaddr,
293 struct stmmac_extra_stats *x);
294 /* If supported then get the optional core features */
295 unsigned int (*get_hw_feature) (void __iomem *ioaddr);
299 /* MAC core initialization */
300 void (*core_init) (void __iomem *ioaddr) ____cacheline_aligned;
301 /* Enable and verify that the IPC module is supported */
302 int (*rx_ipc) (void __iomem *ioaddr);
303 /* Dump MAC registers */
304 void (*dump_regs) (void __iomem *ioaddr);
305 /* Handle extra events on specific interrupts hw dependent */
306 int (*host_irq_status) (void __iomem *ioaddr);
307 /* Multicast filter setting */
308 void (*set_filter) (struct net_device *dev, int id);
309 /* Flow control setting */
310 void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex,
311 unsigned int fc, unsigned int pause_time);
312 /* Set power management mode (e.g. magic frame) */
313 void (*pmt) (void __iomem *ioaddr, unsigned long mode);
314 /* Set/Get Unicast MAC addresses */
315 void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
317 void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
319 void (*set_eee_mode) (void __iomem *ioaddr);
320 void (*reset_eee_mode) (void __iomem *ioaddr);
321 void (*set_eee_timer) (void __iomem *ioaddr, int ls, int tw);
322 void (*set_eee_pls) (void __iomem *ioaddr, int link);
332 unsigned int addr; /* MII Address */
333 unsigned int data; /* MII Data */
336 struct stmmac_ring_mode_ops {
337 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
338 unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
339 void (*refill_desc3) (int bfsize, struct dma_desc *p);
340 void (*init_desc3) (int des3_as_data_buf, struct dma_desc *p);
341 void (*init_dma_chain) (struct dma_desc *des, dma_addr_t phy_addr,
343 void (*clean_desc3) (struct dma_desc *p);
344 int (*set_16kib_bfsize) (int mtu);
347 struct mac_device_info {
348 const struct stmmac_ops *mac;
349 const struct stmmac_desc_ops *desc;
350 const struct stmmac_dma_ops *dma;
351 const struct stmmac_ring_mode_ops *ring;
352 struct mii_regs mii; /* MII register Addresses */
353 struct mac_link link;
354 unsigned int synopsys_uid;
357 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr);
358 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);
360 extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
361 unsigned int high, unsigned int low);
362 extern void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
363 unsigned int high, unsigned int low);
365 extern void stmmac_set_mac(void __iomem *ioaddr, bool enable);
367 extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
368 extern const struct stmmac_ring_mode_ops ring_mode_ops;