bnx2x: Add 57712 support
[linux-3.10.git] / drivers / net / bnx2x / bnx2x_hsi.h
1 /* bnx2x_hsi.h: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2010 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  */
9 #ifndef BNX2X_HSI_H
10 #define BNX2X_HSI_H
11
12 #include "bnx2x_fw_defs.h"
13
14 struct license_key {
15         u32 reserved[6];
16
17 #if defined(__BIG_ENDIAN)
18         u16 max_iscsi_init_conn;
19         u16 max_iscsi_trgt_conn;
20 #elif defined(__LITTLE_ENDIAN)
21         u16 max_iscsi_trgt_conn;
22         u16 max_iscsi_init_conn;
23 #endif
24
25         u32 reserved_a[6];
26 };
27
28
29 #define PORT_0                          0
30 #define PORT_1                          1
31 #define PORT_MAX                        2
32
33 /****************************************************************************
34  * Shared HW configuration                                                  *
35  ****************************************************************************/
36 struct shared_hw_cfg {                                   /* NVRAM Offset */
37         /* Up to 16 bytes of NULL-terminated string */
38         u8  part_num[16];                                       /* 0x104 */
39
40         u32 config;                                             /* 0x114 */
41 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001
42 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT            0
43 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V             0x00000000
44 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V             0x00000001
45 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN        0x00000002
46
47 #define SHARED_HW_CFG_PORT_SWAP                     0x00000004
48
49 #define SHARED_HW_CFG_BEACON_WOL_EN                 0x00000008
50
51 #define SHARED_HW_CFG_MFW_SELECT_MASK               0x00000700
52 #define SHARED_HW_CFG_MFW_SELECT_SHIFT              8
53         /* Whatever MFW found in NVM
54            (if multiple found, priority order is: NC-SI, UMP, IPMI) */
55 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT            0x00000000
56 #define SHARED_HW_CFG_MFW_SELECT_NC_SI              0x00000100
57 #define SHARED_HW_CFG_MFW_SELECT_UMP                0x00000200
58 #define SHARED_HW_CFG_MFW_SELECT_IPMI               0x00000300
59         /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
60           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
61 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI   0x00000400
62         /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
63           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
64 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI     0x00000500
65         /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
66           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
67 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP    0x00000600
68
69 #define SHARED_HW_CFG_LED_MODE_MASK                 0x000f0000
70 #define SHARED_HW_CFG_LED_MODE_SHIFT                16
71 #define SHARED_HW_CFG_LED_MAC1                      0x00000000
72 #define SHARED_HW_CFG_LED_PHY1                      0x00010000
73 #define SHARED_HW_CFG_LED_PHY2                      0x00020000
74 #define SHARED_HW_CFG_LED_PHY3                      0x00030000
75 #define SHARED_HW_CFG_LED_MAC2                      0x00040000
76 #define SHARED_HW_CFG_LED_PHY4                      0x00050000
77 #define SHARED_HW_CFG_LED_PHY5                      0x00060000
78 #define SHARED_HW_CFG_LED_PHY6                      0x00070000
79 #define SHARED_HW_CFG_LED_MAC3                      0x00080000
80 #define SHARED_HW_CFG_LED_PHY7                      0x00090000
81 #define SHARED_HW_CFG_LED_PHY9                      0x000a0000
82 #define SHARED_HW_CFG_LED_PHY11                     0x000b0000
83 #define SHARED_HW_CFG_LED_MAC4                      0x000c0000
84 #define SHARED_HW_CFG_LED_PHY8                      0x000d0000
85 #define SHARED_HW_CFG_LED_EXTPHY1                   0x000e0000
86
87
88 #define SHARED_HW_CFG_AN_ENABLE_MASK                0x3f000000
89 #define SHARED_HW_CFG_AN_ENABLE_SHIFT               24
90 #define SHARED_HW_CFG_AN_ENABLE_CL37                0x01000000
91 #define SHARED_HW_CFG_AN_ENABLE_CL73                0x02000000
92 #define SHARED_HW_CFG_AN_ENABLE_BAM                 0x04000000
93 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION  0x08000000
94 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
95 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY          0x20000000
96
97         u32 config2;                                            /* 0x118 */
98         /* one time auto detect grace period (in sec) */
99 #define SHARED_HW_CFG_GRACE_PERIOD_MASK             0x000000ff
100 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT            0
101
102 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED             0x00000100
103
104         /* The default value for the core clock is 250MHz and it is
105            achieved by setting the clock change to 4 */
106 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK             0x00000e00
107 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT            9
108
109 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ           0x00000000
110 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ           0x00001000
111
112 #define SHARED_HW_CFG_HIDE_PORT1                    0x00002000
113
114         /*  The fan failure mechanism is usually related to the PHY type
115           since the power consumption of the board is determined by the PHY.
116           Currently, fan is required for most designs with SFX7101, BCM8727
117           and BCM8481. If a fan is not required for a board which uses one
118           of those PHYs, this field should be set to "Disabled". If a fan is
119           required for a different PHY type, this option should be set to
120           "Enabled".
121           The fan failure indication is expected on
122           SPIO5 */
123 #define SHARED_HW_CFG_FAN_FAILURE_MASK                        0x00180000
124 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT                       19
125 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE                    0x00000000
126 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED                    0x00080000
127 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED                     0x00100000
128
129         /* Set the MDC/MDIO access for the first external phy */
130 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK         0x1C000000
131 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT        26
132 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE     0x00000000
133 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0        0x04000000
134 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1        0x08000000
135 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH         0x0c000000
136 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED      0x10000000
137
138         /* Set the MDC/MDIO access for the second external phy */
139 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK         0xE0000000
140 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT        29
141 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE     0x00000000
142 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0        0x20000000
143 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1        0x40000000
144 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH         0x60000000
145 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED      0x80000000
146         u32 power_dissipated;                                   /* 0x11c */
147 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK            0xff000000
148 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT           24
149
150 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK         0x00ff0000
151 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT        16
152 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE      0x00000000
153 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT         0x00010000
154 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT        0x00020000
155 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT       0x00030000
156
157         u32 ump_nc_si_config;                                   /* 0x120 */
158 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003
159 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT      0
160 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC        0x00000000
161 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY        0x00000001
162 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII        0x00000000
163 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII       0x00000002
164
165 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK       0x00000f00
166 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT      8
167
168 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK   0x00ff0000
169 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT  16
170 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE   0x00000000
171 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
172
173         u32 board;                                              /* 0x124 */
174 #define SHARED_HW_CFG_BOARD_REV_MASK                0x00FF0000
175 #define SHARED_HW_CFG_BOARD_REV_SHIFT               16
176
177 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK          0x0F000000
178 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT         24
179
180 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0xF0000000
181 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT         28
182
183         u32 reserved;                                           /* 0x128 */
184
185 };
186
187
188 /****************************************************************************
189  * Port HW configuration                                                    *
190  ****************************************************************************/
191 struct port_hw_cfg {                        /* port 0: 0x12c  port 1: 0x2bc */
192
193         u32 pci_id;
194 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xffff0000
195 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000ffff
196
197         u32 pci_sub_id;
198 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xffff0000
199 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000ffff
200
201         u32 power_dissipated;
202 #define PORT_HW_CFG_POWER_DIS_D3_MASK               0xff000000
203 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT              24
204 #define PORT_HW_CFG_POWER_DIS_D2_MASK               0x00ff0000
205 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT              16
206 #define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000ff00
207 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT              8
208 #define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000ff
209 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT              0
210
211         u32 power_consumed;
212 #define PORT_HW_CFG_POWER_CONS_D3_MASK              0xff000000
213 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT             24
214 #define PORT_HW_CFG_POWER_CONS_D2_MASK              0x00ff0000
215 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT             16
216 #define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000ff00
217 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT             8
218 #define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000ff
219 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT             0
220
221         u32 mac_upper;
222 #define PORT_HW_CFG_UPPERMAC_MASK                   0x0000ffff
223 #define PORT_HW_CFG_UPPERMAC_SHIFT                  0
224         u32 mac_lower;
225
226         u32 iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
227         u32 iscsi_mac_lower;
228
229         u32 rdma_mac_upper;   /* Upper 16 bits are always zeroes */
230         u32 rdma_mac_lower;
231
232         u32 serdes_config;
233 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK           0x0000FFFF
234 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT          0
235
236 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK              0xFFFF0000
237 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT             16
238
239
240         u32 Reserved0[16];                                  /* 0x158 */
241
242         /*  for external PHY, or forced mode or during AN */
243         u16 xgxs_config_rx[4];                              /* 0x198 */
244
245         u16 xgxs_config_tx[4];                              /* 0x1A0 */
246
247         u32 Reserved1[57];                                  /* 0x1A8 */
248         u32 speed_capability_mask2;                         /* 0x28C */
249 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK                 0x0000FFFF
250 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT                0
251 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL             0x00000001
252 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__                    0x00000002
253 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___                   0x00000004
254 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL            0x00000008
255 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G                   0x00000010
256 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G             0x00000020
257 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G                  0x00000040
258 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12G                  0x00000080
259 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12_DOT_5G            0x00000100
260 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_13G                  0x00000200
261 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_15G                  0x00000400
262 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_16G                  0x00000800
263
264 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK                 0xFFFF0000
265 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT                16
266 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL             0x00010000
267 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__                    0x00020000
268 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___                   0x00040000
269 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL            0x00080000
270 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G                   0x00100000
271 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G             0x00200000
272 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G                  0x00400000
273 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12G                  0x00800000
274 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12_DOT_5G            0x01000000
275 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_13G                  0x02000000
276 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_15G                  0x04000000
277 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_16G                  0x08000000
278
279         /* In the case where two media types (e.g. copper and fiber) are
280           present and electrically active at the same time, PHY Selection
281           will determine which of the two PHYs will be designated as the
282           Active PHY and used for a connection to the network.  */
283         u32 multi_phy_config;                           /* 0x290 */
284 #define PORT_HW_CFG_PHY_SELECTION_MASK               0x00000007
285 #define PORT_HW_CFG_PHY_SELECTION_SHIFT              0
286 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT   0x00000000
287 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY          0x00000001
288 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY         0x00000002
289 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
290 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
291
292         /* When enabled, all second phy nvram parameters will be swapped
293           with the first phy parameters */
294 #define PORT_HW_CFG_PHY_SWAPPED_MASK                 0x00000008
295 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT                3
296 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED             0x00000000
297 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED              0x00000008
298
299
300         /* Address of the second external phy */
301         u32 external_phy_config2;                               /* 0x294 */
302 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK         0x000000FF
303 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT        0
304
305         /* The second XGXS external PHY type */
306 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK         0x0000FF00
307 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT        8
308 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT       0x00000000
309 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071      0x00000100
310 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072      0x00000200
311 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073      0x00000300
312 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705      0x00000400
313 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706      0x00000500
314 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726      0x00000600
315 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481      0x00000700
316 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101      0x00000800
317 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727      0x00000900
318 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC  0x00000a00
319 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823     0x00000b00
320 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640     0x00000c00
321 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833     0x00000d00
322 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE      0x0000fd00
323 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN     0x0000ff00
324
325         /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as
326           8706, 8726 and 8727) not all 4 values are needed. */
327         u16 xgxs_config2_rx[4];                         /* 0x296 */
328         u16 xgxs_config2_tx[4];                         /* 0x2A0 */
329
330         u32 lane_config;
331 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000ffff
332 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT             0
333
334 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK           0x000000ff
335 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT          0
336 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK           0x0000ff00
337 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT          8
338 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK       0x0000c000
339 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT      14
340         /* AN and forced */
341 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123          0x00001b1b
342         /* forced only */
343 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210          0x00001be4
344         /* forced only */
345 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120          0x0000d8d8
346         /* forced only */
347 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210          0x0000e4e4
348
349         u32 external_phy_config;
350 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK        0xff000000
351 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT       24
352 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT      0x00000000
353 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482     0x01000000
354 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN    0xff000000
355
356 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK        0x00ff0000
357 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT       16
358
359 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK          0x0000ff00
360 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT         8
361 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT        0x00000000
362 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071       0x00000100
363 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072       0x00000200
364 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073       0x00000300
365 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705       0x00000400
366 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706       0x00000500
367 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726       0x00000600
368 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481       0x00000700
369 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101       0x00000800
370 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727       0x00000900
371 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC   0x00000a00
372 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823      0x00000b00
373 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE       0x0000fd00
374 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN      0x0000ff00
375
376 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000ff
377 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT         0
378
379         u32 speed_capability_mask;
380 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK        0xffff0000
381 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT       16
382 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL    0x00010000
383 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF    0x00020000
384 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF   0x00040000
385 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL   0x00080000
386 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G          0x00100000
387 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G        0x00200000
388 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G         0x00400000
389 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G         0x00800000
390 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G       0x01000000
391 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G         0x02000000
392 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G         0x04000000
393 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G         0x08000000
394 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED    0xf0000000
395
396 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000ffff
397 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT       0
398 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL    0x00000001
399 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF    0x00000002
400 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF   0x00000004
401 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL   0x00000008
402 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G          0x00000010
403 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G        0x00000020
404 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G         0x00000040
405 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G         0x00000080
406 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G       0x00000100
407 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G         0x00000200
408 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G         0x00000400
409 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G         0x00000800
410 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED    0x0000f000
411
412         u32 reserved[2];
413
414 };
415
416
417 /****************************************************************************
418  * Shared Feature configuration                                             *
419  ****************************************************************************/
420 struct shared_feat_cfg {                                 /* NVRAM Offset */
421
422         u32 config;                                             /* 0x450 */
423 #define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001
424
425         /*  Use the values from options 47 and 48 instead of the HW default
426           values */
427 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED     0x00000000
428 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED      0x00000002
429
430 #define SHARED_FEATURE_MF_MODE_DISABLED             0x00000100
431
432 };
433
434
435 /****************************************************************************
436  * Port Feature configuration                                               *
437  ****************************************************************************/
438 struct port_feat_cfg {                      /* port 0: 0x454  port 1: 0x4c8 */
439
440         u32 config;
441 #define PORT_FEATURE_BAR1_SIZE_MASK                 0x0000000f
442 #define PORT_FEATURE_BAR1_SIZE_SHIFT                0
443 #define PORT_FEATURE_BAR1_SIZE_DISABLED             0x00000000
444 #define PORT_FEATURE_BAR1_SIZE_64K                  0x00000001
445 #define PORT_FEATURE_BAR1_SIZE_128K                 0x00000002
446 #define PORT_FEATURE_BAR1_SIZE_256K                 0x00000003
447 #define PORT_FEATURE_BAR1_SIZE_512K                 0x00000004
448 #define PORT_FEATURE_BAR1_SIZE_1M                   0x00000005
449 #define PORT_FEATURE_BAR1_SIZE_2M                   0x00000006
450 #define PORT_FEATURE_BAR1_SIZE_4M                   0x00000007
451 #define PORT_FEATURE_BAR1_SIZE_8M                   0x00000008
452 #define PORT_FEATURE_BAR1_SIZE_16M                  0x00000009
453 #define PORT_FEATURE_BAR1_SIZE_32M                  0x0000000a
454 #define PORT_FEATURE_BAR1_SIZE_64M                  0x0000000b
455 #define PORT_FEATURE_BAR1_SIZE_128M                 0x0000000c
456 #define PORT_FEATURE_BAR1_SIZE_256M                 0x0000000d
457 #define PORT_FEATURE_BAR1_SIZE_512M                 0x0000000e
458 #define PORT_FEATURE_BAR1_SIZE_1G                   0x0000000f
459 #define PORT_FEATURE_BAR2_SIZE_MASK                 0x000000f0
460 #define PORT_FEATURE_BAR2_SIZE_SHIFT                4
461 #define PORT_FEATURE_BAR2_SIZE_DISABLED             0x00000000
462 #define PORT_FEATURE_BAR2_SIZE_64K                  0x00000010
463 #define PORT_FEATURE_BAR2_SIZE_128K                 0x00000020
464 #define PORT_FEATURE_BAR2_SIZE_256K                 0x00000030
465 #define PORT_FEATURE_BAR2_SIZE_512K                 0x00000040
466 #define PORT_FEATURE_BAR2_SIZE_1M                   0x00000050
467 #define PORT_FEATURE_BAR2_SIZE_2M                   0x00000060
468 #define PORT_FEATURE_BAR2_SIZE_4M                   0x00000070
469 #define PORT_FEATURE_BAR2_SIZE_8M                   0x00000080
470 #define PORT_FEATURE_BAR2_SIZE_16M                  0x00000090
471 #define PORT_FEATURE_BAR2_SIZE_32M                  0x000000a0
472 #define PORT_FEATURE_BAR2_SIZE_64M                  0x000000b0
473 #define PORT_FEATURE_BAR2_SIZE_128M                 0x000000c0
474 #define PORT_FEATURE_BAR2_SIZE_256M                 0x000000d0
475 #define PORT_FEATURE_BAR2_SIZE_512M                 0x000000e0
476 #define PORT_FEATURE_BAR2_SIZE_1G                   0x000000f0
477 #define PORT_FEATURE_EN_SIZE_MASK                   0x07000000
478 #define PORT_FEATURE_EN_SIZE_SHIFT                  24
479 #define PORT_FEATURE_WOL_ENABLED                    0x01000000
480 #define PORT_FEATURE_MBA_ENABLED                    0x02000000
481 #define PORT_FEATURE_MFW_ENABLED                    0x04000000
482
483         /* Reserved bits: 28-29 */
484         /*  Check the optic vendor via i2c against a list of approved modules
485           in a separate nvram image */
486 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK                   0xE0000000
487 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT                  29
488 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT         0x00000000
489 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER       0x20000000
490 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG            0x40000000
491 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN             0x60000000
492
493
494         u32 wol_config;
495         /* Default is used when driver sets to "auto" mode */
496 #define PORT_FEATURE_WOL_DEFAULT_MASK               0x00000003
497 #define PORT_FEATURE_WOL_DEFAULT_SHIFT              0
498 #define PORT_FEATURE_WOL_DEFAULT_DISABLE            0x00000000
499 #define PORT_FEATURE_WOL_DEFAULT_MAGIC              0x00000001
500 #define PORT_FEATURE_WOL_DEFAULT_ACPI               0x00000002
501 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI     0x00000003
502 #define PORT_FEATURE_WOL_RES_PAUSE_CAP              0x00000004
503 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP         0x00000008
504 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010
505
506         u32 mba_config;
507 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000003
508 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT      0
509 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE        0x00000000
510 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL        0x00000001
511 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP      0x00000002
512 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB     0x00000003
513 #define PORT_FEATURE_MBA_RES_PAUSE_CAP              0x00000100
514 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP         0x00000200
515 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x00000400
516 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S              0x00000000
517 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B              0x00000800
518 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK          0x000ff000
519 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT         12
520 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED      0x00000000
521 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K            0x00001000
522 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K            0x00002000
523 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K            0x00003000
524 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K           0x00004000
525 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K           0x00005000
526 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K           0x00006000
527 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K          0x00007000
528 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K          0x00008000
529 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K          0x00009000
530 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M            0x0000a000
531 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M            0x0000b000
532 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M            0x0000c000
533 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M            0x0000d000
534 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M           0x0000e000
535 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M           0x0000f000
536 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK           0x00f00000
537 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT          20
538 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x03000000
539 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT       24
540 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO        0x00000000
541 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS         0x01000000
542 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H      0x02000000
543 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H      0x03000000
544 #define PORT_FEATURE_MBA_LINK_SPEED_MASK            0x3c000000
545 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT           26
546 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO            0x00000000
547 #define PORT_FEATURE_MBA_LINK_SPEED_10HD            0x04000000
548 #define PORT_FEATURE_MBA_LINK_SPEED_10FD            0x08000000
549 #define PORT_FEATURE_MBA_LINK_SPEED_100HD           0x0c000000
550 #define PORT_FEATURE_MBA_LINK_SPEED_100FD           0x10000000
551 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS           0x14000000
552 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS         0x18000000
553 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4      0x1c000000
554 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4      0x20000000
555 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR       0x24000000
556 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS          0x28000000
557 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS        0x2c000000
558 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS          0x30000000
559 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS          0x34000000
560 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS          0x38000000
561
562         u32 bmc_config;
563 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT      0x00000000
564 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN           0x00000001
565
566         u32 mba_vlan_cfg;
567 #define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000ffff
568 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT             0
569 #define PORT_FEATURE_MBA_VLAN_EN                    0x00010000
570
571         u32 resource_cfg;
572 #define PORT_FEATURE_RESOURCE_CFG_VALID             0x00000001
573 #define PORT_FEATURE_RESOURCE_CFG_DIAG              0x00000002
574 #define PORT_FEATURE_RESOURCE_CFG_L2                0x00000004
575 #define PORT_FEATURE_RESOURCE_CFG_ISCSI             0x00000008
576 #define PORT_FEATURE_RESOURCE_CFG_RDMA              0x00000010
577
578         u32 smbus_config;
579         /* Obsolete */
580 #define PORT_FEATURE_SMBUS_EN                       0x00000001
581 #define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe
582 #define PORT_FEATURE_SMBUS_ADDR_SHIFT               1
583
584         u32 reserved1;
585
586         u32 link_config;    /* Used as HW defaults for the driver */
587 #define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x03000000
588 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT         24
589         /* (forced) low speed switch (< 10G) */
590 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH           0x00000000
591         /* (forced) high speed switch (>= 10G) */
592 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH          0x01000000
593 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT         0x02000000
594 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT     0x03000000
595
596 #define PORT_FEATURE_LINK_SPEED_MASK                0x000f0000
597 #define PORT_FEATURE_LINK_SPEED_SHIFT               16
598 #define PORT_FEATURE_LINK_SPEED_AUTO                0x00000000
599 #define PORT_FEATURE_LINK_SPEED_10M_FULL            0x00010000
600 #define PORT_FEATURE_LINK_SPEED_10M_HALF            0x00020000
601 #define PORT_FEATURE_LINK_SPEED_100M_HALF           0x00030000
602 #define PORT_FEATURE_LINK_SPEED_100M_FULL           0x00040000
603 #define PORT_FEATURE_LINK_SPEED_1G                  0x00050000
604 #define PORT_FEATURE_LINK_SPEED_2_5G                0x00060000
605 #define PORT_FEATURE_LINK_SPEED_10G_CX4             0x00070000
606 #define PORT_FEATURE_LINK_SPEED_10G_KX4             0x00080000
607 #define PORT_FEATURE_LINK_SPEED_10G_KR              0x00090000
608 #define PORT_FEATURE_LINK_SPEED_12G                 0x000a0000
609 #define PORT_FEATURE_LINK_SPEED_12_5G               0x000b0000
610 #define PORT_FEATURE_LINK_SPEED_13G                 0x000c0000
611 #define PORT_FEATURE_LINK_SPEED_15G                 0x000d0000
612 #define PORT_FEATURE_LINK_SPEED_16G                 0x000e0000
613
614 #define PORT_FEATURE_FLOW_CONTROL_MASK              0x00000700
615 #define PORT_FEATURE_FLOW_CONTROL_SHIFT             8
616 #define PORT_FEATURE_FLOW_CONTROL_AUTO              0x00000000
617 #define PORT_FEATURE_FLOW_CONTROL_TX                0x00000100
618 #define PORT_FEATURE_FLOW_CONTROL_RX                0x00000200
619 #define PORT_FEATURE_FLOW_CONTROL_BOTH              0x00000300
620 #define PORT_FEATURE_FLOW_CONTROL_NONE              0x00000400
621
622         /* The default for MCP link configuration,
623         uses the same defines as link_config */
624         u32 mfw_wol_link_cfg;
625         /* The default for the driver of the second external phy,
626         uses the same defines as link_config */
627         u32 link_config2;                                       /* 0x47C */
628
629         /* The default for MCP of the second external phy,
630         uses the same defines as link_config */
631         u32 mfw_wol_link_cfg2;                          /* 0x480 */
632
633         u32 Reserved2[17];                                      /* 0x484 */
634
635 };
636
637
638 /****************************************************************************
639  * Device Information                                                       *
640  ****************************************************************************/
641 struct shm_dev_info {                                               /* size */
642
643         u32    bc_rev; /* 8 bits each: major, minor, build */          /* 4 */
644
645         struct shared_hw_cfg     shared_hw_config;                    /* 40 */
646
647         struct port_hw_cfg       port_hw_config[PORT_MAX];     /* 400*2=800 */
648
649         struct shared_feat_cfg   shared_feature_config;                /* 4 */
650
651         struct port_feat_cfg     port_feature_config[PORT_MAX];/* 116*2=232 */
652
653 };
654
655
656 #define FUNC_0                          0
657 #define FUNC_1                          1
658 #define FUNC_2                          2
659 #define FUNC_3                          3
660 #define FUNC_4                          4
661 #define FUNC_5                          5
662 #define FUNC_6                          6
663 #define FUNC_7                          7
664 #define E1_FUNC_MAX                     2
665 #define E1H_FUNC_MAX                    8
666 #define E2_FUNC_MAX         4   /* per path */
667
668 #define VN_0                            0
669 #define VN_1                            1
670 #define VN_2                            2
671 #define VN_3                            3
672 #define E1VN_MAX                        1
673 #define E1HVN_MAX                       4
674
675
676 /* This value (in milliseconds) determines the frequency of the driver
677  * issuing the PULSE message code.  The firmware monitors this periodic
678  * pulse to determine when to switch to an OS-absent mode. */
679 #define DRV_PULSE_PERIOD_MS             250
680
681 /* This value (in milliseconds) determines how long the driver should
682  * wait for an acknowledgement from the firmware before timing out.  Once
683  * the firmware has timed out, the driver will assume there is no firmware
684  * running and there won't be any firmware-driver synchronization during a
685  * driver reset. */
686 #define FW_ACK_TIME_OUT_MS              5000
687
688 #define FW_ACK_POLL_TIME_MS             1
689
690 #define FW_ACK_NUM_OF_POLL      (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
691
692 /* LED Blink rate that will achieve ~15.9Hz */
693 #define LED_BLINK_RATE_VAL              480
694
695 /****************************************************************************
696  * Driver <-> FW Mailbox                                                    *
697  ****************************************************************************/
698 struct drv_port_mb {
699
700         u32 link_status;
701         /* Driver should update this field on any link change event */
702
703 #define LINK_STATUS_LINK_FLAG_MASK                      0x00000001
704 #define LINK_STATUS_LINK_UP                             0x00000001
705 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK               0x0000001E
706 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE    (0<<1)
707 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD              (1<<1)
708 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD              (2<<1)
709 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD            (3<<1)
710 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4              (4<<1)
711 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD            (5<<1)
712 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            (6<<1)
713 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (7<<1)
714 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD            (7<<1)
715 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD            (8<<1)
716 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD            (9<<1)
717 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD            (9<<1)
718 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD             (10<<1)
719 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD             (10<<1)
720 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD             (11<<1)
721 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD             (11<<1)
722 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD           (12<<1)
723 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD           (12<<1)
724 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD             (13<<1)
725 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD             (13<<1)
726 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD             (14<<1)
727 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD             (14<<1)
728 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD             (15<<1)
729 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD             (15<<1)
730
731 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK            0x00000020
732 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED              0x00000020
733
734 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE             0x00000040
735 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK        0x00000080
736 #define LINK_STATUS_PARALLEL_DETECTION_USED             0x00000080
737
738 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
739 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
740 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE          0x00000800
741 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE        0x00001000
742 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE        0x00002000
743 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE          0x00004000
744 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE          0x00008000
745
746 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK           0x00010000
747 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00010000
748
749 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK           0x00020000
750 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00020000
751
752 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
753 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0<<18)
754 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1<<18)
755 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2<<18)
756 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3<<18)
757
758 #define LINK_STATUS_SERDES_LINK                         0x00100000
759
760 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE        0x00200000
761 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE        0x00400000
762 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE         0x00800000
763 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE         0x01000000
764 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE       0x02000000
765 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE         0x04000000
766 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE         0x08000000
767 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE         0x10000000
768
769         u32 port_stx;
770
771         u32 stat_nig_timer;
772
773         /* MCP firmware does not use this field */
774         u32 ext_phy_fw_version;
775
776 };
777
778
779 struct drv_func_mb {
780
781         u32 drv_mb_header;
782 #define DRV_MSG_CODE_MASK                               0xffff0000
783 #define DRV_MSG_CODE_LOAD_REQ                           0x10000000
784 #define DRV_MSG_CODE_LOAD_DONE                          0x11000000
785 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN                  0x20000000
786 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS                 0x20010000
787 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP                 0x20020000
788 #define DRV_MSG_CODE_UNLOAD_DONE                        0x21000000
789 #define DRV_MSG_CODE_DCC_OK                             0x30000000
790 #define DRV_MSG_CODE_DCC_FAILURE                        0x31000000
791 #define DRV_MSG_CODE_DIAG_ENTER_REQ                     0x50000000
792 #define DRV_MSG_CODE_DIAG_EXIT_REQ                      0x60000000
793 #define DRV_MSG_CODE_VALIDATE_KEY                       0x70000000
794 #define DRV_MSG_CODE_GET_CURR_KEY                       0x80000000
795 #define DRV_MSG_CODE_GET_UPGRADE_KEY                    0x81000000
796 #define DRV_MSG_CODE_GET_MANUF_KEY                      0x82000000
797 #define DRV_MSG_CODE_LOAD_L2B_PRAM                      0x90000000
798         /*
799          * The optic module verification commands require bootcode
800          * v5.0.6 or later
801          */
802 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL     0xa0000000
803 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL     0x00050006
804         /*
805          * The specific optic module verification command requires bootcode
806          * v5.2.12 or later
807          */
808 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL      0xa1000000
809 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL      0x00050234
810
811 #define BIOS_MSG_CODE_LIC_CHALLENGE                     0xff010000
812 #define BIOS_MSG_CODE_LIC_RESPONSE                      0xff020000
813 #define BIOS_MSG_CODE_VIRT_MAC_PRIM                     0xff030000
814 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI                    0xff040000
815
816 #define DRV_MSG_SEQ_NUMBER_MASK                         0x0000ffff
817
818         u32 drv_mb_param;
819
820         u32 fw_mb_header;
821 #define FW_MSG_CODE_MASK                                0xffff0000
822 #define FW_MSG_CODE_DRV_LOAD_COMMON                     0x10100000
823 #define FW_MSG_CODE_DRV_LOAD_PORT                       0x10110000
824 #define FW_MSG_CODE_DRV_LOAD_FUNCTION                   0x10120000
825         /* Load common chip is supported from bc 6.0.0  */
826 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP       0x00060000
827 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP        0x10130000
828 #define FW_MSG_CODE_DRV_LOAD_REFUSED                    0x10200000
829 #define FW_MSG_CODE_DRV_LOAD_DONE                       0x11100000
830 #define FW_MSG_CODE_DRV_UNLOAD_COMMON                   0x20100000
831 #define FW_MSG_CODE_DRV_UNLOAD_PORT                     0x20110000
832 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION                 0x20120000
833 #define FW_MSG_CODE_DRV_UNLOAD_DONE                     0x21100000
834 #define FW_MSG_CODE_DCC_DONE                            0x30100000
835 #define FW_MSG_CODE_DIAG_ENTER_DONE                     0x50100000
836 #define FW_MSG_CODE_DIAG_REFUSE                         0x50200000
837 #define FW_MSG_CODE_DIAG_EXIT_DONE                      0x60100000
838 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS                0x70100000
839 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE                0x70200000
840 #define FW_MSG_CODE_GET_KEY_DONE                        0x80100000
841 #define FW_MSG_CODE_NO_KEY                              0x80f00000
842 #define FW_MSG_CODE_LIC_INFO_NOT_READY                  0x80f80000
843 #define FW_MSG_CODE_L2B_PRAM_LOADED                     0x90100000
844 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE             0x90210000
845 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE             0x90220000
846 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE             0x90230000
847 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE             0x90240000
848 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS                0xa0100000
849 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG              0xa0200000
850 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED             0xa0300000
851
852 #define FW_MSG_CODE_LIC_CHALLENGE                       0xff010000
853 #define FW_MSG_CODE_LIC_RESPONSE                        0xff020000
854 #define FW_MSG_CODE_VIRT_MAC_PRIM                       0xff030000
855 #define FW_MSG_CODE_VIRT_MAC_ISCSI                      0xff040000
856
857 #define FW_MSG_SEQ_NUMBER_MASK                          0x0000ffff
858
859         u32 fw_mb_param;
860
861         u32 drv_pulse_mb;
862 #define DRV_PULSE_SEQ_MASK                              0x00007fff
863 #define DRV_PULSE_SYSTEM_TIME_MASK                      0xffff0000
864         /* The system time is in the format of
865          * (year-2001)*12*32 + month*32 + day. */
866 #define DRV_PULSE_ALWAYS_ALIVE                          0x00008000
867         /* Indicate to the firmware not to go into the
868          * OS-absent when it is not getting driver pulse.
869          * This is used for debugging as well for PXE(MBA). */
870
871         u32 mcp_pulse_mb;
872 #define MCP_PULSE_SEQ_MASK                              0x00007fff
873 #define MCP_PULSE_ALWAYS_ALIVE                          0x00008000
874         /* Indicates to the driver not to assert due to lack
875          * of MCP response */
876 #define MCP_EVENT_MASK                                  0xffff0000
877 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ                0x00010000
878
879         u32 iscsi_boot_signature;
880         u32 iscsi_boot_block_offset;
881
882         u32 drv_status;
883 #define DRV_STATUS_PMF                                  0x00000001
884
885 #define DRV_STATUS_DCC_EVENT_MASK                       0x0000ff00
886 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF                0x00000100
887 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION             0x00000200
888 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS               0x00000400
889 #define DRV_STATUS_DCC_RESERVED1                        0x00000800
890 #define DRV_STATUS_DCC_SET_PROTOCOL                     0x00001000
891 #define DRV_STATUS_DCC_SET_PRIORITY                     0x00002000
892
893         u32 virt_mac_upper;
894 #define VIRT_MAC_SIGN_MASK                              0xffff0000
895 #define VIRT_MAC_SIGNATURE                              0x564d0000
896         u32 virt_mac_lower;
897
898 };
899
900
901 /****************************************************************************
902  * Management firmware state                                                *
903  ****************************************************************************/
904 /* Allocate 440 bytes for management firmware */
905 #define MGMTFW_STATE_WORD_SIZE                              110
906
907 struct mgmtfw_state {
908         u32 opaque[MGMTFW_STATE_WORD_SIZE];
909 };
910
911
912 /****************************************************************************
913  * Multi-Function configuration                                             *
914  ****************************************************************************/
915 struct shared_mf_cfg {
916
917         u32 clp_mb;
918 #define SHARED_MF_CLP_SET_DEFAULT                   0x00000000
919         /* set by CLP */
920 #define SHARED_MF_CLP_EXIT                          0x00000001
921         /* set by MCP */
922 #define SHARED_MF_CLP_EXIT_DONE                     0x00010000
923
924 };
925
926 struct port_mf_cfg {
927
928         u32 dynamic_cfg;        /* device control channel */
929 #define PORT_MF_CFG_E1HOV_TAG_MASK                  0x0000ffff
930 #define PORT_MF_CFG_E1HOV_TAG_SHIFT                 0
931 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT               PORT_MF_CFG_E1HOV_TAG_MASK
932
933         u32 reserved[3];
934
935 };
936
937 struct func_mf_cfg {
938
939         u32 config;
940         /* E/R/I/D */
941         /* function 0 of each port cannot be hidden */
942 #define FUNC_MF_CFG_FUNC_HIDE                       0x00000001
943
944 #define FUNC_MF_CFG_PROTOCOL_MASK                   0x00000007
945 #define FUNC_MF_CFG_PROTOCOL_ETHERNET               0x00000002
946 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA     0x00000004
947 #define FUNC_MF_CFG_PROTOCOL_ISCSI                  0x00000006
948 #define FUNC_MF_CFG_PROTOCOL_DEFAULT\
949         FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
950
951 #define FUNC_MF_CFG_FUNC_DISABLED                   0x00000008
952
953         /* PRI */
954         /* 0 - low priority, 3 - high priority */
955 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK          0x00000300
956 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT         8
957 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT       0x00000000
958
959         /* MINBW, MAXBW */
960         /* value range - 0..100, increments in 100Mbps */
961 #define FUNC_MF_CFG_MIN_BW_MASK                     0x00ff0000
962 #define FUNC_MF_CFG_MIN_BW_SHIFT                    16
963 #define FUNC_MF_CFG_MIN_BW_DEFAULT                  0x00000000
964 #define FUNC_MF_CFG_MAX_BW_MASK                     0xff000000
965 #define FUNC_MF_CFG_MAX_BW_SHIFT                    24
966 #define FUNC_MF_CFG_MAX_BW_DEFAULT                  0x64000000
967
968         u32 mac_upper;          /* MAC */
969 #define FUNC_MF_CFG_UPPERMAC_MASK                   0x0000ffff
970 #define FUNC_MF_CFG_UPPERMAC_SHIFT                  0
971 #define FUNC_MF_CFG_UPPERMAC_DEFAULT                FUNC_MF_CFG_UPPERMAC_MASK
972         u32 mac_lower;
973 #define FUNC_MF_CFG_LOWERMAC_DEFAULT                0xffffffff
974
975         u32 e1hov_tag;  /* VNI */
976 #define FUNC_MF_CFG_E1HOV_TAG_MASK                  0x0000ffff
977 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT                 0
978 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT               FUNC_MF_CFG_E1HOV_TAG_MASK
979
980         u32 reserved[2];
981
982 };
983
984 struct mf_cfg {
985
986         struct shared_mf_cfg    shared_mf_config;
987         struct port_mf_cfg      port_mf_config[PORT_MAX];
988         struct func_mf_cfg      func_mf_config[E1H_FUNC_MAX];
989
990 };
991
992
993 /****************************************************************************
994  * Shared Memory Region                                                     *
995  ****************************************************************************/
996 struct shmem_region {                          /*   SharedMem Offset (size) */
997
998         u32                     validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
999 #define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
1000 #define SHR_MEM_FORMAT_REV_MASK                     0xff000000
1001         /* validity bits */
1002 #define SHR_MEM_VALIDITY_PCI_CFG                    0x00100000
1003 #define SHR_MEM_VALIDITY_MB                         0x00200000
1004 #define SHR_MEM_VALIDITY_DEV_INFO                   0x00400000
1005 #define SHR_MEM_VALIDITY_RESERVED                   0x00000007
1006         /* One licensing bit should be set */
1007 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
1008 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
1009 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
1010 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
1011         /* Active MFW */
1012 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
1013 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x00000040
1014 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x00000080
1015 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c0
1016 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
1017 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
1018
1019         struct shm_dev_info     dev_info;                /* 0x8     (0x438) */
1020
1021         struct license_key      drv_lic_key[PORT_MAX];  /* 0x440 (52*2=0x68) */
1022
1023         /* FW information (for internal FW use) */
1024         u32                     fw_info_fio_offset;    /* 0x4a8       (0x4) */
1025         struct mgmtfw_state     mgmtfw_state;          /* 0x4ac     (0x1b8) */
1026
1027         struct drv_port_mb      port_mb[PORT_MAX];     /* 0x664 (16*2=0x20) */
1028         struct drv_func_mb      func_mb[];             /* 0x684
1029                                              (44*2/4/8=0x58/0xb0/0x160) */
1030
1031 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1032
1033 struct fw_flr_ack {
1034         u32     pf_ack;
1035         u32     vf_ack[1];
1036         u32     iov_dis_ack;
1037 };
1038
1039 struct fw_flr_mb {
1040         u32     aggint;
1041         u32     opgen_addr;
1042         struct  fw_flr_ack ack;
1043 };
1044
1045
1046 struct shmem2_region {
1047
1048         u32                     size;
1049
1050         u32                     dcc_support;
1051 #define SHMEM_DCC_SUPPORT_NONE                      0x00000000
1052 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV     0x00000001
1053 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV  0x00000004
1054 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV    0x00000008
1055 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV          0x00000040
1056 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV          0x00000080
1057 #define SHMEM_DCC_SUPPORT_DEFAULT                   SHMEM_DCC_SUPPORT_NONE
1058         u32 ext_phy_fw_version2[PORT_MAX];
1059         /*
1060          * For backwards compatibility, if the mf_cfg_addr does not exist
1061          * (the size filed is smaller than 0xc) the mf_cfg resides at the
1062          * end of struct shmem_region
1063      */
1064         u32     mf_cfg_addr;
1065 #define SHMEM_MF_CFG_ADDR_NONE                      0x00000000
1066
1067         struct fw_flr_mb flr_mb;
1068         u32     reserved[3];
1069         /*
1070          * The other shmemX_base_addr holds the other path's shmem address
1071          * required for example in case of common phy init, or for path1 to know
1072          * the address of mcp debug trace which is located in offset from shmem
1073          * of path0
1074          */
1075         u32 other_shmem_base_addr;
1076         u32 other_shmem2_base_addr;
1077 };
1078
1079
1080 struct emac_stats {
1081     u32     rx_stat_ifhcinoctets;
1082     u32     rx_stat_ifhcinbadoctets;
1083     u32     rx_stat_etherstatsfragments;
1084     u32     rx_stat_ifhcinucastpkts;
1085     u32     rx_stat_ifhcinmulticastpkts;
1086     u32     rx_stat_ifhcinbroadcastpkts;
1087     u32     rx_stat_dot3statsfcserrors;
1088     u32     rx_stat_dot3statsalignmenterrors;
1089     u32     rx_stat_dot3statscarriersenseerrors;
1090     u32     rx_stat_xonpauseframesreceived;
1091     u32     rx_stat_xoffpauseframesreceived;
1092     u32     rx_stat_maccontrolframesreceived;
1093     u32     rx_stat_xoffstateentered;
1094     u32     rx_stat_dot3statsframestoolong;
1095     u32     rx_stat_etherstatsjabbers;
1096     u32     rx_stat_etherstatsundersizepkts;
1097     u32     rx_stat_etherstatspkts64octets;
1098     u32     rx_stat_etherstatspkts65octetsto127octets;
1099     u32     rx_stat_etherstatspkts128octetsto255octets;
1100     u32     rx_stat_etherstatspkts256octetsto511octets;
1101     u32     rx_stat_etherstatspkts512octetsto1023octets;
1102     u32     rx_stat_etherstatspkts1024octetsto1522octets;
1103     u32     rx_stat_etherstatspktsover1522octets;
1104
1105     u32     rx_stat_falsecarriererrors;
1106
1107     u32     tx_stat_ifhcoutoctets;
1108     u32     tx_stat_ifhcoutbadoctets;
1109     u32     tx_stat_etherstatscollisions;
1110     u32     tx_stat_outxonsent;
1111     u32     tx_stat_outxoffsent;
1112     u32     tx_stat_flowcontroldone;
1113     u32     tx_stat_dot3statssinglecollisionframes;
1114     u32     tx_stat_dot3statsmultiplecollisionframes;
1115     u32     tx_stat_dot3statsdeferredtransmissions;
1116     u32     tx_stat_dot3statsexcessivecollisions;
1117     u32     tx_stat_dot3statslatecollisions;
1118     u32     tx_stat_ifhcoutucastpkts;
1119     u32     tx_stat_ifhcoutmulticastpkts;
1120     u32     tx_stat_ifhcoutbroadcastpkts;
1121     u32     tx_stat_etherstatspkts64octets;
1122     u32     tx_stat_etherstatspkts65octetsto127octets;
1123     u32     tx_stat_etherstatspkts128octetsto255octets;
1124     u32     tx_stat_etherstatspkts256octetsto511octets;
1125     u32     tx_stat_etherstatspkts512octetsto1023octets;
1126     u32     tx_stat_etherstatspkts1024octetsto1522octets;
1127     u32     tx_stat_etherstatspktsover1522octets;
1128     u32     tx_stat_dot3statsinternalmactransmiterrors;
1129 };
1130
1131
1132 struct bmac1_stats {
1133     u32     tx_stat_gtpkt_lo;
1134     u32     tx_stat_gtpkt_hi;
1135     u32     tx_stat_gtxpf_lo;
1136     u32     tx_stat_gtxpf_hi;
1137     u32     tx_stat_gtfcs_lo;
1138     u32     tx_stat_gtfcs_hi;
1139     u32     tx_stat_gtmca_lo;
1140     u32     tx_stat_gtmca_hi;
1141     u32     tx_stat_gtbca_lo;
1142     u32     tx_stat_gtbca_hi;
1143     u32     tx_stat_gtfrg_lo;
1144     u32     tx_stat_gtfrg_hi;
1145     u32     tx_stat_gtovr_lo;
1146     u32     tx_stat_gtovr_hi;
1147     u32     tx_stat_gt64_lo;
1148     u32     tx_stat_gt64_hi;
1149     u32     tx_stat_gt127_lo;
1150     u32     tx_stat_gt127_hi;
1151     u32     tx_stat_gt255_lo;
1152     u32     tx_stat_gt255_hi;
1153     u32     tx_stat_gt511_lo;
1154     u32     tx_stat_gt511_hi;
1155     u32     tx_stat_gt1023_lo;
1156     u32     tx_stat_gt1023_hi;
1157     u32     tx_stat_gt1518_lo;
1158     u32     tx_stat_gt1518_hi;
1159     u32     tx_stat_gt2047_lo;
1160     u32     tx_stat_gt2047_hi;
1161     u32     tx_stat_gt4095_lo;
1162     u32     tx_stat_gt4095_hi;
1163     u32     tx_stat_gt9216_lo;
1164     u32     tx_stat_gt9216_hi;
1165     u32     tx_stat_gt16383_lo;
1166     u32     tx_stat_gt16383_hi;
1167     u32     tx_stat_gtmax_lo;
1168     u32     tx_stat_gtmax_hi;
1169     u32     tx_stat_gtufl_lo;
1170     u32     tx_stat_gtufl_hi;
1171     u32     tx_stat_gterr_lo;
1172     u32     tx_stat_gterr_hi;
1173     u32     tx_stat_gtbyt_lo;
1174     u32     tx_stat_gtbyt_hi;
1175
1176     u32     rx_stat_gr64_lo;
1177     u32     rx_stat_gr64_hi;
1178     u32     rx_stat_gr127_lo;
1179     u32     rx_stat_gr127_hi;
1180     u32     rx_stat_gr255_lo;
1181     u32     rx_stat_gr255_hi;
1182     u32     rx_stat_gr511_lo;
1183     u32     rx_stat_gr511_hi;
1184     u32     rx_stat_gr1023_lo;
1185     u32     rx_stat_gr1023_hi;
1186     u32     rx_stat_gr1518_lo;
1187     u32     rx_stat_gr1518_hi;
1188     u32     rx_stat_gr2047_lo;
1189     u32     rx_stat_gr2047_hi;
1190     u32     rx_stat_gr4095_lo;
1191     u32     rx_stat_gr4095_hi;
1192     u32     rx_stat_gr9216_lo;
1193     u32     rx_stat_gr9216_hi;
1194     u32     rx_stat_gr16383_lo;
1195     u32     rx_stat_gr16383_hi;
1196     u32     rx_stat_grmax_lo;
1197     u32     rx_stat_grmax_hi;
1198     u32     rx_stat_grpkt_lo;
1199     u32     rx_stat_grpkt_hi;
1200     u32     rx_stat_grfcs_lo;
1201     u32     rx_stat_grfcs_hi;
1202     u32     rx_stat_grmca_lo;
1203     u32     rx_stat_grmca_hi;
1204     u32     rx_stat_grbca_lo;
1205     u32     rx_stat_grbca_hi;
1206     u32     rx_stat_grxcf_lo;
1207     u32     rx_stat_grxcf_hi;
1208     u32     rx_stat_grxpf_lo;
1209     u32     rx_stat_grxpf_hi;
1210     u32     rx_stat_grxuo_lo;
1211     u32     rx_stat_grxuo_hi;
1212     u32     rx_stat_grjbr_lo;
1213     u32     rx_stat_grjbr_hi;
1214     u32     rx_stat_grovr_lo;
1215     u32     rx_stat_grovr_hi;
1216     u32     rx_stat_grflr_lo;
1217     u32     rx_stat_grflr_hi;
1218     u32     rx_stat_grmeg_lo;
1219     u32     rx_stat_grmeg_hi;
1220     u32     rx_stat_grmeb_lo;
1221     u32     rx_stat_grmeb_hi;
1222     u32     rx_stat_grbyt_lo;
1223     u32     rx_stat_grbyt_hi;
1224     u32     rx_stat_grund_lo;
1225     u32     rx_stat_grund_hi;
1226     u32     rx_stat_grfrg_lo;
1227     u32     rx_stat_grfrg_hi;
1228     u32     rx_stat_grerb_lo;
1229     u32     rx_stat_grerb_hi;
1230     u32     rx_stat_grfre_lo;
1231     u32     rx_stat_grfre_hi;
1232     u32     rx_stat_gripj_lo;
1233     u32     rx_stat_gripj_hi;
1234 };
1235
1236 struct bmac2_stats {
1237         u32     tx_stat_gtpk_lo; /* gtpok */
1238         u32     tx_stat_gtpk_hi; /* gtpok */
1239         u32     tx_stat_gtxpf_lo; /* gtpf */
1240         u32     tx_stat_gtxpf_hi; /* gtpf */
1241         u32     tx_stat_gtpp_lo; /* NEW BMAC2 */
1242         u32     tx_stat_gtpp_hi; /* NEW BMAC2 */
1243         u32     tx_stat_gtfcs_lo;
1244         u32     tx_stat_gtfcs_hi;
1245         u32     tx_stat_gtuca_lo; /* NEW BMAC2 */
1246         u32     tx_stat_gtuca_hi; /* NEW BMAC2 */
1247         u32     tx_stat_gtmca_lo;
1248         u32     tx_stat_gtmca_hi;
1249         u32     tx_stat_gtbca_lo;
1250         u32     tx_stat_gtbca_hi;
1251         u32     tx_stat_gtovr_lo;
1252         u32     tx_stat_gtovr_hi;
1253         u32     tx_stat_gtfrg_lo;
1254         u32     tx_stat_gtfrg_hi;
1255         u32     tx_stat_gtpkt1_lo; /* gtpkt */
1256         u32     tx_stat_gtpkt1_hi; /* gtpkt */
1257         u32     tx_stat_gt64_lo;
1258         u32     tx_stat_gt64_hi;
1259         u32     tx_stat_gt127_lo;
1260         u32     tx_stat_gt127_hi;
1261         u32     tx_stat_gt255_lo;
1262         u32     tx_stat_gt255_hi;
1263         u32     tx_stat_gt511_lo;
1264         u32     tx_stat_gt511_hi;
1265         u32     tx_stat_gt1023_lo;
1266         u32     tx_stat_gt1023_hi;
1267         u32     tx_stat_gt1518_lo;
1268         u32     tx_stat_gt1518_hi;
1269         u32     tx_stat_gt2047_lo;
1270         u32     tx_stat_gt2047_hi;
1271         u32     tx_stat_gt4095_lo;
1272         u32     tx_stat_gt4095_hi;
1273         u32     tx_stat_gt9216_lo;
1274         u32     tx_stat_gt9216_hi;
1275         u32     tx_stat_gt16383_lo;
1276         u32     tx_stat_gt16383_hi;
1277         u32     tx_stat_gtmax_lo;
1278         u32     tx_stat_gtmax_hi;
1279         u32     tx_stat_gtufl_lo;
1280         u32     tx_stat_gtufl_hi;
1281         u32     tx_stat_gterr_lo;
1282         u32     tx_stat_gterr_hi;
1283         u32     tx_stat_gtbyt_lo;
1284         u32     tx_stat_gtbyt_hi;
1285
1286         u32     rx_stat_gr64_lo;
1287         u32     rx_stat_gr64_hi;
1288         u32     rx_stat_gr127_lo;
1289         u32     rx_stat_gr127_hi;
1290         u32     rx_stat_gr255_lo;
1291         u32     rx_stat_gr255_hi;
1292         u32     rx_stat_gr511_lo;
1293         u32     rx_stat_gr511_hi;
1294         u32     rx_stat_gr1023_lo;
1295         u32     rx_stat_gr1023_hi;
1296         u32     rx_stat_gr1518_lo;
1297         u32     rx_stat_gr1518_hi;
1298         u32     rx_stat_gr2047_lo;
1299         u32     rx_stat_gr2047_hi;
1300         u32     rx_stat_gr4095_lo;
1301         u32     rx_stat_gr4095_hi;
1302         u32     rx_stat_gr9216_lo;
1303         u32     rx_stat_gr9216_hi;
1304         u32     rx_stat_gr16383_lo;
1305         u32     rx_stat_gr16383_hi;
1306         u32     rx_stat_grmax_lo;
1307         u32     rx_stat_grmax_hi;
1308         u32     rx_stat_grpkt_lo;
1309         u32     rx_stat_grpkt_hi;
1310         u32     rx_stat_grfcs_lo;
1311         u32     rx_stat_grfcs_hi;
1312         u32     rx_stat_gruca_lo;
1313         u32     rx_stat_gruca_hi;
1314         u32     rx_stat_grmca_lo;
1315         u32     rx_stat_grmca_hi;
1316         u32     rx_stat_grbca_lo;
1317         u32     rx_stat_grbca_hi;
1318         u32     rx_stat_grxpf_lo; /* grpf */
1319         u32     rx_stat_grxpf_hi; /* grpf */
1320         u32     rx_stat_grpp_lo;
1321         u32     rx_stat_grpp_hi;
1322         u32     rx_stat_grxuo_lo; /* gruo */
1323         u32     rx_stat_grxuo_hi; /* gruo */
1324         u32     rx_stat_grjbr_lo;
1325         u32     rx_stat_grjbr_hi;
1326         u32     rx_stat_grovr_lo;
1327         u32     rx_stat_grovr_hi;
1328         u32     rx_stat_grxcf_lo; /* grcf */
1329         u32     rx_stat_grxcf_hi; /* grcf */
1330         u32     rx_stat_grflr_lo;
1331         u32     rx_stat_grflr_hi;
1332         u32     rx_stat_grpok_lo;
1333         u32     rx_stat_grpok_hi;
1334         u32     rx_stat_grmeg_lo;
1335         u32     rx_stat_grmeg_hi;
1336         u32     rx_stat_grmeb_lo;
1337         u32     rx_stat_grmeb_hi;
1338         u32     rx_stat_grbyt_lo;
1339         u32     rx_stat_grbyt_hi;
1340         u32     rx_stat_grund_lo;
1341         u32     rx_stat_grund_hi;
1342         u32     rx_stat_grfrg_lo;
1343         u32     rx_stat_grfrg_hi;
1344         u32     rx_stat_grerb_lo; /* grerrbyt */
1345         u32     rx_stat_grerb_hi; /* grerrbyt */
1346         u32     rx_stat_grfre_lo; /* grfrerr */
1347         u32     rx_stat_grfre_hi; /* grfrerr */
1348         u32     rx_stat_gripj_lo;
1349         u32     rx_stat_gripj_hi;
1350 };
1351
1352 union mac_stats {
1353         struct emac_stats        emac_stats;
1354         struct bmac1_stats       bmac1_stats;
1355         struct bmac2_stats       bmac2_stats;
1356 };
1357
1358
1359 struct mac_stx {
1360     /* in_bad_octets */
1361     u32     rx_stat_ifhcinbadoctets_hi;
1362     u32     rx_stat_ifhcinbadoctets_lo;
1363
1364     /* out_bad_octets */
1365     u32     tx_stat_ifhcoutbadoctets_hi;
1366     u32     tx_stat_ifhcoutbadoctets_lo;
1367
1368     /* crc_receive_errors */
1369     u32     rx_stat_dot3statsfcserrors_hi;
1370     u32     rx_stat_dot3statsfcserrors_lo;
1371     /* alignment_errors */
1372     u32     rx_stat_dot3statsalignmenterrors_hi;
1373     u32     rx_stat_dot3statsalignmenterrors_lo;
1374     /* carrier_sense_errors */
1375     u32     rx_stat_dot3statscarriersenseerrors_hi;
1376     u32     rx_stat_dot3statscarriersenseerrors_lo;
1377     /* false_carrier_detections */
1378     u32     rx_stat_falsecarriererrors_hi;
1379     u32     rx_stat_falsecarriererrors_lo;
1380
1381     /* runt_packets_received */
1382     u32     rx_stat_etherstatsundersizepkts_hi;
1383     u32     rx_stat_etherstatsundersizepkts_lo;
1384     /* jabber_packets_received */
1385     u32     rx_stat_dot3statsframestoolong_hi;
1386     u32     rx_stat_dot3statsframestoolong_lo;
1387
1388     /* error_runt_packets_received */
1389     u32     rx_stat_etherstatsfragments_hi;
1390     u32     rx_stat_etherstatsfragments_lo;
1391     /* error_jabber_packets_received */
1392     u32     rx_stat_etherstatsjabbers_hi;
1393     u32     rx_stat_etherstatsjabbers_lo;
1394
1395     /* control_frames_received */
1396     u32     rx_stat_maccontrolframesreceived_hi;
1397     u32     rx_stat_maccontrolframesreceived_lo;
1398     u32     rx_stat_bmac_xpf_hi;
1399     u32     rx_stat_bmac_xpf_lo;
1400     u32     rx_stat_bmac_xcf_hi;
1401     u32     rx_stat_bmac_xcf_lo;
1402
1403     /* xoff_state_entered */
1404     u32     rx_stat_xoffstateentered_hi;
1405     u32     rx_stat_xoffstateentered_lo;
1406     /* pause_xon_frames_received */
1407     u32     rx_stat_xonpauseframesreceived_hi;
1408     u32     rx_stat_xonpauseframesreceived_lo;
1409     /* pause_xoff_frames_received */
1410     u32     rx_stat_xoffpauseframesreceived_hi;
1411     u32     rx_stat_xoffpauseframesreceived_lo;
1412     /* pause_xon_frames_transmitted */
1413     u32     tx_stat_outxonsent_hi;
1414     u32     tx_stat_outxonsent_lo;
1415     /* pause_xoff_frames_transmitted */
1416     u32     tx_stat_outxoffsent_hi;
1417     u32     tx_stat_outxoffsent_lo;
1418     /* flow_control_done */
1419     u32     tx_stat_flowcontroldone_hi;
1420     u32     tx_stat_flowcontroldone_lo;
1421
1422     /* ether_stats_collisions */
1423     u32     tx_stat_etherstatscollisions_hi;
1424     u32     tx_stat_etherstatscollisions_lo;
1425     /* single_collision_transmit_frames */
1426     u32     tx_stat_dot3statssinglecollisionframes_hi;
1427     u32     tx_stat_dot3statssinglecollisionframes_lo;
1428     /* multiple_collision_transmit_frames */
1429     u32     tx_stat_dot3statsmultiplecollisionframes_hi;
1430     u32     tx_stat_dot3statsmultiplecollisionframes_lo;
1431     /* deferred_transmissions */
1432     u32     tx_stat_dot3statsdeferredtransmissions_hi;
1433     u32     tx_stat_dot3statsdeferredtransmissions_lo;
1434     /* excessive_collision_frames */
1435     u32     tx_stat_dot3statsexcessivecollisions_hi;
1436     u32     tx_stat_dot3statsexcessivecollisions_lo;
1437     /* late_collision_frames */
1438     u32     tx_stat_dot3statslatecollisions_hi;
1439     u32     tx_stat_dot3statslatecollisions_lo;
1440
1441     /* frames_transmitted_64_bytes */
1442     u32     tx_stat_etherstatspkts64octets_hi;
1443     u32     tx_stat_etherstatspkts64octets_lo;
1444     /* frames_transmitted_65_127_bytes */
1445     u32     tx_stat_etherstatspkts65octetsto127octets_hi;
1446     u32     tx_stat_etherstatspkts65octetsto127octets_lo;
1447     /* frames_transmitted_128_255_bytes */
1448     u32     tx_stat_etherstatspkts128octetsto255octets_hi;
1449     u32     tx_stat_etherstatspkts128octetsto255octets_lo;
1450     /* frames_transmitted_256_511_bytes */
1451     u32     tx_stat_etherstatspkts256octetsto511octets_hi;
1452     u32     tx_stat_etherstatspkts256octetsto511octets_lo;
1453     /* frames_transmitted_512_1023_bytes */
1454     u32     tx_stat_etherstatspkts512octetsto1023octets_hi;
1455     u32     tx_stat_etherstatspkts512octetsto1023octets_lo;
1456     /* frames_transmitted_1024_1522_bytes */
1457     u32     tx_stat_etherstatspkts1024octetsto1522octets_hi;
1458     u32     tx_stat_etherstatspkts1024octetsto1522octets_lo;
1459     /* frames_transmitted_1523_9022_bytes */
1460     u32     tx_stat_etherstatspktsover1522octets_hi;
1461     u32     tx_stat_etherstatspktsover1522octets_lo;
1462     u32     tx_stat_bmac_2047_hi;
1463     u32     tx_stat_bmac_2047_lo;
1464     u32     tx_stat_bmac_4095_hi;
1465     u32     tx_stat_bmac_4095_lo;
1466     u32     tx_stat_bmac_9216_hi;
1467     u32     tx_stat_bmac_9216_lo;
1468     u32     tx_stat_bmac_16383_hi;
1469     u32     tx_stat_bmac_16383_lo;
1470
1471     /* internal_mac_transmit_errors */
1472     u32     tx_stat_dot3statsinternalmactransmiterrors_hi;
1473     u32     tx_stat_dot3statsinternalmactransmiterrors_lo;
1474
1475     /* if_out_discards */
1476     u32     tx_stat_bmac_ufl_hi;
1477     u32     tx_stat_bmac_ufl_lo;
1478 };
1479
1480
1481 #define MAC_STX_IDX_MAX                     2
1482
1483 struct host_port_stats {
1484     u32            host_port_stats_start;
1485
1486     struct mac_stx mac_stx[MAC_STX_IDX_MAX];
1487
1488     u32            brb_drop_hi;
1489     u32            brb_drop_lo;
1490
1491     u32            host_port_stats_end;
1492 };
1493
1494
1495 struct host_func_stats {
1496     u32     host_func_stats_start;
1497
1498     u32     total_bytes_received_hi;
1499     u32     total_bytes_received_lo;
1500
1501     u32     total_bytes_transmitted_hi;
1502     u32     total_bytes_transmitted_lo;
1503
1504     u32     total_unicast_packets_received_hi;
1505     u32     total_unicast_packets_received_lo;
1506
1507     u32     total_multicast_packets_received_hi;
1508     u32     total_multicast_packets_received_lo;
1509
1510     u32     total_broadcast_packets_received_hi;
1511     u32     total_broadcast_packets_received_lo;
1512
1513     u32     total_unicast_packets_transmitted_hi;
1514     u32     total_unicast_packets_transmitted_lo;
1515
1516     u32     total_multicast_packets_transmitted_hi;
1517     u32     total_multicast_packets_transmitted_lo;
1518
1519     u32     total_broadcast_packets_transmitted_hi;
1520     u32     total_broadcast_packets_transmitted_lo;
1521
1522     u32     valid_bytes_received_hi;
1523     u32     valid_bytes_received_lo;
1524
1525     u32     host_func_stats_end;
1526 };
1527
1528
1529 #define BCM_5710_FW_MAJOR_VERSION                       6
1530 #define BCM_5710_FW_MINOR_VERSION                       0
1531 #define BCM_5710_FW_REVISION_VERSION                    34
1532 #define BCM_5710_FW_ENGINEERING_VERSION                 0
1533 #define BCM_5710_FW_COMPILE_FLAGS                       1
1534
1535
1536 /*
1537  * attention bits
1538  */
1539 struct atten_sp_status_block {
1540         __le32 attn_bits;
1541         __le32 attn_bits_ack;
1542         u8 status_block_id;
1543         u8 reserved0;
1544         __le16 attn_bits_index;
1545         __le32 reserved1;
1546 };
1547
1548
1549 /*
1550  * common data for all protocols
1551  */
1552 struct doorbell_hdr {
1553         u8 header;
1554 #define DOORBELL_HDR_RX (0x1<<0)
1555 #define DOORBELL_HDR_RX_SHIFT 0
1556 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
1557 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
1558 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
1559 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
1560 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
1561 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
1562 };
1563
1564 /*
1565  * doorbell message sent to the chip
1566  */
1567 struct doorbell {
1568 #if defined(__BIG_ENDIAN)
1569         u16 zero_fill2;
1570         u8 zero_fill1;
1571         struct doorbell_hdr header;
1572 #elif defined(__LITTLE_ENDIAN)
1573         struct doorbell_hdr header;
1574         u8 zero_fill1;
1575         u16 zero_fill2;
1576 #endif
1577 };
1578
1579
1580 /*
1581  * doorbell message sent to the chip
1582  */
1583 struct doorbell_set_prod {
1584 #if defined(__BIG_ENDIAN)
1585         u16 prod;
1586         u8 zero_fill1;
1587         struct doorbell_hdr header;
1588 #elif defined(__LITTLE_ENDIAN)
1589         struct doorbell_hdr header;
1590         u8 zero_fill1;
1591         u16 prod;
1592 #endif
1593 };
1594
1595
1596 /*
1597  * 3 lines. status block
1598  */
1599 struct hc_status_block_e1x {
1600         __le16 index_values[HC_SB_MAX_INDICES_E1X];
1601         __le16 running_index[HC_SB_MAX_SM];
1602         u32 rsrv;
1603 };
1604
1605 /*
1606  * host status block
1607  */
1608 struct host_hc_status_block_e1x {
1609         struct hc_status_block_e1x sb;
1610 };
1611
1612
1613 /*
1614  * 3 lines. status block
1615  */
1616 struct hc_status_block_e2 {
1617         __le16 index_values[HC_SB_MAX_INDICES_E2];
1618         __le16 running_index[HC_SB_MAX_SM];
1619         u32 reserved;
1620 };
1621
1622 /*
1623  * host status block
1624  */
1625 struct host_hc_status_block_e2 {
1626         struct hc_status_block_e2 sb;
1627 };
1628
1629
1630 /*
1631  * 5 lines. slow-path status block
1632  */
1633 struct hc_sp_status_block {
1634         __le16 index_values[HC_SP_SB_MAX_INDICES];
1635         __le16 running_index;
1636         __le16 rsrv;
1637         u32 rsrv1;
1638 };
1639
1640 /*
1641  * host status block
1642  */
1643 struct host_sp_status_block {
1644         struct atten_sp_status_block atten_status_block;
1645         struct hc_sp_status_block sp_sb;
1646 };
1647
1648
1649 /*
1650  * IGU driver acknowledgment register
1651  */
1652 struct igu_ack_register {
1653 #if defined(__BIG_ENDIAN)
1654         u16 sb_id_and_flags;
1655 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1656 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1657 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1658 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1659 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1660 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1661 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1662 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1663 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1664 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1665         u16 status_block_index;
1666 #elif defined(__LITTLE_ENDIAN)
1667         u16 status_block_index;
1668         u16 sb_id_and_flags;
1669 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1670 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1671 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1672 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1673 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1674 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1675 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1676 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1677 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1678 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1679 #endif
1680 };
1681
1682
1683 /*
1684  * IGU driver acknowledgement register
1685  */
1686 struct igu_backward_compatible {
1687         u32 sb_id_and_flags;
1688 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
1689 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
1690 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
1691 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
1692 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
1693 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
1694 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
1695 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
1696 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
1697 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
1698 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
1699 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
1700         u32 reserved_2;
1701 };
1702
1703
1704 /*
1705  * IGU driver acknowledgement register
1706  */
1707 struct igu_regular {
1708         u32 sb_id_and_flags;
1709 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
1710 #define IGU_REGULAR_SB_INDEX_SHIFT 0
1711 #define IGU_REGULAR_RESERVED0 (0x1<<20)
1712 #define IGU_REGULAR_RESERVED0_SHIFT 20
1713 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
1714 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
1715 #define IGU_REGULAR_BUPDATE (0x1<<24)
1716 #define IGU_REGULAR_BUPDATE_SHIFT 24
1717 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
1718 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
1719 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
1720 #define IGU_REGULAR_RESERVED_1_SHIFT 27
1721 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
1722 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
1723 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
1724 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
1725 #define IGU_REGULAR_BCLEANUP (0x1<<31)
1726 #define IGU_REGULAR_BCLEANUP_SHIFT 31
1727         u32 reserved_2;
1728 };
1729
1730 /*
1731  * IGU driver acknowledgement register
1732  */
1733 union igu_consprod_reg {
1734         struct igu_regular regular;
1735         struct igu_backward_compatible backward_compatible;
1736 };
1737
1738
1739 /*
1740  * Control register for the IGU command register
1741  */
1742 struct igu_ctrl_reg {
1743         u32 ctrl_data;
1744 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
1745 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
1746 #define IGU_CTRL_REG_FID (0x7F<<12)
1747 #define IGU_CTRL_REG_FID_SHIFT 12
1748 #define IGU_CTRL_REG_RESERVED (0x1<<19)
1749 #define IGU_CTRL_REG_RESERVED_SHIFT 19
1750 #define IGU_CTRL_REG_TYPE (0x1<<20)
1751 #define IGU_CTRL_REG_TYPE_SHIFT 20
1752 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
1753 #define IGU_CTRL_REG_UNUSED_SHIFT 21
1754 };
1755
1756
1757 /*
1758  * Parser parsing flags field
1759  */
1760 struct parsing_flags {
1761         __le16 flags;
1762 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
1763 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
1764 #define PARSING_FLAGS_VLAN (0x1<<1)
1765 #define PARSING_FLAGS_VLAN_SHIFT 1
1766 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
1767 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
1768 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
1769 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
1770 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
1771 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
1772 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
1773 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
1774 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
1775 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
1776 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
1777 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
1778 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
1779 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
1780 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
1781 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
1782 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
1783 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
1784 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
1785 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
1786 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
1787 #define PARSING_FLAGS_RESERVED0_SHIFT 14
1788 };
1789
1790
1791 struct regpair {
1792         __le32 lo;
1793         __le32 hi;
1794 };
1795
1796
1797 /*
1798  * dmae command structure
1799  */
1800 struct dmae_command {
1801         u32 opcode;
1802 #define DMAE_COMMAND_SRC (0x1<<0)
1803 #define DMAE_COMMAND_SRC_SHIFT 0
1804 #define DMAE_COMMAND_DST (0x3<<1)
1805 #define DMAE_COMMAND_DST_SHIFT 1
1806 #define DMAE_COMMAND_C_DST (0x1<<3)
1807 #define DMAE_COMMAND_C_DST_SHIFT 3
1808 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
1809 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
1810 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
1811 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
1812 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
1813 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
1814 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
1815 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
1816 #define DMAE_COMMAND_PORT (0x1<<11)
1817 #define DMAE_COMMAND_PORT_SHIFT 11
1818 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
1819 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
1820 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
1821 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
1822 #define DMAE_COMMAND_DST_RESET (0x1<<14)
1823 #define DMAE_COMMAND_DST_RESET_SHIFT 14
1824 #define DMAE_COMMAND_E1HVN (0x3<<15)
1825 #define DMAE_COMMAND_E1HVN_SHIFT 15
1826 #define DMAE_COMMAND_DST_VN (0x3<<17)
1827 #define DMAE_COMMAND_DST_VN_SHIFT 17
1828 #define DMAE_COMMAND_C_FUNC (0x1<<19)
1829 #define DMAE_COMMAND_C_FUNC_SHIFT 19
1830 #define DMAE_COMMAND_ERR_POLICY (0x3<<20)
1831 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20
1832 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
1833 #define DMAE_COMMAND_RESERVED0_SHIFT 22
1834         u32 src_addr_lo;
1835         u32 src_addr_hi;
1836         u32 dst_addr_lo;
1837         u32 dst_addr_hi;
1838 #if defined(__BIG_ENDIAN)
1839         u16 reserved1;
1840         u16 len;
1841 #elif defined(__LITTLE_ENDIAN)
1842         u16 len;
1843         u16 reserved1;
1844 #endif
1845         u32 comp_addr_lo;
1846         u32 comp_addr_hi;
1847         u32 comp_val;
1848         u32 crc32;
1849         u32 crc32_c;
1850 #if defined(__BIG_ENDIAN)
1851         u16 crc16_c;
1852         u16 crc16;
1853 #elif defined(__LITTLE_ENDIAN)
1854         u16 crc16;
1855         u16 crc16_c;
1856 #endif
1857 #if defined(__BIG_ENDIAN)
1858         u16 reserved3;
1859         u16 crc_t10;
1860 #elif defined(__LITTLE_ENDIAN)
1861         u16 crc_t10;
1862         u16 reserved3;
1863 #endif
1864 #if defined(__BIG_ENDIAN)
1865         u16 xsum8;
1866         u16 xsum16;
1867 #elif defined(__LITTLE_ENDIAN)
1868         u16 xsum16;
1869         u16 xsum8;
1870 #endif
1871 };
1872
1873
1874 struct double_regpair {
1875         u32 regpair0_lo;
1876         u32 regpair0_hi;
1877         u32 regpair1_lo;
1878         u32 regpair1_hi;
1879 };
1880
1881
1882 /*
1883  * SDM operation gen command (generate aggregative interrupt)
1884  */
1885 struct sdm_op_gen {
1886         __le32 command;
1887 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
1888 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
1889 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
1890 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
1891 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
1892 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
1893 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
1894 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
1895 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
1896 #define SDM_OP_GEN_RESERVED_SHIFT 17
1897 };
1898
1899 /*
1900  * The eth Rx Buffer Descriptor
1901  */
1902 struct eth_rx_bd {
1903         __le32 addr_lo;
1904         __le32 addr_hi;
1905 };
1906
1907 /*
1908  * The eth Rx SGE Descriptor
1909  */
1910 struct eth_rx_sge {
1911         __le32 addr_lo;
1912         __le32 addr_hi;
1913 };
1914
1915
1916
1917 /*
1918  * The eth storm context of Ustorm
1919  */
1920 struct ustorm_eth_st_context {
1921         u32 reserved0[48];
1922 };
1923
1924 /*
1925  * The eth storm context of Tstorm
1926  */
1927 struct tstorm_eth_st_context {
1928         u32 __reserved0[28];
1929 };
1930
1931 /*
1932  * The eth aggregative context of Xstorm
1933  */
1934 struct xstorm_eth_ag_context {
1935         u32 reserved0;
1936 #if defined(__BIG_ENDIAN)
1937         u8 cdu_reserved;
1938         u8 reserved2;
1939         u16 reserved1;
1940 #elif defined(__LITTLE_ENDIAN)
1941         u16 reserved1;
1942         u8 reserved2;
1943         u8 cdu_reserved;
1944 #endif
1945         u32 reserved3[30];
1946 };
1947
1948 /*
1949  * The eth aggregative context of Tstorm
1950  */
1951 struct tstorm_eth_ag_context {
1952         u32 __reserved0[14];
1953 };
1954
1955
1956 /*
1957  * The eth aggregative context of Cstorm
1958  */
1959 struct cstorm_eth_ag_context {
1960         u32 __reserved0[10];
1961 };
1962
1963
1964 /*
1965  * The eth aggregative context of Ustorm
1966  */
1967 struct ustorm_eth_ag_context {
1968         u32 __reserved0;
1969 #if defined(__BIG_ENDIAN)
1970         u8 cdu_usage;
1971         u8 __reserved2;
1972         u16 __reserved1;
1973 #elif defined(__LITTLE_ENDIAN)
1974         u16 __reserved1;
1975         u8 __reserved2;
1976         u8 cdu_usage;
1977 #endif
1978         u32 __reserved3[6];
1979 };
1980
1981 /*
1982  * Timers connection context
1983  */
1984 struct timers_block_context {
1985         u32 __reserved_0;
1986         u32 __reserved_1;
1987         u32 __reserved_2;
1988         u32 flags;
1989 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
1990 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
1991 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
1992 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
1993 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
1994 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
1995 };
1996
1997 /*
1998  * structure for easy accessibility to assembler
1999  */
2000 struct eth_tx_bd_flags {
2001         u8 as_bitfield;
2002 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
2003 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
2004 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
2005 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
2006 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
2007 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
2008 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
2009 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
2010 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
2011 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
2012 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
2013 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
2014 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
2015 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
2016 };
2017
2018 /*
2019  * The eth Tx Buffer Descriptor
2020  */
2021 struct eth_tx_start_bd {
2022         __le32 addr_lo;
2023         __le32 addr_hi;
2024         __le16 nbd;
2025         __le16 nbytes;
2026         __le16 vlan_or_ethertype;
2027         struct eth_tx_bd_flags bd_flags;
2028         u8 general_data;
2029 #define ETH_TX_START_BD_HDR_NBDS (0x3F<<0)
2030 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
2031 #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
2032 #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
2033 };
2034
2035 /*
2036  * Tx regular BD structure
2037  */
2038 struct eth_tx_bd {
2039         __le32 addr_lo;
2040         __le32 addr_hi;
2041         __le16 total_pkt_bytes;
2042         __le16 nbytes;
2043         u8 reserved[4];
2044 };
2045
2046 /*
2047  * Tx parsing BD structure for ETH E1/E1h
2048  */
2049 struct eth_tx_parse_bd_e1x {
2050         u8 global_data;
2051 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
2052 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
2053 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4)
2054 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4
2055 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
2056 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
2057 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6)
2058 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6
2059 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7)
2060 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7
2061         u8 tcp_flags;
2062 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
2063 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
2064 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
2065 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
2066 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
2067 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
2068 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
2069 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
2070 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
2071 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
2072 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
2073 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
2074 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
2075 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
2076 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
2077 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
2078         u8 ip_hlen_w;
2079         s8 reserved;
2080         __le16 total_hlen_w;
2081         __le16 tcp_pseudo_csum;
2082         __le16 lso_mss;
2083         __le16 ip_id;
2084         __le32 tcp_send_seq;
2085 };
2086
2087 /*
2088  * Tx parsing BD structure for ETH E2
2089  */
2090 struct eth_tx_parse_bd_e2 {
2091         __le16 dst_mac_addr_lo;
2092         __le16 dst_mac_addr_mid;
2093         __le16 dst_mac_addr_hi;
2094         __le16 src_mac_addr_lo;
2095         __le16 src_mac_addr_mid;
2096         __le16 src_mac_addr_hi;
2097         __le32 parsing_data;
2098 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0)
2099 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0
2100 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13)
2101 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13
2102 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17)
2103 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17
2104 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31)
2105 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31
2106 };
2107
2108 /*
2109  * The last BD in the BD memory will hold a pointer to the next BD memory
2110  */
2111 struct eth_tx_next_bd {
2112         __le32 addr_lo;
2113         __le32 addr_hi;
2114         u8 reserved[8];
2115 };
2116
2117 /*
2118  * union for 4 Bd types
2119  */
2120 union eth_tx_bd_types {
2121         struct eth_tx_start_bd start_bd;
2122         struct eth_tx_bd reg_bd;
2123         struct eth_tx_parse_bd_e1x parse_bd_e1x;
2124         struct eth_tx_parse_bd_e2 parse_bd_e2;
2125         struct eth_tx_next_bd next_bd;
2126 };
2127
2128
2129 /*
2130  * The eth storm context of Xstorm
2131  */
2132 struct xstorm_eth_st_context {
2133         u32 reserved0[60];
2134 };
2135
2136 /*
2137  * The eth storm context of Cstorm
2138  */
2139 struct cstorm_eth_st_context {
2140         u32 __reserved0[4];
2141 };
2142
2143 /*
2144  * Ethernet connection context
2145  */
2146 struct eth_context {
2147         struct ustorm_eth_st_context ustorm_st_context;
2148         struct tstorm_eth_st_context tstorm_st_context;
2149         struct xstorm_eth_ag_context xstorm_ag_context;
2150         struct tstorm_eth_ag_context tstorm_ag_context;
2151         struct cstorm_eth_ag_context cstorm_ag_context;
2152         struct ustorm_eth_ag_context ustorm_ag_context;
2153         struct timers_block_context timers_context;
2154         struct xstorm_eth_st_context xstorm_st_context;
2155         struct cstorm_eth_st_context cstorm_st_context;
2156 };
2157
2158
2159 /*
2160  * Ethernet doorbell
2161  */
2162 struct eth_tx_doorbell {
2163 #if defined(__BIG_ENDIAN)
2164         u16 npackets;
2165         u8 params;
2166 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2167 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2168 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2169 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2170 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2171 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2172         struct doorbell_hdr hdr;
2173 #elif defined(__LITTLE_ENDIAN)
2174         struct doorbell_hdr hdr;
2175         u8 params;
2176 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2177 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2178 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2179 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2180 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2181 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2182         u16 npackets;
2183 #endif
2184 };
2185
2186
2187 /*
2188  * client init fc data
2189  */
2190 struct client_init_fc_data {
2191         __le16 cqe_pause_thr_low;
2192         __le16 cqe_pause_thr_high;
2193         __le16 bd_pause_thr_low;
2194         __le16 bd_pause_thr_high;
2195         __le16 sge_pause_thr_low;
2196         __le16 sge_pause_thr_high;
2197         __le16 rx_cos_mask;
2198         u8 safc_group_num;
2199         u8 safc_group_en_flg;
2200         u8 traffic_type;
2201         u8 reserved0;
2202         __le16 reserved1;
2203         __le32 reserved2;
2204 };
2205
2206
2207 /*
2208  * client init ramrod data
2209  */
2210 struct client_init_general_data {
2211         u8 client_id;
2212         u8 statistics_counter_id;
2213         u8 statistics_en_flg;
2214         u8 is_fcoe_flg;
2215         u8 activate_flg;
2216         u8 sp_client_id;
2217         __le16 reserved0;
2218         __le32 reserved1[2];
2219 };
2220
2221
2222 /*
2223  * client init rx data
2224  */
2225 struct client_init_rx_data {
2226         u8 tpa_en_flg;
2227         u8 vmqueue_mode_en_flg;
2228         u8 extra_data_over_sgl_en_flg;
2229         u8 cache_line_alignment_log_size;
2230         u8 enable_dynamic_hc;
2231         u8 max_sges_for_packet;
2232         u8 client_qzone_id;
2233         u8 drop_ip_cs_err_flg;
2234         u8 drop_tcp_cs_err_flg;
2235         u8 drop_ttl0_flg;
2236         u8 drop_udp_cs_err_flg;
2237         u8 inner_vlan_removal_enable_flg;
2238         u8 outer_vlan_removal_enable_flg;
2239         u8 status_block_id;
2240         u8 rx_sb_index_number;
2241         u8 reserved0[3];
2242         __le16 bd_buff_size;
2243         __le16 sge_buff_size;
2244         __le16 mtu;
2245         struct regpair bd_page_base;
2246         struct regpair sge_page_base;
2247         struct regpair cqe_page_base;
2248         u8 is_leading_rss;
2249         u8 is_approx_mcast;
2250         __le16 max_agg_size;
2251         __le32 reserved2[3];
2252 };
2253
2254 /*
2255  * client init tx data
2256  */
2257 struct client_init_tx_data {
2258         u8 enforce_security_flg;
2259         u8 tx_status_block_id;
2260         u8 tx_sb_index_number;
2261         u8 reserved0;
2262         __le16 mtu;
2263         __le16 reserved1;
2264         struct regpair tx_bd_page_base;
2265         __le32 reserved2[2];
2266 };
2267
2268 /*
2269  * client init ramrod data
2270  */
2271 struct client_init_ramrod_data {
2272         struct client_init_general_data general;
2273         struct client_init_rx_data rx;
2274         struct client_init_tx_data tx;
2275         struct client_init_fc_data fc;
2276 };
2277
2278
2279 /*
2280  * The data contain client ID need to the ramrod
2281  */
2282 struct eth_common_ramrod_data {
2283         u32 client_id;
2284         u32 reserved1;
2285 };
2286
2287
2288 /*
2289  * union for sgl and raw data.
2290  */
2291 union eth_sgl_or_raw_data {
2292         __le16 sgl[8];
2293         u32 raw_data[4];
2294 };
2295
2296 /*
2297  * regular eth FP CQE parameters struct
2298  */
2299 struct eth_fast_path_rx_cqe {
2300         u8 type_error_flags;
2301 #define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
2302 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
2303 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
2304 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
2305 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
2306 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
2307 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
2308 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
2309 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
2310 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
2311 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
2312 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
2313 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x3<<6)
2314 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 6
2315         u8 status_flags;
2316 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
2317 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
2318 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
2319 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
2320 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
2321 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
2322 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
2323 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
2324 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
2325 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
2326 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
2327 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
2328         u8 placement_offset;
2329         u8 queue_index;
2330         __le32 rss_hash_result;
2331         __le16 vlan_tag;
2332         __le16 pkt_len;
2333         __le16 len_on_bd;
2334         struct parsing_flags pars_flags;
2335         union eth_sgl_or_raw_data sgl_or_raw_data;
2336 };
2337
2338
2339 /*
2340  * The data for RSS setup ramrod
2341  */
2342 struct eth_halt_ramrod_data {
2343         u32 client_id;
2344         u32 reserved0;
2345 };
2346
2347 /*
2348  * The data for statistics query ramrod
2349  */
2350 struct common_query_ramrod_data {
2351 #if defined(__BIG_ENDIAN)
2352         u8 reserved0;
2353         u8 collect_port;
2354         u16 drv_counter;
2355 #elif defined(__LITTLE_ENDIAN)
2356         u16 drv_counter;
2357         u8 collect_port;
2358         u8 reserved0;
2359 #endif
2360         u32 ctr_id_vector;
2361 };
2362
2363
2364 /*
2365  * Place holder for ramrods protocol specific data
2366  */
2367 struct ramrod_data {
2368         __le32 data_lo;
2369         __le32 data_hi;
2370 };
2371
2372 /*
2373  * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
2374  */
2375 union eth_ramrod_data {
2376         struct ramrod_data general;
2377 };
2378
2379
2380 /*
2381  * Eth Rx Cqe structure- general structure for ramrods
2382  */
2383 struct common_ramrod_eth_rx_cqe {
2384         u8 ramrod_type;
2385 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
2386 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2387 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<1)
2388 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 1
2389 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x3F<<2)
2390 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 2
2391         u8 conn_type;
2392         __le16 reserved1;
2393         __le32 conn_and_cmd_data;
2394 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
2395 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
2396 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
2397 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
2398         struct ramrod_data protocol_data;
2399         __le32 reserved2[4];
2400 };
2401
2402 /*
2403  * Rx Last CQE in page (in ETH)
2404  */
2405 struct eth_rx_cqe_next_page {
2406         __le32 addr_lo;
2407         __le32 addr_hi;
2408         __le32 reserved[6];
2409 };
2410
2411 /*
2412  * union for all eth rx cqe types (fix their sizes)
2413  */
2414 union eth_rx_cqe {
2415         struct eth_fast_path_rx_cqe fast_path_cqe;
2416         struct common_ramrod_eth_rx_cqe ramrod_cqe;
2417         struct eth_rx_cqe_next_page next_page_cqe;
2418 };
2419
2420
2421 /*
2422  * common data for all protocols
2423  */
2424 struct spe_hdr {
2425         __le32 conn_and_cmd_data;
2426 #define SPE_HDR_CID (0xFFFFFF<<0)
2427 #define SPE_HDR_CID_SHIFT 0
2428 #define SPE_HDR_CMD_ID (0xFF<<24)
2429 #define SPE_HDR_CMD_ID_SHIFT 24
2430         __le16 type;
2431 #define SPE_HDR_CONN_TYPE (0xFF<<0)
2432 #define SPE_HDR_CONN_TYPE_SHIFT 0
2433 #define SPE_HDR_FUNCTION_ID (0xFF<<8)
2434 #define SPE_HDR_FUNCTION_ID_SHIFT 8
2435         __le16 reserved1;
2436 };
2437
2438 /*
2439  * Ethernet slow path element
2440  */
2441 union eth_specific_data {
2442         u8 protocol_data[8];
2443         struct regpair client_init_ramrod_init_data;
2444         struct eth_halt_ramrod_data halt_ramrod_data;
2445         struct regpair update_data_addr;
2446         struct eth_common_ramrod_data common_ramrod_data;
2447 };
2448
2449 /*
2450  * Ethernet slow path element
2451  */
2452 struct eth_spe {
2453         struct spe_hdr hdr;
2454         union eth_specific_data data;
2455 };
2456
2457
2458 /*
2459  * array of 13 bds as appears in the eth xstorm context
2460  */
2461 struct eth_tx_bds_array {
2462         union eth_tx_bd_types bds[13];
2463 };
2464
2465
2466 /*
2467  * Common configuration parameters per function in Tstorm
2468  */
2469 struct tstorm_eth_function_common_config {
2470 #if defined(__BIG_ENDIAN)
2471         u8 reserved1;
2472         u8 rss_result_mask;
2473         u16 config_flags;
2474 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2475 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2476 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2477 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2478 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2479 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2480 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2481 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2482 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2483 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2484 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<7)
2485 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 7
2486 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<8)
2487 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 8
2488 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x7F<<9)
2489 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 9
2490 #elif defined(__LITTLE_ENDIAN)
2491         u16 config_flags;
2492 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2493 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2494 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2495 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2496 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2497 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2498 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2499 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2500 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2501 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2502 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<7)
2503 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 7
2504 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<8)
2505 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 8
2506 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x7F<<9)
2507 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 9
2508         u8 rss_result_mask;
2509         u8 reserved1;
2510 #endif
2511         u16 vlan_id[2];
2512 };
2513
2514 /*
2515  * RSS idirection table update configuration
2516  */
2517 struct rss_update_config {
2518 #if defined(__BIG_ENDIAN)
2519         u16 toe_rss_bitmap;
2520         u16 flags;
2521 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
2522 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
2523 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
2524 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
2525 #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
2526 #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
2527 #elif defined(__LITTLE_ENDIAN)
2528         u16 flags;
2529 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
2530 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
2531 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
2532 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
2533 #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
2534 #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
2535         u16 toe_rss_bitmap;
2536 #endif
2537         u32 reserved1;
2538 };
2539
2540 /*
2541  * parameters for eth update ramrod
2542  */
2543 struct eth_update_ramrod_data {
2544         struct tstorm_eth_function_common_config func_config;
2545         u8 indirectionTable[128];
2546         struct rss_update_config rss_config;
2547 };
2548
2549
2550 /*
2551  * MAC filtering configuration command header
2552  */
2553 struct mac_configuration_hdr {
2554         u8 length;
2555         u8 offset;
2556         u16 client_id;
2557         u16 echo;
2558         u16 reserved1;
2559 };
2560
2561 /*
2562  * MAC address in list for ramrod
2563  */
2564 struct mac_configuration_entry {
2565         __le16 lsb_mac_addr;
2566         __le16 middle_mac_addr;
2567         __le16 msb_mac_addr;
2568         __le16 vlan_id;
2569         u8 pf_id;
2570         u8 flags;
2571 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
2572 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
2573 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
2574 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
2575 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
2576 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
2577 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
2578 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
2579 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
2580 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
2581 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
2582 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
2583         u16 reserved0;
2584         u32 clients_bit_vector;
2585 };
2586
2587 /*
2588  * MAC filtering configuration command
2589  */
2590 struct mac_configuration_cmd {
2591         struct mac_configuration_hdr hdr;
2592         struct mac_configuration_entry config_table[64];
2593 };
2594
2595
2596 /*
2597  * approximate-match multicast filtering for E1H per function in Tstorm
2598  */
2599 struct tstorm_eth_approximate_match_multicast_filtering {
2600         u32 mcast_add_hash_bit_array[8];
2601 };
2602
2603
2604 /*
2605  * MAC filtering configuration parameters per port in Tstorm
2606  */
2607 struct tstorm_eth_mac_filter_config {
2608         u32 ucast_drop_all;
2609         u32 ucast_accept_all;
2610         u32 mcast_drop_all;
2611         u32 mcast_accept_all;
2612         u32 bcast_drop_all;
2613         u32 bcast_accept_all;
2614         u32 vlan_filter[2];
2615         u32 unmatched_unicast;
2616         u32 reserved;
2617 };
2618
2619
2620 /*
2621  * common flag to indicate existance of TPA.
2622  */
2623 struct tstorm_eth_tpa_exist {
2624 #if defined(__BIG_ENDIAN)
2625         u16 reserved1;
2626         u8 reserved0;
2627         u8 tpa_exist;
2628 #elif defined(__LITTLE_ENDIAN)
2629         u8 tpa_exist;
2630         u8 reserved0;
2631         u16 reserved1;
2632 #endif
2633         u32 reserved2;
2634 };
2635
2636
2637 /*
2638  * Three RX producers for ETH
2639  */
2640 struct ustorm_eth_rx_producers {
2641 #if defined(__BIG_ENDIAN)
2642         u16 bd_prod;
2643         u16 cqe_prod;
2644 #elif defined(__LITTLE_ENDIAN)
2645         u16 cqe_prod;
2646         u16 bd_prod;
2647 #endif
2648 #if defined(__BIG_ENDIAN)
2649         u16 reserved;
2650         u16 sge_prod;
2651 #elif defined(__LITTLE_ENDIAN)
2652         u16 sge_prod;
2653         u16 reserved;
2654 #endif
2655 };
2656
2657
2658 /*
2659  * cfc delete event data
2660  */
2661 struct cfc_del_event_data {
2662         u32 cid;
2663         u8 error;
2664         u8 reserved0;
2665         u16 reserved1;
2666         u32 reserved2;
2667 };
2668
2669
2670 /*
2671  * per-port SAFC demo variables
2672  */
2673 struct cmng_flags_per_port {
2674         u8 con_number[NUM_OF_PROTOCOLS];
2675         u32 cmng_enables;
2676 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
2677 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
2678 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
2679 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
2680 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2)
2681 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2
2682 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3)
2683 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3
2684 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4)
2685 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4
2686 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<5)
2687 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 5
2688 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x3FFFFFF<<6)
2689 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 6
2690 };
2691
2692
2693 /*
2694  * per-port rate shaping variables
2695  */
2696 struct rate_shaping_vars_per_port {
2697         u32 rs_periodic_timeout;
2698         u32 rs_threshold;
2699 };
2700
2701 /*
2702  * per-port fairness variables
2703  */
2704 struct fairness_vars_per_port {
2705         u32 upper_bound;
2706         u32 fair_threshold;
2707         u32 fairness_timeout;
2708 };
2709
2710 /*
2711  * per-port SAFC variables
2712  */
2713 struct safc_struct_per_port {
2714 #if defined(__BIG_ENDIAN)
2715         u16 __reserved1;
2716         u8 __reserved0;
2717         u8 safc_timeout_usec;
2718 #elif defined(__LITTLE_ENDIAN)
2719         u8 safc_timeout_usec;
2720         u8 __reserved0;
2721         u16 __reserved1;
2722 #endif
2723         u8 cos_to_traffic_types[MAX_COS_NUMBER];
2724         u32 __reserved2;
2725         u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
2726 };
2727
2728 /*
2729  * per-port PFC variables
2730  */
2731 struct pfc_struct_per_port {
2732         u8 priority_to_traffic_types[MAX_PFC_PRIORITIES];
2733 #if defined(__BIG_ENDIAN)
2734         u16 pfc_pause_quanta_in_nanosec;
2735         u8 __reserved0;
2736         u8 priority_non_pausable_mask;
2737 #elif defined(__LITTLE_ENDIAN)
2738         u8 priority_non_pausable_mask;
2739         u8 __reserved0;
2740         u16 pfc_pause_quanta_in_nanosec;
2741 #endif
2742 };
2743
2744 /*
2745  * Priority and cos
2746  */
2747 struct priority_cos {
2748 #if defined(__BIG_ENDIAN)
2749         u16 reserved1;
2750         u8 cos;
2751         u8 priority;
2752 #elif defined(__LITTLE_ENDIAN)
2753         u8 priority;
2754         u8 cos;
2755         u16 reserved1;
2756 #endif
2757         u32 reserved2;
2758 };
2759
2760 /*
2761  * Per-port congestion management variables
2762  */
2763 struct cmng_struct_per_port {
2764         struct rate_shaping_vars_per_port rs_vars;
2765         struct fairness_vars_per_port fair_vars;
2766         struct safc_struct_per_port safc_vars;
2767         struct pfc_struct_per_port pfc_vars;
2768 #if defined(__BIG_ENDIAN)
2769         u16 __reserved1;
2770         u8 dcb_enabled;
2771         u8 llfc_mode;
2772 #elif defined(__LITTLE_ENDIAN)
2773         u8 llfc_mode;
2774         u8 dcb_enabled;
2775         u16 __reserved1;
2776 #endif
2777         struct priority_cos
2778                 traffic_type_to_priority_cos[MAX_PFC_TRAFFIC_TYPES];
2779         struct cmng_flags_per_port flags;
2780 };
2781
2782
2783
2784 /*
2785  * Dynamic HC counters set by the driver
2786  */
2787 struct hc_dynamic_drv_counter {
2788         u32 val[HC_SB_MAX_DYNAMIC_INDICES];
2789 };
2790
2791 /*
2792  * zone A per-queue data
2793  */
2794 struct cstorm_queue_zone_data {
2795         struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
2796         struct regpair reserved[2];
2797 };
2798
2799 /*
2800  * Dynamic host coalescing init parameters
2801  */
2802 struct dynamic_hc_config {
2803         u32 threshold[3];
2804         u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
2805         u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
2806         u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
2807         u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
2808         u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
2809 };
2810
2811
2812 /*
2813  * Protocol-common statistics collected by the Xstorm (per client)
2814  */
2815 struct xstorm_per_client_stats {
2816         __le32 reserved0;
2817         __le32 unicast_pkts_sent;
2818         struct regpair unicast_bytes_sent;
2819         struct regpair multicast_bytes_sent;
2820         __le32 multicast_pkts_sent;
2821         __le32 broadcast_pkts_sent;
2822         struct regpair broadcast_bytes_sent;
2823         __le16 stats_counter;
2824         __le16 reserved1;
2825         __le32 reserved2;
2826 };
2827
2828 /*
2829  * Common statistics collected by the Xstorm (per port)
2830  */
2831 struct xstorm_common_stats {
2832         struct xstorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID];
2833 };
2834
2835 /*
2836  * Protocol-common statistics collected by the Tstorm (per port)
2837  */
2838 struct tstorm_per_port_stats {
2839         __le32 mac_filter_discard;
2840         __le32 xxoverflow_discard;
2841         __le32 brb_truncate_discard;
2842         __le32 mac_discard;
2843 };
2844
2845 /*
2846  * Protocol-common statistics collected by the Tstorm (per client)
2847  */
2848 struct tstorm_per_client_stats {
2849         struct regpair rcv_unicast_bytes;
2850         struct regpair rcv_broadcast_bytes;
2851         struct regpair rcv_multicast_bytes;
2852         struct regpair rcv_error_bytes;
2853         __le32 checksum_discard;
2854         __le32 packets_too_big_discard;
2855         __le32 rcv_unicast_pkts;
2856         __le32 rcv_broadcast_pkts;
2857         __le32 rcv_multicast_pkts;
2858         __le32 no_buff_discard;
2859         __le32 ttl0_discard;
2860         __le16 stats_counter;
2861         __le16 reserved0;
2862 };
2863
2864 /*
2865  * Protocol-common statistics collected by the Tstorm
2866  */
2867 struct tstorm_common_stats {
2868         struct tstorm_per_port_stats port_statistics;
2869         struct tstorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID];
2870 };
2871
2872 /*
2873  * Protocol-common statistics collected by the Ustorm (per client)
2874  */
2875 struct ustorm_per_client_stats {
2876         struct regpair ucast_no_buff_bytes;
2877         struct regpair mcast_no_buff_bytes;
2878         struct regpair bcast_no_buff_bytes;
2879         __le32 ucast_no_buff_pkts;
2880         __le32 mcast_no_buff_pkts;
2881         __le32 bcast_no_buff_pkts;
2882         __le16 stats_counter;
2883         __le16 reserved0;
2884 };
2885
2886 /*
2887  * Protocol-common statistics collected by the Ustorm
2888  */
2889 struct ustorm_common_stats {
2890         struct ustorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID];
2891 };
2892
2893 /*
2894  * Eth statistics query structure for the eth_stats_query ramrod
2895  */
2896 struct eth_stats_query {
2897         struct xstorm_common_stats xstorm_common;
2898         struct tstorm_common_stats tstorm_common;
2899         struct ustorm_common_stats ustorm_common;
2900 };
2901
2902
2903 /*
2904  * set mac event data
2905  */
2906 struct set_mac_event_data {
2907         u16 echo;
2908         u16 reserved0;
2909         u32 reserved1;
2910         u32 reserved2;
2911 };
2912
2913 /*
2914  * union for all event ring message types
2915  */
2916 union event_data {
2917         struct set_mac_event_data set_mac_event;
2918         struct cfc_del_event_data cfc_del_event;
2919 };
2920
2921
2922 /*
2923  * per PF event ring data
2924  */
2925 struct event_ring_data {
2926         struct regpair base_addr;
2927 #if defined(__BIG_ENDIAN)
2928         u8 index_id;
2929         u8 sb_id;
2930         u16 producer;
2931 #elif defined(__LITTLE_ENDIAN)
2932         u16 producer;
2933         u8 sb_id;
2934         u8 index_id;
2935 #endif
2936         u32 reserved0;
2937 };
2938
2939
2940 /*
2941  * event ring message element (each element is 128 bits)
2942  */
2943 struct event_ring_msg {
2944         u8 opcode;
2945         u8 reserved0;
2946         u16 reserved1;
2947         union event_data data;
2948 };
2949
2950 /*
2951  * event ring next page element (128 bits)
2952  */
2953 struct event_ring_next {
2954         struct regpair addr;
2955         u32 reserved[2];
2956 };
2957
2958 /*
2959  * union for event ring element types (each element is 128 bits)
2960  */
2961 union event_ring_elem {
2962         struct event_ring_msg message;
2963         struct event_ring_next next_page;
2964 };
2965
2966
2967 /*
2968  * per-vnic fairness variables
2969  */
2970 struct fairness_vars_per_vn {
2971         u32 cos_credit_delta[MAX_COS_NUMBER];
2972         u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
2973         u32 vn_credit_delta;
2974         u32 __reserved0;
2975 };
2976
2977
2978 /*
2979  * FW version stored in the Xstorm RAM
2980  */
2981 struct fw_version {
2982 #if defined(__BIG_ENDIAN)
2983         u8 engineering;
2984         u8 revision;
2985         u8 minor;
2986         u8 major;
2987 #elif defined(__LITTLE_ENDIAN)
2988         u8 major;
2989         u8 minor;
2990         u8 revision;
2991         u8 engineering;
2992 #endif
2993         u32 flags;
2994 #define FW_VERSION_OPTIMIZED (0x1<<0)
2995 #define FW_VERSION_OPTIMIZED_SHIFT 0
2996 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
2997 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
2998 #define FW_VERSION_CHIP_VERSION (0x3<<2)
2999 #define FW_VERSION_CHIP_VERSION_SHIFT 2
3000 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
3001 #define __FW_VERSION_RESERVED_SHIFT 4
3002 };
3003
3004
3005 /*
3006  * Dynamic Host-Coalescing - Driver(host) counters
3007  */
3008 struct hc_dynamic_sb_drv_counters {
3009         u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
3010 };
3011
3012
3013 /*
3014  * 2 bytes. configuration/state parameters for a single protocol index
3015  */
3016 struct hc_index_data {
3017 #if defined(__BIG_ENDIAN)
3018         u8 flags;
3019 #define HC_INDEX_DATA_SM_ID (0x1<<0)
3020 #define HC_INDEX_DATA_SM_ID_SHIFT 0
3021 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
3022 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
3023 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
3024 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
3025 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
3026 #define HC_INDEX_DATA_RESERVE_SHIFT 3
3027         u8 timeout;
3028 #elif defined(__LITTLE_ENDIAN)
3029         u8 timeout;
3030         u8 flags;
3031 #define HC_INDEX_DATA_SM_ID (0x1<<0)
3032 #define HC_INDEX_DATA_SM_ID_SHIFT 0
3033 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
3034 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
3035 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
3036 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
3037 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
3038 #define HC_INDEX_DATA_RESERVE_SHIFT 3
3039 #endif
3040 };
3041
3042
3043 /*
3044  * HC state-machine
3045  */
3046 struct hc_status_block_sm {
3047 #if defined(__BIG_ENDIAN)
3048         u8 igu_seg_id;
3049         u8 igu_sb_id;
3050         u8 timer_value;
3051         u8 __flags;
3052 #elif defined(__LITTLE_ENDIAN)
3053         u8 __flags;
3054         u8 timer_value;
3055         u8 igu_sb_id;
3056         u8 igu_seg_id;
3057 #endif
3058         u32 time_to_expire;
3059 };
3060
3061 /*
3062  * hold PCI identification variables- used in various places in firmware
3063  */
3064 struct pci_entity {
3065 #if defined(__BIG_ENDIAN)
3066         u8 vf_valid;
3067         u8 vf_id;
3068         u8 vnic_id;
3069         u8 pf_id;
3070 #elif defined(__LITTLE_ENDIAN)
3071         u8 pf_id;
3072         u8 vnic_id;
3073         u8 vf_id;
3074         u8 vf_valid;
3075 #endif
3076 };
3077
3078 /*
3079  * The fast-path status block meta-data, common to all chips
3080  */
3081 struct hc_sb_data {
3082         struct regpair host_sb_addr;
3083         struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
3084         struct pci_entity p_func;
3085 #if defined(__BIG_ENDIAN)
3086         u8 rsrv0;
3087         u8 dhc_qzone_id;
3088         u8 __dynamic_hc_level;
3089         u8 same_igu_sb_1b;
3090 #elif defined(__LITTLE_ENDIAN)
3091         u8 same_igu_sb_1b;
3092         u8 __dynamic_hc_level;
3093         u8 dhc_qzone_id;
3094         u8 rsrv0;
3095 #endif
3096         struct regpair rsrv1[2];
3097 };
3098
3099
3100 /*
3101  * The fast-path status block meta-data
3102  */
3103 struct hc_sp_status_block_data {
3104         struct regpair host_sb_addr;
3105 #if defined(__BIG_ENDIAN)
3106         u16 rsrv;
3107         u8 igu_seg_id;
3108         u8 igu_sb_id;
3109 #elif defined(__LITTLE_ENDIAN)
3110         u8 igu_sb_id;
3111         u8 igu_seg_id;
3112         u16 rsrv;
3113 #endif
3114         struct pci_entity p_func;
3115 };
3116
3117
3118 /*
3119  * The fast-path status block meta-data
3120  */
3121 struct hc_status_block_data_e1x {
3122         struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
3123         struct hc_sb_data common;
3124 };
3125
3126
3127 /*
3128  * The fast-path status block meta-data
3129  */
3130 struct hc_status_block_data_e2 {
3131         struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
3132         struct hc_sb_data common;
3133 };
3134
3135
3136 /*
3137  * FW version stored in first line of pram
3138  */
3139 struct pram_fw_version {
3140         u8 major;
3141         u8 minor;
3142         u8 revision;
3143         u8 engineering;
3144         u8 flags;
3145 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
3146 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
3147 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
3148 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
3149 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
3150 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
3151 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
3152 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
3153 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
3154 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
3155 };
3156
3157
3158 /*
3159  * Ethernet slow path element
3160  */
3161 union protocol_common_specific_data {
3162         u8 protocol_data[8];
3163         struct regpair phy_address;
3164         struct regpair mac_config_addr;
3165         struct common_query_ramrod_data query_ramrod_data;
3166 };
3167
3168 /*
3169  * The send queue element
3170  */
3171 struct protocol_common_spe {
3172         struct spe_hdr hdr;
3173         union protocol_common_specific_data data;
3174 };
3175
3176
3177 /*
3178  * a single rate shaping counter. can be used as protocol or vnic counter
3179  */
3180 struct rate_shaping_counter {
3181         u32 quota;
3182 #if defined(__BIG_ENDIAN)
3183         u16 __reserved0;
3184         u16 rate;
3185 #elif defined(__LITTLE_ENDIAN)
3186         u16 rate;
3187         u16 __reserved0;
3188 #endif
3189 };
3190
3191
3192 /*
3193  * per-vnic rate shaping variables
3194  */
3195 struct rate_shaping_vars_per_vn {
3196         struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
3197         struct rate_shaping_counter vn_counter;
3198 };
3199
3200
3201 /*
3202  * The send queue element
3203  */
3204 struct slow_path_element {
3205         struct spe_hdr hdr;
3206         struct regpair protocol_data;
3207 };
3208
3209
3210 /*
3211  * eth/toe flags that indicate if to query
3212  */
3213 struct stats_indication_flags {
3214         u32 collect_eth;
3215         u32 collect_toe;
3216 };
3217
3218
3219 /*
3220  * per-port PFC variables
3221  */
3222 struct storm_pfc_struct_per_port {
3223 #if defined(__BIG_ENDIAN)
3224         u16 mid_mac_addr;
3225         u16 msb_mac_addr;
3226 #elif defined(__LITTLE_ENDIAN)
3227         u16 msb_mac_addr;
3228         u16 mid_mac_addr;
3229 #endif
3230 #if defined(__BIG_ENDIAN)
3231         u16 pfc_pause_quanta_in_nanosec;
3232         u16 lsb_mac_addr;
3233 #elif defined(__LITTLE_ENDIAN)
3234         u16 lsb_mac_addr;
3235         u16 pfc_pause_quanta_in_nanosec;
3236 #endif
3237 };
3238
3239 /*
3240  * Per-port congestion management variables
3241  */
3242 struct storm_cmng_struct_per_port {
3243         struct storm_pfc_struct_per_port pfc_vars;
3244 };
3245
3246
3247 /*
3248  * zone A per-queue data
3249  */
3250 struct tstorm_queue_zone_data {
3251         struct regpair reserved[4];
3252 };
3253
3254
3255 /*
3256  * zone B per-VF data
3257  */
3258 struct tstorm_vf_zone_data {
3259         struct regpair reserved;
3260 };
3261
3262
3263 /*
3264  * zone A per-queue data
3265  */
3266 struct ustorm_queue_zone_data {
3267         struct ustorm_eth_rx_producers eth_rx_producers;
3268         struct regpair reserved[3];
3269 };
3270
3271
3272 /*
3273  * zone B per-VF data
3274  */
3275 struct ustorm_vf_zone_data {
3276         struct regpair reserved;
3277 };
3278
3279
3280 /*
3281  * data per VF-PF channel
3282  */
3283 struct vf_pf_channel_data {
3284 #if defined(__BIG_ENDIAN)
3285         u16 reserved0;
3286         u8 valid;
3287         u8 state;
3288 #elif defined(__LITTLE_ENDIAN)
3289         u8 state;
3290         u8 valid;
3291         u16 reserved0;
3292 #endif
3293         u32 reserved1;
3294 };
3295
3296
3297 /*
3298  * zone A per-queue data
3299  */
3300 struct xstorm_queue_zone_data {
3301         struct regpair reserved[4];
3302 };
3303
3304
3305 /*
3306  * zone B per-VF data
3307  */
3308 struct xstorm_vf_zone_data {
3309         struct regpair reserved;
3310 };
3311
3312 #endif /* BNX2X_HSI_H */