2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
5 * Bharath H S <bhs@nvidia.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 * drivers/mtd/maps/tegra_nor_gmi.c
23 * MTD mapping driver for the internal SNOR controller in Tegra SoCs
27 #include <linux/platform_device.h>
28 #include <linux/module.h>
29 #include <linux/slab.h>
30 #include <linux/interrupt.h>
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/map.h>
33 #include <linux/dma-mapping.h>
35 #include <linux/clk.h>
36 #include <linux/platform_data/tegra_nor.h>
37 #include <linux/mtd/concat.h>
38 #include <linux/gpio.h>
39 #include <linux/tegra_snor.h>
41 #ifdef CONFIG_TEGRA_GMI_ACCESS_CONTROL
42 #include <linux/tegra_gmi_access.h>
45 struct map_info_list {
48 unsigned long long totalflashsize;
51 struct tegra_nor_info {
52 struct tegra_nor_platform_data *plat; /* Platform data */
53 struct device *dev; /* Platform device */
54 struct clk *clk; /* Clock */
55 struct mtd_partition *parts; /* MtdParts passed by
59 struct mtd_info **mtd;
60 struct mtd_info *concat_mtd;
61 struct gpio_addr_info *adinfo;
62 struct completion dma_complete; /* comletion for DMA */
63 void __iomem *base; /* SNOR register address */
64 void *dma_virt_buffer;
65 dma_addr_t dma_phys_buffer;
67 u32 timing0_default, timing1_default;
68 u32 timing0_read, timing1_read;
70 int (*request_gmi_access)(u32 gmiLockHandle);
71 void (*release_gmi_access)(void);
74 /* Master structure of all tegra NOR private data*/
75 struct tegra_nor_private {
76 struct tegra_nor_info *info;
80 #define DRV_NAME "tegra-nor"
82 #define gmi_lock(info) \
84 if ((info)->request_gmi_access) \
85 (info)->request_gmi_access((info)->gmiLockHandle); \
88 #define gmi_unlock(info) \
90 if ((info)->release_gmi_access) \
91 (info)->release_gmi_access(); \
95 static struct map_info_list nor_gmi_map_list;
97 static inline unsigned long tegra_snor_readl(struct tegra_nor_info *tnor,
100 return readl(tnor->base + reg);
103 static inline void tegra_snor_writel(struct tegra_nor_info *tnor,
104 unsigned long val, unsigned long reg)
106 writel(val, tnor->base + reg);
110 static const char * const part_probes[] = { "cmdlinepart", NULL };
112 static int wait_for_dma_completion(struct tegra_nor_info *info)
114 unsigned long dma_timeout;
117 dma_timeout = msecs_to_jiffies(TEGRA_SNOR_DMA_TIMEOUT_MS);
118 ret = wait_for_completion_timeout(&info->dma_complete, dma_timeout);
119 return ret ? 0 : -ETIMEDOUT;
122 static void flash_bank_cs(struct map_info *map)
124 struct tegra_nor_private *priv =
125 (struct tegra_nor_private *)map->map_priv_1;
126 struct cs_info *csinfo = priv->cs;
127 struct gpio_state *state = &csinfo->gpio_cs;
130 struct tegra_nor_info *c = priv->info;
132 snor_config = tegra_snor_readl(c, TEGRA_SNOR_CONFIG_REG);
133 snor_config &= SNOR_CONFIG_MASK;
134 snor_config |= TEGRA_SNOR_CONFIG_SNOR_CS(csinfo->cs);
135 tegra_snor_writel(c, snor_config, TEGRA_SNOR_CONFIG_REG);
137 c->init_config = snor_config;
139 snor_config = tegra_snor_readl(c, TEGRA_SNOR_CONFIG_REG);
140 for (i = 0; i < csinfo->num_cs_gpio; i++)
141 gpio_set_value(state->gpio_num, state->value);
144 static void flash_bank_addr(struct map_info *map, unsigned int offset)
146 struct tegra_nor_private *priv =
147 (struct tegra_nor_private *)map->map_priv_1;
148 struct gpio_addr_info *adinfo = priv->info->adinfo;
149 struct gpio_addr *addr = adinfo->addr;
150 struct gpio_state state;
153 for (i = 0; i < adinfo->num_gpios; i++) {
154 state.gpio_num = addr[i].gpio_num;
155 state.value = (BIT(addr[i].line_num) & offset) ? HIGH : LOW;
156 gpio_set_value(state.gpio_num, state.value);
160 static void tegra_flash_dma(struct map_info *map,
161 void *to, unsigned long from, ssize_t len)
163 u32 snor_config, dma_config = 0;
164 int dma_transfer_count = 0, word32_count = 0;
165 u32 nor_address, current_transfer = 0;
166 u32 copy_to = (u32)to;
167 struct tegra_nor_private *priv =
168 (struct tegra_nor_private *)map->map_priv_1;
169 struct tegra_nor_info *c = priv->info;
170 struct tegra_nor_chip_parms *chip_parm = &c->plat->chip_parms;
171 unsigned int bytes_remaining = len;
173 snor_config = c->init_config;
175 tegra_snor_writel(c, c->timing0_read, TEGRA_SNOR_TIMING0_REG);
176 tegra_snor_writel(c, c->timing1_read, TEGRA_SNOR_TIMING1_REG);
179 word32_count = len >> 2;
180 bytes_remaining = len & 0x00000003;
182 * The parameters can be setup in any order since we write to
183 * controller register only after all parameters are set.
185 /* SNOR CONFIGURATION SETUP */
187 switch (chip_parm->ReadMode) {
188 case NorReadMode_Async:
189 snor_config |= TEGRA_SNOR_CONFIG_DEVICE_MODE(0);
192 case NorReadMode_Page:
193 switch (chip_parm->PageLength) {
194 case NorPageLength_Unsupported:
195 snor_config |= TEGRA_SNOR_CONFIG_DEVICE_MODE(0);
198 case NorPageLength_4Word:
199 snor_config |= TEGRA_SNOR_CONFIG_DEVICE_MODE(1);
200 snor_config |= TEGRA_SNOR_CONFIG_PAGE_SZ(1);
203 case NorPageLength_8Word:
204 snor_config |= TEGRA_SNOR_CONFIG_DEVICE_MODE(1);
205 snor_config |= TEGRA_SNOR_CONFIG_PAGE_SZ(2);
208 case NorPageLength_16Word:
209 snor_config |= TEGRA_SNOR_CONFIG_DEVICE_MODE(1);
210 snor_config |= TEGRA_SNOR_CONFIG_PAGE_SZ(3);
215 case NorReadMode_Burst:
216 snor_config |= TEGRA_SNOR_CONFIG_DEVICE_MODE(2);
217 switch (chip_parm->BurstLength) {
218 case NorBurstLength_CntBurst:
219 snor_config |= TEGRA_SNOR_CONFIG_BURST_LEN(0);
221 case NorBurstLength_8Word:
222 snor_config |= TEGRA_SNOR_CONFIG_BURST_LEN(1);
225 case NorBurstLength_16Word:
226 snor_config |= TEGRA_SNOR_CONFIG_BURST_LEN(2);
229 case NorBurstLength_32Word:
230 snor_config |= TEGRA_SNOR_CONFIG_BURST_LEN(3);
235 snor_config |= TEGRA_SNOR_CONFIG_MST_ENB;
236 /* SNOR DMA CONFIGURATION SETUP */
238 dma_config &= ~TEGRA_SNOR_DMA_CFG_DIR;
240 /* Fix this to have max burst as in commented code*/
241 /*dma_config |= TEGRA_SNOR_DMA_CFG_BRST_SZ(6);*/
242 dma_config |= TEGRA_SNOR_DMA_CFG_BRST_SZ(4);
244 for (nor_address = (unsigned int)(map->phys + from);
246 word32_count -= current_transfer,
247 dma_transfer_count += current_transfer,
248 nor_address += (current_transfer * 4),
249 copy_to += (current_transfer * 4)) {
252 (word32_count > TEGRA_SNOR_DMA_LIMIT_WORDS)
253 ? (TEGRA_SNOR_DMA_LIMIT_WORDS) : word32_count;
254 /* Start NOR operation */
255 snor_config |= TEGRA_SNOR_CONFIG_GO;
256 dma_config |= TEGRA_SNOR_DMA_CFG_GO;
257 /* Enable interrupt before every transaction since the
258 * interrupt handler disables it */
259 dma_config |= TEGRA_SNOR_DMA_CFG_INT_ENB;
260 /* Num of AHB (32-bit) words to transferred minus 1 */
262 TEGRA_SNOR_DMA_CFG_WRD_CNT(current_transfer - 1);
263 tegra_snor_writel(c, c->dma_phys_buffer,
264 TEGRA_SNOR_AHB_ADDR_PTR_REG);
265 tegra_snor_writel(c, nor_address,
266 TEGRA_SNOR_NOR_ADDR_PTR_REG);
267 tegra_snor_writel(c, snor_config,
268 TEGRA_SNOR_CONFIG_REG);
269 tegra_snor_writel(c, dma_config,
270 TEGRA_SNOR_DMA_CFG_REG);
271 if (wait_for_dma_completion(c)) {
272 dev_err(c->dev, "timout waiting for DMA\n");
273 /* Transfer the remaining words by memcpy */
274 bytes_remaining += (word32_count << 2);
277 /* use dma map single instead of coheret buffer */
278 dma_sync_single_for_cpu(c->dev, c->dma_phys_buffer,
279 (current_transfer << 2), DMA_FROM_DEVICE);
280 memcpy((char *)(copy_to), (char *)(c->dma_virt_buffer),
281 (current_transfer << 2));
285 /* Put the controller back into slave mode. */
286 snor_config = tegra_snor_readl(c, TEGRA_SNOR_CONFIG_REG);
287 snor_config &= ~TEGRA_SNOR_CONFIG_MST_ENB;
288 snor_config |= TEGRA_SNOR_CONFIG_DEVICE_MODE(0);
289 tegra_snor_writel(c, snor_config, TEGRA_SNOR_CONFIG_REG);
291 memcpy_fromio(((char *)to + (dma_transfer_count << 2)),
292 ((char *)(map->virt + from) + (dma_transfer_count << 2)),
295 tegra_snor_writel(c, c->timing0_default, TEGRA_SNOR_TIMING0_REG);
296 tegra_snor_writel(c, c->timing1_default, TEGRA_SNOR_TIMING1_REG);
299 void tegra_nor_copy_from(struct map_info *map,
300 void *to, unsigned long from, ssize_t len)
303 struct tegra_nor_private *priv =
304 (struct tegra_nor_private *)map->map_priv_1;
305 struct tegra_nor_info *c = priv->info;
306 unsigned long bank_boundary;
309 /* All feature for go thru loop*/
312 /* Tegra SNOR controller window is 128MB this
313 check is required to take care of case which cross bank boundary*/
314 bank_boundary = (from & ~SNOR_WINDOW_SIZE) + SNOR_WINDOW_SIZE + 1;
316 if ((from + len) > bank_boundary) {
317 unsigned long transfer_chunk = bank_boundary - from;
319 flash_bank_addr(map, from);
320 tegra_flash_dma(map, to, (from & SNOR_WINDOW_SIZE),
321 bank_boundary - from);
323 flash_bank_addr(map, bank_boundary);
324 tegra_flash_dma(map, to + (bank_boundary - from), 0,
325 len - transfer_chunk);
327 flash_bank_addr(map, from);
328 tegra_flash_dma(map, to, (from & SNOR_WINDOW_SIZE), len);
335 static map_word tegra_nor_read(struct map_info *map,
339 struct tegra_nor_private *priv =
340 (struct tegra_nor_private *)map->map_priv_1;
341 struct tegra_nor_info *c = priv->info;
345 tegra_snor_writel(c, c->init_config, TEGRA_SNOR_CONFIG_REG);
346 tegra_snor_writel(c, c->timing0_read, TEGRA_SNOR_TIMING0_REG);
347 tegra_snor_writel(c, c->timing1_read, TEGRA_SNOR_TIMING1_REG);
350 flash_bank_addr(map, ofs);
351 ret = inline_map_read(map, ofs & SNOR_WINDOW_SIZE);
357 static void tegra_nor_write(struct map_info *map,
358 map_word datum, unsigned long ofs)
361 struct tegra_nor_private *priv =
362 (struct tegra_nor_private *)map->map_priv_1;
363 struct tegra_nor_info *c = priv->info;
366 tegra_snor_writel(c, c->init_config, TEGRA_SNOR_CONFIG_REG);
367 tegra_snor_writel(c, c->timing0_read, TEGRA_SNOR_TIMING0_REG);
368 tegra_snor_writel(c, c->timing1_read, TEGRA_SNOR_TIMING1_REG);
371 flash_bank_addr(map, ofs);
372 inline_map_write(map, datum, ofs & SNOR_WINDOW_SIZE);
377 static irqreturn_t tegra_nor_isr(int flag, void *dev_id)
379 struct tegra_nor_info *info = (struct tegra_nor_info *)dev_id;
381 u32 dma_config = tegra_snor_readl(info, TEGRA_SNOR_DMA_CFG_REG);
383 if (dma_config & TEGRA_SNOR_DMA_CFG_INT_STA) {
384 /* Disable interrupts. WAR for BUG:821560 */
385 dma_config &= ~TEGRA_SNOR_DMA_CFG_INT_ENB;
386 tegra_snor_writel(info, dma_config, TEGRA_SNOR_DMA_CFG_REG);
387 complete(&info->dma_complete);
389 pr_err("%s: Spurious interrupt\n", __func__);
394 static int tegra_snor_controller_init(struct tegra_nor_info *info)
396 struct tegra_nor_chip_parms *chip_parm = &info->plat->chip_parms;
397 u32 width = info->plat->flash.width;
400 config |= TEGRA_SNOR_CONFIG_DEVICE_MODE(0);
401 config |= TEGRA_SNOR_CONFIG_SNOR_CS(0);
402 config &= ~TEGRA_SNOR_CONFIG_DEVICE_TYPE; /* Select NOR */
403 config |= TEGRA_SNOR_CONFIG_WP; /* Enable writes */
406 config &= ~TEGRA_SNOR_CONFIG_WORDWIDE; /* 16 bit */
409 config |= TEGRA_SNOR_CONFIG_WORDWIDE; /* 32 bit */
414 switch (chip_parm->MuxMode) {
415 case NorMuxMode_ADNonMux:
416 config &= ~TEGRA_SNOR_CONFIG_MUX_MODE;
418 case NorMuxMode_ADMux:
419 config |= TEGRA_SNOR_CONFIG_MUX_MODE;
424 switch (chip_parm->ReadyActive) {
425 case NorReadyActive_WithData:
426 config &= ~TEGRA_SNOR_CONFIG_RDY_ACTIVE;
428 case NorReadyActive_BeforeData:
429 config |= TEGRA_SNOR_CONFIG_RDY_ACTIVE;
434 tegra_snor_writel(info, config, TEGRA_SNOR_CONFIG_REG);
435 info->init_config = config;
437 info->timing0_default = chip_parm->timing_default.timing0;
438 info->timing0_read = chip_parm->timing_read.timing0;
439 info->timing1_default = chip_parm->timing_default.timing1;
440 info->timing1_read = chip_parm->timing_read.timing1;
442 tegra_snor_writel(info, info->timing1_default, TEGRA_SNOR_TIMING1_REG);
443 tegra_snor_writel(info, info->timing0_default, TEGRA_SNOR_TIMING0_REG);
447 #ifdef CONFIG_TEGRA_EFS
448 struct map_info *get_map_info(unsigned int bank_index)
450 struct map_info *map = &nor_gmi_map_list.map[bank_index];
453 int get_maps_no(void)
455 int no_of_maps = nor_gmi_map_list.n_maps;
458 unsigned long long getflashsize(void)
460 int flash_size = nor_gmi_map_list.totalflashsize;
465 static int flash_probe(struct tegra_nor_info *info)
467 struct mtd_info **mtd;
468 struct map_info *map_list = info->map;
469 struct map_info *map;
471 struct device *dev = info->dev;
472 int present_banks = 0;
473 unsigned long long size = 0;
476 mtd = devm_kzalloc(dev, sizeof(struct mtd_info *) *
477 info->n_maps, GFP_KERNEL);
480 dev_err(dev, "cannot allocate memory for mtd_info\n");
484 for (i = 0; i < info->n_maps; i++) {
486 mtd[i] = do_map_probe(info->plat->flash.map_name, map);
488 dev_err(dev, "cannot probe flash\n");
498 if (present_banks == 0) {
501 if (present_banks < info->n_maps)
502 info->concat_mtd = mtd_concat_create(info->mtd,
503 present_banks, DRV_NAME);
505 info->concat_mtd = mtd_concat_create(info->mtd,
506 info->n_maps, DRV_NAME);
508 if (!info->concat_mtd) {
509 dev_err(dev, "cannot concatenate flash\n");
513 info->concat_mtd->owner = THIS_MODULE;
515 #ifdef CONFIG_TEGRA_EFS
516 nor_gmi_map_list.totalflashsize = size;
522 static int flash_maps_init(struct tegra_nor_info *info, struct resource *res)
524 struct map_info *map_list;
525 struct map_info *map;
526 struct flash_info *flinfo = &info->plat->info;
527 int num_chips = flinfo->num_chips;
529 struct tegra_nor_private *priv;
530 struct device *dev = info->dev;
532 priv = devm_kzalloc(dev, sizeof(struct tegra_nor_private) * num_chips,
535 dev_err(dev, "cannot allocate memory for" \
536 "private variable\n");
540 map_list = devm_kzalloc(dev, sizeof(struct map_info) * num_chips,
543 dev_err(dev, "cannot allocate memory for" \
548 for (i = 0; i < num_chips; i++) {
549 struct cs_info *csinfo = NULL;
550 struct gpio_state *state = NULL;
551 struct gpio_addr_info *adinfo = NULL;
552 struct gpio_addr *addr = NULL;
557 /* Setup private structure*/
559 priv[i].cs = flinfo->cs + i;
560 map->map_priv_1 = (unsigned long)&priv[i];
563 state = &csinfo->gpio_cs;
564 adinfo = priv[i].info->adinfo;
566 /* Request Needed GPIO's */
568 for (j = 0; j < csinfo->num_cs_gpio; j++) {
569 /* For now ignore the request failures */
571 err = gpio_request(state[j].gpio_num, state[j].label);
572 gpio_direction_output(state[j].gpio_num, 0);
574 for (k = 0; k < adinfo->num_gpios; k++) {
576 err_add = gpio_request(addr[k].gpio_num, NULL);
577 gpio_direction_output(addr[k].gpio_num, 0);
580 map->name = dev_name(info->dev);
581 map->size = csinfo->size;
582 map->bankwidth = info->plat->flash.width;
583 map->virt = priv->cs->virt;
584 map->phys = priv->cs->phys;
586 simple_map_init(map);
587 map->read = tegra_nor_read;
588 map->write = tegra_nor_write;
589 map->copy_from = tegra_nor_copy_from;
592 info->n_maps = num_chips;
593 info->map = map_list;
597 static int tegra_nor_probe(struct platform_device *pdev)
600 struct tegra_nor_platform_data *plat = pdev->dev.platform_data;
601 struct tegra_nor_info *info = NULL;
602 struct device *dev = &pdev->dev;
603 struct resource *res;
607 pr_err("%s: no platform device info\n", __func__);
611 info = devm_kzalloc(dev, sizeof(struct tegra_nor_info),
616 /* Get NOR controller & map the same */
617 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
619 dev_err(dev, "no mem resource?\n");
623 info->base = devm_request_and_ioremap(dev, res);
625 dev_err(dev, "Couldn't ioremap regs\n");
632 #ifdef CONFIG_TEGRA_GMI_ACCESS_CONTROL
633 info->gmiLockHandle = register_gmi_device("tegra-nor", 0);
634 info->request_gmi_access = request_gmi_access;
635 info->release_gmi_access = release_gmi_access;
637 info->gmiLockHandle = 0;
638 info->request_gmi_access = NULL;
639 info->release_gmi_access = NULL;
641 /* Get address line gpios */
642 info->adinfo = &plat->addr;
644 /* Initialize mapping */
645 if (flash_maps_init(info, res)) {
646 dev_err(dev, "can't map NOR flash\n");
651 info->clk = devm_clk_get(dev, NULL);
652 if (IS_ERR(info->clk))
653 return PTR_ERR(info->clk);
655 err = clk_prepare_enable(info->clk);
659 /* Intialise the SNOR controller before probe */
660 err = tegra_snor_controller_init(info);
662 dev_err(dev, "Error initializing controller\n");
663 goto out_clk_disable;
666 init_completion(&info->dma_complete);
668 irq = platform_get_irq(pdev, 0);
670 dev_err(dev, "no irq resource?\n");
672 goto out_clk_disable;
675 /* Register SNOR DMA completion interrupt */
676 err = request_irq(irq, tegra_nor_isr, IRQF_DISABLED,
677 dev_name(dev), info);
679 dev_err(dev, "Failed to request irq %i\n", irq);
680 goto out_clk_disable;
682 info->dma_virt_buffer = dma_alloc_coherent(dev,
683 TEGRA_SNOR_DMA_LIMIT,
684 &info->dma_phys_buffer,
686 if (!info->dma_virt_buffer) {
687 dev_err(&pdev->dev, "Could not allocate buffer for DMA");
689 goto out_clk_disable;
692 /* Probe the flash */
693 if (flash_probe(info)) {
694 dev_err(dev, "can't probe full flash\n");
696 goto out_dma_free_coherent;
700 plat->flash.parts = NULL;
702 platform_set_drvdata(pdev, info);
703 /* Parse partitions and register mtd */
704 err = mtd_device_parse_register(info->concat_mtd,
705 (const char **)part_probes, NULL, info->parts, 0);
708 goto out_dma_free_coherent;
710 #ifdef CONFIG_TEGRA_EFS
711 nor_gmi_map_list.map = info->map;
712 nor_gmi_map_list.n_maps = info->n_maps;
716 out_dma_free_coherent:
717 dma_free_coherent(dev, TEGRA_SNOR_DMA_LIMIT,
718 info->dma_virt_buffer, info->dma_phys_buffer);
720 clk_disable_unprepare(info->clk);
722 pr_err("Tegra NOR probe failed\n");
726 static int tegra_nor_remove(struct platform_device *pdev)
728 struct tegra_nor_info *info = platform_get_drvdata(pdev);
730 mtd_device_unregister(info->concat_mtd);
732 dma_free_coherent(&pdev->dev, TEGRA_SNOR_DMA_LIMIT,
733 info->dma_virt_buffer, info->dma_phys_buffer);
734 map_destroy(info->concat_mtd);
735 clk_disable_unprepare(info->clk);
740 static struct platform_driver __refdata tegra_nor_driver = {
741 .probe = tegra_nor_probe,
742 .remove = tegra_nor_remove,
745 .owner = THIS_MODULE,
750 module_platform_driver(tegra_nor_driver);
752 MODULE_AUTHOR("Bharath H S <bhs@nvidia.com>");
753 MODULE_DESCRIPTION("NOR Flash mapping driver for NVIDIA Tegra based boards");
754 MODULE_LICENSE("GPL");
755 MODULE_ALIAS("platform:" DRV_NAME);