[MMC] Convert all hosts except mmci to use data->blksz
[linux-3.10.git] / drivers / mmc / omap.c
1 /*
2  *  linux/drivers/media/mmc/omap.c
3  *
4  *  Copyright (C) 2004 Nokia Corporation
5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7  *  Other hacks (DMA, SD, etc) by David Brownell
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13
14 #include <linux/config.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/init.h>
18 #include <linux/ioport.h>
19 #include <linux/platform_device.h>
20 #include <linux/interrupt.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/delay.h>
23 #include <linux/spinlock.h>
24 #include <linux/timer.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/protocol.h>
27 #include <linux/mmc/card.h>
28 #include <linux/clk.h>
29
30 #include <asm/io.h>
31 #include <asm/irq.h>
32 #include <asm/scatterlist.h>
33 #include <asm/mach-types.h>
34
35 #include <asm/arch/board.h>
36 #include <asm/arch/gpio.h>
37 #include <asm/arch/dma.h>
38 #include <asm/arch/mux.h>
39 #include <asm/arch/fpga.h>
40 #include <asm/arch/tps65010.h>
41
42 #include "omap.h"
43
44 #define DRIVER_NAME "mmci-omap"
45 #define RSP_TYPE(x)     ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
46
47 /* Specifies how often in millisecs to poll for card status changes
48  * when the cover switch is open */
49 #define OMAP_MMC_SWITCH_POLL_DELAY      500
50
51 static int mmc_omap_enable_poll = 1;
52
53 struct mmc_omap_host {
54         int                     initialized;
55         int                     suspended;
56         struct mmc_request *    mrq;
57         struct mmc_command *    cmd;
58         struct mmc_data *       data;
59         struct mmc_host *       mmc;
60         struct device *         dev;
61         unsigned char           id; /* 16xx chips have 2 MMC blocks */
62         struct clk *            iclk;
63         struct clk *            fclk;
64         void __iomem            *base;
65         int                     irq;
66         unsigned char           bus_mode;
67         unsigned char           hw_bus_mode;
68
69         unsigned int            sg_len;
70         int                     sg_idx;
71         u16 *                   buffer;
72         u32                     buffer_bytes_left;
73         u32                     total_bytes_left;
74
75         unsigned                use_dma:1;
76         unsigned                brs_received:1, dma_done:1;
77         unsigned                dma_is_read:1;
78         unsigned                dma_in_use:1;
79         int                     dma_ch;
80         spinlock_t              dma_lock;
81         struct timer_list       dma_timer;
82         unsigned                dma_len;
83
84         short                   power_pin;
85         short                   wp_pin;
86
87         int                     switch_pin;
88         struct work_struct      switch_work;
89         struct timer_list       switch_timer;
90         int                     switch_last_state;
91 };
92
93 static inline int
94 mmc_omap_cover_is_open(struct mmc_omap_host *host)
95 {
96         if (host->switch_pin < 0)
97                 return 0;
98         return omap_get_gpio_datain(host->switch_pin);
99 }
100
101 static ssize_t
102 mmc_omap_show_cover_switch(struct device *dev,
103         struct device_attribute *attr, char *buf)
104 {
105         struct mmc_omap_host *host = dev_get_drvdata(dev);
106
107         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" :
108                         "closed");
109 }
110
111 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
112
113 static ssize_t
114 mmc_omap_show_enable_poll(struct device *dev,
115         struct device_attribute *attr, char *buf)
116 {
117         return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll);
118 }
119
120 static ssize_t
121 mmc_omap_store_enable_poll(struct device *dev,
122         struct device_attribute *attr, const char *buf,
123         size_t size)
124 {
125         int enable_poll;
126
127         if (sscanf(buf, "%10d", &enable_poll) != 1)
128                 return -EINVAL;
129
130         if (enable_poll != mmc_omap_enable_poll) {
131                 struct mmc_omap_host *host = dev_get_drvdata(dev);
132
133                 mmc_omap_enable_poll = enable_poll;
134                 if (enable_poll && host->switch_pin >= 0)
135                         schedule_work(&host->switch_work);
136         }
137         return size;
138 }
139
140 static DEVICE_ATTR(enable_poll, 0664,
141                    mmc_omap_show_enable_poll, mmc_omap_store_enable_poll);
142
143 static void
144 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
145 {
146         u32 cmdreg;
147         u32 resptype;
148         u32 cmdtype;
149
150         host->cmd = cmd;
151
152         resptype = 0;
153         cmdtype = 0;
154
155         /* Our hardware needs to know exact type */
156         switch (RSP_TYPE(mmc_resp_type(cmd))) {
157         case RSP_TYPE(MMC_RSP_R1):
158                 /* resp 1, resp 1b */
159                 resptype = 1;
160                 break;
161         case RSP_TYPE(MMC_RSP_R2):
162                 resptype = 2;
163                 break;
164         case RSP_TYPE(MMC_RSP_R3):
165                 resptype = 3;
166                 break;
167         default:
168                 break;
169         }
170
171         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
172                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
173         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
174                 cmdtype = OMAP_MMC_CMDTYPE_BC;
175         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
176                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
177         } else {
178                 cmdtype = OMAP_MMC_CMDTYPE_AC;
179         }
180
181         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
182
183         if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
184                 cmdreg |= 1 << 6;
185
186         if (cmd->flags & MMC_RSP_BUSY)
187                 cmdreg |= 1 << 11;
188
189         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
190                 cmdreg |= 1 << 15;
191
192         clk_enable(host->fclk);
193
194         OMAP_MMC_WRITE(host->base, CTO, 200);
195         OMAP_MMC_WRITE(host->base, ARGL, cmd->arg & 0xffff);
196         OMAP_MMC_WRITE(host->base, ARGH, cmd->arg >> 16);
197         OMAP_MMC_WRITE(host->base, IE,
198                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
199                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
200                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
201                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
202                        OMAP_MMC_STAT_END_OF_DATA);
203         OMAP_MMC_WRITE(host->base, CMD, cmdreg);
204 }
205
206 static void
207 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
208 {
209         if (host->dma_in_use) {
210                 enum dma_data_direction dma_data_dir;
211
212                 BUG_ON(host->dma_ch < 0);
213                 if (data->error != MMC_ERR_NONE)
214                         omap_stop_dma(host->dma_ch);
215                 /* Release DMA channel lazily */
216                 mod_timer(&host->dma_timer, jiffies + HZ);
217                 if (data->flags & MMC_DATA_WRITE)
218                         dma_data_dir = DMA_TO_DEVICE;
219                 else
220                         dma_data_dir = DMA_FROM_DEVICE;
221                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
222                              dma_data_dir);
223         }
224         host->data = NULL;
225         host->sg_len = 0;
226         clk_disable(host->fclk);
227
228         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
229          * dozens of requests until the card finishes writing data.
230          * It'd be cheaper to just wait till an EOFB interrupt arrives...
231          */
232
233         if (!data->stop) {
234                 host->mrq = NULL;
235                 mmc_request_done(host->mmc, data->mrq);
236                 return;
237         }
238
239         mmc_omap_start_command(host, data->stop);
240 }
241
242 static void
243 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
244 {
245         unsigned long flags;
246         int done;
247
248         if (!host->dma_in_use) {
249                 mmc_omap_xfer_done(host, data);
250                 return;
251         }
252         done = 0;
253         spin_lock_irqsave(&host->dma_lock, flags);
254         if (host->dma_done)
255                 done = 1;
256         else
257                 host->brs_received = 1;
258         spin_unlock_irqrestore(&host->dma_lock, flags);
259         if (done)
260                 mmc_omap_xfer_done(host, data);
261 }
262
263 static void
264 mmc_omap_dma_timer(unsigned long data)
265 {
266         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
267
268         BUG_ON(host->dma_ch < 0);
269         omap_free_dma(host->dma_ch);
270         host->dma_ch = -1;
271 }
272
273 static void
274 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
275 {
276         unsigned long flags;
277         int done;
278
279         done = 0;
280         spin_lock_irqsave(&host->dma_lock, flags);
281         if (host->brs_received)
282                 done = 1;
283         else
284                 host->dma_done = 1;
285         spin_unlock_irqrestore(&host->dma_lock, flags);
286         if (done)
287                 mmc_omap_xfer_done(host, data);
288 }
289
290 static void
291 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
292 {
293         host->cmd = NULL;
294
295         if (cmd->flags & MMC_RSP_PRESENT) {
296                 if (cmd->flags & MMC_RSP_136) {
297                         /* response type 2 */
298                         cmd->resp[3] =
299                                 OMAP_MMC_READ(host->base, RSP0) |
300                                 (OMAP_MMC_READ(host->base, RSP1) << 16);
301                         cmd->resp[2] =
302                                 OMAP_MMC_READ(host->base, RSP2) |
303                                 (OMAP_MMC_READ(host->base, RSP3) << 16);
304                         cmd->resp[1] =
305                                 OMAP_MMC_READ(host->base, RSP4) |
306                                 (OMAP_MMC_READ(host->base, RSP5) << 16);
307                         cmd->resp[0] =
308                                 OMAP_MMC_READ(host->base, RSP6) |
309                                 (OMAP_MMC_READ(host->base, RSP7) << 16);
310                 } else {
311                         /* response types 1, 1b, 3, 4, 5, 6 */
312                         cmd->resp[0] =
313                                 OMAP_MMC_READ(host->base, RSP6) |
314                                 (OMAP_MMC_READ(host->base, RSP7) << 16);
315                 }
316         }
317
318         if (host->data == NULL || cmd->error != MMC_ERR_NONE) {
319                 host->mrq = NULL;
320                 clk_disable(host->fclk);
321                 mmc_request_done(host->mmc, cmd->mrq);
322         }
323 }
324
325 /* PIO only */
326 static void
327 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
328 {
329         struct scatterlist *sg;
330
331         sg = host->data->sg + host->sg_idx;
332         host->buffer_bytes_left = sg->length;
333         host->buffer = page_address(sg->page) + sg->offset;
334         if (host->buffer_bytes_left > host->total_bytes_left)
335                 host->buffer_bytes_left = host->total_bytes_left;
336 }
337
338 /* PIO only */
339 static void
340 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
341 {
342         int n;
343         void __iomem *reg;
344         u16 *p;
345
346         if (host->buffer_bytes_left == 0) {
347                 host->sg_idx++;
348                 BUG_ON(host->sg_idx == host->sg_len);
349                 mmc_omap_sg_to_buf(host);
350         }
351         n = 64;
352         if (n > host->buffer_bytes_left)
353                 n = host->buffer_bytes_left;
354         host->buffer_bytes_left -= n;
355         host->total_bytes_left -= n;
356         host->data->bytes_xfered += n;
357
358         if (write) {
359                 __raw_writesw(host->base + OMAP_MMC_REG_DATA, host->buffer, n);
360         } else {
361                 __raw_readsw(host->base + OMAP_MMC_REG_DATA, host->buffer, n);
362         }
363 }
364
365 static inline void mmc_omap_report_irq(u16 status)
366 {
367         static const char *mmc_omap_status_bits[] = {
368                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
369                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
370         };
371         int i, c = 0;
372
373         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
374                 if (status & (1 << i)) {
375                         if (c)
376                                 printk(" ");
377                         printk("%s", mmc_omap_status_bits[i]);
378                         c++;
379                 }
380 }
381
382 static irqreturn_t mmc_omap_irq(int irq, void *dev_id, struct pt_regs *regs)
383 {
384         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
385         u16 status;
386         int end_command;
387         int end_transfer;
388         int transfer_error;
389
390         if (host->cmd == NULL && host->data == NULL) {
391                 status = OMAP_MMC_READ(host->base, STAT);
392                 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
393                 if (status != 0) {
394                         OMAP_MMC_WRITE(host->base, STAT, status);
395                         OMAP_MMC_WRITE(host->base, IE, 0);
396                 }
397                 return IRQ_HANDLED;
398         }
399
400         end_command = 0;
401         end_transfer = 0;
402         transfer_error = 0;
403
404         while ((status = OMAP_MMC_READ(host->base, STAT)) != 0) {
405                 OMAP_MMC_WRITE(host->base, STAT, status);
406 #ifdef CONFIG_MMC_DEBUG
407                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
408                         status, host->cmd != NULL ? host->cmd->opcode : -1);
409                 mmc_omap_report_irq(status);
410                 printk("\n");
411 #endif
412                 if (host->total_bytes_left) {
413                         if ((status & OMAP_MMC_STAT_A_FULL) ||
414                             (status & OMAP_MMC_STAT_END_OF_DATA))
415                                 mmc_omap_xfer_data(host, 0);
416                         if (status & OMAP_MMC_STAT_A_EMPTY)
417                                 mmc_omap_xfer_data(host, 1);
418                 }
419
420                 if (status & OMAP_MMC_STAT_END_OF_DATA) {
421                         end_transfer = 1;
422                 }
423
424                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
425                         dev_dbg(mmc_dev(host->mmc), "data timeout\n");
426                         if (host->data) {
427                                 host->data->error |= MMC_ERR_TIMEOUT;
428                                 transfer_error = 1;
429                         }
430                 }
431
432                 if (status & OMAP_MMC_STAT_DATA_CRC) {
433                         if (host->data) {
434                                 host->data->error |= MMC_ERR_BADCRC;
435                                 dev_dbg(mmc_dev(host->mmc),
436                                          "data CRC error, bytes left %d\n",
437                                         host->total_bytes_left);
438                                 transfer_error = 1;
439                         } else {
440                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
441                         }
442                 }
443
444                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
445                         /* Timeouts are routine with some commands */
446                         if (host->cmd) {
447                                 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
448                                                 host->cmd->opcode !=
449                                                 MMC_SEND_OP_COND &&
450                                                 host->cmd->opcode !=
451                                                 MMC_APP_CMD &&
452                                                 !mmc_omap_cover_is_open(host))
453                                         dev_err(mmc_dev(host->mmc),
454                                                 "command timeout, CMD %d\n",
455                                                 host->cmd->opcode);
456                                 host->cmd->error = MMC_ERR_TIMEOUT;
457                                 end_command = 1;
458                         }
459                 }
460
461                 if (status & OMAP_MMC_STAT_CMD_CRC) {
462                         if (host->cmd) {
463                                 dev_err(mmc_dev(host->mmc),
464                                         "command CRC error (CMD%d, arg 0x%08x)\n",
465                                         host->cmd->opcode, host->cmd->arg);
466                                 host->cmd->error = MMC_ERR_BADCRC;
467                                 end_command = 1;
468                         } else
469                                 dev_err(mmc_dev(host->mmc),
470                                         "command CRC error without cmd?\n");
471                 }
472
473                 if (status & OMAP_MMC_STAT_CARD_ERR) {
474                         if (host->cmd && host->cmd->opcode == MMC_STOP_TRANSMISSION) {
475                                 u32 response = OMAP_MMC_READ(host->base, RSP6)
476                                         | (OMAP_MMC_READ(host->base, RSP7) << 16);
477                                 /* STOP sometimes sets must-ignore bits */
478                                 if (!(response & (R1_CC_ERROR
479                                                                 | R1_ILLEGAL_COMMAND
480                                                                 | R1_COM_CRC_ERROR))) {
481                                         end_command = 1;
482                                         continue;
483                                 }
484                         }
485
486                         dev_dbg(mmc_dev(host->mmc), "card status error (CMD%d)\n",
487                                 host->cmd->opcode);
488                         if (host->cmd) {
489                                 host->cmd->error = MMC_ERR_FAILED;
490                                 end_command = 1;
491                         }
492                         if (host->data) {
493                                 host->data->error = MMC_ERR_FAILED;
494                                 transfer_error = 1;
495                         }
496                 }
497
498                 /*
499                  * NOTE: On 1610 the END_OF_CMD may come too early when
500                  * starting a write 
501                  */
502                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
503                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
504                         end_command = 1;
505                 }
506         }
507
508         if (end_command) {
509                 mmc_omap_cmd_done(host, host->cmd);
510         }
511         if (transfer_error)
512                 mmc_omap_xfer_done(host, host->data);
513         else if (end_transfer)
514                 mmc_omap_end_of_data(host, host->data);
515
516         return IRQ_HANDLED;
517 }
518
519 static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id, struct pt_regs *regs)
520 {
521         struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id;
522
523         schedule_work(&host->switch_work);
524
525         return IRQ_HANDLED;
526 }
527
528 static void mmc_omap_switch_timer(unsigned long arg)
529 {
530         struct mmc_omap_host *host = (struct mmc_omap_host *) arg;
531
532         schedule_work(&host->switch_work);
533 }
534
535 /* FIXME: Handle card insertion and removal properly. Maybe use a mask
536  * for MMC state? */
537 static void mmc_omap_switch_callback(unsigned long data, u8 mmc_mask)
538 {
539 }
540
541 static void mmc_omap_switch_handler(void *data)
542 {
543         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
544         struct mmc_card *card;
545         static int complained = 0;
546         int cards = 0, cover_open;
547
548         if (host->switch_pin == -1)
549                 return;
550         cover_open = mmc_omap_cover_is_open(host);
551         if (cover_open != host->switch_last_state) {
552                 kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
553                 host->switch_last_state = cover_open;
554         }
555         mmc_detect_change(host->mmc, 0);
556         list_for_each_entry(card, &host->mmc->cards, node) {
557                 if (mmc_card_present(card))
558                         cards++;
559         }
560         if (mmc_omap_cover_is_open(host)) {
561                 if (!complained) {
562                         dev_info(mmc_dev(host->mmc), "cover is open");
563                         complained = 1;
564                 }
565                 if (mmc_omap_enable_poll)
566                         mod_timer(&host->switch_timer, jiffies +
567                                 msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY));
568         } else {
569                 complained = 0;
570         }
571 }
572
573 /* Prepare to transfer the next segment of a scatterlist */
574 static void
575 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
576 {
577         int dma_ch = host->dma_ch;
578         unsigned long data_addr;
579         u16 buf, frame;
580         u32 count;
581         struct scatterlist *sg = &data->sg[host->sg_idx];
582         int src_port = 0;
583         int dst_port = 0;
584         int sync_dev = 0;
585
586         data_addr = io_v2p((u32) host->base) + OMAP_MMC_REG_DATA;
587         frame = data->blksz;
588         count = sg_dma_len(sg);
589
590         if ((data->blocks == 1) && (count > data->blksz))
591                 count = frame;
592
593         host->dma_len = count;
594
595         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
596          * Use 16 or 32 word frames when the blocksize is at least that large.
597          * Blocksize is usually 512 bytes; but not for some SD reads.
598          */
599         if (cpu_is_omap15xx() && frame > 32)
600                 frame = 32;
601         else if (frame > 64)
602                 frame = 64;
603         count /= frame;
604         frame >>= 1;
605
606         if (!(data->flags & MMC_DATA_WRITE)) {
607                 buf = 0x800f | ((frame - 1) << 8);
608
609                 if (cpu_class_is_omap1()) {
610                         src_port = OMAP_DMA_PORT_TIPB;
611                         dst_port = OMAP_DMA_PORT_EMIFF;
612                 }
613                 if (cpu_is_omap24xx())
614                         sync_dev = OMAP24XX_DMA_MMC1_RX;
615
616                 omap_set_dma_src_params(dma_ch, src_port,
617                                         OMAP_DMA_AMODE_CONSTANT,
618                                         data_addr, 0, 0);
619                 omap_set_dma_dest_params(dma_ch, dst_port,
620                                          OMAP_DMA_AMODE_POST_INC,
621                                          sg_dma_address(sg), 0, 0);
622                 omap_set_dma_dest_data_pack(dma_ch, 1);
623                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
624         } else {
625                 buf = 0x0f80 | ((frame - 1) << 0);
626
627                 if (cpu_class_is_omap1()) {
628                         src_port = OMAP_DMA_PORT_EMIFF;
629                         dst_port = OMAP_DMA_PORT_TIPB;
630                 }
631                 if (cpu_is_omap24xx())
632                         sync_dev = OMAP24XX_DMA_MMC1_TX;
633
634                 omap_set_dma_dest_params(dma_ch, dst_port,
635                                          OMAP_DMA_AMODE_CONSTANT,
636                                          data_addr, 0, 0);
637                 omap_set_dma_src_params(dma_ch, src_port,
638                                         OMAP_DMA_AMODE_POST_INC,
639                                         sg_dma_address(sg), 0, 0);
640                 omap_set_dma_src_data_pack(dma_ch, 1);
641                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
642         }
643
644         /* Max limit for DMA frame count is 0xffff */
645         if (unlikely(count > 0xffff))
646                 BUG();
647
648         OMAP_MMC_WRITE(host->base, BUF, buf);
649         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
650                                      frame, count, OMAP_DMA_SYNC_FRAME,
651                                      sync_dev, 0);
652 }
653
654 /* A scatterlist segment completed */
655 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
656 {
657         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
658         struct mmc_data *mmcdat = host->data;
659
660         if (unlikely(host->dma_ch < 0)) {
661                 dev_err(mmc_dev(host->mmc), "DMA callback while DMA not
662                                 enabled\n");
663                 return;
664         }
665         /* FIXME: We really should do something to _handle_ the errors */
666         if (ch_status & OMAP_DMA_TOUT_IRQ) {
667                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
668                 return;
669         }
670         if (ch_status & OMAP_DMA_DROP_IRQ) {
671                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
672                 return;
673         }
674         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
675                 return;
676         }
677         mmcdat->bytes_xfered += host->dma_len;
678         host->sg_idx++;
679         if (host->sg_idx < host->sg_len) {
680                 mmc_omap_prepare_dma(host, host->data);
681                 omap_start_dma(host->dma_ch);
682         } else
683                 mmc_omap_dma_done(host, host->data);
684 }
685
686 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
687 {
688         const char *dev_name;
689         int sync_dev, dma_ch, is_read, r;
690
691         is_read = !(data->flags & MMC_DATA_WRITE);
692         del_timer_sync(&host->dma_timer);
693         if (host->dma_ch >= 0) {
694                 if (is_read == host->dma_is_read)
695                         return 0;
696                 omap_free_dma(host->dma_ch);
697                 host->dma_ch = -1;
698         }
699
700         if (is_read) {
701                 if (host->id == 1) {
702                         sync_dev = OMAP_DMA_MMC_RX;
703                         dev_name = "MMC1 read";
704                 } else {
705                         sync_dev = OMAP_DMA_MMC2_RX;
706                         dev_name = "MMC2 read";
707                 }
708         } else {
709                 if (host->id == 1) {
710                         sync_dev = OMAP_DMA_MMC_TX;
711                         dev_name = "MMC1 write";
712                 } else {
713                         sync_dev = OMAP_DMA_MMC2_TX;
714                         dev_name = "MMC2 write";
715                 }
716         }
717         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
718                              host, &dma_ch);
719         if (r != 0) {
720                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
721                 return r;
722         }
723         host->dma_ch = dma_ch;
724         host->dma_is_read = is_read;
725
726         return 0;
727 }
728
729 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
730 {
731         u16 reg;
732
733         reg = OMAP_MMC_READ(host->base, SDIO);
734         reg &= ~(1 << 5);
735         OMAP_MMC_WRITE(host->base, SDIO, reg);
736         /* Set maximum timeout */
737         OMAP_MMC_WRITE(host->base, CTO, 0xff);
738 }
739
740 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
741 {
742         int timeout;
743         u16 reg;
744
745         /* Convert ns to clock cycles by assuming 20MHz frequency
746          * 1 cycle at 20MHz = 500 ns
747          */
748         timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
749
750         /* Check if we need to use timeout multiplier register */
751         reg = OMAP_MMC_READ(host->base, SDIO);
752         if (timeout > 0xffff) {
753                 reg |= (1 << 5);
754                 timeout /= 1024;
755         } else
756                 reg &= ~(1 << 5);
757         OMAP_MMC_WRITE(host->base, SDIO, reg);
758         OMAP_MMC_WRITE(host->base, DTO, timeout);
759 }
760
761 static void
762 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
763 {
764         struct mmc_data *data = req->data;
765         int i, use_dma, block_size;
766         unsigned sg_len;
767
768         host->data = data;
769         if (data == NULL) {
770                 OMAP_MMC_WRITE(host->base, BLEN, 0);
771                 OMAP_MMC_WRITE(host->base, NBLK, 0);
772                 OMAP_MMC_WRITE(host->base, BUF, 0);
773                 host->dma_in_use = 0;
774                 set_cmd_timeout(host, req);
775                 return;
776         }
777
778
779         block_size = data->blksz;
780
781         OMAP_MMC_WRITE(host->base, NBLK, data->blocks - 1);
782         OMAP_MMC_WRITE(host->base, BLEN, block_size - 1);
783         set_data_timeout(host, req);
784
785         /* cope with calling layer confusion; it issues "single
786          * block" writes using multi-block scatterlists.
787          */
788         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
789
790         /* Only do DMA for entire blocks */
791         use_dma = host->use_dma;
792         if (use_dma) {
793                 for (i = 0; i < sg_len; i++) {
794                         if ((data->sg[i].length % block_size) != 0) {
795                                 use_dma = 0;
796                                 break;
797                         }
798                 }
799         }
800
801         host->sg_idx = 0;
802         if (use_dma) {
803                 if (mmc_omap_get_dma_channel(host, data) == 0) {
804                         enum dma_data_direction dma_data_dir;
805
806                         if (data->flags & MMC_DATA_WRITE)
807                                 dma_data_dir = DMA_TO_DEVICE;
808                         else
809                                 dma_data_dir = DMA_FROM_DEVICE;
810
811                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
812                                                 sg_len, dma_data_dir);
813                         host->total_bytes_left = 0;
814                         mmc_omap_prepare_dma(host, req->data);
815                         host->brs_received = 0;
816                         host->dma_done = 0;
817                         host->dma_in_use = 1;
818                 } else
819                         use_dma = 0;
820         }
821
822         /* Revert to PIO? */
823         if (!use_dma) {
824                 OMAP_MMC_WRITE(host->base, BUF, 0x1f1f);
825                 host->total_bytes_left = data->blocks * block_size;
826                 host->sg_len = sg_len;
827                 mmc_omap_sg_to_buf(host);
828                 host->dma_in_use = 0;
829         }
830 }
831
832 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
833 {
834         struct mmc_omap_host *host = mmc_priv(mmc);
835
836         WARN_ON(host->mrq != NULL);
837
838         host->mrq = req;
839
840         /* only touch fifo AFTER the controller readies it */
841         mmc_omap_prepare_data(host, req);
842         mmc_omap_start_command(host, req->cmd);
843         if (host->dma_in_use)
844                 omap_start_dma(host->dma_ch);
845 }
846
847 static void innovator_fpga_socket_power(int on)
848 {
849 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
850
851         if (on) {
852                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
853                      OMAP1510_FPGA_POWER);
854         } else {
855                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
856                      OMAP1510_FPGA_POWER);
857         }
858 #endif
859 }
860
861 /*
862  * Turn the socket power on/off. Innovator uses FPGA, most boards
863  * probably use GPIO.
864  */
865 static void mmc_omap_power(struct mmc_omap_host *host, int on)
866 {
867         if (on) {
868                 if (machine_is_omap_innovator())
869                         innovator_fpga_socket_power(1);
870                 else if (machine_is_omap_h2())
871                         tps65010_set_gpio_out_value(GPIO3, HIGH);
872                 else if (machine_is_omap_h3())
873                         /* GPIO 4 of TPS65010 sends SD_EN signal */
874                         tps65010_set_gpio_out_value(GPIO4, HIGH);
875                 else if (cpu_is_omap24xx()) {
876                         u16 reg = OMAP_MMC_READ(host->base, CON);
877                         OMAP_MMC_WRITE(host->base, CON, reg | (1 << 11));
878                 } else
879                         if (host->power_pin >= 0)
880                                 omap_set_gpio_dataout(host->power_pin, 1);
881         } else {
882                 if (machine_is_omap_innovator())
883                         innovator_fpga_socket_power(0);
884                 else if (machine_is_omap_h2())
885                         tps65010_set_gpio_out_value(GPIO3, LOW);
886                 else if (machine_is_omap_h3())
887                         tps65010_set_gpio_out_value(GPIO4, LOW);
888                 else if (cpu_is_omap24xx()) {
889                         u16 reg = OMAP_MMC_READ(host->base, CON);
890                         OMAP_MMC_WRITE(host->base, CON, reg & ~(1 << 11));
891                 } else
892                         if (host->power_pin >= 0)
893                                 omap_set_gpio_dataout(host->power_pin, 0);
894         }
895 }
896
897 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
898 {
899         struct mmc_omap_host *host = mmc_priv(mmc);
900         int dsor;
901         int realclock, i;
902
903         realclock = ios->clock;
904
905         if (ios->clock == 0)
906                 dsor = 0;
907         else {
908                 int func_clk_rate = clk_get_rate(host->fclk);
909
910                 dsor = func_clk_rate / realclock;
911                 if (dsor < 1)
912                         dsor = 1;
913
914                 if (func_clk_rate / dsor > realclock)
915                         dsor++;
916
917                 if (dsor > 250)
918                         dsor = 250;
919                 dsor++;
920
921                 if (ios->bus_width == MMC_BUS_WIDTH_4)
922                         dsor |= 1 << 15;
923         }
924
925         switch (ios->power_mode) {
926         case MMC_POWER_OFF:
927                 mmc_omap_power(host, 0);
928                 break;
929         case MMC_POWER_UP:
930         case MMC_POWER_ON:
931                 mmc_omap_power(host, 1);
932                 dsor |= 1<<11;
933                 break;
934         }
935
936         host->bus_mode = ios->bus_mode;
937         host->hw_bus_mode = host->bus_mode;
938
939         clk_enable(host->fclk);
940
941         /* On insanely high arm_per frequencies something sometimes
942          * goes somehow out of sync, and the POW bit is not being set,
943          * which results in the while loop below getting stuck.
944          * Writing to the CON register twice seems to do the trick. */
945         for (i = 0; i < 2; i++)
946                 OMAP_MMC_WRITE(host->base, CON, dsor);
947         if (ios->power_mode == MMC_POWER_UP) {
948                 /* Send clock cycles, poll completion */
949                 OMAP_MMC_WRITE(host->base, IE, 0);
950                 OMAP_MMC_WRITE(host->base, STAT, 0xffff);
951                 OMAP_MMC_WRITE(host->base, CMD, 1<<7);
952                 while (0 == (OMAP_MMC_READ(host->base, STAT) & 1));
953                 OMAP_MMC_WRITE(host->base, STAT, 1);
954         }
955         clk_disable(host->fclk);
956 }
957
958 static int mmc_omap_get_ro(struct mmc_host *mmc)
959 {
960         struct mmc_omap_host *host = mmc_priv(mmc);
961
962         return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
963 }
964
965 static struct mmc_host_ops mmc_omap_ops = {
966         .request        = mmc_omap_request,
967         .set_ios        = mmc_omap_set_ios,
968         .get_ro         = mmc_omap_get_ro,
969 };
970
971 static int __init mmc_omap_probe(struct platform_device *pdev)
972 {
973         struct omap_mmc_conf *minfo = pdev->dev.platform_data;
974         struct mmc_host *mmc;
975         struct mmc_omap_host *host = NULL;
976         int ret = 0;
977         
978         if (platform_get_resource(pdev, IORESOURCE_MEM, 0) ||
979                         platform_get_irq(pdev, IORESOURCE_IRQ, 0)) {
980                 dev_err(&pdev->dev, "mmc_omap_probe: invalid resource type\n");
981                 return -ENODEV;
982         }
983
984         if (!request_mem_region(pdev->resource[0].start,
985                                 pdev->resource[0].end - pdev->resource[0].start + 1,
986                                 pdev->name)) {
987                 dev_dbg(&pdev->dev, "request_mem_region failed\n");
988                 return -EBUSY;
989         }
990
991         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
992         if (!mmc) {
993                 ret = -ENOMEM;
994                 goto out;
995         }
996
997         host = mmc_priv(mmc);
998         host->mmc = mmc;
999
1000         spin_lock_init(&host->dma_lock);
1001         init_timer(&host->dma_timer);
1002         host->dma_timer.function = mmc_omap_dma_timer;
1003         host->dma_timer.data = (unsigned long) host;
1004
1005         host->id = pdev->id;
1006
1007         if (cpu_is_omap24xx()) {
1008                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1009                 if (IS_ERR(host->iclk))
1010                         goto out;
1011                 clk_enable(host->iclk);
1012         }
1013
1014         if (!cpu_is_omap24xx())
1015                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1016         else
1017                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1018
1019         if (IS_ERR(host->fclk)) {
1020                 ret = PTR_ERR(host->fclk);
1021                 goto out;
1022         }
1023
1024         /* REVISIT:
1025          * Also, use minfo->cover to decide how to manage
1026          * the card detect sensing.
1027          */
1028         host->power_pin = minfo->power_pin;
1029         host->switch_pin = minfo->switch_pin;
1030         host->wp_pin = minfo->wp_pin;
1031         host->use_dma = 1;
1032         host->dma_ch = -1;
1033
1034         host->irq = pdev->resource[1].start;
1035         host->base = ioremap(pdev->res.start, SZ_4K);
1036         if (!host->base) {
1037                 ret = -ENOMEM;
1038                 goto out;
1039         }
1040
1041          if (minfo->wire4)
1042                  mmc->caps |= MMC_CAP_4_BIT_DATA;
1043
1044         mmc->ops = &mmc_omap_ops;
1045         mmc->f_min = 400000;
1046         mmc->f_max = 24000000;
1047         mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
1048
1049         /* Use scatterlist DMA to reduce per-transfer costs.
1050          * NOTE max_seg_size assumption that small blocks aren't
1051          * normally used (except e.g. for reading SD registers).
1052          */
1053         mmc->max_phys_segs = 32;
1054         mmc->max_hw_segs = 32;
1055         mmc->max_sectors = 256; /* NBLK max 11-bits, OMAP also limited by DMA */
1056         mmc->max_seg_size = mmc->max_sectors * 512;
1057
1058         if (host->power_pin >= 0) {
1059                 if ((ret = omap_request_gpio(host->power_pin)) != 0) {
1060                         dev_err(mmc_dev(host->mmc), "Unable to get GPIO
1061                                         pin for MMC power\n");
1062                         goto out;
1063                 }
1064                 omap_set_gpio_direction(host->power_pin, 0);
1065         }
1066
1067         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1068         if (ret)
1069                 goto out;
1070
1071         host->dev = &pdev->dev;
1072         platform_set_drvdata(pdev, host);
1073
1074         mmc_add_host(mmc);
1075
1076         if (host->switch_pin >= 0) {
1077                 INIT_WORK(&host->switch_work, mmc_omap_switch_handler, host);
1078                 init_timer(&host->switch_timer);
1079                 host->switch_timer.function = mmc_omap_switch_timer;
1080                 host->switch_timer.data = (unsigned long) host;
1081                 if (omap_request_gpio(host->switch_pin) != 0) {
1082                         dev_warn(mmc_dev(host->mmc), "Unable to get GPIO pin for MMC cover switch\n");
1083                         host->switch_pin = -1;
1084                         goto no_switch;
1085                 }
1086
1087                 omap_set_gpio_direction(host->switch_pin, 1);
1088                 ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin),
1089                                   mmc_omap_switch_irq, SA_TRIGGER_RISING, DRIVER_NAME, host);
1090                 if (ret) {
1091                         dev_warn(mmc_dev(host->mmc), "Unable to get IRQ for MMC cover switch\n");
1092                         omap_free_gpio(host->switch_pin);
1093                         host->switch_pin = -1;
1094                         goto no_switch;
1095                 }
1096                 ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
1097                 if (ret == 0) {
1098                         ret = device_create_file(&pdev->dev, &dev_attr_enable_poll);
1099                         if (ret != 0)
1100                                 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1101                 }
1102                 if (ret) {
1103                         dev_wan(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
1104                         free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1105                         omap_free_gpio(host->switch_pin);
1106                         host->switch_pin = -1;
1107                         goto no_switch;
1108                 }
1109                 if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host))
1110                         schedule_work(&host->switch_work);
1111         }
1112
1113 no_switch:
1114         return 0;
1115
1116 out:
1117         /* FIXME: Free other resources too. */
1118         if (host) {
1119                 if (host->iclk && !IS_ERR(host->iclk))
1120                         clk_put(host->iclk);
1121                 if (host->fclk && !IS_ERR(host->fclk))
1122                         clk_put(host->fclk);
1123                 mmc_free_host(host->mmc);
1124         }
1125         return ret;
1126 }
1127
1128 static int mmc_omap_remove(struct platform_device *pdev)
1129 {
1130         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1131
1132         platform_set_drvdata(pdev, NULL);
1133
1134         if (host) {
1135                 mmc_remove_host(host->mmc);
1136                 free_irq(host->irq, host);
1137
1138                 if (host->power_pin >= 0)
1139                         omap_free_gpio(host->power_pin);
1140                 if (host->switch_pin >= 0) {
1141                         device_remove_file(&pdev->dev, &dev_attr_enable_poll);
1142                         device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1143                         free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1144                         omap_free_gpio(host->switch_pin);
1145                         host->switch_pin = -1;
1146                         del_timer_sync(&host->switch_timer);
1147                         flush_scheduled_work();
1148                 }
1149                 if (host->iclk && !IS_ERR(host->iclk))
1150                         clk_put(host->iclk);
1151                 if (host->fclk && !IS_ERR(host->fclk))
1152                         clk_put(host->fclk);
1153                 mmc_free_host(host->mmc);
1154         }
1155
1156         release_mem_region(pdev->resource[0].start,
1157                         pdev->resource[0].end - pdev->resource[0].start + 1);
1158
1159         return 0;
1160 }
1161
1162 #ifdef CONFIG_PM
1163 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1164 {
1165         int ret = 0;
1166         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1167
1168         if (host && host->suspended)
1169                 return 0;
1170
1171         if (host) {
1172                 ret = mmc_suspend_host(host->mmc, mesg);
1173                 if (ret == 0)
1174                         host->suspended = 1;
1175         }
1176         return ret;
1177 }
1178
1179 static int mmc_omap_resume(struct platform_device *pdev)
1180 {
1181         int ret = 0;
1182         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1183
1184         if (host && !host->suspended)
1185                 return 0;
1186
1187         if (host) {
1188                 ret = mmc_resume_host(host->mmc);
1189                 if (ret == 0)
1190                         host->suspended = 0;
1191         }
1192
1193         return ret;
1194 }
1195 #else
1196 #define mmc_omap_suspend        NULL
1197 #define mmc_omap_resume         NULL
1198 #endif
1199
1200 static struct platform_driver mmc_omap_driver = {
1201         .probe          = mmc_omap_probe,
1202         .remove         = mmc_omap_remove,
1203         .suspend        = mmc_omap_suspend,
1204         .resume         = mmc_omap_resume,
1205         .driver         = {
1206                 .name   = DRIVER_NAME,
1207         },
1208 };
1209
1210 static int __init mmc_omap_init(void)
1211 {
1212         return platform_driver_register(&mmc_omap_driver);
1213 }
1214
1215 static void __exit mmc_omap_exit(void)
1216 {
1217         platform_driver_unregister(&mmc_omap_driver);
1218 }
1219
1220 module_init(mmc_omap_init);
1221 module_exit(mmc_omap_exit);
1222
1223 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1224 MODULE_LICENSE("GPL");
1225 MODULE_ALIAS(DRIVER_NAME);
1226 MODULE_AUTHOR("Juha Yrjölä");