Merge linux-3.10.67 into dev-kernel-3.10
[linux-3.10.git] / drivers / mmc / host / sdhci.c
1 /*
2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3  *
4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5  *  Copyright (C) 2012-2015, NVIDIA CORPORATION.  All rights reserved.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or (at
10  * your option) any later version.
11  *
12  * Thanks to the following companies for their support:
13  *
14  *     - JMicron (hardware and technical support)
15  */
16
17 #include <linux/delay.h>
18 #include <linux/highmem.h>
19 #include <linux/io.h>
20 #include <linux/module.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/slab.h>
23 #include <linux/scatterlist.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/platform_device.h>
27 #include <linux/sched.h>
28
29 #include <linux/leds.h>
30
31 #include <linux/mmc/mmc.h>
32 #include <linux/mmc/host.h>
33 #include <linux/mmc/card.h>
34 #include <linux/mmc/slot-gpio.h>
35
36 #include <linux/sysedp.h>
37 #ifdef CONFIG_DEBUG_FS
38 #include <linux/debugfs.h>
39 #include <linux/ktime.h>
40 #endif
41
42 #ifdef CONFIG_EMMC_BLKTRACE
43 #include <linux/mmc/emmc-trace.h>
44 #include "../card/queue.h"
45 #endif
46 #include "sdhci.h"
47
48 #define DRIVER_NAME "sdhci"
49
50 #define DBG(f, x...) \
51         pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x)
52 #define MMC_CHECK_CMDQ_MODE(host)                       \
53         (host && host->mmc &&                                   \
54         host->mmc->card &&                                              \
55         host->mmc->card->ext_csd.cmdq_mode_en)
56
57 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
58         defined(CONFIG_MMC_SDHCI_MODULE))
59 #define SDHCI_USE_LEDS_CLASS
60 #endif
61
62 #define MAX_TUNING_LOOP 40
63
64 #ifdef CONFIG_CMD_DUMP
65 static volatile unsigned int printk_cpu_test = UINT_MAX;
66 struct timeval cur_tv;
67 struct timeval prev_tv, curr_tv;
68 void mmc_cmd_dump(struct mmc_host *host);
69 void dbg_add_host_log(struct mmc_host *host, int type, int cmd, int arg)
70 {
71         unsigned long long t;
72         unsigned long long nanosec_rem;
73         unsigned long flags;
74         spin_lock_irqsave(&host->cmd_dump_lock, flags);
75
76         if (host->dbg_run_host_log_dat[host->dbg_host_cnt - 1].type == type &&
77                 host->dbg_run_host_log_dat[host->dbg_host_cnt - 1].cmd == cmd &&
78                 host->dbg_run_host_log_dat[host->dbg_host_cnt - 1].arg == arg) {
79                 spin_unlock_irqrestore(&host->cmd_dump_lock, flags);
80                 return;
81         }
82         t = cpu_clock(printk_cpu_test);
83         nanosec_rem = do_div(t, 1000000000)/1000;
84         do_gettimeofday(&cur_tv);
85         host->dbg_run_host_log_dat[host->dbg_host_cnt].time_sec = t;
86         host->dbg_run_host_log_dat[host->dbg_host_cnt].time_usec = nanosec_rem;
87         host->dbg_run_host_log_dat[host->dbg_host_cnt].type = type;
88         host->dbg_run_host_log_dat[host->dbg_host_cnt].cmd = cmd;
89         host->dbg_run_host_log_dat[host->dbg_host_cnt].arg = arg;
90         host->dbg_host_cnt++;
91         if (host->dbg_host_cnt >= dbg_max_cnt)
92                 host->dbg_host_cnt = 0;
93         spin_unlock_irqrestore(&host->cmd_dump_lock, flags);
94 }
95 #endif
96
97 /* MMC_RTPM timeout */
98 #define MMC_RTPM_MSEC_TMOUT 10
99
100 /* SDIO 1msec timeout, but use 10msec timeout for HZ=100 */
101 #define SDIO_CLK_GATING_TICK_TMOUT ((HZ >= 1000) ? (HZ / 1000) : 1)
102 /* 20msec EMMC delayed clock gate timeout */
103 #define EMMC_CLK_GATING_TICK_TMOUT ((HZ >= 50) ? (HZ / 50) : 2)
104
105 #define IS_SDIO_CARD(host) \
106                 (host->mmc->card && \
107                 (host->mmc->card->type == MMC_TYPE_SDIO))
108
109 #define IS_EMMC_CARD(host) \
110                 (host->mmc->card && \
111                 (host->mmc->card->type == MMC_TYPE_MMC))
112
113 #define IS_SDIO_CARD_OR_EMMC(host) \
114                 (host->mmc->card && \
115                 ((host->mmc->card->type == MMC_TYPE_SDIO) || \
116                 (host->mmc->card->type == MMC_TYPE_MMC)))
117
118 #define IS_DELAYED_CLK_GATE(host) \
119                 ((host->quirks2 & SDHCI_QUIRK2_DELAYED_CLK_GATE) && \
120                 (IS_SDIO_CARD_OR_EMMC(host)) && \
121                 (host->mmc->caps2 & MMC_CAP2_CLOCK_GATING))
122
123 #ifdef CONFIG_DEBUG_FS
124
125 #define IS_32_BIT(x)    (x < (1ULL << 32))
126
127 #define IS_DATA_READ(flags)     ((flags & MMC_DATA_READ) ? true : false)
128
129 #define PERF_STAT_COMPARE(stat, blk_size, blk_count, is_read) \
130                 ( \
131                         (stat->is_read == is_read) && \
132                         (stat->stat_blk_size == blk_size) && \
133                         (stat->stat_blks_per_transfer == blk_count) \
134                 )
135
136 #endif
137
138 #define MIN_SDMMC_FREQ 400000
139
140 static unsigned int debug_quirks;
141 static unsigned int debug_quirks2;
142
143 static void sdhci_finish_data(struct sdhci_host *);
144
145 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
146 static void sdhci_finish_command(struct sdhci_host *);
147 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
148 static int sdhci_validate_sd2_0(struct mmc_host *mmc);
149 static void sdhci_tuning_timer(unsigned long data);
150 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
151
152 #ifdef CONFIG_PM_RUNTIME
153 static int sdhci_runtime_pm_get(struct sdhci_host *host);
154 static int sdhci_runtime_pm_put(struct sdhci_host *host);
155 #else
156 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
157 {
158         return 0;
159 }
160 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
161 {
162         return 0;
163 }
164 static inline int sdhci_runtime_resume_host(struct sdhci_host *host)
165 {
166         return 0;
167 }
168 static inline int sdhci_runtime_suspend_host(struct sdhci_host *host)
169 {
170         return 0;
171 }
172 #endif
173
174 static void sdhci_dumpregs(struct sdhci_host *host)
175 {
176         pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
177                 mmc_hostname(host->mmc));
178
179         pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
180                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
181                 sdhci_readw(host, SDHCI_HOST_VERSION));
182         pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
183                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
184                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
185         pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
186                 sdhci_readl(host, SDHCI_ARGUMENT),
187                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
188         pr_err(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
189                 sdhci_readl(host, SDHCI_PRESENT_STATE),
190                 sdhci_readb(host, SDHCI_HOST_CONTROL));
191         pr_err(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
192                 sdhci_readb(host, SDHCI_POWER_CONTROL),
193                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
194         pr_err(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
195                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
196                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
197         pr_err(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
198                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
199                 sdhci_readl(host, SDHCI_INT_STATUS));
200         pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
201                 sdhci_readl(host, SDHCI_INT_ENABLE),
202                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
203         pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
204                 sdhci_readw(host, SDHCI_ACMD12_ERR),
205                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
206         pr_err(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
207                 sdhci_readl(host, SDHCI_CAPABILITIES),
208                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
209         pr_err(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
210                 sdhci_readw(host, SDHCI_COMMAND),
211                 sdhci_readl(host, SDHCI_MAX_CURRENT));
212         pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n",
213                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
214
215         if (host->flags & SDHCI_USE_ADMA)
216                 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
217                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
218                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
219
220         if (host->ops->dump_host_cust_regs)
221                 host->ops->dump_host_cust_regs(host);
222
223         pr_err(DRIVER_NAME ": ===========================================\n");
224 }
225
226 /*****************************************************************************\
227  *                                                                           *
228  * Low level functions                                                       *
229  *                                                                           *
230 \*****************************************************************************/
231
232 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
233 {
234         host->ier &= ~clear;
235         host->ier |= set;
236         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
237         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
238 }
239
240 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
241 {
242         sdhci_clear_set_irqs(host, 0, irqs);
243 }
244
245 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
246 {
247         sdhci_clear_set_irqs(host, irqs, 0);
248 }
249
250 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
251 {
252         u32 present, irqs;
253
254         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
255             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
256                 return;
257
258         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
259                               SDHCI_CARD_PRESENT;
260         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
261
262         if (enable)
263                 sdhci_unmask_irqs(host, irqs);
264         else
265                 sdhci_mask_irqs(host, irqs);
266 }
267
268 static void sdhci_enable_card_detection(struct sdhci_host *host)
269 {
270         sdhci_set_card_detection(host, true);
271 }
272
273 static void sdhci_disable_card_detection(struct sdhci_host *host)
274 {
275         sdhci_set_card_detection(host, false);
276 }
277
278 static void sdhci_reset(struct sdhci_host *host, u8 mask)
279 {
280         u32 ctrl;
281         unsigned long timeout;
282
283         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
284                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
285                         SDHCI_CARD_PRESENT))
286                         return;
287         }
288
289         if (host->ops->platform_reset_enter)
290                 host->ops->platform_reset_enter(host, mask);
291
292         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
293
294         if (mask & SDHCI_RESET_ALL)
295                 host->clock = 0;
296
297         /* Wait max 100 ms */
298         timeout = 100;
299
300         /* hw clears the bit when it's done */
301         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
302                 if (timeout == 0) {
303                         pr_err("%s: Reset 0x%x never completed.\n",
304                                 mmc_hostname(host->mmc), (int)mask);
305                         sdhci_dumpregs(host);
306                         return;
307                 }
308                 timeout--;
309                 mdelay(1);
310         }
311
312         if (host->ops->platform_reset_exit)
313                 host->ops->platform_reset_exit(host, mask);
314
315         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
316                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, host->ier);
317
318         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
319                 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
320                         host->ops->enable_dma(host);
321         }
322
323         /*
324          * VERSION_4_EN bit and 64BIT_EN bit are cleared after a full reset
325          * need to re-configure them after each full reset
326          */
327         if ((mask & SDHCI_RESET_ALL) && host->version >= SDHCI_SPEC_400) {
328                 ctrl = sdhci_readl(host, SDHCI_ACMD12_ERR);
329                 ctrl |= SDHCI_HOST_VERSION_4_EN;
330                 if (host->quirks2 & SDHCI_QUIRK2_SUPPORT_64BIT_DMA)
331                         ctrl |= SDHCI_ADDRESSING_64BIT_EN;
332                 sdhci_writel(host, ctrl, SDHCI_ACMD12_ERR);
333         }
334 }
335
336 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
337
338 static void sdhci_init(struct sdhci_host *host, int soft)
339 {
340         if (soft)
341                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
342         else
343                 sdhci_reset(host, SDHCI_RESET_ALL);
344
345         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
346                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
347                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
348                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
349                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
350
351         if (soft) {
352                 /* force clock reconfiguration */
353                 host->clock = 0;
354                 sdhci_set_ios(host->mmc, &host->mmc->ios);
355         }
356 }
357
358 static void sdhci_reinit(struct sdhci_host *host)
359 {
360         sdhci_init(host, 0);
361         /*
362          * Retuning stuffs are affected by different cards inserted and only
363          * applicable to UHS-I cards. So reset these fields to their initial
364          * value when card is removed.
365          */
366         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
367                 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
368
369                 del_timer_sync(&host->tuning_timer);
370                 host->flags &= ~SDHCI_NEEDS_RETUNING;
371                 host->mmc->max_blk_count =
372                         (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
373         }
374         sdhci_enable_card_detection(host);
375 }
376
377 static void sdhci_activate_led(struct sdhci_host *host)
378 {
379         u8 ctrl;
380
381         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
382         ctrl |= SDHCI_CTRL_LED;
383         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
384 }
385
386 static void sdhci_deactivate_led(struct sdhci_host *host)
387 {
388         u8 ctrl;
389
390         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
391         ctrl &= ~SDHCI_CTRL_LED;
392         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
393 }
394
395 #ifdef SDHCI_USE_LEDS_CLASS
396 static void sdhci_led_control(struct led_classdev *led,
397         enum led_brightness brightness)
398 {
399         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
400         unsigned long flags;
401
402         spin_lock_irqsave(&host->lock, flags);
403
404         if (host->runtime_suspended)
405                 goto out;
406
407         if (brightness == LED_OFF)
408                 sdhci_deactivate_led(host);
409         else
410                 sdhci_activate_led(host);
411 out:
412         spin_unlock_irqrestore(&host->lock, flags);
413 }
414 #endif
415
416 /*****************************************************************************\
417  *                                                                           *
418  * Core functions                                                            *
419  *                                                                           *
420 \*****************************************************************************/
421
422 static void sdhci_read_block_pio(struct sdhci_host *host)
423 {
424         unsigned long flags;
425         size_t blksize, len, chunk;
426         u32 uninitialized_var(scratch);
427         u8 *buf;
428
429         DBG("PIO reading\n");
430
431         blksize = host->data->blksz;
432         chunk = 0;
433
434         local_irq_save(flags);
435
436         while (blksize) {
437                 if (!sg_miter_next(&host->sg_miter))
438                         BUG();
439
440                 len = min(host->sg_miter.length, blksize);
441
442                 blksize -= len;
443                 host->sg_miter.consumed = len;
444
445                 buf = host->sg_miter.addr;
446
447                 while (len) {
448                         if (chunk == 0) {
449                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
450                                 chunk = 4;
451                         }
452
453                         *buf = scratch & 0xFF;
454
455                         buf++;
456                         scratch >>= 8;
457                         chunk--;
458                         len--;
459                 }
460         }
461
462         sg_miter_stop(&host->sg_miter);
463
464         local_irq_restore(flags);
465 }
466
467 static void sdhci_write_block_pio(struct sdhci_host *host)
468 {
469         unsigned long flags;
470         size_t blksize, len, chunk;
471         u32 scratch;
472         u8 *buf;
473
474         DBG("PIO writing\n");
475
476         blksize = host->data->blksz;
477         chunk = 0;
478         scratch = 0;
479
480         local_irq_save(flags);
481
482         while (blksize) {
483                 if (!sg_miter_next(&host->sg_miter))
484                         BUG();
485
486                 len = min(host->sg_miter.length, blksize);
487
488                 blksize -= len;
489                 host->sg_miter.consumed = len;
490
491                 buf = host->sg_miter.addr;
492
493                 while (len) {
494                         scratch |= (u32)*buf << (chunk * 8);
495
496                         buf++;
497                         chunk++;
498                         len--;
499
500                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
501                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
502                                 chunk = 0;
503                                 scratch = 0;
504                         }
505                 }
506         }
507
508         sg_miter_stop(&host->sg_miter);
509
510         local_irq_restore(flags);
511 }
512
513 static void sdhci_transfer_pio(struct sdhci_host *host)
514 {
515         u32 mask;
516
517         BUG_ON(!host->data);
518
519         if (host->data->flags & MMC_DATA_READ)
520                 mask = SDHCI_DATA_AVAILABLE;
521         else
522                 mask = SDHCI_SPACE_AVAILABLE;
523
524         /*
525          * Some controllers (JMicron JMB38x) mess up the buffer bits
526          * for transfers < 4 bytes. As long as it is just one block,
527          * we can ignore the bits.
528          */
529         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
530                 (host->data->blocks == 1))
531                 mask = ~0;
532
533         /*
534          * Start the transfer if the present state register indicates
535          * SDHCI_DATA_AVAILABLE or SDHCI_SPACE_AVAILABLE. The driver should
536          * transfer one complete block of data and wait for the buffer ready
537          * interrupt to transfer the next block of data.
538          */
539         if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
540                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
541                         udelay(100);
542
543                 if (host->data->flags & MMC_DATA_READ)
544                         sdhci_read_block_pio(host);
545                 else
546                         sdhci_write_block_pio(host);
547         }
548
549         DBG("PIO transfer complete.\n");
550 }
551
552 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
553 {
554         local_irq_save(*flags);
555         return kmap_atomic(sg_page(sg)) + sg->offset;
556 }
557
558 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
559 {
560         kunmap_atomic(buffer);
561         local_irq_restore(*flags);
562 }
563
564 static void sdhci_set_adma_desc(struct sdhci_host *host, u8 *desc,
565                                 dma_addr_t addr, int len, unsigned cmd)
566 {
567         __le32 *dataddr = (__le32 __force *)(desc + 4);
568         __le64 *dataddr64 = (__le64 __force *)(desc + 4);
569         __le16 *cmdlen = (__le16 __force *)desc;
570         u32 ctrl;
571
572         /* SDHCI specification says ADMA descriptors should be 4 byte
573          * aligned, so using 16 or 32bit operations should be safe. */
574
575         cmdlen[0] = cpu_to_le16(cmd);
576         cmdlen[1] = cpu_to_le16(len);
577
578         ctrl = sdhci_readl(host, SDHCI_ACMD12_ERR);
579         if (ctrl & SDHCI_ADDRESSING_64BIT_EN)
580                 dataddr64[0] = cpu_to_le64(addr);
581         else
582                 dataddr[0] = cpu_to_le32(addr);
583 }
584
585 static int sdhci_adma_table_pre(struct sdhci_host *host,
586         struct mmc_data *data)
587 {
588         int direction;
589
590         u8 *desc;
591         u8 *align;
592         dma_addr_t addr;
593         dma_addr_t align_addr;
594         int len, offset;
595
596         struct scatterlist *sg;
597         int i;
598         char *buffer;
599         unsigned long flags;
600         int next_desc;
601         u32 ctrl;
602
603         /*
604          * The spec does not specify endianness of descriptor table.
605          * We currently guess that it is LE.
606          */
607
608         if (data->flags & MMC_DATA_READ)
609                 direction = DMA_FROM_DEVICE;
610         else
611                 direction = DMA_TO_DEVICE;
612
613         /*
614          * The ADMA descriptor table is mapped further down as we
615          * need to fill it with data first.
616          */
617
618         if (!host->use_dma_alloc) {
619                 host->align_addr = dma_map_single(mmc_dev(host->mmc),
620                         host->align_buffer, 128 * 8, direction);
621                 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
622                         goto fail;
623                 BUG_ON(host->align_addr & 0x3);
624         }
625
626         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
627                 data->sg, data->sg_len, direction);
628         if (host->sg_count == 0)
629                 goto unmap_align;
630
631         desc = host->adma_desc;
632         align = host->align_buffer;
633
634         align_addr = host->align_addr;
635
636         ctrl = sdhci_readl(host, SDHCI_ACMD12_ERR);
637         if (ctrl & SDHCI_ADDRESSING_64BIT_EN) {
638                 if (ctrl & SDHCI_HOST_VERSION_4_EN)
639                         next_desc = 16;
640                 else
641                         next_desc = 12;
642         } else {
643                 /* 32 bit DMA mode supported */
644                 next_desc = 8;
645         }
646
647         for_each_sg(data->sg, sg, host->sg_count, i) {
648                 addr = sg_dma_address(sg);
649                 len = sg_dma_len(sg);
650
651                 /*
652                  * The SDHCI specification states that ADMA
653                  * addresses must be 32-bit aligned. If they
654                  * aren't, then we use a bounce buffer for
655                  * the (up to three) bytes that screw up the
656                  * alignment.
657                  */
658                 offset = (4 - (addr & 0x3)) & 0x3;
659                 if (offset) {
660                         if (data->flags & MMC_DATA_WRITE) {
661                                 buffer = sdhci_kmap_atomic(sg, &flags);
662                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
663                                 memcpy(align, buffer, offset);
664                                 sdhci_kunmap_atomic(buffer, &flags);
665                         }
666
667                         /* tran, valid */
668                         sdhci_set_adma_desc(host, desc, align_addr, offset,
669                                                 0x21);
670
671                         BUG_ON(offset > 65536);
672
673                         align += 4;
674                         align_addr += 4;
675
676                         desc += next_desc;
677
678                         addr += offset;
679                         len -= offset;
680                 }
681
682                 BUG_ON(len > 65536);
683
684                 /* tran, valid */
685                 if (len > 0) {
686                         sdhci_set_adma_desc(host, desc, addr, len, 0x21);
687                         desc += next_desc;
688                 }
689
690                 /*
691                  * If this triggers then we have a calculation bug
692                  * somewhere. :/
693                  */
694                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 8);
695         }
696
697         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
698                 /*
699                 * Mark the last descriptor as the terminating descriptor
700                 */
701                 if (desc != host->adma_desc) {
702                         desc -= next_desc;
703                         desc[0] |= 0x3; /* end and valid*/
704                 }
705         } else {
706                 /*
707                 * Add a terminating entry.
708                 */
709
710                 /* nop, end, valid */
711                 sdhci_set_adma_desc(host, desc, 0, 0, 0x3);
712         }
713
714         /*
715          * Resync align buffer as we might have changed it.
716          */
717         if (data->flags & MMC_DATA_WRITE) {
718                 dma_sync_single_for_device(mmc_dev(host->mmc),
719                         host->align_addr, 128 * 8, direction);
720         }
721
722         if (!host->use_dma_alloc) {
723                 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
724                         host->adma_desc, (128 * 2 + 1) * 8, DMA_TO_DEVICE);
725                 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
726                         goto unmap_entries;
727                 BUG_ON(host->adma_addr & 0x3);
728         }
729
730         return 0;
731
732 unmap_entries:
733         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
734                 data->sg_len, direction);
735 unmap_align:
736         if (!host->use_dma_alloc)
737                 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
738                                 128 * 8, direction);
739 fail:
740         return -EINVAL;
741 }
742
743 static void sdhci_adma_table_post(struct sdhci_host *host,
744         struct mmc_data *data)
745 {
746         int direction;
747
748         struct scatterlist *sg;
749         int i, size;
750         u8 *align;
751         char *buffer;
752         unsigned long flags;
753
754         if (data->flags & MMC_DATA_READ)
755                 direction = DMA_FROM_DEVICE;
756         else
757                 direction = DMA_TO_DEVICE;
758
759         if (!host->use_dma_alloc) {
760                 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
761                         (128 * 2 + 1) * 8, DMA_TO_DEVICE);
762
763                 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
764                         128 * 8, direction);
765         }
766
767         if (data->flags & MMC_DATA_READ) {
768                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
769                         data->sg_len, direction);
770
771                 align = host->align_buffer;
772
773                 for_each_sg(data->sg, sg, host->sg_count, i) {
774                         if (sg_dma_address(sg) & 0x3) {
775                                 size = 4 - (sg_dma_address(sg) & 0x3);
776
777                                 buffer = sdhci_kmap_atomic(sg, &flags);
778                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
779                                 memcpy(buffer, align, size);
780                                 sdhci_kunmap_atomic(buffer, &flags);
781
782                                 align += 4;
783                         }
784                 }
785         }
786
787         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
788                 data->sg_len, direction);
789 }
790
791 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
792 {
793         u8 count;
794         struct mmc_data *data = cmd->data;
795         unsigned target_timeout, current_timeout;
796
797         /*
798          * If the host controller provides us with an incorrect timeout
799          * value, just skip the check and use 0xE.  The hardware may take
800          * longer to time out, but that's much better than having a too-short
801          * timeout value.
802          */
803         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
804                 return 0xE;
805
806         /* Unspecified timeout, assume max */
807         if (!data && !cmd->cmd_timeout_ms)
808                 return 0xE;
809
810         /* timeout in us */
811         if (!data)
812                 target_timeout = cmd->cmd_timeout_ms * 1000;
813         else {
814                 target_timeout = data->timeout_ns / 1000;
815                 if (host->clock)
816                         target_timeout += data->timeout_clks / host->clock;
817         }
818
819         /*
820          * Figure out needed cycles.
821          * We do this in steps in order to fit inside a 32 bit int.
822          * The first step is the minimum timeout, which will have a
823          * minimum resolution of 6 bits:
824          * (1) 2^13*1000 > 2^22,
825          * (2) host->timeout_clk < 2^16
826          *     =>
827          *     (1) / (2) > 2^6
828          */
829         count = 0;
830         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
831         while (current_timeout < target_timeout) {
832                 count++;
833                 current_timeout <<= 1;
834                 if (count >= 0xF)
835                         break;
836         }
837
838         if (count >= 0xF) {
839                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
840                     mmc_hostname(host->mmc), count, cmd->opcode);
841                 count = 0xE;
842         }
843
844         return count;
845 }
846
847 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
848 {
849         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
850         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
851
852         if (host->flags & SDHCI_REQ_USE_DMA)
853                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
854         else
855                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
856 }
857
858 static void sdhci_determine_transfer_mode(struct sdhci_host *host,
859         unsigned int req_size, unsigned int req_blocks)
860 {
861         /* Nothing to do if DMA modes are not supported. */
862         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
863                 host->flags &= ~SDHCI_REQ_USE_DMA;
864         } else if (!host->max_pio_size || (req_size > host->max_pio_size)) {
865                 host->flags |= SDHCI_REQ_USE_DMA;
866         } else if (req_size < host->max_pio_size) {
867                 host->flags &= ~SDHCI_REQ_USE_DMA;
868                 if (host->max_pio_blocks &&
869                         (req_blocks > host->max_pio_blocks))
870                         host->flags |= SDHCI_REQ_USE_DMA;
871         }
872 }
873
874 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
875 {
876         u8 count;
877         u8 ctrl;
878         struct mmc_data *data = cmd->data;
879         int ret;
880
881         if (!MMC_CHECK_CMDQ_MODE(host))
882                 WARN_ON(host->data);
883
884         if (data || (cmd->flags & MMC_RSP_BUSY)) {
885                 count = sdhci_calc_timeout(host, cmd);
886                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
887         }
888
889         if (!data)
890                 return;
891
892         /* Sanity checks */
893         BUG_ON(data->blksz * data->blocks > 524288);
894         BUG_ON(data->blksz > host->mmc->max_blk_size);
895         BUG_ON(data->blocks > 65535);
896
897         host->data = data;
898         host->data_early = 0;
899         host->data->bytes_xfered = 0;
900
901         /* Select dma or PIO mode for transfer */
902         sdhci_determine_transfer_mode(host, data->blksz * data->blocks,
903                 data->blocks);
904
905         /*
906          * FIXME: This doesn't account for merging when mapping the
907          * scatterlist.
908          */
909         if (host->flags & SDHCI_REQ_USE_DMA) {
910                 int broken, i;
911                 struct scatterlist *sg;
912
913                 broken = 0;
914                 if (host->flags & SDHCI_USE_ADMA) {
915                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
916                                 broken = 1;
917                 } else {
918                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
919                                 broken = 1;
920                 }
921
922                 if (unlikely(broken)) {
923                         for_each_sg(data->sg, sg, data->sg_len, i) {
924                                 if (sg->length & 0x3) {
925                                         DBG("Reverting to PIO because of "
926                                                 "transfer size (%d)\n",
927                                                 sg->length);
928                                         host->flags &= ~SDHCI_REQ_USE_DMA;
929                                         break;
930                                 }
931                         }
932                 }
933         }
934
935         /*
936          * The assumption here being that alignment is the same after
937          * translation to device address space.
938          */
939         if (host->flags & SDHCI_REQ_USE_DMA) {
940                 int broken, i;
941                 struct scatterlist *sg;
942
943                 broken = 0;
944                 if (host->flags & SDHCI_USE_ADMA) {
945                         /*
946                          * As we use 3 byte chunks to work around
947                          * alignment problems, we need to check this
948                          * quirk.
949                          */
950                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
951                                 broken = 1;
952                 } else {
953                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
954                                 broken = 1;
955                 }
956
957                 if (unlikely(broken)) {
958                         for_each_sg(data->sg, sg, data->sg_len, i) {
959                                 if (sg->offset & 0x3) {
960                                         DBG("Reverting to PIO because of "
961                                                 "bad alignment\n");
962                                         host->flags &= ~SDHCI_REQ_USE_DMA;
963                                         break;
964                                 }
965                         }
966                 }
967         }
968
969         if (host->flags & SDHCI_REQ_USE_DMA) {
970                 if (host->flags & SDHCI_USE_ADMA) {
971                         ret = sdhci_adma_table_pre(host, data);
972                         if (ret) {
973                                 /*
974                                  * This only happens when someone fed
975                                  * us an invalid request.
976                                  */
977                                 WARN_ON(1);
978                                 host->flags &= ~SDHCI_REQ_USE_DMA;
979                         } else {
980                                 sdhci_writel(host,
981                                         (host->adma_addr & 0xFFFFFFFF),
982                                         SDHCI_ADMA_ADDRESS);
983
984                                 if ((host->version >= SDHCI_SPEC_400) &&
985                                     (host->quirks2 &
986                                      SDHCI_QUIRK2_SUPPORT_64BIT_DMA)) {
987                                         if (host->quirks2 &
988                                             SDHCI_QUIRK2_USE_64BIT_ADDR) {
989
990                                                 sdhci_writel(host,
991                                                 (host->adma_addr >> 32)
992                                                         & 0xFFFFFFFF,
993                                                 SDHCI_UPPER_ADMA_ADDRESS);
994                                         } else {
995                                                 sdhci_writel(host, 0,
996                                                 SDHCI_UPPER_ADMA_ADDRESS);
997                                         }
998                                 }
999                         }
1000                 } else {
1001                         int sg_cnt;
1002
1003                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
1004                                         data->sg, data->sg_len,
1005                                         (data->flags & MMC_DATA_READ) ?
1006                                                 DMA_FROM_DEVICE :
1007                                                 DMA_TO_DEVICE);
1008                         if (sg_cnt == 0) {
1009                                 /*
1010                                  * This only happens when someone fed
1011                                  * us an invalid request.
1012                                  */
1013                                 WARN_ON(1);
1014                                 host->flags &= ~SDHCI_REQ_USE_DMA;
1015                         } else {
1016                                 WARN_ON(sg_cnt != 1);
1017                                 sdhci_writel(host, sg_dma_address(data->sg),
1018                                         SDHCI_DMA_ADDRESS);
1019                         }
1020                 }
1021         }
1022
1023         /*
1024          * Always adjust the DMA selection as some controllers
1025          * (e.g. JMicron) can't do PIO properly when the selection
1026          * is ADMA.
1027          */
1028         if (host->version >= SDHCI_SPEC_200) {
1029                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1030                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
1031                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
1032                         (host->flags & SDHCI_USE_ADMA))
1033                         ctrl |= SDHCI_CTRL_ADMA2;
1034                 else
1035                         ctrl |= SDHCI_CTRL_SDMA;
1036                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1037         }
1038
1039         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1040                 int flags;
1041
1042                 flags = SG_MITER_ATOMIC;
1043                 if (host->data->flags & MMC_DATA_READ)
1044                         flags |= SG_MITER_TO_SG;
1045                 else
1046                         flags |= SG_MITER_FROM_SG;
1047                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1048                 host->blocks = data->blocks;
1049         }
1050
1051         sdhci_set_transfer_irqs(host);
1052
1053         /* Set the DMA boundary value and block size */
1054         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
1055                 data->blksz), SDHCI_BLOCK_SIZE);
1056         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1057 }
1058
1059 static void sdhci_set_transfer_mode(struct sdhci_host *host,
1060         struct mmc_command *cmd)
1061 {
1062         u16 mode;
1063         struct mmc_data *data = cmd->data;
1064
1065         if (data == NULL)
1066                 return;
1067
1068         WARN_ON(!host->data);
1069
1070         mode = SDHCI_TRNS_BLK_CNT_EN;
1071         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1072                 mode |= SDHCI_TRNS_MULTI;
1073                 /*
1074                  * If we are sending CMD23, CMD12 never gets sent
1075                  * on successful completion (so no Auto-CMD12).
1076                  */
1077                 if (!MMC_CHECK_CMDQ_MODE(host)) {
1078                         if (!host->mrq_cmd->sbc &&
1079                                 (host->flags & SDHCI_AUTO_CMD12) &&
1080                                 mmc_op_multi(cmd->opcode))
1081                                         mode |= SDHCI_TRNS_AUTO_CMD12;
1082                         else if (host->mrq_cmd->sbc &&
1083                                 (host->flags & SDHCI_AUTO_CMD23)) {
1084                                         mode |= SDHCI_TRNS_AUTO_CMD23;
1085                                         sdhci_writel(host,
1086                                                 host->mrq_cmd->sbc->arg,
1087                                                 SDHCI_ARGUMENT2);
1088                         }
1089                 }
1090         }
1091
1092         if (data->flags & MMC_DATA_READ)
1093                 mode |= SDHCI_TRNS_READ;
1094         if (host->flags & SDHCI_REQ_USE_DMA)
1095                 mode |= SDHCI_TRNS_DMA;
1096
1097         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1098 }
1099
1100 #ifdef CONFIG_DEBUG_FS
1101 static void get_kbps_from_size_n_usec_32bit(
1102                 u32 size_in_bits_x1000, u32 time_usecs,
1103                 u32 *speed_in_kbps)
1104 {
1105         *speed_in_kbps = DIV_ROUND_CLOSEST(size_in_bits_x1000, time_usecs);
1106 }
1107
1108 static void get_kbps_from_size_n_usec_64bit(
1109                 u64 size_in_bits_x1000, u64 time_usecs,
1110                 u32 *speed_in_kbps)
1111 {
1112         int i;
1113
1114         /* convert 64 bit into 32 bits */
1115         i = 0;
1116         while (!(IS_32_BIT(size_in_bits_x1000) && IS_32_BIT(time_usecs))) {
1117                 /* shift right both the operands bytes and time */
1118                 size_in_bits_x1000 >>= 1;
1119                 time_usecs >>= 1;
1120                 i++;
1121         }
1122         if (i)
1123                 pr_debug("%s right shifted operands by %d, size=%lld, time=%lld usec\n",
1124                         __func__, i, size_in_bits_x1000, time_usecs);
1125         /* check for 32 bit operations first */
1126         get_kbps_from_size_n_usec_32bit(
1127                 (u32)size_in_bits_x1000, (u32)time_usecs,
1128                 speed_in_kbps);
1129         return;
1130 }
1131
1132 static void free_stats_nodes(struct sdhci_host *host)
1133 {
1134         struct data_stat_entry *ptr, *ptr2;
1135
1136         ptr = host->sdhci_data_stat.head;
1137         while (ptr) {
1138                 ptr2 = ptr->next;
1139                 host->sdhci_data_stat.stat_size--;
1140                 devm_kfree(host->mmc->parent, ptr);
1141                 ptr = ptr2;
1142         }
1143         if (host->sdhci_data_stat.stat_size)
1144                 pr_err("stat_size=%d after free %s\n",
1145                         host->sdhci_data_stat.stat_size,
1146                         __func__);
1147         host->sdhci_data_stat.head = NULL;
1148 }
1149
1150 static struct data_stat_entry *add_entry_sorted(struct sdhci_host *host,
1151         unsigned int blk_size, unsigned int blk_count,
1152         unsigned int data_flags)
1153 {
1154         struct data_stat_entry *node, *ptr;
1155         bool is_read;
1156
1157         if (!blk_count) {
1158                 pr_err("%s %s: call blk_size=%d, blk_count=%d, data_flags=0x%x\n",
1159                         mmc_hostname(host->mmc), __func__,
1160                         blk_size, blk_count, data_flags);
1161                 goto end;
1162         }
1163
1164         node = devm_kzalloc(host->mmc->parent, sizeof(struct data_stat_entry),
1165                 GFP_KERNEL);
1166         if (!node) {
1167                 pr_err("%s, %s, line=%d %s: unable to allocate data_stat_entry\n",
1168                         __FILE__, __func__, __LINE__, mmc_hostname(host->mmc));
1169                 goto end;
1170         }
1171         node->stat_blk_size = blk_size;
1172         node->stat_blks_per_transfer = blk_count;
1173         is_read = IS_DATA_READ(data_flags);
1174         node->is_read = is_read;
1175         host->sdhci_data_stat.stat_size++;
1176         /* assume existing list is sorted and try to insert this new node
1177          * into the increasing order sorted array
1178          */
1179         ptr = host->sdhci_data_stat.head;
1180         if (!ptr) {
1181                 /* first element */
1182                 host->sdhci_data_stat.head = node;
1183                 return node;
1184         }
1185         if (ptr && ((ptr->stat_blk_size > blk_size) ||
1186                 ((ptr->stat_blk_size == blk_size) &&
1187                 (ptr->stat_blks_per_transfer > blk_count)))) {
1188                 host->sdhci_data_stat.head = node;
1189                 /* update new head */
1190                 node->next = ptr;
1191                 return node;
1192         }
1193         while (ptr->next) {
1194                 if ((ptr->next->stat_blk_size < blk_size) ||
1195                         ((ptr->next->stat_blk_size == blk_size) &&
1196                         (ptr->next->stat_blks_per_transfer < blk_count)))
1197                         ptr = ptr->next;
1198                 else
1199                         break;
1200         }
1201         /* We are here if -
1202          * 1. ptr->next is null or
1203          * 2. blk_size of ptr->next is greater than new blk size, so we should
1204          *    place the new node between ptr and ptr->next
1205          */
1206         if (!ptr->next) {
1207                 ptr->next = node;
1208                 return node;
1209         }
1210         if ((ptr->next->stat_blk_size > blk_size) ||
1211                 ((ptr->next->stat_blk_size == blk_size) &&
1212                 (ptr->next->stat_blks_per_transfer > blk_count)) ||
1213                 ((ptr->next->stat_blk_size == blk_size) &&
1214                 (ptr->next->stat_blks_per_transfer == blk_count) &&
1215                 (ptr->next->is_read != is_read))) {
1216                 node->next = ptr->next;
1217                 ptr->next = node;
1218                 return node;
1219         }
1220         pr_err("%s %s: line=%d should be unreachable ptr-next->blk_size=%d, blks_per_xfer=%d, is_read=%d, new blk_size=%d, blks_per_xfer=%d, data_flags=0x%x\n",
1221                 mmc_hostname(host->mmc), __func__, __LINE__,
1222                 ptr->next->stat_blk_size, ptr->next->stat_blks_per_transfer,
1223                 ptr->next->is_read, blk_size, blk_count, data_flags);
1224 end:
1225         return NULL;
1226 }
1227
1228 static void free_data_entry(struct sdhci_host *host,
1229                                 unsigned int blk_size, unsigned int blk_count,
1230                                 unsigned int data_flags)
1231 {
1232         struct data_stat_entry *ptr, *ptr2;
1233         bool is_read;
1234
1235         ptr = host->sdhci_data_stat.head;
1236         if (!ptr)
1237                 return;
1238         is_read = IS_DATA_READ(data_flags);
1239         if (PERF_STAT_COMPARE(ptr, blk_size, blk_count, is_read)) {
1240                 host->sdhci_data_stat.head = ptr->next;
1241                 devm_kfree(host->mmc->parent, ptr);
1242                 host->sdhci_data_stat.stat_size--;
1243                 return;
1244         }
1245         while (ptr->next) {
1246                 if (PERF_STAT_COMPARE(ptr->next, blk_size, blk_count,
1247                         is_read)) {
1248                         ptr2 = ptr->next->next;
1249                         devm_kfree(host->mmc->parent, ptr->next);
1250                         host->sdhci_data_stat.stat_size--;
1251                         ptr->next = ptr2;
1252                         return;
1253                 }
1254                 ptr = ptr->next;
1255         }
1256         pr_err("Error %s %s: given blk_size=%d not found\n",
1257                 mmc_hostname(host->mmc), __func__, blk_size);
1258         return;
1259 }
1260
1261 static void update_stat(struct sdhci_host *host, u32 blk_size, u32 blk_count,
1262                         bool is_start_stat, bool is_data_error,
1263                         unsigned int data_flags)
1264 {
1265         u32 new_kbps;
1266         struct data_stat_entry *stat;
1267         ktime_t t;
1268         bool is_read;
1269
1270         if (!host->enable_sdhci_perf_stats)
1271                 goto end;
1272
1273         if (!blk_count) {
1274                 pr_err("%s %s error stats case: blk_size=%d, blk_count=0, is_start_stat=%d, is_data_error=%d, data_flags=0x%x\n",
1275                         mmc_hostname(host->mmc), __func__, blk_size,
1276                         (int)is_start_stat, (int)is_data_error, data_flags);
1277                 goto end;
1278         }
1279         stat = host->sdhci_data_stat.head;
1280         is_read = IS_DATA_READ(data_flags);
1281         while (stat) {
1282                 if (PERF_STAT_COMPARE(stat, blk_size, blk_count, is_read))
1283                         break;
1284                 stat = stat->next;
1285         }
1286         /* allocation skipped in finish call */
1287         if (!stat) {
1288                 if (!is_start_stat)
1289                         goto end;
1290                 /* allocate an entry */
1291                 stat = add_entry_sorted(host, blk_size, blk_count, data_flags);
1292                 if (!stat) {
1293                         pr_err("%s %s line=%d: stat entry not found\n",
1294                                 mmc_hostname(host->mmc), __func__, __LINE__);
1295                         goto end;
1296                 }
1297         }
1298
1299         if (is_start_stat) {
1300                 stat->start_ktime = ktime_get();
1301         } else {
1302                 if (is_data_error) {
1303                         pr_err("%s %s error stats case: blk_size=%d, blk_count=0, is_start_stat=%d, data Error case ... data_flags=0x%x\n",
1304                                 mmc_hostname(host->mmc), __func__, blk_size,
1305                                 (int)is_start_stat, data_flags);
1306                         memset(&stat->start_ktime, 0, sizeof(ktime_t));
1307                         if (!stat->total_bytes)
1308                                 free_data_entry(host, blk_size, blk_count,
1309                                         data_flags);
1310                         goto end;
1311                 }
1312                 t = ktime_get();
1313                 stat->duration_usecs = ktime_us_delta(t, stat->start_ktime);
1314                 stat->current_transferred_bytes = (blk_size * blk_count);
1315                 get_kbps_from_size_n_usec_32bit(
1316                         (((u32)stat->current_transferred_bytes << 3) * 1000),
1317                         stat->duration_usecs,
1318                         &new_kbps);
1319                 if (stat->max_kbps == 0) {
1320                         stat->max_kbps = new_kbps;
1321                         stat->min_kbps = new_kbps;
1322                 } else {
1323                         if (new_kbps > stat->max_kbps)
1324                                 stat->max_kbps = new_kbps;
1325                         if (new_kbps < stat->min_kbps)
1326                                 stat->min_kbps = new_kbps;
1327                 }
1328                 /* update the total bytes figure for this entry */
1329                 stat->total_usecs += stat->duration_usecs;
1330                 stat->total_bytes += stat->current_transferred_bytes;
1331                 stat->total_transfers++;
1332         }
1333 end:
1334         return;
1335 }
1336 #endif
1337
1338 static void sdhci_finish_data(struct sdhci_host *host)
1339 {
1340         struct mmc_data *data;
1341
1342         BUG_ON(!host->data);
1343 #ifdef CONFIG_CMD_DUMP
1344         if (IS_EMMC_CARD(host))
1345                 dbg_add_host_log(host->mmc, 9, 9, (int)host->mrq_dat);
1346 #endif
1347
1348         data = host->data;
1349         host->data = NULL;
1350
1351         if (host->flags & SDHCI_REQ_USE_DMA) {
1352                 if (host->flags & SDHCI_USE_ADMA)
1353                         sdhci_adma_table_post(host, data);
1354                 else {
1355                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1356                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
1357                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
1358                 }
1359         }
1360
1361         /*
1362          * The specification states that the block count register must
1363          * be updated, but it does not specify at what point in the
1364          * data flow. That makes the register entirely useless to read
1365          * back so we have to assume that nothing made it to the card
1366          * in the event of an error.
1367          */
1368         if (data->error)
1369                 data->bytes_xfered = 0;
1370         else
1371                 data->bytes_xfered = data->blksz * data->blocks;
1372
1373         /*
1374          * Need to send CMD12 if -
1375          * a) open-ended multiblock transfer (no CMD23)
1376          * b) error in multiblock transfer
1377          */
1378         if (data->stop &&
1379             (data->error ||
1380              (!MMC_CHECK_CMDQ_MODE(host) && !host->mrq_dat->sbc))) {
1381
1382                 /*
1383                  * The controller needs a reset of internal state machines
1384                  * upon error conditions.
1385                  */
1386                 if (data->error) {
1387                         if (!MMC_CHECK_CMDQ_MODE(host))
1388                                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1389                         else
1390                                 sdhci_reset(host, SDHCI_RESET_DATA);
1391                 }
1392                 sdhci_send_command(host, data->stop);
1393         } else {
1394                 if (MMC_CHECK_CMDQ_MODE(host))
1395                         tasklet_schedule(&host->finish_dat_tasklet);
1396                 else
1397                         tasklet_schedule(&host->finish_tasklet);
1398         }
1399 #ifdef CONFIG_DEBUG_FS
1400         if (data->bytes_xfered) {
1401                 update_stat(host, data->blksz, data->blocks, false, false,
1402                         data->flags);
1403         } else {
1404                 host->no_data_transfer_count++;
1405                 /* performance stats does not include cases of data error */
1406                 update_stat(host, data->blksz, data->blocks, false, true,
1407                         data->flags);
1408         }
1409 #endif
1410 }
1411
1412 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1413 {
1414         int flags;
1415         u32 mask;
1416         unsigned long timeout;
1417
1418         WARN_ON(host->cmd);
1419
1420         /* Wait max 10 ms */
1421         timeout = 10;
1422
1423         if (!host->mrq_cmd && host->mrq_dat)
1424                 host->mrq_cmd = host->mrq_dat;
1425
1426         mask = SDHCI_CMD_INHIBIT;
1427         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1428                 mask |= SDHCI_DATA_INHIBIT;
1429
1430         /* We shouldn't wait for data inihibit for stop commands, even
1431            though they might use busy signaling */
1432         if (host->mrq_cmd->data && (cmd == host->mrq_cmd->data->stop))
1433                 mask &= ~SDHCI_DATA_INHIBIT;
1434
1435         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1436                 if (timeout == 0) {
1437                         pr_err("%s: Controller never released "
1438                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1439                         sdhci_dumpregs(host);
1440                         cmd->error = -EIO;
1441                         if (MMC_CHECK_CMDQ_MODE(host))
1442                                 tasklet_schedule(&host->finish_cmd_tasklet);
1443                         else
1444                                 tasklet_schedule(&host->finish_tasklet);
1445                         return;
1446                 }
1447                 timeout--;
1448                 mdelay(1);
1449         }
1450
1451         if ((cmd->opcode == MMC_SWITCH) &&
1452                 (((cmd->arg >> 16) & EXT_CSD_SANITIZE_START)
1453                 == EXT_CSD_SANITIZE_START))
1454                 timeout = 100;
1455         else
1456                 timeout = 10;
1457
1458         mod_timer(&host->timer, jiffies + timeout * HZ);
1459
1460         host->cmd = cmd;
1461
1462         sdhci_prepare_data(host, cmd);
1463
1464         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1465
1466         sdhci_set_transfer_mode(host, cmd);
1467
1468         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1469                 pr_err("%s: Unsupported response type!\n",
1470                         mmc_hostname(host->mmc));
1471                 cmd->error = -EINVAL;
1472                 if (MMC_CHECK_CMDQ_MODE(host))
1473                         tasklet_schedule(&host->finish_cmd_tasklet);
1474                 else
1475                         tasklet_schedule(&host->finish_tasklet);
1476                 return;
1477         }
1478
1479         if (!(cmd->flags & MMC_RSP_PRESENT))
1480                 flags = SDHCI_CMD_RESP_NONE;
1481         else if (cmd->flags & MMC_RSP_136)
1482                 flags = SDHCI_CMD_RESP_LONG;
1483         else if (cmd->flags & MMC_RSP_BUSY)
1484                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1485         else
1486                 flags = SDHCI_CMD_RESP_SHORT;
1487
1488         if (cmd->flags & MMC_RSP_CRC)
1489                 flags |= SDHCI_CMD_CRC;
1490         if (cmd->flags & MMC_RSP_OPCODE)
1491                 flags |= SDHCI_CMD_INDEX;
1492
1493         /* CMD19, CMD21 is special in that the Data Present Select should be set */
1494         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1495             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1496                 flags |= SDHCI_CMD_DATA;
1497
1498 #ifdef CONFIG_CMD_DUMP
1499         if (MMC_CHECK_CMDQ_MODE(host))
1500                 dbg_add_host_log(host->mmc, 0, cmd->opcode, cmd->arg);
1501 #endif
1502 #ifdef CONFIG_EMMC_BLKTRACE
1503         if (!MMC_CHECK_CMDQ_MODE(host)) {
1504                 if (cmd->opcode == MMC_SET_BLOCK_COUNT)
1505                         emmc_trace(MMC_ISSUE, host->mmc->mqrq_cur, host->mmc);
1506                 else if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK ||
1507                                 cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)
1508                         emmc_trace(MMC_ISSUE_DONE,
1509                                 host->mmc->mqrq_cur, host->mmc);
1510         } else {
1511                 if (cmd->opcode == MMC_QUEUED_TASK_ADDRESS)
1512                         emmc_trace(MMC_ISSUE,
1513                                 &host->mmc->mq->mqrq[cmd->mrq->areq->mrq->cmd->arg >> 16],
1514                                 host->mmc);
1515                 else if (cmd->opcode == MMC_EXECUTE_READ_TASK ||
1516                                 cmd->opcode == MMC_EXECUTE_WRITE_TASK)
1517                         emmc_trace(MMC_ISSUE_DONE,
1518                                 &host->mmc->mq->mqrq[cmd->arg >> 16],
1519                                 host->mmc);
1520         }
1521 #endif
1522         host->command = SDHCI_MAKE_CMD(cmd->opcode, flags);
1523         sdhci_writew(host, host->command, SDHCI_COMMAND);
1524 }
1525
1526 static void sdhci_finish_command(struct sdhci_host *host)
1527 {
1528         int i;
1529
1530         BUG_ON(host->cmd == NULL);
1531 #ifdef CONFIG_CMD_DUMP
1532         if (IS_EMMC_CARD(host))
1533                 dbg_add_host_log(host->mmc, 8, 8, (int)host->mrq_cmd);
1534 #endif
1535
1536         if (host->cmd->flags & MMC_RSP_PRESENT) {
1537                 if (host->cmd->flags & MMC_RSP_136) {
1538                         /* CRC is stripped so we need to do some shifting. */
1539                         for (i = 0; i < 4; i++) {
1540                                 host->cmd->resp[i] = sdhci_readl(host,
1541                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1542                                 if (i != 3)
1543                                         host->cmd->resp[i] |=
1544                                                 sdhci_readb(host,
1545                                                 SDHCI_RESPONSE + (3-i)*4-1);
1546                         }
1547                 } else {
1548                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1549                 }
1550         }
1551
1552         host->cmd->error = 0;
1553
1554 #ifdef CONFIG_CMD_DUMP
1555         if (MMC_CHECK_CMDQ_MODE(host))
1556                 dbg_add_host_log(host->mmc, 0,
1557                         host->cmd->opcode, host->cmd->resp[0]);
1558 #endif
1559         /* Finished CMD23, now send actual command. */
1560         if (host->cmd == host->mrq_cmd->sbc) {
1561                 host->cmd = NULL;
1562                 sdhci_send_command(host, host->mrq_cmd->cmd);
1563         } else {
1564
1565                 /* Processed actual command. */
1566                 if (host->cmd->data && host->data_early) {
1567                         host->cmd = NULL;
1568                         host->mrq_dat = host->mrq_cmd;
1569                         host->mrq_cmd = NULL;
1570                         sdhci_finish_data(host);
1571                 }
1572
1573                 if (!MMC_CHECK_CMDQ_MODE(host)) {
1574                         if (!host->cmd->data)
1575
1576                                 tasklet_schedule(&host->finish_tasklet);
1577                         else {
1578                                 host->mrq_dat = host->mrq_cmd;
1579                                 host->mrq_cmd = NULL;
1580                         }
1581
1582                         host->cmd = NULL;
1583                 } else if (!host->data_early) {
1584                         if (!host->mrq_cmd->cmd->error &&
1585                         !host->cmd->error && host->cmd->data) {
1586                                 host->cmd = NULL;
1587                                 host->mrq_dat = host->mrq_cmd;
1588                                 host->mrq_cmd = NULL;
1589                         }
1590                         tasklet_schedule(&host->finish_cmd_tasklet);
1591                 }
1592         }
1593 }
1594
1595 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1596 {
1597         u16 ctrl, preset = 0;
1598
1599         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1600
1601         switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1602         case SDHCI_CTRL_UHS_SDR12:
1603                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1604                 break;
1605         case SDHCI_CTRL_UHS_SDR25:
1606                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1607                 break;
1608         case SDHCI_CTRL_UHS_SDR50:
1609                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1610                 break;
1611         case SDHCI_CTRL_UHS_SDR104:
1612                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1613                 break;
1614         case SDHCI_CTRL_UHS_DDR50:
1615                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1616                 break;
1617         default:
1618                 pr_warn("%s: Invalid UHS-I mode selected\n",
1619                         mmc_hostname(host->mmc));
1620                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1621                 break;
1622         }
1623         return preset;
1624 }
1625
1626 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1627 {
1628         int div = 0; /* Initialized for compiler warning */
1629         int real_div = div, clk_mul = 1;
1630         u16 clk = 0;
1631         unsigned long timeout;
1632         u32 caps;
1633
1634         if (clock && clock == host->clock)
1635                 return;
1636
1637         host->mmc->actual_clock = 0;
1638
1639         if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1640                 return;
1641
1642         /*
1643          * If the entire clock control register is updated with zero, some
1644          * controllers might first update clock divisor fields and then update
1645          * the INT_CLK_EN and CARD_CLK_EN fields. Disable card clock first
1646          * to ensure there is no abnormal clock behavior.
1647          */
1648         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1649         clk &= ~SDHCI_CLOCK_CARD_EN;
1650         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1651         clk = 0;
1652         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1653
1654         if (clock == 0)
1655                 goto out;
1656
1657         if (host->version >= SDHCI_SPEC_300) {
1658                 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1659                         SDHCI_CTRL_PRESET_VAL_ENABLE) {
1660                         u16 pre_val;
1661
1662                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1663                         pre_val = sdhci_get_preset_value(host);
1664                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1665                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1666                         if (host->clk_mul &&
1667                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1668                                 clk = SDHCI_PROG_CLOCK_MODE;
1669                                 real_div = div + 1;
1670                                 clk_mul = host->clk_mul;
1671                         } else {
1672                                 real_div = max_t(int, 1, div << 1);
1673                         }
1674                         goto clock_set;
1675                 }
1676
1677                 /*
1678                  * Check if the Host Controller supports Programmable Clock
1679                  * Mode.
1680                  */
1681                 if (host->clk_mul) {
1682                         for (div = 1; div <= 1024; div++) {
1683                                 if ((host->max_clk * host->clk_mul / div)
1684                                         <= clock)
1685                                         break;
1686                         }
1687                         /*
1688                          * Set Programmable Clock Mode in the Clock
1689                          * Control register.
1690                          */
1691                         clk = SDHCI_PROG_CLOCK_MODE;
1692                         real_div = div;
1693                         clk_mul = host->clk_mul;
1694                         div--;
1695                 } else {
1696                         /* Version 3.00 divisors must be a multiple of 2. */
1697                         if (host->max_clk <= clock) {
1698                                 if (host->mmc->ios.timing ==
1699                                         MMC_TIMING_UHS_DDR50)
1700                                         div = 2;
1701                                 else
1702                                         div = 1;
1703                         } else {
1704                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1705                                      div += 2) {
1706                                         if ((host->max_clk / div) <= clock)
1707                                                 break;
1708                                 }
1709                         }
1710                         real_div = div;
1711                         div >>= 1;
1712                 }
1713         } else {
1714                 /* Version 2.00 divisors must be a power of 2. */
1715                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1716                         if ((host->max_clk / div) <= clock)
1717                                 break;
1718                 }
1719                 real_div = div;
1720                 div >>= 1;
1721         }
1722
1723 clock_set:
1724         if (real_div)
1725                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1726
1727         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1728         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1729                 << SDHCI_DIVIDER_HI_SHIFT;
1730         clk |= SDHCI_CLOCK_INT_EN;
1731         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1732
1733         /*
1734          * For Tegra3 sdmmc controller, internal clock will not be stable bit
1735          * will get set only after some other register write is done. To
1736          * handle, do a dummy reg write to the caps reg if
1737          * SDHCI_QUIRK2_INT_CLK_STABLE_REQ_DUMMY_REG_WRITE is set.
1738          */
1739         if (host->quirks2 & SDHCI_QUIRK2_INT_CLK_STABLE_REQ_DUMMY_REG_WRITE) {
1740                 udelay(5);
1741
1742                 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
1743                 caps |= 1;
1744                 sdhci_writel(host, caps, SDHCI_CAPABILITIES);
1745         }
1746
1747         /* Wait max 20 ms */
1748         timeout = 20;
1749         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1750                 & SDHCI_CLOCK_INT_STABLE)) {
1751                 if (timeout == 0) {
1752                         pr_err("%s: Internal clock never "
1753                                 "stabilised.\n", mmc_hostname(host->mmc));
1754                         sdhci_dumpregs(host);
1755                         return;
1756                 }
1757                 timeout--;
1758                 mdelay(1);
1759         }
1760
1761         clk |= SDHCI_CLOCK_CARD_EN;
1762         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1763
1764 out:
1765         host->clock = clock;
1766 }
1767
1768 static inline void sdhci_update_clock(struct sdhci_host *host)
1769 {
1770         unsigned int clock;
1771
1772         clock = host->clock;
1773         host->clock = 0;
1774         if (host->ops->set_clock)
1775                 host->ops->set_clock(host, clock);
1776         sdhci_set_clock(host, clock);
1777 }
1778
1779 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1780 {
1781         u8 pwr = 0;
1782
1783         if (power != (unsigned short)-1) {
1784                 switch (1 << power) {
1785                 case MMC_VDD_165_195:
1786                         pwr = SDHCI_POWER_180;
1787                         break;
1788                 case MMC_VDD_29_30:
1789                 case MMC_VDD_30_31:
1790                         pwr = SDHCI_POWER_300;
1791                         break;
1792                 case MMC_VDD_32_33:
1793                 case MMC_VDD_33_34:
1794                         pwr = SDHCI_POWER_330;
1795                         break;
1796                 default:
1797                         BUG();
1798                 }
1799         }
1800
1801         if (host->pwr == pwr)
1802                 return -1;
1803
1804         host->pwr = pwr;
1805
1806         if (pwr == 0) {
1807                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1808                 return 0;
1809         }
1810
1811         /*
1812          * Spec says that we should clear the power reg before setting
1813          * a new value. Some controllers don't seem to like this though.
1814          */
1815         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1816                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1817
1818         /*
1819          * At least the Marvell CaFe chip gets confused if we set the voltage
1820          * and set turn on power at the same time, so set the voltage first.
1821          */
1822         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1823                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1824
1825         pwr |= SDHCI_POWER_ON;
1826
1827         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1828
1829         /*
1830          * Some controllers need an extra 10ms delay of 10ms before they
1831          * can apply clock after applying power
1832          */
1833         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1834                 mdelay(10);
1835
1836         return power;
1837 }
1838
1839 static void sdhci_en_strobe(struct mmc_host *mmc)
1840 {
1841         struct sdhci_host *host;
1842
1843         host = mmc_priv(mmc);
1844
1845         sdhci_runtime_pm_get(host);
1846         if (host->ops->en_strobe)
1847                 host->ops->en_strobe(host);
1848         sdhci_runtime_pm_put(host);
1849 }
1850 /* Execute DLL calibration once for MMC device if it is
1851  * enumerated in HS400 mode at 200MHz clock freq before
1852  * starting any data transfer.
1853  */
1854 static void sdhci_post_init(struct mmc_host *mmc)
1855 {
1856         struct sdhci_host *host;
1857
1858         host = mmc_priv(mmc);
1859
1860         sdhci_runtime_pm_get(host);
1861         if (host->ops->post_init)
1862                 host->ops->post_init(host);
1863         sdhci_runtime_pm_put(host);
1864 }
1865 /*****************************************************************************\
1866  *                                                                           *
1867  * MMC callbacks                                                             *
1868  *                                                                           *
1869 \*****************************************************************************/
1870
1871 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1872 {
1873         struct sdhci_host *host;
1874         int present;
1875         unsigned long flags;
1876         u32 tuning_opcode;
1877
1878         host = mmc_priv(mmc);
1879
1880 #ifdef CONFIG_DEBUG_FS
1881         if (mrq->data && mrq->data->blocks)
1882                 update_stat(host, mrq->data->blksz, mrq->data->blocks,
1883                         true, false, mrq->data->flags);
1884 #endif
1885
1886         sdhci_runtime_pm_get(host);
1887
1888         present = mmc_gpio_get_cd(host->mmc);
1889
1890         spin_lock_irqsave(&host->lock, flags);
1891
1892         WARN_ON(host->mrq_cmd != NULL);
1893
1894 #ifndef SDHCI_USE_LEDS_CLASS
1895         sdhci_activate_led(host);
1896 #endif
1897
1898         /*
1899          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1900          * requests if Auto-CMD12 is enabled.
1901          */
1902         if (!MMC_CHECK_CMDQ_MODE(host) && !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1903                 if (mrq->stop) {
1904                         mrq->data->stop = NULL;
1905                         mrq->stop = NULL;
1906                 }
1907         }
1908
1909         host->mrq_cmd = mrq;
1910         host->mrq_cmd->data_early = 0;
1911
1912         /*
1913          * Firstly check card presence from cd-gpio.  The return could
1914          * be one of the following possibilities:
1915          *     negative: cd-gpio is not available
1916          *     zero: cd-gpio is used, and card is removed
1917          *     one: cd-gpio is used, and card is present
1918          */
1919         if (present < 0) {
1920                 /* If polling, assume that the card is always present. */
1921                 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1922                         if (host->ops->get_cd)
1923                                 present = host->ops->get_cd(host);
1924                         else
1925                                 present = 1;
1926                 else
1927                         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1928                                         SDHCI_CARD_PRESENT;
1929         }
1930
1931         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1932                 host->mrq_cmd->cmd->error = -ENOMEDIUM;
1933                 if (MMC_CHECK_CMDQ_MODE(host))
1934                         tasklet_schedule(&host->finish_cmd_tasklet);
1935                 else
1936                         tasklet_schedule(&host->finish_tasklet);
1937         } else {
1938                 u32 present_state;
1939
1940                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1941                 /*
1942                  * Check if the re-tuning timer has already expired and there
1943                  * is no on-going data transfer. If so, we need to execute
1944                  * tuning procedure before sending command.
1945                  */
1946                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1947                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1948                         if (!mmc->need_tuning || !mmc->ready_tuning) {
1949                                 if (!mmc->need_tuning)
1950                                         mmc->need_tuning = 1;
1951                                 goto end_tuning;
1952                         }
1953
1954                         if (mmc->card) {
1955                                 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1956                                 tuning_opcode =
1957                                         mmc->card->type == MMC_TYPE_MMC ?
1958                                         MMC_SEND_TUNING_BLOCK_HS200 :
1959                                         MMC_SEND_TUNING_BLOCK;
1960                                 host->mrq_cmd = NULL;
1961                                 spin_unlock_irqrestore(&host->lock, flags);
1962                                 sdhci_execute_tuning(mmc, tuning_opcode);
1963                                 mmc->need_tuning = 0;
1964                                 mmc->ready_tuning = 0;
1965                                 spin_lock_irqsave(&host->lock, flags);
1966
1967 end_tuning:
1968                                 /* Restore original mmc_request structure */
1969                                 host->mrq_cmd = mrq;
1970                         }
1971                 }
1972
1973                 /* For a data cmd, check for plat specific preparation */
1974                 spin_unlock_irqrestore(&host->lock, flags);
1975                 if (mrq->data)
1976                         host->ops->platform_get_bus(host);
1977                 spin_lock_irqsave(&host->lock, flags);
1978
1979                 if (!MMC_CHECK_CMDQ_MODE(host) &&
1980                         (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)))
1981                                 sdhci_send_command(host, mrq->sbc);
1982                 else if (MMC_CHECK_CMDQ_MODE(host) && mrq->sbc)
1983                         sdhci_send_command(host, mrq->sbc);
1984                 else {
1985                         sdhci_send_command(host, mrq->cmd);
1986                 }
1987         }
1988
1989         mmiowb();
1990         spin_unlock_irqrestore(&host->lock, flags);
1991 }
1992
1993 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1994 {
1995         unsigned long flags;
1996         int vdd_bit = -1;
1997         u8 ctrl;
1998
1999         /* cancel delayed clk gate work */
2000         if (host->quirks2 & SDHCI_QUIRK2_DELAYED_CLK_GATE)
2001                 cancel_delayed_work_sync(&host->delayed_clk_gate_wrk);
2002
2003         /* Do any required preparations prior to setting ios */
2004         if (host->ops->platform_ios_config_enter)
2005                 host->ops->platform_ios_config_enter(host, ios);
2006
2007         spin_lock_irqsave(&host->lock, flags);
2008
2009         if (host->flags & SDHCI_DEVICE_DEAD) {
2010                 spin_unlock_irqrestore(&host->lock, flags);
2011                 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
2012                         mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
2013                 return;
2014         }
2015
2016         /*
2017          * Reset the chip on each power off.
2018          * Should clear out any weird states.
2019          */
2020         if (ios->power_mode == MMC_POWER_OFF) {
2021                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2022                 sdhci_reinit(host);
2023         }
2024
2025         if (host->version >= SDHCI_SPEC_300 &&
2026                 (ios->power_mode == MMC_POWER_UP))
2027                 sdhci_enable_preset_value(host, false);
2028
2029         if (ios->power_mode == MMC_POWER_OFF)
2030                 vdd_bit = sdhci_set_power(host, -1);
2031         else
2032                 vdd_bit = sdhci_set_power(host, ios->vdd);
2033
2034         if (host->vmmc && vdd_bit != -1) {
2035                 spin_unlock_irqrestore(&host->lock, flags);
2036                 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
2037                 spin_lock_irqsave(&host->lock, flags);
2038         }
2039
2040         sdhci_set_clock(host, ios->clock);
2041
2042         if (host->ops->platform_send_init_74_clocks)
2043                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2044
2045         /*
2046          * If your platform has 8-bit width support but is not a v3 controller,
2047          * or if it requires special setup code, you should implement that in
2048          * platform_bus_width().
2049          */
2050         if (host->ops->platform_bus_width) {
2051                 host->ops->platform_bus_width(host, ios->bus_width);
2052         } else {
2053                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2054                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
2055                         ctrl &= ~SDHCI_CTRL_4BITBUS;
2056                         if (host->version >= SDHCI_SPEC_300)
2057                                 ctrl |= SDHCI_CTRL_8BITBUS;
2058                 } else {
2059                         if (host->version >= SDHCI_SPEC_300)
2060                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
2061                         if (ios->bus_width == MMC_BUS_WIDTH_4)
2062                                 ctrl |= SDHCI_CTRL_4BITBUS;
2063                         else
2064                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
2065                 }
2066                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2067         }
2068
2069         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2070
2071         if ((ios->timing == MMC_TIMING_SD_HS ||
2072              ios->timing == MMC_TIMING_MMC_HS)
2073             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
2074                 ctrl |= SDHCI_CTRL_HISPD;
2075         else
2076                 ctrl &= ~SDHCI_CTRL_HISPD;
2077
2078         if (host->version >= SDHCI_SPEC_300) {
2079                 u16 clk, ctrl_2;
2080
2081                 /* In case of UHS-I modes, set High Speed Enable */
2082                 if (((ios->timing == MMC_TIMING_MMC_HS200) ||
2083                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
2084                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
2085                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
2086                     (ios->timing == MMC_TIMING_UHS_SDR25))
2087                     && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
2088                         ctrl |= SDHCI_CTRL_HISPD;
2089
2090                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2091                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2092                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2093                         /*
2094                          * We only need to set Driver Strength if the
2095                          * preset value enable is not set.
2096                          */
2097                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
2098                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
2099                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
2100                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
2101                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
2102
2103                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2104                 } else {
2105                         /*
2106                          * According to SDHC Spec v3.00, if the Preset Value
2107                          * Enable in the Host Control 2 register is set, we
2108                          * need to reset SD Clock Enable before changing High
2109                          * Speed Enable to avoid generating clock gliches.
2110                          */
2111
2112                         /* Reset SD Clock Enable */
2113                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2114                         clk &= ~SDHCI_CLOCK_CARD_EN;
2115                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2116
2117                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2118
2119                         /* Re-enable SD Clock */
2120                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2121                         clk |= SDHCI_CLOCK_CARD_EN;
2122                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2123                 }
2124
2125
2126                 /* Reset SD Clock Enable */
2127                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2128                 clk &= ~SDHCI_CLOCK_CARD_EN;
2129                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2130
2131                 if (host->ops->set_uhs_signaling)
2132                         host->ops->set_uhs_signaling(host, ios->timing);
2133                 else {
2134                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2135                         /* Select Bus Speed Mode for host */
2136                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
2137                         if (ios->timing == MMC_TIMING_MMC_HS200)
2138                                 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
2139                         else if (ios->timing == MMC_TIMING_UHS_SDR12)
2140                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
2141                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
2142                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
2143                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
2144                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
2145                         else if (ios->timing == MMC_TIMING_UHS_SDR104)
2146                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
2147                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
2148                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
2149                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2150                 }
2151
2152                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2153                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
2154                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
2155                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
2156                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
2157                                  (ios->timing == MMC_TIMING_UHS_DDR50))) {
2158                         u16 preset;
2159
2160                         sdhci_enable_preset_value(host, true);
2161                         preset = sdhci_get_preset_value(host);
2162                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
2163                                 >> SDHCI_PRESET_DRV_SHIFT;
2164                 }
2165
2166                 /* Re-enable SD Clock */
2167                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2168                 clk |= SDHCI_CLOCK_CARD_EN;
2169                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2170         } else
2171                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2172
2173         /*
2174          * Some (ENE) controllers go apeshit on some ios operation,
2175          * signalling timeout and CRC errors even on CMD0. Resetting
2176          * it on each ios seems to solve the problem.
2177          */
2178         if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
2179                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2180
2181         mmiowb();
2182         spin_unlock_irqrestore(&host->lock, flags);
2183
2184         /* Platform specific handling post ios setting */
2185         if (host->ops->platform_ios_config_exit)
2186                 host->ops->platform_ios_config_exit(host, ios);
2187
2188 }
2189
2190 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2191 {
2192         struct sdhci_host *host = mmc_priv(mmc);
2193
2194         sdhci_runtime_pm_get(host);
2195         sdhci_do_set_ios(host, ios);
2196         sdhci_runtime_pm_put(host);
2197 }
2198
2199 static int sdhci_do_get_cd(struct sdhci_host *host)
2200 {
2201         int gpio_cd = mmc_gpio_get_cd(host->mmc);
2202
2203         if (host->flags & SDHCI_DEVICE_DEAD)
2204                 return 0;
2205
2206         /* If polling/nonremovable, assume that the card is always present. */
2207         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
2208             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
2209                 return 1;
2210
2211         /* Try slot gpio detect */
2212         if (!IS_ERR_VALUE(gpio_cd))
2213                 return !!gpio_cd;
2214
2215         /* Host native card detect */
2216         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2217 }
2218
2219 static int sdhci_get_cd(struct mmc_host *mmc)
2220 {
2221         struct sdhci_host *host = mmc_priv(mmc);
2222         int ret;
2223
2224         sdhci_runtime_pm_get(host);
2225         ret = sdhci_do_get_cd(host);
2226         sdhci_runtime_pm_put(host);
2227         return ret;
2228 }
2229
2230 static int sdhci_check_ro(struct sdhci_host *host)
2231 {
2232         unsigned long flags;
2233         int is_readonly;
2234
2235         spin_lock_irqsave(&host->lock, flags);
2236
2237         if (host->flags & SDHCI_DEVICE_DEAD)
2238                 is_readonly = 0;
2239         else if (host->ops->get_ro)
2240                 is_readonly = host->ops->get_ro(host);
2241         else
2242                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2243                                 & SDHCI_WRITE_PROTECT);
2244
2245         spin_unlock_irqrestore(&host->lock, flags);
2246
2247         /* This quirk needs to be replaced by a callback-function later */
2248         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2249                 !is_readonly : is_readonly;
2250 }
2251
2252 #define SAMPLE_COUNT    5
2253
2254 static int sdhci_do_get_ro(struct sdhci_host *host)
2255 {
2256         int i, ro_count;
2257
2258         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
2259                 return sdhci_check_ro(host);
2260
2261         ro_count = 0;
2262         for (i = 0; i < SAMPLE_COUNT; i++) {
2263                 if (sdhci_check_ro(host)) {
2264                         if (++ro_count > SAMPLE_COUNT / 2)
2265                                 return 1;
2266                 }
2267                 msleep(30);
2268         }
2269         return 0;
2270 }
2271
2272 static void sdhci_hw_reset(struct mmc_host *mmc)
2273 {
2274         struct sdhci_host *host = mmc_priv(mmc);
2275
2276         if (host->ops && host->ops->hw_reset)
2277                 host->ops->hw_reset(host);
2278 }
2279
2280 static int sdhci_get_ro(struct mmc_host *mmc)
2281 {
2282         struct sdhci_host *host = mmc_priv(mmc);
2283         int ret;
2284
2285         sdhci_runtime_pm_get(host);
2286         ret = sdhci_do_get_ro(host);
2287         sdhci_runtime_pm_put(host);
2288         return ret;
2289 }
2290
2291 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2292 {
2293         if (host->flags & SDHCI_DEVICE_DEAD)
2294                 goto out;
2295
2296         if (enable)
2297                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
2298         else
2299                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
2300
2301         /* SDIO IRQ will be enabled as appropriate in runtime resume */
2302         if (host->runtime_suspended)
2303                 goto out;
2304
2305         if (enable)
2306                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
2307         else
2308                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
2309 out:
2310         mmiowb();
2311 }
2312
2313 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
2314 {
2315         struct sdhci_host *host = mmc_priv(mmc);
2316         unsigned long flags;
2317
2318         spin_lock_irqsave(&host->lock, flags);
2319         sdhci_enable_sdio_irq_nolock(host, enable);
2320         spin_unlock_irqrestore(&host->lock, flags);
2321 }
2322
2323 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
2324                                                 struct mmc_ios *ios)
2325 {
2326         u16 ctrl;
2327         int ret;
2328
2329         /*
2330          * Signal Voltage Switching is only applicable for Host Controllers
2331          * v3.00 and above.
2332          */
2333         if (host->version < SDHCI_SPEC_300)
2334                 return 0;
2335
2336         if (host->quirks2 & SDHCI_QUIRK2_NON_STD_VOLTAGE_SWITCHING) {
2337                 if (host->ops->switch_signal_voltage)
2338                         return host->ops->switch_signal_voltage(
2339                                 host, ios->signal_voltage);
2340         }
2341
2342         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2343
2344         switch (ios->signal_voltage) {
2345         case MMC_SIGNAL_VOLTAGE_330:
2346                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2347                 ctrl &= ~SDHCI_CTRL_VDD_180;
2348                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2349
2350                 if (host->vqmmc) {
2351                         ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
2352                         if (ret) {
2353                                 pr_warning("%s: Switching to 3.3V signalling voltage "
2354                                                 " failed\n", mmc_hostname(host->mmc));
2355                                 return -EIO;
2356                         }
2357                 }
2358                 /* Wait for 5ms */
2359                 usleep_range(5000, 5500);
2360
2361                 /* 3.3V regulator output should be stable within 5 ms */
2362                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2363                 if (!(ctrl & SDHCI_CTRL_VDD_180))
2364                         return 0;
2365
2366                 pr_warning("%s: 3.3V regulator output did not became stable\n",
2367                                 mmc_hostname(host->mmc));
2368
2369                 return -EAGAIN;
2370         case MMC_SIGNAL_VOLTAGE_180:
2371                 if (host->vqmmc) {
2372                         ret = regulator_set_voltage(host->vqmmc,
2373                                         1700000, 1950000);
2374                         if (ret) {
2375                                 pr_warning("%s: Switching to 1.8V signalling voltage "
2376                                                 " failed\n", mmc_hostname(host->mmc));
2377                                 return -EIO;
2378                         }
2379                 }
2380
2381                 /*
2382                  * Enable 1.8V Signal Enable in the Host Control2
2383                  * register
2384                  */
2385                 ctrl |= SDHCI_CTRL_VDD_180;
2386                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2387
2388                 /* Wait for 5ms */
2389                 usleep_range(5000, 5500);
2390
2391                 /* 1.8V regulator output should be stable within 5 ms */
2392                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2393                 if (ctrl & SDHCI_CTRL_VDD_180)
2394                         return 0;
2395
2396                 pr_warning("%s: 1.8V regulator output did not became stable\n",
2397                                 mmc_hostname(host->mmc));
2398
2399                 return -EAGAIN;
2400         case MMC_SIGNAL_VOLTAGE_120:
2401                 if (host->vqmmc) {
2402                         ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
2403                         if (ret) {
2404                                 pr_warning("%s: Switching to 1.2V signalling voltage "
2405                                                 " failed\n", mmc_hostname(host->mmc));
2406                                 return -EIO;
2407                         }
2408                 }
2409                 return 0;
2410         default:
2411                 /* No signal voltage switch required */
2412                 return 0;
2413         }
2414 }
2415
2416 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2417         struct mmc_ios *ios)
2418 {
2419         struct sdhci_host *host = mmc_priv(mmc);
2420         int err;
2421
2422         if (host->version < SDHCI_SPEC_300)
2423                 return 0;
2424         sdhci_runtime_pm_get(host);
2425         err = sdhci_do_start_signal_voltage_switch(host, ios);
2426         /* Do any post voltage switch platform specific configuration */
2427         if  (host->ops->switch_signal_voltage_exit)
2428                 host->ops->switch_signal_voltage_exit(host,
2429                         ios->signal_voltage);
2430         sdhci_runtime_pm_put(host);
2431         return err;
2432 }
2433
2434 static int sdhci_card_busy(struct mmc_host *mmc)
2435 {
2436         struct sdhci_host *host = mmc_priv(mmc);
2437         u32 present_state;
2438
2439         sdhci_runtime_pm_get(host);
2440         /* Check whether DAT[3:0] is 0000 */
2441         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2442         sdhci_runtime_pm_put(host);
2443
2444         return !(present_state & SDHCI_DATA_LVL_MASK);
2445 }
2446
2447 static void sdhci_config_tap(struct mmc_host *mmc, u8 option)
2448 {
2449         struct sdhci_host *host = mmc_priv(mmc);
2450
2451         if (host->ops->config_tap_delay)
2452                 host->ops->config_tap_delay(host, option);
2453 }
2454
2455 static int sdhci_validate_sd2_0(struct mmc_host *mmc)
2456 {
2457         struct sdhci_host *host;
2458         int err = 0;
2459
2460         host = mmc_priv(mmc);
2461
2462         if (host->ops->validate_sd2_0)
2463                 err = host->ops->validate_sd2_0(host);
2464         return err;
2465 }
2466
2467 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2468 {
2469         struct sdhci_host *host;
2470         u16 ctrl;
2471         u32 ier;
2472         int tuning_loop_counter = MAX_TUNING_LOOP;
2473         unsigned long timeout;
2474         int err = 0;
2475         bool requires_tuning_nonuhs = false;
2476         u16 clk = 0;
2477
2478         host = mmc_priv(mmc);
2479
2480         sdhci_runtime_pm_get(host);
2481         disable_irq(host->irq);
2482
2483         if ((host->quirks2 & SDHCI_QUIRK2_NON_STANDARD_TUNING) &&
2484                 host->ops->execute_freq_tuning) {
2485                 err = host->ops->execute_freq_tuning(host, opcode);
2486                 enable_irq(host->irq);
2487                 sdhci_runtime_pm_put(host);
2488                 return err;
2489         }
2490
2491         if ((host->quirks2 & SDHCI_QUIRK2_NON_STD_TUNING_LOOP_CNTR) &&
2492                 (host->ops->get_max_tuning_loop_counter))
2493                 tuning_loop_counter =
2494                         host->ops->get_max_tuning_loop_counter(host);
2495
2496         spin_lock(&host->lock);
2497         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2498
2499         /*
2500          * The Host Controller needs tuning only in case of SDR104 mode
2501          * and for SDR50 mode when Use Tuning for SDR50 is set in the
2502          * Capabilities register.
2503          * If the Host Controller supports the HS200 mode then the
2504          * tuning function has to be executed.
2505          */
2506         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
2507             (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
2508              host->flags & SDHCI_HS200_NEEDS_TUNING))
2509                 requires_tuning_nonuhs = true;
2510
2511         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
2512             requires_tuning_nonuhs)
2513                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2514         else {
2515                 spin_unlock(&host->lock);
2516                 enable_irq(host->irq);
2517                 sdhci_runtime_pm_put(host);
2518                 return 0;
2519         }
2520
2521         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2522
2523         /*
2524          * As per the Host Controller spec v3.00, tuning command
2525          * generates Buffer Read Ready interrupt, so enable that.
2526          *
2527          * Note: The spec clearly says that when tuning sequence
2528          * is being performed, the controller does not generate
2529          * interrupts other than Buffer Read Ready interrupt. But
2530          * to make sure we don't hit a controller bug, we _only_
2531          * enable Buffer Read Ready interrupt here.
2532          */
2533         ier = host->ier;
2534         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
2535
2536         /*
2537          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
2538          * of loops reaches 40 times or a timeout of 150ms occurs.
2539          */
2540         timeout = 150;
2541         do {
2542                 struct mmc_command cmd = {0};
2543                 struct mmc_request mrq = {NULL};
2544
2545                 if (!tuning_loop_counter && !timeout)
2546                         break;
2547
2548                 cmd.opcode = opcode;
2549                 cmd.arg = 0;
2550                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2551                 cmd.retries = 0;
2552                 cmd.data = NULL;
2553                 cmd.error = 0;
2554
2555                 mrq.cmd = &cmd;
2556                 host->mrq_cmd = &mrq;
2557
2558                 if (host->quirks2 & SDHCI_QUIRK2_NON_STD_TUN_CARD_CLOCK) {
2559                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2560                         clk &= ~SDHCI_CLOCK_CARD_EN;
2561                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2562                 }
2563
2564                 /*
2565                  * In response to CMD19, the card sends 64 bytes of tuning
2566                  * block to the Host Controller. So we set the block size
2567                  * to 64 here.
2568                  * In response to CMD21, the card sends 128 bytes of tuning
2569                  * block for MMC_BUS_WIDTH_8 and 64 bytes for MMC_BUS_WIDTH_4
2570                  * to the Host Controller. So we set the block size to 64 here.
2571                  */
2572                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2573                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2574                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2575                                              SDHCI_BLOCK_SIZE);
2576                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2577                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2578                                              SDHCI_BLOCK_SIZE);
2579                 } else {
2580                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2581                                      SDHCI_BLOCK_SIZE);
2582                 }
2583
2584                 /*
2585                  * The tuning block is sent by the card to the host controller.
2586                  * So we set the TRNS_READ bit in the Transfer Mode register.
2587                  * This also takes care of setting DMA Enable and Multi Block
2588                  * Select in the same register to 0.
2589                  */
2590                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2591
2592                 sdhci_send_command(host, &cmd);
2593
2594                 host->cmd = NULL;
2595                 host->mrq_cmd = NULL;
2596
2597                 spin_unlock(&host->lock);
2598                 enable_irq(host->irq);
2599
2600                 if (host->quirks2 & SDHCI_QUIRK2_NON_STD_TUN_CARD_CLOCK) {
2601                         udelay(1);
2602                         sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2603                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2604                         clk |= SDHCI_CLOCK_CARD_EN;
2605                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2606                 }
2607
2608                 /* Wait for Buffer Read Ready interrupt */
2609                 wait_event_interruptible_timeout(host->buf_ready_int,
2610                                         (host->tuning_done == 1),
2611                                         msecs_to_jiffies(50));
2612                 disable_irq(host->irq);
2613                 spin_lock(&host->lock);
2614
2615                 if (!host->tuning_done) {
2616                         pr_info(DRIVER_NAME ": Timeout waiting for "
2617                                 "Buffer Read Ready interrupt during tuning "
2618                                 "procedure, falling back to fixed sampling "
2619                                 "clock\n");
2620                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2621                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2622                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2623                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2624
2625                         err = -EIO;
2626                         goto out;
2627                 }
2628
2629                 host->tuning_done = 0;
2630
2631                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2632                 tuning_loop_counter--;
2633                 timeout--;
2634                 mdelay(1);
2635         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2636
2637         /*
2638          * The Host Driver has exhausted the maximum number of loops allowed,
2639          * so use fixed sampling frequency.
2640          */
2641         if (!tuning_loop_counter || !timeout) {
2642                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2643                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2644         } else {
2645                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2646                         pr_info(DRIVER_NAME ": Tuning procedure"
2647                                 " failed, falling back to fixed sampling"
2648                                 " clock\n");
2649                         err = -EIO;
2650                 } else {
2651                         sdhci_config_tap(mmc, SAVE_TUNED_TAP);
2652                         pr_info("%s: tap value and tuning window after hw tuning completion ...\n",
2653                                 mmc_hostname(mmc));
2654                         /* log tap, trim and tuning windows */
2655                         if (host->ops->dump_host_cust_regs)
2656                                 host->ops->dump_host_cust_regs(host);
2657                 }
2658         }
2659
2660 out:
2661         /*
2662          * If this is the very first time we are here, we start the retuning
2663          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2664          * flag won't be set, we check this condition before actually starting
2665          * the timer.
2666          */
2667         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2668             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
2669                 host->flags |= SDHCI_USING_RETUNING_TIMER;
2670                 mod_timer(&host->tuning_timer, jiffies +
2671                         host->tuning_count * HZ);
2672                 /* Tuning mode 1 limits the maximum data length to 4MB */
2673                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2674         } else {
2675                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2676                 /* Reload the new initial value for timer */
2677                 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2678                         mod_timer(&host->tuning_timer, jiffies +
2679                                 host->tuning_count * HZ);
2680         }
2681
2682         /*
2683          * In case tuning fails, host controllers which support re-tuning can
2684          * try tuning again at a later time, when the re-tuning timer expires.
2685          * So for these controllers, we return 0. Since there might be other
2686          * controllers who do not have this capability, we return error for
2687          * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2688          * a retuning timer to do the retuning for the card.
2689          */
2690         if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2691                 err = 0;
2692
2693         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
2694         spin_unlock(&host->lock);
2695         enable_irq(host->irq);
2696         sdhci_runtime_pm_put(host);
2697
2698         return err;
2699 }
2700
2701
2702 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2703 {
2704         u16 ctrl;
2705
2706         /* Host Controller v3.00 defines preset value registers */
2707         if (host->version < SDHCI_SPEC_300)
2708                 return;
2709
2710         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2711
2712         /*
2713          * We only enable or disable Preset Value if they are not already
2714          * enabled or disabled respectively. Otherwise, we bail out.
2715          */
2716         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2717                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2718                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2719                 host->flags |= SDHCI_PV_ENABLED;
2720         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2721                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2722                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2723                 host->flags &= ~SDHCI_PV_ENABLED;
2724         }
2725 }
2726
2727 static void sdhci_card_event(struct mmc_host *mmc)
2728 {
2729         struct sdhci_host *host = mmc_priv(mmc);
2730         unsigned long flags;
2731
2732         sdhci_runtime_pm_get(host);
2733         spin_lock_irqsave(&host->lock, flags);
2734
2735         /* Check host->mrq_cmd first in case we are runtime suspended */
2736         if ((host->mrq_cmd || host->mrq_dat) &&
2737             !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
2738                 pr_err("%s: Card removed during transfer!\n",
2739                         mmc_hostname(host->mmc));
2740                 pr_err("%s: Resetting controller.\n",
2741                         mmc_hostname(host->mmc));
2742
2743                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2744
2745                 if (host->mrq_cmd) {
2746                         host->mrq_cmd->cmd->error = -ENOMEDIUM;
2747                         if (MMC_CHECK_CMDQ_MODE(host))
2748                                 tasklet_schedule(&host->finish_cmd_tasklet);
2749                         else
2750                                 tasklet_schedule(&host->finish_tasklet);
2751                 }
2752                 if (host->mrq_dat) {
2753                         host->mrq_dat->cmd->error = -ENOMEDIUM;
2754                         if (MMC_CHECK_CMDQ_MODE(host))
2755                                 tasklet_schedule(&host->finish_dat_tasklet);
2756                         else
2757                                 tasklet_schedule(&host->finish_tasklet);
2758                 }
2759         }
2760
2761         spin_unlock_irqrestore(&host->lock, flags);
2762         sdhci_runtime_pm_put(host);
2763 }
2764
2765 int sdhci_enable(struct mmc_host *mmc)
2766 {
2767         struct sdhci_host *host = mmc_priv(mmc);
2768
2769         if (!mmc->card || !(mmc->caps2 & MMC_CAP2_CLOCK_GATING))
2770                 return 0;
2771
2772         /* cancel delayed clk gate work */
2773         if (host->quirks2 & SDHCI_QUIRK2_DELAYED_CLK_GATE)
2774                 cancel_delayed_work_sync(&host->delayed_clk_gate_wrk);
2775
2776         sysedp_set_state(host->sysedpc, 1);
2777
2778         if (mmc->ios.clock) {
2779                 if (host->ops->set_clock)
2780                         host->ops->set_clock(host, mmc->ios.clock);
2781                 sdhci_set_clock(host, mmc->ios.clock);
2782         }
2783
2784         return 0;
2785 }
2786
2787 static void mmc_host_clk_gate(struct sdhci_host *host)
2788 {
2789         sdhci_set_clock(host, 0);
2790         if (host->ops->set_clock)
2791                 host->ops->set_clock(host, 0);
2792
2793         sysedp_set_state(host->sysedpc, 0);
2794
2795         return;
2796 }
2797
2798 void delayed_clk_gate_cb(struct work_struct *work)
2799 {
2800         struct sdhci_host *host = container_of(work, struct sdhci_host,
2801                                               delayed_clk_gate_wrk.work);
2802
2803         /* power off check */
2804         if (host->mmc->ios.power_mode == MMC_POWER_OFF)
2805                 goto end;
2806
2807         mmc_host_clk_gate(host);
2808 end:
2809         return;
2810 }
2811 EXPORT_SYMBOL_GPL(delayed_clk_gate_cb);
2812
2813 int sdhci_disable(struct mmc_host *mmc)
2814 {
2815         struct sdhci_host *host = mmc_priv(mmc);
2816
2817         if (!mmc->card || !(mmc->caps2 & MMC_CAP2_CLOCK_GATING))
2818                 return 0;
2819
2820         if (IS_DELAYED_CLK_GATE(host)) {
2821                 if (host->is_clk_on) {
2822                         if (IS_SDIO_CARD(host))
2823                                 host->clk_gate_tmout_ticks =
2824                                         SDIO_CLK_GATING_TICK_TMOUT;
2825                         else if (IS_EMMC_CARD(host))
2826                                 host->clk_gate_tmout_ticks =
2827                                         EMMC_CLK_GATING_TICK_TMOUT;
2828                         if (host->clk_gate_tmout_ticks > 0)
2829                                 schedule_delayed_work(
2830                                         &host->delayed_clk_gate_wrk,
2831                                         host->clk_gate_tmout_ticks);
2832                 }
2833                 return 0;
2834         }
2835
2836         mmc_host_clk_gate(host);
2837
2838         return 0;
2839 }
2840
2841 #ifdef CONFIG_MMC_FREQ_SCALING
2842 /*
2843  * Wrapper functions to call any platform specific implementation for
2844  * supporting dynamic frequency scaling for SD/MMC devices.
2845  */
2846 static int sdhci_gov_get_target(struct mmc_host *mmc, unsigned long *freq)
2847 {
2848         struct sdhci_host *host = mmc_priv(mmc);
2849
2850         if (host->ops->dfs_gov_get_target_freq)
2851                 *freq = host->ops->dfs_gov_get_target_freq(host,
2852                         mmc->devfreq_stats);
2853
2854         return 0;
2855 }
2856
2857 static int sdhci_gov_init(struct mmc_host *mmc)
2858 {
2859         struct sdhci_host *host = mmc_priv(mmc);
2860
2861         if (host->ops->dfs_gov_init)
2862                 return host->ops->dfs_gov_init(host);
2863
2864         return 0;
2865 }
2866
2867 static void sdhci_gov_exit(struct mmc_host *mmc)
2868 {
2869         struct sdhci_host *host = mmc_priv(mmc);
2870
2871         if (host->ops->dfs_gov_exit)
2872                 host->ops->dfs_gov_exit(host);
2873 }
2874 #endif
2875
2876 static int sdhci_select_drive_strength(struct mmc_host *mmc,
2877                                        unsigned int max_dtr,
2878                                        int host_drv,
2879                                        int card_drv)
2880 {
2881         struct sdhci_host *host = mmc_priv(mmc);
2882         unsigned char   drv_type;
2883
2884         /* return default strength if no handler in driver */
2885         if (!host->ops->get_drive_strength)
2886                 return MMC_SET_DRIVER_TYPE_B;
2887
2888         drv_type = host->ops->get_drive_strength(host, max_dtr,
2889                         host_drv, card_drv);
2890
2891         if (drv_type > MMC_SET_DRIVER_TYPE_D) {
2892                 pr_err("%s: Error on getting drive strength. Got drv_type %d\n"
2893                         , mmc_hostname(host->mmc), drv_type);
2894                 return MMC_SET_DRIVER_TYPE_B;
2895         }
2896
2897         return drv_type;
2898 }
2899 static void sdhci_init_card(struct mmc_host *mmc, struct mmc_card *card)
2900 {
2901         struct sdhci_host *host = mmc_priv(mmc);
2902
2903         /*
2904          * Get the max pio transfer limits if defined. This would be used to
2905          * dynamically choose between dma and pio modes depending on the
2906          * transfer parameters.
2907          */
2908         if (host->ops->get_max_pio_transfer_limits)
2909                 host->ops->get_max_pio_transfer_limits(host);
2910 }
2911 static const struct mmc_host_ops sdhci_ops = {
2912         .request        = sdhci_request,
2913         .set_ios        = sdhci_set_ios,
2914         .get_cd         = sdhci_get_cd,
2915         .get_ro         = sdhci_get_ro,
2916         .hw_reset       = sdhci_hw_reset,
2917         .enable         = sdhci_enable,
2918         .disable        = sdhci_disable,
2919         .enable_sdio_irq = sdhci_enable_sdio_irq,
2920         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2921         .execute_tuning                 = sdhci_execute_tuning,
2922         .validate_sd2_0                 = sdhci_validate_sd2_0,
2923         .card_event                     = sdhci_card_event,
2924         .card_busy      = sdhci_card_busy,
2925 #ifdef CONFIG_MMC_FREQ_SCALING
2926         .dfs_governor_init              = sdhci_gov_init,
2927         .dfs_governor_exit              = sdhci_gov_exit,
2928         .dfs_governor_get_target        = sdhci_gov_get_target,
2929 #endif
2930         .select_drive_strength          = sdhci_select_drive_strength,
2931         .post_init      = sdhci_post_init,
2932         .en_strobe      = sdhci_en_strobe,
2933         .init_card      = sdhci_init_card,
2934 };
2935
2936 /*****************************************************************************\
2937  *                                                                           *
2938  * Tasklets                                                                  *
2939  *                                                                           *
2940 \*****************************************************************************/
2941
2942 static void sdhci_tasklet_card(unsigned long param)
2943 {
2944         struct sdhci_host *host = (struct sdhci_host *)param;
2945
2946         sdhci_card_event(host->mmc);
2947
2948         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2949 }
2950
2951 static void sdhci_tasklet_finish(unsigned long param)
2952 {
2953         struct sdhci_host *host;
2954         unsigned long flags;
2955         struct mmc_request *mrq = NULL;
2956
2957         host = (struct sdhci_host *)param;
2958
2959         spin_lock_irqsave(&host->lock, flags);
2960
2961         /*
2962          * If this tasklet gets rescheduled while running, it will
2963          * be run again afterwards but without any active request.
2964          */
2965         if (!host->mrq_cmd && !host->mrq_dat) {
2966                 spin_unlock_irqrestore(&host->lock, flags);
2967                 return;
2968         }
2969
2970         del_timer(&host->timer);
2971
2972         if (host->mrq_cmd)
2973                 mrq = host->mrq_cmd;
2974         else if (host->mrq_dat)
2975                 mrq = host->mrq_dat;
2976
2977         /*
2978          * The controller needs a reset of internal state machines
2979          * upon error conditions.
2980          */
2981         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2982             ((mrq->cmd && mrq->cmd->error) ||
2983                  (mrq->data && (mrq->data->error ||
2984                   (mrq->data->stop && mrq->data->stop->error))) ||
2985                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2986
2987                 /* Some controllers need this kick or reset won't work here */
2988                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2989                         /* This is to force an update */
2990                         sdhci_update_clock(host);
2991
2992                 /* Spec says we should do both at the same time */
2993                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2994         }
2995
2996         host->mrq_cmd = NULL;
2997         host->mrq_dat = NULL;
2998         host->cmd = NULL;
2999         host->data = NULL;
3000
3001 #ifndef SDHCI_USE_LEDS_CLASS
3002         sdhci_deactivate_led(host);
3003 #endif
3004
3005         mmiowb();
3006         spin_unlock_irqrestore(&host->lock, flags);
3007
3008         mmc_request_done(host->mmc, mrq);
3009         sdhci_runtime_pm_put(host);
3010 }
3011
3012 /*
3013  * This tasklet gets scheduled to handle CMD only requests in CQ.
3014  */
3015 static void sdhci_tasklet_cmd_finish(unsigned long param)
3016 {
3017         struct sdhci_host *host;
3018         unsigned long flags;
3019         struct mmc_request *mrq;
3020
3021         host = (struct sdhci_host *)param;
3022
3023         if (!host->mrq_cmd && host->mrq_dat) {
3024                 mmc_handle_queued_request(host->mmc, MMC_HANDLE_CLR_CMD);
3025                 return;
3026         }
3027
3028         spin_lock_irqsave(&host->lock, flags);
3029
3030         /*
3031          * If this tasklet gets rescheduled while running, it will
3032          * be run again afterwards but without any active request.
3033          */
3034         if (!host->mrq_cmd) {
3035                 spin_unlock_irqrestore(&host->lock, flags);
3036                 return;
3037         }
3038
3039         del_timer(&host->timer);
3040
3041         mrq = host->mrq_cmd;
3042
3043         /*
3044          * The controller needs a reset of internal state machines
3045          * upon error conditions.
3046          */
3047         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
3048             ((mrq->cmd && mrq->cmd->error) ||
3049                  (mrq->data && (mrq->data->error ||
3050                   (mrq->data->stop && mrq->data->stop->error))) ||
3051                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
3052
3053                 /* Some controllers need this kick or reset won't work here */
3054                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3055                         /* This is to force an update */
3056                         sdhci_update_clock(host);
3057
3058                 sdhci_reset(host, SDHCI_RESET_CMD);
3059         }
3060
3061         host->mrq_cmd = NULL;
3062         host->cmd = NULL;
3063
3064 #ifndef SDHCI_USE_LEDS_CLASS
3065         sdhci_deactivate_led(host);
3066 #endif
3067
3068         mmiowb();
3069         spin_unlock_irqrestore(&host->lock, flags);
3070
3071         mmc_request_done(host->mmc, mrq);
3072         sdhci_runtime_pm_put(host);
3073 }
3074
3075 /*
3076  * This tasklet gets scheduled to handle CMD with DATA requests in CQ.
3077  */
3078 static void sdhci_tasklet_dat_finish(unsigned long param)
3079 {
3080         struct sdhci_host *host;
3081         unsigned long flags;
3082         struct mmc_request *mrq;
3083
3084         host = (struct sdhci_host *)param;
3085
3086         spin_lock_irqsave(&host->lock, flags);
3087
3088         /*
3089          * If this tasklet gets rescheduled while running, it will
3090          * be run again afterwards but without any active request.
3091          */
3092         if (!host->mrq_dat) {
3093                 spin_unlock_irqrestore(&host->lock, flags);
3094                 return;
3095         }
3096
3097         del_timer(&host->timer);
3098
3099         mrq = host->mrq_dat;
3100
3101         if (host->data_early)
3102                 mrq->data_early = 1;
3103
3104         /*
3105          * The controller needs a reset of internal state machines
3106          * upon error conditions.
3107          */
3108         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
3109             ((mrq->cmd && mrq->cmd->error) ||
3110                  (mrq->data && (mrq->data->error ||
3111                   (mrq->data->stop && mrq->data->stop->error))) ||
3112                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
3113
3114                 /* Some controllers need this kick or reset won't work here */
3115                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3116                         /* This is to force an update */
3117                         sdhci_update_clock(host);
3118
3119                 sdhci_reset(host, SDHCI_RESET_DATA);
3120         }
3121
3122         host->mrq_dat = NULL;
3123         host->data = NULL;
3124
3125 #ifndef SDHCI_USE_LEDS_CLASS
3126         sdhci_deactivate_led(host);
3127 #endif
3128
3129         mmiowb();
3130         spin_unlock_irqrestore(&host->lock, flags);
3131
3132         mmc_request_done(host->mmc, mrq);
3133         sdhci_runtime_pm_put(host);
3134 }
3135
3136 static void sdhci_timeout_timer(unsigned long data)
3137 {
3138         struct sdhci_host *host;
3139         unsigned long flags;
3140
3141         host = (struct sdhci_host *)data;
3142
3143         spin_lock_irqsave(&host->lock, flags);
3144
3145         if (host->mrq_cmd || host->mrq_dat) {
3146                 pr_err("%s: Timeout waiting for hardware "
3147                         "interrupt.\n", mmc_hostname(host->mmc));
3148                 sdhci_dumpregs(host);
3149
3150                 if (host->data) {
3151                         host->data->error = -ETIMEDOUT;
3152                         sdhci_finish_data(host);
3153                 } else {
3154                         if (host->cmd)
3155                                 host->cmd->error = -ETIMEDOUT;
3156                         else if (host->mrq_dat)
3157                                 host->mrq_dat->cmd->error = -ETIMEDOUT;
3158
3159                         if (MMC_CHECK_CMDQ_MODE(host))
3160                                 tasklet_schedule(&host->finish_cmd_tasklet);
3161                         else
3162                                 tasklet_schedule(&host->finish_tasklet);
3163                 }
3164         }
3165
3166         mmiowb();
3167         spin_unlock_irqrestore(&host->lock, flags);
3168 }
3169
3170 static void sdhci_tuning_timer(unsigned long data)
3171 {
3172         struct sdhci_host *host;
3173         unsigned long flags;
3174
3175         host = (struct sdhci_host *)data;
3176
3177         spin_lock_irqsave(&host->lock, flags);
3178
3179         host->flags |= SDHCI_NEEDS_RETUNING;
3180
3181         spin_unlock_irqrestore(&host->lock, flags);
3182 }
3183
3184 /*****************************************************************************\
3185  *                                                                           *
3186  * Interrupt handling                                                        *
3187  *                                                                           *
3188 \*****************************************************************************/
3189
3190 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
3191 {
3192         BUG_ON(intmask == 0);
3193
3194         if (!host->cmd) {
3195                 pr_err("%s: Got command interrupt 0x%08x even "
3196                         "though no command operation was in progress.\n",
3197                         mmc_hostname(host->mmc), (unsigned)intmask);
3198                 sdhci_dumpregs(host);
3199                 return;
3200         }
3201
3202         if (intmask & SDHCI_INT_TIMEOUT) {
3203                 host->cmd->error = -ETIMEDOUT;
3204         } else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
3205                         SDHCI_INT_INDEX)) {
3206                 host->cmd->error = -EILSEQ;
3207                 sdhci_dumpregs(host);
3208                 if (intmask & SDHCI_INT_INDEX)
3209                         pr_err("%s: Command END bit error, intmask: %x Interface clock = %uHz\n",
3210                         mmc_hostname(host->mmc), intmask, host->max_clk);
3211                 else
3212                         pr_err("%s: Command CRC error, intmask: %x Interface clock = %uHz\n",
3213                         mmc_hostname(host->mmc), intmask, host->max_clk);
3214         }
3215
3216         if (host->cmd->error) {
3217                 if (MMC_CHECK_CMDQ_MODE(host))
3218                         tasklet_schedule(&host->finish_cmd_tasklet);
3219                 else
3220                         tasklet_schedule(&host->finish_tasklet);
3221                 return;
3222         }
3223
3224         /*
3225          * The host can send and interrupt when the busy state has
3226          * ended, allowing us to wait without wasting CPU cycles.
3227          * Unfortunately this is overloaded on the "data complete"
3228          * interrupt, so we need to take some care when handling
3229          * it.
3230          *
3231          * Note: The 1.0 specification is a bit ambiguous about this
3232          *       feature so there might be some problems with older
3233          *       controllers.
3234          */
3235         if (host->cmd->flags & MMC_RSP_BUSY) {
3236                 if (host->cmd->data)
3237                         DBG("Cannot wait for busy signal when also "
3238                                 "doing a data transfer");
3239                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
3240                         return;
3241
3242                 /* The controller does not support the end-of-busy IRQ,
3243                  * fall through and take the SDHCI_INT_RESPONSE */
3244         }
3245
3246         if (intmask & SDHCI_INT_RESPONSE)
3247                 sdhci_finish_command(host);
3248 }
3249
3250 #ifdef CONFIG_MMC_DEBUG
3251 static void sdhci_show_adma_error(struct sdhci_host *host)
3252 {
3253         const char *name = mmc_hostname(host->mmc);
3254         u8 *desc = host->adma_desc;
3255         __le32 *dma;
3256         __le16 *len;
3257         u8 attr;
3258
3259         u32 ctrl;
3260         int next_desc;
3261         ctrl = sdhci_readl(host, SDHCI_ACMD12_ERR);
3262         if (ctrl & SDHCI_ADDRESSING_64BIT_EN) {
3263                 if (ctrl & SDHCI_HOST_VERSION_4_EN)
3264                         next_desc = 16;
3265                 else
3266                         next_desc = 12;
3267         } else {
3268                 /* 32 bit DMA mode supported*/
3269                 next_desc = 8;
3270         }
3271
3272         sdhci_dumpregs(host);
3273
3274         while (true) {
3275                 dma = (__le32 *)(desc + 4);
3276                 len = (__le16 *)(desc + 2);
3277                 attr = *desc;
3278
3279                 if (next_desc == 8) {
3280                         DBG("%s: %p: DMA-32 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
3281                                 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
3282                 } else if (next_desc == 16) {
3283                         DBG("%s: %p: DMA-64 0x%16x, LEN 0x%04x, Attr=0x%02x\n",
3284                                 name, desc, le64_to_cpu(*((__le64 *)dma)), le16_to_cpu(*len), attr);
3285                 }
3286                 desc += next_desc;
3287                 if (attr & 2)
3288                         break;
3289         }
3290 }
3291 #else
3292 static void sdhci_show_adma_error(struct sdhci_host *host) { }
3293 #endif
3294
3295 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3296 {
3297         u32 command;
3298         BUG_ON(intmask == 0);
3299
3300         /* CMD19, CMD21 generates _only_ Buffer Read Ready interrupt */
3301         if (intmask & SDHCI_INT_DATA_AVAIL) {
3302                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
3303                 if (command == MMC_SEND_TUNING_BLOCK ||
3304                     command == MMC_SEND_TUNING_BLOCK_HS200) {
3305                         host->tuning_done = 1;
3306                         wake_up(&host->buf_ready_int);
3307                         return;
3308                 }
3309         }
3310
3311         if (!host->data) {
3312                 /*
3313                  * The "data complete" interrupt is also used to
3314                  * indicate that a busy state has ended. See comment
3315                  * above in sdhci_cmd_irq().
3316                  */
3317                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
3318                         if (intmask & SDHCI_INT_DATA_END) {
3319                                 sdhci_finish_command(host);
3320                                 return;
3321                         }
3322                 }
3323
3324                 pr_err("%s: Got data interrupt 0x%08x even "
3325                         "though no data operation was in progress.\n",
3326                         mmc_hostname(host->mmc), (unsigned)intmask);
3327                 sdhci_dumpregs(host);
3328
3329                 return;
3330         }
3331
3332         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3333                 host->data->error = -ETIMEDOUT;
3334                 pr_err("%s: Data Timeout error, intmask: %x Interface clock = %uHz\n",
3335                         mmc_hostname(host->mmc), intmask, host->max_clk);
3336                 sdhci_dumpregs(host);
3337         } else if (intmask & SDHCI_INT_DATA_END_BIT) {
3338                 host->data->error = -EILSEQ;
3339                 pr_err("%s: Data END Bit error, intmask: %x Interface clock = %uHz\n",
3340                         mmc_hostname(host->mmc), intmask, host->max_clk);
3341         } else if ((intmask & SDHCI_INT_DATA_CRC) &&
3342                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
3343                         != MMC_BUS_TEST_R) {
3344                 host->data->error = -EILSEQ;
3345                 pr_err("%s: Data CRC error, intmask: %x Interface clock = %uHz\n",
3346                         mmc_hostname(host->mmc), intmask, host->max_clk);
3347                 sdhci_dumpregs(host);
3348         } else if (intmask & SDHCI_INT_ADMA_ERROR) {
3349                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
3350                 sdhci_dumpregs(host);
3351                 sdhci_show_adma_error(host);
3352                 host->data->error = -EIO;
3353                 if (host->ops->adma_workaround)
3354                         host->ops->adma_workaround(host, intmask);
3355         }
3356
3357         if (host->data->error)
3358                 sdhci_finish_data(host);
3359         else {
3360                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
3361                         sdhci_transfer_pio(host);
3362
3363                 /*
3364                  * We currently don't do anything fancy with DMA
3365                  * boundaries, but as we can't disable the feature
3366                  * we need to at least restart the transfer.
3367                  *
3368                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3369                  * should return a valid address to continue from, but as
3370                  * some controllers are faulty, don't trust them.
3371                  */
3372                 if (intmask & SDHCI_INT_DMA_END) {
3373                         u32 dmastart, dmanow;
3374                         dmastart = sg_dma_address(host->data->sg);
3375                         dmanow = dmastart + host->data->bytes_xfered;
3376                         /*
3377                          * Force update to the next DMA block boundary.
3378                          */
3379                         dmanow = (dmanow &
3380                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
3381                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
3382                         host->data->bytes_xfered = dmanow - dmastart;
3383                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
3384                                 " next 0x%08x\n",
3385                                 mmc_hostname(host->mmc), dmastart,
3386                                 host->data->bytes_xfered, dmanow);
3387                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
3388                 }
3389
3390                 if (intmask & SDHCI_INT_DATA_END) {
3391                         if ((!MMC_CHECK_CMDQ_MODE(host) && host->cmd) ||
3392                                 (MMC_CHECK_CMDQ_MODE(host) && host->cmd && (host->mrq_dat->cmd == host->cmd))) {
3393
3394                                 /*
3395                                  * Data managed to finish before the
3396                                  * command completed. Make sure we do
3397                                  * things in the proper order.
3398                                  */
3399                                 host->data_early = 1;
3400                         } else
3401                                 sdhci_finish_data(host);
3402                 }
3403         }
3404 }
3405
3406 static irqreturn_t sdhci_irq(int irq, void *dev_id)
3407 {
3408         irqreturn_t result;
3409         struct sdhci_host *host = dev_id;
3410         u32 intmask, unexpected = 0;
3411         int cardint = 0, max_loops = 16;
3412
3413         spin_lock(&host->lock);
3414
3415         if (host->runtime_suspended) {
3416                 spin_unlock(&host->lock);
3417                 pr_warning("%s: got irq while runtime suspended\n",
3418                        mmc_hostname(host->mmc));
3419                 return IRQ_HANDLED;
3420         }
3421
3422         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3423
3424         if (!intmask || intmask == 0xffffffff) {
3425                 result = IRQ_NONE;
3426                 goto out;
3427         }
3428
3429 again:
3430         DBG("*** %s got interrupt: 0x%08x\n",
3431                 mmc_hostname(host->mmc), intmask);
3432
3433         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3434                 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3435                               SDHCI_CARD_PRESENT;
3436
3437                 /*
3438                  * There is a observation on i.mx esdhc.  INSERT bit will be
3439                  * immediately set again when it gets cleared, if a card is
3440                  * inserted.  We have to mask the irq to prevent interrupt
3441                  * storm which will freeze the system.  And the REMOVE gets
3442                  * the same situation.
3443                  *
3444                  * More testing are needed here to ensure it works for other
3445                  * platforms though.
3446                  */
3447                 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
3448                                                 SDHCI_INT_CARD_REMOVE);
3449                 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
3450                                                   SDHCI_INT_CARD_INSERT);
3451
3452                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3453                              SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3454                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
3455                 tasklet_schedule(&host->card_tasklet);
3456         }
3457
3458 #ifdef CONFIG_CMD_DUMP
3459         if (mmc_hostname(host->mmc)[3] == '0')
3460                 dbg_add_host_log(host->mmc, 7,  intmask, 0xffffffff);
3461 #endif
3462
3463         if (intmask & SDHCI_INT_CMD_MASK) {
3464                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
3465                         SDHCI_INT_STATUS);
3466                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
3467         }
3468
3469         if (intmask & SDHCI_INT_DATA_MASK) {
3470                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
3471                         SDHCI_INT_STATUS);
3472                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3473         }
3474
3475         if (intmask & SDHCI_INT_RETUNING_EVENT)
3476                 host->flags |= SDHCI_NEEDS_RETUNING;
3477
3478         if ((intmask & SDHCI_INT_DATA_MASK) || (intmask & SDHCI_INT_CMD_MASK))
3479                 if (host->ops->sd_error_stats)
3480                         host->ops->sd_error_stats(host, intmask);
3481
3482         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
3483
3484         intmask &= ~SDHCI_INT_ERROR;
3485
3486         if (intmask & SDHCI_INT_BUS_POWER) {
3487                 pr_err("%s: Card is consuming too much power!\n",
3488                         mmc_hostname(host->mmc));
3489                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
3490         }
3491
3492         intmask &= ~SDHCI_INT_BUS_POWER;
3493
3494         if (intmask & SDHCI_INT_CARD_INT)
3495                 cardint = 1;
3496
3497         intmask &= ~SDHCI_INT_CARD_INT;
3498
3499         if (intmask) {
3500                 unexpected |= intmask;
3501                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3502         }
3503
3504         result = IRQ_HANDLED;
3505
3506         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3507         if (intmask && --max_loops)
3508                 goto again;
3509 out:
3510         spin_unlock(&host->lock);
3511
3512         if (unexpected) {
3513                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3514                            mmc_hostname(host->mmc), unexpected);
3515                 sdhci_dumpregs(host);
3516         }
3517         /*
3518          * We have to delay this as it calls back into the driver.
3519          */
3520         if (cardint)
3521                 mmc_signal_sdio_irq(host->mmc);
3522
3523         return result;
3524 }
3525
3526 /*****************************************************************************\
3527  *                                                                           *
3528  * Suspend/resume                                                            *
3529  *                                                                           *
3530 \*****************************************************************************/
3531
3532 #ifdef CONFIG_PM
3533 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
3534 {
3535         u8 val;
3536         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3537                         | SDHCI_WAKE_ON_INT;
3538
3539         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3540         val |= mask ;
3541         /* Avoid fake wake up */
3542         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
3543                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
3544         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3545 }
3546 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
3547
3548 void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3549 {
3550         u8 val;
3551         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3552                         | SDHCI_WAKE_ON_INT;
3553
3554         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3555         val &= ~mask;
3556         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3557 }
3558 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
3559
3560 int sdhci_suspend_host(struct sdhci_host *host)
3561 {
3562         int ret;
3563         struct mmc_host *mmc = host->mmc;
3564
3565         host->suspend_task = current;
3566
3567         if (host->ops->platform_suspend)
3568                 host->ops->platform_suspend(host);
3569
3570         sdhci_disable_card_detection(host);
3571
3572         /* Disable tuning since we are suspending */
3573         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
3574                 del_timer_sync(&host->tuning_timer);
3575                 host->flags &= ~SDHCI_NEEDS_RETUNING;
3576         }
3577
3578         /*
3579          * If eMMC cards are put in sleep state, Vccq can be disabled
3580          * but Vcc would still be powered on. In resume, we only restore
3581          * the controller context. So, set MMC_PM_KEEP_POWER flag.
3582          */
3583         if (mmc_card_can_sleep(mmc) && !(mmc->caps2 & MMC_CAP2_NO_SLEEP_CMD))
3584                 mmc->pm_flags |= MMC_PM_KEEP_POWER;
3585
3586         ret = mmc_suspend_host(host->mmc);
3587         if (ret) {
3588                 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
3589                         host->flags |= SDHCI_NEEDS_RETUNING;
3590                         mod_timer(&host->tuning_timer, jiffies +
3591                                         host->tuning_count * HZ);
3592                 }
3593
3594                 sdhci_enable_card_detection(host);
3595
3596                 host->suspend_task = NULL;
3597                 return ret;
3598         }
3599
3600         /* cancel delayed clk gate work */
3601         if (host->quirks2 & SDHCI_QUIRK2_DELAYED_CLK_GATE)
3602                 cancel_delayed_work_sync(&host->delayed_clk_gate_wrk);
3603
3604         /*
3605          * If host clock is disabled but the register access requires host
3606          * clock, then enable the clock, mask the interrupts and disable
3607          * the clock.
3608          */
3609         if (host->quirks2 & SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK)
3610                 if ((!host->clock && host->ops->set_clock) &&
3611                         (host->quirks2 & SDHCI_QUIRK2_DELAYED_CLK_GATE))
3612                         host->ops->set_clock(host, max(mmc->ios.clock, mmc->f_min));
3613
3614         if (mmc->pm_flags & MMC_PM_KEEP_POWER)
3615                 host->card_int_set = host->ier &
3616                         SDHCI_INT_CARD_INT;
3617
3618         if (!device_may_wakeup(mmc_dev(host->mmc))) {
3619                 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3620
3621                 if (host->quirks2 & SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK)
3622                         if ((!host->clock && host->ops->set_clock) &&
3623                         (host->quirks2 & SDHCI_QUIRK2_DELAYED_CLK_GATE))
3624                                 host->ops->set_clock(host, 0);
3625
3626                 if (host->irq)
3627                         disable_irq(host->irq);
3628         } else {
3629                 sdhci_enable_irq_wakeups(host);
3630                 enable_irq_wake(host->irq);
3631
3632                 if (host->quirks2 & SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK)
3633                         if ((!host->clock && host->ops->set_clock) &&
3634                         (host->quirks2 & SDHCI_QUIRK2_DELAYED_CLK_GATE))
3635                                 host->ops->set_clock(host, 0);
3636         }
3637
3638         host->suspend_task = NULL;
3639
3640         return ret;
3641 }
3642
3643 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3644
3645 int sdhci_resume_host(struct sdhci_host *host)
3646 {
3647         int ret;
3648         struct mmc_host *mmc = host->mmc;
3649
3650         host->suspend_task = current;
3651
3652
3653         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3654                 if (host->ops->enable_dma)
3655                         host->ops->enable_dma(host);
3656         }
3657
3658         if (!device_may_wakeup(mmc_dev(host->mmc))) {
3659                 if (host->irq)
3660                         enable_irq(host->irq);
3661         } else {
3662                 sdhci_disable_irq_wakeups(host);
3663                 disable_irq_wake(host->irq);
3664         }
3665
3666         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3667             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3668                 /* Card keeps power but host controller does not */
3669                 sdhci_init(host, 0);
3670                 host->pwr = 0;
3671                 host->clock = 0;
3672                 sdhci_do_set_ios(host, &host->mmc->ios);
3673         } else {
3674                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3675                 mmiowb();
3676         }
3677
3678         ret = mmc_resume_host(host->mmc);
3679         /* Enable card interrupt as it is overwritten in sdhci_init */
3680         if ((mmc->caps & MMC_CAP_SDIO_IRQ) &&
3681                 (mmc->pm_flags & MMC_PM_KEEP_POWER))
3682                         if (host->card_int_set)
3683                                 mmc->ops->enable_sdio_irq(mmc, true);
3684
3685         sdhci_enable_card_detection(host);
3686
3687         if (host->ops->platform_resume)
3688                 host->ops->platform_resume(host);
3689
3690         /* Set the re-tuning expiration flag */
3691         if (host->flags & SDHCI_USING_RETUNING_TIMER)
3692                 host->flags |= SDHCI_NEEDS_RETUNING;
3693
3694         host->suspend_task = NULL;
3695
3696         return ret;
3697 }
3698
3699 EXPORT_SYMBOL_GPL(sdhci_resume_host);
3700 #endif /* CONFIG_PM */
3701
3702 #ifdef CONFIG_PM_RUNTIME
3703
3704 static int sdhci_runtime_pm_get(struct sdhci_host *host)
3705 {
3706         int present;
3707
3708         if (!(host->quirks2 & SDHCI_QUIRK2_MMC_RTPM))
3709                 return 0;
3710
3711         present = mmc_gpio_get_cd(host->mmc);
3712         if (present < 0) {
3713                 /* If polling, assume that the card is always present. */
3714                 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
3715                         if (host->ops->get_cd)
3716                                 present = host->ops->get_cd(host);
3717                         else
3718                                 present = 1;
3719                 else
3720                         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3721                                         SDHCI_CARD_PRESENT;
3722         }
3723
3724         if ((present && !host->mmc->card && (host->runtime_suspended == false))
3725                                         || host->suspend_task == current) {
3726                 pm_runtime_get_noresume(host->mmc->parent);
3727                 return 0;
3728         }
3729
3730         return pm_runtime_get_sync(host->mmc->parent);
3731 }
3732
3733 static int sdhci_runtime_pm_put(struct sdhci_host *host)
3734 {
3735         int present;
3736
3737         if (!(host->quirks2 & SDHCI_QUIRK2_MMC_RTPM))
3738                 return 0;
3739
3740         present = mmc_gpio_get_cd(host->mmc);
3741         if (present < 0) {
3742                 /* If polling, assume that the card is always present. */
3743                 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
3744                         if (host->ops->get_cd)
3745                                 present = host->ops->get_cd(host);
3746                         else
3747                                 present = 1;
3748                 else
3749                         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3750                                         SDHCI_CARD_PRESENT;
3751         }
3752         if ((present && !host->mmc->card) || host->suspend_task == current) {
3753                 pm_runtime_mark_last_busy(host->mmc->parent);
3754                 pm_runtime_put_noidle(host->mmc->parent);
3755                 return 0;
3756         }
3757
3758         pm_runtime_mark_last_busy(host->mmc->parent);
3759         return pm_runtime_put_autosuspend(host->mmc->parent);
3760 }
3761
3762 int sdhci_runtime_suspend_host(struct sdhci_host *host)
3763 {
3764         unsigned long flags;
3765         int ret = 0;
3766
3767         if (!(host->quirks2 & SDHCI_QUIRK2_MMC_RTPM))
3768                 return 0;
3769
3770         if (host->quirks2 & SDHCI_QUIRK2_NON_STD_RTPM) {
3771                 spin_lock_irqsave(&host->lock, flags);
3772                 host->runtime_suspended = true;
3773                 spin_unlock_irqrestore(&host->lock, flags);
3774
3775                 if (host->mmc->ios.clock) {
3776                         sdhci_set_clock(host, 0);
3777                         if (host->ops->set_clock)
3778                                 host->ops->set_clock(host, 0);
3779                         sysedp_set_state(host->sysedpc, 0);
3780                 }
3781                 goto lbl_end;
3782         }
3783
3784         /* Disable tuning since we are suspending */
3785         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
3786                 del_timer_sync(&host->tuning_timer);
3787                 host->flags &= ~SDHCI_NEEDS_RETUNING;
3788         }
3789
3790         if (host->ops->set_clock)
3791                 host->ops->set_clock(host, host->mmc->f_min);
3792         sdhci_set_clock(host, host->mmc->f_min);
3793
3794         spin_lock_irqsave(&host->lock, flags);
3795         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3796         spin_unlock_irqrestore(&host->lock, flags);
3797
3798         synchronize_irq(host->irq);
3799
3800         spin_lock_irqsave(&host->lock, flags);
3801         host->runtime_suspended = true;
3802         spin_unlock_irqrestore(&host->lock, flags);
3803
3804         sdhci_set_clock(host, 0);
3805         if (host->ops->set_clock)
3806                 host->ops->set_clock(host, 0);
3807
3808 lbl_end:
3809         return ret;
3810 }
3811 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3812
3813 int sdhci_runtime_resume_host(struct sdhci_host *host)
3814 {
3815         unsigned long flags;
3816         int ret = 0, host_flags = host->flags;
3817         unsigned int freq;
3818
3819         if (!(host->quirks2 & SDHCI_QUIRK2_MMC_RTPM))
3820                 return 0;
3821
3822         if (host->quirks2 & SDHCI_QUIRK2_NON_STD_RTPM) {
3823                 if (host->mmc->ios.clock) {
3824                         freq = host->mmc->ios.clock;
3825                 } else {
3826                         if (!host->mmc->f_min)
3827                                 host->mmc->f_min = MIN_SDMMC_FREQ;
3828                         freq = host->mmc->f_min;
3829                         host->clock = freq;
3830                 }
3831
3832                 if (host->ops->set_clock)
3833                         host->ops->set_clock(host, freq);
3834                 sdhci_set_clock(host, freq);
3835
3836                 sysedp_set_state(host->sysedpc, 1);
3837                 spin_lock_irqsave(&host->lock, flags);
3838                 host->runtime_suspended = false;
3839                 spin_unlock_irqrestore(&host->lock, flags);
3840                 goto lbl_end;
3841         }
3842
3843         if (host->ops->set_clock)
3844                 host->ops->set_clock(host, host->mmc->f_min);
3845         sdhci_set_clock(host, host->mmc->f_min);
3846
3847         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3848                 if (host->ops->enable_dma)
3849                         host->ops->enable_dma(host);
3850         }
3851
3852         sdhci_init(host, 0);
3853
3854         /* Force clock and power re-program */
3855         host->pwr = 0;
3856         host->clock = 0;
3857         sdhci_do_set_ios(host, &host->mmc->ios);
3858
3859         if (host->mmc->ios.clock) {
3860                 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
3861         /* Do any post voltage switch platform specific configuration */
3862                 if (host->ops->switch_signal_voltage_exit)
3863                         host->ops->switch_signal_voltage_exit(host,
3864                                 host->mmc->ios.signal_voltage);
3865         }
3866
3867         if ((host_flags & SDHCI_PV_ENABLED) &&
3868                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3869                 spin_lock_irqsave(&host->lock, flags);
3870                 sdhci_enable_preset_value(host, true);
3871                 spin_unlock_irqrestore(&host->lock, flags);
3872         }
3873
3874         /* Set the re-tuning expiration flag */
3875         if (host->flags & SDHCI_USING_RETUNING_TIMER)
3876                 host->flags |= SDHCI_NEEDS_RETUNING;
3877
3878         spin_lock_irqsave(&host->lock, flags);
3879
3880         host->runtime_suspended = false;
3881
3882         /* Enable SDIO IRQ */
3883         if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
3884                 sdhci_enable_sdio_irq_nolock(host, true);
3885
3886         /* Enable Card Detection */
3887         sdhci_enable_card_detection(host);
3888
3889         spin_unlock_irqrestore(&host->lock, flags);
3890
3891 lbl_end:
3892         return ret;
3893 }
3894 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3895
3896 #endif
3897
3898 /*****************************************************************************\
3899  *                                                                           *
3900  * Device allocation/registration                                            *
3901  *                                                                           *
3902 \*****************************************************************************/
3903
3904 struct sdhci_host *sdhci_alloc_host(struct device *dev,
3905         size_t priv_size)
3906 {
3907         struct mmc_host *mmc;
3908         struct sdhci_host *host;
3909
3910         WARN_ON(dev == NULL);
3911
3912         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3913         if (!mmc)
3914                 return ERR_PTR(-ENOMEM);
3915
3916         host = mmc_priv(mmc);
3917         host->mmc = mmc;
3918
3919         return host;
3920 }
3921
3922 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3923
3924 #ifdef CONFIG_DEBUG_FS
3925 static int show_sdhci_perf_stats(struct seq_file *s, void *data)
3926 {
3927         struct sdhci_host *host = s->private;
3928         int i;
3929         u32 avg_perf2;
3930         u32 last_perf_in_class;
3931         struct data_stat_entry *stat = NULL;
3932         char buf[250];
3933         u64 my_total_bytes;
3934         u64 my_total_usecs;
3935         unsigned int overall_avg_perf2;
3936
3937         seq_printf(s, "SDHCI(%s): perf statistics stat_size=%d\n",
3938                 mmc_hostname(host->mmc),
3939                 host->sdhci_data_stat.stat_size
3940                 );
3941         if (host->sdhci_data_stat.stat_size) {
3942                 seq_printf(s, "SDHCI(%s): perf statistics:\n",
3943                         mmc_hostname(host->mmc));
3944                 seq_puts(s,
3945                 "Note: Performance figures in kilo bits per sec(kbps)\n");
3946                 seq_puts(s,
3947                 "S.No.    Block       Direction    Num blks/        Total     Total           Total          Last            Last usec          Avg kbps        Last kbps           Min kbps   Max kbps\n");
3948                 seq_puts(s,
3949                 "         Size        (R/W)        transfer         Bytes     Transfers       Time(usec)     Bytes           Duration           Perf            Perf                Perf       Perf\n");
3950         }
3951         my_total_bytes = 0;
3952         my_total_usecs = 0;
3953         for (i = 0; i < host->sdhci_data_stat.stat_size; i++) {
3954                 if (!stat)
3955                         stat = host->sdhci_data_stat.head;
3956                 else
3957                         stat = stat->next;
3958                 if (!stat) {
3959                         pr_err("%s %s: sdhci data stat head NULL i=%d\n",
3960                                 mmc_hostname(host->mmc), __func__, i);
3961                         break;
3962                 }
3963                 get_kbps_from_size_n_usec_64bit(
3964                         ((stat->total_bytes << 3) * 1000),
3965                         stat->total_usecs, &avg_perf2);
3966                 get_kbps_from_size_n_usec_32bit(
3967                         (((u32)stat->current_transferred_bytes << 3) * 1000),
3968                         stat->duration_usecs,
3969                         &last_perf_in_class);
3970                 my_total_bytes += stat->total_bytes;
3971                 my_total_usecs += stat->total_usecs;
3972                 snprintf(buf, 250,
3973                         "%2d    %4d           %c       %8d    %16lld    %8d        %16lld    %8d            %8d           %8d         %8d         %8d    %8d\n",
3974                         (i + 1),
3975                         stat->stat_blk_size,
3976                         stat->is_read ? 'R' : 'W',
3977                         stat->stat_blks_per_transfer,
3978                         stat->total_bytes,
3979                         stat->total_transfers,
3980                         stat->total_usecs,
3981                         stat->current_transferred_bytes,
3982                         stat->duration_usecs,
3983                         avg_perf2,
3984                         last_perf_in_class,
3985                         stat->min_kbps,
3986                         stat->max_kbps
3987                         );
3988                 seq_puts(s, buf);
3989         }
3990         get_kbps_from_size_n_usec_64bit(
3991                 ((my_total_bytes << 3) * 1000),
3992                 my_total_usecs, &overall_avg_perf2);
3993         snprintf(buf, 250,
3994                 "Total_bytes=%lldB, time=%lldusecs, overall kbps=%d\n",
3995                 my_total_bytes, my_total_usecs,
3996                 overall_avg_perf2);
3997         seq_puts(s, buf);
3998
3999         return 0;
4000 }
4001
4002 static int sdhci_perf_stats_dump(struct inode *inode, struct file *file)
4003 {
4004         return single_open(file, show_sdhci_perf_stats, inode->i_private);
4005 }
4006
4007 static const struct file_operations flush_sdhci_perf_stats_fops = {
4008         .open           = sdhci_perf_stats_dump,
4009         .read           = seq_read,
4010         .llseek         = seq_lseek,
4011         .release        = single_release,
4012 };
4013
4014 static int restart_sdhci_perf_stats(struct seq_file *s, void *data)
4015 {
4016         struct sdhci_host *host = s->private;
4017
4018         free_stats_nodes(host);
4019         return 0;
4020 }
4021
4022 static int sdhci_perf_stats_restart(struct inode *inode, struct file *file)
4023 {
4024         return single_open(file, restart_sdhci_perf_stats, inode->i_private);
4025 }
4026
4027 static const struct file_operations reset_sdhci_perf_stats_fops = {
4028         .open           = sdhci_perf_stats_restart,
4029         .read           = seq_read,
4030         .llseek         = seq_lseek,
4031         .release        = single_release,
4032 };
4033
4034 static void sdhci_debugfs_init(struct sdhci_host *host)
4035 {
4036         struct dentry *root = host->debugfs_root;
4037
4038         /*
4039          * debugfs nodes earlier were created from sdhci-tegra,
4040          * In this change root debugfs node is created first-come-first-serve
4041          */
4042         if (!root) {
4043                 root = debugfs_create_dir(dev_name(mmc_dev(host->mmc)), NULL);
4044                 if (IS_ERR_OR_NULL(root))
4045                         goto err_root;
4046                 host->debugfs_root = root;
4047         }
4048
4049         if (!debugfs_create_u32("enable_sdhci_perf_stats", S_IRUGO | S_IWUSR,
4050                 root, (u32 *)&host->enable_sdhci_perf_stats))
4051                 goto err_root;
4052
4053         if (!debugfs_create_file("reset_sdhci_perf_stats", S_IRUGO,
4054                 root, host, &reset_sdhci_perf_stats_fops))
4055                 goto err_root;
4056
4057         if (!debugfs_create_file("sdhci_perf_stats", S_IRUGO,
4058                 root, host, &flush_sdhci_perf_stats_fops))
4059                 goto err_root;
4060
4061         if (!debugfs_create_u32("sdhci_perf_no_data_transfer_count", S_IRUGO,
4062                 root, (u32 *)&host->no_data_transfer_count))
4063                 goto err_root;
4064
4065         if (!debugfs_create_u32("max_pio_size", S_IRUGO | S_IWUSR,
4066                 root, (u32 *)&host->max_pio_size))
4067                 goto err_root;
4068
4069         if (!debugfs_create_u32("max_pio_blocks", S_IRUGO | S_IWUSR,
4070                 root, (u32 *)&host->max_pio_blocks))
4071                 goto err_root;
4072
4073         return;
4074
4075 err_root:
4076         debugfs_remove_recursive(root);
4077         host->debugfs_root = NULL;
4078
4079         return;
4080 }
4081 #endif
4082
4083 /* runtime pm is not enabled before add host */
4084 int sdhci_add_host(struct sdhci_host *host)
4085 {
4086         struct mmc_host *mmc;
4087         u32 caps[2] = {0, 0};
4088         u32 max_current_caps;
4089         unsigned int ocr_avail;
4090         int ret;
4091
4092         WARN_ON(host == NULL);
4093         if (host == NULL)
4094                 return -EINVAL;
4095
4096         mmc = host->mmc;
4097
4098         if (debug_quirks)
4099                 host->quirks = debug_quirks;
4100         if (debug_quirks2)
4101                 host->quirks2 = debug_quirks2;
4102
4103         sdhci_reset(host, SDHCI_RESET_ALL);
4104
4105         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
4106         host->version = (host->version & SDHCI_SPEC_VER_MASK)
4107                                 >> SDHCI_SPEC_VER_SHIFT;
4108         if (host->version > SDHCI_SPEC_400) {
4109                 pr_err("%s: Unknown controller version (%d). "
4110                         "You may experience problems.\n", mmc_hostname(mmc),
4111                         host->version);
4112         }
4113
4114         host->mrq_cmd = NULL;
4115         host->mrq_dat = NULL;
4116         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
4117                 sdhci_readl(host, SDHCI_CAPABILITIES);
4118
4119         if (host->version >= SDHCI_SPEC_300)
4120                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
4121                         host->caps1 :
4122                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
4123
4124         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
4125                 host->flags |= SDHCI_USE_SDMA;
4126         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
4127                 DBG("Controller doesn't have SDMA capability\n");
4128         else
4129                 host->flags |= SDHCI_USE_SDMA;
4130
4131         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
4132                 (host->flags & SDHCI_USE_SDMA)) {
4133                 DBG("Disabling DMA as it is marked broken\n");
4134                 host->flags &= ~SDHCI_USE_SDMA;
4135         }
4136
4137         if ((host->version >= SDHCI_SPEC_200) &&
4138                 (caps[0] & SDHCI_CAN_DO_ADMA2))
4139                 host->flags |= SDHCI_USE_ADMA;
4140
4141         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
4142                 (host->flags & SDHCI_USE_ADMA)) {
4143                 DBG("Disabling ADMA as it is marked broken\n");
4144                 host->flags &= ~SDHCI_USE_ADMA;
4145         }
4146
4147         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
4148                 if (host->ops->enable_dma) {
4149                         if (host->ops->enable_dma(host)) {
4150                                 pr_warning("%s: No suitable DMA "
4151                                         "available. Falling back to PIO.\n",
4152                                         mmc_hostname(mmc));
4153                                 host->flags &=
4154                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4155                         }
4156                 }
4157         }
4158
4159         if (host->flags & SDHCI_USE_ADMA) {
4160                 /*
4161                  * We need to allocate descriptors for all sg entries
4162                  * (128) and potentially one alignment transfer for
4163                  * each of those entries. Simply allocating 128 bits
4164                  * for each entry
4165                  */
4166                 if (mmc_dev(host->mmc)->dma_mask &&
4167                                 mmc_dev(host->mmc)->coherent_dma_mask) {
4168                         host->adma_desc = dma_alloc_coherent(
4169                                         mmc_dev(host->mmc), (128 * 2 + 1) * 8,
4170                                         &host->adma_addr, GFP_KERNEL);
4171                         if (!host->adma_desc)
4172                                 goto err_dma_alloc;
4173
4174                         host->align_buffer = dma_alloc_coherent(
4175                                         mmc_dev(host->mmc), 128 * 8,
4176                                         &host->align_addr, GFP_KERNEL);
4177                         if (!host->align_buffer) {
4178                                 dma_free_coherent(mmc_dev(host->mmc),
4179                                                 (128 * 2 + 1) * 8,
4180                                                 host->adma_desc,
4181                                                 host->adma_addr);
4182                                 host->adma_desc = NULL;
4183                                 goto err_dma_alloc;
4184                         }
4185
4186                         host->use_dma_alloc = true;
4187
4188                         BUG_ON(host->adma_addr & 0x3);
4189                         BUG_ON(host->align_addr & 0x3);
4190                         goto out_dma_alloc;
4191                 }
4192 err_dma_alloc:
4193
4194                 host->adma_desc = kmalloc((128 * 2 + 1) * 8, GFP_KERNEL);
4195                 host->align_buffer = kmalloc(128 * 8, GFP_KERNEL);
4196                 if (!host->adma_desc || !host->align_buffer) {
4197                         kfree(host->adma_desc);
4198                         kfree(host->align_buffer);
4199                         pr_warning("%s: Unable to allocate ADMA "
4200                                 "buffers. Falling back to standard DMA.\n",
4201                                 mmc_hostname(mmc));
4202                         host->flags &= ~SDHCI_USE_ADMA;
4203                 }
4204         }
4205 out_dma_alloc:
4206
4207         /*
4208          * If we use DMA, then it's up to the caller to set the DMA
4209          * mask, but PIO does not need the hw shim so we set a new
4210          * mask here in that case.
4211          */
4212         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
4213                 host->dma_mask = DMA_BIT_MASK(64);
4214                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
4215         }
4216
4217         if (host->version >= SDHCI_SPEC_300)
4218                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
4219                         >> SDHCI_CLOCK_BASE_SHIFT;
4220         else
4221                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
4222                         >> SDHCI_CLOCK_BASE_SHIFT;
4223
4224         host->max_clk *= 1000000;
4225
4226         if (mmc->caps2 & MMC_CAP2_HS533)
4227                 host->max_clk = MMC_HS533_MAX_DTR;
4228
4229         if (host->max_clk == 0 || host->quirks &
4230                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4231                 if (!host->ops->get_max_clock) {
4232                         pr_err("%s: Hardware doesn't specify base clock "
4233                                "frequency.\n", mmc_hostname(mmc));
4234                         return -ENODEV;
4235                 }
4236                 host->max_clk = host->ops->get_max_clock(host);
4237         }
4238
4239         /*
4240          * In case of Host Controller v3.00, find out whether clock
4241          * multiplier is supported.
4242          */
4243         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
4244                         SDHCI_CLOCK_MUL_SHIFT;
4245
4246         /*
4247          * In case the value in Clock Multiplier is 0, then programmable
4248          * clock mode is not supported, otherwise the actual clock
4249          * multiplier is one more than the value of Clock Multiplier
4250          * in the Capabilities Register.
4251          */
4252         if (host->clk_mul)
4253                 host->clk_mul += 1;
4254
4255         /*
4256          * Set host parameters.
4257          */
4258         mmc->ops = &sdhci_ops;
4259         mmc->f_max = host->max_clk;
4260         if (host->ops->get_min_clock)
4261                 mmc->f_min = host->ops->get_min_clock(host);
4262         else if (host->version >= SDHCI_SPEC_300) {
4263                 if (host->clk_mul) {
4264                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
4265                         mmc->f_max = host->max_clk * host->clk_mul;
4266                 } else
4267                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
4268         } else
4269                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
4270
4271         host->timeout_clk =
4272                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
4273         if (host->timeout_clk == 0) {
4274                 if (host->ops->get_timeout_clock) {
4275                         host->timeout_clk = host->ops->get_timeout_clock(host);
4276                 } else if (!(host->quirks &
4277                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4278                         pr_err("%s: Hardware doesn't specify timeout clock "
4279                                "frequency.\n", mmc_hostname(mmc));
4280                         return -ENODEV;
4281                 }
4282         }
4283         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
4284                 host->timeout_clk *= 1000;
4285
4286         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
4287                 host->timeout_clk = mmc->f_max / 1000;
4288
4289         if (!(host->quirks2 & SDHCI_QUIRK2_NO_CALC_MAX_DISCARD_TO))
4290                 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
4291
4292         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4293                 host->flags |= SDHCI_AUTO_CMD12;
4294
4295         /* Auto-CMD23 stuff only works in ADMA or PIO. */
4296         if ((host->version >= SDHCI_SPEC_300) &&
4297             ((host->flags & SDHCI_USE_ADMA) ||
4298              !(host->flags & SDHCI_USE_SDMA))) {
4299                 host->flags |= SDHCI_AUTO_CMD23;
4300                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
4301         } else {
4302                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
4303         }
4304
4305         /*
4306          * A controller may support 8-bit width, but the board itself
4307          * might not have the pins brought out.  Boards that support
4308          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
4309          * their platform code before calling sdhci_add_host(), and we
4310          * won't assume 8-bit width for hosts without that CAP.
4311          */
4312         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
4313                 mmc->caps |= MMC_CAP_4_BIT_DATA;
4314
4315         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4316                 mmc->caps &= ~MMC_CAP_CMD23;
4317
4318         if (caps[0] & SDHCI_CAN_DO_HISPD)
4319                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
4320
4321         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4322             !(host->mmc->caps & MMC_CAP_NONREMOVABLE) && !(host->ops->get_cd))
4323                 mmc->caps |= MMC_CAP_NEEDS_POLL;
4324
4325         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
4326         host->vqmmc = regulator_get(mmc_dev(mmc), "vqmmc");
4327         if (IS_ERR_OR_NULL(host->vqmmc)) {
4328                 if (PTR_ERR(host->vqmmc) < 0) {
4329                         pr_info("%s: no vqmmc regulator found\n",
4330                                 mmc_hostname(mmc));
4331                         host->vqmmc = NULL;
4332                 }
4333         } else {
4334                 ret = regulator_enable(host->vqmmc);
4335                 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
4336                         1950000))
4337                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
4338                                         SDHCI_SUPPORT_SDR50 |
4339                                         SDHCI_SUPPORT_DDR50);
4340                 if (ret) {
4341                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
4342                                 mmc_hostname(mmc), ret);
4343                         host->vqmmc = NULL;
4344                 }
4345         }
4346
4347         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
4348                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4349                        SDHCI_SUPPORT_DDR50);
4350
4351         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
4352         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4353                        SDHCI_SUPPORT_DDR50))
4354                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4355
4356         /* SDR104 supports also implies SDR50 support */
4357         if (caps[1] & SDHCI_SUPPORT_SDR104)
4358                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
4359         else if (caps[1] & SDHCI_SUPPORT_SDR50)
4360                 mmc->caps |= MMC_CAP_UHS_SDR50;
4361
4362         if (caps[1] & SDHCI_SUPPORT_DDR50)
4363                 mmc->caps |= MMC_CAP_UHS_DDR50;
4364
4365         /* Does the host need tuning for SDR50? */
4366         if (caps[1] & SDHCI_USE_SDR50_TUNING)
4367                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4368
4369         /* Does the host need tuning for HS200? */
4370         if (mmc->caps2 & MMC_CAP2_HS200)
4371                 host->flags |= SDHCI_HS200_NEEDS_TUNING;
4372
4373         /* Driver Type(s) (A, C, D) supported by the host */
4374         if (caps[1] & SDHCI_DRIVER_TYPE_A)
4375                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
4376         if (caps[1] & SDHCI_DRIVER_TYPE_C)
4377                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
4378         if (caps[1] & SDHCI_DRIVER_TYPE_D)
4379                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4380
4381         /* Initial value for re-tuning timer count */
4382         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
4383                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
4384         /*
4385          * If the re-tuning timer count value is 0xF, the timer count
4386          * information should be obtained in a non-standard way.
4387          */
4388         if (host->tuning_count == 0xF) {
4389                 if (host->ops->get_tuning_counter) {
4390                         host->tuning_count =
4391                                 host->ops->get_tuning_counter(host);
4392                 } else {
4393                         host->tuning_count = 0;
4394                 }
4395         }
4396
4397         /*
4398          * In case Re-tuning Timer is not disabled, the actual value of
4399          * re-tuning timer will be 2 ^ (n - 1).
4400          */
4401         if (host->tuning_count)
4402                 host->tuning_count = 1 << (host->tuning_count - 1);
4403
4404         /* Re-tuning mode supported by the Host Controller */
4405         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
4406                              SDHCI_RETUNING_MODE_SHIFT;
4407
4408         ocr_avail = 0;
4409
4410         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
4411         if (IS_ERR_OR_NULL(host->vmmc)) {
4412                 if (PTR_ERR(host->vmmc) < 0) {
4413                         pr_info("%s: no vmmc regulator found\n",
4414                                 mmc_hostname(mmc));
4415                         host->vmmc = NULL;
4416                 }
4417         }
4418
4419 #ifdef CONFIG_REGULATOR
4420         /*
4421          * Voltage range check makes sense only if regulator reports
4422          * any voltage value.
4423          */
4424         if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
4425                 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
4426                         3600000);
4427                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
4428                         caps[0] &= ~SDHCI_CAN_VDD_330;
4429                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
4430                         caps[0] &= ~SDHCI_CAN_VDD_300;
4431                 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
4432                         1950000);
4433                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
4434                         caps[0] &= ~SDHCI_CAN_VDD_180;
4435         }
4436 #endif /* CONFIG_REGULATOR */
4437
4438         /*
4439          * According to SD Host Controller spec v3.00, if the Host System
4440          * can afford more than 150mA, Host Driver should set XPC to 1. Also
4441          * the value is meaningful only if Voltage Support in the Capabilities
4442          * register is set. The actual current value is 4 times the register
4443          * value.
4444          */
4445         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
4446         if (!max_current_caps && host->vmmc) {
4447                 u32 curr = regulator_get_current_limit(host->vmmc);
4448                 if (curr > 0) {
4449
4450                         /* convert to SDHCI_MAX_CURRENT format */
4451                         curr = curr/1000;  /* convert to mA */
4452                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4453
4454                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4455                         max_current_caps =
4456                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
4457                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
4458                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
4459                 }
4460         }
4461
4462         if (caps[0] & SDHCI_CAN_VDD_330) {
4463                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
4464
4465                 mmc->max_current_330 = ((max_current_caps &
4466                                    SDHCI_MAX_CURRENT_330_MASK) >>
4467                                    SDHCI_MAX_CURRENT_330_SHIFT) *
4468                                    SDHCI_MAX_CURRENT_MULTIPLIER;
4469         }
4470         if (caps[0] & SDHCI_CAN_VDD_300) {
4471                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
4472
4473                 mmc->max_current_300 = ((max_current_caps &
4474                                    SDHCI_MAX_CURRENT_300_MASK) >>
4475                                    SDHCI_MAX_CURRENT_300_SHIFT) *
4476                                    SDHCI_MAX_CURRENT_MULTIPLIER;
4477         }
4478         if (caps[0] & SDHCI_CAN_VDD_180) {
4479                 ocr_avail |= MMC_VDD_165_195;
4480
4481                 mmc->max_current_180 = ((max_current_caps &
4482                                    SDHCI_MAX_CURRENT_180_MASK) >>
4483                                    SDHCI_MAX_CURRENT_180_SHIFT) *
4484                                    SDHCI_MAX_CURRENT_MULTIPLIER;
4485         }
4486
4487         mmc->ocr_avail = ocr_avail;
4488         mmc->ocr_avail_sdio = ocr_avail;
4489         if (host->ocr_avail_sdio)
4490                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4491         mmc->ocr_avail_sd = ocr_avail;
4492         if (host->ocr_avail_sd)
4493                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4494         else /* normal SD controllers don't support 1.8V */
4495                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4496         mmc->ocr_avail_mmc = ocr_avail;
4497         if (host->ocr_avail_mmc)
4498                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4499
4500         if (mmc->ocr_avail == 0) {
4501                 pr_err("%s: Hardware doesn't report any "
4502                         "support voltages.\n", mmc_hostname(mmc));
4503                 return -ENODEV;
4504         }
4505
4506         spin_lock_init(&host->lock);
4507
4508         /*
4509          * Maximum number of segments. Depends on if the hardware
4510          * can do scatter/gather or not.
4511          */
4512         if (host->flags & SDHCI_USE_ADMA)
4513                 mmc->max_segs = 128;
4514         else if (host->flags & SDHCI_USE_SDMA)
4515                 mmc->max_segs = 1;
4516         else /* PIO */
4517                 mmc->max_segs = 128;
4518
4519         /*
4520          * Maximum number of sectors in one transfer. Limited by DMA boundary
4521          * size (512KiB).
4522          */
4523         mmc->max_req_size = 524288;
4524
4525         /*
4526          * Maximum segment size. Could be one segment with the maximum number
4527          * of bytes. When doing hardware scatter/gather, each entry cannot
4528          * be larger than 64 KiB though.
4529          */
4530         if (host->flags & SDHCI_USE_ADMA) {
4531                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
4532                         mmc->max_seg_size = 65535;
4533                 else
4534                         mmc->max_seg_size = 65536;
4535         } else {
4536                 mmc->max_seg_size = mmc->max_req_size;
4537         }
4538
4539         /*
4540          * Maximum block size. This varies from controller to controller and
4541          * is specified in the capabilities register.
4542          */
4543         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4544                 mmc->max_blk_size = 2;
4545         } else {
4546                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
4547                                 SDHCI_MAX_BLOCK_SHIFT;
4548                 if (mmc->max_blk_size >= 3) {
4549                         pr_info("%s: Invalid maximum block size, "
4550                                 "assuming 512 bytes\n", mmc_hostname(mmc));
4551                         mmc->max_blk_size = 0;
4552                 }
4553         }
4554
4555         mmc->max_blk_size = 512 << mmc->max_blk_size;
4556
4557         /*
4558          * Maximum block count.
4559          */
4560         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4561 #ifdef CONFIG_CMD_DUMP
4562         mmc->dbg_host_cnt = 0;
4563 #endif
4564
4565         /*
4566          * Init tasklets.
4567          */
4568         tasklet_init(&host->card_tasklet,
4569                 sdhci_tasklet_card, (unsigned long)host);
4570         tasklet_init(&host->finish_tasklet,
4571                 sdhci_tasklet_finish, (unsigned long)host);
4572         tasklet_init(&host->finish_cmd_tasklet,
4573                 sdhci_tasklet_cmd_finish, (unsigned long)host);
4574         tasklet_init(&host->finish_dat_tasklet,
4575                 sdhci_tasklet_dat_finish, (unsigned long)host);
4576
4577         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
4578
4579         if (host->version >= SDHCI_SPEC_300) {
4580                 init_waitqueue_head(&host->buf_ready_int);
4581
4582                 /* Initialize re-tuning timer */
4583                 init_timer(&host->tuning_timer);
4584                 host->tuning_timer.data = (unsigned long)host;
4585                 host->tuning_timer.function = sdhci_tuning_timer;
4586         }
4587
4588         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
4589                 mmc_hostname(mmc), host);
4590         if (ret) {
4591                 pr_err("%s: Failed to request IRQ %d: %d\n",
4592                        mmc_hostname(mmc), host->irq, ret);
4593                 goto untasklet;
4594         }
4595
4596         sdhci_init(host, 0);
4597
4598         host->sysedpc = sysedp_create_consumer(dev_name(mmc_dev(mmc)),
4599                                                dev_name(mmc_dev(mmc)));
4600
4601 #ifdef CONFIG_MMC_DEBUG
4602         sdhci_dumpregs(host);
4603 #endif
4604
4605 #ifdef SDHCI_USE_LEDS_CLASS
4606         snprintf(host->led_name, sizeof(host->led_name),
4607                 "%s::", mmc_hostname(mmc));
4608         host->led.name = host->led_name;
4609         host->led.brightness = LED_OFF;
4610         host->led.default_trigger = mmc_hostname(mmc);
4611         host->led.brightness_set = sdhci_led_control;
4612
4613         ret = led_classdev_register(mmc_dev(mmc), &host->led);
4614         if (ret) {
4615                 pr_err("%s: Failed to register LED device: %d\n",
4616                        mmc_hostname(mmc), ret);
4617                 goto reset;
4618         }
4619 #endif
4620
4621         mmiowb();
4622
4623         mmc_add_host(mmc);
4624
4625         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4626                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4627                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
4628                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4629
4630         sdhci_enable_card_detection(host);
4631
4632         pm_runtime_enable(mmc_dev(mmc));
4633         pm_runtime_use_autosuspend(mmc_dev(mmc));
4634         if (host->quirks2 & SDHCI_QUIRK2_MMC_RTPM) {
4635                 /*
4636                  * Below Autosuspend delay can be increased/decreased based on
4637                  * power and perf data
4638                  */
4639                 pm_runtime_set_autosuspend_delay(mmc_dev(mmc),
4640                         MMC_RTPM_MSEC_TMOUT);
4641         }
4642         host->runtime_pm_init_done = true;
4643
4644 #ifdef CONFIG_DEBUG_FS
4645         /* Add debugfs nodes */
4646         sdhci_debugfs_init(host);
4647 #endif
4648
4649         return 0;
4650
4651 #ifdef SDHCI_USE_LEDS_CLASS
4652 reset:
4653         sdhci_reset(host, SDHCI_RESET_ALL);
4654         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
4655         free_irq(host->irq, host);
4656 #endif
4657 untasklet:
4658         tasklet_kill(&host->card_tasklet);
4659         tasklet_kill(&host->finish_tasklet);
4660         tasklet_kill(&host->finish_cmd_tasklet);
4661         tasklet_kill(&host->finish_dat_tasklet);
4662
4663         return ret;
4664 }
4665
4666 EXPORT_SYMBOL_GPL(sdhci_add_host);
4667
4668 void sdhci_runtime_forbid(struct sdhci_host *host)
4669 {
4670         pm_runtime_forbid(mmc_dev(host->mmc));
4671 }
4672 EXPORT_SYMBOL_GPL(sdhci_runtime_forbid);
4673
4674 void sdhci_remove_host(struct sdhci_host *host, int dead)
4675 {
4676         unsigned long flags;
4677
4678         sdhci_runtime_pm_get(host);
4679         if (dead) {
4680                 spin_lock_irqsave(&host->lock, flags);
4681
4682                 host->flags |= SDHCI_DEVICE_DEAD;
4683
4684                 if (host->mrq_cmd || host->mrq_dat) {
4685                         pr_err("%s: Controller removed during "
4686                                 " transfer!\n", mmc_hostname(host->mmc));
4687
4688                         if (host->mrq_cmd) {
4689                                 host->mrq_cmd->cmd->error = -ENOMEDIUM;
4690                                 if (MMC_CHECK_CMDQ_MODE(host))
4691                                         tasklet_schedule(&host->finish_cmd_tasklet);
4692                                 else
4693                                         tasklet_schedule(&host->finish_tasklet);
4694                         }
4695                         if (host->mrq_dat) {
4696                                 host->mrq_dat->cmd->error = -ENOMEDIUM;
4697                                 if (MMC_CHECK_CMDQ_MODE(host))
4698                                         tasklet_schedule(&host->finish_dat_tasklet);
4699                                 else
4700                                         tasklet_schedule(&host->finish_tasklet);
4701                         }
4702                 }
4703
4704                 spin_unlock_irqrestore(&host->lock, flags);
4705         }
4706
4707         sdhci_disable_card_detection(host);
4708
4709         mmc_remove_host(host->mmc);
4710
4711 #ifdef SDHCI_USE_LEDS_CLASS
4712         led_classdev_unregister(&host->led);
4713 #endif
4714
4715         if (!dead)
4716                 sdhci_reset(host, SDHCI_RESET_ALL);
4717
4718         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
4719         free_irq(host->irq, host);
4720
4721         del_timer_sync(&host->timer);
4722
4723         tasklet_kill(&host->card_tasklet);
4724         tasklet_kill(&host->finish_tasklet);
4725         tasklet_kill(&host->finish_cmd_tasklet);
4726         tasklet_kill(&host->finish_dat_tasklet);
4727
4728         if (host->vmmc) {
4729                 regulator_disable(host->vmmc);
4730                 regulator_put(host->vmmc);
4731         }
4732
4733         if (host->vqmmc) {
4734                 regulator_disable(host->vqmmc);
4735                 regulator_put(host->vqmmc);
4736         }
4737
4738         if (host->use_dma_alloc) {
4739                 dma_free_coherent(mmc_dev(host->mmc), (128 * 2 + 1) * 8,
4740                                 host->adma_desc, host->adma_addr);
4741                 dma_free_coherent(mmc_dev(host->mmc), 128 * 8,
4742                                 host->align_buffer, host->align_addr);
4743         } else {
4744                 kfree(host->adma_desc);
4745                 kfree(host->align_buffer);
4746         }
4747
4748         host->adma_desc = NULL;
4749         host->align_buffer = NULL;
4750
4751         sdhci_runtime_pm_put(host);
4752         sysedp_free_consumer(host->sysedpc);
4753         host->sysedpc = NULL;
4754 }
4755
4756 EXPORT_SYMBOL_GPL(sdhci_remove_host);
4757
4758 void sdhci_free_host(struct sdhci_host *host)
4759 {
4760         mmc_free_host(host->mmc);
4761 }
4762
4763 EXPORT_SYMBOL_GPL(sdhci_free_host);
4764
4765 /*****************************************************************************\
4766  *                                                                           *
4767  * Driver init/exit                                                          *
4768  *                                                                           *
4769 \*****************************************************************************/
4770
4771 static int __init sdhci_drv_init(void)
4772 {
4773         pr_info(DRIVER_NAME
4774                 ": Secure Digital Host Controller Interface driver\n");
4775         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4776
4777         return 0;
4778 }
4779
4780 static void __exit sdhci_drv_exit(void)
4781 {
4782 }
4783
4784 module_init(sdhci_drv_init);
4785 module_exit(sdhci_drv_exit);
4786
4787 module_param(debug_quirks, uint, 0444);
4788 module_param(debug_quirks2, uint, 0444);
4789
4790 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4791 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4792 MODULE_LICENSE("GPL");
4793
4794 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4795 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");