2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 * Copyright (C) 2012-2013, NVIDIA CORPORATION. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or (at
10 * your option) any later version.
12 * Thanks to the following companies for their support:
14 * - JMicron (hardware and technical support)
17 #include <linux/delay.h>
18 #include <linux/highmem.h>
20 #include <linux/module.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/slab.h>
23 #include <linux/scatterlist.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/platform_device.h>
28 #include <linux/leds.h>
30 #include <linux/mmc/mmc.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/card.h>
33 #include <linux/mmc/slot-gpio.h>
35 #include <linux/edp.h>
36 #include <linux/sysedp.h>
38 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
39 #include <linux/tegra-soc.h>
44 #define DRIVER_NAME "sdhci"
46 #define DBG(f, x...) \
47 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
49 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
50 defined(CONFIG_MMC_SDHCI_MODULE))
51 #define SDHCI_USE_LEDS_CLASS
54 #define MAX_TUNING_LOOP 40
56 #define SDIO_CLK_GATING_TICK_TMOUT (HZ / 50)
58 #define IS_SDIO_CARD_OR_EMMC(host) \
60 ((host->mmc->card->type == MMC_TYPE_SDIO) || \
61 (host->mmc->card->type == MMC_TYPE_MMC)))
63 #define IS_DELAYED_CLK_GATE(host) \
64 ((host->quirks2 & SDHCI_QUIRK2_DELAYED_CLK_GATE) && \
65 (IS_SDIO_CARD_OR_EMMC(host)) && \
66 (host->mmc->caps2 & MMC_CAP2_CLOCK_GATING))
68 static unsigned int debug_quirks = 0;
69 static unsigned int debug_quirks2;
71 static void sdhci_finish_data(struct sdhci_host *);
73 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
74 static void sdhci_finish_command(struct sdhci_host *);
75 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
76 static void sdhci_tuning_timer(unsigned long data);
77 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
79 #ifdef CONFIG_PM_RUNTIME
80 static int sdhci_runtime_pm_get(struct sdhci_host *host);
81 static int sdhci_runtime_pm_put(struct sdhci_host *host);
83 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
87 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
93 static void sdhci_dumpregs(struct sdhci_host *host)
95 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
96 mmc_hostname(host->mmc));
98 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
99 sdhci_readl(host, SDHCI_DMA_ADDRESS),
100 sdhci_readw(host, SDHCI_HOST_VERSION));
101 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
102 sdhci_readw(host, SDHCI_BLOCK_SIZE),
103 sdhci_readw(host, SDHCI_BLOCK_COUNT));
104 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
105 sdhci_readl(host, SDHCI_ARGUMENT),
106 sdhci_readw(host, SDHCI_TRANSFER_MODE));
107 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
108 sdhci_readl(host, SDHCI_PRESENT_STATE),
109 sdhci_readb(host, SDHCI_HOST_CONTROL));
110 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
111 sdhci_readb(host, SDHCI_POWER_CONTROL),
112 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
113 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
114 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
115 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
116 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
117 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
118 sdhci_readl(host, SDHCI_INT_STATUS));
119 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
120 sdhci_readl(host, SDHCI_INT_ENABLE),
121 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
122 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
123 sdhci_readw(host, SDHCI_ACMD12_ERR),
124 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
125 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
126 sdhci_readl(host, SDHCI_CAPABILITIES),
127 sdhci_readl(host, SDHCI_CAPABILITIES_1));
128 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
129 sdhci_readw(host, SDHCI_COMMAND),
130 sdhci_readl(host, SDHCI_MAX_CURRENT));
131 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
132 sdhci_readw(host, SDHCI_HOST_CONTROL2));
134 if (host->flags & SDHCI_USE_ADMA)
135 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
136 readl(host->ioaddr + SDHCI_ADMA_ERROR),
137 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
139 pr_debug(DRIVER_NAME ": ===========================================\n");
142 /*****************************************************************************\
144 * Low level functions *
146 \*****************************************************************************/
148 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
152 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
155 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
156 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
159 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
161 sdhci_clear_set_irqs(host, 0, irqs);
164 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
166 sdhci_clear_set_irqs(host, irqs, 0);
169 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
173 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
174 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
177 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
179 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
182 sdhci_unmask_irqs(host, irqs);
184 sdhci_mask_irqs(host, irqs);
187 static void sdhci_enable_card_detection(struct sdhci_host *host)
189 sdhci_set_card_detection(host, true);
192 static void sdhci_disable_card_detection(struct sdhci_host *host)
194 sdhci_set_card_detection(host, false);
197 static void sdhci_reset(struct sdhci_host *host, u8 mask)
199 unsigned long timeout;
200 u32 uninitialized_var(ier);
202 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
203 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
208 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
209 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
211 if (host->ops->platform_reset_enter)
212 host->ops->platform_reset_enter(host, mask);
214 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
216 if (mask & SDHCI_RESET_ALL)
219 /* Wait max 100 ms */
222 /* hw clears the bit when it's done */
223 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
225 pr_err("%s: Reset 0x%x never completed.\n",
226 mmc_hostname(host->mmc), (int)mask);
227 sdhci_dumpregs(host);
234 if (host->ops->platform_reset_exit)
235 host->ops->platform_reset_exit(host, mask);
237 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
238 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
240 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
241 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
242 host->ops->enable_dma(host);
246 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
248 static void sdhci_init(struct sdhci_host *host, int soft)
251 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
253 sdhci_reset(host, SDHCI_RESET_ALL);
255 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
256 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
257 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
258 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
259 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
262 /* force clock reconfiguration */
264 sdhci_set_ios(host->mmc, &host->mmc->ios);
268 static void sdhci_reinit(struct sdhci_host *host)
272 * Retuning stuffs are affected by different cards inserted and only
273 * applicable to UHS-I cards. So reset these fields to their initial
274 * value when card is removed.
276 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
277 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
279 del_timer_sync(&host->tuning_timer);
280 host->flags &= ~SDHCI_NEEDS_RETUNING;
281 host->mmc->max_blk_count =
282 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
284 sdhci_enable_card_detection(host);
287 static void sdhci_activate_led(struct sdhci_host *host)
291 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
292 ctrl |= SDHCI_CTRL_LED;
293 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
296 static void sdhci_deactivate_led(struct sdhci_host *host)
300 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
301 ctrl &= ~SDHCI_CTRL_LED;
302 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
305 #ifdef SDHCI_USE_LEDS_CLASS
306 static void sdhci_led_control(struct led_classdev *led,
307 enum led_brightness brightness)
309 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
312 spin_lock_irqsave(&host->lock, flags);
314 if (host->runtime_suspended)
317 if (brightness == LED_OFF)
318 sdhci_deactivate_led(host);
320 sdhci_activate_led(host);
322 spin_unlock_irqrestore(&host->lock, flags);
326 /*****************************************************************************\
330 \*****************************************************************************/
332 static void sdhci_read_block_pio(struct sdhci_host *host)
335 size_t blksize, len, chunk;
336 u32 uninitialized_var(scratch);
339 DBG("PIO reading\n");
341 blksize = host->data->blksz;
344 local_irq_save(flags);
347 if (!sg_miter_next(&host->sg_miter))
350 len = min(host->sg_miter.length, blksize);
353 host->sg_miter.consumed = len;
355 buf = host->sg_miter.addr;
359 scratch = sdhci_readl(host, SDHCI_BUFFER);
363 *buf = scratch & 0xFF;
372 sg_miter_stop(&host->sg_miter);
374 local_irq_restore(flags);
377 static void sdhci_write_block_pio(struct sdhci_host *host)
380 size_t blksize, len, chunk;
384 DBG("PIO writing\n");
386 blksize = host->data->blksz;
390 local_irq_save(flags);
393 if (!sg_miter_next(&host->sg_miter))
396 len = min(host->sg_miter.length, blksize);
399 host->sg_miter.consumed = len;
401 buf = host->sg_miter.addr;
404 scratch |= (u32)*buf << (chunk * 8);
410 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
411 sdhci_writel(host, scratch, SDHCI_BUFFER);
418 sg_miter_stop(&host->sg_miter);
420 local_irq_restore(flags);
423 static void sdhci_transfer_pio(struct sdhci_host *host)
429 if (host->blocks == 0)
432 if (host->data->flags & MMC_DATA_READ)
433 mask = SDHCI_DATA_AVAILABLE;
435 mask = SDHCI_SPACE_AVAILABLE;
438 * Some controllers (JMicron JMB38x) mess up the buffer bits
439 * for transfers < 4 bytes. As long as it is just one block,
440 * we can ignore the bits.
442 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
443 (host->data->blocks == 1))
446 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
447 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
450 if (host->data->flags & MMC_DATA_READ)
451 sdhci_read_block_pio(host);
453 sdhci_write_block_pio(host);
456 if (host->blocks == 0)
460 DBG("PIO transfer complete.\n");
463 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
465 local_irq_save(*flags);
466 return kmap_atomic(sg_page(sg)) + sg->offset;
469 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
471 kunmap_atomic(buffer);
472 local_irq_restore(*flags);
475 static void sdhci_set_adma_desc(struct sdhci_host *host, u8 *desc, u32 addr,
476 int len, unsigned cmd)
478 __le32 *dataddr = (__le32 __force *)(desc + 4);
479 __le64 *dataddr64 = (__le64 __force *)(desc + 4);
480 __le16 *cmdlen = (__le16 __force *)desc;
483 /* SDHCI specification says ADMA descriptors should be 4 byte
484 * aligned, so using 16 or 32bit operations should be safe. */
486 cmdlen[0] = cpu_to_le16(cmd);
487 cmdlen[1] = cpu_to_le16(len);
489 ctrl = sdhci_readl(host, SDHCI_ACMD12_ERR);
490 if (ctrl & SDHCI_ADDRESSING_64BIT_EN)
491 dataddr64[0] = cpu_to_le64(addr);
493 dataddr[0] = cpu_to_le32(addr);
496 static int sdhci_adma_table_pre(struct sdhci_host *host,
497 struct mmc_data *data)
504 dma_addr_t align_addr;
507 struct scatterlist *sg;
515 * The spec does not specify endianness of descriptor table.
516 * We currently guess that it is LE.
519 if (data->flags & MMC_DATA_READ)
520 direction = DMA_FROM_DEVICE;
522 direction = DMA_TO_DEVICE;
525 * The ADMA descriptor table is mapped further down as we
526 * need to fill it with data first.
529 host->align_addr = dma_map_single(mmc_dev(host->mmc),
530 host->align_buffer, 128 * 4, direction);
531 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
533 BUG_ON(host->align_addr & 0x3);
535 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
536 data->sg, data->sg_len, direction);
537 if (host->sg_count == 0)
540 desc = host->adma_desc;
541 align = host->align_buffer;
543 align_addr = host->align_addr;
545 ctrl = sdhci_readl(host, SDHCI_ACMD12_ERR);
546 if (ctrl & SDHCI_ADDRESSING_64BIT_EN) {
547 if (ctrl & SDHCI_HOST_VERSION_4_EN)
552 /* 32 bit DMA mode supported */
556 for_each_sg(data->sg, sg, host->sg_count, i) {
557 addr = sg_dma_address(sg);
558 len = sg_dma_len(sg);
561 * The SDHCI specification states that ADMA
562 * addresses must be 32-bit aligned. If they
563 * aren't, then we use a bounce buffer for
564 * the (up to three) bytes that screw up the
567 offset = (4 - (addr & 0x3)) & 0x3;
569 if (data->flags & MMC_DATA_WRITE) {
570 buffer = sdhci_kmap_atomic(sg, &flags);
571 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
572 memcpy(align, buffer, offset);
573 sdhci_kunmap_atomic(buffer, &flags);
577 sdhci_set_adma_desc(host, desc, align_addr, offset,
580 BUG_ON(offset > 65536);
594 sdhci_set_adma_desc(host, desc, addr, len, 0x21);
598 * If this triggers then we have a calculation bug
601 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
604 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
606 * Mark the last descriptor as the terminating descriptor
608 if (desc != host->adma_desc) {
610 desc[0] |= 0x2; /* end */
614 * Add a terminating entry.
617 /* nop, end, valid */
618 sdhci_set_adma_desc(host, desc, 0, 0, 0x3);
622 * Resync align buffer as we might have changed it.
624 if (data->flags & MMC_DATA_WRITE) {
625 dma_sync_single_for_device(mmc_dev(host->mmc),
626 host->align_addr, 128 * 4, direction);
629 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
630 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
631 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
633 BUG_ON(host->adma_addr & 0x3);
638 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
639 data->sg_len, direction);
641 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
647 static void sdhci_adma_table_post(struct sdhci_host *host,
648 struct mmc_data *data)
652 struct scatterlist *sg;
658 if (data->flags & MMC_DATA_READ)
659 direction = DMA_FROM_DEVICE;
661 direction = DMA_TO_DEVICE;
663 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
664 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
666 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
669 if (data->flags & MMC_DATA_READ) {
670 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
671 data->sg_len, direction);
673 align = host->align_buffer;
675 for_each_sg(data->sg, sg, host->sg_count, i) {
676 if (sg_dma_address(sg) & 0x3) {
677 size = 4 - (sg_dma_address(sg) & 0x3);
679 buffer = sdhci_kmap_atomic(sg, &flags);
680 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
681 memcpy(buffer, align, size);
682 sdhci_kunmap_atomic(buffer, &flags);
689 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
690 data->sg_len, direction);
693 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
696 struct mmc_data *data = cmd->data;
697 unsigned target_timeout, current_timeout;
700 * If the host controller provides us with an incorrect timeout
701 * value, just skip the check and use 0xE. The hardware may take
702 * longer to time out, but that's much better than having a too-short
705 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
708 /* Unspecified timeout, assume max */
709 if (!data && !cmd->cmd_timeout_ms)
714 target_timeout = cmd->cmd_timeout_ms * 1000;
716 target_timeout = data->timeout_ns / 1000;
718 target_timeout += data->timeout_clks / host->clock;
722 * Figure out needed cycles.
723 * We do this in steps in order to fit inside a 32 bit int.
724 * The first step is the minimum timeout, which will have a
725 * minimum resolution of 6 bits:
726 * (1) 2^13*1000 > 2^22,
727 * (2) host->timeout_clk < 2^16
732 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
733 while (current_timeout < target_timeout) {
735 current_timeout <<= 1;
741 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
742 mmc_hostname(host->mmc), count, cmd->opcode);
749 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
751 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
752 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
754 if (host->flags & SDHCI_REQ_USE_DMA)
755 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
757 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
760 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
764 struct mmc_data *data = cmd->data;
769 if (data || (cmd->flags & MMC_RSP_BUSY)) {
770 count = sdhci_calc_timeout(host, cmd);
771 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
778 BUG_ON(data->blksz * data->blocks > 524288);
779 BUG_ON(data->blksz > host->mmc->max_blk_size);
780 BUG_ON(data->blocks > 65535);
783 host->data_early = 0;
784 host->data->bytes_xfered = 0;
786 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
787 host->flags |= SDHCI_REQ_USE_DMA;
790 * FIXME: This doesn't account for merging when mapping the
793 if (host->flags & SDHCI_REQ_USE_DMA) {
795 struct scatterlist *sg;
798 if (host->flags & SDHCI_USE_ADMA) {
799 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
802 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
806 if (unlikely(broken)) {
807 for_each_sg(data->sg, sg, data->sg_len, i) {
808 if (sg->length & 0x3) {
809 DBG("Reverting to PIO because of "
810 "transfer size (%d)\n",
812 host->flags &= ~SDHCI_REQ_USE_DMA;
820 * The assumption here being that alignment is the same after
821 * translation to device address space.
823 if (host->flags & SDHCI_REQ_USE_DMA) {
825 struct scatterlist *sg;
828 if (host->flags & SDHCI_USE_ADMA) {
830 * As we use 3 byte chunks to work around
831 * alignment problems, we need to check this
834 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
837 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
841 if (unlikely(broken)) {
842 for_each_sg(data->sg, sg, data->sg_len, i) {
843 if (sg->offset & 0x3) {
844 DBG("Reverting to PIO because of "
846 host->flags &= ~SDHCI_REQ_USE_DMA;
853 if (host->flags & SDHCI_REQ_USE_DMA) {
854 if (host->flags & SDHCI_USE_ADMA) {
855 ret = sdhci_adma_table_pre(host, data);
858 * This only happens when someone fed
859 * us an invalid request.
862 host->flags &= ~SDHCI_REQ_USE_DMA;
865 (host->adma_addr & 0xFFFFFFFF),
868 if ((host->version >= SDHCI_SPEC_400) &&
870 SDHCI_QUIRK2_SUPPORT_64BIT_DMA)) {
872 SDHCI_QUIRK2_USE_64BIT_ADDR) {
875 (host->adma_addr >> 32)
877 SDHCI_UPPER_ADMA_ADDRESS);
879 sdhci_writel(host, 0,
880 SDHCI_UPPER_ADMA_ADDRESS);
887 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
888 data->sg, data->sg_len,
889 (data->flags & MMC_DATA_READ) ?
894 * This only happens when someone fed
895 * us an invalid request.
898 host->flags &= ~SDHCI_REQ_USE_DMA;
900 WARN_ON(sg_cnt != 1);
901 sdhci_writel(host, sg_dma_address(data->sg),
908 * Always adjust the DMA selection as some controllers
909 * (e.g. JMicron) can't do PIO properly when the selection
912 if (host->version >= SDHCI_SPEC_200) {
913 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
914 ctrl &= ~SDHCI_CTRL_DMA_MASK;
915 if ((host->flags & SDHCI_REQ_USE_DMA) &&
916 (host->flags & SDHCI_USE_ADMA))
917 ctrl |= SDHCI_CTRL_ADMA2;
919 ctrl |= SDHCI_CTRL_SDMA;
920 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
923 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
926 flags = SG_MITER_ATOMIC;
927 if (host->data->flags & MMC_DATA_READ)
928 flags |= SG_MITER_TO_SG;
930 flags |= SG_MITER_FROM_SG;
931 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
932 host->blocks = data->blocks;
935 sdhci_set_transfer_irqs(host);
937 /* Set the DMA boundary value and block size */
938 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
939 data->blksz), SDHCI_BLOCK_SIZE);
940 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
943 static void sdhci_set_transfer_mode(struct sdhci_host *host,
944 struct mmc_command *cmd)
947 struct mmc_data *data = cmd->data;
952 WARN_ON(!host->data);
954 mode = SDHCI_TRNS_BLK_CNT_EN;
955 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
956 mode |= SDHCI_TRNS_MULTI;
958 * If we are sending CMD23, CMD12 never gets sent
959 * on successful completion (so no Auto-CMD12).
961 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
962 mmc_op_multi(cmd->opcode))
963 mode |= SDHCI_TRNS_AUTO_CMD12;
964 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
965 mode |= SDHCI_TRNS_AUTO_CMD23;
966 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
970 if (data->flags & MMC_DATA_READ)
971 mode |= SDHCI_TRNS_READ;
972 if (host->flags & SDHCI_REQ_USE_DMA)
973 mode |= SDHCI_TRNS_DMA;
975 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
978 static void sdhci_finish_data(struct sdhci_host *host)
980 struct mmc_data *data;
987 if (host->flags & SDHCI_REQ_USE_DMA) {
988 if (host->flags & SDHCI_USE_ADMA)
989 sdhci_adma_table_post(host, data);
991 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
992 data->sg_len, (data->flags & MMC_DATA_READ) ?
993 DMA_FROM_DEVICE : DMA_TO_DEVICE);
998 * The specification states that the block count register must
999 * be updated, but it does not specify at what point in the
1000 * data flow. That makes the register entirely useless to read
1001 * back so we have to assume that nothing made it to the card
1002 * in the event of an error.
1005 data->bytes_xfered = 0;
1007 data->bytes_xfered = data->blksz * data->blocks;
1010 * Need to send CMD12 if -
1011 * a) open-ended multiblock transfer (no CMD23)
1012 * b) error in multiblock transfer
1019 * The controller needs a reset of internal state machines
1020 * upon error conditions.
1023 sdhci_reset(host, SDHCI_RESET_CMD);
1024 sdhci_reset(host, SDHCI_RESET_DATA);
1027 sdhci_send_command(host, data->stop);
1029 tasklet_schedule(&host->finish_tasklet);
1032 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1036 unsigned long timeout;
1040 /* Wait max 10 ms */
1043 mask = SDHCI_CMD_INHIBIT;
1044 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1045 mask |= SDHCI_DATA_INHIBIT;
1047 /* We shouldn't wait for data inihibit for stop commands, even
1048 though they might use busy signaling */
1049 if (host->mrq->data && (cmd == host->mrq->data->stop))
1050 mask &= ~SDHCI_DATA_INHIBIT;
1052 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1054 pr_err("%s: Controller never released "
1055 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1056 sdhci_dumpregs(host);
1058 tasklet_schedule(&host->finish_tasklet);
1065 mod_timer(&host->timer, jiffies + 10 * HZ);
1069 sdhci_prepare_data(host, cmd);
1071 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1073 sdhci_set_transfer_mode(host, cmd);
1075 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1076 pr_err("%s: Unsupported response type!\n",
1077 mmc_hostname(host->mmc));
1078 cmd->error = -EINVAL;
1079 tasklet_schedule(&host->finish_tasklet);
1083 if (!(cmd->flags & MMC_RSP_PRESENT))
1084 flags = SDHCI_CMD_RESP_NONE;
1085 else if (cmd->flags & MMC_RSP_136)
1086 flags = SDHCI_CMD_RESP_LONG;
1087 else if (cmd->flags & MMC_RSP_BUSY)
1088 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1090 flags = SDHCI_CMD_RESP_SHORT;
1092 if (cmd->flags & MMC_RSP_CRC)
1093 flags |= SDHCI_CMD_CRC;
1094 if (cmd->flags & MMC_RSP_OPCODE)
1095 flags |= SDHCI_CMD_INDEX;
1097 /* CMD19, CMD21 is special in that the Data Present Select should be set */
1098 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1099 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1100 flags |= SDHCI_CMD_DATA;
1102 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1105 static void sdhci_finish_command(struct sdhci_host *host)
1109 BUG_ON(host->cmd == NULL);
1111 if (host->cmd->flags & MMC_RSP_PRESENT) {
1112 if (host->cmd->flags & MMC_RSP_136) {
1113 /* CRC is stripped so we need to do some shifting. */
1114 for (i = 0;i < 4;i++) {
1115 host->cmd->resp[i] = sdhci_readl(host,
1116 SDHCI_RESPONSE + (3-i)*4) << 8;
1118 host->cmd->resp[i] |=
1120 SDHCI_RESPONSE + (3-i)*4-1);
1123 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1127 host->cmd->error = 0;
1129 /* Finished CMD23, now send actual command. */
1130 if (host->cmd == host->mrq->sbc) {
1132 sdhci_send_command(host, host->mrq->cmd);
1135 /* Processed actual command. */
1136 if (host->data && host->data_early)
1137 sdhci_finish_data(host);
1139 if (!host->cmd->data)
1140 tasklet_schedule(&host->finish_tasklet);
1146 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1148 u16 ctrl, preset = 0;
1150 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1152 switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1153 case SDHCI_CTRL_UHS_SDR12:
1154 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1156 case SDHCI_CTRL_UHS_SDR25:
1157 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1159 case SDHCI_CTRL_UHS_SDR50:
1160 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1162 case SDHCI_CTRL_UHS_SDR104:
1163 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1165 case SDHCI_CTRL_UHS_DDR50:
1166 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1169 pr_warn("%s: Invalid UHS-I mode selected\n",
1170 mmc_hostname(host->mmc));
1171 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1177 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1179 int div = 0; /* Initialized for compiler warning */
1180 int real_div = div, clk_mul = 1;
1182 unsigned long timeout;
1185 if (clock && clock == host->clock)
1188 host->mmc->actual_clock = 0;
1190 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1194 * If the entire clock control register is updated with zero, some
1195 * controllers might first update clock divisor fields and then update
1196 * the INT_CLK_EN and CARD_CLK_EN fields. Disable card clock first
1197 * to ensure there is no abnormal clock behavior.
1199 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1200 clk &= ~SDHCI_CLOCK_CARD_EN;
1201 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1203 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1208 if (host->version >= SDHCI_SPEC_300) {
1209 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1210 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1213 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1214 pre_val = sdhci_get_preset_value(host);
1215 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1216 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1217 if (host->clk_mul &&
1218 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1219 clk = SDHCI_PROG_CLOCK_MODE;
1221 clk_mul = host->clk_mul;
1223 real_div = max_t(int, 1, div << 1);
1229 * Check if the Host Controller supports Programmable Clock
1232 if (host->clk_mul) {
1233 for (div = 1; div <= 1024; div++) {
1234 if ((host->max_clk * host->clk_mul / div)
1239 * Set Programmable Clock Mode in the Clock
1242 clk = SDHCI_PROG_CLOCK_MODE;
1244 clk_mul = host->clk_mul;
1247 /* Version 3.00 divisors must be a multiple of 2. */
1248 if (host->max_clk <= clock) {
1249 if (host->mmc->ios.timing ==
1250 MMC_TIMING_UHS_DDR50)
1255 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1257 if ((host->max_clk / div) <= clock)
1265 /* Version 2.00 divisors must be a power of 2. */
1266 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1267 if ((host->max_clk / div) <= clock)
1276 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1278 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
1279 if (tegra_platform_is_fpga() && clock > 400000)
1282 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1283 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1284 << SDHCI_DIVIDER_HI_SHIFT;
1285 clk |= SDHCI_CLOCK_INT_EN;
1286 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1289 * For Tegra3 sdmmc controller, internal clock will not be stable bit
1290 * will get set only after some other register write is done. To
1291 * handle, do a dummy reg write to the caps reg if
1292 * SDHCI_QUIRK2_INT_CLK_STABLE_REQ_DUMMY_REG_WRITE is set.
1294 if (host->quirks2 & SDHCI_QUIRK2_INT_CLK_STABLE_REQ_DUMMY_REG_WRITE) {
1297 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
1299 sdhci_writel(host, caps, SDHCI_CAPABILITIES);
1302 /* Wait max 20 ms */
1304 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1305 & SDHCI_CLOCK_INT_STABLE)) {
1307 pr_err("%s: Internal clock never "
1308 "stabilised.\n", mmc_hostname(host->mmc));
1309 sdhci_dumpregs(host);
1316 clk |= SDHCI_CLOCK_CARD_EN;
1317 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1320 host->clock = clock;
1323 static inline void sdhci_update_clock(struct sdhci_host *host)
1327 clock = host->clock;
1329 if (host->ops->set_clock)
1330 host->ops->set_clock(host, clock);
1331 sdhci_set_clock(host, clock);
1334 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1338 if (power != (unsigned short)-1) {
1339 switch (1 << power) {
1340 case MMC_VDD_165_195:
1341 pwr = SDHCI_POWER_180;
1345 pwr = SDHCI_POWER_300;
1349 pwr = SDHCI_POWER_330;
1356 if (host->pwr == pwr)
1362 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1367 * Spec says that we should clear the power reg before setting
1368 * a new value. Some controllers don't seem to like this though.
1370 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1371 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1374 * At least the Marvell CaFe chip gets confused if we set the voltage
1375 * and set turn on power at the same time, so set the voltage first.
1377 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1378 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1380 pwr |= SDHCI_POWER_ON;
1382 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1385 * Some controllers need an extra 10ms delay of 10ms before they
1386 * can apply clock after applying power
1388 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1394 /*****************************************************************************\
1398 \*****************************************************************************/
1400 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1402 struct sdhci_host *host;
1404 unsigned long flags;
1407 host = mmc_priv(mmc);
1409 sdhci_runtime_pm_get(host);
1411 spin_lock_irqsave(&host->lock, flags);
1413 WARN_ON(host->mrq != NULL);
1415 #ifndef SDHCI_USE_LEDS_CLASS
1416 sdhci_activate_led(host);
1420 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1421 * requests if Auto-CMD12 is enabled.
1423 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1425 mrq->data->stop = NULL;
1433 * Firstly check card presence from cd-gpio. The return could
1434 * be one of the following possibilities:
1435 * negative: cd-gpio is not available
1436 * zero: cd-gpio is used, and card is removed
1437 * one: cd-gpio is used, and card is present
1439 present = mmc_gpio_get_cd(host->mmc);
1441 /* If polling, assume that the card is always present. */
1442 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1443 if (host->ops->get_cd)
1444 present = host->ops->get_cd(host);
1448 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1452 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1453 host->mrq->cmd->error = -ENOMEDIUM;
1454 tasklet_schedule(&host->finish_tasklet);
1458 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1460 * Check if the re-tuning timer has already expired and there
1461 * is no on-going data transfer. If so, we need to execute
1462 * tuning procedure before sending command.
1464 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1465 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1467 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1469 mmc->card->type == MMC_TYPE_MMC ?
1470 MMC_SEND_TUNING_BLOCK_HS200 :
1471 MMC_SEND_TUNING_BLOCK;
1472 spin_unlock_irqrestore(&host->lock, flags);
1473 sdhci_execute_tuning(mmc, tuning_opcode);
1474 spin_lock_irqsave(&host->lock, flags);
1476 /* Restore original mmc_request structure */
1481 /* For a data cmd, check for plat specific preparation */
1482 spin_unlock_irqrestore(&host->lock, flags);
1484 host->ops->platform_get_bus(host);
1485 spin_lock_irqsave(&host->lock, flags);
1487 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1488 sdhci_send_command(host, mrq->sbc);
1490 sdhci_send_command(host, mrq->cmd);
1494 spin_unlock_irqrestore(&host->lock, flags);
1497 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1499 unsigned long flags;
1503 /* Do any required preparations prior to setting ios */
1504 if (host->ops->platform_ios_config_enter)
1505 host->ops->platform_ios_config_enter(host, ios);
1507 spin_lock_irqsave(&host->lock, flags);
1509 if (host->flags & SDHCI_DEVICE_DEAD) {
1510 spin_unlock_irqrestore(&host->lock, flags);
1511 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1512 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1517 * Reset the chip on each power off.
1518 * Should clear out any weird states.
1520 if (ios->power_mode == MMC_POWER_OFF) {
1521 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1525 if (host->version >= SDHCI_SPEC_300 &&
1526 (ios->power_mode == MMC_POWER_UP))
1527 sdhci_enable_preset_value(host, false);
1529 if (ios->power_mode == MMC_POWER_OFF)
1530 vdd_bit = sdhci_set_power(host, -1);
1532 vdd_bit = sdhci_set_power(host, ios->vdd);
1534 if (host->vmmc && vdd_bit != -1) {
1535 spin_unlock_irqrestore(&host->lock, flags);
1536 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1537 spin_lock_irqsave(&host->lock, flags);
1540 sdhci_set_clock(host, ios->clock);
1542 if (host->ops->platform_send_init_74_clocks)
1543 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1546 * If your platform has 8-bit width support but is not a v3 controller,
1547 * or if it requires special setup code, you should implement that in
1548 * platform_bus_width().
1550 if (host->ops->platform_bus_width) {
1551 host->ops->platform_bus_width(host, ios->bus_width);
1553 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1554 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1555 ctrl &= ~SDHCI_CTRL_4BITBUS;
1556 if (host->version >= SDHCI_SPEC_300)
1557 ctrl |= SDHCI_CTRL_8BITBUS;
1559 if (host->version >= SDHCI_SPEC_300)
1560 ctrl &= ~SDHCI_CTRL_8BITBUS;
1561 if (ios->bus_width == MMC_BUS_WIDTH_4)
1562 ctrl |= SDHCI_CTRL_4BITBUS;
1564 ctrl &= ~SDHCI_CTRL_4BITBUS;
1566 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1569 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1571 if ((ios->timing == MMC_TIMING_SD_HS ||
1572 ios->timing == MMC_TIMING_MMC_HS)
1573 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1574 ctrl |= SDHCI_CTRL_HISPD;
1576 ctrl &= ~SDHCI_CTRL_HISPD;
1578 if (host->version >= SDHCI_SPEC_300) {
1581 /* In case of UHS-I modes, set High Speed Enable */
1582 if (((ios->timing == MMC_TIMING_MMC_HS200) ||
1583 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1584 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1585 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1586 (ios->timing == MMC_TIMING_UHS_SDR25))
1587 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1588 ctrl |= SDHCI_CTRL_HISPD;
1590 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1591 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1592 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1594 * We only need to set Driver Strength if the
1595 * preset value enable is not set.
1597 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1598 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1599 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1600 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1601 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1603 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1606 * According to SDHC Spec v3.00, if the Preset Value
1607 * Enable in the Host Control 2 register is set, we
1608 * need to reset SD Clock Enable before changing High
1609 * Speed Enable to avoid generating clock gliches.
1612 /* Reset SD Clock Enable */
1613 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1614 clk &= ~SDHCI_CLOCK_CARD_EN;
1615 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1617 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1619 /* Re-enable SD Clock */
1620 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1621 clk |= SDHCI_CLOCK_CARD_EN;
1622 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1626 /* Reset SD Clock Enable */
1627 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1628 clk &= ~SDHCI_CLOCK_CARD_EN;
1629 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1631 if (host->ops->set_uhs_signaling)
1632 host->ops->set_uhs_signaling(host, ios->timing);
1634 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1635 /* Select Bus Speed Mode for host */
1636 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1637 if (ios->timing == MMC_TIMING_MMC_HS200)
1638 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1639 else if (ios->timing == MMC_TIMING_UHS_SDR12)
1640 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1641 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1642 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1643 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1644 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1645 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1646 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1647 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1648 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1649 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1652 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1653 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1654 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1655 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1656 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1657 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1660 sdhci_enable_preset_value(host, true);
1661 preset = sdhci_get_preset_value(host);
1662 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1663 >> SDHCI_PRESET_DRV_SHIFT;
1666 /* Re-enable SD Clock */
1667 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1668 clk |= SDHCI_CLOCK_CARD_EN;
1669 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1671 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1674 * Some (ENE) controllers go apeshit on some ios operation,
1675 * signalling timeout and CRC errors even on CMD0. Resetting
1676 * it on each ios seems to solve the problem.
1678 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1679 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1682 spin_unlock_irqrestore(&host->lock, flags);
1684 /* Platform specific handling post ios setting */
1685 if (host->ops->platform_ios_config_exit)
1686 host->ops->platform_ios_config_exit(host, ios);
1690 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1692 struct sdhci_host *host = mmc_priv(mmc);
1694 sdhci_runtime_pm_get(host);
1695 sdhci_do_set_ios(host, ios);
1696 sdhci_runtime_pm_put(host);
1699 static int sdhci_do_get_cd(struct sdhci_host *host)
1701 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1703 if (host->flags & SDHCI_DEVICE_DEAD)
1706 /* If polling/nonremovable, assume that the card is always present. */
1707 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1708 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1711 /* Try slot gpio detect */
1712 if (!IS_ERR_VALUE(gpio_cd))
1715 /* Host native card detect */
1716 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1719 static int sdhci_get_cd(struct mmc_host *mmc)
1721 struct sdhci_host *host = mmc_priv(mmc);
1724 sdhci_runtime_pm_get(host);
1725 ret = sdhci_do_get_cd(host);
1726 sdhci_runtime_pm_put(host);
1730 static int sdhci_check_ro(struct sdhci_host *host)
1732 unsigned long flags;
1735 spin_lock_irqsave(&host->lock, flags);
1737 if (host->flags & SDHCI_DEVICE_DEAD)
1739 else if (host->ops->get_ro)
1740 is_readonly = host->ops->get_ro(host);
1742 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1743 & SDHCI_WRITE_PROTECT);
1745 spin_unlock_irqrestore(&host->lock, flags);
1747 /* This quirk needs to be replaced by a callback-function later */
1748 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1749 !is_readonly : is_readonly;
1752 #define SAMPLE_COUNT 5
1754 static int sdhci_do_get_ro(struct sdhci_host *host)
1758 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1759 return sdhci_check_ro(host);
1762 for (i = 0; i < SAMPLE_COUNT; i++) {
1763 if (sdhci_check_ro(host)) {
1764 if (++ro_count > SAMPLE_COUNT / 2)
1772 static void sdhci_hw_reset(struct mmc_host *mmc)
1774 struct sdhci_host *host = mmc_priv(mmc);
1776 if (host->ops && host->ops->hw_reset)
1777 host->ops->hw_reset(host);
1780 static int sdhci_get_ro(struct mmc_host *mmc)
1782 struct sdhci_host *host = mmc_priv(mmc);
1785 sdhci_runtime_pm_get(host);
1786 ret = sdhci_do_get_ro(host);
1787 sdhci_runtime_pm_put(host);
1791 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1793 if (host->flags & SDHCI_DEVICE_DEAD)
1797 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1799 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1801 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1802 if (host->runtime_suspended)
1806 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1808 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1813 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1815 struct sdhci_host *host = mmc_priv(mmc);
1816 unsigned long flags;
1818 spin_lock_irqsave(&host->lock, flags);
1819 sdhci_enable_sdio_irq_nolock(host, enable);
1820 spin_unlock_irqrestore(&host->lock, flags);
1823 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1824 struct mmc_ios *ios)
1830 * Signal Voltage Switching is only applicable for Host Controllers
1833 if (host->version < SDHCI_SPEC_300)
1836 if (host->quirks2 & SDHCI_QUIRK2_NON_STD_VOLTAGE_SWITCHING) {
1837 if (host->ops->switch_signal_voltage)
1838 return host->ops->switch_signal_voltage(
1839 host, ios->signal_voltage);
1842 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1844 switch (ios->signal_voltage) {
1845 case MMC_SIGNAL_VOLTAGE_330:
1846 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1847 ctrl &= ~SDHCI_CTRL_VDD_180;
1848 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1851 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1853 pr_warning("%s: Switching to 3.3V signalling voltage "
1854 " failed\n", mmc_hostname(host->mmc));
1859 usleep_range(5000, 5500);
1861 /* 3.3V regulator output should be stable within 5 ms */
1862 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1863 if (!(ctrl & SDHCI_CTRL_VDD_180))
1866 pr_warning("%s: 3.3V regulator output did not became stable\n",
1867 mmc_hostname(host->mmc));
1870 case MMC_SIGNAL_VOLTAGE_180:
1872 ret = regulator_set_voltage(host->vqmmc,
1875 pr_warning("%s: Switching to 1.8V signalling voltage "
1876 " failed\n", mmc_hostname(host->mmc));
1882 * Enable 1.8V Signal Enable in the Host Control2
1885 ctrl |= SDHCI_CTRL_VDD_180;
1886 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1889 usleep_range(5000, 5500);
1891 /* 1.8V regulator output should be stable within 5 ms */
1892 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1893 if (ctrl & SDHCI_CTRL_VDD_180)
1896 pr_warning("%s: 1.8V regulator output did not became stable\n",
1897 mmc_hostname(host->mmc));
1900 case MMC_SIGNAL_VOLTAGE_120:
1902 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1904 pr_warning("%s: Switching to 1.2V signalling voltage "
1905 " failed\n", mmc_hostname(host->mmc));
1911 /* No signal voltage switch required */
1916 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1917 struct mmc_ios *ios)
1919 struct sdhci_host *host = mmc_priv(mmc);
1922 if (host->version < SDHCI_SPEC_300)
1924 sdhci_runtime_pm_get(host);
1925 err = sdhci_do_start_signal_voltage_switch(host, ios);
1926 /* Do any post voltage switch platform specific configuration */
1927 if (host->ops->switch_signal_voltage_exit)
1928 host->ops->switch_signal_voltage_exit(host);
1929 sdhci_runtime_pm_put(host);
1933 static int sdhci_card_busy(struct mmc_host *mmc)
1935 struct sdhci_host *host = mmc_priv(mmc);
1938 sdhci_runtime_pm_get(host);
1939 /* Check whether DAT[3:0] is 0000 */
1940 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1941 sdhci_runtime_pm_put(host);
1943 return !(present_state & SDHCI_DATA_LVL_MASK);
1946 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1948 struct sdhci_host *host;
1951 int tuning_loop_counter = MAX_TUNING_LOOP;
1952 unsigned long timeout;
1954 bool requires_tuning_nonuhs = false;
1956 host = mmc_priv(mmc);
1958 sdhci_runtime_pm_get(host);
1959 disable_irq(host->irq);
1961 if ((host->quirks2 & SDHCI_QUIRK2_NON_STANDARD_TUNING) &&
1962 host->ops->execute_freq_tuning) {
1963 err = host->ops->execute_freq_tuning(host, opcode);
1964 enable_irq(host->irq);
1965 sdhci_runtime_pm_put(host);
1969 spin_lock(&host->lock);
1970 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1973 * The Host Controller needs tuning only in case of SDR104 mode
1974 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1975 * Capabilities register.
1976 * If the Host Controller supports the HS200 mode then the
1977 * tuning function has to be executed.
1979 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1980 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1981 host->flags & SDHCI_HS200_NEEDS_TUNING))
1982 requires_tuning_nonuhs = true;
1984 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1985 requires_tuning_nonuhs)
1986 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1988 spin_unlock(&host->lock);
1989 enable_irq(host->irq);
1990 sdhci_runtime_pm_put(host);
1994 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1997 * As per the Host Controller spec v3.00, tuning command
1998 * generates Buffer Read Ready interrupt, so enable that.
2000 * Note: The spec clearly says that when tuning sequence
2001 * is being performed, the controller does not generate
2002 * interrupts other than Buffer Read Ready interrupt. But
2003 * to make sure we don't hit a controller bug, we _only_
2004 * enable Buffer Read Ready interrupt here.
2006 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
2007 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
2010 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
2011 * of loops reaches 40 times or a timeout of 150ms occurs.
2015 struct mmc_command cmd = {0};
2016 struct mmc_request mrq = {NULL};
2018 if (!tuning_loop_counter && !timeout)
2021 cmd.opcode = opcode;
2023 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2032 * In response to CMD19, the card sends 64 bytes of tuning
2033 * block to the Host Controller. So we set the block size
2035 * In response to CMD21, the card sends 128 bytes of tuning
2036 * block for MMC_BUS_WIDTH_8 and 64 bytes for MMC_BUS_WIDTH_4
2037 * to the Host Controller. So we set the block size to 64 here.
2039 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2040 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2041 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2043 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2044 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2047 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2052 * The tuning block is sent by the card to the host controller.
2053 * So we set the TRNS_READ bit in the Transfer Mode register.
2054 * This also takes care of setting DMA Enable and Multi Block
2055 * Select in the same register to 0.
2057 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2059 sdhci_send_command(host, &cmd);
2064 spin_unlock(&host->lock);
2065 enable_irq(host->irq);
2067 /* Wait for Buffer Read Ready interrupt */
2068 wait_event_interruptible_timeout(host->buf_ready_int,
2069 (host->tuning_done == 1),
2070 msecs_to_jiffies(50));
2071 disable_irq(host->irq);
2072 spin_lock(&host->lock);
2074 if (!host->tuning_done) {
2075 pr_info(DRIVER_NAME ": Timeout waiting for "
2076 "Buffer Read Ready interrupt during tuning "
2077 "procedure, falling back to fixed sampling "
2079 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2080 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2081 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2082 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2088 host->tuning_done = 0;
2090 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2091 tuning_loop_counter--;
2094 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2097 * The Host Driver has exhausted the maximum number of loops allowed,
2098 * so use fixed sampling frequency.
2100 if (!tuning_loop_counter || !timeout) {
2101 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2102 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2104 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2105 pr_info(DRIVER_NAME ": Tuning procedure"
2106 " failed, falling back to fixed sampling"
2114 * If this is the very first time we are here, we start the retuning
2115 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2116 * flag won't be set, we check this condition before actually starting
2119 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2120 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
2121 host->flags |= SDHCI_USING_RETUNING_TIMER;
2122 mod_timer(&host->tuning_timer, jiffies +
2123 host->tuning_count * HZ);
2124 /* Tuning mode 1 limits the maximum data length to 4MB */
2125 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2127 host->flags &= ~SDHCI_NEEDS_RETUNING;
2128 /* Reload the new initial value for timer */
2129 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2130 mod_timer(&host->tuning_timer, jiffies +
2131 host->tuning_count * HZ);
2135 * In case tuning fails, host controllers which support re-tuning can
2136 * try tuning again at a later time, when the re-tuning timer expires.
2137 * So for these controllers, we return 0. Since there might be other
2138 * controllers who do not have this capability, we return error for
2139 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2140 * a retuning timer to do the retuning for the card.
2142 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2145 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
2146 spin_unlock(&host->lock);
2147 enable_irq(host->irq);
2148 sdhci_runtime_pm_put(host);
2154 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2158 /* Host Controller v3.00 defines preset value registers */
2159 if (host->version < SDHCI_SPEC_300)
2162 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2165 * We only enable or disable Preset Value if they are not already
2166 * enabled or disabled respectively. Otherwise, we bail out.
2168 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2169 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2170 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2171 host->flags |= SDHCI_PV_ENABLED;
2172 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2173 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2174 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2175 host->flags &= ~SDHCI_PV_ENABLED;
2179 static void sdhci_card_event(struct mmc_host *mmc)
2181 struct sdhci_host *host = mmc_priv(mmc);
2182 unsigned long flags;
2184 spin_lock_irqsave(&host->lock, flags);
2186 /* Check host->mrq first in case we are runtime suspended */
2188 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
2189 pr_err("%s: Card removed during transfer!\n",
2190 mmc_hostname(host->mmc));
2191 pr_err("%s: Resetting controller.\n",
2192 mmc_hostname(host->mmc));
2194 sdhci_reset(host, SDHCI_RESET_CMD);
2195 sdhci_reset(host, SDHCI_RESET_DATA);
2197 host->mrq->cmd->error = -ENOMEDIUM;
2198 tasklet_schedule(&host->finish_tasklet);
2201 spin_unlock_irqrestore(&host->lock, flags);
2204 int sdhci_enable(struct mmc_host *mmc)
2206 struct sdhci_host *host = mmc_priv(mmc);
2207 unsigned int approved;
2209 struct platform_device *pdev = to_platform_device(mmc_dev(mmc));
2211 if (!mmc->card || !(mmc->caps2 & MMC_CAP2_CLOCK_GATING))
2214 if (IS_DELAYED_CLK_GATE(host)) {
2215 /* cancel sdio clk gate work */
2216 cancel_delayed_work_sync(&host->delayed_clk_gate_wrk);
2219 sysedp_set_state(host->sysedpc, 1);
2221 if (mmc->ios.clock) {
2222 if (host->ops->set_clock)
2223 host->ops->set_clock(host, mmc->ios.clock);
2224 sdhci_set_clock(host, mmc->ios.clock);
2227 if (host->sd_edp_client) {
2228 ret = edp_update_client_request(host->sd_edp_client,
2229 SD_EDP_HIGH, &approved);
2231 dev_err(&pdev->dev, "Unable to set SD_EDP_HIGH state\n");
2237 static void mmc_host_clk_gate(struct sdhci_host *host)
2240 struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
2242 sdhci_set_clock(host, 0);
2243 if (host->ops->set_clock)
2244 host->ops->set_clock(host, 0);
2246 sysedp_set_state(host->sysedpc, 0);
2248 if (host->sd_edp_client) {
2249 ret = edp_update_client_request(host->sd_edp_client,
2252 dev_err(&pdev->dev, "Unable to set SD_EDP_LOW state\n");
2257 void delayed_clk_gate_cb(struct work_struct *work)
2259 struct sdhci_host *host = container_of(work, struct sdhci_host,
2260 delayed_clk_gate_wrk.work);
2261 struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
2263 /* power off check */
2264 if (host->mmc->ios.power_mode == MMC_POWER_OFF)
2267 mmc_host_clk_gate(host);
2271 EXPORT_SYMBOL_GPL(delayed_clk_gate_cb);
2273 int sdhci_disable(struct mmc_host *mmc)
2275 struct sdhci_host *host = mmc_priv(mmc);
2277 if (!mmc->card || !(mmc->caps2 & MMC_CAP2_CLOCK_GATING))
2280 if (IS_DELAYED_CLK_GATE(host)) {
2281 if (host->is_clk_on)
2282 schedule_delayed_work(&host->delayed_clk_gate_wrk,
2283 SDIO_CLK_GATING_TICK_TMOUT);
2287 mmc_host_clk_gate(host);
2292 #ifdef CONFIG_MMC_FREQ_SCALING
2294 * Wrapper functions to call any platform specific implementation for
2295 * supporting dynamic frequency scaling for SD/MMC devices.
2297 static int sdhci_gov_get_target(struct mmc_host *mmc, unsigned long *freq)
2299 struct sdhci_host *host = mmc_priv(mmc);
2301 if (host->ops->dfs_gov_get_target_freq)
2302 *freq = host->ops->dfs_gov_get_target_freq(host,
2303 mmc->devfreq_stats);
2308 static int sdhci_gov_init(struct mmc_host *mmc)
2310 struct sdhci_host *host = mmc_priv(mmc);
2312 if (host->ops->dfs_gov_init)
2313 return host->ops->dfs_gov_init(host);
2318 static void sdhci_gov_exit(struct mmc_host *mmc)
2320 struct sdhci_host *host = mmc_priv(mmc);
2322 if (host->ops->dfs_gov_exit)
2323 host->ops->dfs_gov_exit(host);
2326 static const struct mmc_host_ops sdhci_ops = {
2327 .request = sdhci_request,
2328 .set_ios = sdhci_set_ios,
2329 .get_cd = sdhci_get_cd,
2330 .get_ro = sdhci_get_ro,
2331 .hw_reset = sdhci_hw_reset,
2332 .enable = sdhci_enable,
2333 .disable = sdhci_disable,
2334 .enable_sdio_irq = sdhci_enable_sdio_irq,
2335 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2336 .execute_tuning = sdhci_execute_tuning,
2337 .card_event = sdhci_card_event,
2338 .card_busy = sdhci_card_busy,
2339 #ifdef CONFIG_MMC_FREQ_SCALING
2340 .dfs_governor_init = sdhci_gov_init,
2341 .dfs_governor_exit = sdhci_gov_exit,
2342 .dfs_governor_get_target = sdhci_gov_get_target,
2346 /*****************************************************************************\
2350 \*****************************************************************************/
2352 static void sdhci_tasklet_card(unsigned long param)
2354 struct sdhci_host *host = (struct sdhci_host*)param;
2356 sdhci_card_event(host->mmc);
2358 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2361 static void sdhci_tasklet_finish(unsigned long param)
2363 struct sdhci_host *host;
2364 unsigned long flags;
2365 struct mmc_request *mrq;
2367 host = (struct sdhci_host*)param;
2369 spin_lock_irqsave(&host->lock, flags);
2372 * If this tasklet gets rescheduled while running, it will
2373 * be run again afterwards but without any active request.
2376 spin_unlock_irqrestore(&host->lock, flags);
2380 del_timer(&host->timer);
2385 * The controller needs a reset of internal state machines
2386 * upon error conditions.
2388 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2389 ((mrq->cmd && mrq->cmd->error) ||
2390 (mrq->data && (mrq->data->error ||
2391 (mrq->data->stop && mrq->data->stop->error))) ||
2392 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2394 /* Some controllers need this kick or reset won't work here */
2395 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2396 /* This is to force an update */
2397 sdhci_update_clock(host);
2399 /* Spec says we should do both at the same time, but Ricoh
2400 controllers do not like that. */
2401 sdhci_reset(host, SDHCI_RESET_CMD);
2402 sdhci_reset(host, SDHCI_RESET_DATA);
2409 #ifndef SDHCI_USE_LEDS_CLASS
2410 sdhci_deactivate_led(host);
2414 spin_unlock_irqrestore(&host->lock, flags);
2416 mmc_request_done(host->mmc, mrq);
2417 sdhci_runtime_pm_put(host);
2420 static void sdhci_timeout_timer(unsigned long data)
2422 struct sdhci_host *host;
2423 unsigned long flags;
2425 host = (struct sdhci_host*)data;
2427 spin_lock_irqsave(&host->lock, flags);
2430 pr_err("%s: Timeout waiting for hardware "
2431 "interrupt.\n", mmc_hostname(host->mmc));
2432 sdhci_dumpregs(host);
2435 host->data->error = -ETIMEDOUT;
2436 sdhci_finish_data(host);
2439 host->cmd->error = -ETIMEDOUT;
2441 host->mrq->cmd->error = -ETIMEDOUT;
2443 tasklet_schedule(&host->finish_tasklet);
2448 spin_unlock_irqrestore(&host->lock, flags);
2451 static void sdhci_tuning_timer(unsigned long data)
2453 struct sdhci_host *host;
2454 unsigned long flags;
2456 host = (struct sdhci_host *)data;
2458 spin_lock_irqsave(&host->lock, flags);
2460 host->flags |= SDHCI_NEEDS_RETUNING;
2462 spin_unlock_irqrestore(&host->lock, flags);
2465 /*****************************************************************************\
2467 * Interrupt handling *
2469 \*****************************************************************************/
2471 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2473 BUG_ON(intmask == 0);
2476 pr_err("%s: Got command interrupt 0x%08x even "
2477 "though no command operation was in progress.\n",
2478 mmc_hostname(host->mmc), (unsigned)intmask);
2479 sdhci_dumpregs(host);
2483 if (intmask & SDHCI_INT_TIMEOUT) {
2484 host->cmd->error = -ETIMEDOUT;
2485 } else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2487 host->cmd->error = -EILSEQ;
2488 pr_err("%s: Command CRC or END bit error, intmask: %x\n",
2489 mmc_hostname(host->mmc), intmask);
2492 if (host->cmd->error) {
2493 tasklet_schedule(&host->finish_tasklet);
2498 * The host can send and interrupt when the busy state has
2499 * ended, allowing us to wait without wasting CPU cycles.
2500 * Unfortunately this is overloaded on the "data complete"
2501 * interrupt, so we need to take some care when handling
2504 * Note: The 1.0 specification is a bit ambiguous about this
2505 * feature so there might be some problems with older
2508 if (host->cmd->flags & MMC_RSP_BUSY) {
2509 if (host->cmd->data)
2510 DBG("Cannot wait for busy signal when also "
2511 "doing a data transfer");
2512 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2515 /* The controller does not support the end-of-busy IRQ,
2516 * fall through and take the SDHCI_INT_RESPONSE */
2519 if (intmask & SDHCI_INT_RESPONSE)
2520 sdhci_finish_command(host);
2523 #ifdef CONFIG_MMC_DEBUG
2524 static void sdhci_show_adma_error(struct sdhci_host *host)
2526 const char *name = mmc_hostname(host->mmc);
2527 u8 *desc = host->adma_desc;
2532 sdhci_dumpregs(host);
2535 dma = (__le32 *)(desc + 4);
2536 len = (__le16 *)(desc + 2);
2539 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2540 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2549 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2552 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2555 BUG_ON(intmask == 0);
2557 /* CMD19, CMD21 generates _only_ Buffer Read Ready interrupt */
2558 if (intmask & SDHCI_INT_DATA_AVAIL) {
2559 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2560 if (command == MMC_SEND_TUNING_BLOCK ||
2561 command == MMC_SEND_TUNING_BLOCK_HS200) {
2562 host->tuning_done = 1;
2563 wake_up(&host->buf_ready_int);
2570 * The "data complete" interrupt is also used to
2571 * indicate that a busy state has ended. See comment
2572 * above in sdhci_cmd_irq().
2574 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2575 if (intmask & SDHCI_INT_DATA_END) {
2576 sdhci_finish_command(host);
2581 pr_err("%s: Got data interrupt 0x%08x even "
2582 "though no data operation was in progress.\n",
2583 mmc_hostname(host->mmc), (unsigned)intmask);
2584 sdhci_dumpregs(host);
2589 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2590 host->data->error = -ETIMEDOUT;
2591 pr_err("%s: Data Timeout error, intmask: %x\n",
2592 mmc_hostname(host->mmc), intmask);
2593 } else if (intmask & SDHCI_INT_DATA_END_BIT) {
2594 host->data->error = -EILSEQ;
2595 pr_err("%s: Data END Bit error, intmask: %x\n",
2596 mmc_hostname(host->mmc), intmask);
2597 } else if ((intmask & SDHCI_INT_DATA_CRC) &&
2598 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2599 != MMC_BUS_TEST_R) {
2600 host->data->error = -EILSEQ;
2601 pr_err("%s: Data CRC error, intmask: %x\n",
2602 mmc_hostname(host->mmc), intmask);
2603 } else if (intmask & SDHCI_INT_ADMA_ERROR) {
2604 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2605 sdhci_show_adma_error(host);
2606 host->data->error = -EIO;
2607 if (host->ops->adma_workaround)
2608 host->ops->adma_workaround(host, intmask);
2611 if (host->data->error)
2612 sdhci_finish_data(host);
2614 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2615 sdhci_transfer_pio(host);
2618 * We currently don't do anything fancy with DMA
2619 * boundaries, but as we can't disable the feature
2620 * we need to at least restart the transfer.
2622 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2623 * should return a valid address to continue from, but as
2624 * some controllers are faulty, don't trust them.
2626 if (intmask & SDHCI_INT_DMA_END) {
2627 u32 dmastart, dmanow;
2628 dmastart = sg_dma_address(host->data->sg);
2629 dmanow = dmastart + host->data->bytes_xfered;
2631 * Force update to the next DMA block boundary.
2634 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2635 SDHCI_DEFAULT_BOUNDARY_SIZE;
2636 host->data->bytes_xfered = dmanow - dmastart;
2637 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2639 mmc_hostname(host->mmc), dmastart,
2640 host->data->bytes_xfered, dmanow);
2641 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2644 if (intmask & SDHCI_INT_DATA_END) {
2647 * Data managed to finish before the
2648 * command completed. Make sure we do
2649 * things in the proper order.
2651 host->data_early = 1;
2653 sdhci_finish_data(host);
2659 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2662 struct sdhci_host *host = dev_id;
2663 u32 intmask, unexpected = 0;
2664 int cardint = 0, max_loops = 16;
2666 spin_lock(&host->lock);
2668 if (host->runtime_suspended) {
2669 spin_unlock(&host->lock);
2670 pr_warning("%s: got irq while runtime suspended\n",
2671 mmc_hostname(host->mmc));
2675 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2677 if (!intmask || intmask == 0xffffffff) {
2683 DBG("*** %s got interrupt: 0x%08x\n",
2684 mmc_hostname(host->mmc), intmask);
2686 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2687 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2691 * There is a observation on i.mx esdhc. INSERT bit will be
2692 * immediately set again when it gets cleared, if a card is
2693 * inserted. We have to mask the irq to prevent interrupt
2694 * storm which will freeze the system. And the REMOVE gets
2695 * the same situation.
2697 * More testing are needed here to ensure it works for other
2700 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2701 SDHCI_INT_CARD_REMOVE);
2702 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2703 SDHCI_INT_CARD_INSERT);
2705 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2706 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2707 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2708 tasklet_schedule(&host->card_tasklet);
2711 if (intmask & SDHCI_INT_CMD_MASK) {
2712 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2714 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2717 if (intmask & SDHCI_INT_DATA_MASK) {
2718 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2720 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2723 if ((intmask & SDHCI_INT_DATA_MASK) || (intmask & SDHCI_INT_CMD_MASK))
2724 if (host->ops->sd_error_stats)
2725 host->ops->sd_error_stats(host, intmask);
2727 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2729 intmask &= ~SDHCI_INT_ERROR;
2731 if (intmask & SDHCI_INT_BUS_POWER) {
2732 pr_err("%s: Card is consuming too much power!\n",
2733 mmc_hostname(host->mmc));
2734 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2737 intmask &= ~SDHCI_INT_BUS_POWER;
2739 if (intmask & SDHCI_INT_CARD_INT)
2742 intmask &= ~SDHCI_INT_CARD_INT;
2745 unexpected |= intmask;
2746 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2749 result = IRQ_HANDLED;
2751 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2752 if (intmask && --max_loops)
2755 spin_unlock(&host->lock);
2758 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2759 mmc_hostname(host->mmc), unexpected);
2760 sdhci_dumpregs(host);
2763 * We have to delay this as it calls back into the driver.
2766 mmc_signal_sdio_irq(host->mmc);
2771 /*****************************************************************************\
2775 \*****************************************************************************/
2778 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2781 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2782 | SDHCI_WAKE_ON_INT;
2784 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2786 /* Avoid fake wake up */
2787 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2788 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2789 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2791 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2793 void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2796 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2797 | SDHCI_WAKE_ON_INT;
2799 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2801 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2803 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
2805 int sdhci_suspend_host(struct sdhci_host *host)
2808 struct mmc_host *mmc = host->mmc;
2810 if (host->ops->platform_suspend)
2811 host->ops->platform_suspend(host);
2813 sdhci_disable_card_detection(host);
2815 /* Disable tuning since we are suspending */
2816 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2817 del_timer_sync(&host->tuning_timer);
2818 host->flags &= ~SDHCI_NEEDS_RETUNING;
2822 * If eMMC cards are put in sleep state, Vccq can be disabled
2823 * but Vcc would still be powered on. In resume, we only restore
2824 * the controller context. So, set MMC_PM_KEEP_POWER flag.
2826 if (mmc_card_can_sleep(mmc) && !(mmc->caps2 & MMC_CAP2_NO_SLEEP_CMD))
2827 mmc->pm_flags = MMC_PM_KEEP_POWER;
2829 ret = mmc_suspend_host(host->mmc);
2831 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2832 host->flags |= SDHCI_NEEDS_RETUNING;
2833 mod_timer(&host->tuning_timer, jiffies +
2834 host->tuning_count * HZ);
2837 sdhci_enable_card_detection(host);
2843 * If host clock is disabled but the register access requires host
2844 * clock, then enable the clock, mask the interrupts and disable
2847 if (host->quirks2 & SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK)
2848 if (!host->clock && host->ops->set_clock)
2849 host->ops->set_clock(host, max(mmc->ios.clock, mmc->f_min));
2851 if (mmc->pm_flags & MMC_PM_KEEP_POWER)
2852 host->card_int_set = sdhci_readl(host, SDHCI_INT_ENABLE) &
2855 /* cancel sdio clk gate work */
2856 cancel_delayed_work_sync(&host->delayed_clk_gate_wrk);
2858 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2859 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2861 if (host->quirks2 & SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK)
2862 if (!host->clock && host->ops->set_clock)
2863 host->ops->set_clock(host, 0);
2866 disable_irq(host->irq);
2868 sdhci_enable_irq_wakeups(host);
2869 enable_irq_wake(host->irq);
2871 if (host->quirks2 & SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK)
2872 if (!host->clock && host->ops->set_clock)
2873 host->ops->set_clock(host, 0);
2879 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2881 int sdhci_resume_host(struct sdhci_host *host)
2884 struct mmc_host *mmc = host->mmc;
2886 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2887 if (host->ops->enable_dma)
2888 host->ops->enable_dma(host);
2891 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2893 enable_irq(host->irq);
2895 sdhci_disable_irq_wakeups(host);
2896 disable_irq_wake(host->irq);
2899 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2900 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2901 /* Card keeps power but host controller does not */
2902 sdhci_init(host, 0);
2905 sdhci_do_set_ios(host, &host->mmc->ios);
2907 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2911 ret = mmc_resume_host(host->mmc);
2912 /* Enable card interrupt as it is overwritten in sdhci_init */
2913 if ((mmc->caps & MMC_CAP_SDIO_IRQ) &&
2914 (mmc->pm_flags & MMC_PM_KEEP_POWER))
2915 if (host->card_int_set)
2916 mmc->ops->enable_sdio_irq(mmc, true);
2918 sdhci_enable_card_detection(host);
2920 if (host->ops->platform_resume)
2921 host->ops->platform_resume(host);
2923 /* Set the re-tuning expiration flag */
2924 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2925 host->flags |= SDHCI_NEEDS_RETUNING;
2930 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2931 #endif /* CONFIG_PM */
2933 #ifdef CONFIG_PM_RUNTIME
2935 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2937 return pm_runtime_get_sync(host->mmc->parent);
2940 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2942 pm_runtime_mark_last_busy(host->mmc->parent);
2943 return pm_runtime_put_autosuspend(host->mmc->parent);
2946 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2948 unsigned long flags;
2951 /* Disable tuning since we are suspending */
2952 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2953 del_timer_sync(&host->tuning_timer);
2954 host->flags &= ~SDHCI_NEEDS_RETUNING;
2957 spin_lock_irqsave(&host->lock, flags);
2958 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2959 spin_unlock_irqrestore(&host->lock, flags);
2961 synchronize_irq(host->irq);
2963 spin_lock_irqsave(&host->lock, flags);
2964 host->runtime_suspended = true;
2965 spin_unlock_irqrestore(&host->lock, flags);
2969 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2971 int sdhci_runtime_resume_host(struct sdhci_host *host)
2973 unsigned long flags;
2974 int ret = 0, host_flags = host->flags;
2976 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2977 if (host->ops->enable_dma)
2978 host->ops->enable_dma(host);
2981 sdhci_init(host, 0);
2983 /* Force clock and power re-program */
2986 sdhci_do_set_ios(host, &host->mmc->ios);
2988 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2989 /* Do any post voltage switch platform specific configuration */
2990 if (host->ops->switch_signal_voltage_exit)
2991 host->ops->switch_signal_voltage_exit(host);
2992 if ((host_flags & SDHCI_PV_ENABLED) &&
2993 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2994 spin_lock_irqsave(&host->lock, flags);
2995 sdhci_enable_preset_value(host, true);
2996 spin_unlock_irqrestore(&host->lock, flags);
2999 /* Set the re-tuning expiration flag */
3000 if (host->flags & SDHCI_USING_RETUNING_TIMER)
3001 host->flags |= SDHCI_NEEDS_RETUNING;
3003 spin_lock_irqsave(&host->lock, flags);
3005 host->runtime_suspended = false;
3007 /* Enable SDIO IRQ */
3008 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
3009 sdhci_enable_sdio_irq_nolock(host, true);
3011 /* Enable Card Detection */
3012 sdhci_enable_card_detection(host);
3014 spin_unlock_irqrestore(&host->lock, flags);
3018 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3022 /*****************************************************************************\
3024 * Device allocation/registration *
3026 \*****************************************************************************/
3028 struct sdhci_host *sdhci_alloc_host(struct device *dev,
3031 struct mmc_host *mmc;
3032 struct sdhci_host *host;
3034 WARN_ON(dev == NULL);
3036 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3038 return ERR_PTR(-ENOMEM);
3040 host = mmc_priv(mmc);
3046 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3048 int sdhci_add_host(struct sdhci_host *host)
3050 struct mmc_host *mmc;
3051 u32 caps[2] = {0, 0};
3052 u32 max_current_caps;
3053 unsigned int ocr_avail;
3055 struct edp_manager *battery_manager = NULL;
3056 struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
3059 WARN_ON(host == NULL);
3066 host->quirks = debug_quirks;
3068 host->quirks2 = debug_quirks2;
3070 sdhci_reset(host, SDHCI_RESET_ALL);
3072 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
3073 host->version = (host->version & SDHCI_SPEC_VER_MASK)
3074 >> SDHCI_SPEC_VER_SHIFT;
3075 if (host->version > SDHCI_SPEC_400) {
3076 pr_err("%s: Unknown controller version (%d). "
3077 "You may experience problems.\n", mmc_hostname(mmc),
3081 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
3082 sdhci_readl(host, SDHCI_CAPABILITIES);
3084 if (host->version >= SDHCI_SPEC_300)
3085 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
3087 sdhci_readl(host, SDHCI_CAPABILITIES_1);
3089 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3090 host->flags |= SDHCI_USE_SDMA;
3091 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
3092 DBG("Controller doesn't have SDMA capability\n");
3094 host->flags |= SDHCI_USE_SDMA;
3096 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3097 (host->flags & SDHCI_USE_SDMA)) {
3098 DBG("Disabling DMA as it is marked broken\n");
3099 host->flags &= ~SDHCI_USE_SDMA;
3102 if ((host->version >= SDHCI_SPEC_200) &&
3103 (caps[0] & SDHCI_CAN_DO_ADMA2))
3104 host->flags |= SDHCI_USE_ADMA;
3106 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3107 (host->flags & SDHCI_USE_ADMA)) {
3108 DBG("Disabling ADMA as it is marked broken\n");
3109 host->flags &= ~SDHCI_USE_ADMA;
3112 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3113 if (host->ops->enable_dma) {
3114 if (host->ops->enable_dma(host)) {
3115 pr_warning("%s: No suitable DMA "
3116 "available. Falling back to PIO.\n",
3119 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3124 if (host->flags & SDHCI_USE_ADMA) {
3126 * We need to allocate descriptors for all sg entries
3127 * (128) and potentially one alignment transfer for
3128 * each of those entries.
3130 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
3131 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
3132 if (!host->adma_desc || !host->align_buffer) {
3133 kfree(host->adma_desc);
3134 kfree(host->align_buffer);
3135 pr_warning("%s: Unable to allocate ADMA "
3136 "buffers. Falling back to standard DMA.\n",
3138 host->flags &= ~SDHCI_USE_ADMA;
3143 * If we use DMA, then it's up to the caller to set the DMA
3144 * mask, but PIO does not need the hw shim so we set a new
3145 * mask here in that case.
3147 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3148 host->dma_mask = DMA_BIT_MASK(64);
3149 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
3152 if (host->version >= SDHCI_SPEC_300)
3153 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3154 >> SDHCI_CLOCK_BASE_SHIFT;
3156 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3157 >> SDHCI_CLOCK_BASE_SHIFT;
3159 host->max_clk *= 1000000;
3160 if (host->max_clk == 0 || host->quirks &
3161 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3162 if (!host->ops->get_max_clock) {
3163 pr_err("%s: Hardware doesn't specify base clock "
3164 "frequency.\n", mmc_hostname(mmc));
3167 host->max_clk = host->ops->get_max_clock(host);
3171 * In case of Host Controller v3.00, find out whether clock
3172 * multiplier is supported.
3174 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3175 SDHCI_CLOCK_MUL_SHIFT;
3178 * In case the value in Clock Multiplier is 0, then programmable
3179 * clock mode is not supported, otherwise the actual clock
3180 * multiplier is one more than the value of Clock Multiplier
3181 * in the Capabilities Register.
3187 * Set host parameters.
3189 mmc->ops = &sdhci_ops;
3190 mmc->f_max = host->max_clk;
3191 if (host->ops->get_min_clock)
3192 mmc->f_min = host->ops->get_min_clock(host);
3193 else if (host->version >= SDHCI_SPEC_300) {
3194 if (host->clk_mul) {
3195 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3196 mmc->f_max = host->max_clk * host->clk_mul;
3198 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3200 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3203 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
3204 if (host->timeout_clk == 0) {
3205 if (host->ops->get_timeout_clock) {
3206 host->timeout_clk = host->ops->get_timeout_clock(host);
3207 } else if (!(host->quirks &
3208 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3209 pr_err("%s: Hardware doesn't specify timeout clock "
3210 "frequency.\n", mmc_hostname(mmc));
3214 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3215 host->timeout_clk *= 1000;
3217 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
3218 host->timeout_clk = mmc->f_max / 1000;
3220 if (!(host->quirks2 & SDHCI_QUIRK2_NO_CALC_MAX_DISCARD_TO))
3221 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
3223 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3224 host->flags |= SDHCI_AUTO_CMD12;
3226 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3227 if ((host->version >= SDHCI_SPEC_300) &&
3228 ((host->flags & SDHCI_USE_ADMA) ||
3229 !(host->flags & SDHCI_USE_SDMA))) {
3230 host->flags |= SDHCI_AUTO_CMD23;
3231 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3233 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3236 if (host->version >= SDHCI_SPEC_400) {
3237 ctrl = sdhci_readl(host, SDHCI_ACMD12_ERR);
3238 ctrl |= SDHCI_HOST_VERSION_4_EN;
3239 if (host->quirks2 & SDHCI_QUIRK2_SUPPORT_64BIT_DMA)
3240 ctrl |= SDHCI_ADDRESSING_64BIT_EN;
3241 sdhci_writel(host, ctrl, SDHCI_ACMD12_ERR);
3245 * A controller may support 8-bit width, but the board itself
3246 * might not have the pins brought out. Boards that support
3247 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3248 * their platform code before calling sdhci_add_host(), and we
3249 * won't assume 8-bit width for hosts without that CAP.
3251 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3252 mmc->caps |= MMC_CAP_4_BIT_DATA;
3254 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3255 mmc->caps &= ~MMC_CAP_CMD23;
3257 if (caps[0] & SDHCI_CAN_DO_HISPD)
3258 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3260 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3261 !(host->mmc->caps & MMC_CAP_NONREMOVABLE) && !(host->ops->get_cd))
3262 mmc->caps |= MMC_CAP_NEEDS_POLL;
3264 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3265 host->vqmmc = regulator_get(mmc_dev(mmc), "vqmmc");
3266 if (IS_ERR_OR_NULL(host->vqmmc)) {
3267 if (PTR_ERR(host->vqmmc) < 0) {
3268 pr_info("%s: no vqmmc regulator found\n",
3273 ret = regulator_enable(host->vqmmc);
3274 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
3276 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3277 SDHCI_SUPPORT_SDR50 |
3278 SDHCI_SUPPORT_DDR50);
3280 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3281 mmc_hostname(mmc), ret);
3286 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3287 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3288 SDHCI_SUPPORT_DDR50);
3290 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3291 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3292 SDHCI_SUPPORT_DDR50))
3293 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3295 /* SDR104 supports also implies SDR50 support */
3296 if (caps[1] & SDHCI_SUPPORT_SDR104)
3297 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3298 else if (caps[1] & SDHCI_SUPPORT_SDR50)
3299 mmc->caps |= MMC_CAP_UHS_SDR50;
3301 if (caps[1] & SDHCI_SUPPORT_DDR50)
3302 mmc->caps |= MMC_CAP_UHS_DDR50;
3304 /* Does the host need tuning for SDR50? */
3305 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3306 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3308 /* Does the host need tuning for HS200? */
3309 if (mmc->caps2 & MMC_CAP2_HS200)
3310 host->flags |= SDHCI_HS200_NEEDS_TUNING;
3312 /* Driver Type(s) (A, C, D) supported by the host */
3313 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3314 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3315 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3316 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3317 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3318 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3320 /* Initial value for re-tuning timer count */
3321 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3322 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3324 * If the re-tuning timer count value is 0xF, the timer count
3325 * information should be obtained in a non-standard way.
3327 if (host->tuning_count == 0xF) {
3328 if (host->ops->get_tuning_counter) {
3329 host->tuning_count =
3330 host->ops->get_tuning_counter(host);
3332 host->tuning_count = 0;
3337 * In case Re-tuning Timer is not disabled, the actual value of
3338 * re-tuning timer will be 2 ^ (n - 1).
3340 if (host->tuning_count)
3341 host->tuning_count = 1 << (host->tuning_count - 1);
3343 /* Re-tuning mode supported by the Host Controller */
3344 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3345 SDHCI_RETUNING_MODE_SHIFT;
3349 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
3350 if (IS_ERR_OR_NULL(host->vmmc)) {
3351 if (PTR_ERR(host->vmmc) < 0) {
3352 pr_info("%s: no vmmc regulator found\n",
3358 #ifdef CONFIG_REGULATOR
3360 * Voltage range check makes sense only if regulator reports
3361 * any voltage value.
3363 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
3364 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3366 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3367 caps[0] &= ~SDHCI_CAN_VDD_330;
3368 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3369 caps[0] &= ~SDHCI_CAN_VDD_300;
3370 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3372 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3373 caps[0] &= ~SDHCI_CAN_VDD_180;
3375 #endif /* CONFIG_REGULATOR */
3378 * According to SD Host Controller spec v3.00, if the Host System
3379 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3380 * the value is meaningful only if Voltage Support in the Capabilities
3381 * register is set. The actual current value is 4 times the register
3384 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3385 if (!max_current_caps && host->vmmc) {
3386 u32 curr = regulator_get_current_limit(host->vmmc);
3389 /* convert to SDHCI_MAX_CURRENT format */
3390 curr = curr/1000; /* convert to mA */
3391 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3393 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3395 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3396 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3397 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3401 if (caps[0] & SDHCI_CAN_VDD_330) {
3402 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3404 mmc->max_current_330 = ((max_current_caps &
3405 SDHCI_MAX_CURRENT_330_MASK) >>
3406 SDHCI_MAX_CURRENT_330_SHIFT) *
3407 SDHCI_MAX_CURRENT_MULTIPLIER;
3409 if (caps[0] & SDHCI_CAN_VDD_300) {
3410 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3412 mmc->max_current_300 = ((max_current_caps &
3413 SDHCI_MAX_CURRENT_300_MASK) >>
3414 SDHCI_MAX_CURRENT_300_SHIFT) *
3415 SDHCI_MAX_CURRENT_MULTIPLIER;
3417 if (caps[0] & SDHCI_CAN_VDD_180) {
3418 ocr_avail |= MMC_VDD_165_195;
3420 mmc->max_current_180 = ((max_current_caps &
3421 SDHCI_MAX_CURRENT_180_MASK) >>
3422 SDHCI_MAX_CURRENT_180_SHIFT) *
3423 SDHCI_MAX_CURRENT_MULTIPLIER;
3426 mmc->ocr_avail = ocr_avail;
3427 mmc->ocr_avail_sdio = ocr_avail;
3428 if (host->ocr_avail_sdio)
3429 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3430 mmc->ocr_avail_sd = ocr_avail;
3431 if (host->ocr_avail_sd)
3432 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3433 else /* normal SD controllers don't support 1.8V */
3434 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3435 mmc->ocr_avail_mmc = ocr_avail;
3436 if (host->ocr_avail_mmc)
3437 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3439 if (mmc->ocr_avail == 0) {
3440 pr_err("%s: Hardware doesn't report any "
3441 "support voltages.\n", mmc_hostname(mmc));
3445 spin_lock_init(&host->lock);
3448 * Maximum number of segments. Depends on if the hardware
3449 * can do scatter/gather or not.
3451 if (host->flags & SDHCI_USE_ADMA)
3452 mmc->max_segs = 128;
3453 else if (host->flags & SDHCI_USE_SDMA)
3456 mmc->max_segs = 128;
3459 * Maximum number of sectors in one transfer. Limited by DMA boundary
3462 mmc->max_req_size = 524288;
3465 * Maximum segment size. Could be one segment with the maximum number
3466 * of bytes. When doing hardware scatter/gather, each entry cannot
3467 * be larger than 64 KiB though.
3469 if (host->flags & SDHCI_USE_ADMA) {
3470 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3471 mmc->max_seg_size = 65535;
3473 mmc->max_seg_size = 65536;
3475 mmc->max_seg_size = mmc->max_req_size;
3479 * Maximum block size. This varies from controller to controller and
3480 * is specified in the capabilities register.
3482 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3483 mmc->max_blk_size = 2;
3485 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3486 SDHCI_MAX_BLOCK_SHIFT;
3487 if (mmc->max_blk_size >= 3) {
3488 pr_info("%s: Invalid maximum block size, "
3489 "assuming 512 bytes\n", mmc_hostname(mmc));
3490 mmc->max_blk_size = 0;
3494 mmc->max_blk_size = 512 << mmc->max_blk_size;
3497 * Maximum block count.
3499 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3504 tasklet_init(&host->card_tasklet,
3505 sdhci_tasklet_card, (unsigned long)host);
3506 tasklet_init(&host->finish_tasklet,
3507 sdhci_tasklet_finish, (unsigned long)host);
3509 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3511 if (host->version >= SDHCI_SPEC_300) {
3512 init_waitqueue_head(&host->buf_ready_int);
3514 /* Initialize re-tuning timer */
3515 init_timer(&host->tuning_timer);
3516 host->tuning_timer.data = (unsigned long)host;
3517 host->tuning_timer.function = sdhci_tuning_timer;
3520 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3521 mmc_hostname(mmc), host);
3523 pr_err("%s: Failed to request IRQ %d: %d\n",
3524 mmc_hostname(mmc), host->irq, ret);
3528 sdhci_init(host, 0);
3530 host->sysedpc = sysedp_create_consumer(dev_name(mmc_dev(mmc)),
3531 dev_name(mmc_dev(mmc)));
3533 if (host->edp_support == true) {
3534 battery_manager = edp_get_manager("battery");
3535 if (!battery_manager)
3536 dev_err(&pdev->dev, "unable to get edp manager\n");
3538 host->sd_edp_client = devm_kzalloc(&pdev->dev,
3539 sizeof(struct edp_client), GFP_KERNEL);
3540 if (IS_ERR_OR_NULL(host->sd_edp_client)) {
3542 "could not allocate edp client\n");
3543 host->sd_edp_client = NULL;
3546 strncpy(host->sd_edp_client->name,
3547 dev_name(mmc_dev(mmc)), EDP_NAME_LEN-1);
3548 host->sd_edp_client->name[EDP_NAME_LEN-1] = '\0';
3549 host->sd_edp_client->states = host->edp_states;
3550 host->sd_edp_client->num_states = SD_EDP_NUM_STATES;
3551 host->sd_edp_client->e0_index = SD_EDP_HIGH;
3552 host->sd_edp_client->priority = EDP_MAX_PRIO + 2;
3554 ret = edp_register_client(battery_manager,
3555 host->sd_edp_client);
3558 "unable to register edp client\n");
3560 pr_info("%s: edp client registration" \
3562 dev_name(mmc_dev(mmc)));
3563 ret = edp_update_client_request(
3564 host->sd_edp_client,
3568 "Unable to set E0 EDP state\n");
3569 edp_unregister_client(
3570 host->sd_edp_client);
3571 devm_kfree(&pdev->dev,
3572 host->sd_edp_client);
3578 #ifdef CONFIG_MMC_DEBUG
3579 sdhci_dumpregs(host);
3582 #ifdef SDHCI_USE_LEDS_CLASS
3583 snprintf(host->led_name, sizeof(host->led_name),
3584 "%s::", mmc_hostname(mmc));
3585 host->led.name = host->led_name;
3586 host->led.brightness = LED_OFF;
3587 host->led.default_trigger = mmc_hostname(mmc);
3588 host->led.brightness_set = sdhci_led_control;
3590 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3592 pr_err("%s: Failed to register LED device: %d\n",
3593 mmc_hostname(mmc), ret);
3602 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3603 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3604 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3605 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3607 sdhci_enable_card_detection(host);
3611 #ifdef SDHCI_USE_LEDS_CLASS
3613 sdhci_reset(host, SDHCI_RESET_ALL);
3614 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3615 free_irq(host->irq, host);
3618 tasklet_kill(&host->card_tasklet);
3619 tasklet_kill(&host->finish_tasklet);
3624 EXPORT_SYMBOL_GPL(sdhci_add_host);
3626 void sdhci_remove_host(struct sdhci_host *host, int dead)
3628 unsigned long flags;
3631 spin_lock_irqsave(&host->lock, flags);
3633 host->flags |= SDHCI_DEVICE_DEAD;
3636 pr_err("%s: Controller removed during "
3637 " transfer!\n", mmc_hostname(host->mmc));
3639 host->mrq->cmd->error = -ENOMEDIUM;
3640 tasklet_schedule(&host->finish_tasklet);
3643 spin_unlock_irqrestore(&host->lock, flags);
3646 sdhci_disable_card_detection(host);
3648 mmc_remove_host(host->mmc);
3650 #ifdef SDHCI_USE_LEDS_CLASS
3651 led_classdev_unregister(&host->led);
3655 sdhci_reset(host, SDHCI_RESET_ALL);
3657 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3658 free_irq(host->irq, host);
3660 del_timer_sync(&host->timer);
3662 tasklet_kill(&host->card_tasklet);
3663 tasklet_kill(&host->finish_tasklet);
3666 regulator_disable(host->vmmc);
3667 regulator_put(host->vmmc);
3671 regulator_disable(host->vqmmc);
3672 regulator_put(host->vqmmc);
3675 kfree(host->adma_desc);
3676 kfree(host->align_buffer);
3678 host->adma_desc = NULL;
3679 host->align_buffer = NULL;
3681 sysedp_free_consumer(host->sysedpc);
3682 host->sysedpc = NULL;
3685 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3687 void sdhci_free_host(struct sdhci_host *host)
3689 mmc_free_host(host->mmc);
3692 EXPORT_SYMBOL_GPL(sdhci_free_host);
3694 /*****************************************************************************\
3696 * Driver init/exit *
3698 \*****************************************************************************/
3700 static int __init sdhci_drv_init(void)
3703 ": Secure Digital Host Controller Interface driver\n");
3704 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3709 static void __exit sdhci_drv_exit(void)
3713 module_init(sdhci_drv_init);
3714 module_exit(sdhci_drv_exit);
3716 module_param(debug_quirks, uint, 0444);
3717 module_param(debug_quirks2, uint, 0444);
3719 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3720 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3721 MODULE_LICENSE("GPL");
3723 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3724 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");